From a59177004eedccaa26f7311ba5e7413acdf2e750 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sun, 20 Aug 2023 07:10:11 -0400 Subject: [PATCH] MAX, MachXO, MachXO2 working --- CPLD/LCMXO2-640HC/.run_manager.ini | 18 +- CPLD/LCMXO2-640HC/.setting.ini | 7 +- CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf | 3 + CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf | 2 - CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html | 136 + .../LCMXO2_640HC_tcr.dir/pn230819062748.tcr | 7 + .../LCMXO2_640HC_tcr.dir/pn230819062826.tcr | 5 + .../LCMXO2_640HC_tcr.dir/pn230819062853.tcr | 6 + .../LCMXO2_640HC_tcr.dir/pn230819062900.tcr | 5 + .../LCMXO2_640HC_tcr.dir/pn230819063021.tcr | 4 + .../LCMXO2_640HC_tcr.dir/pn230819205234.tcr | 47 + .../LCMXO2_640HC_tcr.dir/pn230820055534.tcr | 6 + .../LCMXO2_640HC_tcr.dir/pn230820055626.tcr | 4 + CPLD/LCMXO2-640HC/REFB.edn | 10 +- CPLD/LCMXO2-640HC/REFB.ipx | 8 +- CPLD/LCMXO2-640HC/REFB.lpc | 282 +- CPLD/LCMXO2-640HC/REFB.naf | 62 +- CPLD/LCMXO2-640HC/REFB.sort | 2 +- CPLD/LCMXO2-640HC/REFB.srp | 4 +- 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CPLD/MAXV/output_files/RAM2GS.fit.smsg | 8 +- CPLD/MAXV/output_files/RAM2GS.fit.summary | 22 +- CPLD/MAXV/output_files/RAM2GS.flow.rpt | 236 +- CPLD/MAXV/output_files/RAM2GS.jdi | 16 +- CPLD/MAXV/output_files/RAM2GS.map.rpt | 624 +- CPLD/MAXV/output_files/RAM2GS.map.smsg | 6 +- CPLD/MAXV/output_files/RAM2GS.map.summary | 18 +- CPLD/MAXV/output_files/RAM2GS.pin | 330 +- CPLD/MAXV/output_files/RAM2GS.sld | 2 +- CPLD/MAXV/output_files/RAM2GS.sta.rpt | 2021 +- CPLD/MAXV/output_files/RAM2GS.sta.summary | 138 +- CPLD/RAM2GS-AGM.v | 10 +- CPLD/RAM2GS-LCMXO2.mem | 7 + CPLD/RAM2GS-LCMXO2.v | 349 +- 545 files changed, 317413 insertions(+), 205635 deletions(-) delete mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr create mode 100644 CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr create mode 100644 CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bit create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mt create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.twr create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_fpga_mapper.htm create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_iotiming.html create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvho.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvho.vho create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.vo create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_premap.htm create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_tw1.html create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_twr.html create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.vho create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.vo create mode 100644 CPLD/LCMXO2-640HC/impl1/impl1.xcf create mode 100644 CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1.ior create mode 100644 CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd create mode 100644 CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm create mode 100644 CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_toc.htm create mode 100644 CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_srr.htm create mode 100644 CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_toc.htm delete mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819063022.tcr create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819205700.tcr create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230820055550.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063021.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063032.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819215438.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055538.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055558.tcr delete mode 100644 CPLD/MAXII/RAM2GS.qws create mode 100644 CPLD/MAXII/db/RAM2GS-MAXII.quiproj.11208.rdr.flock delete mode 100644 CPLD/MAXV/RAM2GS.qws create mode 100644 CPLD/MAXV/db/RAM2GS-MAXV.quiproj.13204.rdr.flock create mode 100644 CPLD/MAXV/db/RAM2GS.tmw_info create mode 100644 CPLD/RAM2GS-LCMXO2.mem diff --git a/CPLD/LCMXO2-640HC/.run_manager.ini b/CPLD/LCMXO2-640HC/.run_manager.ini index 8c0aa7b..b5da7d8 100644 --- a/CPLD/LCMXO2-640HC/.run_manager.ini +++ b/CPLD/LCMXO2-640HC/.run_manager.ini @@ -1,9 +1,9 @@ -[Runmanager] -Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) -windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) -headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) - -[impl1%3CStrategy1%3E] -isChecked=false -isHidden=false -isExpanded=false +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini index 1546db3..2436406 100644 --- a/CPLD/LCMXO2-640HC/.setting.ini +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -1,3 +1,4 @@ -[General] -Export.auto_tasks=Jedecgen -PAR.auto_tasks=@@empty() +[General] +Export.auto_tasks=IBIS, TimingSimFileVlg, TimingSimFileVHD, Bitgen, Jedecgen +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf index 4204338..b28ecd3 100644 --- a/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf @@ -9,6 +9,9 @@ + + + diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf deleted file mode 100644 index 325063a..0000000 --- a/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf +++ /dev/null @@ -1,2 +0,0 @@ -BLOCK RESETPATHS; -BLOCK ASYNCPATHS; diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html index ff52e3e..0c0ecef 100644 --- a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html @@ -17,6 +17,142 @@ prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf +pn230816210353 +#Start recording tcl command: 8/16/2023 20:34:55 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Synthesis -impl impl1 +prj_run Map -impl impl1 +prj_run Export -impl impl1 +prj_run PAR -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc" +prj_run Export -impl impl1 +#Stop recording: 8/16/2023 21:03:53 + + + +pn230819062748 +#Start recording tcl command: 8/18/2023 08:16:23 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Synthesis -impl impl1 +#Stop recording: 8/19/2023 06:27:48 + + + +pn230819062826 +#Start recording tcl command: 8/19/2023 06:27:54 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Synthesis -impl impl1 -task Synplify_Synthesis +#Stop recording: 8/19/2023 06:28:26 + + + +pn230819062853 +#Start recording tcl command: 8/19/2023 06:28:30 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Synthesis -impl impl1 +prj_project close +#Stop recording: 8/19/2023 06:28:53 + + + +pn230819062900 +#Start recording tcl command: 8/19/2023 06:28:53 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_project close +#Stop recording: 8/19/2023 06:29:00 + + + +pn230819063021 +#Start recording tcl command: 8/19/2023 06:29:00 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +#Stop recording: 8/19/2023 06:30:21 + + + +pn230819205234 +#Start recording tcl command: 8/19/2023 06:30:42 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +pgr_program run +pgr_program set -cable USB2 +pgr_program set -port FTUSB-0 +pgr_program run +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +pgr_project close +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_project save +prj_project close +#Stop recording: 8/19/2023 20:52:34 + + + +pn230820055534 +#Start recording tcl command: 8/19/2023 21:54:38 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 -forceAll +prj_project close +#Stop recording: 8/20/2023 05:55:34 + + +


diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr new file mode 100644 index 0000000..d35b931 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr @@ -0,0 +1,7 @@ +#Start recording tcl command: 8/18/2023 08:16:23 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Synthesis -impl impl1 +#Stop recording: 8/19/2023 06:27:48 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr new file mode 100644 index 0000000..53eedad --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/19/2023 06:27:54 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Synthesis -impl impl1 -task Synplify_Synthesis +#Stop recording: 8/19/2023 06:28:26 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr new file mode 100644 index 0000000..b189ad6 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr @@ -0,0 +1,6 @@ +#Start recording tcl command: 8/19/2023 06:28:30 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Synthesis -impl impl1 +prj_project close +#Stop recording: 8/19/2023 06:28:53 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr new file mode 100644 index 0000000..98a45a7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/19/2023 06:28:53 +#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_project close +#Stop recording: 8/19/2023 06:29:00 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr new file mode 100644 index 0000000..e25c9f4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/19/2023 06:29:00 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +#Stop recording: 8/19/2023 06:30:21 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr new file mode 100644 index 0000000..0577625 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr @@ -0,0 +1,47 @@ +#Start recording tcl command: 8/19/2023 06:30:42 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +pgr_program run +pgr_program set -cable USB2 +pgr_program set -port FTUSB-0 +pgr_program run +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +pgr_project close +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_run Export -impl impl1 -forceOne +prj_project save +prj_project close +#Stop recording: 8/19/2023 20:52:34 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr new file mode 100644 index 0000000..b33a59d --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr @@ -0,0 +1,6 @@ +#Start recording tcl command: 8/19/2023 21:54:38 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +prj_run Export -impl impl1 -forceAll +prj_project close +#Stop recording: 8/20/2023 05:55:34 diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr new file mode 100644 index 0000000..e7f1318 --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/20/2023 05:55:58 +#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC +prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf" +#Stop recording: 8/20/2023 05:56:26 diff --git a/CPLD/LCMXO2-640HC/REFB.edn b/CPLD/LCMXO2-640HC/REFB.edn index 59d4276..6075b51 100644 --- a/CPLD/LCMXO2-640HC/REFB.edn +++ b/CPLD/LCMXO2-640HC/REFB.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2023 8 16 20 52 2) + (timestamp 2023 8 19 7 25 4) (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) - (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ") + (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 ") (library ORCLIB (edifLevel 0) (technology @@ -287,9 +287,9 @@ (property UFM_INIT_FILE_FORMAT (string "HEX")) (property UFM_INIT_FILE_NAME - (string "NONE")) + (string "../RAM2GS-LCMXO2.mem")) (property UFM_INIT_ALL_ZEROS - (string "ENABLED")) + (string "DISABLED")) (property UFM_INIT_START_PAGE (string "190")) (property UFM_INIT_PAGES @@ -383,7 +383,7 @@ (property EFB_I2C1 (string "DISABLED")) (property EFB_WB_CLK_FREQ - (string "62.5"))) + (string "66.7"))) (net scuba_vhi (joined (portRef Z (instanceRef scuba_vhi_inst)) diff --git a/CPLD/LCMXO2-640HC/REFB.ipx b/CPLD/LCMXO2-640HC/REFB.ipx index 4d397ec..bbea108 100644 --- a/CPLD/LCMXO2-640HC/REFB.ipx +++ b/CPLD/LCMXO2-640HC/REFB.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/CPLD/LCMXO2-640HC/REFB.lpc b/CPLD/LCMXO2-640HC/REFB.lpc index 7e8558b..b811267 100644 --- a/CPLD/LCMXO2-640HC/REFB.lpc +++ b/CPLD/LCMXO2-640HC/REFB.lpc @@ -1,141 +1,141 @@ -[Device] -Family=machxo2 -PartType=LCMXO2-640HC -PartName=LCMXO2-640HC-4TG100C -SpeedGrade=4 -Package=TQFP100 -OperatingCondition=COM -Status=S - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=EFB -CoreRevision=1.2 -ModuleName=REFB -SourceFormat=Verilog HDL -ParameterFileVersion=1.0 -Date=08/16/2023 -Time=20:52:02 - -[Parameters] -Verilog=1 -VHDL=0 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -freq= -i2c1=0 -i2c1config=0 -i2c1_addr=7-Bit Addressing -i2c1_ce=0 -i2c1_freq=100 -i2c1_sa=10000 -i2c1_we=0 -i2c2=0 -i2c2_addr=7-Bit Addressing -i2c2_ce=0 -i2c2_freq=100 -i2c2_sa=10000 -i2c2_we=0 -ufm_addr=7-Bit Addressing -ufm_sa=10000 -pll=0 -pll_cnt=1 -spi=0 -spi_clkinv=0 -spi_cs=1 -spi_en=0 -spi_freq=1 -spi_lsb=0 -spi_mode=Slave -spi_ib=0 -spi_ph=0 -spi_hs=0 -spi_rxo=0 -spi_rxr=0 -spi_txo=0 -spi_txr=0 -spi_we=0 -static_tc=Static -tc=0 -tc_clkinv=Positive -tc_ctr=1 -tc_div=1 -tc_ipcap=0 -tc_mode=CTCM -tc_ocr=32767 -tc_oflow=1 -tc_o=TOGGLE -tc_opcomp=0 -tc_osc=0 -tc_sa_oflow=0 -tc_top=65535 -ufm=1 -ufm0=0 -ufm1=0 -ufm2=0 -ufm3=0 -ufm_cfg0=0 -ufm_cfg1=0 -wb_clk_freq=62.5 -ufm_usage=SHARED_EBR_TAG -ufm_ebr=190 -ufm_remain= -mem_size=1 -ufm_start= -ufm_init=0 -memfile= -ufm_dt=hex -ufm0_ebr= -mem_size0=1 -ufm0_init=0 -memfile0= -ufm0_dt=hex -ufm1_ebr= -mem_size1=1 -ufm1_init=0 -memfile1= -ufm1_dt=hex -ufm2_ebr= -mem_size2=1 -ufm2_init=0 -memfile2= -ufm2_dt=hex -ufm3_ebr= -mem_size3=1 -ufm3_init=0 -memfile3= -ufm3_dt=hex -ufm_cfg0_ebr= -mem_size_cfg0=1 -ufm_cfg0_init=0 -memfile_cfg0= -ufm_cfg0_dt=hex -ufm_cfg1_ebr= -mem_size_cfg1=1 -ufm_cfg1_init=0 -memfile_cfg1= -ufm_cfg1_dt=hex -wb=1 -boot_option=Internal -efb_ufm=0 -boot_option_internal=Single Boot -internal_ufm0=0 -internal_ufm1=0 -efb_ufm_boot= -tamperdr=0 -t_pwd=0 -t_lockflash=0 -t_manmode=0 -t_jtagport=0 -t_sspiport=0 -t_sic2port=0 -t_wbport=0 -t_portlock=0 - -[Command] -cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 +[Device] +Family=machxo2 +PartType=LCMXO2-640HC +PartName=LCMXO2-640HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=REFB +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=08/19/2023 +Time=07:25:04 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +ufm0=0 +ufm1=0 +ufm2=0 +ufm3=0 +ufm_cfg0=0 +ufm_cfg1=0 +wb_clk_freq=66.7 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=190 +ufm_remain= +mem_size=1 +ufm_start= +ufm_init=mem +memfile=../RAM2GS-LCMXO2.mem +ufm_dt=hex +ufm0_ebr= +mem_size0=1 +ufm0_init=0 +memfile0= +ufm0_dt=hex +ufm1_ebr= +mem_size1=1 +ufm1_init=0 +memfile1= +ufm1_dt=hex +ufm2_ebr= +mem_size2=1 +ufm2_init=0 +memfile2= +ufm2_dt=hex +ufm3_ebr= +mem_size3=1 +ufm3_init=0 +memfile3= +ufm3_dt=hex +ufm_cfg0_ebr= +mem_size_cfg0=1 +ufm_cfg0_init=0 +memfile_cfg0= +ufm_cfg0_dt=hex +ufm_cfg1_ebr= +mem_size_cfg1=1 +ufm_cfg1_init=0 +memfile_cfg1= +ufm_cfg1_dt=hex +wb=1 +boot_option=Internal +efb_ufm=0 +boot_option_internal=Single Boot +internal_ufm0=0 +internal_ufm1=0 +efb_ufm_boot= +tamperdr=0 +t_pwd=0 +t_lockflash=0 +t_manmode=0 +t_jtagport=0 +t_sspiport=0 +t_sic2port=0 +t_wbport=0 +t_portlock=0 + +[Command] +cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 diff --git a/CPLD/LCMXO2-640HC/REFB.naf b/CPLD/LCMXO2-640HC/REFB.naf index bf6d243..5c239f5 100644 --- a/CPLD/LCMXO2-640HC/REFB.naf +++ b/CPLD/LCMXO2-640HC/REFB.naf @@ -1,31 +1,31 @@ -wb_clk_i i -wb_rst_i i -wb_cyc_i i -wb_stb_i i -wb_we_i i -wb_adr_i[7] i -wb_adr_i[6] i -wb_adr_i[5] i -wb_adr_i[4] i -wb_adr_i[3] i -wb_adr_i[2] i -wb_adr_i[1] i -wb_adr_i[0] i -wb_dat_i[7] i -wb_dat_i[6] i -wb_dat_i[5] i -wb_dat_i[4] i -wb_dat_i[3] i -wb_dat_i[2] i -wb_dat_i[1] i -wb_dat_i[0] i -wb_dat_o[7] o -wb_dat_o[6] o -wb_dat_o[5] o -wb_dat_o[4] o -wb_dat_o[3] o -wb_dat_o[2] o -wb_dat_o[1] o -wb_dat_o[0] o -wb_ack_o o -wbc_ufm_irq o +wb_clk_i i +wb_rst_i i +wb_cyc_i i +wb_stb_i i +wb_we_i i +wb_adr_i[7] i +wb_adr_i[6] i +wb_adr_i[5] i +wb_adr_i[4] i +wb_adr_i[3] i +wb_adr_i[2] i +wb_adr_i[1] i +wb_adr_i[0] i +wb_dat_i[7] i +wb_dat_i[6] i +wb_dat_i[5] i +wb_dat_i[4] i +wb_dat_i[3] i +wb_dat_i[2] i +wb_dat_i[1] i +wb_dat_i[0] i +wb_dat_o[7] o +wb_dat_o[6] o +wb_dat_o[5] o +wb_dat_o[4] o +wb_dat_o[3] o +wb_dat_o[2] o +wb_dat_o[1] o +wb_dat_o[0] o +wb_ack_o o +wbc_ufm_irq o diff --git a/CPLD/LCMXO2-640HC/REFB.sort b/CPLD/LCMXO2-640HC/REFB.sort index 794b751..96fe0d5 100644 --- a/CPLD/LCMXO2-640HC/REFB.sort +++ b/CPLD/LCMXO2-640HC/REFB.sort @@ -1 +1 @@ -REFB.v +REFB.v diff --git a/CPLD/LCMXO2-640HC/REFB.srp b/CPLD/LCMXO2-640HC/REFB.srp index 7dc4bd4..4cc652e 100644 --- a/CPLD/LCMXO2-640HC/REFB.srp +++ b/CPLD/LCMXO2-640HC/REFB.srp @@ -1,5 +1,5 @@ SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Aug 16 20:52:02 2023 +Sat Aug 19 07:25:04 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -7,7 +7,7 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 Circuit name : REFB Module type : efb Module Version : 1.2 diff --git a/CPLD/LCMXO2-640HC/REFB.v b/CPLD/LCMXO2-640HC/REFB.v index d9b5238..1b62001 100644 --- a/CPLD/LCMXO2-640HC/REFB.v +++ b/CPLD/LCMXO2-640HC/REFB.v @@ -1,7 +1,7 @@ /* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ /* Module Version: 1.2 */ -/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */ -/* Wed Aug 16 20:52:02 2023 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 */ +/* Sat Aug 19 07:25:04 2023 */ `timescale 1 ns / 1 ps @@ -26,8 +26,8 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, VLO scuba_vlo_inst (.Z(scuba_vlo)); defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; - defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ; - defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ; + defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ; + defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ; defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ; defparam EFBInst_0.UFM_INIT_PAGES = 1 ; defparam EFBInst_0.DEV_DENSITY = "640L" ; @@ -74,7 +74,7 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; - defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ; + defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ; EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), diff --git a/CPLD/LCMXO2-640HC/REFB_generate.log b/CPLD/LCMXO2-640HC/REFB_generate.log index 7291f66..a85d4f2 100644 --- a/CPLD/LCMXO2-640HC/REFB_generate.log +++ b/CPLD/LCMXO2-640HC/REFB_generate.log @@ -1,44 +1,44 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Aug 16 20:52:02 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - -File: REFB.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 07:25:04 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: REFB.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/CPLD/LCMXO2-640HC/REFB_tmpl.v b/CPLD/LCMXO2-640HC/REFB_tmpl.v index ac4a91c..97abc0c 100644 --- a/CPLD/LCMXO2-640HC/REFB_tmpl.v +++ b/CPLD/LCMXO2-640HC/REFB_tmpl.v @@ -1,6 +1,6 @@ /* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ /* Module Version: 1.2 */ -/* Wed Aug 16 20:52:02 2023 */ +/* Sat Aug 19 07:25:04 2023 */ /* parameterized module instance */ REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), diff --git a/CPLD/LCMXO2-640HC/_math_real.vhd b/CPLD/LCMXO2-640HC/_math_real.vhd index ad185b2..e1215d8 100644 --- a/CPLD/LCMXO2-640HC/_math_real.vhd +++ b/CPLD/LCMXO2-640HC/_math_real.vhd @@ -1,2574 +1,2574 @@ - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. --- --- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package defines a standard for designers to use in --- describing VHDL models that make use of common REAL constants --- and common REAL elementary mathematical functions. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076- --- 1993. --- --- Notes: --- No declarations or definitions shall be included in, or --- excluded from, this package. --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to provide a guideline for implementations to --- verify their implementation of MATH_REAL. Tool developers may --- choose to implement the package body in the most efficient --- manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package MATH_REAL is - constant CopyRightNotice: STRING - := "Copyright 1996 IEEE. All rights reserved."; - - -- - -- Constant Definitions - -- - constant MATH_E : REAL := 2.71828_18284_59045_23536; - -- Value of e - constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; - -- Value of 1/e - constant MATH_PI : REAL := 3.14159_26535_89793_23846; - -- Value of pi - constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; - -- Value of 2*pi - constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; - -- Value of 1/pi - constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; - -- Value of pi/2 - constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; - -- Value of pi/3 - constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; - -- Value of pi/4 - constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; - -- Value 3*pi/2 - constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; - -- Natural log of 2 - constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; - -- Natural log of 10 - constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; - -- Log base 2 of e - constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; - -- Log base 10 of e - constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; - -- square root of 2 - constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; - -- square root of 1/2 - constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; - -- square root of pi - constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; - -- Conversion factor from degree to radian - constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; - -- Conversion factor from radian to degree - - -- - -- Function Declarations - -- - function SIGN (X: in REAL ) return REAL; - -- Purpose: - -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIGN(X)) <= 1.0 - -- Notes: - -- None - - function CEIL (X : in REAL ) return REAL; - -- Purpose: - -- Returns smallest INTEGER value (as REAL) not less than X - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CEIL(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function FLOOR (X : in REAL ) return REAL; - -- Purpose: - -- Returns largest INTEGER value (as REAL) not greater than X - -- Special values: - -- FLOOR(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- FLOOR(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function ROUND (X : in REAL ) return REAL; - -- Purpose: - -- Rounds X to the nearest integer value (as real). If X is - -- halfway between two integers, rounding is away from 0.0 - -- Special values: - -- ROUND(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ROUND(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function TRUNC (X : in REAL ) return REAL; - -- Purpose: - -- Truncates X towards 0.0 and returns truncated value - -- Special values: - -- TRUNC(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- TRUNC(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function "MOD" (X, Y: in REAL ) return REAL; - -- Purpose: - -- Returns floating point modulus of X/Y, with the same sign as - -- Y, and absolute value less than the absolute value of Y, and - -- for some INTEGER value N the result satisfies the relation - -- X = Y*N + MOD(X,Y) - -- Special values: - -- None - -- Domain: - -- X in REAL; Y in REAL and Y /= 0.0 - -- Error conditions: - -- Error if Y = 0.0 - -- Range: - -- ABS(MOD(X,Y)) < ABS(Y) - -- Notes: - -- None - - function REALMAX (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically larger of X and Y - -- Special values: - -- REALMAX(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMAX(X,Y) is mathematically unbounded - -- Notes: - -- None - - function REALMIN (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically smaller of X and Y - -- Special values: - -- REALMIN(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMIN(X,Y) is mathematically unbounded - -- Notes: - -- None - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); - -- Purpose: - -- Returns, in X, a pseudo-random number with uniform - -- distribution in the open interval (0.0, 1.0). - -- Special values: - -- None - -- Domain: - -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 - -- Error conditions: - -- Error if SEED1 or SEED2 outside of valid domain - -- Range: - -- 0.0 < X < 1.0 - -- Notes: - -- a) The semantics for this function are described by the - -- algorithm published by Pierre L'Ecuyer in "Communications - -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. - -- The algorithm is based on the combination of two - -- multiplicative linear congruential generators for 32-bit - -- platforms. - -- - -- b) Before the first call to UNIFORM, the seed values - -- (SEED1, SEED2) have to be initialized to values in the range - -- [1, 2147483562] and [1, 2147483398] respectively. The - -- seed values are modified after each call to UNIFORM. - -- - -- c) This random number generator is portable for 32-bit - -- computers, and it has a period of ~2.30584*(10**18) for each - -- set of seed values. - -- - -- d) For information on spectral tests for the algorithm, refer - -- to the L'Ecuyer article. - - function SQRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns square root of X - -- Special values: - -- SQRT(0.0) = 0.0 - -- SQRT(1.0) = 1.0 - -- Domain: - -- X >= 0.0 - -- Error conditions: - -- Error if X < 0.0 - -- Range: - -- SQRT(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of SQRT is - -- approximately given by: - -- SQRT(X) <= SQRT(REAL'HIGH) - - function CBRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns cube root of X - -- Special values: - -- CBRT(0.0) = 0.0 - -- CBRT(1.0) = 1.0 - -- CBRT(-1.0) = -1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CBRT(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of CBRT is approximately given by: - -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) - - function "**" (X : in INTEGER; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0 - -- 0**Y = 0.0; Y > 0.0 - -- X**1.0 = REAL(X); X >= 0 - -- 1**Y = 1.0 - -- Domain: - -- X > 0 - -- X = 0 for Y > 0.0 - -- X < 0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0 and Y /= 0.0 - -- Error if X = 0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function "**" (X : in REAL; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0.0 - -- 0.0**Y = 0.0; Y > 0.0 - -- X**1.0 = X; X >= 0.0 - -- 1.0**Y = 1.0 - -- Domain: - -- X > 0.0 - -- X = 0.0 for Y > 0.0 - -- X < 0.0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0.0 and Y /= 0.0 - -- Error if X = 0.0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function EXP (X : in REAL ) return REAL; - -- Purpose: - -- Returns e**X; where e = MATH_E - -- Special values: - -- EXP(0.0) = 1.0 - -- EXP(1.0) = MATH_E - -- EXP(-1.0) = MATH_1_OVER_E - -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) - -- Domain: - -- X in REAL such that EXP(X) <= REAL'HIGH - -- Error conditions: - -- Error if X > LOG(REAL'HIGH) - -- Range: - -- EXP(X) >= 0.0 - -- Notes: - -- a) The usable domain of EXP is approximately given by: - -- X <= LOG(REAL'HIGH) - - function LOG (X : in REAL ) return REAL; - -- Purpose: - -- Returns natural logarithm of X - -- Special values: - -- LOG(1.0) = 0.0 - -- LOG(MATH_E) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG is approximately given by: - -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) - - function LOG2 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 2 of X - -- Special values: - -- LOG2(1.0) = 0.0 - -- LOG2(2.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG2(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG2 is approximately given by: - -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) - - function LOG10 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 10 of X - -- Special values: - -- LOG10(1.0) = 0.0 - -- LOG10(10.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG10(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG10 is approximately given by: - -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) - - function LOG (X: in REAL; BASE: in REAL) return REAL; - -- Purpose: - -- Returns logarithm base BASE of X - -- Special values: - -- LOG(1.0, BASE) = 0.0 - -- LOG(BASE, BASE) = 1.0 - -- Domain: - -- X > 0.0 - -- BASE > 0.0 - -- BASE /= 1.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Error if BASE <= 0.0 - -- Error if BASE = 1.0 - -- Range: - -- LOG(X, BASE) is mathematically unbounded - -- Notes: - -- a) When BASE > 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) - -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) - - function SIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns sine of X; X in radians - -- Special values: - -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIN(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function COS ( X : in REAL ) return REAL; - -- Purpose: - -- Returns cosine of X; X in radians - -- Special values: - -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER - -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(COS(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function TAN (X : in REAL ) return REAL; - -- Purpose: - -- Returns tangent of X; X in radians - -- Special values: - -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL and - -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER - -- Error conditions: - -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an - -- INTEGER - -- Range: - -- TAN(X) is mathematically unbounded - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function ARCSIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse sine of X - -- Special values: - -- ARCSIN(0.0) = 0.0 - -- ARCSIN(1.0) = MATH_PI_OVER_2 - -- ARCSIN(-1.0) = -MATH_PI_OVER_2 - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCCOS (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse cosine of X - -- Special values: - -- ARCCOS(1.0) = 0.0 - -- ARCCOS(0.0) = MATH_PI_OVER_2 - -- ARCCOS(-1.0) = MATH_PI - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- 0.0 <= ARCCOS(X) <= MATH_PI - -- Notes: - -- None - - function ARCTAN (Y : in REAL) return REAL; - -- Purpose: - -- Returns the value of the angle in radians of the point - -- (1.0, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0) = 0.0 - -- Domain: - -- Y in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCTAN (Y : in REAL; X : in REAL) return REAL; - -- Purpose: - -- Returns the principal value of the angle in radians of - -- the point (X, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0, X) = 0.0 if X > 0.0 - -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 - -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 - -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 - -- Domain: - -- Y in REAL - -- X in REAL, X /= 0.0 when Y = 0.0 - -- Error conditions: - -- Error if X = 0.0 and Y = 0.0 - -- Range: - -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI - -- Notes: - -- None - - function SINH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic sine of X - -- Special values: - -- SINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- SINH(X) is mathematically unbounded - -- Notes: - -- a) The usable domain of SINH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - - function COSH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic cosine of X - -- Special values: - -- COSH(0.0) = 1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- COSH(X) >= 1.0 - -- Notes: - -- a) The usable domain of COSH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - function TANH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic tangent of X - -- Special values: - -- TANH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(TANH(X)) <= 1.0 - -- Notes: - -- None - - function ARCSINH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic sine of X - -- Special values: - -- ARCSINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ARCSINH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCSINH is approximately given by: - -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) - - function ARCCOSH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic cosine of X - -- Special values: - -- ARCCOSH(1.0) = 0.0 - -- Domain: - -- X >= 1.0 - -- Error conditions: - -- Error if X < 1.0 - -- Range: - -- ARCCOSH(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of ARCCOSH is - -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) - - function ARCTANH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic tangent of X - -- Special values: - -- ARCTANH(0.0) = 0.0 - -- Domain: - -- ABS(X) < 1.0 - -- Error conditions: - -- Error if ABS(X) >= 1.0 - -- Range: - -- ARCTANH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCTANH is approximately given by: - -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) - -end MATH_REAL; - - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. - --- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. - --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package body is a nonnormative implementation of the --- functionality defined in the MATH_REAL package declaration. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076 --- -1993. --- --- Notes: --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to clarify such semantics and provide a --- guideline for implementations to verify their implementation --- of MATH_REAL. Tool developers may choose to implement --- the package body in the most efficient manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package body MATH_REAL is - - -- - -- Local Constants for Use in the Package Body Only - -- - constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 - constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 - constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi - constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic - constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries - constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria - constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic - - -- - -- Local Type Declarations for Cordic Operations - -- - type REAL_VECTOR is array (NATURAL range <>) of REAL; - type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; - subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); - subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); - subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); - subtype QUADRANT is INTEGER range 0 to 3; - type CORDIC_MODE_TYPE is (ROTATION, VECTORING); - - -- - -- Auxiliary Functions for Cordic Algorithms - -- - function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; - NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is - -- Description: - -- Returns power of two for a vector of values - -- Notes: - -- None - -- - variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); - variable TEMP : REAL := INITIAL_VALUE; - variable FLAG : BOOLEAN := TRUE; - begin - for I in 0 to NUMBER_OF_VALUES loop - V(I) := TEMP; - for P in D'RANGE loop - if I = D(P) then - FLAG := FALSE; - exit; - end if; - end loop; - if FLAG then - TEMP := TEMP/2.0; - end if; - FLAG := TRUE; - end loop; - return V; - end POWER_OF_2_SERIES; - - - constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( - NATURAL_VECTOR'(100, 90),1.0, - MAX_ITER); - - constant EPSILON : REAL_VECTOR_N := ( - 7.8539816339744827e-01, - 4.6364760900080606e-01, - 2.4497866312686413e-01, - 1.2435499454676144e-01, - 6.2418809995957351e-02, - 3.1239833430268277e-02, - 1.5623728620476830e-02, - 7.8123410601011116e-03, - 3.9062301319669717e-03, - 1.9531225164788189e-03, - 9.7656218955931937e-04, - 4.8828121119489829e-04, - 2.4414062014936175e-04, - 1.2207031189367021e-04, - 6.1035156174208768e-05, - 3.0517578115526093e-05, - 1.5258789061315760e-05, - 7.6293945311019699e-06, - 3.8146972656064960e-06, - 1.9073486328101870e-06, - 9.5367431640596080e-07, - 4.7683715820308876e-07, - 2.3841857910155801e-07, - 1.1920928955078067e-07, - 5.9604644775390553e-08, - 2.9802322387695303e-08, - 1.4901161193847654e-08, - 7.4505805969238281e-09 - ); - - function CORDIC ( X0 : in REAL; - Y0 : in REAL; - Z0 : in REAL; - N : in NATURAL; -- Precision factor - CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) - -- or vectoring (Y -> 0) - ) return REAL_ARR_3 is - -- Description: - -- Compute cordic values - -- Notes: - -- None - variable X : REAL := X0; - variable Y : REAL := Y0; - variable Z : REAL := Z0; - variable X_TEMP : REAL; - begin - if CORDIC_MODE = ROTATION then - for K in 0 to N loop - X_TEMP := X; - if ( Z >= 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - else - for K in 0 to N loop - X_TEMP := X; - if ( Y < 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - end if; - return REAL_ARR_3'(X, Y, Z); - end CORDIC; - - -- - -- Bodies for Global Mathematical Functions Start Here - -- - function SIGN (X: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- None - begin - if ( X > 0.0 ) then - return 1.0; - elsif ( X < 0.0 ) then - return -1.0; - else - return 0.0; - end if; - end SIGN; - - function CEIL (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is X <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS(X) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD >= X then - return RD; - else - return RD + 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD <= X then - return RD + 1.0; - else - return RD; - end if; - end if; - end CEIL; - - function FLOOR (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is ABS(X) <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS( X ) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD <= X then - return RD; - else - return RD - 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD >= X then - return RD - 1.0; - else - return RD; - end if; - end if; - end FLOOR; - - function ROUND (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X + 0.5) if X > 0 - -- c) Returns CEIL(X - 0.5) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X + 0.5); - elsif X < 0.0 then - return CEIL( X - 0.5); - else - return 0.0; - end if; - end ROUND; - - function TRUNC (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X) if X > 0 - -- c) Returns CEIL(X) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X); - elsif X < 0.0 then - return CEIL( X); - else - return 0.0; - end if; - end TRUNC; - - - - - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - end "MOD"; - - - function REALMAX (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMAX(X,Y) = X when X = Y - -- - begin - if X >= Y then - return X; - else - return Y; - end if; - end REALMAX; - - function REALMIN (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMIN(X,Y) = X when X = Y - -- - begin - if X <= Y then - return X; - else - return Y; - end if; - end REALMIN; - - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) - is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - -- - variable Z, K: INTEGER; - variable TSEED1 : INTEGER := INTEGER'(SEED1); - variable TSEED2 : INTEGER := INTEGER'(SEED2); - begin - -- Check validity of arguments - if SEED1 > 2147483562 then - assert FALSE - report "SEED1 > 2147483562 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - if SEED2 > 2147483398 then - assert FALSE - report "SEED2 > 2147483398 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - -- Compute new seed values and pseudo-random number - K := TSEED1/53668; - TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; - - if TSEED1 < 0 then - TSEED1 := TSEED1 + 2147483563; - end if; - - K := TSEED2/52774; - TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; - - if TSEED2 < 0 then - TSEED2 := TSEED2 + 2147483399; - end if; - - Z := TSEED1 - TSEED2; - if Z < 1 then - Z := Z + 2147483562; - end if; - - -- Get output values - SEED1 := POSITIVE'(TSEED1); - SEED2 := POSITIVE'(TSEED2); - X := REAL(Z)*4.656613e-10; - end UNIFORM; - - - - function SQRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = 0.5*[F(n) + x/F(n)] - -- b) Returns 0.0 on error - -- - - constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor - - variable INIVAL: REAL; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - -- Check validity of argument - if ( X < 0.0 ) then - assert FALSE - report "X < 0.0 in SQRT(X)" - severity ERROR; - return 0.0; - end if; - - -- Get the square root for special cases - if X = 0.0 then - return 0.0; - else - if ( X = 1.0 ) then - return 1.0; - end if; - end if; - - -- Get the square root for general cases - INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise - OLDVAL := INIVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - - -- Check for relative and absolute error and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT) ) loop - OLDVAL := NEWVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - COUNT := COUNT + 1; - end loop; - return NEWVAL; - end SQRT; - - function CBRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; - -- - constant EPS : REAL := BASE_EPS*BASE_EPS; - - variable INIVAL: REAL; - variable XLOCAL : REAL := X; - variable NEGATIVE : BOOLEAN := X < 0.0; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - - -- Compute root for special cases - if X = 0.0 then - return 0.0; - elsif ( X = 1.0 ) then - return 1.0; - else - if X = -1.0 then - return -1.0; - end if; - end if; - - -- Compute root for general cases - if NEGATIVE then - XLOCAL := -X; - end if; - - INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but - -- imprecise - OLDVAL := INIVAL; - NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR - (ABS(NEWVAL - OLDVAL) > EPS ) ) AND - ( COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - COUNT := COUNT + 1; - end loop; - - if NEGATIVE then - NEWVAL := -NEWVAL; - end if; - - return NEWVAL; - end CBRT; - - function "**" (X : in INTEGER; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (REAL(X)); - end if; - - -- Get value for general case - return EXP (Y * LOG (REAL(X))); - end "**"; - - function "**" (X : in REAL; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0.0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0.0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0.0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1.0 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0.0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (X); - end if; - - -- Get value for general case - return EXP (Y * LOG (X)); - end "**"; - - function EXP (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) This function computes the exponential using the following - -- series: - -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 - -- and reduces argument X to take advantage of exp(x+y) = - -- exp(x)*exp(y) - -- - -- b) This implementation limits X to be less than LOG(REAL'HIGH) - -- to avoid overflow. Returns REAL'HIGH when X reaches that - -- limit - -- - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria - - variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument - variable XLOCAL : REAL := ABS(X); -- Use positive value - variable OLDVAL: REAL ; - variable COUNT: INTEGER ; - variable NEWVAL: REAL ; - variable LAST_TERM: REAL ; - variable FACTOR : REAL := 1.0; - - begin - -- Compute value for special cases - if X = 0.0 then - return 1.0; - end if; - - if XLOCAL = 1.0 then - if RECIPROCAL then - return MATH_1_OVER_E; - else - return MATH_E; - end if; - end if; - - if XLOCAL = 2.0 then - if RECIPROCAL then - return 1.0/MATH_E_P2; - else - return MATH_E_P2; - end if; - end if; - - if XLOCAL = 10.0 then - if RECIPROCAL then - return 1.0/MATH_E_P10; - else - return MATH_E_P10; - end if; - end if; - - if XLOCAL > LOG(REAL'HIGH) then - if RECIPROCAL then - return 0.0; - else - assert FALSE - report "X > LOG(REAL'HIGH) in EXP(X)" - severity NOTE; - return REAL'HIGH; - end if; - end if; - - -- Reduce argument to ABS(X) < 1.0 - while XLOCAL > 10.0 loop - XLOCAL := XLOCAL - 10.0; - FACTOR := FACTOR*MATH_E_P10; - end loop; - - while XLOCAL > 1.0 loop - XLOCAL := XLOCAL - 1.0; - FACTOR := FACTOR*MATH_E; - end loop; - - -- Compute value for case 0 < XLOCAL < 1 - OLDVAL := 1.0; - LAST_TERM := XLOCAL; - NEWVAL:= OLDVAL + LAST_TERM; - COUNT := 2; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); - NEWVAL := OLDVAL + LAST_TERM; - COUNT := COUNT + 1; - end loop; - - -- Compute final value using exp(x+y) = exp(x)*exp(y) - NEWVAL := NEWVAL*FACTOR; - - if RECIPROCAL then - NEWVAL := 1.0/NEWVAL; - end if; - - return NEWVAL; - end EXP; - - - -- - -- Auxiliary Functions to Compute LOG - -- - function ILOGB(X: in REAL) return INTEGER IS - -- Description: - -- Returns n such that -1 <= ABS(X)/2^n < 2 - -- Notes: - -- None - - variable N: INTEGER := 0; - variable Y: REAL := ABS(X); - - begin - if(Y = 1.0 or Y = 0.0) then - return 0; - end if; - - if( Y > 1.0) then - while Y >= 2.0 loop - Y := Y/2.0; - N := N+1; - end loop; - return N; - end if; - - -- O < Y < 1 - while Y < 1.0 loop - Y := Y*2.0; - N := N -1; - end loop; - return N; - end ILOGB; - - function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS - -- Description: - -- Returns X*2^n - -- Notes: - -- None - begin - return X*(2.0 ** N); - end LDEXP; - - function LOG (X : in REAL ) return REAL IS - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- - -- Notes: - -- a) Returns REAL'LOW on error - -- - -- Copyright (c) 1992 Regents of the University of California. - -- All rights reserved. - -- - -- Redistribution and use in source and binary forms, with or without - -- modification, are permitted provided that the following conditions - -- are met: - -- 1. Redistributions of source code must retain the above copyright - -- notice, this list of conditions and the following disclaimer. - -- 2. Redistributions in binary form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- 3. All advertising materials mentioning features or use of this - -- software must display the following acknowledgement: - -- This product includes software developed by the University of - -- California, Berkeley and its contributors. - -- 4. Neither the name of the University nor the names of its - -- contributors may be used to endorse or promote products derived - -- from this software without specific prior written permission. - -- - -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR - -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - -- DAMAGE. - -- - -- NOTE: This VHDL version was generated using the C version of the - -- original function by the IEEE VHDL Mathematical Package - -- Working Group (CS/JT) - - constant N: INTEGER := 128; - - -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. - -- Used for generation of extend precision logarithms. - -- The constant 35184372088832 is 2^45, so the divide is exact. - -- It ensures correct reading of logF_head, even for inaccurate - -- decimal-to-binary conversion routines. (Everybody gets the - -- right answer for INTEGERs less than 2^53.) - -- Values for LOG(F) were generated using error < 10^-57 absolute - -- with the bc -l package. - - type REAL_VECTOR is array (NATURAL range <>) of REAL; - - constant A1:REAL := 0.08333333333333178827; - constant A2:REAL := 0.01250000000377174923; - constant A3:REAL := 0.002232139987919447809; - constant A4:REAL := 0.0004348877777076145742; - - constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( - 0.0, - 0.007782140442060381246, - 0.015504186535963526694, - 0.023167059281547608406, - 0.030771658666765233647, - 0.038318864302141264488, - 0.045809536031242714670, - 0.053244514518837604555, - 0.060624621816486978786, - 0.067950661908525944454, - 0.075223421237524235039, - 0.082443669210988446138, - 0.089612158689760690322, - 0.096729626458454731618, - 0.103796793681567578460, - 0.110814366340264314203, - 0.117783035656430001836, - 0.124703478501032805070, - 0.131576357788617315236, - 0.138402322859292326029, - 0.145182009844575077295, - 0.151916042025732167530, - 0.158605030176659056451, - 0.165249572895390883786, - 0.171850256926518341060, - 0.178407657472689606947, - 0.184922338493834104156, - 0.191394852999565046047, - 0.197825743329758552135, - 0.204215541428766300668, - 0.210564769107350002741, - 0.216873938300523150246, - 0.223143551314024080056, - 0.229374101064877322642, - 0.235566071312860003672, - 0.241719936886966024758, - 0.247836163904594286577, - 0.253915209980732470285, - 0.259957524436686071567, - 0.265963548496984003577, - 0.271933715484010463114, - 0.277868451003087102435, - 0.283768173130738432519, - 0.289633292582948342896, - 0.295464212893421063199, - 0.301261330578199704177, - 0.307025035294827830512, - 0.312755710004239517729, - 0.318453731118097493890, - 0.324119468654316733591, - 0.329753286372579168528, - 0.335355541920762334484, - 0.340926586970454081892, - 0.346466767346100823488, - 0.351976423156884266063, - 0.357455888922231679316, - 0.362905493689140712376, - 0.368325561158599157352, - 0.373716409793814818840, - 0.379078352934811846353, - 0.384411698910298582632, - 0.389716751140440464951, - 0.394993808240542421117, - 0.400243164127459749579, - 0.405465108107819105498, - 0.410659924985338875558, - 0.415827895143593195825, - 0.420969294644237379543, - 0.426084395310681429691, - 0.431173464818130014464, - 0.436236766774527495726, - 0.441274560805140936281, - 0.446287102628048160113, - 0.451274644139630254358, - 0.456237433481874177232, - 0.461175715122408291790, - 0.466089729924533457960, - 0.470979715219073113985, - 0.475845904869856894947, - 0.480688529345570714212, - 0.485507815781602403149, - 0.490303988045525329653, - 0.495077266798034543171, - 0.499827869556611403822, - 0.504556010751912253908, - 0.509261901790523552335, - 0.513945751101346104405, - 0.518607764208354637958, - 0.523248143765158602036, - 0.527867089620485785417, - 0.532464798869114019908, - 0.537041465897345915436, - 0.541597282432121573947, - 0.546132437597407260909, - 0.550647117952394182793, - 0.555141507540611200965, - 0.559615787935399566777, - 0.564070138285387656651, - 0.568504735352689749561, - 0.572919753562018740922, - 0.577315365035246941260, - 0.581691739635061821900, - 0.586049045003164792433, - 0.590387446602107957005, - 0.594707107746216934174, - 0.599008189645246602594, - 0.603290851438941899687, - 0.607555250224322662688, - 0.611801541106615331955, - 0.616029877215623855590, - 0.620240409751204424537, - 0.624433288012369303032, - 0.628608659422752680256, - 0.632766669570628437213, - 0.636907462236194987781, - 0.641031179420679109171, - 0.645137961373620782978, - 0.649227946625615004450, - 0.653301272011958644725, - 0.657358072709030238911, - 0.661398482245203922502, - 0.665422632544505177065, - 0.669430653942981734871, - 0.673422675212350441142, - 0.677398823590920073911, - 0.681359224807238206267, - 0.685304003098281100392, - 0.689233281238557538017, - 0.693147180560117703862); - - constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( - 0.0, - -0.00000000000000543229938420049, - 0.00000000000000172745674997061, - -0.00000000000001323017818229233, - -0.00000000000001154527628289872, - -0.00000000000000466529469958300, - 0.00000000000005148849572685810, - -0.00000000000002532168943117445, - -0.00000000000005213620639136504, - -0.00000000000001819506003016881, - 0.00000000000006329065958724544, - 0.00000000000008614512936087814, - -0.00000000000007355770219435028, - 0.00000000000009638067658552277, - 0.00000000000007598636597194141, - 0.00000000000002579999128306990, - -0.00000000000004654729747598444, - -0.00000000000007556920687451336, - 0.00000000000010195735223708472, - -0.00000000000017319034406422306, - -0.00000000000007718001336828098, - 0.00000000000010980754099855238, - -0.00000000000002047235780046195, - -0.00000000000008372091099235912, - 0.00000000000014088127937111135, - 0.00000000000012869017157588257, - 0.00000000000017788850778198106, - 0.00000000000006440856150696891, - 0.00000000000016132822667240822, - -0.00000000000007540916511956188, - -0.00000000000000036507188831790, - 0.00000000000009120937249914984, - 0.00000000000018567570959796010, - -0.00000000000003149265065191483, - -0.00000000000009309459495196889, - 0.00000000000017914338601329117, - -0.00000000000001302979717330866, - 0.00000000000023097385217586939, - 0.00000000000023999540484211737, - 0.00000000000015393776174455408, - -0.00000000000036870428315837678, - 0.00000000000036920375082080089, - -0.00000000000009383417223663699, - 0.00000000000009433398189512690, - 0.00000000000041481318704258568, - -0.00000000000003792316480209314, - 0.00000000000008403156304792424, - -0.00000000000034262934348285429, - 0.00000000000043712191957429145, - -0.00000000000010475750058776541, - -0.00000000000011118671389559323, - 0.00000000000037549577257259853, - 0.00000000000013912841212197565, - 0.00000000000010775743037572640, - 0.00000000000029391859187648000, - -0.00000000000042790509060060774, - 0.00000000000022774076114039555, - 0.00000000000010849569622967912, - -0.00000000000023073801945705758, - 0.00000000000015761203773969435, - 0.00000000000003345710269544082, - -0.00000000000041525158063436123, - 0.00000000000032655698896907146, - -0.00000000000044704265010452446, - 0.00000000000034527647952039772, - -0.00000000000007048962392109746, - 0.00000000000011776978751369214, - -0.00000000000010774341461609578, - 0.00000000000021863343293215910, - 0.00000000000024132639491333131, - 0.00000000000039057462209830700, - -0.00000000000026570679203560751, - 0.00000000000037135141919592021, - -0.00000000000017166921336082431, - -0.00000000000028658285157914353, - -0.00000000000023812542263446809, - 0.00000000000006576659768580062, - -0.00000000000028210143846181267, - 0.00000000000010701931762114254, - 0.00000000000018119346366441110, - 0.00000000000009840465278232627, - -0.00000000000033149150282752542, - -0.00000000000018302857356041668, - -0.00000000000016207400156744949, - 0.00000000000048303314949553201, - -0.00000000000071560553172382115, - 0.00000000000088821239518571855, - -0.00000000000030900580513238244, - -0.00000000000061076551972851496, - 0.00000000000035659969663347830, - 0.00000000000035782396591276383, - -0.00000000000046226087001544578, - 0.00000000000062279762917225156, - 0.00000000000072838947272065741, - 0.00000000000026809646615211673, - -0.00000000000010960825046059278, - 0.00000000000002311949383800537, - -0.00000000000058469058005299247, - -0.00000000000002103748251144494, - -0.00000000000023323182945587408, - -0.00000000000042333694288141916, - -0.00000000000043933937969737844, - 0.00000000000041341647073835565, - 0.00000000000006841763641591466, - 0.00000000000047585534004430641, - 0.00000000000083679678674757695, - -0.00000000000085763734646658640, - 0.00000000000021913281229340092, - -0.00000000000062242842536431148, - -0.00000000000010983594325438430, - 0.00000000000065310431377633651, - -0.00000000000047580199021710769, - -0.00000000000037854251265457040, - 0.00000000000040939233218678664, - 0.00000000000087424383914858291, - 0.00000000000025218188456842882, - -0.00000000000003608131360422557, - -0.00000000000050518555924280902, - 0.00000000000078699403323355317, - -0.00000000000067020876961949060, - 0.00000000000016108575753932458, - 0.00000000000058527188436251509, - -0.00000000000035246757297904791, - -0.00000000000018372084495629058, - 0.00000000000088606689813494916, - 0.00000000000066486268071468700, - 0.00000000000063831615170646519, - 0.00000000000025144230728376072, - -0.00000000000017239444525614834); - - variable M, J:INTEGER; - variable F1, F2, G, Q, U, U2, V: REAL; - variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs - variable ONE: REAL := 1.0; --Made variable so no constant folding occurs - - -- double logb(), ldexp(); - - variable U1:REAL; - - begin - - -- Check validity of argument - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = MATH_E ) then - return 1.0; - end if; - - -- Argument reduction: 1 <= g < 2; x/2^m = g; - -- y = F*(1 + f/F) for |f| <= 2^-8 - - M := ILOGB(X); - G := LDEXP(X, -M); - J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding - F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] - F2 := G - F1; - - -- Approximate expansion for log(1+f2/F1) ~= u + q - G := 1.0/(2.0*F1+F2); - U := 2.0*F2*G; - V := U*U; - Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); - - -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, - -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. - -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. - -- - if ( J /= 0 or M /= 0) then - U1 := U + 513.0; - U1 := U1 - 513.0; - - -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero - -- u1 = u to 24 bits. - -- - else - U1 := U; - --TRUNC(U1); --In c this is u1 = (double) (float) (u1) - end if; - - U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; - -- u1 + u2 = 2f/(2F+f) to extra precision. - - -- log(x) = log(2^m*F1*(1+f2/F1)) = - -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); - -- (exact) + (tiny) - - U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact - U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny - U2 := U2 + LOGF_TAIL(N)*REAL(M); - return (U1 + U2); - end LOG; - - - function LOG2 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG2(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 2.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG2_OF_E*LOG(X) ); - end LOG2; - - - function LOG10 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG10(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 10.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG10_OF_E*LOG(X) ); - end LOG10; - - - function LOG (X: in REAL; BASE: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - if ( BASE <= 0.0 or BASE = 1.0 ) then - assert FALSE - report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = BASE ) then - return 1.0; - end if; - - -- Compute value for general case - return ( LOG(X)/LOG(BASE)); - end LOG; - - - function SIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) SIN(-X) = -SIN(X) - -- b) SIN(X) = X if ABS(X) < EPS - -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS - -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) - -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS - -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in SIN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then - return 0.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 then - if NEGATIVE then - return -1.0; - else - return 1.0; - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - if NEGATIVE then - return 1.0; - else - return -1.0; - end if; - end if; - - if XLOCAL < EPS then - if NEGATIVE then - return -XLOCAL; - else - return XLOCAL; - end if; - else - if XLOCAL < BASE_EPS then - TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_2_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - -- Compute value for general cases - if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then - VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); - end if; - - N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); - case QUADRANT( N mod 4) is - when 0 => - VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); - when 1 => - VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, - ROTATION)(0); - when 2 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); - when 3 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, - ROTATION)(0); - end case; - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end SIN; - - - function COS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) COS(-X) = COS(X) - -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) - -- c) COS(MATH_PI + X) = -COS(X) - -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS - -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in COS(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then - return 1.0; - end if; - - if XLOCAL = MATH_PI then - return -1.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then - return 0.0; - end if; - - TEMP := ABS(XLOCAL); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS(XLOCAL -MATH_2_PI); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS (XLOCAL - MATH_PI); - if TEMP < EPS then - return (-1.0 + 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - -- Compute value for general cases - return SIN(MATH_PI_OVER_2 - XLOCAL); - end COS; - - function TAN (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) TAN(0.0) = 0.0 - -- b) TAN(-X) = -TAN(X) - -- c) Returns REAL'LOW on error if X < 0.0 - -- d) Returns REAL'HIGH on error if X > 0.0 - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X) ; - variable VALUE: REAL; - variable TEMP : REAL; - - begin - -- Make 0.0 <= XLOCAL <= MATH_2_PI - if XLOCAL > MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in TAN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Check validity of argument - if XLOCAL = MATH_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'LOW); - else - return(REAL'HIGH); - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'HIGH); - else - return(REAL'LOW); - end if; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_PI then - return 0.0; - end if; - - -- Compute value for general cases - VALUE := SIN(XLOCAL)/COS(XLOCAL); - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TAN; - - function ARCSIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCSIN(-X) = -ARCSIN(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of arguments - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCSIN(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - elsif XLOCAL = 1.0 then - if NEGATIVE then - return -MATH_PI_OVER_2; - else - return MATH_PI_OVER_2; - end if; - end if; - - -- Compute value for general cases - if XLOCAL < 0.9 then - VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCSIN; - - function ARCCOS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of argument - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCCOS(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - elsif X = 0.0 then - return MATH_PI_OVER_2; - elsif X = -1.0 then - return MATH_PI; - end if; - - -- Compute value for general cases - if XLOCAL > 0.9 then - VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); - end if; - - - if NEGATIVE then - VALUE := MATH_PI - VALUE; - end if; - - return VALUE; - end ARCCOS; - - - function ARCTAN (Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCTAN(-Y) = -ARCTAN(Y) - -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 - -- c) ARCTAN(Y) = Y for |Y| < EPS - - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; - - variable NEGATIVE : BOOLEAN := Y < 0.0; - variable RECIPROCAL : BOOLEAN; - variable YLOCAL : REAL := ABS(Y); - variable VALUE : REAL; - - begin - -- Make argument |Y| <=1.0 - if YLOCAL > 1.0 then - YLOCAL := 1.0/YLOCAL; - RECIPROCAL := TRUE; - else - RECIPROCAL := FALSE; - end if; - - -- Compute value for special cases - if YLOCAL = 0.0 then - if RECIPROCAL then - if NEGATIVE then - return (-MATH_PI_OVER_2); - else - return (MATH_PI_OVER_2); - end if; - else - return 0.0; - end if; - end if; - - if YLOCAL < EPS then - if NEGATIVE then - if RECIPROCAL then - return (-MATH_PI_OVER_2 + YLOCAL); - else - return -YLOCAL; - end if; - else - if RECIPROCAL then - return (MATH_PI_OVER_2 - YLOCAL); - else - return YLOCAL; - end if; - end if; - end if; - - -- Compute value for general cases - VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); - - if RECIPROCAL then - VALUE := MATH_PI_OVER_2 - VALUE; - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function ARCTAN (Y : in REAL; X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable YLOCAL : REAL; - variable VALUE : REAL; - begin - - -- Check validity of arguments - if (Y = 0.0 and X = 0.0 ) then - assert FALSE report - "ARCTAN(0.0, 0.0) is undetermined" - severity ERROR; - return 0.0; - end if; - - -- Compute value for special cases - if Y = 0.0 then - if X > 0.0 then - return 0.0; - else - return MATH_PI; - end if; - end if; - - if X = 0.0 then - if Y > 0.0 then - return MATH_PI_OVER_2; - else - return -MATH_PI_OVER_2; - end if; - end if; - - - -- Compute value for general cases - YLOCAL := ABS(Y/X); - - VALUE := ARCTAN(YLOCAL); - - if X < 0.0 then - VALUE := MATH_PI - VALUE; - end if; - - if Y < 0.0 then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function SINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/2.0 - -- b) SINH(-X) = SINH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)*0.5; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end SINH; - - function COSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) + EXP(-X))/2.0 - -- b) COSH(-X) = COSH(X) - - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 1.0; - end if; - - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP + 1.0/TEMP)*0.5; - - return VALUE; - end COSH; - - function TANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) - -- b) TANH(-X) = -TANH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TANH; - - function ARCSINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X + 1.0)) - - begin - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X + 1.0)) ); - end ARCSINH; - - - - function ARCCOSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 - -- b) Returns X on error - - begin - -- Check validity of arguments - if X < 1.0 then - assert FALSE - report "X < 1.0 in ARCCOSH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X - 1.0))); - end ARCCOSH; - - function ARCTANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 - -- b) Returns X on error - begin - -- Check validity of arguments - if ABS(X) >= 1.0 then - assert FALSE - report "ABS(X) >= 1.0 in ARCTANH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); - end ARCTANH; - -end MATH_REAL; + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/CPLD/LCMXO2-640HC/generate_core.tcl b/CPLD/LCMXO2-640HC/generate_core.tcl index d562b73..47f429b 100644 --- a/CPLD/LCMXO2-640HC/generate_core.tcl +++ b/CPLD/LCMXO2-640HC/generate_core.tcl @@ -1,100 +1,100 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "REFB" -set lang "verilog" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "xo2c00" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "REFB" +set lang "verilog" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "xo2c00" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg diff --git a/CPLD/LCMXO2-640HC/generate_ngd.tcl b/CPLD/LCMXO2-640HC/generate_ngd.tcl index 239c19c..d6ce2af 100644 --- a/CPLD/LCMXO2-640HC/generate_ngd.tcl +++ b/CPLD/LCMXO2-640HC/generate_ngd.tcl @@ -1,74 +1,74 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "REFB" -set Para(Module) "EFB" -set Para(libname) machxo2 -set Para(arch_name) xo2c00 -set Para(PartType) "LCMXO2-640HC" - -set Para(tech_syn) machxo2 -set Para(tech_cae) machxo2 -set Para(Package) "TQFP100" -set Para(SpeedGrade) "4" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "REFB" +set Para(Module) "EFB" +set Para(libname) machxo2 +set Para(arch_name) xo2c00 +set Para(PartType) "LCMXO2-640HC" + +set Para(tech_syn) machxo2 +set Para(tech_cae) machxo2 +set Para(Package) "TQFP100" +set Para(SpeedGrade) "4" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg diff --git a/CPLD/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2-640HC/impl1/.build_status index b4a92f0..4caaa2d 100644 --- a/CPLD/LCMXO2-640HC/impl1/.build_status +++ b/CPLD/LCMXO2-640HC/impl1/.build_status @@ -2,41 +2,54 @@ - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - + + - - + + - - + + - - - - - - + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs b/CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs new file mode 100644 index 0000000..267f374 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs @@ -0,0 +1,3151 @@ +|************************************************************************ +| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454 +| Generate date: Sat Aug 19 21:55:13 2023 +|************************************************************************ +| IBIS File LibisMaker.ibs +| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation +| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor +| North Carolina State University, ERL, 2006 +|************************************************************************ +[IBIS ver] 3.2 +[File Name] LCMXO2_640HC_impl1.ibs +[File Rev] 3.5 +[Date] Thu Sep 10 07:33:23 PDT 2020 +[Source] Lattice Semiconductor cs200fl Process + LCMXO2-640HC FINAL + Lattice Semiconductor has worked hard to ensure the + models below are accurate and complete. However, the + data below was generated using simulation of the + input/output model files for the silicon. Therefore, + the data below is for reference and initial design + purposes only. +| + Lattice Semiconductor grants permission to use this + data for use in printed circuit design using this + Lattice programmable logic device. Other use of this + code, including the selling or duplication of any + portion is strictly prohibited. +| +| NAMING CONVENTION +| + The IBIS [Model] header is limited by the specification to a + total of characters. With such a set of characters available + for naming models it becomes important to attempt to + meaningfully encode the IO standards so they fit within the + twenty character limit. It would seem that twenty characters + would provide room enough for describing IO's. However, the + PLD IO structure continues to grow more and more complex. The + complexity is making the twenty characters insuffiently + descriptive. In order to overcome this issue the naming + convention described below is implemented to resolve the issue. +| +The twenty character space is managed as follows: + bbbvvvsdddprugtcoixx +| + b = standard + v = voltage (x.xx V) + s = slew code + d = drive (xx.x ma) + p = pullup code + r = series resistance or bank_vccio code + u = terminate to vcc code + g = terminate to gnd code + t = terminate to vtt code + c = common mode termination mode + o = diff resistor code + i = diff resistor current code + x = reserved +| +| + standard +| + lvcmos lvc + lvcmosd lvd + lvcmosr lvr + lvds25e lve + lvttl lvt + lvttld ltd + pci pci + sstl_I ss1 + sstl_II ss2 + sstld_I s1d + sstld_II s2d + hstl_i hs1 + hstl_ii hs2 + hstld_i h1d + hstld_ii h2d + lvds25 lvs + blvds25 blv + blvds25e blv + mlvds25 mlv + mlvds25e mlv + lvpecl33 lvp + lvpecl33e lvp + rsds25 rsd + rsds25e rse + mipi mip + mipi_lp mip + vref1 vr1 + vref2 vr2 + ref_res rer +| +| + slew + na a + fast f + slow s +| + pullmode + off a + pullup b + pulldown c + bushold d + clamp e + up_clamp f + down_clamp g + keeper_clamp h +| + impedance or Bank_vccio + off a + 25 b + 33 c + 50 d + 100 e + 3.3 f + 2.5 g + 1.8 h + 1.5 i + 1.2 j +| + termVCC + off a + 50 b + 100 c + 120 d +| + termGND + off a + 50 b + 100 c + 120 d +| + termVTT + off a + 60 b + 75 c + 120 d + 150 e + 210 f +| + VCMT + off a + VCMT b + VTT c + DDR-2 d +| + differential resistor + off a + 100 b +| + diff drive + NA a + 2.0 b + 3.5 c + 1.25 f + 2.5 g +| + Reserved IO type + in input only + ou output + io I/O + od Open drain + on Inverting differential I/O + (signal name only) + op Non-Inverting differential I/O + (signal name only) +| + Lattice Semiconductor Corporation + 5555 NE Moore Court + Hillsboro, OR 97214 + U.S.A +| + TEL: 1-800-Lattice (USA and Canada) + 408-826-6000 (other locations) +| + web: http://www.latticesemi.com/ + email: techsupport@latticesemi.com +| +| +| +[Disclaimer] This IBIS source code is intended as a design reference + which illustrates how the Lattice Semiconductor device operates. + It is the user's responsibility to verify their design for + consistency and functionality through the use of formal + verification methods. Lattice Semiconductor provides no warranty + regarding the use or functionality of this data. +| +[Copyright] Copyright 2007 by Lattice Semiconductor Corporation +| +| +|************************************************************************ +| Component XO2 +|************************************************************************ +| +[Component] XO2 +[Manufacturer] Lattice Semiconductor Corp. +[Package] +|TQFP100 +| variable typ min max +R_pkg 150.5m 124.0m 187.0m +L_pkg 6.27nH 5.50nH 7.16nH +C_pkg 0.95pF 0.87pF 1.07pF +| +[Pin] signal_name model_name R_pin L_pin C_pin +10 CROW[0] lvc330axxxhfaaaaaain +16 CROW[1] lvc330axxxhfaaaaaain +3 Din[0] lvc330axxxhfaaaaaain +96 Din[1] lvc330axxxhfaaaaaain +88 Din[2] lvc330axxxhfaaaaaain +97 Din[3] lvc330axxxhfaaaaaain +99 Din[4] lvc330axxxhfaaaaaain +98 Din[5] lvc330axxxhfaaaaaain +2 Din[6] lvc330axxxhfaaaaaain +1 Din[7] lvc330axxxhfaaaaaain +76 Dout[0] lvc330s040daaaaaaaou +86 Dout[1] lvc330s040daaaaaaaou +87 Dout[2] lvc330s040daaaaaaaou +85 Dout[3] lvc330s040daaaaaaaou +83 Dout[4] lvc330s040daaaaaaaou +84 Dout[5] lvc330s040daaaaaaaou +78 Dout[6] lvc330s040daaaaaaaou +82 Dout[7] lvc330s040daaaaaaaou +34 LED lvc330s240daaaaaaaou +14 MAin[0] lvc330axxxhfaaaaaain +12 MAin[1] lvc330axxxhfaaaaaain +13 MAin[2] lvc330axxxhfaaaaaain +21 MAin[3] lvc330axxxhfaaaaaain +20 MAin[4] lvc330axxxhfaaaaaain +19 MAin[5] lvc330axxxhfaaaaaain +24 MAin[6] lvc330axxxhfaaaaaain +18 MAin[7] lvc330axxxhfaaaaaain +25 MAin[8] lvc330axxxhfaaaaaain +32 MAin[9] lvc330axxxhfaaaaaain +8 PHI2 lvc330axxxgfaaaaaain +66 RA[0] lvc330s040daaaaaaaou +64 RA[10] lvc330s040daaaaaaaou +59 RA[11] lvc330s040daaaaaaaou +67 RA[1] lvc330s040daaaaaaaou +69 RA[2] lvc330s040daaaaaaaou +71 RA[3] lvc330s040daaaaaaaou +74 RA[4] lvc330s040daaaaaaaou +70 RA[5] lvc330s040daaaaaaaou +68 RA[6] lvc330s040daaaaaaaou +75 RA[7] lvc330s040daaaaaaaou +65 RA[8] lvc330s040daaaaaaaou +63 RA[9] lvc330s040daaaaaaaou +58 RBA[0] lvc330s040daaaaaaaou +60 RBA[1] lvc330s040daaaaaaaou +53 RCKE lvc330s040daaaaaaaou +62 RCLK lvc330axxxhfaaaaaain +51 RDQMH lvc330s040daaaaaaaou +48 RDQML lvc330s040daaaaaaaou +36 RD[0] lvc330s040haaaaaaaio +37 RD[1] lvc330s040haaaaaaaio +38 RD[2] lvc330s040haaaaaaaio +39 RD[3] lvc330s040haaaaaaaio +40 RD[4] lvc330s040haaaaaaaio +41 RD[5] lvc330s040haaaaaaaio +42 RD[6] lvc330s040haaaaaaaio +43 RD[7] lvc330s040haaaaaaaio +9 nCCAS lvc330axxxffaaaaaain +17 nCRAS lvc330axxxffaaaaaain +15 nFWE lvc330axxxffaaaaaain +52 nRCAS lvc330s040daaaaaaaou +57 nRCS lvc330s040daaaaaaaou +54 nRRAS lvc330s040daaaaaaaou +49 nRWE lvc330s040daaaaaaaou +|************************************************************************ +[Model] lvc330axxxffaaaaaain +Model_type Input +Polarity Non-Inverting +Enable Active-Low +Vinl = 0.8000V +Vinh = 2.0000V +C_comp 4.2000pF 3.8000pF 7.5000pF +| +| +[Temperature Range] 25.0000 0.1050k -40.0000 +[Voltage Range] 3.3000V 3.1400V 3.4700V +[GND_clamp] +|Voltage I(typ) I(min) I(max) +| + -3.30 -0.9552A -0.9302A -0.9778A + -3.25 -0.9306A -0.9058A -0.9532A + -3.20 -0.9061A -0.8814A -0.9285A + -3.15 -0.8815A -0.857A -0.9039A + -3.10 -0.857A -0.8327A -0.8792A + -3.05 -0.8325A -0.8083A -0.8546A + -3.00 -0.808A -0.784A -0.83A + -2.95 -0.7836A -0.7597A -0.8054A + -2.90 -0.7591A -0.7355A -0.7808A + -2.85 -0.7347A -0.7112A -0.7563A + -2.80 -0.7103A -0.6871A -0.7317A + -2.75 -0.6859A -0.6629A -0.7072A + -2.70 -0.6616A -0.6388A -0.6827A + -2.65 -0.6373A -0.6148A -0.6582A + -2.60 -0.613A -0.5908A -0.6338A + -2.55 -0.5888A -0.5668A -0.6094A + -2.50 -0.5646A -0.543A -0.585A + -2.45 -0.5405A -0.5192A -0.5607A + -2.40 -0.5165A -0.4955A -0.5364A + -2.35 -0.4925A -0.4719A -0.5122A + -2.30 -0.4686A -0.4484A -0.488A + -2.25 -0.4448A -0.425A -0.4639A + -2.20 -0.4211A -0.4018A -0.4398A + -2.15 -0.3975A -0.3788A -0.4159A + -2.10 -0.3741A -0.3561A -0.3921A + -2.05 -0.3508A -0.3336A -0.3684A + -2.00 -0.3278A -0.3115A -0.3449A + -1.95 -0.3051A -0.2898A -0.3216A + -1.90 -0.2829A -0.2688A -0.2986A + -1.85 -0.2611A -0.2485A -0.276A + -1.80 -0.2402A -0.2293A -0.2541A + -1.75 -0.2203A -0.2115A -0.233A + -1.70 -0.2019A -0.1953A -0.2133A + -1.65 -0.1857A -0.1809A -0.1957A + -1.60 -0.1716A -0.1681A -0.1809A + -1.55 -0.1593A -0.1563A -0.1683A + -1.50 -0.148A -0.1451A -0.157A + -1.45 -0.1372A -0.1342A -0.146A + -1.40 -0.1266A -0.1236A -0.1353A + -1.35 -0.1162A -0.1132A -0.1248A + -1.30 -0.1059A -0.1029A -0.1145A + -1.25 -95.8482mA -92.7723mA -0.1044A + -1.20 -86.0742mA -82.8733mA -94.725mA + -1.15 -76.6252mA -73.2263mA -85.558mA + -1.10 -67.6012mA -63.8903mA -77.102mA + -1.05 -59.1382mA -54.9483mA -69.575mA + -1.00 -51.4122mA -46.5123mA -63.045mA + -0.95 -44.6112mA -38.7383mA -57.143mA + -0.90 -38.7692mA -31.8253mA -51.094mA + -0.85 -33.4342mA -25.8583mA -44.555mA + -0.80 -28.1572mA -20.5303mA -37.807mA + -0.75 -22.9772mA -15.7343mA -31.119mA + -0.70 -18.0122mA -11.5873mA -24.6550mA + -0.65 -13.3752mA -8.0973mA -18.542mA + -0.60 -9.1923mA -5.229mA -12.922mA + -0.55 -5.6276mA -2.9965mA -7.9981mA + -0.50 -2.8879mA -1.4522mA -4.077mA + -0.45 -1.1507mA -0.5766mA -1.5269mA + -0.40 -0.3444mA -0.1919mA -0.3907mA + -0.35 -83.1uA -56.964uA -74.5uA + -0.30 -17.4uA -15.6640uA -11.6uA + -0.25 -3.3000uA -4.0270uA -1.7uA + -0.20 -0.7uA -1.017uA -0.4000uA + -0.15 -0.2000uA -0.275uA -0.2000uA + -0.10 -0.1uA -89.0000nA -0.1uA + -0.05 -0.1uA -31.0nA -0.1uA + 0.00 0.0A 0.0A 0.0A + 6.60 0.0A 0.0A 0.0A +| +[POWER_clamp] +|Voltage I(typ) I(min) I(max) +| + -3.25 0.1221A 0.1248A 0.1242A + -3.15 0.1200A 0.1232A 0.1212A + -3.05 0.1178A 0.1215A 0.1181A + -2.95 0.1153A 0.1196A 0.1148A + -2.85 0.1128A 0.1174A 0.1114A + -2.75 0.1100A 0.1151A 0.1078A + -2.65 0.1071A 0.1126A 0.1041A + -2.55 0.1039A 0.1098A 0.1001A + -2.45 0.1006A 0.1069A 95.9680mA + -2.35 97.0630mA 0.1037A 91.5590mA + -2.25 93.2670mA 0.1003A 86.8480mA + -2.15 89.1920mA 96.7010mA 81.7630mA + -2.05 84.8070mA 92.8600mA 76.2010mA + -1.95 80.0800mA 88.7860mA 70.0340mA + -1.85 74.9870mA 84.4790mA 63.1570mA + -1.75 69.5180mA 79.9450mA 55.5700mA + -1.65 63.6850mA 75.1950mA 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+|************************************************************************ +| End [Component] +[End] diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt index 8aac9df..ca445fb 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt @@ -1,71 +1,71 @@ -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 * -NOTE DESIGN NAME: RAM2GS * -NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * -NOTE PIN ASSIGNMENTS * -NOTE PINS RD[0] : 36 : inout * -NOTE PINS Dout[0] : 76 : out * -NOTE PINS PHI2 : 8 : in * -NOTE PINS RDQML : 48 : out * -NOTE PINS RDQMH : 51 : out * -NOTE PINS nRCAS : 52 : out * -NOTE PINS nRRAS : 54 : out * -NOTE PINS nRWE : 49 : out * -NOTE PINS RCKE : 53 : out * -NOTE PINS RCLK : 62 : in * -NOTE PINS nRCS : 57 : out * -NOTE PINS RD[7] : 43 : inout * -NOTE PINS RD[6] : 42 : inout * -NOTE PINS RD[5] : 41 : inout * -NOTE PINS RD[4] : 40 : inout * -NOTE PINS RD[3] : 39 : inout * -NOTE PINS RD[2] : 38 : inout * -NOTE PINS RD[1] : 37 : inout * -NOTE PINS RA[11] : 59 : out * -NOTE PINS RA[10] : 64 : out * -NOTE PINS RA[9] : 63 : out * -NOTE PINS RA[8] : 65 : out * -NOTE PINS RA[7] : 75 : out * -NOTE PINS RA[6] : 68 : out * -NOTE PINS RA[5] : 70 : out * -NOTE PINS RA[4] : 74 : out * -NOTE PINS RA[3] : 71 : out * -NOTE PINS RA[2] : 69 : out * -NOTE PINS RA[1] : 67 : out * -NOTE PINS RA[0] : 66 : out * -NOTE PINS RBA[1] : 60 : out * -NOTE PINS RBA[0] : 58 : out * -NOTE PINS LED : 34 : out * -NOTE PINS nFWE : 15 : in * -NOTE PINS nCRAS : 17 : in * -NOTE PINS nCCAS : 9 : in * -NOTE PINS Dout[7] : 82 : out * -NOTE PINS Dout[6] : 78 : out * -NOTE PINS Dout[5] : 84 : out * -NOTE PINS Dout[4] : 83 : out * -NOTE PINS Dout[3] : 85 : out * -NOTE PINS Dout[2] : 87 : out * -NOTE PINS Dout[1] : 86 : out * -NOTE PINS Din[7] : 1 : in * -NOTE PINS Din[6] : 2 : in * -NOTE PINS Din[5] : 98 : in * -NOTE PINS Din[4] : 99 : in * -NOTE PINS Din[3] : 97 : in * -NOTE PINS Din[2] : 88 : in * -NOTE PINS Din[1] : 96 : in * -NOTE PINS Din[0] : 3 : in * -NOTE PINS CROW[1] : 16 : in * -NOTE PINS CROW[0] : 10 : in * -NOTE PINS MAin[9] : 32 : in * -NOTE PINS MAin[8] : 25 : in * -NOTE PINS MAin[7] : 18 : in * -NOTE PINS MAin[6] : 24 : in * -NOTE PINS MAin[5] : 19 : in * -NOTE PINS MAin[4] : 20 : in * -NOTE PINS MAin[3] : 21 : in * -NOTE PINS MAin[2] : 13 : in * -NOTE PINS MAin[1] : 12 : in * -NOTE PINS MAin[0] : 14 : in * -NOTE CONFIGURATION MODE: NONE * -NOTE COMPRESSION: on * +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Sat Aug 19 21:55:27 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS RDQML : 48 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS RCLK : 62 : in * +NOTE PINS nRCS : 57 : out * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS LED : 34 : out * +NOTE PINS nFWE : 15 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr index 69f71bd..0375507 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr @@ -1,42 +1,43 @@ ----------------------------------------------------------------------- -Report for cell RAM2GS.verilog - -Register bits: 109 of 640 (17%) -PIC Latch: 0 -I/O cells: 63 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 10 100.0 - EFB 1 100.0 - FD1P3AX 27 100.0 - FD1P3IX 3 100.0 - FD1S3AX 51 100.0 - FD1S3IX 3 100.0 - GSR 1 100.0 - IB 25 100.0 - IFS1P3DX 9 100.0 - INV 8 100.0 - OB 30 100.0 - OFS1P3BX 4 100.0 - OFS1P3DX 11 100.0 - OFS1P3JX 1 100.0 - ORCALUT4 206 100.0 - PFUMX 1 100.0 - PUR 1 100.0 - VHI 2 100.0 - VLO 2 100.0 -SUB MODULES - REFB 1 100.0 - - TOTAL 405 ----------------------------------------------------------------------- -Report for cell REFB.netlist - Instance path: ufmefb - Cell usage: - cell count Res Usage(%) - EFB 1 100.0 - VHI 1 50.0 - VLO 1 50.0 - - TOTAL 3 +---------------------------------------------------------------------- +Report for cell RAM2GS.verilog + +Register bits: 111 of 640 (17%) +PIC Latch: 0 +I/O cells: 63 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + EFB 1 100.0 + FD1P3AX 28 100.0 + FD1P3IX 2 100.0 + FD1S3AX 52 100.0 + FD1S3IX 4 100.0 + GSR 1 100.0 + IB 25 100.0 + IFS1P3DX 9 100.0 + INV 6 100.0 + OB 30 100.0 + OFS1P3BX 4 100.0 + OFS1P3DX 11 100.0 + OFS1P3JX 1 100.0 + ORCALUT4 199 100.0 + PFUMX 3 100.0 + PUR 1 100.0 + VHI 2 100.0 + VLO 2 100.0 +SUB MODULES + REFB 1 100.0 + + TOTAL 400 +---------------------------------------------------------------------- +Report for cell REFB.netlist + Instance path: ufmefb + Cell usage: + cell count Res Usage(%) + EFB 1 100.0 + ORCALUT4 1 0.5 + VHI 1 50.0 + VLO 1 50.0 + + TOTAL 4 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn index 178bb21..97908f0 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn @@ -1,86 +1,86 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:44 2023 +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sat Aug 19 21:55:24 2023 + - -Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf - -Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from LCMXO2_640HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "LCMXO2_640HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 191 Pages (128*191 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). -Initialized UFM Pages: 1 Page (Page 190). - -Total CPU Time: 1 secs -Total REAL Time: 2 secs -Peak Memory Usage: 245 MB +Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf + +Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. 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zE-{y+P?|@~WpR`~2Pze%`M|RGJKqm1fyHK6iKU=R;;+kySsF%ZIYd)XS^<)Q(n`oi3Z+#L zjY+GCxl2Rc8e*1Hp(wDHn7;&3`Ua!~O6!Q3Nuso#nCy%`phJl?>NXJbFD7jy<{lk& zn}A+HX)`hRM^O5fnER3_Z6Rh!9HsBT&Om7^*ria~M$7{$O52H<4WsluF-;An9mM=6 ziP8_m{8vTkNBA|2(ogVf2&FVJ3vrZwjusUqP}&(Ss+B@%7nIde`Xw5;IgHY;Ah8&` zqk-E}sQWD%xRI6pJsP+tg1SA?!0mCA{)h&8sVMy!4fKwo^j9F{XaAq9UuA{uy_Nk>Kl4 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t index 16daf53..1df1245 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t @@ -1,9 +1,9 @@ --w --l 5 --i 6 --n 1 --t 1 --s 1 --c 0 --e 0 --exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad index ff49f3a..8bebe2f 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad @@ -1,273 +1,273 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-640HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.39 - -Wed Aug 16 20:59:41 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | -| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | -| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | -| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3A | | | | -| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | -| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | -| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | -| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | -| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | -| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | -| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | -| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | -| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | -| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | -| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | -| 28/2 | unused, PULL:DOWN | | | PB4B | | | | -| 29/2 | unused, PULL:DOWN | | | PB4C | | | | -| 30/2 | unused, PULL:DOWN | | | PB4D | | | | -| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | -| 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | -| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | -| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | -| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | -| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | -| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | -| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | -| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | -| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | -| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | -| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | -| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | -| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | -| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | -| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | -| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | -| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | -| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | -| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | -| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | -| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | -| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | -| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | -| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | -| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | -| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | -| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "63"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "62"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "15"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:42 2023 - +PAD Specification File +*************************** + +PART TYPE: LCMXO2-640HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.39 + +Sat Aug 19 21:55:06 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | 3.3V | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | +| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | +| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3A | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | +| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | +| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | +| 28/2 | unused, PULL:DOWN | | | PB4B | | | | +| 29/2 | unused, PULL:DOWN | | | PB4C | | | | +| 30/2 | unused, PULL:DOWN | | | PB4D | | | | +| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | +| 45/2 | unused, PULL:DOWN | | | PB14A | | | | +| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | +| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | +| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | +| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | +| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | +| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | +| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | +| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | +| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | +| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | +| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | +| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | +| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "15"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sat Aug 19 21:55:09 2023 + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par index 4ca9e57..2ef15d4 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par @@ -1,264 +1,243 @@ -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:37 2023 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t -LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui --msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml - - -Preference file: LCMXO2_640HC_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 4.922 0 0.088 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" -Wed Aug 16 20:59:37 2023 - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf -Preference file: LCMXO2_640HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 63+4(JTAG)/80 84% used - 63+4(JTAG)/79 85% bonded - IOLOGIC 25/80 31% used - - SLICE 117/320 36% used - - EFB 1/1 100% used - - -Number of Signals: 380 -Number of Connections: 1008 - -Pin Constraint Summary: - 63 out of 63 pins locked (100% locked). - -The following 3 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 46) - PHI2_c (driver: PHI2, clk load #: 19) - nCRAS_c (driver: nCRAS, clk load #: 10) - -WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. - -The following 2 signals are selected to use the secondary clock routing resources: - nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) - un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10) - -WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -.............. -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 55012. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 54994 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 4 out of 80 (5%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 - SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 - SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 - - PRIMARY : 3 out of 8 (37%) - SECONDARY: 2 out of 8 (25%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. - 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. - Number of PIO comps: 63; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 3.3V | - | -| 1 | 20 / 20 (100%) | 3.3V | - | -| 2 | 12 / 20 ( 60%) | 3.3V | - | -| 3 | 18 / 20 ( 90%) | 3.3V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - -0 connections routed; 1008 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 - -Completed router resource preassignment. Real time: 5 secs - -Start NBR router at 20:59:43 08/16/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 20:59:43 08/16/23 - -Start NBR section for initial routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23 -Level 4, iteration 0 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs -Level 4, iteration 0 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs - -Start NBR section for re-routing at 20:59:44 08/16/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs - -Start NBR section for post-routing at 20:59:44 08/16/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 4.922ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 1008 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 4.922 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.088 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sat Aug 19 21:55:01 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t +LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui +-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Preference file: LCMXO2_640HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 6.966 0 0.304 0 10 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 10 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" +Sat Aug 19 21:55:01 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf +Preference file: LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 63+4(JTAG)/80 84% used + 63+4(JTAG)/79 85% bonded + IOLOGIC 25/80 31% used + + SLICE 113/320 35% used + + EFB 1/1 100% used + + +Number of Signals: 374 +Number of Connections: 978 + +Pin Constraint Summary: + 63 out of 63 pins locked (100% locked). + +The following 3 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 47) + PHI2_c (driver: PHI2, clk load #: 21) + nCRAS_c (driver: nCRAS, clk load #: 10) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +............ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.................... +Placer score = 53481. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 53406 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 4 out of 80 (5%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 + SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 + + PRIMARY : 3 out of 8 (37%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. + 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. + Number of PIO comps: 63; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 3.3V | - | +| 1 | 20 / 20 (100%) | 3.3V | - | +| 2 | 12 / 20 ( 60%) | 3.3V | - | +| 3 | 18 / 20 ( 90%) | 3.3V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 5 secs + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 978 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 8 secs + +Start NBR router at 21:55:09 08/19/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:55:09 08/19/23 + +Start NBR section for initial routing at 21:55:10 08/19/23 +Level 1, iteration 1 +0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.085ns/0.000ns; real time: 9 secs +Level 2, iteration 1 +0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.138ns/0.000ns; real time: 9 secs +Level 3, iteration 1 +0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.276ns/0.000ns; real time: 9 secs +Level 4, iteration 1 +10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:55:10 08/19/23 +Level 4, iteration 1 +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23 + +Start NBR section for re-routing at 21:55:10 08/19/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for post-routing at 21:55:10 08/19/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 6.966ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 9 secs +Total REAL time: 9 secs +Completely routed. +End of route. 978 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 6.966 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 9 secs +Total REAL time to completion: 10 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf index ed37f0e..6d8d9d3 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf @@ -1,75 +1,75 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[9]" SITE "63" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[0]" SITE "14" ; -FREQUENCY PORT "PHI2" 2.900000 MHz ; -FREQUENCY PORT "nCCAS" 2.900000 MHz ; -FREQUENCY PORT "nCRAS" 2.900000 MHz ; -FREQUENCY PORT "RCLK" 62.500000 MHz ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -COMMERCIAL ; +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "nFWE" SITE "15" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +FREQUENCY PORT "PHI2" 2.900000 MHz ; +FREQUENCY PORT "nCCAS" 2.900000 MHz ; +FREQUENCY PORT "nCRAS" 2.900000 MHz ; +FREQUENCY PORT "RCLK" 62.500000 MHz ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK 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zK*sfpZ#iDe{Et)4b$>8kea?GrIT(0<5ME<$iwZ8)o6 ztIz$u?~Z6)+~c|NeJ?(<%5^KZDaW{qzDId(bc*`kkOu9DOn>WVd!5|0>GHwf&*S&y z+h}mVyl(m4aIIF$csU1oZN7=9@>S$FkoaIuolN?@TYql{^BnjG;%0FlnzkA|XMJ;R z*92^pISQU*`{7a6Ag^-fl{Sl9B-O^2X7V@Y{?zsqoWG9~=AtdWX!%SmyJ2VW$p*Iu z4~yF>&aq!+?}4c9fjGxsxnMm5caKbzH2!5*@^zaIas5a9OWzq3b6J1(pUMEWj`#At zHXc}ycOH-djWu2MrFj3Ce}g_`n T0ssI2|NjF3B!E~7!K?rP21Ad4 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b index a0ffb20..3c08dc1 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b @@ -2,4 +2,4 @@ -g RamCfg:Reset --path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" +-path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC" diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 new file mode 100644 index 0000000..7bf1c85 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 @@ -0,0 +1,423 @@ + +Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:54:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1_map.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 158 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[2] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels. + + Constraint Details: + + 9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns + + Physical Path Details: + + Data path Din[2]_MGIOL to SLICE_10: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2] +CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37 +ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94 +ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304 +CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90 +ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7 +CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91 +ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR +CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10 +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c) + -------- + 9.223 (33.1% logic, 66.9% route), 6 logic levels. + +Report: 53.254MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 844 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 6.226ns + The internal maximum frequency of the following component is 102.312 MHz + + Logical Details: Cell type Pin name Component name + + Destination: EFB WBCLKI ufmefb/EFBInst_0 + + Delay: 9.774ns -- based on Minimum Pulse Width + + +Passed: The following path meets requirements by 6.270ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRCS_0io (to RCLK_c +) + + Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets + 16.000ns delay constraint less + 0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns + + Physical Path Details: + + Data path SLICE_16 to nRCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c) +ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0 +CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45 +ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41 +CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45 +ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0 +CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77 +ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25 +CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117 +ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn +CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c) + -------- + 9.577 (30.6% logic, 69.4% route), 6 logic levels. + +Report: 102.312MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6 + | | | +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:54:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1_map.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 158 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_10 to SLICE_10 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted +CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10 +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 844 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_12 to SLICE_12 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_12 to SLICE_12: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 + | | | +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.twr new file mode 100644 index 0000000..a09a8d7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.twr @@ -0,0 +1,2219 @@ + +Loading design for application trce from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:55:11 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 158 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 161.900ns (weighted slack = 323.800ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 10.175ns (30.0% logic, 70.0% route), 6 logic levels. + + Constraint Details: + + 10.175ns physical path delay Din[6]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.900ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_10: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c) + -------- + 10.175 (30.0% logic, 70.0% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.099ns (weighted slack = 324.198ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdValid (to PHI2_c -) + + Delay: 9.976ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.976ns physical path delay Din[6]_MGIOL to SLICE_23 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.099ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_23: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24 +ROUTE 8 0.808 R5C7A.F1 to R5C6D.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C6D.C0 to R5C6D.F0 SLICE_23 +ROUTE 1 0.000 R5C6D.F0 to R5C6D.DI0 CmdValid_r (to PHI2_c) + -------- + 9.976 (30.6% logic, 69.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R5C6D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 9.821ns (26.0% logic, 74.0% route), 5 logic levels. + + Constraint Details: + + 9.821ns physical path delay Din[6]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_18: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24 +ROUTE 8 1.148 R5C7A.F1 to R4C6C.CE XOR8MEG18 (to PHI2_c) + -------- + 9.821 (26.0% logic, 74.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R4C6C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + + Delay: 9.821ns (26.0% logic, 74.0% route), 5 logic levels. + + Constraint Details: + + 9.821ns physical path delay Din[6]_MGIOL to SLICE_25 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_25: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24 +ROUTE 8 1.148 R5C7A.F1 to R4C6A.CE XOR8MEG18 (to PHI2_c) + -------- + 9.821 (26.0% logic, 74.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_25: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R4C6A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.197ns (weighted slack = 324.394ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdValid_fast (to PHI2_c -) + + Delay: 9.878ns (30.9% logic, 69.1% route), 6 logic levels. + + Constraint Details: + + 9.878ns physical path delay Din[6]_MGIOL to SLICE_24 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.197ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_24: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24 +ROUTE 8 0.710 R5C7A.F1 to R5C7A.B0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_24 +ROUTE 1 0.000 R5C7A.F0 to R5C7A.DI0 N_36_fast (to PHI2_c) + -------- + 9.878 (30.9% logic, 69.1% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R5C7A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.260ns (weighted slack = 324.520ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[5] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 9.815ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 9.815ns physical path delay Din[5]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.260ns + + Physical Path Details: + + Data path Din[5]_MGIOL to SLICE_10: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) +ROUTE 1 1.753 IOL_T6B.IN to R4C7B.B1 Bank[5] +CTOF_DEL --- 0.495 R4C7B.B1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c) + -------- + 9.815 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[5]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_T6B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.335ns (weighted slack = 324.670ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 9.740ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 9.740ns physical path delay Din[7]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.335ns + + Physical Path Details: + + Data path Din[7]_MGIOL to SLICE_10: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.678 IOL_L2A.IN to R4C7B.D1 Bank[7] +CTOF_DEL --- 0.495 R4C7B.D1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c) + -------- + 9.740 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[7]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2A.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.452ns (weighted slack = 324.904ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.623ns (30.5% logic, 69.5% route), 6 logic levels. + + Constraint Details: + + 9.623ns physical path delay Din[6]_MGIOL to SLICE_17 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.452ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_17: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11 +ROUTE 3 0.585 R5C8D.F1 to R5C8A.M0 CmdEnable16 +MTOOFX_DEL --- 0.376 R5C8A.M0 to R5C8A.OFX0 SLICE_17 +ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.623 (30.5% logic, 69.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R5C8A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.459ns (weighted slack = 324.918ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[5] (from PHI2_c +) + Destination: FF Data in CmdValid (to PHI2_c -) + + Delay: 9.616ns (31.7% logic, 68.3% route), 6 logic levels. + + Constraint Details: + + 9.616ns physical path delay Din[5]_MGIOL to SLICE_23 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.459ns + + Physical Path Details: + + Data path Din[5]_MGIOL to SLICE_23: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) +ROUTE 1 1.753 IOL_T6B.IN to R4C7B.B1 Bank[5] +CTOF_DEL --- 0.495 R4C7B.B1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24 +ROUTE 8 0.808 R5C7A.F1 to R5C6D.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C6D.C0 to R5C6D.F0 SLICE_23 +ROUTE 1 0.000 R5C6D.F0 to R5C6D.DI0 CmdValid_r (to PHI2_c) + -------- + 9.616 (31.7% logic, 68.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[5]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_T6B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R5C6D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.465ns (weighted slack = 324.930ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in C1Submitted (to PHI2_c -) + + Delay: 9.610ns (31.8% logic, 68.2% route), 6 logic levels. + + Constraint Details: + + 9.610ns physical path delay Din[6]_MGIOL to SLICE_11 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.465ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_11: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6] +CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37 +ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94 +ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304 +CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90 +ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7 +CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11 +ROUTE 3 0.453 R5C8D.F1 to R5C8D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C8D.C0 to R5C8D.F0 SLICE_11 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_s (to PHI2_c) + -------- + 9.610 (31.8% logic, 68.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 3.539 8.PADDI to R5C8D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 47.556MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 844 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 6.226ns + The internal maximum frequency of the following component is 102.312 MHz + + Logical Details: Cell type Pin name Component name + + Destination: EFB WBCLKI ufmefb/EFBInst_0 + + Delay: 9.774ns -- based on Minimum Pulse Width + + +Passed: The following path meets requirements by 6.966ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in wb_dati[7] (to RCLK_c +) + + Delay: 8.868ns (33.0% logic, 67.0% route), 6 logic levels. + + Constraint Details: + + 8.868ns physical path delay SLICE_2 to SLICE_57 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.966ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c) +ROUTE 5 1.615 R6C5A.Q0 to R4C5D.C1 FS[15] +CTOF_DEL --- 0.495 R4C5D.C1 to R4C5D.F1 SLICE_76 +ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11 +CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109 +ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119 +CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83 +ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91 +CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81 +ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7] +CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57 +ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c) + -------- + 8.868 (33.0% logic, 67.0% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.141ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[16] (from RCLK_c +) + Destination: FF Data in wb_dati[7] (to RCLK_c +) + + Delay: 8.693ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.693ns physical path delay SLICE_2 to SLICE_57 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.141ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c) +ROUTE 5 1.440 R6C5A.Q1 to R4C5D.B1 FS[16] +CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_76 +ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11 +CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109 +ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119 +CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83 +ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91 +CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81 +ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7] +CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57 +ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c) + -------- + 8.693 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.241ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in wb_dati[7] (to RCLK_c +) + + Delay: 8.593ns (34.1% logic, 65.9% route), 6 logic levels. + + Constraint Details: + + 8.593ns physical path delay SLICE_1 to SLICE_57 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.241ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 1.340 R6C5B.Q0 to R4C5D.A1 FS[17] +CTOF_DEL --- 0.495 R4C5D.A1 to R4C5D.F1 SLICE_76 +ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11 +CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109 +ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119 +CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83 +ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91 +CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81 +ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7] +CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57 +ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c) + -------- + 8.593 (34.1% logic, 65.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C5B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.305ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRCS_0io (to RCLK_c +) + + Delay: 8.715ns (33.6% logic, 66.4% route), 6 logic levels. + + Constraint Details: + + 8.715ns physical path delay SLICE_16 to nRCS_MGIOL meets + 16.000ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.305ns + + Physical Path Details: + + Data path SLICE_16 to nRCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C11B.CLK to R5C11B.Q0 SLICE_16 (from RCLK_c) +ROUTE 9 1.105 R5C11B.Q0 to R6C10D.C0 CO0 +CTOF_DEL --- 0.495 R6C10D.C0 to R6C10D.F0 SLICE_45 +ROUTE 4 0.461 R6C10D.F0 to R6C10D.C1 N_41 +CTOF_DEL --- 0.495 R6C10D.C1 to R6C10D.F1 SLICE_45 +ROUTE 2 0.972 R6C10D.F1 to R5C11A.D0 nRRAS_5_u_i_0 +CTOF_DEL --- 0.495 R5C11A.D0 to R5C11A.F0 SLICE_77 +ROUTE 1 0.693 R5C11A.F0 to R5C10C.B1 N_25 +CTOF_DEL --- 0.495 R5C10C.B1 to R5C10C.F1 SLICE_117 +ROUTE 1 0.958 R5C10C.F1 to R6C11A.D1 N_28_i_sn +CTOF_DEL --- 0.495 R6C11A.D1 to R6C11A.F1 SLICE_88 +ROUTE 1 1.599 R6C11A.F1 to IOL_R6D.OPOS N_28_i (to RCLK_c) + -------- + 8.715 (33.6% logic, 66.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R5C11B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.243 62.PADDI to IOL_R6D.CLK RCLK_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.392ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) + + Delay: 8.269ns (81.9% logic, 18.1% route), 2 logic levels. + + Constraint Details: + + 8.269ns physical path delay ufmefb/EFBInst_0 to SLICE_47 meets + 16.000ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 15.661ns) by 7.392ns + + Physical Path Details: + + Data path ufmefb/EFBInst_0 to SLICE_47: + + Name Fanout Delay (ns) Site Resource +WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c) +ROUTE 1 1.496 EFB.WBDATO0 to R4C5B.C0 wb_dato[0] +CTOF_DEL --- 0.495 R4C5B.C0 to R4C5B.F0 SLICE_47 +ROUTE 1 0.000 R4C5B.F0 to R4C5B.DI0 n8MEGEN_6 (to RCLK_c) + -------- + 8.269 (81.9% logic, 18.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.243 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_47: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R4C5B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.416ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q InitReady (from RCLK_c +) + Destination: FF Data in wb_dati[7] (to RCLK_c +) + + Delay: 8.418ns (34.8% logic, 65.2% route), 6 logic levels. + + Constraint Details: + + 8.418ns physical path delay SLICE_31 to SLICE_57 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.416ns + + Physical Path Details: + + Data path SLICE_31 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C4D.CLK to R5C4D.Q0 SLICE_31 (from RCLK_c) +ROUTE 33 1.165 R5C4D.Q0 to R4C5D.D1 InitReady +CTOF_DEL --- 0.495 R4C5D.D1 to R4C5D.F1 SLICE_76 +ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11 +CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109 +ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119 +CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83 +ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91 +CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81 +ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7] +CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57 +ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c) + -------- + 8.418 (34.8% logic, 65.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R5C4D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.490ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) + + Delay: 8.171ns (72.9% logic, 27.1% route), 2 logic levels. + + Constraint Details: + + 8.171ns physical path delay ufmefb/EFBInst_0 to SLICE_32 meets + 16.000ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 15.661ns) by 7.490ns + + Physical Path Details: + + Data path ufmefb/EFBInst_0 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c) +ROUTE 1 2.215 EFB.WBDATO1 to R4C6D.A0 wb_dato[1] +CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 SLICE_32 +ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 LEDEN_6 (to RCLK_c) + -------- + 8.171 (72.9% logic, 27.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.243 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R4C6D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.546ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in wb_adr[1] (to RCLK_c +) + + Delay: 8.288ns (29.3% logic, 70.7% route), 5 logic levels. + + Constraint Details: + + 8.288ns physical path delay SLICE_3 to SLICE_49 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.546ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 22 2.071 R6C4D.Q0 to R4C5A.B1 FS[13] +CTOF_DEL --- 0.495 R4C5A.B1 to R4C5A.F1 SLICE_82 +ROUTE 2 0.982 R4C5A.F1 to R4C5C.A0 un1_FS_20_3 +CTOF_DEL --- 0.495 R4C5C.A0 to R4C5C.F0 SLICE_87 +ROUTE 2 0.993 R4C5C.F0 to R4C4B.A0 wb_we95 +CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_84 +ROUTE 1 1.810 R4C4B.F0 to R2C2A.A1 N_181 +CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_49 +ROUTE 1 0.000 R2C2A.F1 to R2C2A.DI1 wb_adr_5[1] (to RCLK_c) + -------- + 8.288 (29.3% logic, 70.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C4D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R2C2A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.583ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in wb_dati[6] (to RCLK_c +) + + Delay: 8.251ns (35.5% logic, 64.5% route), 6 logic levels. + + Constraint Details: + + 8.251ns physical path delay SLICE_2 to SLICE_57 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.583ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c) +ROUTE 5 1.615 R6C5A.Q0 to R4C5D.C1 FS[15] +CTOF_DEL --- 0.495 R4C5D.C1 to R4C5D.F1 SLICE_76 +ROUTE 18 1.137 R4C5D.F1 to R2C3D.D1 wb_rst11 +CTOF_DEL --- 0.495 R2C3D.D1 to R2C3D.F1 SLICE_109 +ROUTE 2 0.982 R2C3D.F1 to R2C3A.A1 N_246 +CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 SLICE_74 +ROUTE 1 0.967 R2C3A.F1 to R2C3A.A0 N_98 +CTOF_DEL --- 0.495 R2C3A.A0 to R2C3A.F0 SLICE_74 +ROUTE 1 0.623 R2C3A.F0 to R3C3A.D0 wb_dati_5_1_iv_0_1[6] +CTOF_DEL --- 0.495 R3C3A.D0 to R3C3A.F0 SLICE_57 +ROUTE 1 0.000 R3C3A.F0 to R3C3A.DI0 wb_dati_5[6] (to RCLK_c) + -------- + 8.251 (35.5% logic, 64.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.586ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRCS_0io (to RCLK_c +) + + Delay: 8.434ns (28.8% logic, 71.2% route), 5 logic levels. + + Constraint Details: + + 8.434ns physical path delay SLICE_34 to nRCS_MGIOL meets + 16.000ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.586ns + + Physical Path Details: + + Data path SLICE_34 to nRCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_34 (from RCLK_c) +ROUTE 10 1.972 R6C7A.Q1 to R5C11C.A1 RASr2 +CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_63 +ROUTE 7 0.780 R5C11C.F1 to R5C11A.C0 N_250 +CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_77 +ROUTE 1 0.693 R5C11A.F0 to R5C10C.B1 N_25 +CTOF_DEL --- 0.495 R5C10C.B1 to R5C10C.F1 SLICE_117 +ROUTE 1 0.958 R5C10C.F1 to R6C11A.D1 N_28_i_sn +CTOF_DEL --- 0.495 R6C11A.D1 to R6C11A.F1 SLICE_88 +ROUTE 1 1.599 R6C11A.F1 to IOL_R6D.OPOS N_28_i (to RCLK_c) + -------- + 8.434 (28.8% logic, 71.2% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.070 62.PADDI to R6C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 3.243 62.PADDI to IOL_R6D.CLK RCLK_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 102.312MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.556 MHz| 6 + | | | +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:55:11 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 158 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_10 to SLICE_10 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.132 R4C8D.Q0 to R4C8D.A0 ADSubmitted +CTOF_DEL --- 0.101 R4C8D.A0 to R4C8D.F0 SLICE_10 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdUFMShift_fast (from PHI2_c -) + Destination: FF Data in CmdUFMShift_fast (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_21 to SLICE_21 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_21 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.132 R5C6B.Q0 to R5C6B.A0 CmdUFMShift_fast +CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_21 +ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 CmdUFMShift_3_fast (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdUFMWrite (from PHI2_c -) + Destination: FF Data in CmdUFMWrite (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_22 to SLICE_22 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_22 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_22 (from PHI2_c) +ROUTE 2 0.132 R5C6A.Q0 to R5C6A.A0 CmdUFMWrite +CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_22 +ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 CmdUFMWrite_3 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_46 to SLICE_46 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_46 to SLICE_46: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C7C.CLK to R5C7C.Q0 SLICE_46 (from PHI2_c) +ROUTE 2 0.132 R5C7C.Q0 to R5C7C.A0 XOR8MEG +CTOF_DEL --- 0.101 R5C7C.A0 to R5C7C.F0 SLICE_46 +ROUTE 1 0.000 R5C7C.F0 to R5C7C.DI0 XOR8MEG_3 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_46: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_46: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.380ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdUFMShift (from PHI2_c -) + Destination: FF Data in CmdUFMShift (to PHI2_c -) + + Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels. + + Constraint Details: + + 0.367ns physical path delay SLICE_20 to SLICE_20 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.380ns + + Physical Path Details: + + Data path SLICE_20 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C6C.CLK to R5C6C.Q0 SLICE_20 (from PHI2_c) +ROUTE 3 0.133 R5C6C.Q0 to R5C6C.A0 CmdUFMShift +CTOF_DEL --- 0.101 R5C6C.A0 to R5C6C.F0 SLICE_20 +ROUTE 1 0.000 R5C6C.F0 to R5C6C.DI0 CmdUFMShift_3 (to PHI2_c) + -------- + 0.367 (63.8% logic, 36.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C6C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.435ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.422ns (68.5% logic, 31.5% route), 2 logic levels. + + Constraint Details: + + 0.422ns physical path delay SLICE_17 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.435ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c) +ROUTE 4 0.133 R5C8A.Q0 to R5C8A.A0 CmdEnable +CTOOFX_DEL --- 0.156 R5C8A.A0 to R5C8A.OFX0 SLICE_17 +ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.422 (68.5% logic, 31.5% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.471ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in C1Submitted (to PHI2_c -) + + Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels. + + Constraint Details: + + 0.458ns physical path delay SLICE_11 to SLICE_11 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.471ns + + Physical Path Details: + + Data path SLICE_11 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.224 R5C8D.Q0 to R5C8D.B0 C1Submitted +CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_11 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_s (to PHI2_c) + -------- + 0.458 (51.1% logic, 48.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.527ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.514ns (56.2% logic, 43.8% route), 2 logic levels. + + Constraint Details: + + 0.514ns physical path delay SLICE_17 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.527ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c) +ROUTE 4 0.225 R5C8A.Q0 to R5C8A.B1 CmdEnable +CTOOFX_DEL --- 0.156 R5C8A.B1 to R5C8A.OFX0 SLICE_17 +ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.514 (56.2% logic, 43.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.550ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.537ns (53.8% logic, 46.2% route), 2 logic levels. + + Constraint Details: + + 0.537ns physical path delay SLICE_10 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.550ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.248 R4C8D.Q0 to R5C8A.D1 ADSubmitted +CTOOFX_DEL --- 0.156 R5C8A.D1 to R5C8A.OFX0 SLICE_17 +ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.537 (53.8% logic, 46.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.550ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.522ns (44.8% logic, 55.2% route), 2 logic levels. + + Constraint Details: + + 0.522ns physical path delay SLICE_17 to SLICE_46 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.550ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_46: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c) +ROUTE 4 0.142 R5C8A.Q0 to R5C7A.C1 CmdEnable +CTOF_DEL --- 0.101 R5C7A.C1 to R5C7A.F1 SLICE_24 +ROUTE 8 0.146 R5C7A.F1 to R5C7C.CE XOR8MEG18 (to PHI2_c) + -------- + 0.522 (44.8% logic, 55.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_46: + + Name Fanout Delay (ns) Site Resource +ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 844 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_12 to SLICE_12 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_12 to SLICE_12: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 0.152 R5C9A.Q0 to R5C9A.M1 CASr (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_12: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_12: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr2 (from RCLK_c +) + Destination: FF Data in CASr3 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_12 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_12 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q1 SLICE_12 (from RCLK_c) +ROUTE 4 0.154 R5C9A.Q1 to R5C9D.M0 CASr2 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_12: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R5C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_34 to SLICE_34 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_34 to SLICE_34: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C7A.CLK to R6C7A.Q0 SLICE_34 (from RCLK_c) +ROUTE 2 0.154 R6C7A.Q0 to R6C7A.M1 RASr (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C7A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C7A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.313ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[6] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets + -0.060ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.006ns) by 0.313ns + + Physical Path Details: + + Data path SLICE_52 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q0 SLICE_52 (from RCLK_c) +ROUTE 2 0.174 R2C2C.Q0 to EFB.WBADRI6 wb_adr[6] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R2C2C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.318ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[7] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels. + + Constraint Details: + + 0.304ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets + -0.068ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.014ns) by 0.318ns + + Physical Path Details: + + Data path SLICE_52 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q1 SLICE_52 (from RCLK_c) +ROUTE 1 0.171 R2C2C.Q1 to EFB.WBADRI7 wb_adr[7] (to RCLK_c) + -------- + 0.304 (43.8% logic, 56.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R2C2C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.334ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[2] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets + -0.081ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.027ns) by 0.334ns + + Physical Path Details: + + Data path SLICE_50 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2B.CLK to R2C2B.Q0 SLICE_50 (from RCLK_c) +ROUTE 2 0.174 R2C2B.Q0 to EFB.WBADRI2 wb_adr[2] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R2C2B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.355ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[1] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_49 to ufmefb/EFBInst_0 meets + -0.102ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.048ns) by 0.355ns + + Physical Path Details: + + Data path SLICE_49 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2A.CLK to R2C2A.Q1 SLICE_49 (from RCLK_c) +ROUTE 2 0.174 R2C2A.Q1 to EFB.WBADRI1 wb_adr[1] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R2C2A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[0] (from RCLK_c +) + Destination: FF Data in FS[0] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_0 to SLICE_0 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C3A.CLK to R6C3A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R6C3A.Q1 to R6C3A.A1 FS[0] +CTOF_DEL --- 0.101 R6C3A.A1 to R6C3A.F1 SLICE_0 +ROUTE 1 0.000 R6C3A.F1 to R6C3A.DI1 FS_s[0] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in FS[17] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_1 to SLICE_1 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_1: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 0.132 R6C5B.Q0 to R6C5B.A0 FS[17] +CTOF_DEL --- 0.101 R6C5B.A0 to R6C5B.F0 SLICE_1 +ROUTE 1 0.000 R6C5B.F0 to R6C5B.DI0 FS_s[17] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C5B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C5B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[16] (from RCLK_c +) + Destination: FF Data in FS[16] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_2 to SLICE_2 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_2: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c) +ROUTE 5 0.132 R6C5A.Q1 to R6C5A.A1 FS[16] +CTOF_DEL --- 0.101 R6C5A.A1 to R6C5A.F1 SLICE_2 +ROUTE 1 0.000 R6C5A.F1 to R6C5A.DI1 FS_s[16] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 47 1.059 62.PADDI to R6C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 + | | | +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html index 6dee59f..0f52c2a 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html @@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:58:50 2023 +Sat Aug 19 21:55:24 2023 -Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf +Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. Design name: RAM2GS @@ -91,9 +91,9 @@ UFM Utilization: General Purpose Flash Memory. Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). Initialized UFM Pages: 1 Page (Page 190). -Total CPU Time: 1 secs -Total REAL Time: 2 secs -Peak Memory Usage: 246 MB +Total CPU Time: 3 secs +Total REAL Time: 3 secs +Peak Memory Usage: 266 MB diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt index 5aedfac..d15cb52 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt @@ -1,153 +1,153 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 - -# Written on Wed Aug 16 20:59:31 2023 - -##### DESIGN INFO ####################################################### - -Top View: "RAM2GS" -Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" - - - - -##### SUMMARY ############################################################ - -Found 0 issues in 0 out of 4 constraints - - -##### DETAILS ############################################################ - - - -Clock Relationships -******************* - -Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------ -System RCLK | 16.000 | No paths | No paths | No paths -RCLK System | 16.000 | No paths | No paths | No paths -RCLK RCLK | 16.000 | No paths | No paths | No paths -RCLK PHI2 | 2.000 | No paths | 1.000 | No paths -RCLK nCRAS | No paths | No paths | 1.000 | No paths -PHI2 RCLK | No paths | No paths | No paths | 1.000 -PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000 -nCRAS RCLK | No paths | No paths | No paths | 1.000 -=================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - -@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. -@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. -@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. -@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. -@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. - - -Unconstrained Start/End Points -****************************** - -p:CROW[0] -p:CROW[1] -p:Din[0] -p:Din[1] -p:Din[2] -p:Din[3] -p:Din[4] -p:Din[5] -p:Din[6] -p:Din[7] -p:Dout[0] -p:Dout[1] -p:Dout[2] -p:Dout[3] -p:Dout[4] -p:Dout[5] -p:Dout[6] -p:Dout[7] -p:MAin[0] -p:MAin[1] -p:MAin[2] -p:MAin[3] -p:MAin[4] -p:MAin[5] -p:MAin[6] -p:MAin[7] -p:MAin[8] -p:MAin[9] -p:RA[0] -p:RA[1] -p:RA[2] -p:RA[3] -p:RA[4] -p:RA[5] -p:RA[6] -p:RA[7] -p:RA[8] -p:RA[9] -p:RA[10] -p:RA[11] -p:RBA[0] -p:RBA[1] -p:RCKE -p:RDQMH -p:RDQML -p:RD[0] (bidir end point) -p:RD[0] (bidir start point) -p:RD[1] (bidir end point) -p:RD[1] (bidir start point) -p:RD[2] (bidir end point) -p:RD[2] (bidir start point) -p:RD[3] (bidir end point) -p:RD[3] (bidir start point) -p:RD[4] (bidir end point) -p:RD[4] (bidir start point) -p:RD[5] (bidir end point) -p:RD[5] (bidir start point) -p:RD[6] (bidir end point) -p:RD[6] (bidir start point) -p:RD[7] (bidir end point) -p:RD[7] (bidir start point) -p:nFWE -p:nRCAS -p:nRCS -p:nRRAS -p:nRWE - - -Inapplicable constraints -************************ - -(none) - - -Applicable constraints with issues -********************************** - -(none) - - -Constraints with matching wildcard expressions -********************************************** - -(none) - - -Library Report -************** - - -# End of Constraint Checker Report + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Sat Aug 19 21:54:51 2023 + +##### DESIGN INFO ####################################################### + +Top View: "RAM2GS" +Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc" + + + + +##### SUMMARY ############################################################ + +Found 0 issues in 0 out of 4 constraints + + +##### DETAILS ############################################################ + + + +Clock Relationships +******************* + +Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise +----------------------------------------------------------------------------------------------------------------------------------- +System RCLK | 16.000 | No paths | No paths | No paths +RCLK System | 16.000 | No paths | No paths | No paths +RCLK RCLK | 16.000 | No paths | No paths | No paths +RCLK PHI2 | 2.000 | No paths | 1.000 | No paths +RCLK nCRAS | No paths | No paths | 1.000 | No paths +PHI2 RCLK | No paths | No paths | No paths | 1.000 +PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000 +nCRAS RCLK | No paths | No paths | No paths | 1.000 +=================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + +@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + +Unconstrained Start/End Points +****************************** + +p:CROW[0] +p:CROW[1] +p:Din[0] +p:Din[1] +p:Din[2] +p:Din[3] +p:Din[4] +p:Din[5] +p:Din[6] +p:Din[7] +p:Dout[0] +p:Dout[1] +p:Dout[2] +p:Dout[3] +p:Dout[4] +p:Dout[5] +p:Dout[6] +p:Dout[7] +p:MAin[0] +p:MAin[1] +p:MAin[2] +p:MAin[3] +p:MAin[4] +p:MAin[5] +p:MAin[6] +p:MAin[7] +p:MAin[8] +p:MAin[9] +p:RA[0] +p:RA[1] +p:RA[2] +p:RA[3] +p:RA[4] +p:RA[5] +p:RA[6] +p:RA[7] +p:RA[8] +p:RA[9] +p:RA[10] +p:RA[11] +p:RBA[0] +p:RBA[1] +p:RCKE +p:RDQMH +p:RDQML +p:RD[0] (bidir end point) +p:RD[0] (bidir start point) +p:RD[1] (bidir end point) +p:RD[1] (bidir start point) +p:RD[2] (bidir end point) +p:RD[2] (bidir start point) +p:RD[3] (bidir end point) +p:RD[3] (bidir start point) +p:RD[4] (bidir end point) +p:RD[4] (bidir start point) +p:RD[5] (bidir end point) +p:RD[5] (bidir start point) +p:RD[6] (bidir end point) +p:RD[6] (bidir start point) +p:RD[7] (bidir end point) +p:RD[7] (bidir start point) +p:nFWE +p:nRCAS +p:nRCS +p:nRRAS +p:nRWE + + +Inapplicable constraints +************************ + +(none) + + +Applicable constraints with issues +********************************** + +(none) + + +Constraints with matching wildcard expressions +********************************************** + +(none) + + +Library Report +************** + + +# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db index 68c8b1be4eeab82248bb01d1eddae9b111a88823..ab2dd1ce06d2bcfd6c502589a56da0843bfc2a18 100644 GIT binary patch delta 179 zcmZp0XmHrTCcrb9fj^LMA@3(%XP(I$3mbWa8+BRPdE*;PrJ0l}t@Mjh3-XI6FOZX* zY#^&Wd74bPs8&s*4hu*{F{X+}uq-nc*;ybNT_&t1f01nh>tn>C4`i>w1{Tp delta 264 zcmZp0XmHrTCcvY`z;DA>!MmB~J&)GLLJ1y?MkiJd-bVJuQfVfo6f6DwywsGU%(7Jd zl>Fq<+|<01V*T{Yl8n-%$;)JBYl-}6bYuZ5FD9fsOm-GXxf3&Srf-phn9f9;>8x^K U(;XR!QywPkIeD#oAd|=+0PO8q!2kdN diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_fpga_mapper.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_fpga_mapper.htm new file mode 100644 index 0000000..9b9d704 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_fpga_mapper.htm @@ -0,0 +1,9 @@ + + + syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_iotiming.html new file mode 100644 index 0000000..a046d86 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_iotiming.html @@ -0,0 +1,200 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Sat Aug 19 21:55:13 2023
+// M: Minimum Performance Grade
+// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     2.553      4      -0.117     M
+CROW[1] nCRAS F     2.019      4       0.001     M
+Din[0]  PHI2  F     4.715      4       3.636     4
+Din[0]  nCCAS F     0.790      4       0.535     4
+Din[1]  PHI2  F     5.021      4       3.516     4
+Din[1]  nCCAS F     1.086      4       0.264     4
+Din[2]  PHI2  F     3.385      4       3.516     4
+Din[2]  nCCAS F     0.282      4       0.948     4
+Din[3]  PHI2  F     4.644      4       3.516     4
+Din[3]  nCCAS F     1.278      4       0.095     4
+Din[4]  PHI2  F     4.335      4       3.516     4
+Din[4]  nCCAS F     2.446      4      -0.199     M
+Din[5]  PHI2  F     3.662      4       3.516     4
+Din[5]  nCCAS F     0.907      4       0.402     4
+Din[6]  PHI2  F     4.869      4       3.636     4
+Din[6]  nCCAS F     1.378      4       0.023     M
+Din[7]  PHI2  F     4.138      4       3.636     4
+Din[7]  nCCAS F     2.072      4      -0.120     M
+MAin[0] PHI2  F     5.613      4       0.006     M
+MAin[0] nCRAS F     0.244      4       1.146     4
+MAin[1] PHI2  F     3.409      4       0.354     6
+MAin[1] nCRAS F     0.244      4       1.146     4
+MAin[2] PHI2  F     5.391      4       0.132     M
+MAin[2] nCRAS F     0.250      4       1.141     4
+MAin[3] PHI2  F     4.627      4       0.087     M
+MAin[3] nCRAS F     0.507      4       0.910     4
+MAin[4] PHI2  F     5.665      4      -0.133     M
+MAin[4] nCRAS F     0.675      4       0.777     4
+MAin[5] PHI2  F     5.569      4       0.129     M
+MAin[5] nCRAS F     0.050      4       1.238     4
+MAin[6] PHI2  F     5.717      4      -0.141     M
+MAin[6] nCRAS F     0.242      4       1.146     4
+MAin[7] PHI2  F     5.943      4      -0.173     M
+MAin[7] nCRAS F     0.170      4       1.228     4
+MAin[8] nCRAS F     0.759      4       0.696     4
+MAin[9] nCRAS F     0.516      4       0.891     4
+PHI2    RCLK  R    -0.312      M       3.167     4
+nCCAS   RCLK  R     2.600      4      -0.176     M
+nCCAS   nCRAS F     3.106      4      -0.235     M
+nCRAS   RCLK  R     1.803      4      -0.055     M
+nFWE    PHI2  F     4.680      4       0.261     M
+nFWE    nCRAS F     2.234      4       1.143     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     9.922         4        2.878          M
+LED    nCRAS F    10.555         4        3.057          M
+RA[0]  RCLK  R    11.638         4        3.406          M
+RA[0]  nCRAS F    11.771         4        3.430          M
+RA[10] RCLK  R     8.141         4        2.620          M
+RA[11] PHI2  R     8.610         4        2.756          M
+RA[1]  RCLK  R    11.674         4        3.407          M
+RA[1]  nCRAS F    10.635         4        3.155          M
+RA[2]  RCLK  R    12.933         4        3.729          M
+RA[2]  nCRAS F    11.858         4        3.449          M
+RA[3]  RCLK  R    12.587         4        3.664          M
+RA[3]  nCRAS F    11.255         4        3.298          M
+RA[4]  RCLK  R    11.721         4        3.433          M
+RA[4]  nCRAS F    11.153         4        3.297          M
+RA[5]  RCLK  R    12.544         4        3.620          M
+RA[5]  nCRAS F    11.480         4        3.360          M
+RA[6]  RCLK  R    12.984         4        3.775          M
+RA[6]  nCRAS F    11.528         4        3.407          M
+RA[7]  RCLK  R    12.553         4        3.625          M
+RA[7]  nCRAS F    11.610         4        3.368          M
+RA[8]  RCLK  R    11.836         4        3.453          M
+RA[8]  nCRAS F    10.797         4        3.201          M
+RA[9]  RCLK  R    11.182         4        3.271          M
+RA[9]  nCRAS F    11.135         4        3.279          M
+RBA[0] nCRAS F     8.439         4        2.703          M
+RBA[1] nCRAS F     8.439         4        2.703          M
+RCKE   RCLK  R    10.083         4        3.081          M
+RDQMH  RCLK  R    11.381         4        3.325          M
+RDQML  RCLK  R    10.735         4        3.173          M
+RD[0]  nCCAS F     8.223         4        2.594          M
+RD[1]  nCCAS F     8.223         4        2.594          M
+RD[2]  nCCAS F     8.223         4        2.594          M
+RD[3]  nCCAS F     8.223         4        2.594          M
+RD[4]  nCCAS F     8.223         4        2.594          M
+RD[5]  nCCAS F     8.223         4        2.594          M
+RD[6]  nCCAS F     8.223         4        2.594          M
+RD[7]  nCCAS F     8.223         4        2.594          M
+nRCAS  RCLK  R     8.141         4        2.620          M
+nRCS   RCLK  R     8.141         4        2.620          M
+nRRAS  RCLK  R     8.141         4        2.620          M
+nRWE   RCLK  R     8.121         4        2.627          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
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+ + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd index 165a86f..1f334b9 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd @@ -1,24 +1,24 @@ -[ActiveSupport MAP] -Device = LCMXO2-640HC; -Package = TQFP100; -Performance = 4; -LUTS_avail = 640; -LUTS_used = 230; -FF_avail = 719; -FF_used = 109; -INPUT_LVCMOS33 = 25; -OUTPUT_LVCMOS33 = 30; -BIDI_LVCMOS33 = 8; -IO_avail = 79; -IO_used = 63; -EBR_avail = 2; -EBR_used = 0; -; -; start of EFB statistics -I2C = 0; -SPI = 0; -TimerCounter = 0; -UFM = 1; -PLL = 0; -; end of EFB statistics -; +[ActiveSupport MAP] +Device = LCMXO2-640HC; +Package = TQFP100; +Performance = 4; +LUTS_avail = 640; +LUTS_used = 222; +FF_avail = 719; +FF_used = 111; +INPUT_LVCMOS33 = 25; +OUTPUT_LVCMOS33 = 30; +BIDI_LVCMOS33 = 8; +IO_avail = 79; +IO_used = 63; +EBR_avail = 2; +EBR_used = 0; +; +; start of EFB statistics +I2C = 0; +SPI = 0; +TimerCounter = 0; +UFM = 1; +PLL = 0; +; end of EFB statistics +; diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam index b49ff9d..7e9e945 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam @@ -1,145 +1,144 @@ -[ START MERGED ] -RASr2_i RASr2 -XOR8MEG.CN PHI2_c -nCRAS_c_i nCRAS_c -InitReady_i InitReady -[ END MERGED ] -[ START CLIPPED ] -GND -ufmefb/VCC -ufmefb/GND -FS_s_0_S1[17] -FS_s_0_COUT[17] -ufmefb/CFGSTDBY -ufmefb/CFGWAKE -ufmefb/wbc_ufm_irq -ufmefb/TCOC -ufmefb/TCINT -ufmefb/SPIIRQO -ufmefb/SPICSNEN -ufmefb/SPIMCSN7 -ufmefb/SPIMCSN6 -ufmefb/SPIMCSN5 -ufmefb/SPIMCSN4 -ufmefb/SPIMCSN3 -ufmefb/SPIMCSN2 -ufmefb/SPIMCSN1 -ufmefb/SPIMCSN0 -ufmefb/SPIMOSIEN -ufmefb/SPIMOSIO -ufmefb/SPIMISOEN -ufmefb/SPIMISOO -ufmefb/SPISCKEN -ufmefb/SPISCKO -ufmefb/I2C2IRQO -ufmefb/I2C1IRQO -ufmefb/I2C2SDAOEN -ufmefb/I2C2SDAO -ufmefb/I2C2SCLOEN -ufmefb/I2C2SCLO -ufmefb/I2C1SDAOEN -ufmefb/I2C1SDAO -ufmefb/I2C1SCLOEN -ufmefb/I2C1SCLO -ufmefb/PLLDATO0 -ufmefb/PLLDATO1 -ufmefb/PLLDATO2 -ufmefb/PLLDATO3 -ufmefb/PLLDATO4 -ufmefb/PLLDATO5 -ufmefb/PLLDATO6 -ufmefb/PLLDATO7 -ufmefb/PLLADRO0 -ufmefb/PLLADRO1 -ufmefb/PLLADRO2 -ufmefb/PLLADRO3 -ufmefb/PLLADRO4 -ufmefb/PLLWEO -ufmefb/PLL1STBO -ufmefb/PLL0STBO -ufmefb/PLLRSTO -ufmefb/PLLCLKO -ufmefb/wb_ack_o -ufmefb/wb_dat_o_1[2] -ufmefb/wb_dat_o_1[3] -ufmefb/wb_dat_o_1[4] -ufmefb/wb_dat_o_1[5] -ufmefb/wb_dat_o_1[6] -ufmefb/wb_dat_o_1[7] -FS_cry_0_S0[0] -N_1 -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[9]" SITE "63" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[0]" SITE "14" ; -FREQUENCY PORT "PHI2" 2.900000 MHz ; -FREQUENCY PORT "nCCAS" 2.900000 MHz ; -FREQUENCY PORT "nCRAS" 2.900000 MHz ; -FREQUENCY PORT "RCLK" 62.500000 MHz ; -SCHEMATIC END ; -[ END DESIGN PREFS ] +[ START MERGED ] +RASr2_i RASr2 +XOR8MEG.CN PHI2_c +XOR8MEG_3_u_0_am XOR8MEG +nCRAS_c_i nCRAS_c +[ END MERGED ] +[ START CLIPPED ] +GND +ufmefb/VCC +ufmefb/GND +FS_s_0_S1[17] +FS_s_0_COUT[17] +ufmefb/CFGSTDBY +ufmefb/CFGWAKE +ufmefb/wbc_ufm_irq +ufmefb/TCOC +ufmefb/TCINT +ufmefb/SPIIRQO +ufmefb/SPICSNEN +ufmefb/SPIMCSN7 +ufmefb/SPIMCSN6 +ufmefb/SPIMCSN5 +ufmefb/SPIMCSN4 +ufmefb/SPIMCSN3 +ufmefb/SPIMCSN2 +ufmefb/SPIMCSN1 +ufmefb/SPIMCSN0 +ufmefb/SPIMOSIEN +ufmefb/SPIMOSIO +ufmefb/SPIMISOEN +ufmefb/SPIMISOO +ufmefb/SPISCKEN +ufmefb/SPISCKO +ufmefb/I2C2IRQO +ufmefb/I2C1IRQO +ufmefb/I2C2SDAOEN +ufmefb/I2C2SDAO +ufmefb/I2C2SCLOEN +ufmefb/I2C2SCLO +ufmefb/I2C1SDAOEN +ufmefb/I2C1SDAO +ufmefb/I2C1SCLOEN +ufmefb/I2C1SCLO +ufmefb/PLLDATO0 +ufmefb/PLLDATO1 +ufmefb/PLLDATO2 +ufmefb/PLLDATO3 +ufmefb/PLLDATO4 +ufmefb/PLLDATO5 +ufmefb/PLLDATO6 +ufmefb/PLLDATO7 +ufmefb/PLLADRO0 +ufmefb/PLLADRO1 +ufmefb/PLLADRO2 +ufmefb/PLLADRO3 +ufmefb/PLLADRO4 +ufmefb/PLLWEO +ufmefb/PLL1STBO +ufmefb/PLL0STBO +ufmefb/PLLRSTO +ufmefb/PLLCLKO +ufmefb/wb_dat_o_1[2] +ufmefb/wb_dat_o_1[3] +ufmefb/wb_dat_o_1[4] +ufmefb/wb_dat_o_1[5] +ufmefb/wb_dat_o_1[6] +ufmefb/wb_dat_o_1[7] +FS_cry_0_S0[0] +N_1 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "nFWE" SITE "15" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +FREQUENCY PORT "PHI2" 2.900000 MHz ; +FREQUENCY PORT "nCCAS" 2.900000 MHz ; +FREQUENCY PORT "nCRAS" 2.900000 MHz ; +FREQUENCY PORT "RCLK" 62.500000 MHz ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr index b4bdefa..3c4bcec 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr @@ -1,20 +1,22 @@ ---------------------------------------------------- -Report for cell RAM2GS - Instance path: RAM2GS - Cell usage: - cell count Res Usage(%) - SLIC 117.00 100.0 - IOLGC 25.00 100.0 - LUT4 210.00 100.0 - IOREG 25 100.0 - IOBUF 63 100.0 - PFUREG 84 100.0 - RIPPLE 10 100.0 -SUB MODULES - cell count SLC Usage(%) - REFB 1 0.0 ---------------------------------------------------- -Report for cell REFB - Instance path: RAM2GS/ufmefb - Cell usage: - cell count Res Usage(%) +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 113.00 100.0 + IOLGC 25.00 100.0 + LUT4 202.00 100.0 + IOREG 25 100.0 + IOBUF 63 100.0 + PFUREG 86 100.0 + RIPPLE 10 100.0 +SUB MODULES + cell count SLC Usage(%) + REFB 1 0.4 +--------------------------------------------------- +Report for cell REFB + Instance path: RAM2GS/ufmefb + Cell usage: + cell count Res Usage(%) + SLIC 0.50 0.4 + LUT4 1.00 0.5 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd index 3f6e410165244f7092dee557170e1c7731639d6a..1caa63a1cb9766ac3f2de33740bfe670d549ad2e 100644 GIT binary patch literal 193033 zcmeHw34mNxm3CEcqyqtp&IS?Efh24q*s>`o zq9O`zi2E)oZn*EtxQydC?vBgvHjbl?vpLR8{YaD)x#ymH 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z)5?zZEG?_(SC8mggZNE!X~OMZmuc}5-?Nn$B~j>cSp18Ig=o;=69d(AVxVR%@u;kr zPiPRaR=q3A)w{wn-i7ay`3fN=j z^PD@@x{fC#cVTIADPqc?E_(d$o2(E!%~R6F>GdoPNIBo33NQCkrd_mQ%aFUDbHrJ# zs8SxqURE6^8g*zT8kHq=qYW@EB8_X| zccgVolWbfWw&c`aY*0m#O6x>e#)}*&(&bRA`vEPkocdBt8Yfak(%%>>;bB!;>HM~u zwn)k-H6pA?Aj@D9mNoq-^5?7#+c6zQiZ&VFDXOIF(JGgOCQp8=Or83(v(yc8EK6%$ z+@S5HNNGM)>-r)|EJG&;{d)Dub!nem;#pb>QWZi7#$Hrm?vw>ayaGr(A^=idB4vuN zQ(A@-J7QE#l>^!u55h8$6`BgOH|kUWO`UqYFQe+xk+@hdrcRORrtSTQbMHlOYWtxn%O00GFfb4EnsZ&X@QkDjc zO8*!mH0Usa1i$6?sGh6Srk&+k#&K!W3a+SoRiBhgYq{w48Si05Bmocaz(M0~RAn;$ zR%HTiQ^=L@wF*ERyuFxwII4s_+pS9GMwBEJ Khf40h|NjHH "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_cry_0_0: ccu2B0 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out) + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_s_0_17: ccu20001 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_15: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_13: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_11: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_9: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_7: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_5: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_3: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_1: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"00F2") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + CmdEnable17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + ADSubmitted_r: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + begin + INST10: ROM16X1A + generic map (initval => X"F2F2") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_11 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_11 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_11"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_11 : ENTITY IS TRUE; + + end SLICE_11; + + architecture Structure of SLICE_11 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable16: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + C1Submitted_s: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + C1Submitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_12 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_12 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_12"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_12 : ENTITY IS TRUE; + + end SLICE_12; + + architecture Structure of SLICE_12 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nCCAS_pad_RNISUR8: lut40005 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + begin + INST10: ROM16X1A + generic map (initval => X"DDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0008 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0008 : ENTITY IS TRUE; + + end vmuxregsre0008; + + architecture Structure of vmuxregsre0008 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3_2: lut40006 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_RNO_0: lut40007 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_0: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"AC8C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_17 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_17 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_17"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE; + + end SLICE_17; + + architecture Structure of SLICE_17 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_17_SLICE_17_K1_H1: Std_logic; + signal SLICE_17_CmdEnable_s_GATE_H0: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_17_K1: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, + Z=>SLICE_17_SLICE_17_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdEnable_s_GATE: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_17_CmdEnable_s_GATE_H0); + CmdEnable: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + SLICE_17_K0K1MUX: selmux2 + port map (D0=>SLICE_17_CmdEnable_s_GATE_H0, D1=>SLICE_17_SLICE_17_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"ACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdLEDEN_4_0: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdLEDEN_4_u: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + CmdLEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"030A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMShift_3_u: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMShift: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_21 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_21 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_21"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE; + + end SLICE_21; + + architecture Structure of SLICE_21 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMShift_3_u_fast: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMShift_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"0C0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_22 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_22 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_22"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE; + + end SLICE_22; + + architecture Structure of SLICE_22 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMWrite_2: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMWrite_3_u: lut40015 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMWrite: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"A8A8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG11: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdValid_r: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdValid: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG18: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdValid_r_fast: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + CmdValid_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"3A3A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"E2E2") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Cmdn8MEGEN_4_0: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_4_u: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Cmdn8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nCCAS_pad_RNI01SJ: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nFWE_pad_RNI420B: lut40005 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + FWEr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"FFF7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"A9A9") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_28 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_28 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_28"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_28 : ENTITY IS TRUE; + + end SLICE_28; + + architecture Structure of SLICE_28 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_0io_RNO: lut40022 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_RNO_0: lut40023 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"7878") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"6666") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_29 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_29 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_29"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE; + + end SLICE_29; + + architecture Structure of SLICE_29 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_RNO_2: lut40024 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_n1_0_x2: lut40025 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"6AAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_2_sqmuxa_0_o2: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_RNO_3: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + InitReady3_0_a3: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + InitReady_RNO: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"B8B8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LEDEN_6: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LED_pad_RNO: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr_RNO: lut40005 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"1111") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_4: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + PHI2r2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"5072") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + begin + INST10: ROM16X1A + generic map (initval => X"DCCC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_8_u_RNO: lut40030 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKEEN_8_u: lut40031 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RCKEEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"FE30") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_Bank_1_4: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKE_2_0: lut40033 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RCKE: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"7F7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"AEAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_38 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_38 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_38"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE; + + end SLICE_38; + + architecture Structure of SLICE_38 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_o2: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_RNO: lut40035 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Ready: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_39 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_39 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_39"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE; + + end SLICE_39; + + architecture Structure of SLICE_39 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3: lut40036 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + Ready_fast_RNO: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_40 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_40 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_40"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE; + + end SLICE_40; + + architecture Structure of SLICE_40 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_1: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_0: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_41 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_41 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_41"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE; + + end SLICE_41; + + architecture Structure of SLICE_41 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_3: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_2: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_42 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_42 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_42"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE; + + end SLICE_42; + + architecture Structure of SLICE_42 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_5: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_4: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_7: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_6: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_9: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_8: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_9: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_8: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"5400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRRAS_5_u_i_0: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_0_i_o2_1: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_1: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"40C0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_46 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_46 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_46"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE; + + end SLICE_46; + + architecture Structure of SLICE_46 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG_3_u_0_bm: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + XOR8MEG_3_u_0_GATE: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + XOR8MEG: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_47 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_47 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_47"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE; + + end SLICE_47; + + architecture Structure of SLICE_47 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_rst10: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_6: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"DCEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_48 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_48 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_48"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE; + + end SLICE_48; + + architecture Structure of SLICE_48 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRowColSel_0_0_a3_0: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRowColSel_0_0: lut40043 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"B1A0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"E4E4") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_1: lut40044 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_adr_5_0: lut40045 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_3: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_2: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + wb_adr_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"D8D8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_51 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_51 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_51"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE; + + end SLICE_51; + + architecture Structure of SLICE_51 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_5: lut40046 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_4: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + wb_adr_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_52 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_52 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_52"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE; + + end SLICE_52; + + architecture Structure of SLICE_52 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_7: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_6: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + wb_adr_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI1_dly, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"0100") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"ECCC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_53 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_53 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_53"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE; + + end SLICE_53; + + architecture Structure of SLICE_53 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_2: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_wb_cyc_stb_1_sqmuxa_0: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_cyc_stb: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"EAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_54 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_54 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_54"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE; + + end SLICE_54; + + architecture Structure of SLICE_54 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_0_iv_0_0: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_55 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_55 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_55"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE; + + end SLICE_55; + + architecture Structure of SLICE_55 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_3: lut40051 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_2: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"FFE4") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_5: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_4: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"ECEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_7: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_6: lut40054 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_dati_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"7250") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + FS_RNIVOOA_14: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_reqe: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_req: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"3B33") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"7430") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + PHI2r3_RNIS5A51: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_rste: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_rst: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"888F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0008 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_adr_0_sqmuxa_2: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we_0: lut40058 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_we: vmuxregsre0008 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"FFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity wb_cyc_stb_RNO_SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity wb_cyc_stb_RNO_SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "wb_cyc_stb_RNO_SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF wb_cyc_stb_RNO_SLICE_61 : ENTITY IS TRUE; + + end wb_cyc_stb_RNO_SLICE_61; + + architecture Structure of wb_cyc_stb_RNO_SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_cyc_stb_RNO_SLICE_61_K1: lut40059 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1); + wb_cyc_stb_RNO_GATE: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_cyc_stb_RNO_SLICE_61_K0K1MUX: selmux2 + port map (D0=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0, + D1=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"B8F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdValid_fast_RNITQBM1: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + ufmefb_EFBInst_0_RNI9PBJ: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"0BFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_0_sqmuxa_0_o2_0: lut40022 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_nRCAS_6_sqmuxa_i_0: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"F1FC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_0_sqmuxa_1_0_a3: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"1108") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"2A2B") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_0: lut40065 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_40_1_0_1: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"1313") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + begin + INST10: ROM16X1A + generic map (initval => X"1303") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCAS_0io_RNO_0: lut40067 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_0io_RNO: lut40068 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + begin + INST10: ROM16X1A + generic map (initval => X"EAEA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_1: lut40069 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_o3_2: lut40070 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + begin + INST10: ROM16X1A + generic map (initval => X"5252") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_1: lut40071 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_0io_RNO_4: lut40072 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + begin + INST10: ROM16X1A + generic map (initval => X"BFBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + begin + INST10: ROM16X1A + generic map (initval => X"0202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_3: lut40073 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_RNICVV51_0: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + begin + INST10: ROM16X1A + generic map (initval => X"4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_4: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_a3_RNO_4: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40076 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40076 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE; + + end lut40076; + + architecture Structure of lut40076 is + begin + INST10: ROM16X1A + generic map (initval => X"0090") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_71"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE; + + end SLICE_71; + + architecture Structure of SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40076 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_we113_i_a2: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_RNO_7: lut40076 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40077 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40077 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE; + + end lut40077; + + architecture Structure of lut40077 is + begin + INST10: ROM16X1A + generic map (initval => X"B000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_2: lut40077 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + FS_RNI3V8E_9: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG14: lut40006 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdUFMData_RNO: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMData: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_6: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_6: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40078 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40078 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE; + + end lut40078; + + architecture Structure of lut40078 is + begin + INST10: ROM16X1A + generic map (initval => X"0404") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40079 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40079 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE; + + end lut40079; + + architecture Structure of lut40079 is + begin + INST10: ROM16X1A + generic map (initval => X"ECA0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40078 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40079 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_0_3: lut40078 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_0_3: lut40079 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_cnst_sn_m2_0_a3: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_RNO_4: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40080 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40080 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE; + + end lut40080; + + architecture Structure of lut40080 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40081 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40081 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE; + + end lut40081; + + architecture Structure of lut40081 is + begin + INST10: ROM16X1A + generic map (initval => X"FF32") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40080 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40081 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_nRCAS_6_sqmuxa_i_o2: lut40080 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRRAS_5_u_i: lut40081 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40082 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40082 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE; + + end lut40082; + + architecture Structure of lut40082 is + begin + INST10: ROM16X1A + generic map (initval => X"D3D3") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40082 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_m3_7: lut40082 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_7: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40079 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_2_0_1: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_0_1: lut40079 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40083 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40083 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE; + + end lut40083; + + architecture Structure of lut40083 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40083 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_1_1_4: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_4: lut40083 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_3_7: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_7: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40084 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40084 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE; + + end lut40084; + + architecture Structure of lut40084 is + begin + INST10: ROM16X1A + generic map (initval => X"8060") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40084 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_we95_0_0: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_we95_1: lut40084 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40085 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40085 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE; + + end lut40085; + + architecture Structure of lut40085 is + begin + INST10: ROM16X1A + generic map (initval => X"0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40085 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_7: lut40085 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_1_7: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40086 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40086 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE; + + end lut40086; + + architecture Structure of lut40086 is + begin + INST10: ROM16X1A + generic map (initval => X"1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40086 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_29: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_adr_cnst_sn_m4_32: lut40086 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40087 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40087 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE; + + end lut40087; + + architecture Structure of lut40087 is + begin + INST10: ROM16X1A + generic map (initval => X"9090") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40088 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40088 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE; + + end lut40088; + + architecture Structure of lut40088 is + begin + INST10: ROM16X1A + generic map (initval => X"F6F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40087 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40088 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_cnst_0_0: lut40087 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_FS_40_1_1_1: lut40088 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40089 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40089 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE; + + end lut40089; + + architecture Structure of lut40089 is + begin + INST10: ROM16X1A + generic map (initval => X"FFB1") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40089 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_o6: lut40089 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_40_1_a6: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40090 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40090 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE; + + end lut40090; + + architecture Structure of lut40090 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40091 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40091 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE; + + end lut40091; + + architecture Structure of lut40091 is + begin + INST10: ROM16X1A + generic map (initval => X"8040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40090 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40091 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_21_1_i: lut40090 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we95: lut40091 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40092 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40092 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE; + + end lut40092; + + architecture Structure of lut40092 is + begin + INST10: ROM16X1A + generic map (initval => X"3AFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40093 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40093 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE; + + end lut40093; + + architecture Structure of lut40093 is + begin + INST10: ROM16X1A + generic map (initval => X"200F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40092 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40093 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_0io_RNO: lut40092 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_r_i_a3_1_1_tz: lut40093 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_o3: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_2_sqmuxa_i_a3: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40094 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40094 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE; + + end lut40094; + + architecture Structure of lut40094 is + begin + INST10: ROM16X1A + generic map (initval => X"CCC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40094 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_CMDWR: lut40094 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + C1WR_7: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40095 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40095 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE; + + end lut40095; + + architecture Structure of lut40095 is + begin + INST10: ROM16X1A + generic map (initval => X"E0E0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40095 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_ADWR: lut40095 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADWR_7: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40096 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40096 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE; + + end lut40096; + + architecture Structure of lut40096 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40096 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + C1WR_0: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + C1WR_2: lut40096 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40097 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40097 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE; + + end lut40097; + + architecture Structure of lut40097 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40097 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_adr_0_sqmuxa_3: lut40073 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we113_i_0: lut40097 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_Bank_1_3: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_Bank_1: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_PHI2r3_0: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_1_sqmuxa_0_a3: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40085 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_1: lut40085 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40098 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40098 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE; + + end lut40098; + + architecture Structure of lut40098 is + begin + INST10: ROM16X1A + generic map (initval => X"80FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40098 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + PHI2r3_RNIFT0I: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMShift_fast_RNIG9JD1: lut40098 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_2: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_0io_RNO_0: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40099 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40099 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE; + + end lut40099; + + architecture Structure of lut40099 is + begin + INST10: ROM16X1A + generic map (initval => X"8004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40099 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_0_0_0_1: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_a3_0_0_3: lut40099 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40100 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE; + + end lut40100; + + architecture Structure of lut40100 is + begin + INST10: ROM16X1A + generic map (initval => X"4042") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40101 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE; + + end lut40101; + + architecture Structure of lut40101 is + begin + INST10: ROM16X1A + generic map (initval => X"0810") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40100 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40101 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_1_tz: lut40100 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_o3_1: lut40101 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable17_5: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_Din_2: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + InitReady3_0_a3_2: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_11: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40102 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE; + + end lut40102; + + architecture Structure of lut40102 is + begin + INST10: ROM16X1A + generic map (initval => X"8282") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40102 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_0_0_6: lut40102 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_3_0_7: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40096 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable16_4: lut40036 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdEnable17_4: lut40096 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40103 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE; + + end lut40103; + + architecture Structure of lut40103 is + begin + INST10: ROM16X1A + generic map (initval => X"0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40104 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE; + + end lut40104; + + architecture Structure of lut40104 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40103 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40104 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + ADWR_4: lut40103 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CMDWR_2: lut40104 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CBR_fast: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG9_1: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdEnable16_5: lut40047 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_107 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_107 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_107"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_107 : ENTITY IS TRUE; + + end SLICE_107; + + architecture Structure of SLICE_107 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQMH: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_9: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40105 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE; + + end lut40105; + + architecture Structure of lut40105 is + begin + INST10: ROM16X1A + generic map (initval => X"5051") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_108 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_108 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_108"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_108 : ENTITY IS TRUE; + + end SLICE_108; + + architecture Structure of SLICE_108 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40105 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRRAS_5_u_i_0_RNILD5I: lut40105 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_0_sqmuxa_0_o2_0_RNIS63D: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FWEr_fast: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_109 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_109 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_109"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_109 : ENTITY IS TRUE; + + end SLICE_109; + + architecture Structure of SLICE_109 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_4: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a2_0_4: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40106 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE; + + end lut40106; + + architecture Structure of lut40106 is + begin + INST10: ROM16X1A + generic map (initval => X"4800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_110 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_110 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_110"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_110 : ENTITY IS TRUE; + + end SLICE_110; + + architecture Structure of SLICE_110 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40090 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40106 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_22_1_i: lut40090 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_0_iv_0_a3_1_0: lut40106 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_111 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_111 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_111"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_111 : ENTITY IS TRUE; + + end SLICE_111; + + architecture Structure of SLICE_111 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_7: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADWR_5: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_112 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_112 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_112"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_112 : ENTITY IS TRUE; + + end SLICE_112; + + architecture Structure of SLICE_112 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40090 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQML: lut40090 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_0: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_113 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_113 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_113"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_113 : ENTITY IS TRUE; + + end SLICE_113; + + architecture Structure of SLICE_113 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_8: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_1: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_114 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_114 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_114"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_114 : ENTITY IS TRUE; + + end SLICE_114; + + architecture Structure of SLICE_114 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_6: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_2: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_115 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_115 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_115"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_115 : ENTITY IS TRUE; + + end SLICE_115; + + architecture Structure of SLICE_115 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_5: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_3: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40107 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40107 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE; + + end lut40107; + + architecture Structure of lut40107 is + begin + INST10: ROM16X1A + generic map (initval => X"C048") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40108 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40108 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE; + + end lut40108; + + architecture Structure of lut40108 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_116 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_116 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_116"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_116 : ENTITY IS TRUE; + + end SLICE_116; + + architecture Structure of SLICE_116 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40107 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40108 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA11d: lut40107 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + XOR8MEG14_1: lut40108 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40109 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40109 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE; + + end lut40109; + + architecture Structure of lut40109 is + begin + INST10: ROM16X1A + generic map (initval => X"70CF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_117 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_117 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_117"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_117 : ENTITY IS TRUE; + + end SLICE_117; + + architecture Structure of SLICE_117 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40086 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40109 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_0io_RNO_0: lut40086 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_8_u_1_0: lut40109 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_118 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_118 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_118"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_118 : ENTITY IS TRUE; + + end SLICE_118; + + architecture Structure of SLICE_118 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RBAd_0: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBAd_1: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + PHI2r3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IB + port map (I=>PADI, O=>Z); + INST2: OBW + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_0: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE; + + end mfflsre; + + architecture Structure of mfflsre is + begin + INST01: FD1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity RD_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE; + + end RD_0_MGIOL; + + architecture Structure of RD_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0110 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0110 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0110 : ENTITY IS TRUE; + + end xo2iobuf0110; + + architecture Structure of xo2iobuf0110 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0111 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0111 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0111 : ENTITY IS TRUE; + + end xo2iobuf0111; + + architecture Structure of xo2iobuf0111 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0111 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0111 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity smuxlregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity smuxlregsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE; + + end smuxlregsre; + + architecture Structure of smuxlregsre is + begin + INST01: IFS1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity PHI2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE; + + end PHI2_MGIOL; + + architecture Structure of PHI2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + PHI2r_0io: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RDQMLS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RDQMHS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>nRCASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre0112 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0112 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0112 : ENTITY IS TRUE; + + end mfflsre0112; + + architecture Structure of mfflsre0112 is + begin + INST01: FD1P3BX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity nRCAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE; + + end nRCAS_MGIOL; + + architecture Structure of nRCAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0112 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCAS_0io: mfflsre0112 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>nRRASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE; + + end nRRAS_MGIOL; + + architecture Structure of nRRAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0112 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRRAS_0io: mfflsre0112 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>nRWES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWE_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWE_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWE_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE; + + end nRWE_MGIOL; + + architecture Structure of nRWE_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0112 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRWE_0io: mfflsre0112 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RCKES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0113 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0113 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0113 : ENTITY IS TRUE; + + end xo2iobuf0113; + + architecture Structure of xo2iobuf0113 is + begin + INST1: IB + port map (I=>PAD, O=>Z); + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>nRCSS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE; + + end nRCS_MGIOL; + + architecture Structure of nRCS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0112 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCS_0io: mfflsre0112 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_7: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_7_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE; + + end RD_7_MGIOL; + + architecture Structure of RD_7_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_7: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_6: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE; + + end RD_6_MGIOL; + + architecture Structure of RD_6_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_6: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_5: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE; + + end RD_5_MGIOL; + + architecture Structure of RD_5_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_5: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_4: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE; + + end RD_4_MGIOL; + + architecture Structure of RD_4_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_4: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_3: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE; + + end RD_3_MGIOL; + + architecture Structure of RD_3_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_3: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_2: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE; + + end RD_2_MGIOL; + + architecture Structure of RD_2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_2: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_1: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE; + + end RD_1_MGIOL; + + architecture Structure of RD_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>RA11_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE; + + end RA_11_MGIOL; + + architecture Structure of RA_11_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA11_0io: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>RA10_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre0114 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0114 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0114 : ENTITY IS TRUE; + + end mfflsre0114; + + architecture Structure of mfflsre0114 is + begin + INST01: FD1P3JX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity RA_10_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE; + + end RA_10_MGIOL; + + architecture Structure of RA_10_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component mfflsre0114 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA10_0io: mfflsre0114 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, + Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA9_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA8_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA7_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA6_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA5_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA4_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA3_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA2_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>RA0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>RBA1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE; + + end RBA_1_MGIOL; + + architecture Structure of RBA_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RBA_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0110 + port map (I=>IOLDO_ipd, PAD=>RBA0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE; + + end RBA_0_MGIOL; + + architecture Structure of RBA_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RBA_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0115 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0115 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0115 : ENTITY IS TRUE; + + end xo2iobuf0115; + + architecture Structure of xo2iobuf0115 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + component xo2iobuf0115 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0115 + port map (I=>PADDO_ipd, PAD=>LEDS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0116 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0116 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0116 : ENTITY IS TRUE; + + end xo2iobuf0116; + + architecture Structure of xo2iobuf0116 is + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0116 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0116 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0116 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0116 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0116 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0116 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout7_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout6_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout5_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout4_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout3_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout2_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + component xo2iobuf0110 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0110 + port map (I=>PADDO_ipd, PAD=>Dout1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE; + + end Din_7_MGIOL; + + architecture Structure of Din_7_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_7: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE; + + end Din_6_MGIOL; + + architecture Structure of Din_6_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_6: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE; + + end Din_5_MGIOL; + + architecture Structure of Din_5_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_5: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE; + + end Din_4_MGIOL; + + architecture Structure of Din_4_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_4: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE; + + end Din_3_MGIOL; + + architecture Structure of Din_3_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_3: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE; + + end Din_2_MGIOL; + + architecture Structure of Din_2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_2: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE; + + end Din_1_MGIOL; + + architecture Structure of Din_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_1: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE; + + end Din_0_MGIOL; + + architecture Structure of Din_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_0: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0113 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0113 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity EFB_Buffer_Block + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity EFB_Buffer_Block is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "EFB_Buffer_Block"; + + tipd_WBCLKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBRSTIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBCYCIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBSTBIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBWEIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0ACKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1ACKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCSNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCCLKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCRSTNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCICin : VitalDelayType01 := (0 ns, 0 ns); + tipd_UFMSNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBACKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLCLKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLRSTOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0STBOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1STBOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLWEOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1IRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2IRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPICSNENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIIRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCINTin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCOCin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBCUFMIRQin : VitalDelayType01 := (0 ns, 0 ns); + tipd_CFGWAKEin : VitalDelayType01 := (0 ns, 0 ns); + tipd_CFGSTDBYin : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBDATO0out : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBDATO1out : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBACKOout : VitalDelayType01 := (0 ns, 0 ns); + ticd_WBCLKIin : VitalDelayType := 0 ns; + tisd_WBRSTIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBCYCIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBSTBIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBWEIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI0in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI1in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI2in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI3in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI4in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI5in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI6in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI7in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI0in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI1in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI2in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI3in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI4in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI5in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI6in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI7in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tperiod_WBCLKIin : VitalDelayType := 0 ns; + tpw_WBCLKIin_posedge : VitalDelayType := 0 ns; + tpw_WBCLKIin_negedge : VitalDelayType := 0 ns); + + port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic; + WBRSTIin: in Std_logic; WBRSTIout: out Std_logic; + WBCYCIin: in Std_logic; WBCYCIout: out Std_logic; + WBSTBIin: in Std_logic; WBSTBIout: out Std_logic; + WBWEIin: in Std_logic; WBWEIout: out Std_logic; + WBADRI7in: in Std_logic; WBADRI7out: out Std_logic; + WBADRI6in: in Std_logic; WBADRI6out: out Std_logic; + WBADRI5in: in Std_logic; WBADRI5out: out Std_logic; + WBADRI4in: in Std_logic; WBADRI4out: out Std_logic; + WBADRI3in: in Std_logic; WBADRI3out: out Std_logic; + WBADRI2in: in Std_logic; WBADRI2out: out Std_logic; + WBADRI1in: in Std_logic; WBADRI1out: out Std_logic; + WBADRI0in: in Std_logic; WBADRI0out: out Std_logic; + WBDATI7in: in Std_logic; WBDATI7out: out Std_logic; + WBDATI6in: in Std_logic; WBDATI6out: out Std_logic; + WBDATI5in: in Std_logic; WBDATI5out: out Std_logic; + WBDATI4in: in Std_logic; WBDATI4out: out Std_logic; + WBDATI3in: in Std_logic; WBDATI3out: out Std_logic; + WBDATI2in: in Std_logic; WBDATI2out: out Std_logic; + WBDATI1in: in Std_logic; WBDATI1out: out Std_logic; + WBDATI0in: in Std_logic; WBDATI0out: out Std_logic; + PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic; + PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic; + PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic; + PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic; + PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic; + PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic; + PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic; + PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic; + PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic; + PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic; + PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic; + PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic; + PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic; + PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic; + PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic; + PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic; + PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic; + PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic; + I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic; + I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic; + I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic; + I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic; + SPISCKIin: in Std_logic; SPISCKIout: out Std_logic; + SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic; + SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic; + SPISCSNin: in Std_logic; SPISCSNout: out Std_logic; + TCCLKIin: in Std_logic; TCCLKIout: out Std_logic; + TCRSTNin: in Std_logic; TCRSTNout: out Std_logic; + TCICin: in Std_logic; TCICout: out Std_logic; UFMSNin: in Std_logic; + UFMSNout: out Std_logic; WBDATO7out: out Std_logic; + WBDATO7in: in Std_logic; WBDATO6out: out Std_logic; + WBDATO6in: in Std_logic; WBDATO5out: out Std_logic; + WBDATO5in: in Std_logic; WBDATO4out: out Std_logic; + WBDATO4in: in Std_logic; WBDATO3out: out Std_logic; + WBDATO3in: in Std_logic; WBDATO2out: out Std_logic; + WBDATO2in: in Std_logic; WBDATO1out: out Std_logic; + WBDATO1in: in Std_logic; WBDATO0out: out Std_logic; + WBDATO0in: in Std_logic; WBACKOout: out Std_logic; + WBACKOin: in Std_logic; PLLCLKOout: out Std_logic; + PLLCLKOin: in Std_logic; PLLRSTOout: out Std_logic; + PLLRSTOin: in Std_logic; PLL0STBOout: out Std_logic; + PLL0STBOin: in Std_logic; PLL1STBOout: out Std_logic; + PLL1STBOin: in Std_logic; PLLWEOout: out Std_logic; + PLLWEOin: in Std_logic; PLLADRO4out: out Std_logic; + PLLADRO4in: in Std_logic; PLLADRO3out: out Std_logic; + PLLADRO3in: in Std_logic; PLLADRO2out: out Std_logic; + PLLADRO2in: in Std_logic; PLLADRO1out: out Std_logic; + PLLADRO1in: in Std_logic; PLLADRO0out: out Std_logic; + PLLADRO0in: in Std_logic; PLLDATO7out: out Std_logic; + PLLDATO7in: in Std_logic; PLLDATO6out: out Std_logic; + PLLDATO6in: in Std_logic; PLLDATO5out: out Std_logic; + PLLDATO5in: in Std_logic; PLLDATO4out: out Std_logic; + PLLDATO4in: in Std_logic; PLLDATO3out: out Std_logic; + PLLDATO3in: in Std_logic; PLLDATO2out: out Std_logic; + PLLDATO2in: in Std_logic; PLLDATO1out: out Std_logic; + PLLDATO1in: in Std_logic; PLLDATO0out: out Std_logic; + PLLDATO0in: in Std_logic; I2C1SCLOout: out Std_logic; + I2C1SCLOin: in Std_logic; I2C1SCLOENout: out Std_logic; + I2C1SCLOENin: in Std_logic; I2C1SDAOout: out Std_logic; + I2C1SDAOin: in Std_logic; I2C1SDAOENout: out Std_logic; + I2C1SDAOENin: in Std_logic; I2C2SCLOout: out Std_logic; + I2C2SCLOin: in Std_logic; I2C2SCLOENout: out Std_logic; + I2C2SCLOENin: in Std_logic; I2C2SDAOout: out Std_logic; + I2C2SDAOin: in Std_logic; I2C2SDAOENout: out Std_logic; + I2C2SDAOENin: in Std_logic; I2C1IRQOout: out Std_logic; + I2C1IRQOin: in Std_logic; I2C2IRQOout: out Std_logic; + I2C2IRQOin: in Std_logic; SPISCKOout: out Std_logic; + SPISCKOin: in Std_logic; SPISCKENout: out Std_logic; + SPISCKENin: in Std_logic; SPIMISOOout: out Std_logic; + SPIMISOOin: in Std_logic; SPIMISOENout: out Std_logic; + SPIMISOENin: in Std_logic; SPIMOSIOout: out Std_logic; + SPIMOSIOin: in Std_logic; SPIMOSIENout: out Std_logic; + SPIMOSIENin: in Std_logic; SPIMCSN0out: out Std_logic; + SPIMCSN0in: in Std_logic; SPIMCSN1out: out Std_logic; + SPIMCSN1in: in Std_logic; SPIMCSN2out: out Std_logic; + SPIMCSN2in: in Std_logic; SPIMCSN3out: out Std_logic; + SPIMCSN3in: in Std_logic; SPIMCSN4out: out Std_logic; + SPIMCSN4in: in Std_logic; SPIMCSN5out: out Std_logic; + SPIMCSN5in: in Std_logic; SPIMCSN6out: out Std_logic; + SPIMCSN6in: in Std_logic; SPIMCSN7out: out Std_logic; + SPIMCSN7in: in Std_logic; SPICSNENout: out Std_logic; + SPICSNENin: in Std_logic; SPIIRQOout: out Std_logic; + SPIIRQOin: in Std_logic; TCINTout: out Std_logic; + TCINTin: in Std_logic; TCOCout: out Std_logic; TCOCin: in Std_logic; + WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic; + CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic; + CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic); + + ATTRIBUTE Vital_Level0 OF EFB_Buffer_Block : ENTITY IS TRUE; + + end EFB_Buffer_Block; + + architecture Structure of EFB_Buffer_Block is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal WBCLKIin_ipd : std_logic := 'X'; + signal WBCLKIin_dly : std_logic := 'X'; + signal WBCLKIout_out : std_logic := 'X'; + signal WBRSTIin_ipd : std_logic := 'X'; + signal WBRSTIin_dly : std_logic := 'X'; + signal WBRSTIout_out : std_logic := 'X'; + signal WBCYCIin_ipd : std_logic := 'X'; + signal WBCYCIin_dly : std_logic := 'X'; + signal WBCYCIout_out : std_logic := 'X'; + signal WBSTBIin_ipd : std_logic := 'X'; + signal WBSTBIin_dly : std_logic := 'X'; + signal WBSTBIout_out : std_logic := 'X'; + signal WBWEIin_ipd : std_logic := 'X'; + signal WBWEIin_dly : std_logic := 'X'; + signal WBWEIout_out : std_logic := 'X'; + signal WBADRI7in_ipd : std_logic := 'X'; + signal WBADRI7in_dly : std_logic := 'X'; + signal WBADRI7out_out : std_logic := 'X'; + signal WBADRI6in_ipd : std_logic := 'X'; + signal WBADRI6in_dly : std_logic := 'X'; + signal WBADRI6out_out : std_logic := 'X'; + signal WBADRI5in_ipd : std_logic := 'X'; + signal WBADRI5in_dly : std_logic := 'X'; + signal WBADRI5out_out : std_logic := 'X'; + signal WBADRI4in_ipd : std_logic := 'X'; + signal WBADRI4in_dly : std_logic := 'X'; + signal WBADRI4out_out : std_logic := 'X'; + signal WBADRI3in_ipd : std_logic := 'X'; + signal WBADRI3in_dly : std_logic := 'X'; + signal WBADRI3out_out : std_logic := 'X'; + signal WBADRI2in_ipd : std_logic := 'X'; + signal WBADRI2in_dly : std_logic := 'X'; + signal WBADRI2out_out : std_logic := 'X'; + signal WBADRI1in_ipd : std_logic := 'X'; + signal WBADRI1in_dly : std_logic := 'X'; + signal WBADRI1out_out : std_logic := 'X'; + signal WBADRI0in_ipd : std_logic := 'X'; + signal WBADRI0in_dly : std_logic := 'X'; + signal WBADRI0out_out : std_logic := 'X'; + signal WBDATI7in_ipd : std_logic := 'X'; + signal WBDATI7in_dly : std_logic := 'X'; + signal WBDATI7out_out : std_logic := 'X'; + signal WBDATI6in_ipd : std_logic := 'X'; + signal WBDATI6in_dly : std_logic := 'X'; + signal WBDATI6out_out : std_logic := 'X'; + signal WBDATI5in_ipd : std_logic := 'X'; + signal WBDATI5in_dly : std_logic := 'X'; + signal WBDATI5out_out : std_logic := 'X'; + signal WBDATI4in_ipd : std_logic := 'X'; + signal WBDATI4in_dly : std_logic := 'X'; + signal WBDATI4out_out : std_logic := 'X'; + signal WBDATI3in_ipd : std_logic := 'X'; + signal WBDATI3in_dly : std_logic := 'X'; + signal WBDATI3out_out : std_logic := 'X'; + signal WBDATI2in_ipd : std_logic := 'X'; + signal WBDATI2in_dly : std_logic := 'X'; + signal WBDATI2out_out : std_logic := 'X'; + signal WBDATI1in_ipd : std_logic := 'X'; + signal WBDATI1in_dly : std_logic := 'X'; + signal WBDATI1out_out : std_logic := 'X'; + signal WBDATI0in_ipd : std_logic := 'X'; + signal WBDATI0in_dly : std_logic := 'X'; + signal WBDATI0out_out : std_logic := 'X'; + signal PLL0DATI7in_ipd : std_logic := 'X'; + signal PLL0DATI7out_out : std_logic := 'X'; + signal PLL0DATI6in_ipd : std_logic := 'X'; + signal PLL0DATI6out_out : std_logic := 'X'; + signal PLL0DATI5in_ipd : std_logic := 'X'; + signal PLL0DATI5out_out : std_logic := 'X'; + signal PLL0DATI4in_ipd : std_logic := 'X'; + signal PLL0DATI4out_out : std_logic := 'X'; + signal PLL0DATI3in_ipd : std_logic := 'X'; + signal PLL0DATI3out_out : std_logic := 'X'; + signal PLL0DATI2in_ipd : std_logic := 'X'; + signal PLL0DATI2out_out : std_logic := 'X'; + signal PLL0DATI1in_ipd : std_logic := 'X'; + signal PLL0DATI1out_out : std_logic := 'X'; + signal PLL0DATI0in_ipd : std_logic := 'X'; + signal PLL0DATI0out_out : std_logic := 'X'; + signal PLL0ACKIin_ipd : std_logic := 'X'; + signal PLL0ACKIout_out : std_logic := 'X'; + signal PLL1DATI7in_ipd : std_logic := 'X'; + signal PLL1DATI7out_out : std_logic := 'X'; + signal PLL1DATI6in_ipd : std_logic := 'X'; + signal PLL1DATI6out_out : std_logic := 'X'; + signal PLL1DATI5in_ipd : std_logic := 'X'; + signal PLL1DATI5out_out : std_logic := 'X'; + signal PLL1DATI4in_ipd : std_logic := 'X'; + signal PLL1DATI4out_out : std_logic := 'X'; + signal PLL1DATI3in_ipd : std_logic := 'X'; + signal PLL1DATI3out_out : std_logic := 'X'; + signal PLL1DATI2in_ipd : std_logic := 'X'; + signal PLL1DATI2out_out : std_logic := 'X'; + signal PLL1DATI1in_ipd : std_logic := 'X'; + signal PLL1DATI1out_out : std_logic := 'X'; + signal PLL1DATI0in_ipd : std_logic := 'X'; + signal PLL1DATI0out_out : std_logic := 'X'; + signal PLL1ACKIin_ipd : std_logic := 'X'; + signal PLL1ACKIout_out : std_logic := 'X'; + signal I2C1SCLIin_ipd : std_logic := 'X'; + signal I2C1SCLIout_out : std_logic := 'X'; + signal I2C1SDAIin_ipd : std_logic := 'X'; + signal I2C1SDAIout_out : std_logic := 'X'; + signal I2C2SCLIin_ipd : std_logic := 'X'; + signal I2C2SCLIout_out : std_logic := 'X'; + signal I2C2SDAIin_ipd : std_logic := 'X'; + signal I2C2SDAIout_out : std_logic := 'X'; + signal SPISCKIin_ipd : std_logic := 'X'; + signal SPISCKIout_out : std_logic := 'X'; + signal SPIMISOIin_ipd : std_logic := 'X'; + signal SPIMISOIout_out : std_logic := 'X'; + signal SPIMOSIIin_ipd : std_logic := 'X'; + signal SPIMOSIIout_out : std_logic := 'X'; + signal SPISCSNin_ipd : std_logic := 'X'; + signal SPISCSNout_out : std_logic := 'X'; + signal TCCLKIin_ipd : std_logic := 'X'; + signal TCCLKIout_out : std_logic := 'X'; + signal TCRSTNin_ipd : std_logic := 'X'; + signal TCRSTNout_out : std_logic := 'X'; + signal TCICin_ipd : std_logic := 'X'; + signal TCICout_out : std_logic := 'X'; + signal UFMSNin_ipd : std_logic := 'X'; + signal UFMSNout_out : std_logic := 'X'; + signal WBDATO7out_out : std_logic := 'X'; + signal WBDATO7in_ipd : std_logic := 'X'; + signal WBDATO6out_out : std_logic := 'X'; + signal WBDATO6in_ipd : std_logic := 'X'; + signal WBDATO5out_out : std_logic := 'X'; + signal WBDATO5in_ipd : std_logic := 'X'; + signal WBDATO4out_out : std_logic := 'X'; + signal WBDATO4in_ipd : std_logic := 'X'; + signal WBDATO3out_out : std_logic := 'X'; + signal WBDATO3in_ipd : std_logic := 'X'; + signal WBDATO2out_out : std_logic := 'X'; + signal WBDATO2in_ipd : std_logic := 'X'; + signal WBDATO1out_out : std_logic := 'X'; + signal WBDATO1in_ipd : std_logic := 'X'; + signal WBDATO0out_out : std_logic := 'X'; + signal WBDATO0in_ipd : std_logic := 'X'; + signal WBACKOout_out : std_logic := 'X'; + signal WBACKOin_ipd : std_logic := 'X'; + signal PLLCLKOout_out : std_logic := 'X'; + signal PLLCLKOin_ipd : std_logic := 'X'; + signal PLLRSTOout_out : std_logic := 'X'; + signal PLLRSTOin_ipd : std_logic := 'X'; + signal PLL0STBOout_out : std_logic := 'X'; + signal PLL0STBOin_ipd : std_logic := 'X'; + signal PLL1STBOout_out : std_logic := 'X'; + signal PLL1STBOin_ipd : std_logic := 'X'; + signal PLLWEOout_out : std_logic := 'X'; + signal PLLWEOin_ipd : std_logic := 'X'; + signal PLLADRO4out_out : std_logic := 'X'; + signal PLLADRO4in_ipd : std_logic := 'X'; + signal PLLADRO3out_out : std_logic := 'X'; + signal PLLADRO3in_ipd : std_logic := 'X'; + signal PLLADRO2out_out : std_logic := 'X'; + signal PLLADRO2in_ipd : std_logic := 'X'; + signal PLLADRO1out_out : std_logic := 'X'; + signal PLLADRO1in_ipd : std_logic := 'X'; + signal PLLADRO0out_out : std_logic := 'X'; + signal PLLADRO0in_ipd : std_logic := 'X'; + signal PLLDATO7out_out : std_logic := 'X'; + signal PLLDATO7in_ipd : std_logic := 'X'; + signal PLLDATO6out_out : std_logic := 'X'; + signal PLLDATO6in_ipd : std_logic := 'X'; + signal PLLDATO5out_out : std_logic := 'X'; + signal PLLDATO5in_ipd : std_logic := 'X'; + signal PLLDATO4out_out : std_logic := 'X'; + signal PLLDATO4in_ipd : std_logic := 'X'; + signal PLLDATO3out_out : std_logic := 'X'; + signal PLLDATO3in_ipd : std_logic := 'X'; + signal PLLDATO2out_out : std_logic := 'X'; + signal PLLDATO2in_ipd : std_logic := 'X'; + signal PLLDATO1out_out : std_logic := 'X'; + signal PLLDATO1in_ipd : std_logic := 'X'; + signal PLLDATO0out_out : std_logic := 'X'; + signal PLLDATO0in_ipd : std_logic := 'X'; + signal I2C1SCLOout_out : std_logic := 'X'; + signal I2C1SCLOin_ipd : std_logic := 'X'; + signal I2C1SCLOENout_out : std_logic := 'X'; + signal I2C1SCLOENin_ipd : std_logic := 'X'; + signal I2C1SDAOout_out : std_logic := 'X'; + signal I2C1SDAOin_ipd : std_logic := 'X'; + signal I2C1SDAOENout_out : std_logic := 'X'; + signal I2C1SDAOENin_ipd : std_logic := 'X'; + signal I2C2SCLOout_out : std_logic := 'X'; + signal I2C2SCLOin_ipd : std_logic := 'X'; + signal I2C2SCLOENout_out : std_logic := 'X'; + signal I2C2SCLOENin_ipd : std_logic := 'X'; + signal I2C2SDAOout_out : std_logic := 'X'; + signal I2C2SDAOin_ipd : std_logic := 'X'; + signal I2C2SDAOENout_out : std_logic := 'X'; + signal I2C2SDAOENin_ipd : std_logic := 'X'; + signal I2C1IRQOout_out : std_logic := 'X'; + signal I2C1IRQOin_ipd : std_logic := 'X'; + signal I2C2IRQOout_out : std_logic := 'X'; + signal I2C2IRQOin_ipd : std_logic := 'X'; + signal SPISCKOout_out : std_logic := 'X'; + signal SPISCKOin_ipd : std_logic := 'X'; + signal SPISCKENout_out : std_logic := 'X'; + signal SPISCKENin_ipd : std_logic := 'X'; + signal SPIMISOOout_out : std_logic := 'X'; + signal SPIMISOOin_ipd : std_logic := 'X'; + signal SPIMISOENout_out : std_logic := 'X'; + signal SPIMISOENin_ipd : std_logic := 'X'; + signal SPIMOSIOout_out : std_logic := 'X'; + signal SPIMOSIOin_ipd : std_logic := 'X'; + signal SPIMOSIENout_out : std_logic := 'X'; + signal SPIMOSIENin_ipd : std_logic := 'X'; + signal SPIMCSN0out_out : std_logic := 'X'; + signal SPIMCSN0in_ipd : std_logic := 'X'; + signal SPIMCSN1out_out : std_logic := 'X'; + signal SPIMCSN1in_ipd : std_logic := 'X'; + signal SPIMCSN2out_out : std_logic := 'X'; + signal SPIMCSN2in_ipd : std_logic := 'X'; + signal SPIMCSN3out_out : std_logic := 'X'; + signal SPIMCSN3in_ipd : std_logic := 'X'; + signal SPIMCSN4out_out : std_logic := 'X'; + signal SPIMCSN4in_ipd : std_logic := 'X'; + signal SPIMCSN5out_out : std_logic := 'X'; + signal SPIMCSN5in_ipd : std_logic := 'X'; + signal SPIMCSN6out_out : std_logic := 'X'; + signal SPIMCSN6in_ipd : std_logic := 'X'; + signal SPIMCSN7out_out : std_logic := 'X'; + signal SPIMCSN7in_ipd : std_logic := 'X'; + signal SPICSNENout_out : std_logic := 'X'; + signal SPICSNENin_ipd : std_logic := 'X'; + signal SPIIRQOout_out : std_logic := 'X'; + signal SPIIRQOin_ipd : std_logic := 'X'; + signal TCINTout_out : std_logic := 'X'; + signal TCINTin_ipd : std_logic := 'X'; + signal TCOCout_out : std_logic := 'X'; + signal TCOCin_ipd : std_logic := 'X'; + signal WBCUFMIRQout_out : std_logic := 'X'; + signal WBCUFMIRQin_ipd : std_logic := 'X'; + signal CFGWAKEout_out : std_logic := 'X'; + signal CFGWAKEin_ipd : std_logic := 'X'; + signal CFGSTDBYout_out : std_logic := 'X'; + signal CFGSTDBYin_ipd : std_logic := 'X'; + + begin + WBCLKI_buf: BUFBA + port map (A=>WBCLKIin_dly, Z=>WBCLKIout_out); + WBRSTI_buf: BUFBA + port map (A=>WBRSTIin_dly, Z=>WBRSTIout_out); + WBCYCI_buf: BUFBA + port map (A=>WBCYCIin_dly, Z=>WBCYCIout_out); + WBSTBI_buf: BUFBA + port map (A=>WBSTBIin_dly, Z=>WBSTBIout_out); + WBWEI_buf: BUFBA + port map (A=>WBWEIin_dly, Z=>WBWEIout_out); + WBADRI7_buf: BUFBA + port map (A=>WBADRI7in_dly, Z=>WBADRI7out_out); + WBADRI6_buf: BUFBA + port map (A=>WBADRI6in_dly, Z=>WBADRI6out_out); + WBADRI5_buf: BUFBA + port map (A=>WBADRI5in_dly, Z=>WBADRI5out_out); + WBADRI4_buf: BUFBA + port map (A=>WBADRI4in_dly, Z=>WBADRI4out_out); + WBADRI3_buf: BUFBA + port map (A=>WBADRI3in_dly, Z=>WBADRI3out_out); + WBADRI2_buf: BUFBA + port map (A=>WBADRI2in_dly, Z=>WBADRI2out_out); + WBADRI1_buf: BUFBA + port map (A=>WBADRI1in_dly, Z=>WBADRI1out_out); + WBADRI0_buf: BUFBA + port map (A=>WBADRI0in_dly, Z=>WBADRI0out_out); + WBDATI7_buf: BUFBA + port map (A=>WBDATI7in_dly, Z=>WBDATI7out_out); + WBDATI6_buf: BUFBA + port map (A=>WBDATI6in_dly, Z=>WBDATI6out_out); + WBDATI5_buf: BUFBA + port map (A=>WBDATI5in_dly, Z=>WBDATI5out_out); + WBDATI4_buf: BUFBA + port map (A=>WBDATI4in_dly, Z=>WBDATI4out_out); + WBDATI3_buf: BUFBA + port map (A=>WBDATI3in_dly, Z=>WBDATI3out_out); + WBDATI2_buf: BUFBA + port map (A=>WBDATI2in_dly, Z=>WBDATI2out_out); + WBDATI1_buf: BUFBA + port map (A=>WBDATI1in_dly, Z=>WBDATI1out_out); + WBDATI0_buf: BUFBA + port map (A=>WBDATI0in_dly, Z=>WBDATI0out_out); + PLL0DATI7_buf: BUFBA + port map (A=>PLL0DATI7in_ipd, Z=>PLL0DATI7out_out); + PLL0DATI6_buf: BUFBA + port map (A=>PLL0DATI6in_ipd, Z=>PLL0DATI6out_out); + PLL0DATI5_buf: BUFBA + port map (A=>PLL0DATI5in_ipd, Z=>PLL0DATI5out_out); + PLL0DATI4_buf: BUFBA + port map (A=>PLL0DATI4in_ipd, Z=>PLL0DATI4out_out); + PLL0DATI3_buf: BUFBA + port map (A=>PLL0DATI3in_ipd, Z=>PLL0DATI3out_out); + PLL0DATI2_buf: BUFBA + port map (A=>PLL0DATI2in_ipd, Z=>PLL0DATI2out_out); + PLL0DATI1_buf: BUFBA + port map (A=>PLL0DATI1in_ipd, Z=>PLL0DATI1out_out); + PLL0DATI0_buf: BUFBA + port map (A=>PLL0DATI0in_ipd, Z=>PLL0DATI0out_out); + PLL0ACKI_buf: BUFBA + port map (A=>PLL0ACKIin_ipd, Z=>PLL0ACKIout_out); + PLL1DATI7_buf: BUFBA + port map (A=>PLL1DATI7in_ipd, Z=>PLL1DATI7out_out); + PLL1DATI6_buf: BUFBA + port map (A=>PLL1DATI6in_ipd, Z=>PLL1DATI6out_out); + PLL1DATI5_buf: BUFBA + port map (A=>PLL1DATI5in_ipd, Z=>PLL1DATI5out_out); + PLL1DATI4_buf: BUFBA + port map (A=>PLL1DATI4in_ipd, Z=>PLL1DATI4out_out); + PLL1DATI3_buf: BUFBA + port map (A=>PLL1DATI3in_ipd, Z=>PLL1DATI3out_out); + PLL1DATI2_buf: BUFBA + port map (A=>PLL1DATI2in_ipd, Z=>PLL1DATI2out_out); + PLL1DATI1_buf: BUFBA + port map (A=>PLL1DATI1in_ipd, Z=>PLL1DATI1out_out); + PLL1DATI0_buf: BUFBA + port map (A=>PLL1DATI0in_ipd, Z=>PLL1DATI0out_out); + PLL1ACKI_buf: BUFBA + port map (A=>PLL1ACKIin_ipd, Z=>PLL1ACKIout_out); + I2C1SCLI_buf: BUFBA + port map (A=>I2C1SCLIin_ipd, Z=>I2C1SCLIout_out); + I2C1SDAI_buf: BUFBA + port map (A=>I2C1SDAIin_ipd, Z=>I2C1SDAIout_out); + I2C2SCLI_buf: BUFBA + port map (A=>I2C2SCLIin_ipd, Z=>I2C2SCLIout_out); + I2C2SDAI_buf: BUFBA + port map (A=>I2C2SDAIin_ipd, Z=>I2C2SDAIout_out); + SPISCKI_buf: BUFBA + port map (A=>SPISCKIin_ipd, Z=>SPISCKIout_out); + SPIMISOI_buf: BUFBA + port map (A=>SPIMISOIin_ipd, Z=>SPIMISOIout_out); + SPIMOSII_buf: BUFBA + port map (A=>SPIMOSIIin_ipd, Z=>SPIMOSIIout_out); + SPISCSN_buf: BUFBA + port map (A=>SPISCSNin_ipd, Z=>SPISCSNout_out); + TCCLKI_buf: BUFBA + port map (A=>TCCLKIin_ipd, Z=>TCCLKIout_out); + TCRSTN_buf: BUFBA + port map (A=>TCRSTNin_ipd, Z=>TCRSTNout_out); + TCIC_buf: BUFBA + port map (A=>TCICin_ipd, Z=>TCICout_out); + UFMSN_buf: BUFBA + port map (A=>UFMSNin_ipd, Z=>UFMSNout_out); + WBDATO7_buf: BUFBA + port map (A=>WBDATO7in_ipd, Z=>WBDATO7out_out); + WBDATO6_buf: BUFBA + port map (A=>WBDATO6in_ipd, Z=>WBDATO6out_out); + WBDATO5_buf: BUFBA + port map (A=>WBDATO5in_ipd, Z=>WBDATO5out_out); + WBDATO4_buf: BUFBA + port map (A=>WBDATO4in_ipd, Z=>WBDATO4out_out); + WBDATO3_buf: BUFBA + port map (A=>WBDATO3in_ipd, Z=>WBDATO3out_out); + WBDATO2_buf: BUFBA + port map (A=>WBDATO2in_ipd, Z=>WBDATO2out_out); + WBDATO1_buf: BUFBA + port map (A=>WBDATO1in_ipd, Z=>WBDATO1out_out); + WBDATO0_buf: BUFBA + port map (A=>WBDATO0in_ipd, Z=>WBDATO0out_out); + WBACKO_buf: BUFBA + port map (A=>WBACKOin_ipd, Z=>WBACKOout_out); + PLLCLKO_buf: BUFBA + port map (A=>PLLCLKOin_ipd, Z=>PLLCLKOout_out); + PLLRSTO_buf: BUFBA + port map (A=>PLLRSTOin_ipd, Z=>PLLRSTOout_out); + PLL0STBO_buf: BUFBA + port map (A=>PLL0STBOin_ipd, Z=>PLL0STBOout_out); + PLL1STBO_buf: BUFBA + port map (A=>PLL1STBOin_ipd, Z=>PLL1STBOout_out); + PLLWEO_buf: BUFBA + port map (A=>PLLWEOin_ipd, Z=>PLLWEOout_out); + PLLADRO4_buf: BUFBA + port map (A=>PLLADRO4in_ipd, Z=>PLLADRO4out_out); + PLLADRO3_buf: BUFBA + port map (A=>PLLADRO3in_ipd, Z=>PLLADRO3out_out); + PLLADRO2_buf: BUFBA + port map (A=>PLLADRO2in_ipd, Z=>PLLADRO2out_out); + PLLADRO1_buf: BUFBA + port map (A=>PLLADRO1in_ipd, Z=>PLLADRO1out_out); + PLLADRO0_buf: BUFBA + port map (A=>PLLADRO0in_ipd, Z=>PLLADRO0out_out); + PLLDATO7_buf: BUFBA + port map (A=>PLLDATO7in_ipd, Z=>PLLDATO7out_out); + PLLDATO6_buf: BUFBA + port map (A=>PLLDATO6in_ipd, Z=>PLLDATO6out_out); + PLLDATO5_buf: BUFBA + port map (A=>PLLDATO5in_ipd, Z=>PLLDATO5out_out); + PLLDATO4_buf: BUFBA + port map (A=>PLLDATO4in_ipd, Z=>PLLDATO4out_out); + PLLDATO3_buf: BUFBA + port map (A=>PLLDATO3in_ipd, Z=>PLLDATO3out_out); + PLLDATO2_buf: BUFBA + port map (A=>PLLDATO2in_ipd, Z=>PLLDATO2out_out); + PLLDATO1_buf: BUFBA + port map (A=>PLLDATO1in_ipd, Z=>PLLDATO1out_out); + PLLDATO0_buf: BUFBA + port map (A=>PLLDATO0in_ipd, Z=>PLLDATO0out_out); + I2C1SCLO_buf: BUFBA + port map (A=>I2C1SCLOin_ipd, Z=>I2C1SCLOout_out); + I2C1SCLOEN_buf: BUFBA + port map (A=>I2C1SCLOENin_ipd, Z=>I2C1SCLOENout_out); + I2C1SDAO_buf: BUFBA + port map (A=>I2C1SDAOin_ipd, Z=>I2C1SDAOout_out); + I2C1SDAOEN_buf: BUFBA + port map (A=>I2C1SDAOENin_ipd, Z=>I2C1SDAOENout_out); + I2C2SCLO_buf: BUFBA + port map (A=>I2C2SCLOin_ipd, Z=>I2C2SCLOout_out); + I2C2SCLOEN_buf: BUFBA + port map (A=>I2C2SCLOENin_ipd, Z=>I2C2SCLOENout_out); + I2C2SDAO_buf: BUFBA + port map (A=>I2C2SDAOin_ipd, Z=>I2C2SDAOout_out); + I2C2SDAOEN_buf: BUFBA + port map (A=>I2C2SDAOENin_ipd, Z=>I2C2SDAOENout_out); + I2C1IRQO_buf: BUFBA + port map (A=>I2C1IRQOin_ipd, Z=>I2C1IRQOout_out); + I2C2IRQO_buf: BUFBA + port map (A=>I2C2IRQOin_ipd, Z=>I2C2IRQOout_out); + SPISCKO_buf: BUFBA + port map (A=>SPISCKOin_ipd, Z=>SPISCKOout_out); + SPISCKEN_buf: BUFBA + port map (A=>SPISCKENin_ipd, Z=>SPISCKENout_out); + SPIMISOO_buf: BUFBA + port map (A=>SPIMISOOin_ipd, Z=>SPIMISOOout_out); + SPIMISOEN_buf: BUFBA + port map (A=>SPIMISOENin_ipd, Z=>SPIMISOENout_out); + SPIMOSIO_buf: BUFBA + port map (A=>SPIMOSIOin_ipd, Z=>SPIMOSIOout_out); + SPIMOSIEN_buf: BUFBA + port map (A=>SPIMOSIENin_ipd, Z=>SPIMOSIENout_out); + SPIMCSN0_buf: BUFBA + port map (A=>SPIMCSN0in_ipd, Z=>SPIMCSN0out_out); + SPIMCSN1_buf: BUFBA + port map (A=>SPIMCSN1in_ipd, Z=>SPIMCSN1out_out); + SPIMCSN2_buf: BUFBA + port map (A=>SPIMCSN2in_ipd, Z=>SPIMCSN2out_out); + SPIMCSN3_buf: BUFBA + port map (A=>SPIMCSN3in_ipd, Z=>SPIMCSN3out_out); + SPIMCSN4_buf: BUFBA + port map (A=>SPIMCSN4in_ipd, Z=>SPIMCSN4out_out); + SPIMCSN5_buf: BUFBA + port map (A=>SPIMCSN5in_ipd, Z=>SPIMCSN5out_out); + SPIMCSN6_buf: BUFBA + port map (A=>SPIMCSN6in_ipd, Z=>SPIMCSN6out_out); + SPIMCSN7_buf: BUFBA + port map (A=>SPIMCSN7in_ipd, Z=>SPIMCSN7out_out); + SPICSNEN_buf: BUFBA + port map (A=>SPICSNENin_ipd, Z=>SPICSNENout_out); + SPIIRQO_buf: BUFBA + port map (A=>SPIIRQOin_ipd, Z=>SPIIRQOout_out); + TCINT_buf: BUFBA + port map (A=>TCINTin_ipd, Z=>TCINTout_out); + TCOC_buf: BUFBA + port map (A=>TCOCin_ipd, Z=>TCOCout_out); + WBCUFMIRQ_buf: BUFBA + port map (A=>WBCUFMIRQin_ipd, Z=>WBCUFMIRQout_out); + CFGWAKE_buf: BUFBA + port map (A=>CFGWAKEin_ipd, Z=>CFGWAKEout_out); + CFGSTDBY_buf: BUFBA + port map (A=>CFGSTDBYin_ipd, Z=>CFGSTDBYout_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(WBCLKIin_ipd, WBCLKIin, tipd_WBCLKIin); + VitalWireDelay(WBRSTIin_ipd, WBRSTIin, tipd_WBRSTIin); + VitalWireDelay(WBCYCIin_ipd, WBCYCIin, tipd_WBCYCIin); + VitalWireDelay(WBSTBIin_ipd, WBSTBIin, tipd_WBSTBIin); + VitalWireDelay(WBWEIin_ipd, WBWEIin, tipd_WBWEIin); + VitalWireDelay(WBADRI7in_ipd, WBADRI7in, tipd_WBADRI7in); + VitalWireDelay(WBADRI6in_ipd, WBADRI6in, tipd_WBADRI6in); + VitalWireDelay(WBADRI5in_ipd, WBADRI5in, tipd_WBADRI5in); + VitalWireDelay(WBADRI4in_ipd, WBADRI4in, tipd_WBADRI4in); + VitalWireDelay(WBADRI3in_ipd, WBADRI3in, tipd_WBADRI3in); + VitalWireDelay(WBADRI2in_ipd, WBADRI2in, tipd_WBADRI2in); + VitalWireDelay(WBADRI1in_ipd, WBADRI1in, tipd_WBADRI1in); + VitalWireDelay(WBADRI0in_ipd, WBADRI0in, tipd_WBADRI0in); + VitalWireDelay(WBDATI7in_ipd, WBDATI7in, tipd_WBDATI7in); + VitalWireDelay(WBDATI6in_ipd, WBDATI6in, tipd_WBDATI6in); + VitalWireDelay(WBDATI5in_ipd, WBDATI5in, tipd_WBDATI5in); + VitalWireDelay(WBDATI4in_ipd, WBDATI4in, tipd_WBDATI4in); + VitalWireDelay(WBDATI3in_ipd, WBDATI3in, tipd_WBDATI3in); + VitalWireDelay(WBDATI2in_ipd, WBDATI2in, tipd_WBDATI2in); + VitalWireDelay(WBDATI1in_ipd, WBDATI1in, tipd_WBDATI1in); + VitalWireDelay(WBDATI0in_ipd, WBDATI0in, tipd_WBDATI0in); + VitalWireDelay(PLL0DATI7in_ipd, PLL0DATI7in, tipd_PLL0DATI7in); + VitalWireDelay(PLL0DATI6in_ipd, PLL0DATI6in, tipd_PLL0DATI6in); + VitalWireDelay(PLL0DATI5in_ipd, PLL0DATI5in, tipd_PLL0DATI5in); + VitalWireDelay(PLL0DATI4in_ipd, PLL0DATI4in, tipd_PLL0DATI4in); + VitalWireDelay(PLL0DATI3in_ipd, PLL0DATI3in, tipd_PLL0DATI3in); + VitalWireDelay(PLL0DATI2in_ipd, PLL0DATI2in, tipd_PLL0DATI2in); + VitalWireDelay(PLL0DATI1in_ipd, PLL0DATI1in, tipd_PLL0DATI1in); + VitalWireDelay(PLL0DATI0in_ipd, PLL0DATI0in, tipd_PLL0DATI0in); + VitalWireDelay(PLL0ACKIin_ipd, PLL0ACKIin, tipd_PLL0ACKIin); + VitalWireDelay(PLL1DATI7in_ipd, PLL1DATI7in, tipd_PLL1DATI7in); + VitalWireDelay(PLL1DATI6in_ipd, PLL1DATI6in, tipd_PLL1DATI6in); + VitalWireDelay(PLL1DATI5in_ipd, PLL1DATI5in, tipd_PLL1DATI5in); + VitalWireDelay(PLL1DATI4in_ipd, PLL1DATI4in, tipd_PLL1DATI4in); + VitalWireDelay(PLL1DATI3in_ipd, PLL1DATI3in, tipd_PLL1DATI3in); + VitalWireDelay(PLL1DATI2in_ipd, PLL1DATI2in, tipd_PLL1DATI2in); + VitalWireDelay(PLL1DATI1in_ipd, PLL1DATI1in, tipd_PLL1DATI1in); + VitalWireDelay(PLL1DATI0in_ipd, PLL1DATI0in, tipd_PLL1DATI0in); + VitalWireDelay(PLL1ACKIin_ipd, PLL1ACKIin, tipd_PLL1ACKIin); + VitalWireDelay(I2C1SCLIin_ipd, I2C1SCLIin, tipd_I2C1SCLIin); + VitalWireDelay(I2C1SDAIin_ipd, I2C1SDAIin, tipd_I2C1SDAIin); + VitalWireDelay(I2C2SCLIin_ipd, I2C2SCLIin, tipd_I2C2SCLIin); + VitalWireDelay(I2C2SDAIin_ipd, I2C2SDAIin, tipd_I2C2SDAIin); + VitalWireDelay(SPISCKIin_ipd, SPISCKIin, tipd_SPISCKIin); + VitalWireDelay(SPIMISOIin_ipd, SPIMISOIin, tipd_SPIMISOIin); + VitalWireDelay(SPIMOSIIin_ipd, SPIMOSIIin, tipd_SPIMOSIIin); + VitalWireDelay(SPISCSNin_ipd, SPISCSNin, tipd_SPISCSNin); + VitalWireDelay(TCCLKIin_ipd, TCCLKIin, tipd_TCCLKIin); + VitalWireDelay(TCRSTNin_ipd, TCRSTNin, tipd_TCRSTNin); + VitalWireDelay(TCICin_ipd, TCICin, tipd_TCICin); + VitalWireDelay(UFMSNin_ipd, UFMSNin, tipd_UFMSNin); + VitalWireDelay(WBDATO7in_ipd, WBDATO7in, tipd_WBDATO7in); + VitalWireDelay(WBDATO6in_ipd, WBDATO6in, tipd_WBDATO6in); + VitalWireDelay(WBDATO5in_ipd, WBDATO5in, tipd_WBDATO5in); + VitalWireDelay(WBDATO4in_ipd, WBDATO4in, tipd_WBDATO4in); + VitalWireDelay(WBDATO3in_ipd, WBDATO3in, tipd_WBDATO3in); + VitalWireDelay(WBDATO2in_ipd, WBDATO2in, tipd_WBDATO2in); + VitalWireDelay(WBDATO1in_ipd, WBDATO1in, tipd_WBDATO1in); + VitalWireDelay(WBDATO0in_ipd, WBDATO0in, tipd_WBDATO0in); + VitalWireDelay(WBACKOin_ipd, WBACKOin, tipd_WBACKOin); + VitalWireDelay(PLLCLKOin_ipd, PLLCLKOin, tipd_PLLCLKOin); + VitalWireDelay(PLLRSTOin_ipd, PLLRSTOin, tipd_PLLRSTOin); + VitalWireDelay(PLL0STBOin_ipd, PLL0STBOin, tipd_PLL0STBOin); + VitalWireDelay(PLL1STBOin_ipd, PLL1STBOin, tipd_PLL1STBOin); + VitalWireDelay(PLLWEOin_ipd, PLLWEOin, tipd_PLLWEOin); + VitalWireDelay(PLLADRO4in_ipd, PLLADRO4in, tipd_PLLADRO4in); + VitalWireDelay(PLLADRO3in_ipd, PLLADRO3in, tipd_PLLADRO3in); + VitalWireDelay(PLLADRO2in_ipd, PLLADRO2in, tipd_PLLADRO2in); + VitalWireDelay(PLLADRO1in_ipd, PLLADRO1in, tipd_PLLADRO1in); + VitalWireDelay(PLLADRO0in_ipd, PLLADRO0in, tipd_PLLADRO0in); + VitalWireDelay(PLLDATO7in_ipd, PLLDATO7in, tipd_PLLDATO7in); + VitalWireDelay(PLLDATO6in_ipd, PLLDATO6in, tipd_PLLDATO6in); + VitalWireDelay(PLLDATO5in_ipd, PLLDATO5in, tipd_PLLDATO5in); + VitalWireDelay(PLLDATO4in_ipd, PLLDATO4in, tipd_PLLDATO4in); + VitalWireDelay(PLLDATO3in_ipd, PLLDATO3in, tipd_PLLDATO3in); + VitalWireDelay(PLLDATO2in_ipd, PLLDATO2in, tipd_PLLDATO2in); + VitalWireDelay(PLLDATO1in_ipd, PLLDATO1in, tipd_PLLDATO1in); + VitalWireDelay(PLLDATO0in_ipd, PLLDATO0in, tipd_PLLDATO0in); + VitalWireDelay(I2C1SCLOin_ipd, I2C1SCLOin, tipd_I2C1SCLOin); + VitalWireDelay(I2C1SCLOENin_ipd, I2C1SCLOENin, tipd_I2C1SCLOENin); + VitalWireDelay(I2C1SDAOin_ipd, I2C1SDAOin, tipd_I2C1SDAOin); + VitalWireDelay(I2C1SDAOENin_ipd, I2C1SDAOENin, tipd_I2C1SDAOENin); + VitalWireDelay(I2C2SCLOin_ipd, I2C2SCLOin, tipd_I2C2SCLOin); + VitalWireDelay(I2C2SCLOENin_ipd, I2C2SCLOENin, tipd_I2C2SCLOENin); + VitalWireDelay(I2C2SDAOin_ipd, I2C2SDAOin, tipd_I2C2SDAOin); + VitalWireDelay(I2C2SDAOENin_ipd, I2C2SDAOENin, tipd_I2C2SDAOENin); + VitalWireDelay(I2C1IRQOin_ipd, I2C1IRQOin, tipd_I2C1IRQOin); + VitalWireDelay(I2C2IRQOin_ipd, I2C2IRQOin, tipd_I2C2IRQOin); + VitalWireDelay(SPISCKOin_ipd, SPISCKOin, tipd_SPISCKOin); + VitalWireDelay(SPISCKENin_ipd, SPISCKENin, tipd_SPISCKENin); + VitalWireDelay(SPIMISOOin_ipd, SPIMISOOin, tipd_SPIMISOOin); + VitalWireDelay(SPIMISOENin_ipd, SPIMISOENin, tipd_SPIMISOENin); + VitalWireDelay(SPIMOSIOin_ipd, SPIMOSIOin, tipd_SPIMOSIOin); + VitalWireDelay(SPIMOSIENin_ipd, SPIMOSIENin, tipd_SPIMOSIENin); + VitalWireDelay(SPIMCSN0in_ipd, SPIMCSN0in, tipd_SPIMCSN0in); + VitalWireDelay(SPIMCSN1in_ipd, SPIMCSN1in, tipd_SPIMCSN1in); + VitalWireDelay(SPIMCSN2in_ipd, SPIMCSN2in, tipd_SPIMCSN2in); + VitalWireDelay(SPIMCSN3in_ipd, SPIMCSN3in, tipd_SPIMCSN3in); + VitalWireDelay(SPIMCSN4in_ipd, SPIMCSN4in, tipd_SPIMCSN4in); + VitalWireDelay(SPIMCSN5in_ipd, SPIMCSN5in, tipd_SPIMCSN5in); + VitalWireDelay(SPIMCSN6in_ipd, SPIMCSN6in, tipd_SPIMCSN6in); + VitalWireDelay(SPIMCSN7in_ipd, SPIMCSN7in, tipd_SPIMCSN7in); + VitalWireDelay(SPICSNENin_ipd, SPICSNENin, tipd_SPICSNENin); + VitalWireDelay(SPIIRQOin_ipd, SPIIRQOin, tipd_SPIIRQOin); + VitalWireDelay(TCINTin_ipd, TCINTin, tipd_TCINTin); + VitalWireDelay(TCOCin_ipd, TCOCin, tipd_TCOCin); + VitalWireDelay(WBCUFMIRQin_ipd, WBCUFMIRQin, tipd_WBCUFMIRQin); + VitalWireDelay(CFGWAKEin_ipd, CFGWAKEin, tipd_CFGWAKEin); + VitalWireDelay(CFGSTDBYin_ipd, CFGSTDBYin, tipd_CFGSTDBYin); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(WBCLKIin_dly, WBCLKIin_ipd, ticd_WBCLKIin); + VitalSignalDelay(WBRSTIin_dly, WBRSTIin_ipd, tisd_WBRSTIin_WBCLKIin); + VitalSignalDelay(WBCYCIin_dly, WBCYCIin_ipd, tisd_WBCYCIin_WBCLKIin); + VitalSignalDelay(WBSTBIin_dly, WBSTBIin_ipd, tisd_WBSTBIin_WBCLKIin); + VitalSignalDelay(WBWEIin_dly, WBWEIin_ipd, tisd_WBWEIin_WBCLKIin); + VitalSignalDelay(WBADRI7in_dly, WBADRI7in_ipd, tisd_WBADRI7in_WBCLKIin); + VitalSignalDelay(WBADRI6in_dly, WBADRI6in_ipd, tisd_WBADRI6in_WBCLKIin); + VitalSignalDelay(WBADRI5in_dly, WBADRI5in_ipd, tisd_WBADRI5in_WBCLKIin); + VitalSignalDelay(WBADRI4in_dly, WBADRI4in_ipd, tisd_WBADRI4in_WBCLKIin); + VitalSignalDelay(WBADRI3in_dly, WBADRI3in_ipd, tisd_WBADRI3in_WBCLKIin); + VitalSignalDelay(WBADRI2in_dly, WBADRI2in_ipd, tisd_WBADRI2in_WBCLKIin); + VitalSignalDelay(WBADRI1in_dly, WBADRI1in_ipd, tisd_WBADRI1in_WBCLKIin); + VitalSignalDelay(WBADRI0in_dly, WBADRI0in_ipd, tisd_WBADRI0in_WBCLKIin); + VitalSignalDelay(WBDATI7in_dly, WBDATI7in_ipd, tisd_WBDATI7in_WBCLKIin); + VitalSignalDelay(WBDATI6in_dly, WBDATI6in_ipd, tisd_WBDATI6in_WBCLKIin); + VitalSignalDelay(WBDATI5in_dly, WBDATI5in_ipd, tisd_WBDATI5in_WBCLKIin); + VitalSignalDelay(WBDATI4in_dly, WBDATI4in_ipd, tisd_WBDATI4in_WBCLKIin); + VitalSignalDelay(WBDATI3in_dly, WBDATI3in_ipd, tisd_WBDATI3in_WBCLKIin); + VitalSignalDelay(WBDATI2in_dly, WBDATI2in_ipd, tisd_WBDATI2in_WBCLKIin); + VitalSignalDelay(WBDATI1in_dly, WBDATI1in_ipd, tisd_WBDATI1in_WBCLKIin); + VitalSignalDelay(WBDATI0in_dly, WBDATI0in_ipd, tisd_WBDATI0in_WBCLKIin); + END BLOCK; + + VitalBehavior : PROCESS (WBCLKIin_dly, WBCLKIout_out, WBRSTIin_dly, + WBRSTIout_out, WBCYCIin_dly, WBCYCIout_out, WBSTBIin_dly, WBSTBIout_out, + WBWEIin_dly, WBWEIout_out, WBADRI7in_dly, WBADRI7out_out, WBADRI6in_dly, + WBADRI6out_out, WBADRI5in_dly, WBADRI5out_out, WBADRI4in_dly, + WBADRI4out_out, WBADRI3in_dly, WBADRI3out_out, WBADRI2in_dly, + WBADRI2out_out, WBADRI1in_dly, WBADRI1out_out, WBADRI0in_dly, + WBADRI0out_out, WBDATI7in_dly, WBDATI7out_out, WBDATI6in_dly, + WBDATI6out_out, WBDATI5in_dly, WBDATI5out_out, WBDATI4in_dly, + WBDATI4out_out, WBDATI3in_dly, WBDATI3out_out, WBDATI2in_dly, + WBDATI2out_out, WBDATI1in_dly, WBDATI1out_out, WBDATI0in_dly, + WBDATI0out_out, PLL0DATI7in_ipd, PLL0DATI7out_out, PLL0DATI6in_ipd, + PLL0DATI6out_out, PLL0DATI5in_ipd, PLL0DATI5out_out, PLL0DATI4in_ipd, + PLL0DATI4out_out, PLL0DATI3in_ipd, PLL0DATI3out_out, PLL0DATI2in_ipd, + PLL0DATI2out_out, PLL0DATI1in_ipd, PLL0DATI1out_out, PLL0DATI0in_ipd, + PLL0DATI0out_out, PLL0ACKIin_ipd, PLL0ACKIout_out, PLL1DATI7in_ipd, + PLL1DATI7out_out, PLL1DATI6in_ipd, PLL1DATI6out_out, PLL1DATI5in_ipd, + PLL1DATI5out_out, PLL1DATI4in_ipd, PLL1DATI4out_out, PLL1DATI3in_ipd, + PLL1DATI3out_out, PLL1DATI2in_ipd, PLL1DATI2out_out, PLL1DATI1in_ipd, + PLL1DATI1out_out, PLL1DATI0in_ipd, PLL1DATI0out_out, PLL1ACKIin_ipd, + PLL1ACKIout_out, I2C1SCLIin_ipd, I2C1SCLIout_out, I2C1SDAIin_ipd, + I2C1SDAIout_out, I2C2SCLIin_ipd, I2C2SCLIout_out, I2C2SDAIin_ipd, + I2C2SDAIout_out, SPISCKIin_ipd, SPISCKIout_out, SPIMISOIin_ipd, + SPIMISOIout_out, SPIMOSIIin_ipd, SPIMOSIIout_out, SPISCSNin_ipd, + SPISCSNout_out, TCCLKIin_ipd, TCCLKIout_out, TCRSTNin_ipd, TCRSTNout_out, + TCICin_ipd, TCICout_out, UFMSNin_ipd, UFMSNout_out, WBDATO7out_out, + WBDATO7in_ipd, WBDATO6out_out, WBDATO6in_ipd, WBDATO5out_out, + WBDATO5in_ipd, WBDATO4out_out, WBDATO4in_ipd, WBDATO3out_out, + WBDATO3in_ipd, WBDATO2out_out, WBDATO2in_ipd, WBDATO1out_out, + WBDATO1in_ipd, WBDATO0out_out, WBDATO0in_ipd, WBACKOout_out, + WBACKOin_ipd, PLLCLKOout_out, PLLCLKOin_ipd, PLLRSTOout_out, + PLLRSTOin_ipd, PLL0STBOout_out, PLL0STBOin_ipd, PLL1STBOout_out, + PLL1STBOin_ipd, PLLWEOout_out, PLLWEOin_ipd, PLLADRO4out_out, + PLLADRO4in_ipd, PLLADRO3out_out, PLLADRO3in_ipd, PLLADRO2out_out, + PLLADRO2in_ipd, PLLADRO1out_out, PLLADRO1in_ipd, PLLADRO0out_out, + PLLADRO0in_ipd, PLLDATO7out_out, PLLDATO7in_ipd, PLLDATO6out_out, + PLLDATO6in_ipd, PLLDATO5out_out, PLLDATO5in_ipd, PLLDATO4out_out, + PLLDATO4in_ipd, PLLDATO3out_out, PLLDATO3in_ipd, PLLDATO2out_out, + PLLDATO2in_ipd, PLLDATO1out_out, PLLDATO1in_ipd, PLLDATO0out_out, + PLLDATO0in_ipd, I2C1SCLOout_out, I2C1SCLOin_ipd, I2C1SCLOENout_out, + I2C1SCLOENin_ipd, I2C1SDAOout_out, I2C1SDAOin_ipd, I2C1SDAOENout_out, + I2C1SDAOENin_ipd, I2C2SCLOout_out, I2C2SCLOin_ipd, I2C2SCLOENout_out, + I2C2SCLOENin_ipd, I2C2SDAOout_out, I2C2SDAOin_ipd, I2C2SDAOENout_out, + I2C2SDAOENin_ipd, I2C1IRQOout_out, I2C1IRQOin_ipd, I2C2IRQOout_out, + I2C2IRQOin_ipd, SPISCKOout_out, SPISCKOin_ipd, SPISCKENout_out, + SPISCKENin_ipd, SPIMISOOout_out, SPIMISOOin_ipd, SPIMISOENout_out, + SPIMISOENin_ipd, SPIMOSIOout_out, SPIMOSIOin_ipd, SPIMOSIENout_out, + SPIMOSIENin_ipd, SPIMCSN0out_out, SPIMCSN0in_ipd, SPIMCSN1out_out, + SPIMCSN1in_ipd, SPIMCSN2out_out, SPIMCSN2in_ipd, SPIMCSN3out_out, + SPIMCSN3in_ipd, SPIMCSN4out_out, SPIMCSN4in_ipd, SPIMCSN5out_out, + SPIMCSN5in_ipd, SPIMCSN6out_out, SPIMCSN6in_ipd, SPIMCSN7out_out, + SPIMCSN7in_ipd, SPICSNENout_out, SPICSNENin_ipd, SPIIRQOout_out, + SPIIRQOin_ipd, TCINTout_out, TCINTin_ipd, TCOCout_out, TCOCin_ipd, + WBCUFMIRQout_out, WBCUFMIRQin_ipd, CFGWAKEout_out, CFGWAKEin_ipd, + CFGSTDBYout_out, CFGSTDBYin_ipd) + VARIABLE WBDATO1out_zd : std_logic := 'X'; + VARIABLE WBDATO1out_GlitchData : VitalGlitchDataType; + VARIABLE WBDATO0out_zd : std_logic := 'X'; + VARIABLE WBDATO0out_GlitchData : VitalGlitchDataType; + VARIABLE WBACKOout_zd : std_logic := 'X'; + VARIABLE WBACKOout_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_WBRSTIin_WBCLKIin : x01 := '0'; + VARIABLE WBRSTIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBCYCIin_WBCLKIin : x01 := '0'; + VARIABLE WBCYCIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBSTBIin_WBCLKIin : x01 := '0'; + VARIABLE WBSTBIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBWEIin_WBCLKIin : x01 := '0'; + VARIABLE WBWEIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI0in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI0in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI1in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI1in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI2in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI2in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI3in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI3in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI4in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI4in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI5in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI5in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI6in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI6in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI7in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI7in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI0in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI0in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI1in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI1in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI2in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI2in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI3in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI3in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI4in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI4in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI5in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI5in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI6in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI6in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI7in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI7in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBCLKIin_WBCLKIin : x01 := '0'; + VARIABLE periodcheckinfo_WBCLKIin : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => WBRSTIin_dly, + TestSignalName => "WBRSTIin", + TestDelay => tisd_WBRSTIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBRSTIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBRSTIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBRSTIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBRSTIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBRSTIin_WBCLKIin_TimingDatash, + Violation => tviol_WBRSTIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBCYCIin_dly, + TestSignalName => "WBCYCIin", + TestDelay => tisd_WBCYCIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBCYCIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBCYCIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBCYCIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBCYCIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBCYCIin_WBCLKIin_TimingDatash, + Violation => tviol_WBCYCIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBSTBIin_dly, + TestSignalName => "WBSTBIin", + TestDelay => tisd_WBSTBIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBSTBIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBSTBIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBSTBIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBSTBIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBSTBIin_WBCLKIin_TimingDatash, + Violation => tviol_WBSTBIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBWEIin_dly, + TestSignalName => "WBWEIin", + TestDelay => tisd_WBWEIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBWEIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBWEIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBWEIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBWEIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBWEIin_WBCLKIin_TimingDatash, + Violation => tviol_WBWEIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI0in_dly, + TestSignalName => "WBADRI0in", + TestDelay => tisd_WBADRI0in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI0in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI0in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI0in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI0in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI0in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI0in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI1in_dly, + TestSignalName => "WBADRI1in", + TestDelay => tisd_WBADRI1in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI1in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI1in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI1in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI1in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI1in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI1in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI2in_dly, + TestSignalName => "WBADRI2in", + TestDelay => tisd_WBADRI2in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI2in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI2in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI2in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI2in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI2in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI2in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI3in_dly, + TestSignalName => "WBADRI3in", + TestDelay => tisd_WBADRI3in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI3in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI3in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI3in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI3in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI3in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI3in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI4in_dly, + TestSignalName => "WBADRI4in", + TestDelay => tisd_WBADRI4in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI4in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI4in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI4in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI4in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI4in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI4in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI5in_dly, + TestSignalName => "WBADRI5in", + TestDelay => tisd_WBADRI5in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI5in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI5in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI5in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI5in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI5in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI5in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI6in_dly, + TestSignalName => "WBADRI6in", + TestDelay => tisd_WBADRI6in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI6in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI6in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI6in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI6in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI6in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI6in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI7in_dly, + TestSignalName => "WBADRI7in", + TestDelay => tisd_WBADRI7in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI7in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI7in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI7in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI7in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI7in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI7in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI0in_dly, + TestSignalName => "WBDATI0in", + TestDelay => tisd_WBDATI0in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI0in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI0in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI0in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI0in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI0in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI0in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI1in_dly, + TestSignalName => "WBDATI1in", + TestDelay => tisd_WBDATI1in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI1in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI1in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI1in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI1in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI1in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI1in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI2in_dly, + TestSignalName => "WBDATI2in", + TestDelay => tisd_WBDATI2in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI2in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI2in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI2in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI2in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI2in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI2in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI3in_dly, + TestSignalName => "WBDATI3in", + TestDelay => tisd_WBDATI3in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI3in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI3in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI3in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI3in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI3in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI3in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI4in_dly, + TestSignalName => "WBDATI4in", + TestDelay => tisd_WBDATI4in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI4in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI4in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI4in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI4in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI4in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI4in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI5in_dly, + TestSignalName => "WBDATI5in", + TestDelay => tisd_WBDATI5in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI5in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI5in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI5in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI5in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI5in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI5in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI6in_dly, + TestSignalName => "WBDATI6in", + TestDelay => tisd_WBDATI6in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI6in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI6in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI6in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI6in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI6in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI6in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI7in_dly, + TestSignalName => "WBDATI7in", + TestDelay => tisd_WBDATI7in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI7in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI7in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI7in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI7in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI7in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI7in_WBCLKIin, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => WBCLKIin_ipd, + TestSignalName => "WBCLKIin", + Period => tperiod_WBCLKIin, + PulseWidthHigh => tpw_WBCLKIin_posedge, + PulseWidthLow => tpw_WBCLKIin_negedge, + PeriodData => periodcheckinfo_WBCLKIin, + Violation => tviol_WBCLKIin_WBCLKIin, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + WBCLKIout <= WBCLKIout_out; + WBRSTIout <= WBRSTIout_out; + WBCYCIout <= WBCYCIout_out; + WBSTBIout <= WBSTBIout_out; + WBWEIout <= WBWEIout_out; + WBADRI7out <= WBADRI7out_out; + WBADRI6out <= WBADRI6out_out; + WBADRI5out <= WBADRI5out_out; + WBADRI4out <= WBADRI4out_out; + WBADRI3out <= WBADRI3out_out; + WBADRI2out <= WBADRI2out_out; + WBADRI1out <= WBADRI1out_out; + WBADRI0out <= WBADRI0out_out; + WBDATI7out <= WBDATI7out_out; + WBDATI6out <= WBDATI6out_out; + WBDATI5out <= WBDATI5out_out; + WBDATI4out <= WBDATI4out_out; + WBDATI3out <= WBDATI3out_out; + WBDATI2out <= WBDATI2out_out; + WBDATI1out <= WBDATI1out_out; + WBDATI0out <= WBDATI0out_out; + PLL0DATI7out <= PLL0DATI7out_out; + PLL0DATI6out <= PLL0DATI6out_out; + PLL0DATI5out <= PLL0DATI5out_out; + PLL0DATI4out <= PLL0DATI4out_out; + PLL0DATI3out <= PLL0DATI3out_out; + PLL0DATI2out <= PLL0DATI2out_out; + PLL0DATI1out <= PLL0DATI1out_out; + PLL0DATI0out <= PLL0DATI0out_out; + PLL0ACKIout <= PLL0ACKIout_out; + PLL1DATI7out <= PLL1DATI7out_out; + PLL1DATI6out <= PLL1DATI6out_out; + PLL1DATI5out <= PLL1DATI5out_out; + PLL1DATI4out <= PLL1DATI4out_out; + PLL1DATI3out <= PLL1DATI3out_out; + PLL1DATI2out <= PLL1DATI2out_out; + PLL1DATI1out <= PLL1DATI1out_out; + PLL1DATI0out <= PLL1DATI0out_out; + PLL1ACKIout <= PLL1ACKIout_out; + I2C1SCLIout <= I2C1SCLIout_out; + I2C1SDAIout <= I2C1SDAIout_out; + I2C2SCLIout <= I2C2SCLIout_out; + I2C2SDAIout <= I2C2SDAIout_out; + SPISCKIout <= SPISCKIout_out; + SPIMISOIout <= SPIMISOIout_out; + SPIMOSIIout <= SPIMOSIIout_out; + SPISCSNout <= SPISCSNout_out; + TCCLKIout <= TCCLKIout_out; + TCRSTNout <= TCRSTNout_out; + TCICout <= TCICout_out; + UFMSNout <= UFMSNout_out; + WBDATO7out <= WBDATO7out_out; + WBDATO6out <= WBDATO6out_out; + WBDATO5out <= WBDATO5out_out; + WBDATO4out <= WBDATO4out_out; + WBDATO3out <= WBDATO3out_out; + WBDATO2out <= WBDATO2out_out; + WBDATO1out_zd := WBDATO1out_out; + WBDATO0out_zd := WBDATO0out_out; + WBACKOout_zd := WBACKOout_out; + PLLCLKOout <= PLLCLKOout_out; + PLLRSTOout <= PLLRSTOout_out; + PLL0STBOout <= PLL0STBOout_out; + PLL1STBOout <= PLL1STBOout_out; + PLLWEOout <= PLLWEOout_out; + PLLADRO4out <= PLLADRO4out_out; + PLLADRO3out <= PLLADRO3out_out; + PLLADRO2out <= PLLADRO2out_out; + PLLADRO1out <= PLLADRO1out_out; + PLLADRO0out <= PLLADRO0out_out; + PLLDATO7out <= PLLDATO7out_out; + PLLDATO6out <= PLLDATO6out_out; + PLLDATO5out <= PLLDATO5out_out; + PLLDATO4out <= PLLDATO4out_out; + PLLDATO3out <= PLLDATO3out_out; + PLLDATO2out <= PLLDATO2out_out; + PLLDATO1out <= PLLDATO1out_out; + PLLDATO0out <= PLLDATO0out_out; + I2C1SCLOout <= I2C1SCLOout_out; + I2C1SCLOENout <= I2C1SCLOENout_out; + I2C1SDAOout <= I2C1SDAOout_out; + I2C1SDAOENout <= I2C1SDAOENout_out; + I2C2SCLOout <= I2C2SCLOout_out; + I2C2SCLOENout <= I2C2SCLOENout_out; + I2C2SDAOout <= I2C2SDAOout_out; + I2C2SDAOENout <= I2C2SDAOENout_out; + I2C1IRQOout <= I2C1IRQOout_out; + I2C2IRQOout <= I2C2IRQOout_out; + SPISCKOout <= SPISCKOout_out; + SPISCKENout <= SPISCKENout_out; + SPIMISOOout <= SPIMISOOout_out; + SPIMISOENout <= SPIMISOENout_out; + SPIMOSIOout <= SPIMOSIOout_out; + SPIMOSIENout <= SPIMOSIENout_out; + SPIMCSN0out <= SPIMCSN0out_out; + SPIMCSN1out <= SPIMCSN1out_out; + SPIMCSN2out <= SPIMCSN2out_out; + SPIMCSN3out <= SPIMCSN3out_out; + SPIMCSN4out <= SPIMCSN4out_out; + SPIMCSN5out <= SPIMCSN5out_out; + SPIMCSN6out <= SPIMCSN6out_out; + SPIMCSN7out <= SPIMCSN7out_out; + SPICSNENout <= SPICSNENout_out; + SPIIRQOout <= SPIIRQOout_out; + TCINTout <= TCINTout_out; + TCOCout <= TCOCout_out; + WBCUFMIRQout <= WBCUFMIRQout_out; + CFGWAKEout <= CFGWAKEout_out; + CFGSTDBYout <= CFGSTDBYout_out; + + VitalPathDelay01 ( + + OutSignal => WBDATO0out, OutSignalName => "WBDATO0out", OutTemp => WBDATO0out_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBDATO0out, + PathCondition => TRUE)), + GlitchData => WBDATO0out_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + + OutSignal => WBDATO1out, OutSignalName => "WBDATO1out", OutTemp => WBDATO1out_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBDATO1out, + PathCondition => TRUE)), + GlitchData => WBDATO1out_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => WBACKOout, OutSignalName => "WBACKOout", OutTemp => WBACKOout_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBACKOout, + PathCondition => TRUE)), + GlitchData => WBACKOout_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity EFBB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity EFBB is + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic; + WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic; + WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic; + WBDATO0: out Std_logic; WBDATO1: out Std_logic; + WBDATO2: out Std_logic; WBDATO3: out Std_logic; + WBDATO4: out Std_logic; WBDATO5: out Std_logic; + WBDATO6: out Std_logic; WBDATO7: out Std_logic; + WBACKO: out Std_logic; WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic; + CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic; + I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic; + I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic; + I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic; + I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic; + I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic; + I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic; + I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic; + SPISCKI: in Std_logic; SPISCKO: out Std_logic; + SPISCKEN: out Std_logic; SPIMISOI: in Std_logic; + SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic; + SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic; + SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic; + SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic; + SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic; + SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic; + SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic; + SPISCSN: in Std_logic; SPIIRQO: out Std_logic; TCCLKI: in Std_logic; + TCRSTN: in Std_logic; TCIC: in Std_logic; TCINT: out Std_logic; + TCOC: out Std_logic; PLLCLKO: out Std_logic; PLLRSTO: out Std_logic; + PLL0STBO: out Std_logic; PLL1STBO: out Std_logic; + PLLWEO: out Std_logic; PLLADRO0: out Std_logic; + PLLADRO1: out Std_logic; PLLADRO2: out Std_logic; + PLLADRO3: out Std_logic; PLLADRO4: out Std_logic; + PLLDATO0: out Std_logic; PLLDATO1: out Std_logic; + PLLDATO2: out Std_logic; PLLDATO3: out Std_logic; + PLLDATO4: out Std_logic; PLLDATO5: out Std_logic; + PLLDATO6: out Std_logic; PLLDATO7: out Std_logic; + PLL0DATI0: in Std_logic; PLL0DATI1: in Std_logic; + PLL0DATI2: in Std_logic; PLL0DATI3: in Std_logic; + PLL0DATI4: in Std_logic; PLL0DATI5: in Std_logic; + PLL0DATI6: in Std_logic; PLL0DATI7: in Std_logic; + PLL0ACKI: in Std_logic; PLL1DATI0: in Std_logic; + PLL1DATI1: in Std_logic; PLL1DATI2: in Std_logic; + PLL1DATI3: in Std_logic; PLL1DATI4: in Std_logic; + PLL1DATI5: in Std_logic; PLL1DATI6: in Std_logic; + PLL1DATI7: in Std_logic; PLL1ACKI: in Std_logic); + + + + end EFBB; + + architecture Structure of EFBB is + signal WBCLKI_buf: Std_logic; + signal WBRSTI_buf: Std_logic; + signal WBCYCI_buf: Std_logic; + signal WBSTBI_buf: Std_logic; + signal WBWEI_buf: Std_logic; + signal WBADRI7_buf: Std_logic; + signal WBADRI6_buf: Std_logic; + signal WBADRI5_buf: Std_logic; + signal WBADRI4_buf: Std_logic; + signal WBADRI3_buf: Std_logic; + signal WBADRI2_buf: Std_logic; + signal WBADRI1_buf: Std_logic; + signal WBADRI0_buf: Std_logic; + signal WBDATI7_buf: Std_logic; + signal WBDATI6_buf: Std_logic; + signal WBDATI5_buf: Std_logic; + signal WBDATI4_buf: Std_logic; + signal WBDATI3_buf: Std_logic; + signal WBDATI2_buf: Std_logic; + signal WBDATI1_buf: Std_logic; + signal WBDATI0_buf: Std_logic; + signal PLL0DATI7_buf: Std_logic; + signal PLL0DATI6_buf: Std_logic; + signal PLL0DATI5_buf: Std_logic; + signal PLL0DATI4_buf: Std_logic; + signal PLL0DATI3_buf: Std_logic; + signal PLL0DATI2_buf: Std_logic; + signal PLL0DATI1_buf: Std_logic; + signal PLL0DATI0_buf: Std_logic; + signal PLL0ACKI_buf: Std_logic; + signal PLL1DATI7_buf: Std_logic; + signal PLL1DATI6_buf: Std_logic; + signal PLL1DATI5_buf: Std_logic; + signal PLL1DATI4_buf: Std_logic; + signal PLL1DATI3_buf: Std_logic; + signal PLL1DATI2_buf: Std_logic; + signal PLL1DATI1_buf: Std_logic; + signal PLL1DATI0_buf: Std_logic; + signal PLL1ACKI_buf: Std_logic; + signal I2C1SCLI_buf: Std_logic; + signal I2C1SDAI_buf: Std_logic; + signal I2C2SCLI_buf: Std_logic; + signal I2C2SDAI_buf: Std_logic; + signal SPISCKI_buf: Std_logic; + signal SPIMISOI_buf: Std_logic; + signal SPIMOSII_buf: Std_logic; + signal SPISCSN_buf: Std_logic; + signal TCCLKI_buf: Std_logic; + signal TCRSTN_buf: Std_logic; + signal TCIC_buf: Std_logic; + signal UFMSN_buf: Std_logic; + signal WBDATO7_buf: Std_logic; + signal WBDATO6_buf: Std_logic; + signal WBDATO5_buf: Std_logic; + signal WBDATO4_buf: Std_logic; + signal WBDATO3_buf: Std_logic; + signal WBDATO2_buf: Std_logic; + signal WBDATO1_buf: Std_logic; + signal WBDATO0_buf: Std_logic; + signal WBACKO_buf: Std_logic; + signal PLLCLKO_buf: Std_logic; + signal PLLRSTO_buf: Std_logic; + signal PLL0STBO_buf: Std_logic; + signal PLL1STBO_buf: Std_logic; + signal PLLWEO_buf: Std_logic; + signal PLLADRO4_buf: Std_logic; + signal PLLADRO3_buf: Std_logic; + signal PLLADRO2_buf: Std_logic; + signal PLLADRO1_buf: Std_logic; + signal PLLADRO0_buf: Std_logic; + signal PLLDATO7_buf: Std_logic; + signal PLLDATO6_buf: Std_logic; + signal PLLDATO5_buf: Std_logic; + signal PLLDATO4_buf: Std_logic; + signal PLLDATO3_buf: Std_logic; + signal PLLDATO2_buf: Std_logic; + signal PLLDATO1_buf: Std_logic; + signal PLLDATO0_buf: Std_logic; + signal I2C1SCLO_buf: Std_logic; + signal I2C1SCLOEN_buf: Std_logic; + signal I2C1SDAO_buf: Std_logic; + signal I2C1SDAOEN_buf: Std_logic; + signal I2C2SCLO_buf: Std_logic; + signal I2C2SCLOEN_buf: Std_logic; + signal I2C2SDAO_buf: Std_logic; + signal I2C2SDAOEN_buf: Std_logic; + signal I2C1IRQO_buf: Std_logic; + signal I2C2IRQO_buf: Std_logic; + signal SPISCKO_buf: Std_logic; + signal SPISCKEN_buf: Std_logic; + signal SPIMISOO_buf: Std_logic; + signal SPIMISOEN_buf: Std_logic; + signal SPIMOSIO_buf: Std_logic; + signal SPIMOSIEN_buf: Std_logic; + signal SPIMCSN0_buf: Std_logic; + signal SPIMCSN1_buf: Std_logic; + signal SPIMCSN2_buf: Std_logic; + signal SPIMCSN3_buf: Std_logic; + signal SPIMCSN4_buf: Std_logic; + signal SPIMCSN5_buf: Std_logic; + signal SPIMCSN6_buf: Std_logic; + signal SPIMCSN7_buf: Std_logic; + signal SPICSNEN_buf: Std_logic; + signal SPIIRQO_buf: Std_logic; + signal TCINT_buf: Std_logic; + signal TCOC_buf: Std_logic; + signal WBCUFMIRQ_buf: Std_logic; + signal CFGWAKE_buf: Std_logic; + signal CFGSTDBY_buf: Std_logic; + component EFB_Buffer_Block + port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic; + WBRSTIin: in Std_logic; WBRSTIout: out Std_logic; + WBCYCIin: in Std_logic; WBCYCIout: out Std_logic; + WBSTBIin: in Std_logic; WBSTBIout: out Std_logic; + WBWEIin: in Std_logic; WBWEIout: out Std_logic; + WBADRI7in: in Std_logic; WBADRI7out: out Std_logic; + WBADRI6in: in Std_logic; WBADRI6out: out Std_logic; + WBADRI5in: in Std_logic; WBADRI5out: out Std_logic; + WBADRI4in: in Std_logic; WBADRI4out: out Std_logic; + WBADRI3in: in Std_logic; WBADRI3out: out Std_logic; + WBADRI2in: in Std_logic; WBADRI2out: out Std_logic; + WBADRI1in: in Std_logic; WBADRI1out: out Std_logic; + WBADRI0in: in Std_logic; WBADRI0out: out Std_logic; + WBDATI7in: in Std_logic; WBDATI7out: out Std_logic; + WBDATI6in: in Std_logic; WBDATI6out: out Std_logic; + WBDATI5in: in Std_logic; WBDATI5out: out Std_logic; + WBDATI4in: in Std_logic; WBDATI4out: out Std_logic; + WBDATI3in: in Std_logic; WBDATI3out: out Std_logic; + WBDATI2in: in Std_logic; WBDATI2out: out Std_logic; + WBDATI1in: in Std_logic; WBDATI1out: out Std_logic; + WBDATI0in: in Std_logic; WBDATI0out: out Std_logic; + PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic; + PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic; + PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic; + PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic; + PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic; + PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic; + PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic; + PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic; + PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic; + PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic; + PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic; + PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic; + PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic; + PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic; + PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic; + PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic; + PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic; + PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic; + I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic; + I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic; + I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic; + I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic; + SPISCKIin: in Std_logic; SPISCKIout: out Std_logic; + SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic; + SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic; + SPISCSNin: in Std_logic; SPISCSNout: out Std_logic; + TCCLKIin: in Std_logic; TCCLKIout: out Std_logic; + TCRSTNin: in Std_logic; TCRSTNout: out Std_logic; + TCICin: in Std_logic; TCICout: out Std_logic; + UFMSNin: in Std_logic; UFMSNout: out Std_logic; + WBDATO7out: out Std_logic; WBDATO7in: in Std_logic; + WBDATO6out: out Std_logic; WBDATO6in: in Std_logic; + WBDATO5out: out Std_logic; WBDATO5in: in Std_logic; + WBDATO4out: out Std_logic; WBDATO4in: in Std_logic; + WBDATO3out: out Std_logic; WBDATO3in: in Std_logic; + WBDATO2out: out Std_logic; WBDATO2in: in Std_logic; + WBDATO1out: out Std_logic; WBDATO1in: in Std_logic; + WBDATO0out: out Std_logic; WBDATO0in: in Std_logic; + WBACKOout: out Std_logic; WBACKOin: in Std_logic; + PLLCLKOout: out Std_logic; PLLCLKOin: in Std_logic; + PLLRSTOout: out Std_logic; PLLRSTOin: in Std_logic; + PLL0STBOout: out Std_logic; PLL0STBOin: in Std_logic; + PLL1STBOout: out Std_logic; PLL1STBOin: in Std_logic; + PLLWEOout: out Std_logic; PLLWEOin: in Std_logic; + PLLADRO4out: out Std_logic; PLLADRO4in: in Std_logic; + PLLADRO3out: out Std_logic; PLLADRO3in: in Std_logic; + PLLADRO2out: out Std_logic; PLLADRO2in: in Std_logic; + PLLADRO1out: out Std_logic; PLLADRO1in: in Std_logic; + PLLADRO0out: out Std_logic; PLLADRO0in: in Std_logic; + PLLDATO7out: out Std_logic; PLLDATO7in: in Std_logic; + PLLDATO6out: out Std_logic; PLLDATO6in: in Std_logic; + PLLDATO5out: out Std_logic; PLLDATO5in: in Std_logic; + PLLDATO4out: out Std_logic; PLLDATO4in: in Std_logic; + PLLDATO3out: out Std_logic; PLLDATO3in: in Std_logic; + PLLDATO2out: out Std_logic; PLLDATO2in: in Std_logic; + PLLDATO1out: out Std_logic; PLLDATO1in: in Std_logic; + PLLDATO0out: out Std_logic; PLLDATO0in: in Std_logic; + I2C1SCLOout: out Std_logic; I2C1SCLOin: in Std_logic; + I2C1SCLOENout: out Std_logic; I2C1SCLOENin: in Std_logic; + I2C1SDAOout: out Std_logic; I2C1SDAOin: in Std_logic; + I2C1SDAOENout: out Std_logic; I2C1SDAOENin: in Std_logic; + I2C2SCLOout: out Std_logic; I2C2SCLOin: in Std_logic; + I2C2SCLOENout: out Std_logic; I2C2SCLOENin: in Std_logic; + I2C2SDAOout: out Std_logic; I2C2SDAOin: in Std_logic; + I2C2SDAOENout: out Std_logic; I2C2SDAOENin: in Std_logic; + I2C1IRQOout: out Std_logic; I2C1IRQOin: in Std_logic; + I2C2IRQOout: out Std_logic; I2C2IRQOin: in Std_logic; + SPISCKOout: out Std_logic; SPISCKOin: in Std_logic; + SPISCKENout: out Std_logic; SPISCKENin: in Std_logic; + SPIMISOOout: out Std_logic; SPIMISOOin: in Std_logic; + SPIMISOENout: out Std_logic; SPIMISOENin: in Std_logic; + SPIMOSIOout: out Std_logic; SPIMOSIOin: in Std_logic; + SPIMOSIENout: out Std_logic; SPIMOSIENin: in Std_logic; + SPIMCSN0out: out Std_logic; SPIMCSN0in: in Std_logic; + SPIMCSN1out: out Std_logic; SPIMCSN1in: in Std_logic; + SPIMCSN2out: out Std_logic; SPIMCSN2in: in Std_logic; + SPIMCSN3out: out Std_logic; SPIMCSN3in: in Std_logic; + SPIMCSN4out: out Std_logic; SPIMCSN4in: in Std_logic; + SPIMCSN5out: out Std_logic; SPIMCSN5in: in Std_logic; + SPIMCSN6out: out Std_logic; SPIMCSN6in: in Std_logic; + SPIMCSN7out: out Std_logic; SPIMCSN7in: in Std_logic; + SPICSNENout: out Std_logic; SPICSNENin: in Std_logic; + SPIIRQOout: out Std_logic; SPIIRQOin: in Std_logic; + TCINTout: out Std_logic; TCINTin: in Std_logic; + TCOCout: out Std_logic; TCOCin: in Std_logic; + WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic; + CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic; + CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic); + end component; + begin + INST10: EFB + generic map (DEV_DENSITY => "640L", EFB_I2C1 => "DISABLED", + EFB_I2C2 => "DISABLED", EFB_SPI => "DISABLED", + EFB_TC => "DISABLED", EFB_TC_PORTMODE => "WB", + EFB_UFM => "ENABLED", EFB_WB_CLK_FREQ => "66.7", + GSR => "ENABLED", I2C1_ADDRESSING => "7BIT", + I2C1_BUS_PERF => "100kHz", I2C1_CLK_DIVIDER => 1, + I2C1_GEN_CALL => "DISABLED", I2C1_SLAVE_ADDR => "0b1000001", + I2C1_WAKEUP => "DISABLED", I2C2_ADDRESSING => "7BIT", + I2C2_BUS_PERF => "100kHz", I2C2_CLK_DIVIDER => 1, + I2C2_GEN_CALL => "DISABLED", I2C2_SLAVE_ADDR => "0b1000010", + I2C2_WAKEUP => "DISABLED", SPI_CLK_DIVIDER => 1, + SPI_CLK_INV => "DISABLED", SPI_INTR_RXOVR => "DISABLED", + SPI_INTR_RXRDY => "DISABLED", SPI_INTR_TXOVR => "DISABLED", + SPI_INTR_TXRDY => "DISABLED", SPI_LSB_FIRST => "DISABLED", + SPI_MODE => "MASTER", SPI_PHASE_ADJ => "DISABLED", + SPI_SLAVE_HANDSHAKE => "DISABLED", SPI_WAKEUP => "DISABLED", + TC_CCLK_SEL => 1, TC_ICAPTURE => "DISABLED", + TC_ICR_INT => "OFF", TC_MODE => "CTCM", TC_OCR_INT => "OFF", + TC_OCR_SET => 32767, TC_OC_MODE => "TOGGLE", + TC_OVERFLOW => "DISABLED", TC_OV_INT => "OFF", + TC_RESETN => "ENABLED", TC_SCLK_SEL => "PCLOCK", + TC_TOP_SEL => "OFF", TC_TOP_SET => 65535, + UFM_INIT_ALL_ZEROS => "DISABLED", + UFM_INIT_FILE_FORMAT => "HEX", + UFM_INIT_FILE_NAME => "../RAM2GS-LCMXO2.mem", + UFM_INIT_PAGES => 1, UFM_INIT_START_PAGE => 190) + port map (WBCLKI=>WBCLKI_buf, WBRSTI=>WBRSTI_buf, WBCYCI=>WBCYCI_buf, + WBSTBI=>WBSTBI_buf, WBWEI=>WBWEI_buf, WBADRI7=>WBADRI7_buf, + WBADRI6=>WBADRI6_buf, WBADRI5=>WBADRI5_buf, + WBADRI4=>WBADRI4_buf, WBADRI3=>WBADRI3_buf, + WBADRI2=>WBADRI2_buf, WBADRI1=>WBADRI1_buf, + WBADRI0=>WBADRI0_buf, WBDATI7=>WBDATI7_buf, + WBDATI6=>WBDATI6_buf, WBDATI5=>WBDATI5_buf, + WBDATI4=>WBDATI4_buf, WBDATI3=>WBDATI3_buf, + WBDATI2=>WBDATI2_buf, WBDATI1=>WBDATI1_buf, + WBDATI0=>WBDATI0_buf, PLL0DATI7=>PLL0DATI7_buf, + PLL0DATI6=>PLL0DATI6_buf, PLL0DATI5=>PLL0DATI5_buf, + PLL0DATI4=>PLL0DATI4_buf, PLL0DATI3=>PLL0DATI3_buf, + PLL0DATI2=>PLL0DATI2_buf, PLL0DATI1=>PLL0DATI1_buf, + PLL0DATI0=>PLL0DATI0_buf, PLL0ACKI=>PLL0ACKI_buf, + PLL1DATI7=>PLL1DATI7_buf, PLL1DATI6=>PLL1DATI6_buf, + PLL1DATI5=>PLL1DATI5_buf, PLL1DATI4=>PLL1DATI4_buf, + PLL1DATI3=>PLL1DATI3_buf, PLL1DATI2=>PLL1DATI2_buf, + PLL1DATI1=>PLL1DATI1_buf, PLL1DATI0=>PLL1DATI0_buf, + PLL1ACKI=>PLL1ACKI_buf, I2C1SCLI=>I2C1SCLI_buf, + I2C1SDAI=>I2C1SDAI_buf, I2C2SCLI=>I2C2SCLI_buf, + I2C2SDAI=>I2C2SDAI_buf, SPISCKI=>SPISCKI_buf, + SPIMISOI=>SPIMISOI_buf, SPIMOSII=>SPIMOSII_buf, + SPISCSN=>SPISCSN_buf, TCCLKI=>TCCLKI_buf, TCRSTN=>TCRSTN_buf, + TCIC=>TCIC_buf, UFMSN=>UFMSN_buf, WBDATO7=>WBDATO7_buf, + WBDATO6=>WBDATO6_buf, WBDATO5=>WBDATO5_buf, + WBDATO4=>WBDATO4_buf, WBDATO3=>WBDATO3_buf, + WBDATO2=>WBDATO2_buf, WBDATO1=>WBDATO1_buf, + WBDATO0=>WBDATO0_buf, WBACKO=>WBACKO_buf, PLLCLKO=>PLLCLKO_buf, + PLLRSTO=>PLLRSTO_buf, PLL0STBO=>PLL0STBO_buf, + PLL1STBO=>PLL1STBO_buf, PLLWEO=>PLLWEO_buf, + PLLADRO4=>PLLADRO4_buf, PLLADRO3=>PLLADRO3_buf, + PLLADRO2=>PLLADRO2_buf, PLLADRO1=>PLLADRO1_buf, + PLLADRO0=>PLLADRO0_buf, PLLDATO7=>PLLDATO7_buf, + PLLDATO6=>PLLDATO6_buf, PLLDATO5=>PLLDATO5_buf, + PLLDATO4=>PLLDATO4_buf, PLLDATO3=>PLLDATO3_buf, + PLLDATO2=>PLLDATO2_buf, PLLDATO1=>PLLDATO1_buf, + PLLDATO0=>PLLDATO0_buf, I2C1SCLO=>I2C1SCLO_buf, + I2C1SCLOEN=>I2C1SCLOEN_buf, I2C1SDAO=>I2C1SDAO_buf, + I2C1SDAOEN=>I2C1SDAOEN_buf, I2C2SCLO=>I2C2SCLO_buf, + I2C2SCLOEN=>I2C2SCLOEN_buf, I2C2SDAO=>I2C2SDAO_buf, + I2C2SDAOEN=>I2C2SDAOEN_buf, I2C1IRQO=>I2C1IRQO_buf, + I2C2IRQO=>I2C2IRQO_buf, SPISCKO=>SPISCKO_buf, + SPISCKEN=>SPISCKEN_buf, SPIMISOO=>SPIMISOO_buf, + SPIMISOEN=>SPIMISOEN_buf, SPIMOSIO=>SPIMOSIO_buf, + SPIMOSIEN=>SPIMOSIEN_buf, SPIMCSN0=>SPIMCSN0_buf, + SPIMCSN1=>SPIMCSN1_buf, SPIMCSN2=>SPIMCSN2_buf, + SPIMCSN3=>SPIMCSN3_buf, SPIMCSN4=>SPIMCSN4_buf, + SPIMCSN5=>SPIMCSN5_buf, SPIMCSN6=>SPIMCSN6_buf, + SPIMCSN7=>SPIMCSN7_buf, SPICSNEN=>SPICSNEN_buf, + SPIIRQO=>SPIIRQO_buf, TCINT=>TCINT_buf, TCOC=>TCOC_buf, + WBCUFMIRQ=>WBCUFMIRQ_buf, CFGWAKE=>CFGWAKE_buf, + CFGSTDBY=>CFGSTDBY_buf); + INST20: EFB_Buffer_Block + port map (WBCLKIin=>WBCLKI, WBCLKIout=>WBCLKI_buf, WBRSTIin=>WBRSTI, + WBRSTIout=>WBRSTI_buf, WBCYCIin=>WBCYCI, WBCYCIout=>WBCYCI_buf, + WBSTBIin=>WBSTBI, WBSTBIout=>WBSTBI_buf, WBWEIin=>WBWEI, + WBWEIout=>WBWEI_buf, WBADRI7in=>WBADRI7, + WBADRI7out=>WBADRI7_buf, WBADRI6in=>WBADRI6, + WBADRI6out=>WBADRI6_buf, WBADRI5in=>WBADRI5, + WBADRI5out=>WBADRI5_buf, WBADRI4in=>WBADRI4, + WBADRI4out=>WBADRI4_buf, WBADRI3in=>WBADRI3, + WBADRI3out=>WBADRI3_buf, WBADRI2in=>WBADRI2, + WBADRI2out=>WBADRI2_buf, WBADRI1in=>WBADRI1, + WBADRI1out=>WBADRI1_buf, WBADRI0in=>WBADRI0, + WBADRI0out=>WBADRI0_buf, WBDATI7in=>WBDATI7, + WBDATI7out=>WBDATI7_buf, WBDATI6in=>WBDATI6, + WBDATI6out=>WBDATI6_buf, WBDATI5in=>WBDATI5, + WBDATI5out=>WBDATI5_buf, WBDATI4in=>WBDATI4, + WBDATI4out=>WBDATI4_buf, WBDATI3in=>WBDATI3, + WBDATI3out=>WBDATI3_buf, WBDATI2in=>WBDATI2, + WBDATI2out=>WBDATI2_buf, WBDATI1in=>WBDATI1, + WBDATI1out=>WBDATI1_buf, WBDATI0in=>WBDATI0, + WBDATI0out=>WBDATI0_buf, PLL0DATI7in=>PLL0DATI7, + PLL0DATI7out=>PLL0DATI7_buf, PLL0DATI6in=>PLL0DATI6, + PLL0DATI6out=>PLL0DATI6_buf, PLL0DATI5in=>PLL0DATI5, + PLL0DATI5out=>PLL0DATI5_buf, PLL0DATI4in=>PLL0DATI4, + PLL0DATI4out=>PLL0DATI4_buf, PLL0DATI3in=>PLL0DATI3, + PLL0DATI3out=>PLL0DATI3_buf, PLL0DATI2in=>PLL0DATI2, + PLL0DATI2out=>PLL0DATI2_buf, PLL0DATI1in=>PLL0DATI1, + PLL0DATI1out=>PLL0DATI1_buf, PLL0DATI0in=>PLL0DATI0, + PLL0DATI0out=>PLL0DATI0_buf, PLL0ACKIin=>PLL0ACKI, + PLL0ACKIout=>PLL0ACKI_buf, PLL1DATI7in=>PLL1DATI7, + PLL1DATI7out=>PLL1DATI7_buf, PLL1DATI6in=>PLL1DATI6, + PLL1DATI6out=>PLL1DATI6_buf, PLL1DATI5in=>PLL1DATI5, + PLL1DATI5out=>PLL1DATI5_buf, PLL1DATI4in=>PLL1DATI4, + PLL1DATI4out=>PLL1DATI4_buf, PLL1DATI3in=>PLL1DATI3, + PLL1DATI3out=>PLL1DATI3_buf, PLL1DATI2in=>PLL1DATI2, + PLL1DATI2out=>PLL1DATI2_buf, PLL1DATI1in=>PLL1DATI1, + PLL1DATI1out=>PLL1DATI1_buf, PLL1DATI0in=>PLL1DATI0, + PLL1DATI0out=>PLL1DATI0_buf, PLL1ACKIin=>PLL1ACKI, + PLL1ACKIout=>PLL1ACKI_buf, I2C1SCLIin=>I2C1SCLI, + I2C1SCLIout=>I2C1SCLI_buf, I2C1SDAIin=>I2C1SDAI, + I2C1SDAIout=>I2C1SDAI_buf, I2C2SCLIin=>I2C2SCLI, + I2C2SCLIout=>I2C2SCLI_buf, I2C2SDAIin=>I2C2SDAI, + I2C2SDAIout=>I2C2SDAI_buf, SPISCKIin=>SPISCKI, + SPISCKIout=>SPISCKI_buf, SPIMISOIin=>SPIMISOI, + SPIMISOIout=>SPIMISOI_buf, SPIMOSIIin=>SPIMOSII, + SPIMOSIIout=>SPIMOSII_buf, SPISCSNin=>SPISCSN, + SPISCSNout=>SPISCSN_buf, TCCLKIin=>TCCLKI, + TCCLKIout=>TCCLKI_buf, TCRSTNin=>TCRSTN, TCRSTNout=>TCRSTN_buf, + TCICin=>TCIC, TCICout=>TCIC_buf, UFMSNin=>UFMSN, + UFMSNout=>UFMSN_buf, WBDATO7out=>WBDATO7, + WBDATO7in=>WBDATO7_buf, WBDATO6out=>WBDATO6, + WBDATO6in=>WBDATO6_buf, WBDATO5out=>WBDATO5, + WBDATO5in=>WBDATO5_buf, WBDATO4out=>WBDATO4, + WBDATO4in=>WBDATO4_buf, WBDATO3out=>WBDATO3, + WBDATO3in=>WBDATO3_buf, WBDATO2out=>WBDATO2, + WBDATO2in=>WBDATO2_buf, WBDATO1out=>WBDATO1, + WBDATO1in=>WBDATO1_buf, WBDATO0out=>WBDATO0, + WBDATO0in=>WBDATO0_buf, WBACKOout=>WBACKO, + WBACKOin=>WBACKO_buf, PLLCLKOout=>PLLCLKO, + PLLCLKOin=>PLLCLKO_buf, PLLRSTOout=>PLLRSTO, + PLLRSTOin=>PLLRSTO_buf, PLL0STBOout=>PLL0STBO, + PLL0STBOin=>PLL0STBO_buf, PLL1STBOout=>PLL1STBO, + PLL1STBOin=>PLL1STBO_buf, PLLWEOout=>PLLWEO, + PLLWEOin=>PLLWEO_buf, PLLADRO4out=>PLLADRO4, + PLLADRO4in=>PLLADRO4_buf, PLLADRO3out=>PLLADRO3, + PLLADRO3in=>PLLADRO3_buf, PLLADRO2out=>PLLADRO2, + PLLADRO2in=>PLLADRO2_buf, PLLADRO1out=>PLLADRO1, + PLLADRO1in=>PLLADRO1_buf, PLLADRO0out=>PLLADRO0, + PLLADRO0in=>PLLADRO0_buf, PLLDATO7out=>PLLDATO7, + PLLDATO7in=>PLLDATO7_buf, PLLDATO6out=>PLLDATO6, + PLLDATO6in=>PLLDATO6_buf, PLLDATO5out=>PLLDATO5, + PLLDATO5in=>PLLDATO5_buf, PLLDATO4out=>PLLDATO4, + PLLDATO4in=>PLLDATO4_buf, PLLDATO3out=>PLLDATO3, + PLLDATO3in=>PLLDATO3_buf, PLLDATO2out=>PLLDATO2, + PLLDATO2in=>PLLDATO2_buf, PLLDATO1out=>PLLDATO1, + PLLDATO1in=>PLLDATO1_buf, PLLDATO0out=>PLLDATO0, + PLLDATO0in=>PLLDATO0_buf, I2C1SCLOout=>I2C1SCLO, + I2C1SCLOin=>I2C1SCLO_buf, I2C1SCLOENout=>I2C1SCLOEN, + I2C1SCLOENin=>I2C1SCLOEN_buf, I2C1SDAOout=>I2C1SDAO, + I2C1SDAOin=>I2C1SDAO_buf, I2C1SDAOENout=>I2C1SDAOEN, + I2C1SDAOENin=>I2C1SDAOEN_buf, I2C2SCLOout=>I2C2SCLO, + I2C2SCLOin=>I2C2SCLO_buf, I2C2SCLOENout=>I2C2SCLOEN, + I2C2SCLOENin=>I2C2SCLOEN_buf, I2C2SDAOout=>I2C2SDAO, + I2C2SDAOin=>I2C2SDAO_buf, I2C2SDAOENout=>I2C2SDAOEN, + I2C2SDAOENin=>I2C2SDAOEN_buf, I2C1IRQOout=>I2C1IRQO, + I2C1IRQOin=>I2C1IRQO_buf, I2C2IRQOout=>I2C2IRQO, + I2C2IRQOin=>I2C2IRQO_buf, SPISCKOout=>SPISCKO, + SPISCKOin=>SPISCKO_buf, SPISCKENout=>SPISCKEN, + SPISCKENin=>SPISCKEN_buf, SPIMISOOout=>SPIMISOO, + SPIMISOOin=>SPIMISOO_buf, SPIMISOENout=>SPIMISOEN, + SPIMISOENin=>SPIMISOEN_buf, SPIMOSIOout=>SPIMOSIO, + SPIMOSIOin=>SPIMOSIO_buf, SPIMOSIENout=>SPIMOSIEN, + SPIMOSIENin=>SPIMOSIEN_buf, SPIMCSN0out=>SPIMCSN0, + SPIMCSN0in=>SPIMCSN0_buf, SPIMCSN1out=>SPIMCSN1, + SPIMCSN1in=>SPIMCSN1_buf, SPIMCSN2out=>SPIMCSN2, + SPIMCSN2in=>SPIMCSN2_buf, SPIMCSN3out=>SPIMCSN3, + SPIMCSN3in=>SPIMCSN3_buf, SPIMCSN4out=>SPIMCSN4, + SPIMCSN4in=>SPIMCSN4_buf, SPIMCSN5out=>SPIMCSN5, + SPIMCSN5in=>SPIMCSN5_buf, SPIMCSN6out=>SPIMCSN6, + SPIMCSN6in=>SPIMCSN6_buf, SPIMCSN7out=>SPIMCSN7, + SPIMCSN7in=>SPIMCSN7_buf, SPICSNENout=>SPICSNEN, + SPICSNENin=>SPICSNEN_buf, SPIIRQOout=>SPIIRQO, + SPIIRQOin=>SPIIRQO_buf, TCINTout=>TCINT, TCINTin=>TCINT_buf, + TCOCout=>TCOC, TCOCin=>TCOC_buf, WBCUFMIRQout=>WBCUFMIRQ, + WBCUFMIRQin=>WBCUFMIRQ_buf, CFGWAKEout=>CFGWAKE, + CFGWAKEin=>CFGWAKE_buf, CFGSTDBYout=>CFGSTDBY, + CFGSTDBYin=>CFGSTDBY_buf); + end Structure; + +-- entity ufmefb_EFBInst_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ufmefb_EFBInst_0 is + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic; + WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic; + WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic; + WBDATO0: out Std_logic; WBDATO1: out Std_logic; + WBACKO: out Std_logic); + + + + end ufmefb_EFBInst_0; + + architecture Structure of ufmefb_EFBInst_0 is + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component EFBB + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; + WBADRI3: in Std_logic; WBADRI4: in Std_logic; + WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; + WBDATI1: in Std_logic; WBDATI2: in Std_logic; + WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; + WBDATI7: in Std_logic; WBDATO0: out Std_logic; + WBDATO1: out Std_logic; WBDATO2: out Std_logic; + WBDATO3: out Std_logic; WBDATO4: out Std_logic; + WBDATO5: out Std_logic; WBDATO6: out Std_logic; + WBDATO7: out Std_logic; WBACKO: out Std_logic; + WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic; + CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic; + I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic; + I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic; + I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic; + I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic; + I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic; + I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic; + I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic; + SPISCKI: in Std_logic; SPISCKO: out Std_logic; + SPISCKEN: out Std_logic; SPIMISOI: in Std_logic; + SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic; + SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic; + SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic; + SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic; + SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic; + SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic; + SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic; + SPISCSN: in Std_logic; SPIIRQO: out Std_logic; + TCCLKI: in Std_logic; TCRSTN: in Std_logic; TCIC: in Std_logic; + TCINT: out Std_logic; TCOC: out Std_logic; PLLCLKO: out Std_logic; + PLLRSTO: out Std_logic; PLL0STBO: out Std_logic; + PLL1STBO: out Std_logic; PLLWEO: out Std_logic; + PLLADRO0: out Std_logic; PLLADRO1: out Std_logic; + PLLADRO2: out Std_logic; PLLADRO3: out Std_logic; + PLLADRO4: out Std_logic; PLLDATO0: out Std_logic; + PLLDATO1: out Std_logic; PLLDATO2: out Std_logic; + PLLDATO3: out Std_logic; PLLDATO4: out Std_logic; + PLLDATO5: out Std_logic; PLLDATO6: out Std_logic; + PLLDATO7: out Std_logic; PLL0DATI0: in Std_logic; + PLL0DATI1: in Std_logic; PLL0DATI2: in Std_logic; + PLL0DATI3: in Std_logic; PLL0DATI4: in Std_logic; + PLL0DATI5: in Std_logic; PLL0DATI6: in Std_logic; + PLL0DATI7: in Std_logic; PLL0ACKI: in Std_logic; + PLL1DATI0: in Std_logic; PLL1DATI1: in Std_logic; + PLL1DATI2: in Std_logic; PLL1DATI3: in Std_logic; + PLL1DATI4: in Std_logic; PLL1DATI5: in Std_logic; + PLL1DATI6: in Std_logic; PLL1DATI7: in Std_logic; + PLL1ACKI: in Std_logic); + end component; + begin + ufmefb_EFBInst_0_EFB: EFBB + port map (WBCLKI=>WBCLKI, WBRSTI=>WBRSTI, WBCYCI=>WBCYCI, WBSTBI=>WBSTBI, + WBWEI=>WBWEI, WBADRI0=>WBADRI0, WBADRI1=>WBADRI1, + WBADRI2=>WBADRI2, WBADRI3=>WBADRI3, WBADRI4=>WBADRI4, + WBADRI5=>WBADRI5, WBADRI6=>WBADRI6, WBADRI7=>WBADRI7, + WBDATI0=>WBDATI0, WBDATI1=>WBDATI1, WBDATI2=>WBDATI2, + WBDATI3=>WBDATI3, WBDATI4=>WBDATI4, WBDATI5=>WBDATI5, + WBDATI6=>WBDATI6, WBDATI7=>WBDATI7, WBDATO0=>WBDATO0, + WBDATO1=>WBDATO1, WBDATO2=>open, WBDATO3=>open, WBDATO4=>open, + WBDATO5=>open, WBDATO6=>open, WBDATO7=>open, WBACKO=>WBACKO, + WBCUFMIRQ=>open, UFMSN=>VCCI, CFGWAKE=>open, CFGSTDBY=>open, + I2C1SCLI=>GNDI, I2C1SCLO=>open, I2C1SCLOEN=>open, + I2C1SDAI=>GNDI, I2C1SDAO=>open, I2C1SDAOEN=>open, + I2C2SCLI=>GNDI, I2C2SCLO=>open, I2C2SCLOEN=>open, + I2C2SDAI=>GNDI, I2C2SDAO=>open, I2C2SDAOEN=>open, + I2C1IRQO=>open, I2C2IRQO=>open, SPISCKI=>GNDI, SPISCKO=>open, + SPISCKEN=>open, SPIMISOI=>GNDI, SPIMISOO=>open, + SPIMISOEN=>open, SPIMOSII=>GNDI, SPIMOSIO=>open, + SPIMOSIEN=>open, SPIMCSN0=>open, SPIMCSN1=>open, + SPIMCSN2=>open, SPIMCSN3=>open, SPIMCSN4=>open, SPIMCSN5=>open, + SPIMCSN6=>open, SPIMCSN7=>open, SPICSNEN=>open, SPISCSN=>GNDI, + SPIIRQO=>open, TCCLKI=>GNDI, TCRSTN=>GNDI, TCIC=>GNDI, + TCINT=>open, TCOC=>open, PLLCLKO=>open, PLLRSTO=>open, + PLL0STBO=>open, PLL1STBO=>open, PLLWEO=>open, PLLADRO0=>open, + PLLADRO1=>open, PLLADRO2=>open, PLLADRO3=>open, PLLADRO4=>open, + PLLDATO0=>open, PLLDATO1=>open, PLLDATO2=>open, PLLDATO3=>open, + PLLDATO4=>open, PLLDATO5=>open, PLLDATO6=>open, PLLDATO7=>open, + PLL0DATI0=>GNDI, PLL0DATI1=>GNDI, PLL0DATI2=>GNDI, + PLL0DATI3=>GNDI, PLL0DATI4=>GNDI, PLL0DATI5=>GNDI, + PLL0DATI6=>GNDI, PLL0DATI7=>GNDI, PLL0ACKI=>GNDI, + PLL1DATI0=>GNDI, PLL1DATI1=>GNDI, PLL1DATI2=>GNDI, + PLL1DATI3=>GNDI, PLL1DATI4=>GNDI, PLL1DATI5=>GNDI, + PLL1DATI6=>GNDI, PLL1DATI7=>GNDI, PLL1ACKI=>GNDI); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_0: Std_logic; + signal FS_s_0: Std_logic; + signal RCLK_c: Std_logic; + signal FS_cry_0: Std_logic; + signal FS_17: Std_logic; + signal FS_s_17: Std_logic; + signal FS_cry_16: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal FS_s_16: Std_logic; + signal FS_s_15: Std_logic; + signal FS_cry_14: Std_logic; + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal FS_s_14: Std_logic; + signal FS_s_13: Std_logic; + signal FS_cry_12: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal FS_s_12: Std_logic; + signal FS_s_11: Std_logic; + signal FS_cry_10: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal FS_s_10: Std_logic; + signal FS_s_9: Std_logic; + signal FS_cry_8: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal FS_s_8: Std_logic; + signal FS_s_7: Std_logic; + signal FS_cry_6: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal FS_s_6: Std_logic; + signal FS_s_5: Std_logic; + signal FS_cry_4: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal FS_s_4: Std_logic; + signal FS_s_3: Std_logic; + signal FS_cry_2: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal FS_s_2: Std_logic; + signal FS_s_1: Std_logic; + signal N_304: Std_logic; + signal CmdEnable17_5: Std_logic; + signal CmdEnable17_4: Std_logic; + signal ADWR_7: Std_logic; + signal CmdEnable16: Std_logic; + signal CmdEnable17: Std_logic; + signal un1_ADWR: Std_logic; + signal ADSubmitted: Std_logic; + signal ADSubmitted_r: Std_logic; + signal PHI2_c: Std_logic; + signal CmdEnable16_5: Std_logic; + signal CmdEnable16_4: Std_logic; + signal C1WR_7: Std_logic; + signal C1WR_2: Std_logic; + signal C1Submitted: Std_logic; + signal C1Submitted_s: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_c_i: Std_logic; + signal CASr: Std_logic; + signal CASr2: Std_logic; + signal S_1: Std_logic; + signal RASr2: Std_logic; + signal IS_3: Std_logic; + signal CO0: Std_logic; + signal N_79_i: Std_logic; + signal Ready_0_sqmuxa_0_a3_2: Std_logic; + signal CmdEnable: Std_logic; + signal un1_CMDWR: Std_logic; + signal CmdEnable_s: Std_logic; + signal XOR8MEG11: Std_logic; + signal Din_c_1: Std_logic; + signal CmdLEDEN: Std_logic; + signal XOR8MEG14: Std_logic; + signal N_75: Std_logic; + signal LEDEN: Std_logic; + signal CmdLEDEN_4: Std_logic; + signal XOR8MEG18: Std_logic; + signal CmdUFMShift: Std_logic; + signal CmdUFMShift_3: Std_logic; + signal CmdUFMShift_fast: Std_logic; + signal CmdUFMShift_3_fast: Std_logic; + signal Din_c_0: Std_logic; + signal CmdUFMWrite_2: Std_logic; + signal CmdUFMWrite: Std_logic; + signal CmdUFMWrite_3: Std_logic; + signal Din_c_7: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_4: Std_logic; + signal CmdValid_r: Std_logic; + signal CmdValid: Std_logic; + signal CMDWR_2: Std_logic; + signal N_36_fast: Std_logic; + signal CmdValid_fast: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal n8MEGEN: Std_logic; + signal N_93: Std_logic; + signal Cmdn8MEGEN_4: Std_logic; + signal nFWE_c: Std_logic; + signal nFWE_c_i: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal RD_1_i: Std_logic; + signal Ready: Std_logic; + signal N_250: Std_logic; + signal IS_0: Std_logic; + signal N_60_i_i: Std_logic; + signal RA10s_i: Std_logic; + signal IS_2: Std_logic; + signal IS_1: Std_logic; + signal N_57_i_i: Std_logic; + signal IS_n1_0_x2: Std_logic; + signal N_253_i: Std_logic; + signal N_58_i_i: Std_logic; + signal N_45: Std_logic; + signal N_116: Std_logic; + signal InitReady3_0_a3_2: Std_logic; + signal InitReady: Std_logic; + signal InitReady3: Std_logic; + signal N_487_0: Std_logic; + signal wb_dato_1: Std_logic; + signal LEDEN_6: Std_logic; + signal un1_FS_38_i: Std_logic; + signal CBR: Std_logic; + signal nCRAS_c_i_0: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal nRowColSel: Std_logic; + signal RowA_4: Std_logic; + signal MAin_c_4: Std_logic; + signal PHI2r: Std_logic; + signal RA_c_4: Std_logic; + signal RASr3: Std_logic; + signal un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: Std_logic; + signal PHI2r2: Std_logic; + signal N_41: Std_logic; + signal RCKEEN_8_u_1_0: Std_logic; + signal RCKEEN_8_u_0_0: Std_logic; + signal RCKEEN_8: Std_logic; + signal RCKEEN: Std_logic; + signal Bank_7: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal Bank_2: Std_logic; + signal RCKE_2: Std_logic; + signal RCKE_c: Std_logic; + signal un1_Bank_1_4: Std_logic; + signal N_258: Std_logic; + signal N_486_0: Std_logic; + signal Ready_fast: Std_logic; + signal Ready_0_sqmuxa: Std_logic; + signal N_489_0: Std_logic; + signal MAin_c_1: Std_logic; + signal MAin_c_0: Std_logic; + signal RowAd_0_1: Std_logic; + signal RowAd_0_0: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal MAin_c_3: Std_logic; + signal MAin_c_2: Std_logic; + signal RowAd_0_3: Std_logic; + signal RowAd_0_2: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal MAin_c_5: Std_logic; + signal RowAd_0_5: Std_logic; + signal RowAd_0_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowAd_0_7: Std_logic; + signal RowAd_0_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowAd_0_9: Std_logic; + signal RowAd_0_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal nRRAS_5_u_i_0: Std_logic; + signal XOR8MEG9_1: Std_logic; + signal un1_Din_2: Std_logic; + signal XOR8MEG_3_u_0_bm: Std_logic; + signal XOR8MEG: Std_logic; + signal XOR8MEG_3: Std_logic; + signal wb_dato_0: Std_logic; + signal n8MEGEN_6: Std_logic; + signal wb_rst10: Std_logic; + signal CASr3: Std_logic; + signal N_265: Std_logic; + signal nRowColSel_0_0: Std_logic; + signal nRRAS_0_sqmuxa: Std_logic; + signal wb_rst11: Std_logic; + signal wb_adr_0: Std_logic; + signal N_181: Std_logic; + signal wb_dati_7: Std_logic; + signal wb_adr_cnst_m2_0: Std_logic; + signal wb_adr_5_1: Std_logic; + signal wb_adr_5_0: Std_logic; + signal un1_wb_rst14_i: Std_logic; + signal wb_adr_1: Std_logic; + signal wb_adr_2: Std_logic; + signal wb_adr_5_3: Std_logic; + signal wb_adr_5_2: Std_logic; + signal wb_adr_3: Std_logic; + signal wb_adr_4: Std_logic; + signal wb_adr_5_5: Std_logic; + signal wb_adr_5_4: Std_logic; + signal wb_adr_5: Std_logic; + signal wb_adr_6: Std_logic; + signal wb_adr_5_7: Std_logic; + signal wb_adr_5_6: Std_logic; + signal wb_adr_7: Std_logic; + signal un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1: Std_logic; + signal N_245: Std_logic; + signal N_102_2: Std_logic; + signal un1_wb_cyc_stb_1_sqmuxa_0: Std_logic; + signal un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: Std_logic; + signal wb_cyc_stb: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_0_1: Std_logic; + signal wb_dati_5_1_iv_0_0_1: Std_logic; + signal N_128: Std_logic; + signal N_94: Std_logic; + signal wb_we: Std_logic; + signal wb_dati_5_0_iv_0_a3_1_0: Std_logic; + signal N_119: Std_logic; + signal wb_dati_5_1: Std_logic; + signal wb_dati_5_0: Std_logic; + signal wb_dati_0: Std_logic; + signal wb_dati_1: Std_logic; + signal un1_wb_we95_1: Std_logic; + signal wb_dati_5_1_iv_0_0_3: Std_logic; + signal N_240: Std_logic; + signal N_49: Std_logic; + signal wb_dati_5_3: Std_logic; + signal wb_dati_5_2: Std_logic; + signal wb_dati_2: Std_logic; + signal wb_dati_3: Std_logic; + signal wb_dati_4: Std_logic; + signal wb_dati_5_1_iv_0_1_4: Std_logic; + signal un1_wb_rst11_1_s6_1: Std_logic; + signal wb_dati_5_5: Std_logic; + signal wb_dati_5_4: Std_logic; + signal wb_dati_5: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_0_7: Std_logic; + signal wb_dati_5_1_iv_0_1_7: Std_logic; + signal N_89: Std_logic; + signal wb_dati_5_1_iv_0_1_6: Std_logic; + signal wb_dati_5_7: Std_logic; + signal wb_dati_5_6: Std_logic; + signal wb_dati_6: Std_logic; + signal wb_req: Std_logic; + signal un1_FS_37_i_0: Std_logic; + signal N_78_i: Std_logic; + signal wb_reqe_0: Std_logic; + signal PHI2r3: Std_logic; + signal wb_rst: Std_logic; + signal wb_rste_0: Std_logic; + signal wb_we95: Std_logic; + signal un1_FS_29: Std_logic; + signal un1_wb_adr_0_sqmuxa_3: Std_logic; + signal un1_wb_adr_0_sqmuxa_2: Std_logic; + signal CmdUFMData: Std_logic; + signal wb_we_0: Std_logic; + signal un1_PHI2r3_0: Std_logic; + signal N_102: Std_logic; + signal un1_FS_11: Std_logic; + signal wb_ack: Std_logic; + signal d_N_5_mux: Std_logic; + signal N_254: Std_logic; + signal N_39: Std_logic; + signal nRCAS_0_sqmuxa_1: Std_logic; + signal nRWE_0io_RNO_1: Std_logic; + signal N_37_i_1: Std_logic; + signal CBR_fast: Std_logic; + signal N_37_i: Std_logic; + signal un1_FS_40_1_0_1: Std_logic; + signal un1_FS_40_1_0: Std_logic; + signal nRCAS_0io_RNO_0: Std_logic; + signal N_28_i_1: Std_logic; + signal N_249_i: Std_logic; + signal N_230: Std_logic; + signal nRWE_0io_RNO_4: Std_logic; + signal nRWE_0io_RNO_3: Std_logic; + signal N_131: Std_logic; + signal N_85: Std_logic; + signal N_248: Std_logic; + signal XOR8MEG14_1: Std_logic; + signal Din_c_3: Std_logic; + signal CmdUFMData_1_sqmuxa: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_6: Std_logic; + signal N_246: Std_logic; + signal N_98: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_3: Std_logic; + signal N_25: Std_logic; + signal N_59: Std_logic; + signal wb_dati_5_1_iv_0_a3_2_0_1: Std_logic; + signal wb_dati_5_1_iv_0_a3_1_1_4: Std_logic; + signal wb_dati_5_1_iv_0_a3_3_0_7: Std_logic; + signal N_242: Std_logic; + signal N_91: Std_logic; + signal wb_we95_0_tz_tz_tz: Std_logic; + signal un1_FS_20_3: Std_logic; + signal N_120: Std_logic; + signal N_228: Std_logic; + signal wb_we113_i: Std_logic; + signal un1_FS_40_1_1_1: Std_logic; + signal un1_FS_40_1_1_tz: Std_logic; + signal N_139: Std_logic; + signal N_136: Std_logic; + signal N_28_i_sn: Std_logic; + signal N_25_i: Std_logic; + signal FWEr_fast: Std_logic; + signal N_28_i: Std_logic; + signal N_233: Std_logic; + signal N_102_1: Std_logic; + signal ADWR_5: Std_logic; + signal ADWR_4: Std_logic; + signal C1WR_0: Std_logic; + signal Bank_1: Std_logic; + signal Bank_0: Std_logic; + signal un1_Bank_1_3: Std_logic; + signal Bank_4: Std_logic; + signal Bank_3: Std_logic; + signal G_8_0_a3_0_0: Std_logic; + signal nRWE_0io_RNO_2: Std_logic; + signal Din_c_2: Std_logic; + signal RA_c_9: Std_logic; + signal RDQMH_c: Std_logic; + signal RA_c_7: Std_logic; + signal RA_c_0: Std_logic; + signal RDQML_c: Std_logic; + signal RA_c_1: Std_logic; + signal RA_c_8: Std_logic; + signal RA_c_2: Std_logic; + signal RA_c_6: Std_logic; + signal RA_c_3: Std_logic; + signal RA_c_5: Std_logic; + signal RA11d_0: Std_logic; + signal CROW_c_0: Std_logic; + signal CROW_c_1: Std_logic; + signal RBAd_0_1: Std_logic; + signal RBAd_0_0: Std_logic; + signal RD_in_0: Std_logic; + signal WRD_0: Std_logic; + signal nRCAS_c: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_c: Std_logic; + signal nRCS_c: Std_logic; + signal RD_in_7: Std_logic; + signal WRD_7: Std_logic; + signal RD_in_6: Std_logic; + signal WRD_6: Std_logic; + signal RD_in_5: Std_logic; + signal WRD_5: Std_logic; + signal RD_in_4: Std_logic; + signal WRD_4: Std_logic; + signal RD_in_3: Std_logic; + signal WRD_3: Std_logic; + signal RD_in_2: Std_logic; + signal WRD_2: Std_logic; + signal RD_in_1: Std_logic; + signal WRD_1: Std_logic; + signal RA_c_11: Std_logic; + signal RA_c_10: Std_logic; + signal RBA_c_1: Std_logic; + signal RBA_c_0: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_11 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_12 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_16 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_17 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_18 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_21 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_22 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_25 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_26 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_28 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_29 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_30 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_34 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_36 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_37 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_38 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_39 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_40 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_41 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_42 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_43 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_44 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_46 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_47 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_48 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_50 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_51 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_52 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_53 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_54 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_55 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_56 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_58 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_60 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component wb_cyc_stb_RNO_SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_64 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_66 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_69 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_71 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_75 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_77 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_78 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_80 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_81 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_82 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_83 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_85 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_86 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_87 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_89 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_92 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_93 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_96 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_98 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_101 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_102 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_104 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_105 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_106 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_107 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_108 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_109 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_110 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_111 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_112 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_113 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_114 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_115 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_116 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_117 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_118 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD0: inout Std_logic); + end component; + component RD_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component PHI2_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component nRCASB + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + end component; + component nRCAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRRASB + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRRAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRWEB + port (IOLDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRWE_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component nRCSB + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + end component; + component nRCS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_7_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_6_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_5_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_4_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_3_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_2_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RA_11_B + port (IOLDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_11_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RA_10_B + port (IOLDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_10_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component RBA_1_B + port (IOLDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RBA_0_B + port (IOLDO: in Std_logic; RBA0: out Std_logic); + end component; + component RBA_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_7_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_6_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_5_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_4_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_3_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_2_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_1_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component Din_0_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component ufmefb_EFBInst_0 + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; + WBADRI3: in Std_logic; WBADRI4: in Std_logic; + WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; + WBDATI1: in Std_logic; WBDATI2: in Std_logic; + WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; + WBDATI7: in Std_logic; WBDATO0: out Std_logic; + WBDATO1: out Std_logic; WBACKO: out Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0, + FCO=>FS_cry_0); + SLICE_1I: SLICE_1 + port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16, + F0=>FS_s_17, Q0=>FS_17); + SLICE_2I: SLICE_2 + port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c, + FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16, + FCO=>FS_cry_16); + SLICE_3I: SLICE_3 + port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c, + FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14, + FCO=>FS_cry_14); + SLICE_4I: SLICE_4 + port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c, + FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12, + FCO=>FS_cry_12); + SLICE_5I: SLICE_5 + port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c, + FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10, + FCO=>FS_cry_10); + SLICE_6I: SLICE_6 + port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c, + FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8, + FCO=>FS_cry_8); + SLICE_7I: SLICE_7 + port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c, + FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6, + FCO=>FS_cry_6); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c, + FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4, + FCO=>FS_cry_4); + SLICE_9I: SLICE_9 + port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c, + FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2, + FCO=>FS_cry_2); + SLICE_10I: SLICE_10 + port map (D1=>N_304, C1=>CmdEnable17_5, B1=>CmdEnable17_4, A1=>ADWR_7, + D0=>CmdEnable16, C0=>CmdEnable17, B0=>un1_ADWR, + A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c, + F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17); + SLICE_11I: SLICE_11 + port map (D1=>CmdEnable16_5, C1=>CmdEnable16_4, B1=>C1WR_7, A1=>C1WR_2, + C0=>CmdEnable16, B0=>un1_ADWR, A0=>C1Submitted, + DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s, + Q0=>C1Submitted, F1=>CmdEnable16); + SLICE_12I: SLICE_12 + port map (A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_c_i, Q0=>CASr, Q1=>CASr2); + SLICE_16I: SLICE_16 + port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, + DI0=>N_79_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_79_i, Q0=>CO0, + F1=>Ready_0_sqmuxa_0_a3_2); + SLICE_17I: SLICE_17 + port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, + B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, + M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable); + SLICE_18I: SLICE_18 + port map (C1=>XOR8MEG11, B1=>Din_c_1, A1=>CmdLEDEN, C0=>XOR8MEG14, + B0=>N_75, A0=>LEDEN, DI0=>CmdLEDEN_4, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>CmdLEDEN_4, Q0=>CmdLEDEN, F1=>N_75); + SLICE_20I: SLICE_20 + port map (D0=>XOR8MEG14, C0=>XOR8MEG11, B0=>Din_c_1, A0=>CmdUFMShift, + DI0=>CmdUFMShift_3, CE=>XOR8MEG18, CLK=>PHI2_c, + F0=>CmdUFMShift_3, Q0=>CmdUFMShift); + SLICE_21I: SLICE_21 + port map (D0=>XOR8MEG14, C0=>XOR8MEG11, B0=>Din_c_1, + A0=>CmdUFMShift_fast, DI0=>CmdUFMShift_3_fast, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>CmdUFMShift_3_fast, Q0=>CmdUFMShift_fast); + SLICE_22I: SLICE_22 + port map (B1=>Din_c_1, A1=>Din_c_0, D0=>XOR8MEG14, C0=>XOR8MEG11, + B0=>CmdUFMWrite_2, A0=>CmdUFMWrite, DI0=>CmdUFMWrite_3, + CE=>XOR8MEG18, CLK=>PHI2_c, F0=>CmdUFMWrite_3, Q0=>CmdUFMWrite, + F1=>CmdUFMWrite_2); + SLICE_23I: SLICE_23 + port map (D1=>Din_c_7, C1=>Din_c_6, B1=>Din_c_5, A1=>Din_c_4, + C0=>XOR8MEG14, B0=>XOR8MEG11, A0=>XOR8MEG18, DI0=>CmdValid_r, + CLK=>PHI2_c, F0=>CmdValid_r, Q0=>CmdValid, F1=>XOR8MEG11); + SLICE_24I: SLICE_24 + port map (C1=>CmdEnable, B1=>CMDWR_2, A1=>C1WR_7, C0=>XOR8MEG14, + B0=>XOR8MEG11, A0=>XOR8MEG18, DI0=>N_36_fast, CLK=>PHI2_c, + F0=>N_36_fast, Q0=>CmdValid_fast, F1=>XOR8MEG18); + SLICE_25I: SLICE_25 + port map (C1=>XOR8MEG11, B1=>Din_c_0, A1=>Cmdn8MEGEN, C0=>n8MEGEN, + B0=>XOR8MEG14, A0=>N_93, DI0=>Cmdn8MEGEN_4, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>Cmdn8MEGEN_4, Q0=>Cmdn8MEGEN, F1=>N_93); + SLICE_26I: SLICE_26 + port map (B1=>nFWE_c, A1=>nCCAS_c, A0=>nFWE_c, DI0=>nFWE_c_i, + CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, F1=>RD_1_i); + SLICE_28I: SLICE_28 + port map (D1=>Ready, C1=>N_250, B1=>IS_3, A1=>IS_0, C0=>Ready, B0=>N_250, + A0=>IS_0, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0, + F1=>RA10s_i); + SLICE_29I: SLICE_29 + port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, + DI1=>N_57_i_i, DI0=>IS_n1_0_x2, CE=>N_253_i, CLK=>RCLK_c, + F0=>IS_n1_0_x2, Q0=>IS_1, F1=>N_57_i_i, Q1=>IS_2); + SLICE_30I: SLICE_30 + port map (B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, B0=>IS_2, A0=>IS_3, + DI0=>N_58_i_i, CE=>N_253_i, CLK=>RCLK_c, F0=>N_58_i_i, + Q0=>IS_3, F1=>N_45); + SLICE_31I: SLICE_31 + port map (D1=>N_116, C1=>InitReady3_0_a3_2, B1=>FS_14, A1=>FS_13, + B0=>InitReady, A0=>InitReady3, DI0=>N_487_0, CLK=>RCLK_c, + F0=>N_487_0, Q0=>InitReady, F1=>InitReady3); + SLICE_32I: SLICE_32 + port map (C0=>wb_dato_1, B0=>InitReady, A0=>CmdLEDEN, DI0=>LEDEN_6, + CE=>un1_FS_38_i, CLK=>RCLK_c, F0=>LEDEN_6, Q0=>LEDEN); + SLICE_34I: SLICE_34 + port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, A0=>nCRAS_c, DI0=>nCRAS_c_i_0, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_35I: SLICE_35 + port map (B1=>FS_7, A1=>FS_3, C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, + M1=>PHI2r, M0=>RASr2, CLK=>RCLK_c, F0=>RA_c_4, Q0=>RASr3, + F1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, Q1=>PHI2r2); + SLICE_36I: SLICE_36 + port map (D1=>N_41, C1=>InitReady, B1=>RASr2, A1=>Ready, D0=>Ready, + C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, + CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_0_0); + SLICE_37I: SLICE_37 + port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, D0=>RCKEEN, + C0=>RASr3, B0=>RASr2, A0=>RASr, DI0=>RCKE_2, CLK=>RCLK_c, + F0=>RCKE_2, Q0=>RCKE_c, F1=>un1_Bank_1_4); + SLICE_38I: SLICE_38 + port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>InitReady, C0=>N_258, + B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_486_0, + CLK=>RCLK_c, F0=>N_486_0, Q0=>Ready, F1=>N_258); + SLICE_39I: SLICE_39 + port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_258, A1=>InitReady, + B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_489_0, CLK=>RCLK_c, + F0=>N_489_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa); + SLICE_40I: SLICE_40 + port map (B1=>Ready_fast, A1=>MAin_c_1, B0=>Ready_fast, A0=>MAin_c_0, + DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0, + Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1); + SLICE_41I: SLICE_41 + port map (B1=>Ready_fast, A1=>MAin_c_3, B0=>Ready_fast, A0=>MAin_c_2, + DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2, + Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3); + SLICE_42I: SLICE_42 + port map (B1=>Ready_fast, A1=>MAin_c_5, B0=>Ready_fast, A0=>MAin_c_4, + DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4, + Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5); + SLICE_43I: SLICE_43 + port map (B1=>Ready_fast, A1=>MAin_c_7, B0=>Ready_fast, A0=>MAin_c_6, + DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6, + Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7); + SLICE_44I: SLICE_44 + port map (B1=>Ready_fast, A1=>MAin_c_9, B0=>Ready_fast, A0=>MAin_c_8, + DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8, + Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9); + SLICE_45I: SLICE_45 + port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>N_41, B0=>S_1, A0=>CO0, + DI0=>N_41, LSR=>RASr2, CLK=>RCLK_c, F0=>N_41, Q0=>S_1, + F1=>nRRAS_5_u_i_0); + SLICE_46I: SLICE_46 + port map (D1=>Din_c_1, C1=>Din_c_0, B1=>XOR8MEG9_1, A1=>LEDEN, + C0=>un1_Din_2, B0=>XOR8MEG_3_u_0_bm, A0=>XOR8MEG, + DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, + Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_bm); + SLICE_47I: SLICE_47 + port map (D1=>InitReady, C1=>FS_17, B1=>FS_16, A1=>FS_15, C0=>wb_dato_0, + B0=>InitReady, A0=>Cmdn8MEGEN, DI0=>n8MEGEN_6, CE=>un1_FS_38_i, + CLK=>RCLK_c, F0=>n8MEGEN_6, Q0=>n8MEGEN, F1=>wb_rst10); + SLICE_48I: SLICE_48 + port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, + B0=>N_265, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, + CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_265); + SLICE_49I: SLICE_49 + port map (D1=>wb_rst11, C1=>wb_adr_0, B1=>N_181, A1=>InitReady, + C0=>wb_dati_7, B0=>wb_adr_cnst_m2_0, A0=>InitReady, + DI1=>wb_adr_5_1, DI0=>wb_adr_5_0, CE=>un1_wb_rst14_i, + CLK=>RCLK_c, F0=>wb_adr_5_0, Q0=>wb_adr_0, F1=>wb_adr_5_1, + Q1=>wb_adr_1); + SLICE_50I: SLICE_50 + port map (B1=>wb_adr_2, A1=>InitReady, B0=>wb_adr_1, A0=>InitReady, + DI1=>wb_adr_5_3, DI0=>wb_adr_5_2, CE=>un1_wb_rst14_i, + CLK=>RCLK_c, F0=>wb_adr_5_2, Q0=>wb_adr_2, F1=>wb_adr_5_3, + Q1=>wb_adr_3); + SLICE_51I: SLICE_51 + port map (C1=>wb_rst11, B1=>wb_adr_4, A1=>InitReady, C0=>wb_rst11, + B0=>wb_adr_3, A0=>InitReady, DI1=>wb_adr_5_5, DI0=>wb_adr_5_4, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_4, Q0=>wb_adr_4, + F1=>wb_adr_5_5, Q1=>wb_adr_5); + SLICE_52I: SLICE_52 + port map (B1=>wb_adr_6, A1=>InitReady, C0=>wb_rst11, B0=>wb_adr_5, + A0=>InitReady, DI1=>wb_adr_5_7, DI0=>wb_adr_5_6, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_6, Q0=>wb_adr_6, + F1=>wb_adr_5_7, Q1=>wb_adr_7); + SLICE_53I: SLICE_53 + port map (D1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, C1=>FS_5, B1=>FS_4, + A1=>FS_2, D0=>wb_rst11, C0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, + B0=>N_245, A0=>N_102_2, DI0=>un1_wb_cyc_stb_1_sqmuxa_0, + CE=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, LSR=>wb_rst10, + CLK=>RCLK_c, F0=>un1_wb_cyc_stb_1_sqmuxa_0, Q0=>wb_cyc_stb, + F1=>N_102_2); + SLICE_54I: SLICE_54 + port map (D1=>wb_dati_5_1_iv_0_a3_0_0_1, C1=>wb_dati_5_1_iv_0_0_1, + B1=>N_128, A1=>N_94, D0=>wb_we, C0=>wb_dati_5_0_iv_0_a3_1_0, + B0=>N_119, A0=>InitReady, DI1=>wb_dati_5_1, DI0=>wb_dati_5_0, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_dati_5_0, + Q0=>wb_dati_0, F1=>wb_dati_5_1, Q1=>wb_dati_1); + SLICE_55I: SLICE_55 + port map (D1=>N_94, C1=>wb_rst11, B1=>un1_wb_we95_1, + A1=>wb_dati_5_1_iv_0_0_3, D0=>wb_dati_1, C0=>N_240, B0=>N_49, + A0=>InitReady, DI1=>wb_dati_5_3, DI0=>wb_dati_5_2, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_dati_5_2, + Q0=>wb_dati_2, F1=>wb_dati_5_3, Q1=>wb_dati_3); + SLICE_56I: SLICE_56 + port map (D1=>wb_dati_4, C1=>N_240, B1=>N_49, A1=>InitReady, + D0=>wb_dati_5_1_iv_0_1_4, C0=>wb_dati_3, + B0=>un1_wb_rst11_1_s6_1, A0=>InitReady, DI1=>wb_dati_5_5, + DI0=>wb_dati_5_4, CE=>un1_wb_rst14_i, CLK=>RCLK_c, + F0=>wb_dati_5_4, Q0=>wb_dati_4, F1=>wb_dati_5_5, Q1=>wb_dati_5); + SLICE_57I: SLICE_57 + port map (D1=>wb_dati_5_1_iv_0_a3_0_0_7, C1=>wb_dati_5_1_iv_0_1_7, + B1=>N_119, A1=>N_89, C0=>wb_dati_5_1_iv_0_a3_0_0_1, + B0=>wb_dati_5_1_iv_0_1_6, A0=>N_128, DI1=>wb_dati_5_7, + DI0=>wb_dati_5_6, CE=>un1_wb_rst14_i, CLK=>RCLK_c, + F0=>wb_dati_5_6, Q0=>wb_dati_6, F1=>wb_dati_5_7, Q1=>wb_dati_7); + SLICE_58I: SLICE_58 + port map (C1=>FS_14, B1=>FS_13, A1=>FS_12, D0=>wb_rst11, C0=>wb_req, + B0=>un1_FS_37_i_0, A0=>N_78_i, DI0=>wb_reqe_0, LSR=>wb_rst10, + CLK=>RCLK_c, F0=>wb_reqe_0, Q0=>wb_req, F1=>un1_FS_37_i_0); + SLICE_59I: SLICE_59 + port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdValid, + D0=>wb_rst10, C0=>wb_rst, B0=>N_78_i, A0=>FS_14, + DI0=>wb_rste_0, CLK=>RCLK_c, F0=>wb_rste_0, Q0=>wb_rst, + F1=>N_78_i); + SLICE_60I: SLICE_60 + port map (B1=>wb_we95, A1=>un1_FS_29, D0=>un1_wb_adr_0_sqmuxa_3, + C0=>un1_wb_adr_0_sqmuxa_2, B0=>InitReady, A0=>CmdUFMData, + DI0=>wb_we_0, CE=>un1_wb_rst14_i, LSR=>wb_rst10, CLK=>RCLK_c, + F0=>wb_we_0, Q0=>wb_we, F1=>un1_wb_adr_0_sqmuxa_2); + wb_cyc_stb_RNO_SLICE_61I: wb_cyc_stb_RNO_SLICE_61 + port map (D1=>CmdUFMWrite, C1=>un1_PHI2r3_0, B1=>CmdUFMShift, + A1=>CmdValid, C0=>N_102, B0=>un1_FS_11, A0=>wb_ack, + M0=>InitReady, OFX0=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i); + SLICE_62I: SLICE_62 + port map (D1=>un1_PHI2r3_0, C1=>d_N_5_mux, B1=>InitReady, + A1=>CmdValid_fast, D0=>wb_ack, C0=>un1_FS_29, B0=>un1_FS_11, + A0=>InitReady, F0=>d_N_5_mux, F1=>un1_FS_38_i); + SLICE_63I: SLICE_63 + port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>Ready, + B0=>N_254, A0=>N_250, F0=>N_39, F1=>N_250); + SLICE_64I: SLICE_64 + port map (D1=>Ready, C1=>nRCAS_0_sqmuxa_1, B1=>nRWE_0io_RNO_1, + A1=>N_37_i_1, D0=>Ready, C0=>RASr2, B0=>N_41, A0=>CBR_fast, + F0=>nRCAS_0_sqmuxa_1, F1=>N_37_i); + SLICE_65I: SLICE_65 + port map (D1=>un1_FS_40_1_0_1, C1=>FS_13, B1=>FS_10, A1=>FS_9, D0=>FS_14, + C0=>FS_12, B0=>FS_11, A0=>FS_9, F0=>un1_FS_40_1_0_1, + F1=>un1_FS_40_1_0); + SLICE_66I: SLICE_66 + port map (C1=>S_1, B1=>N_39, A1=>CBR, D0=>S_1, C0=>nRCAS_0io_RNO_0, + B0=>nRCAS_0_sqmuxa_1, A0=>N_28_i_1, F0=>N_249_i, + F1=>nRCAS_0io_RNO_0); + SLICE_67I: SLICE_67 + port map (D1=>FS_9, C1=>wb_rst11, B1=>FS_13, A1=>N_230, + C0=>un1_wb_we95_1, B0=>wb_rst11, A0=>N_94, F0=>N_49, F1=>N_94); + SLICE_68I: SLICE_68 + port map (C1=>Ready, B1=>nRWE_0io_RNO_4, A1=>nRWE_0io_RNO_3, D0=>IS_1, + C0=>IS_2, B0=>IS_0, A0=>N_250, F0=>nRWE_0io_RNO_4, + F1=>nRWE_0io_RNO_1); + SLICE_69I: SLICE_69 + port map (C1=>nRRAS_0_sqmuxa, B1=>RCKE_c, A1=>RASr2, C0=>CO0, B0=>S_1, + A0=>Ready, F0=>nRRAS_0_sqmuxa, F1=>nRWE_0io_RNO_3); + SLICE_70I: SLICE_70 + port map (D1=>N_131, C1=>N_119, B1=>FS_14, A1=>FS_13, C0=>FS_10, + B0=>FS_11, A0=>FS_12, F0=>N_131, F1=>N_85); + SLICE_71I: SLICE_71 + port map (B1=>FS_11, A1=>FS_10, D0=>FS_12, C0=>N_116, B0=>FS_13, + A0=>FS_14, F0=>wb_dati_5_1_iv_0_a3_0_0_7, F1=>N_116); + SLICE_72I: SLICE_72 + port map (D1=>wb_rst11, C1=>N_248, B1=>FS_14, A1=>FS_13, D0=>FS_10, + C0=>FS_11, B0=>FS_12, A0=>FS_9, F0=>N_248, F1=>N_240); + SLICE_73I: SLICE_73 + port map (D1=>XOR8MEG14_1, C1=>Din_c_7, B1=>Din_c_5, A1=>Din_c_3, + D0=>C1WR_7, C0=>CMDWR_2, B0=>CmdEnable, A0=>XOR8MEG14, + M0=>Din_c_0, CE=>CmdUFMData_1_sqmuxa, CLK=>PHI2_c, + F0=>CmdUFMData_1_sqmuxa, Q0=>CmdUFMData, F1=>XOR8MEG14); + SLICE_74I: SLICE_74 + port map (D1=>wb_dati_5_1_iv_0_a3_0_6, C1=>N_246, B1=>FS_12, A1=>FS_10, + D0=>wb_dati_5, C0=>N_98, B0=>N_85, A0=>InitReady, + F0=>wb_dati_5_1_iv_0_1_6, F1=>N_98); + SLICE_75I: SLICE_75 + port map (C1=>FS_14, B1=>wb_rst11, A1=>FS_11, + D0=>wb_dati_5_1_iv_0_a3_0_3, C0=>wb_dati_2, B0=>N_128, + A0=>InitReady, F0=>wb_dati_5_1_iv_0_0_3, F1=>N_128); + SLICE_76I: SLICE_76 + port map (D1=>FS_15, C1=>FS_16, B1=>FS_17, A1=>InitReady, B0=>wb_rst11, + A0=>un1_wb_we95_1, F0=>un1_wb_rst11_1_s6_1, F1=>wb_rst11); + SLICE_77I: SLICE_77 + port map (C1=>IS_1, B1=>IS_2, A1=>IS_3, D0=>nRRAS_5_u_i_0, C0=>N_254, + B0=>N_250, A0=>IS_0, F0=>N_25, F1=>N_254); + SLICE_78I: SLICE_78 + port map (C1=>FS_12, B1=>FS_10, A1=>FS_9, C0=>N_128, B0=>N_59, A0=>FS_13, + F0=>N_89, F1=>N_59); + SLICE_79I: SLICE_79 + port map (C1=>wb_rst11, B1=>FS_14, A1=>FS_13, + D0=>wb_dati_5_1_iv_0_a3_2_0_1, C0=>wb_dati_0, B0=>N_248, + A0=>InitReady, F0=>wb_dati_5_1_iv_0_0_1, + F1=>wb_dati_5_1_iv_0_a3_2_0_1); + SLICE_80I: SLICE_80 + port map (D1=>FS_13, C1=>FS_12, B1=>FS_10, A1=>FS_9, + D0=>wb_dati_5_1_iv_0_a3_1_1_4, C0=>N_248, B0=>N_246, A0=>N_85, + F0=>wb_dati_5_1_iv_0_1_4, F1=>wb_dati_5_1_iv_0_a3_1_1_4); + SLICE_81I: SLICE_81 + port map (D1=>wb_rst11, C1=>wb_dati_5_1_iv_0_a3_3_0_7, B1=>FS_12, + A1=>FS_10, D0=>wb_dati_6, C0=>N_242, B0=>N_91, A0=>InitReady, + F0=>wb_dati_5_1_iv_0_1_7, F1=>N_242); + SLICE_82I: SLICE_82 + port map (B1=>FS_14, A1=>FS_13, D0=>wb_we95_0_tz_tz_tz, C0=>un1_FS_20_3, + B0=>FS_12, A0=>FS_11, F0=>un1_wb_we95_1, F1=>un1_FS_20_3); + SLICE_83I: SLICE_83 + port map (C1=>FS_12, B1=>FS_11, A1=>FS_10, D0=>N_120, C0=>N_119, + B0=>FS_14, A0=>FS_13, F0=>N_91, F1=>N_120); + SLICE_84I: SLICE_84 + port map (D1=>wb_we95_0_tz_tz_tz, C1=>N_228, B1=>FS_14, A1=>FS_13, + C0=>wb_we113_i, B0=>wb_we95, A0=>un1_FS_29, F0=>N_181, + F1=>un1_FS_29); + SLICE_85I: SLICE_85 + port map (C1=>wb_rst11, B1=>un1_FS_40_1_1_1, A1=>un1_FS_40_1_0, + D0=>un1_FS_40_1_1_tz, C0=>N_139, B0=>FS_10, A0=>FS_9, + F0=>un1_FS_40_1_1_1, F1=>wb_adr_cnst_m2_0); + SLICE_86I: SLICE_86 + port map (D1=>FS_12, C1=>FS_11, B1=>FS_10, A1=>FS_9, C0=>N_136, + B0=>FS_14, A0=>FS_13, F0=>N_139, F1=>N_136); + SLICE_87I: SLICE_87 + port map (B1=>FS_10, A1=>FS_9, D0=>wb_we95_0_tz_tz_tz, C0=>un1_FS_20_3, + B0=>FS_12, A0=>FS_11, F0=>wb_we95, F1=>wb_we95_0_tz_tz_tz); + SLICE_88I: SLICE_88 + port map (D1=>Ready, C1=>N_28_i_sn, B1=>N_28_i_1, A1=>N_25_i, + D0=>FWEr_fast, C0=>CO0, B0=>CASr3, A0=>CASr2, F0=>N_28_i_1, + F1=>N_28_i); + SLICE_89I: SLICE_89 + port map (B1=>wb_req, A1=>FS_0, D0=>N_233, C0=>N_102_2, B0=>N_102_1, + A0=>InitReady, F0=>N_102, F1=>N_233); + SLICE_90I: SLICE_90 + port map (D1=>ADWR_7, C1=>C1WR_2, B1=>C1WR_7, A1=>CMDWR_2, D0=>N_304, + C0=>MAin_c_7, B0=>MAin_c_6, A0=>MAin_c_5, F0=>C1WR_7, + F1=>un1_CMDWR); + SLICE_91I: SLICE_91 + port map (C1=>C1WR_7, B1=>C1WR_2, A1=>ADWR_7, D0=>MAin_c_3, C0=>MAin_c_1, + B0=>ADWR_5, A0=>ADWR_4, F0=>ADWR_7, F1=>un1_ADWR); + SLICE_92I: SLICE_92 + port map (C1=>MAin_c_4, B1=>MAin_c_3, A1=>MAin_c_2, D0=>nFWE_c, + C0=>MAin_c_1, B0=>MAin_c_0, A0=>C1WR_0, F0=>C1WR_2, F1=>C1WR_0); + SLICE_93I: SLICE_93 + port map (C1=>wb_we113_i, B1=>wb_rst11, A1=>un1_FS_37_i_0, + D0=>wb_we95_0_tz_tz_tz, C0=>N_228, B0=>FS_14, A0=>FS_13, + F0=>wb_we113_i, F1=>un1_wb_adr_0_sqmuxa_3); + SLICE_94I: SLICE_94 + port map (B1=>Bank_1, A1=>Bank_0, D0=>un1_Bank_1_4, C0=>un1_Bank_1_3, + B0=>Bank_4, A0=>Bank_3, F0=>N_304, F1=>un1_Bank_1_3); + SLICE_95I: SLICE_95 + port map (B1=>PHI2r3, A1=>PHI2r2, D0=>un1_PHI2r3_0, C0=>InitReady, + B0=>CmdValid, A0=>CmdUFMShift, F0=>N_245, F1=>un1_PHI2r3_0); + SLICE_96I: SLICE_96 + port map (C1=>FS_8, B1=>FS_6, A1=>FS_1, C0=>wb_req, B0=>N_102_1, + A0=>FS_0, F0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, F1=>N_102_1); + SLICE_97I: SLICE_97 + port map (B1=>PHI2r3, A1=>PHI2r2, D0=>InitReady, C0=>G_8_0_a3_0_0, + B0=>CmdValid_fast, A0=>CmdUFMShift_fast, F0=>un1_wb_rst14_i, + F1=>G_8_0_a3_0_0); + SLICE_98I: SLICE_98 + port map (D1=>S_1, C1=>CO0, B1=>CASr3, A1=>CASr2, C0=>nRWE_0io_RNO_2, + B0=>FWEr, A0=>CBR_fast, F0=>N_37_i_1, F1=>nRWE_0io_RNO_2); + SLICE_99I: SLICE_99 + port map (D1=>FS_13, C1=>FS_12, B1=>FS_10, A1=>FS_9, D0=>FS_13, + C0=>FS_12, B0=>FS_10, A0=>FS_9, F0=>wb_dati_5_1_iv_0_a3_0_3, + F1=>wb_dati_5_1_iv_0_a3_0_0_1); + SLICE_100I: SLICE_100 + port map (D1=>FS_14, C1=>FS_13, B1=>FS_12, A1=>FS_11, D0=>FS_14, + C0=>FS_12, B0=>FS_11, A0=>FS_10, F0=>N_230, + F1=>un1_FS_40_1_1_tz); + SLICE_101I: SLICE_101 + port map (D1=>Din_c_7, C1=>Din_c_5, B1=>Din_c_4, A1=>Din_c_3, + D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4, + F0=>un1_Din_2, F1=>CmdEnable17_5); + SLICE_102I: SLICE_102 + port map (D1=>FS_17, C1=>FS_16, B1=>FS_15, A1=>FS_12, C0=>FS_17, + B0=>FS_16, A0=>FS_15, F0=>un1_FS_11, F1=>InitReady3_0_a3_2); + SLICE_103I: SLICE_103 + port map (C1=>FS_13, B1=>FS_11, A1=>FS_9, D0=>FS_14, C0=>FS_13, + B0=>FS_11, A0=>FS_9, F0=>wb_dati_5_1_iv_0_a3_3_0_7, + F1=>wb_dati_5_1_iv_0_a3_0_6); + SLICE_104I: SLICE_104 + port map (D1=>Din_c_6, C1=>Din_c_5, B1=>Din_c_1, A1=>Din_c_0, + D0=>Din_c_6, C0=>Din_c_2, B0=>Din_c_1, A0=>Din_c_0, + F0=>CmdEnable17_4, F1=>CmdEnable16_4); + SLICE_105I: SLICE_105 + port map (C1=>nFWE_c, B1=>MAin_c_6, A1=>MAin_c_0, D0=>nFWE_c, + C0=>MAin_c_1, B0=>MAin_c_0, A0=>C1WR_0, M1=>nCCAS_c_i, + M0=>nCCAS_c_i, CLK=>nCRAS_c, F0=>CMDWR_2, Q0=>CBR, F1=>ADWR_4, + Q1=>CBR_fast); + SLICE_106I: SLICE_106 + port map (B1=>Din_c_3, A1=>Din_c_2, D0=>Din_c_7, C0=>Din_c_4, + B0=>Din_c_3, A0=>Din_c_2, M0=>CASr2, CLK=>RCLK_c, + F0=>CmdEnable16_5, Q0=>CASr3, F1=>XOR8MEG9_1); + SLICE_107I: SLICE_107 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, + A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQMH_c); + SLICE_108I: SLICE_108 + port map (D1=>IS_0, C1=>N_250, B1=>N_254, A1=>nRRAS_5_u_i_0, B0=>Ready, + A0=>N_250, M0=>nFWE_c_i, CLK=>nCRAS_c, F0=>N_253_i, + Q0=>FWEr_fast, F1=>N_25_i); + SLICE_109I: SLICE_109 + port map (B1=>wb_rst11, A1=>FS_14, B0=>wb_rst11, A0=>FS_9, F0=>N_119, + F1=>N_246); + SLICE_110I: SLICE_110 + port map (B1=>FS_12, A1=>FS_11, D0=>N_116, C0=>FS_14, B0=>FS_13, + A0=>FS_12, F0=>wb_dati_5_0_iv_0_a3_1_0, F1=>N_228); + SLICE_111I: SLICE_111 + port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, D0=>MAin_c_7, + C0=>MAin_c_5, B0=>MAin_c_4, A0=>MAin_c_2, F0=>ADWR_5, + F1=>RA_c_7); + SLICE_112I: SLICE_112 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_0, + A0=>MAin_c_0, F0=>RA_c_0, F1=>RDQML_c); + SLICE_113I: SLICE_113 + port map (C1=>nRowColSel, B1=>RowA_8, A1=>MAin_c_8, C0=>nRowColSel, + B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_8); + SLICE_114I: SLICE_114 + port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, + B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6); + SLICE_115I: SLICE_115 + port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, + B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5); + SLICE_116I: SLICE_116 + port map (D1=>n8MEGEN, C1=>XOR8MEG, B1=>Ready_fast, A1=>Din_c_6, + B0=>Din_c_6, A0=>Din_c_4, F0=>XOR8MEG14_1, F1=>RA11d_0); + SLICE_117I: SLICE_117 + port map (C1=>S_1, B1=>N_25, A1=>CBR_fast, D0=>S_1, C0=>FWEr, B0=>CO0, + A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>N_28_i_sn); + SLICE_118I: SLICE_118 + port map (B1=>Ready_fast, A1=>CROW_c_0, B0=>Ready_fast, A0=>CROW_c_1, + M0=>PHI2r2, CLK=>RCLK_c, F0=>RBAd_0_1, Q0=>PHI2r3, + F1=>RBAd_0_0); + RD_0_I: RD_0_B + port map (PADDI=>RD_in_0, IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0)); + RD_0_MGIOLI: RD_0_MGIOL + port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c); + Dout_0_I: Dout_0_B + port map (PADDO=>RD_in_0, Dout0=>Dout(0)); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + PHI2_MGIOLI: PHI2_MGIOL + port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + nRCASI: nRCASB + port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS); + nRCAS_MGIOLI: nRCAS_MGIOL + port map (IOLDO=>nRCAS_c, OPOS=>N_249_i, CLK=>RCLK_c); + nRRASI: nRRASB + port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS); + nRRAS_MGIOLI: nRRAS_MGIOL + port map (IOLDO=>nRRAS_c, OPOS=>N_25_i, CLK=>RCLK_c); + nRWEI: nRWEB + port map (IOLDO=>nRWE_c, nRWES=>nRWE); + nRWE_MGIOLI: nRWE_MGIOL + port map (IOLDO=>nRWE_c, OPOS=>N_37_i, CLK=>RCLK_c); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + nRCSI: nRCSB + port map (IOLDO=>nRCS_c, nRCSS=>nRCS); + nRCS_MGIOLI: nRCS_MGIOL + port map (IOLDO=>nRCS_c, OPOS=>N_28_i, CLK=>RCLK_c); + RD_7_I: RD_7_B + port map (PADDI=>RD_in_7, IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7)); + RD_7_MGIOLI: RD_7_MGIOL + port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c); + RD_6_I: RD_6_B + port map (PADDI=>RD_in_6, IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6)); + RD_6_MGIOLI: RD_6_MGIOL + port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c); + RD_5_I: RD_5_B + port map (PADDI=>RD_in_5, IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5)); + RD_5_MGIOLI: RD_5_MGIOL + port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c); + RD_4_I: RD_4_B + port map (PADDI=>RD_in_4, IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4)); + RD_4_MGIOLI: RD_4_MGIOL + port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c); + RD_3_I: RD_3_B + port map (PADDI=>RD_in_3, IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3)); + RD_3_MGIOLI: RD_3_MGIOL + port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c); + RD_2_I: RD_2_B + port map (PADDI=>RD_in_2, IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2)); + RD_2_MGIOLI: RD_2_MGIOL + port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c); + RD_1_I0: RD_1_B + port map (PADDI=>RD_in_1, IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1)); + RD_1_MGIOLI: RD_1_MGIOL + port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c); + RA_11_I: RA_11_B + port map (IOLDO=>RA_c_11, RA11=>RA(11)); + RA_11_MGIOLI: RA_11_MGIOL + port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c); + RA_10_I: RA_10_B + port map (IOLDO=>RA_c_10, RA10=>RA(10)); + RA_10_MGIOLI: RA_10_MGIOL + port map (IOLDO=>RA_c_10, OPOS=>N_45, LSR=>RA10s_i, CLK=>RCLK_c); + RA_9_I: RA_9_B + port map (PADDO=>RA_c_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_c_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_c_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_c_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_c_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_c_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_c_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_c_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_c_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_c_0, RA0=>RA(0)); + RBA_1_I: RBA_1_B + port map (IOLDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_1_MGIOLI: RBA_1_MGIOL + port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c); + RBA_0_I: RBA_0_B + port map (IOLDO=>RBA_c_0, RBA0=>RBA(0)); + RBA_0_MGIOLI: RBA_0_MGIOL + port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + Dout_7_I: Dout_7_B + port map (PADDO=>RD_in_7, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>RD_in_6, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>RD_in_5, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>RD_in_4, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>RD_in_3, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>RD_in_2, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>RD_in_1, Dout1=>Dout(1)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_7_MGIOLI: Din_7_MGIOL + port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_6_MGIOLI: Din_6_MGIOL + port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_5_MGIOLI: Din_5_MGIOL + port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_4_MGIOLI: Din_4_MGIOL + port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_3_MGIOLI: Din_3_MGIOL + port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_2_MGIOLI: Din_2_MGIOL + port map (DI=>Din_c_2, CLK=>PHI2_c, INP=>Bank_2); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_1_MGIOLI: Din_1_MGIOL + port map (DI=>Din_c_1, CLK=>PHI2_c, INP=>Bank_1); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + Din_0_MGIOLI: Din_0_MGIOL + port map (DI=>Din_c_0, CLK=>PHI2_c, INP=>Bank_0); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + ufmefb_EFBInst_0I: ufmefb_EFBInst_0 + port map (WBCLKI=>RCLK_c, WBRSTI=>wb_rst, WBCYCI=>wb_cyc_stb, + WBSTBI=>wb_cyc_stb, WBWEI=>wb_we, WBADRI0=>wb_adr_0, + WBADRI1=>wb_adr_1, WBADRI2=>wb_adr_2, WBADRI3=>wb_adr_3, + WBADRI4=>wb_adr_4, WBADRI5=>wb_adr_5, WBADRI6=>wb_adr_6, + WBADRI7=>wb_adr_7, WBDATI0=>wb_dati_0, WBDATI1=>wb_dati_1, + WBDATI2=>wb_dati_2, WBDATI3=>wb_dati_3, WBDATI4=>wb_dati_4, + WBDATI5=>wb_dati_5, WBDATI6=>wb_dati_6, WBDATI7=>wb_dati_7, + WBDATO0=>wb_dato_0, WBDATO1=>wb_dato_1, WBACKO=>wb_ack); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.sdf new file mode 100644 index 0000000..24faea0 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.sdf @@ -0,0 +1,4384 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Sat Aug 19 21:54:59 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 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(TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_49/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_54/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_118/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_47/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_102/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_47/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_102/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_47/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_31/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_59/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_103/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_109/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_110/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_31/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_67/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_80/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_99/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_99/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_110/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_65/C0 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SLICE_97/F1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_107/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_107/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_111/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F1 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_118/A1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_118/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F0 RBA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F1 RBA\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.vo new file mode 100644 index 0000000..c04e627 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mapvo.vo @@ -0,0 +1,5552 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd +// Netlist created on Sat Aug 19 21:54:57 2023 +// Netlist written on Sat Aug 19 21:54:59 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , + \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_304, + CmdEnable17_5, CmdEnable17_4, ADWR_7, CmdEnable16, CmdEnable17, + un1_ADWR, ADSubmitted, ADSubmitted_r, PHI2_c, CmdEnable16_5, + CmdEnable16_4, C1WR_7, C1WR_2, C1Submitted, C1Submitted_s, nCCAS_c, + nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_79_i, + Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, XOR8MEG11, + \Din_c[1] , CmdLEDEN, XOR8MEG14, N_75, LEDEN, CmdLEDEN_4, XOR8MEG18, + CmdUFMShift, CmdUFMShift_3, CmdUFMShift_fast, CmdUFMShift_3_fast, + \Din_c[0] , CmdUFMWrite_2, CmdUFMWrite, CmdUFMWrite_3, \Din_c[7] , + \Din_c[6] , \Din_c[5] , \Din_c[4] , CmdValid_r, CmdValid, CMDWR_2, + N_36_fast, CmdValid_fast, Cmdn8MEGEN, n8MEGEN, N_93, Cmdn8MEGEN_4, + nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, Ready, N_250, \IS[0] , + N_60_i_i, RA10s_i, \IS[2] , \IS[1] , N_57_i_i, IS_n1_0_x2, N_253_i, + N_58_i_i, N_45, N_116, InitReady3_0_a3_2, InitReady, InitReady3, + N_487_0, \wb_dato[1] , LEDEN_6, un1_FS_38_i, CBR, nCRAS_c_i_0, RASr, + LED_c, nRowColSel, \RowA[4] , \MAin_c[4] , PHI2r, \RA_c[4] , RASr3, + un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, PHI2r2, N_41, RCKEEN_8_u_1_0, + RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, \Bank[7] , \Bank[6] , \Bank[5] , + \Bank[2] , RCKE_2, RCKE_c, un1_Bank_1_4, N_258, N_486_0, Ready_fast, + Ready_0_sqmuxa, N_489_0, \MAin_c[1] , \MAin_c[0] , \RowAd_0[1] , + \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , \MAin_c[2] , + \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \RowA[3] , \MAin_c[5] , + \RowAd_0[5] , \RowAd_0[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , + \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , + \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , + nRRAS_5_u_i_0, XOR8MEG9_1, un1_Din_2, XOR8MEG_3_u_0_bm, XOR8MEG, + XOR8MEG_3, \wb_dato[0] , n8MEGEN_6, wb_rst10, CASr3, N_265, + nRowColSel_0_0, nRRAS_0_sqmuxa, wb_rst11, \wb_adr[0] , N_181, + \wb_dati[7] , \wb_adr_cnst_m2[0] , \wb_adr_5[1] , \wb_adr_5[0] , + un1_wb_rst14_i, \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , + \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , \wb_adr_5[5] , \wb_adr_5[4] , + \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , + un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, N_245, N_102_2, + un1_wb_cyc_stb_1_sqmuxa_0, un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, + wb_cyc_stb, \wb_dati_5_1_iv_0_a3_0_0[1] , \wb_dati_5_1_iv_0_0[1] , + N_128, N_94, wb_we, \wb_dati_5_0_iv_0_a3_1[0] , N_119, \wb_dati_5[1] , + \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , un1_wb_we95_1, + \wb_dati_5_1_iv_0_0[3] , N_240, N_49, \wb_dati_5[3] , \wb_dati_5[2] , + \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , \wb_dati_5_1_iv_0_1[4] , + un1_wb_rst11_1_s6_1, \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , + \wb_dati_5_1_iv_0_a3_0_0[7] , \wb_dati_5_1_iv_0_1[7] , N_89, + \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , \wb_dati[6] , + wb_req, un1_FS_37_i_0, N_78_i, wb_reqe_0, PHI2r3, wb_rst, wb_rste_0, + wb_we95, un1_FS_29, un1_wb_adr_0_sqmuxa_3, un1_wb_adr_0_sqmuxa_2, + CmdUFMData, wb_we_0, un1_PHI2r3_0, N_102, un1_FS_11, wb_ack, + d_N_5_mux, N_254, N_39, nRCAS_0_sqmuxa_1, nRWE_0io_RNO_1, N_37_i_1, + CBR_fast, N_37_i, un1_FS_40_1_0_1, un1_FS_40_1_0, nRCAS_0io_RNO_0, + N_28_i_1, N_249_i, N_230, nRWE_0io_RNO_4, nRWE_0io_RNO_3, N_131, N_85, + N_248, XOR8MEG14_1, \Din_c[3] , CmdUFMData_1_sqmuxa, + \wb_dati_5_1_iv_0_a3_0[6] , N_246, N_98, \wb_dati_5_1_iv_0_a3_0[3] , + N_25, N_59, \wb_dati_5_1_iv_0_a3_2_0[1] , + \wb_dati_5_1_iv_0_a3_1_1[4] , \wb_dati_5_1_iv_0_a3_3_0[7] , N_242, + N_91, wb_we95_0_tz_tz_tz, un1_FS_20_3, N_120, N_228, wb_we113_i, + un1_FS_40_1_1_1, un1_FS_40_1_1_tz, N_139, N_136, N_28_i_sn, N_25_i, + FWEr_fast, N_28_i, N_233, N_102_1, ADWR_5, ADWR_4, C1WR_0, \Bank[1] , + \Bank[0] , un1_Bank_1_3, \Bank[4] , \Bank[3] , G_8_0_a3_0_0, + nRWE_0io_RNO_2, \Din_c[2] , \RA_c[9] , RDQMH_c, \RA_c[7] , \RA_c[0] , + RDQML_c, \RA_c[1] , \RA_c[8] , \RA_c[2] , \RA_c[6] , \RA_c[3] , + \RA_c[5] , RA11d_0, \CROW_c[0] , \CROW_c[1] , \RBAd_0[1] , + \RBAd_0[0] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, + \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , + \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , + \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , + VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c), + .FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] )); + SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ), + .DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), + .Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] )); + SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_10 SLICE_10( .D1(N_304), .C1(CmdEnable17_5), .B1(CmdEnable17_4), + .A1(ADWR_7), .D0(CmdEnable16), .C0(CmdEnable17), .B0(un1_ADWR), + .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), + .Q0(ADSubmitted), .F1(CmdEnable17)); + SLICE_11 SLICE_11( .D1(CmdEnable16_5), .C1(CmdEnable16_4), .B1(C1WR_7), + .A1(C1WR_2), .C0(CmdEnable16), .B0(un1_ADWR), .A0(C1Submitted), + .DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted), + .F1(CmdEnable16)); + SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); + SLICE_16 SLICE_16( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), + .B0(\S[1] ), .A0(CO0), .DI0(N_79_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_79_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); + SLICE_17 SLICE_17( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), + .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), + .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); + SLICE_18 SLICE_18( .C1(XOR8MEG11), .B1(\Din_c[1] ), .A1(CmdLEDEN), + .C0(XOR8MEG14), .B0(N_75), .A0(LEDEN), .DI0(CmdLEDEN_4), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(CmdLEDEN_4), .Q0(CmdLEDEN), .F1(N_75)); + SLICE_20 SLICE_20( .D0(XOR8MEG14), .C0(XOR8MEG11), .B0(\Din_c[1] ), + .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(CmdUFMShift_3), .Q0(CmdUFMShift)); + SLICE_21 SLICE_21( .D0(XOR8MEG14), .C0(XOR8MEG11), .B0(\Din_c[1] ), + .A0(CmdUFMShift_fast), .DI0(CmdUFMShift_3_fast), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(CmdUFMShift_3_fast), .Q0(CmdUFMShift_fast)); + SLICE_22 SLICE_22( .B1(\Din_c[1] ), .A1(\Din_c[0] ), .D0(XOR8MEG14), + .C0(XOR8MEG11), .B0(CmdUFMWrite_2), .A0(CmdUFMWrite), .DI0(CmdUFMWrite_3), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), + .F1(CmdUFMWrite_2)); + SLICE_23 SLICE_23( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), + .A1(\Din_c[4] ), .C0(XOR8MEG14), .B0(XOR8MEG11), .A0(XOR8MEG18), + .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), + .F1(XOR8MEG11)); + SLICE_24 SLICE_24( .C1(CmdEnable), .B1(CMDWR_2), .A1(C1WR_7), .C0(XOR8MEG14), + .B0(XOR8MEG11), .A0(XOR8MEG18), .DI0(N_36_fast), .CLK(PHI2_c), + .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_25 SLICE_25( .C1(XOR8MEG11), .B1(\Din_c[0] ), .A1(Cmdn8MEGEN), + .C0(n8MEGEN), .B0(XOR8MEG14), .A0(N_93), .DI0(Cmdn8MEGEN_4), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(Cmdn8MEGEN_4), .Q0(Cmdn8MEGEN), + .F1(N_93)); + SLICE_26 SLICE_26( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i), + .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); + SLICE_28 SLICE_28( .D1(Ready), .C1(N_250), .B1(\IS[3] ), .A1(\IS[0] ), + .C0(Ready), .B0(N_250), .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), + .F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i)); + SLICE_29 SLICE_29( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), + .A0(\IS[0] ), .DI1(N_57_i_i), .DI0(IS_n1_0_x2), .CE(N_253_i), .CLK(RCLK_c), + .F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] )); + SLICE_30 SLICE_30( .B1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), .C0(\IS[1] ), + .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_58_i_i), .CE(N_253_i), .CLK(RCLK_c), + .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_45)); + SLICE_31 SLICE_31( .D1(N_116), .C1(InitReady3_0_a3_2), .B1(\FS[14] ), + .A1(\FS[13] ), .B0(InitReady), .A0(InitReady3), .DI0(N_487_0), + .CLK(RCLK_c), .F0(N_487_0), .Q0(InitReady), .F1(InitReady3)); + SLICE_32 SLICE_32( .C0(\wb_dato[1] ), .B0(InitReady), .A0(CmdLEDEN), + .DI0(LEDEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(LEDEN_6), .Q0(LEDEN)); + SLICE_34 SLICE_34( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), + .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_35 SLICE_35( .B1(\FS[7] ), .A1(\FS[3] ), .C0(nRowColSel), + .B0(\RowA[4] ), .A0(\MAin_c[4] ), .M1(PHI2r), .M0(RASr2), .CLK(RCLK_c), + .F0(\RA_c[4] ), .Q0(RASr3), .F1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), + .Q1(PHI2r2)); + SLICE_36 SLICE_36( .D1(N_41), .C1(InitReady), .B1(RASr2), .A1(Ready), + .D0(Ready), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(CBR), + .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), + .F1(RCKEEN_8_u_0_0)); + SLICE_37 SLICE_37( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), + .A1(\Bank[2] ), .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), + .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(un1_Bank_1_4)); + SLICE_38 SLICE_38( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), + .C0(N_258), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_486_0), + .CLK(RCLK_c), .F0(N_486_0), .Q0(Ready), .F1(N_258)); + SLICE_39 SLICE_39( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_258), + .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_489_0), + .CLK(RCLK_c), .F0(N_489_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); + SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), + .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), + .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); + SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), + .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), + .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); + SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), + .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), + .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); + SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), + .A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), + .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); + SLICE_44 SLICE_44( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), + .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), + .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); + SLICE_45 SLICE_45( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(N_41), + .B0(\S[1] ), .A0(CO0), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41), + .Q0(\S[1] ), .F1(nRRAS_5_u_i_0)); + SLICE_46 SLICE_46( .D1(\Din_c[1] ), .C1(\Din_c[0] ), .B1(XOR8MEG9_1), + .A1(LEDEN), .C0(un1_Din_2), .B0(XOR8MEG_3_u_0_bm), .A0(XOR8MEG), + .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), + .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_bm)); + SLICE_47 SLICE_47( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), + .A1(\FS[15] ), .C0(\wb_dato[0] ), .B0(InitReady), .A0(Cmdn8MEGEN), + .DI0(n8MEGEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(n8MEGEN_6), + .Q0(n8MEGEN), .F1(wb_rst10)); + SLICE_48 SLICE_48( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), + .C0(Ready), .B0(N_265), .A0(CO0), .DI0(nRowColSel_0_0), + .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), + .F1(N_265)); + SLICE_49 SLICE_49( .D1(wb_rst11), .C1(\wb_adr[0] ), .B1(N_181), + .A1(InitReady), .C0(\wb_dati[7] ), .B0(\wb_adr_cnst_m2[0] ), + .A0(InitReady), .DI1(\wb_adr_5[1] ), .DI0(\wb_adr_5[0] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[0] ), .Q0(\wb_adr[0] ), + .F1(\wb_adr_5[1] ), .Q1(\wb_adr[1] )); + SLICE_50 SLICE_50( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ), + .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), + .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); + SLICE_51 SLICE_51( .C1(wb_rst11), .B1(\wb_adr[4] ), .A1(InitReady), + .C0(wb_rst11), .B0(\wb_adr[3] ), .A0(InitReady), .DI1(\wb_adr_5[5] ), + .DI0(\wb_adr_5[4] ), .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[4] ), + .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_52 SLICE_52( .B1(\wb_adr[6] ), .A1(InitReady), .C0(wb_rst11), + .B0(\wb_adr[5] ), .A0(InitReady), .DI1(\wb_adr_5[7] ), .DI0(\wb_adr_5[6] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), .Q0(\wb_adr[6] ), + .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); + SLICE_53 SLICE_53( .D1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), .C1(\FS[5] ), + .B1(\FS[4] ), .A1(\FS[2] ), .D0(wb_rst11), + .C0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), .B0(N_245), .A0(N_102_2), + .DI0(un1_wb_cyc_stb_1_sqmuxa_0), .CE(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i), + .LSR(wb_rst10), .CLK(RCLK_c), .F0(un1_wb_cyc_stb_1_sqmuxa_0), + .Q0(wb_cyc_stb), .F1(N_102_2)); + SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_a3_0_0[1] ), + .C1(\wb_dati_5_1_iv_0_0[1] ), .B1(N_128), .A1(N_94), .D0(wb_we), + .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(N_119), .A0(InitReady), + .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(un1_wb_rst14_i), + .CLK(RCLK_c), .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), + .Q1(\wb_dati[1] )); + SLICE_55 SLICE_55( .D1(N_94), .C1(wb_rst11), .B1(un1_wb_we95_1), + .A1(\wb_dati_5_1_iv_0_0[3] ), .D0(\wb_dati[1] ), .C0(N_240), .B0(N_49), + .A0(InitReady), .DI1(\wb_dati_5[3] ), .DI0(\wb_dati_5[2] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), + .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); + SLICE_56 SLICE_56( .D1(\wb_dati[4] ), .C1(N_240), .B1(N_49), .A1(InitReady), + .D0(\wb_dati_5_1_iv_0_1[4] ), .C0(\wb_dati[3] ), .B0(un1_wb_rst11_1_s6_1), + .A0(InitReady), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), + .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); + SLICE_57 SLICE_57( .D1(\wb_dati_5_1_iv_0_a3_0_0[7] ), + .C1(\wb_dati_5_1_iv_0_1[7] ), .B1(N_119), .A1(N_89), + .C0(\wb_dati_5_1_iv_0_a3_0_0[1] ), .B0(\wb_dati_5_1_iv_0_1[6] ), + .A0(N_128), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), + .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] )); + SLICE_58 SLICE_58( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), + .D0(wb_rst11), .C0(wb_req), .B0(un1_FS_37_i_0), .A0(N_78_i), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_FS_37_i_0)); + SLICE_59 SLICE_59( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdValid), + .D0(wb_rst10), .C0(wb_rst), .B0(N_78_i), .A0(\FS[14] ), .DI0(wb_rste_0), + .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(N_78_i)); + SLICE_60 SLICE_60( .B1(wb_we95), .A1(un1_FS_29), .D0(un1_wb_adr_0_sqmuxa_3), + .C0(un1_wb_adr_0_sqmuxa_2), .B0(InitReady), .A0(CmdUFMData), .DI0(wb_we_0), + .CE(un1_wb_rst14_i), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_we_0), + .Q0(wb_we), .F1(un1_wb_adr_0_sqmuxa_2)); + wb_cyc_stb_RNO_SLICE_61 \wb_cyc_stb_RNO/SLICE_61 ( .D1(CmdUFMWrite), + .C1(un1_PHI2r3_0), .B1(CmdUFMShift), .A1(CmdValid), .C0(N_102), + .B0(un1_FS_11), .A0(wb_ack), .M0(InitReady), + .OFX0(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i)); + SLICE_62 SLICE_62( .D1(un1_PHI2r3_0), .C1(d_N_5_mux), .B1(InitReady), + .A1(CmdValid_fast), .D0(wb_ack), .C0(un1_FS_29), .B0(un1_FS_11), + .A0(InitReady), .F0(d_N_5_mux), .F1(un1_FS_38_i)); + SLICE_63 SLICE_63( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(Ready), .B0(N_254), .A0(N_250), .F0(N_39), .F1(N_250)); + SLICE_64 SLICE_64( .D1(Ready), .C1(nRCAS_0_sqmuxa_1), .B1(nRWE_0io_RNO_1), + .A1(N_37_i_1), .D0(Ready), .C0(RASr2), .B0(N_41), .A0(CBR_fast), + .F0(nRCAS_0_sqmuxa_1), .F1(N_37_i)); + SLICE_65 SLICE_65( .D1(un1_FS_40_1_0_1), .C1(\FS[13] ), .B1(\FS[10] ), + .A1(\FS[9] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[9] ), + .F0(un1_FS_40_1_0_1), .F1(un1_FS_40_1_0)); + SLICE_66 SLICE_66( .C1(\S[1] ), .B1(N_39), .A1(CBR), .D0(\S[1] ), + .C0(nRCAS_0io_RNO_0), .B0(nRCAS_0_sqmuxa_1), .A0(N_28_i_1), .F0(N_249_i), + .F1(nRCAS_0io_RNO_0)); + SLICE_67 SLICE_67( .D1(\FS[9] ), .C1(wb_rst11), .B1(\FS[13] ), .A1(N_230), + .C0(un1_wb_we95_1), .B0(wb_rst11), .A0(N_94), .F0(N_49), .F1(N_94)); + SLICE_68 SLICE_68( .C1(Ready), .B1(nRWE_0io_RNO_4), .A1(nRWE_0io_RNO_3), + .D0(\IS[1] ), .C0(\IS[2] ), .B0(\IS[0] ), .A0(N_250), .F0(nRWE_0io_RNO_4), + .F1(nRWE_0io_RNO_1)); + SLICE_69 SLICE_69( .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), .A1(RASr2), .C0(CO0), + .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_3)); + SLICE_70 SLICE_70( .D1(N_131), .C1(N_119), .B1(\FS[14] ), .A1(\FS[13] ), + .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_131), .F1(N_85)); + SLICE_71 SLICE_71( .B1(\FS[11] ), .A1(\FS[10] ), .D0(\FS[12] ), .C0(N_116), + .B0(\FS[13] ), .A0(\FS[14] ), .F0(\wb_dati_5_1_iv_0_a3_0_0[7] ), + .F1(N_116)); + SLICE_72 SLICE_72( .D1(wb_rst11), .C1(N_248), .B1(\FS[14] ), .A1(\FS[13] ), + .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[12] ), .A0(\FS[9] ), .F0(N_248), + .F1(N_240)); + SLICE_73 SLICE_73( .D1(XOR8MEG14_1), .C1(\Din_c[7] ), .B1(\Din_c[5] ), + .A1(\Din_c[3] ), .D0(C1WR_7), .C0(CMDWR_2), .B0(CmdEnable), .A0(XOR8MEG14), + .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CmdUFMData), .F1(XOR8MEG14)); + SLICE_74 SLICE_74( .D1(\wb_dati_5_1_iv_0_a3_0[6] ), .C1(N_246), + .B1(\FS[12] ), .A1(\FS[10] ), .D0(\wb_dati[5] ), .C0(N_98), .B0(N_85), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_98)); + SLICE_75 SLICE_75( .C1(\FS[14] ), .B1(wb_rst11), .A1(\FS[11] ), + .D0(\wb_dati_5_1_iv_0_a3_0[3] ), .C0(\wb_dati[2] ), .B0(N_128), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[3] ), .F1(N_128)); + SLICE_76 SLICE_76( .D1(\FS[15] ), .C1(\FS[16] ), .B1(\FS[17] ), + .A1(InitReady), .B0(wb_rst11), .A0(un1_wb_we95_1), + .F0(un1_wb_rst11_1_s6_1), .F1(wb_rst11)); + SLICE_77 SLICE_77( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), + .D0(nRRAS_5_u_i_0), .C0(N_254), .B0(N_250), .A0(\IS[0] ), .F0(N_25), + .F1(N_254)); + SLICE_78 SLICE_78( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .C0(N_128), + .B0(N_59), .A0(\FS[13] ), .F0(N_89), .F1(N_59)); + SLICE_79 SLICE_79( .C1(wb_rst11), .B1(\FS[14] ), .A1(\FS[13] ), + .D0(\wb_dati_5_1_iv_0_a3_2_0[1] ), .C0(\wb_dati[0] ), .B0(N_248), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\wb_dati_5_1_iv_0_a3_2_0[1] )); + SLICE_80 SLICE_80( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a3_1_1[4] ), .C0(N_248), .B0(N_246), .A0(N_85), + .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(\wb_dati_5_1_iv_0_a3_1_1[4] )); + SLICE_81 SLICE_81( .D1(wb_rst11), .C1(\wb_dati_5_1_iv_0_a3_3_0[7] ), + .B1(\FS[12] ), .A1(\FS[10] ), .D0(\wb_dati[6] ), .C0(N_242), .B0(N_91), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[7] ), .F1(N_242)); + SLICE_82 SLICE_82( .B1(\FS[14] ), .A1(\FS[13] ), .D0(wb_we95_0_tz_tz_tz), + .C0(un1_FS_20_3), .B0(\FS[12] ), .A0(\FS[11] ), .F0(un1_wb_we95_1), + .F1(un1_FS_20_3)); + SLICE_83 SLICE_83( .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_120), + .C0(N_119), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_91), .F1(N_120)); + SLICE_84 SLICE_84( .D1(wb_we95_0_tz_tz_tz), .C1(N_228), .B1(\FS[14] ), + .A1(\FS[13] ), .C0(wb_we113_i), .B0(wb_we95), .A0(un1_FS_29), .F0(N_181), + .F1(un1_FS_29)); + SLICE_85 SLICE_85( .C1(wb_rst11), .B1(un1_FS_40_1_1_1), .A1(un1_FS_40_1_0), + .D0(un1_FS_40_1_1_tz), .C0(N_139), .B0(\FS[10] ), .A0(\FS[9] ), + .F0(un1_FS_40_1_1_1), .F1(\wb_adr_cnst_m2[0] )); + SLICE_86 SLICE_86( .D1(\FS[12] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(N_136), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_139), .F1(N_136)); + SLICE_87 SLICE_87( .B1(\FS[10] ), .A1(\FS[9] ), .D0(wb_we95_0_tz_tz_tz), + .C0(un1_FS_20_3), .B0(\FS[12] ), .A0(\FS[11] ), .F0(wb_we95), + .F1(wb_we95_0_tz_tz_tz)); + SLICE_88 SLICE_88( .D1(Ready), .C1(N_28_i_sn), .B1(N_28_i_1), .A1(N_25_i), + .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_28_i_1), + .F1(N_28_i)); + SLICE_89 SLICE_89( .B1(wb_req), .A1(\FS[0] ), .D0(N_233), .C0(N_102_2), + .B0(N_102_1), .A0(InitReady), .F0(N_102), .F1(N_233)); + SLICE_90 SLICE_90( .D1(ADWR_7), .C1(C1WR_2), .B1(C1WR_7), .A1(CMDWR_2), + .D0(N_304), .C0(\MAin_c[7] ), .B0(\MAin_c[6] ), .A0(\MAin_c[5] ), + .F0(C1WR_7), .F1(un1_CMDWR)); + SLICE_91 SLICE_91( .C1(C1WR_7), .B1(C1WR_2), .A1(ADWR_7), .D0(\MAin_c[3] ), + .C0(\MAin_c[1] ), .B0(ADWR_5), .A0(ADWR_4), .F0(ADWR_7), .F1(un1_ADWR)); + SLICE_92 SLICE_92( .C1(\MAin_c[4] ), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), + .D0(nFWE_c), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), .A0(C1WR_0), .F0(C1WR_2), + .F1(C1WR_0)); + SLICE_93 SLICE_93( .C1(wb_we113_i), .B1(wb_rst11), .A1(un1_FS_37_i_0), + .D0(wb_we95_0_tz_tz_tz), .C0(N_228), .B0(\FS[14] ), .A0(\FS[13] ), + .F0(wb_we113_i), .F1(un1_wb_adr_0_sqmuxa_3)); + SLICE_94 SLICE_94( .B1(\Bank[1] ), .A1(\Bank[0] ), .D0(un1_Bank_1_4), + .C0(un1_Bank_1_3), .B0(\Bank[4] ), .A0(\Bank[3] ), .F0(N_304), + .F1(un1_Bank_1_3)); + SLICE_95 SLICE_95( .B1(PHI2r3), .A1(PHI2r2), .D0(un1_PHI2r3_0), + .C0(InitReady), .B0(CmdValid), .A0(CmdUFMShift), .F0(N_245), + .F1(un1_PHI2r3_0)); + SLICE_96 SLICE_96( .C1(\FS[8] ), .B1(\FS[6] ), .A1(\FS[1] ), .C0(wb_req), + .B0(N_102_1), .A0(\FS[0] ), .F0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), + .F1(N_102_1)); + SLICE_97 SLICE_97( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), + .C0(G_8_0_a3_0_0), .B0(CmdValid_fast), .A0(CmdUFMShift_fast), + .F0(un1_wb_rst14_i), .F1(G_8_0_a3_0_0)); + SLICE_98 SLICE_98( .D1(\S[1] ), .C1(CO0), .B1(CASr3), .A1(CASr2), + .C0(nRWE_0io_RNO_2), .B0(FWEr), .A0(CBR_fast), .F0(N_37_i_1), + .F1(nRWE_0io_RNO_2)); + SLICE_99 SLICE_99( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), + .D0(\FS[13] ), .C0(\FS[12] ), .B0(\FS[10] ), .A0(\FS[9] ), + .F0(\wb_dati_5_1_iv_0_a3_0[3] ), .F1(\wb_dati_5_1_iv_0_a3_0_0[1] )); + SLICE_100 SLICE_100( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), + .A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(N_230), .F1(un1_FS_40_1_1_tz)); + SLICE_101 SLICE_101( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[3] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), + .A0(\Din_c[4] ), .F0(un1_Din_2), .F1(CmdEnable17_5)); + SLICE_102 SLICE_102( .D1(\FS[17] ), .C1(\FS[16] ), .B1(\FS[15] ), + .A1(\FS[12] ), .C0(\FS[17] ), .B0(\FS[16] ), .A0(\FS[15] ), .F0(un1_FS_11), + .F1(InitReady3_0_a3_2)); + SLICE_103 SLICE_103( .C1(\FS[13] ), .B1(\FS[11] ), .A1(\FS[9] ), + .D0(\FS[14] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[9] ), + .F0(\wb_dati_5_1_iv_0_a3_3_0[7] ), .F1(\wb_dati_5_1_iv_0_a3_0[6] )); + SLICE_104 SLICE_104( .D1(\Din_c[6] ), .C1(\Din_c[5] ), .B1(\Din_c[1] ), + .A1(\Din_c[0] ), .D0(\Din_c[6] ), .C0(\Din_c[2] ), .B0(\Din_c[1] ), + .A0(\Din_c[0] ), .F0(CmdEnable17_4), .F1(CmdEnable16_4)); + SLICE_105 SLICE_105( .C1(nFWE_c), .B1(\MAin_c[6] ), .A1(\MAin_c[0] ), + .D0(nFWE_c), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), .A0(C1WR_0), + .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CMDWR_2), .Q0(CBR), + .F1(ADWR_4), .Q1(CBR_fast)); + SLICE_106 SLICE_106( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(\Din_c[7] ), + .C0(\Din_c[4] ), .B0(\Din_c[3] ), .A0(\Din_c[2] ), .M0(CASr2), + .CLK(RCLK_c), .F0(CmdEnable16_5), .Q0(CASr3), .F1(XOR8MEG9_1)); + SLICE_107 SLICE_107( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_108 SLICE_108( .D1(\IS[0] ), .C1(N_250), .B1(N_254), + .A1(nRRAS_5_u_i_0), .B0(Ready), .A0(N_250), .M0(nFWE_c_i), .CLK(nCRAS_c), + .F0(N_253_i), .Q0(FWEr_fast), .F1(N_25_i)); + SLICE_109 SLICE_109( .B1(wb_rst11), .A1(\FS[14] ), .B0(wb_rst11), + .A0(\FS[9] ), .F0(N_119), .F1(N_246)); + SLICE_110 SLICE_110( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_116), .C0(\FS[14] ), + .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), .F1(N_228)); + SLICE_111 SLICE_111( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), + .D0(\MAin_c[7] ), .C0(\MAin_c[5] ), .B0(\MAin_c[4] ), .A0(\MAin_c[2] ), + .F0(ADWR_5), .F1(\RA_c[7] )); + SLICE_112 SLICE_112( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), .F1(RDQML_c)); + SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ), + .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), + .F1(\RA_c[8] )); + SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), + .F1(\RA_c[6] )); + SLICE_115 SLICE_115( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), + .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), + .F1(\RA_c[5] )); + SLICE_116 SLICE_116( .D1(n8MEGEN), .C1(XOR8MEG), .B1(Ready_fast), + .A1(\Din_c[6] ), .B0(\Din_c[6] ), .A0(\Din_c[4] ), .F0(XOR8MEG14_1), + .F1(RA11d_0)); + SLICE_117 SLICE_117( .C1(\S[1] ), .B1(N_25), .A1(CBR_fast), .D0(\S[1] ), + .C0(FWEr), .B0(CO0), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(N_28_i_sn)); + SLICE_118 SLICE_118( .B1(Ready_fast), .A1(\CROW_c[0] ), .B0(Ready_fast), + .A0(\CROW_c[1] ), .M0(PHI2r2), .CLK(RCLK_c), .F0(\RBAd_0[1] ), .Q0(PHI2r3), + .F1(\RBAd_0[0] )); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), + .RD0(RD[0])); + RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), + .CLK(nCCAS_c)); + Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_249_i), .CLK(RCLK_c)); + nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), + .RD7(RD[7])); + RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), + .CLK(nCCAS_c)); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .IOLDO(\WRD[6] ), .PADDT(RD_1_i), + .RD6(RD[6])); + RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ), + .CLK(nCCAS_c)); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .IOLDO(\WRD[5] ), .PADDT(RD_1_i), + .RD5(RD[5])); + RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ), + .CLK(nCCAS_c)); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .IOLDO(\WRD[4] ), .PADDT(RD_1_i), + .RD4(RD[4])); + RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ), + .CLK(nCCAS_c)); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .IOLDO(\WRD[3] ), .PADDT(RD_1_i), + .RD3(RD[3])); + RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ), + .CLK(nCCAS_c)); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .IOLDO(\WRD[2] ), .PADDT(RD_1_i), + .RD2(RD[2])); + RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ), + .CLK(nCCAS_c)); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .IOLDO(\WRD[1] ), .PADDT(RD_1_i), + .RD1(RD[1])); + RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ), + .CLK(nCCAS_c)); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0), + .CLK(PHI2_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_45), .LSR(RA10s_i), + .CLK(RCLK_c)); + RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1])); + RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ), + .CLK(nCRAS_c)); + RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0])); + RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ), + .CLK(nCRAS_c)); + LED LED_I( .PADDO(LED_c), .LED(LED)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] )); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] )); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] )); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] )); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] )); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CLK(PHI2_c), .IN(\Bank[2] )); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CLK(PHI2_c), .IN(\Bank[1] )); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CLK(PHI2_c), .IN(\Bank[0] )); + CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0])); + MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0])); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(RCLK_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; + + lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_11 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut4 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40005 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40006 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0008 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0008 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_17 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); + wire GNDI, \SLICE_17/SLICE_17_K1_H1 , \SLICE_17/CmdEnable_s/GATE_H0 , VCCI, + CLK_NOTIN, DI0_dly, CLK_dly; + + lut40009 SLICE_17_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(\SLICE_17/SLICE_17_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_17/CmdEnable_s/GATE_H0 )); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + selmux2 SLICE_17_K0K1MUX( .D0(\SLICE_17/CmdEnable_s/GATE_H0 ), + .D1(\SLICE_17/SLICE_17_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_18 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 CmdLEDEN_4_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 CmdLEDEN_4_u( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdUFMShift_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h030A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdUFMShift_3_u_fast( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMShift_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_22 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40014 CmdUFMWrite_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40015 CmdUFMWrite_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40016 XOR8MEG11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 CmdValid_r( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40018 XOR8MEG18( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 CmdValid_r_fast( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40019 Cmdn8MEGEN_4_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 Cmdn8MEGEN_4_u( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40021 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 nFWE_pad_RNI420B( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40022 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40023 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_29 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40024 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_30 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40021 RA10_2_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut4 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_32 ( input C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40027 LEDEN_6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40028 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40029 un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40032 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40034 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40036 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40038 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_44 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40038 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40039 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0008 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40040 XOR8MEG_3_u_0_bm( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 \XOR8MEG_3_u_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h40C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40041 wb_rst10( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 n8MEGEN_6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40042 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40044 \wb_adr_5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 \wb_adr_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40037 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_51 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40046 \wb_adr_5[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \wb_adr_5[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40037 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \wb_adr_5[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40047 un1_wb_cyc_stb_2_sqmuxa_i_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40048 un1_wb_cyc_stb_1_sqmuxa_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40049 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40051 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40052 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFE4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40049 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40018 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40055 wb_reqe( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7250) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40056 PHI2r3_RNIS5A51( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40021 un1_wb_adr_0_sqmuxa_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40058 wb_we_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h888F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_cyc_stb_RNO_SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, M0, output + OFX0 ); + wire \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 , GNDI, + \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ; + + lut40059 \wb_cyc_stb_RNO/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 )); + lut40060 \wb_cyc_stb_RNO/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \wb_cyc_stb_RNO/SLICE_61_K0K1MUX ( + .D0(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ), + .D1(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40061 CmdValid_fast_RNITQBM1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 \ufmefb/EFBInst_0_RNI9PBJ ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40022 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 nRCAS_0_sqmuxa_1_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 un1_FS_40_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 un1_FS_40_1_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1108) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A2B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40067 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40068 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40069 \wb_dati_5_1_iv_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 \wb_dati_5_1_iv_0_o3[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40071 nRWE_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 nRWE_0io_RNO_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5252) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40073 nRWE_0io_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40074 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 \wb_dati_5_1_iv_0_a3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40037 wb_we113_i_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40077 \wb_dati_5_1_iv_0_a3[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40016 \FS_RNI3V8E[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40006 XOR8MEG14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdUFMData_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40042 \wb_dati_5_1_iv_0_a3[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \wb_dati_5_1_iv_0_a2_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \wb_dati_5_1_iv_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40047 \wb_adr_cnst_sn.m2_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \wb_dati_5_1_iv_0_RNO[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40080 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40082 \wb_dati_5_1_iv_0_m3[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 \wb_dati_5_1_iv_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD3D3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40018 \wb_dati_5_1_iv_0_a3_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40042 \wb_dati_5_1_iv_0_a3_1_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40083 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40042 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40029 wb_we95_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40084 un1_wb_we95_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40085 \wb_dati_5_1_iv_0_a2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \wb_dati_5_1_iv_0_a3_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40016 un1_FS_29( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40086 \wb_adr_cnst_sn.m4_32 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \wb_adr_cnst_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40088 un1_FS_40_1_1_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40089 un1_FS_40_1_o6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 un1_FS_40_1_a6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFB1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40090 un1_FS_21_1_i( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40091 wb_we95( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40092 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 un1_wb_cyc_stb_2_sqmuxa_i_o3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40032 un1_wb_cyc_stb_2_sqmuxa_i_a3( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40094 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40095 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 ADWR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40018 C1WR_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40096 C1WR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40073 un1_wb_adr_0_sqmuxa_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 wb_we113_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40037 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40032 un1_wb_cyc_stb_1_sqmuxa_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_96 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40085 un1_wb_cyc_stb_2_sqmuxa_i_a3_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 PHI2r3_RNIFT0I( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40098 CmdUFMShift_fast_RNIG9JD1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40064 nRWE_0io_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 nRWE_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut4 \wb_dati_5_1_iv_0_a3_0_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \wb_dati_5_1_iv_0_a3_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40100 un1_FS_40_1_1_tz( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40101 \wb_dati_5_1_iv_0_o3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4042) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40064 CmdEnable17_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 un1_Din_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 InitReady3_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 un1_FS_11( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \wb_dati_5_1_iv_0_a3_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \wb_dati_5_1_iv_0_a3_3_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40036 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40096 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_105 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40103 ADWR_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40014 XOR8MEG9_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40047 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_107 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40038 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_108 ( input D1, C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly; + + lut40105 nRRAS_5_u_i_0_RNILD5I( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \wb_dati_5_1_iv_0_a2_0[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_110 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40090 un1_FS_22_1_i( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40106 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40012 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 ADWR_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_112 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40090 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40012 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40012 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_115 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40012 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_116 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 RA11d( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 XOR8MEG14_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40086 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40037 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RBAd[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre PHI2r3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (IOLDO => RD0) = (0:0:0,0:0:0); + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + + xo2iobuf0110 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0110 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0111 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0111 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module PHI2_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RDQML ( input PADDO, output RDQML ); + + xo2iobuf0110 RDQML_pad( .I(PADDO), .PAD(RDQML)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + + xo2iobuf0110 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input IOLDO, output nRCAS ); + + xo2iobuf0110 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + + specify + (IOLDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0112 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0112 ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module nRRAS ( input IOLDO, output nRRAS ); + + xo2iobuf0110 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + + specify + (IOLDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0112 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0110 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0112 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + + xo2iobuf0110 RCKE_pad( .I(PADDO), .PAD(RCKE)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0113 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0113 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module nRCS ( input IOLDO, output nRCS ); + + xo2iobuf0110 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + + specify + (IOLDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0112 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input IOLDO, PADDT, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (IOLDO => RD7) = (0:0:0,0:0:0); + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_7__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input IOLDO, PADDT, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (IOLDO => RD6) = (0:0:0,0:0:0); + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_6__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input IOLDO, PADDT, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (IOLDO => RD5) = (0:0:0,0:0:0); + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_5__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input IOLDO, PADDT, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (IOLDO => RD4) = (0:0:0,0:0:0); + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_4__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input IOLDO, PADDT, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (IOLDO => RD3) = (0:0:0,0:0:0); + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_3__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input IOLDO, PADDT, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (IOLDO => RD2) = (0:0:0,0:0:0); + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_2__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input IOLDO, PADDT, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (IOLDO => RD1) = (0:0:0,0:0:0); + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0110 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0110 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0114 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0114 ( input D0, SP, CK, LSR, output Q ); + + FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + + xo2iobuf0110 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + + xo2iobuf0110 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + + xo2iobuf0110 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + + xo2iobuf0110 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + + xo2iobuf0110 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + + xo2iobuf0110 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0110 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + + xo2iobuf0110 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + + xo2iobuf0110 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0110 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input IOLDO, output RBA1 ); + + xo2iobuf0110 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + + specify + (IOLDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RBA_0_ ( input IOLDO, output RBA0 ); + + xo2iobuf0110 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + + specify + (IOLDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0115 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0115 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0116 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0116 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0116 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0116 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + + xo2iobuf0110 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + + xo2iobuf0110 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + + xo2iobuf0110 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + + xo2iobuf0110 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + + xo2iobuf0110 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + + xo2iobuf0110 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + + xo2iobuf0110 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0113 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_7__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0113 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_6__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0113 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_5__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0113 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_4__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0113 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_3__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0113 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_2__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[2] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0113 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_1__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[1] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0113 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Din_0__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0113 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0113 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0113 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0113 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0113 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0113 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0113 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0113 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0113 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0113 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0113 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0113 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(), .WBDATO3(), .WBDATO4(), .WBDATO5(), + .WBDATO6(), .WBDATO7(), .WBACKO(WBACKO), .WBCUFMIRQ(), .UFMSN(VCCI), + .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLI(GNDI), .I2C2SCLO(), + .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), .I2C2SDAOEN(), .I2C1IRQO(), + .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), .SPISCKEN(), .SPIMISOI(GNDI), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), .SPIMOSIO(), .SPIMOSIEN(), + .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), .SPIMCSN3(), .SPIMCSN4(), + .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), .SPICSNEN(), .SPISCSN(GNDI), + .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), .TCIC(GNDI), .TCINT(), .TCOC(), + .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), .PLLWEO(), .PLLADRO0(), + .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), .PLLADRO4(), .PLLDATO0(), + .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), .PLLDATO4(), .PLLDATO5(), + .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), .PLL0DATI1(GNDI), + .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), .PLL0DATI5(GNDI), + .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), .PLL1DATI0(GNDI), + .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), .PLL1DATI4(GNDI), + .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "640L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "66.7"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 1; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html index 08af2f2..18e481b 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html @@ -15,27 +15,27 @@ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr - LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document - s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf - -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui - -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf + Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf + -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset + Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-640HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 08/16/23 20:59:36 +Mapped on: 08/19/23 21:54:57 Design Summary - Number of registers: 109 out of 877 (12%) - PFU registers: 84 out of 640 (13%) + Number of registers: 111 out of 877 (13%) + PFU registers: 86 out of 640 (13%) PIO registers: 25 out of 237 (11%) - Number of SLICEs: 117 out of 320 (37%) - SLICEs as Logic/ROM: 117 out of 320 (37%) + Number of SLICEs: 113 out of 320 (35%) + SLICEs as Logic/ROM: 113 out of 320 (35%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 230 out of 640 (36%) - Number used as logic LUTs: 210 + Number of LUT4s: 222 out of 640 (35%) + Number used as logic LUTs: 202 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -58,39 +58,37 @@ Mapped on: 08/16/23 20:59:36 distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. - Number of clocks: 5 - Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) - Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk ) + Number of clocks: 4 + Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 ) + Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK ) Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 7 - Net N_245_i: 1 loads, 1 LSLICEs - Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs + Number of Clock Enables: 6 + Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs + Net XOR8MEG18: 6 loads, 6 LSLICEs + Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs - Net InitReady: 1 loads, 1 LSLICEs - Net un1_wb_clk32_i: 10 loads, 10 LSLICEs - Net N_18: 2 loads, 2 LSLICEs - Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_193_i: 2 loads, 2 LSLICEs + Net un1_wb_rst14_i: 9 loads, 9 LSLICEs + Net un1_FS_38_i: 2 loads, 2 LSLICEs + Net N_253_i: 2 loads, 2 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 0 LSLICEs - Net wb_clk23: 3 loads, 3 LSLICEs + Net wb_rst10: 3 loads, 3 LSLICEs Net wb_rst: 1 loads, 0 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net InitReady: 42 loads - Net FS[12]: 27 loads - Net FS[10]: 25 loads - Net FS[11]: 22 loads - Net FS[7]: 17 loads - Net FS[6]: 16 loads - Net Ready: 15 loads + Net InitReady: 33 loads + Net FS[13]: 22 loads + Net FS[12]: 21 loads + Net FS[14]: 20 loads + Net wb_rst11: 18 loads + Net FS[10]: 16 loads + Net Ready: 16 loads + Net FS[11]: 15 loads + Net FS[9]: 15 loads Net Ready_fast: 14 loads - Net nRowColSel: 12 loads - Net S[1]: 12 loads @@ -127,9 +125,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will +---------------------+-----------+-----------+------------+ | RDQML | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ - | RDQMH | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ + | nRCAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ | nRRAS | OUTPUT | LVCMOS33 | OUT | @@ -184,9 +182,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will +---------------------+-----------+-----------+------------+ | RBA[0] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ - | LED | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ + | nFWE | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nCRAS | INPUT | LVCMOS33 | | @@ -241,9 +239,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will +---------------------+-----------+-----------+------------+ | MAin[3] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ - | MAin[2] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ + | MAin[1] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | MAin[0] | INPUT | LVCMOS33 | | @@ -256,8 +254,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will Block GSR_INST undriven or does not drive anything - clipped. Signal nCRAS_c_i was merged into signal nCRAS_c Signal RASr2_i was merged into signal RASr2 -Signal InitReady_i was merged into signal InitReady Signal XOR8MEG.CN was merged into signal PHI2_c +Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG Signal GND undriven or does not drive anything - clipped. Signal ufmefb/VCC undriven or does not drive anything - clipped. Signal ufmefb/GND undriven or does not drive anything - clipped. @@ -299,9 +297,9 @@ Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. - Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. + Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. @@ -313,7 +311,6 @@ Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. -Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. @@ -324,8 +321,8 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. Signal N_1 undriven or does not drive anything - clipped. Block nCRAS_pad_RNIBPVB was optimized away. Block RASr2_RNIAFR1 was optimized away. -Block wb_rst_RNO_0 was optimized away. Block XOR8MEG.CN was optimized away. +Block XOR8MEG_3_u_0_am was optimized away. Block GND was optimized away. Block ufmefb/VCC was optimized away. Block ufmefb/GND was optimized away. @@ -336,8 +333,8 @@ Block ufmefb/GND was optimized away. Embedded Functional Block Connection Summary - Desired WISHBONE clock frequency: 62.5 MHz - Clock source: wb_clk + Desired WISHBONE clock frequency: 66.7 MHz + Clock source: RCLK_c Reset source: wb_rst Functions mode: I2C #1 (Primary) Function: DISABLED @@ -357,10 +354,10 @@ Block ufmefb/GND was optimized away. Timer/Counter Function Summary: ------------------------------ None - UFM Function Summary: -------------------- UFM Utilization: General Purpose Flash Memory + Initialized UFM Pages: 1 Pages (1*128 Bits) Available General Purpose Flash Memory: 191 Pages (191*128 Bits) @@ -387,7 +384,7 @@ Instance Name: ufmefb/EFBInst_0 Total CPU Time: 0 secs Total REAL Time: 0 secs - Peak Memory Usage: 37 MB + Peak Memory Usage: 57 MB @@ -417,6 +414,9 @@ Instance Name: ufmefb/EFBInst_0 + + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm index f3bf63b..69bd562 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm @@ -1,9 +1,9 @@ - - - syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file - - - - - - + + + syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd index c265c78..8440a7e 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd @@ -1 +1 @@ -[ActiveSupport NGD] +[ActiveSupport NGD] diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html index 0371599..7eb325b 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.39 -Wed Aug 16 20:59:41 2023 +Sat Aug 19 21:55:06 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:42 2023 +Sat Aug 19 21:55:09 2023 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html index 954f131..07b2afc 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html @@ -12,11 +12,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:37 2023 +Sat Aug 19 21:55:01 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui --msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml +-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Preference file: LCMXO2_640HC_impl1.prf. @@ -25,22 +25,22 @@ Preference file: LCMXO2_640HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 4.922 0 0.088 0 07 Completed +5_1 * 0 6.966 0 0.304 0 10 Completed * : Design saved. -Total (real) run time for 1-seed: 7 secs +Total (real) run time for 1-seed: 10 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" -Wed Aug 16 20:59:37 2023 +Sat Aug 19 21:55:01 2023 Best Par Run PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf Preference file: LCMXO2_640HC_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 @@ -66,45 +66,44 @@ Ignore Preference Error(s): True 63+4(JTAG)/79 85% bonded IOLOGIC 25/80 31% used - SLICE 117/320 36% used + SLICE 113/320 35% used EFB 1/1 100% used -Number of Signals: 380 -Number of Connections: 1008 +Number of Signals: 374 +Number of Connections: 978 Pin Constraint Summary: 63 out of 63 pins locked (100% locked). The following 3 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 46) - PHI2_c (driver: PHI2, clk load #: 19) + RCLK_c (driver: RCLK, clk load #: 47) + PHI2_c (driver: PHI2, clk load #: 21) nCRAS_c (driver: nCRAS, clk load #: 10) WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -The following 2 signals are selected to use the secondary clock routing resources: +The following 1 signal is selected to use the secondary clock routing resources: nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) - un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10) WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset. Starting Placer Phase 0. -.............. +............ Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. -................... -Placer score = 55012. -Finished Placer Phase 1. REAL time: 4 secs +.................... +Placer score = 53481. +Finished Placer Phase 1. REAL time: 5 secs Starting Placer Phase 2. . -Placer score = 54994 -Finished Placer Phase 2. REAL time: 4 secs +Placer score = 53406 +Finished Placer Phase 2. REAL time: 5 secs @@ -117,14 +116,13 @@ Global Clock Resources: DCC : 0 out of 8 (0%) Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21 PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 - SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 PRIMARY : 3 out of 8 (37%) - SECONDARY: 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) @@ -145,21 +143,18 @@ I/O Bank Usage Summary: | 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ -Total placer CPU time: 3 secs +Total placer CPU time: 5 secs Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. -0 connections routed; 1008 unrouted. +0 connections routed; 978 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 +Completed router resource preassignment. Real time: 8 secs -Completed router resource preassignment. Real time: 5 secs - -Start NBR router at 20:59:43 08/16/23 +Start NBR router at 21:55:09 08/19/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -174,54 +169,41 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 20:59:43 08/16/23 +Start NBR special constraint process at 21:55:09 08/19/23 -Start NBR section for initial routing at 20:59:43 08/16/23 +Start NBR section for initial routing at 21:55:10 08/19/23 Level 1, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs Level 2, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs Level 3, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs Level 4, iteration 1 -7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +Start NBR section for normal routing at 21:55:10 08/19/23 Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs +Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23 -Level 4, iteration 0 +Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23 + +Start NBR section for re-routing at 21:55:10 08/19/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs -Level 4, iteration 0 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs +Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs -Start NBR section for re-routing at 20:59:44 08/16/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs - -Start NBR section for post-routing at 20:59:44 08/16/23 +Start NBR section for post-routing at 21:55:10 08/19/23 End NBR router with 0 unrouted connection @@ -229,20 +211,17 @@ NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) - Estimated worst slack<setup> : 4.922ns + Estimated worst slack<setup> : 6.966ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 - -Total CPU time 6 secs -Total REAL time: 7 secs +Total CPU time 9 secs +Total REAL time: 9 secs Completely routed. -End of route. 1008 routed (100.00%); 0 unrouted. +End of route. 978 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 @@ -256,14 +235,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922 +PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 -PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088 +PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs +Total CPU time to completion: 9 secs +Total REAL time to completion: 10 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_premap.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_premap.htm new file mode 100644 index 0000000..0b22b53 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_premap.htm @@ -0,0 +1,9 @@ + + + syntmp/LCMXO2_640HC_impl1_premap_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt index 3aad37a..b292f34 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt @@ -1,63 +1,63 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 - -# Written on Wed Aug 16 20:59:30 2023 - -##### FILES SYNTAX CHECKED ############################################## -Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" - -#Run constraint checker to find more issues with constraints. -######################################################################### - - - -No issues found in constraint syntax. - - - -Clock Summary -************* - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 - -0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18 - -0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 - -0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - -Clock Load Summary -****************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------ -RCLK 65 RCLK(port) CASr2.C - - - -PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) - -nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) - -nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) - -System 0 - - - - -========================================================================================= + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Sat Aug 19 21:54:50 2023 + +##### FILES SYNTAX CHECKED ############################################## +Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +======================================================================================== + + +Clock Load Summary +****************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +----------------------------------------------------------------------------------------- +RCLK 65 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) + +System 0 - - - - +========================================================================================= diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html index d9a4e22..ed721b6 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html @@ -24,9 +24,9 @@ Last Process: -JEDEC File + State: -Passed + Target Device: @@ -62,15 +62,15 @@ Updated: -2023/08/16 20:59:46 +2023/08/20 05:55:58 Implementation Location: -D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 +Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1 Project File: -D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf +Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html index eccc49c..e2a2943 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html @@ -10,9 +10,9 @@ #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 -#Hostname: ZANEPC +#Hostname: ZANEMACWIN11 -# Wed Aug 16 20:59:29 2023 +# Sat Aug 19 21:54:48 2023 #Implementation: impl1 @@ -27,7 +27,7 @@ Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 -Hostname: ZANEPC +Hostname: ZANEMACWIN11 Implementation : impl1 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @@ -45,7 +45,7 @@ Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 -Hostname: ZANEPC +Hostname: ZANEMACWIN11 Implementation : impl1 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @@ -57,8 +57,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) -@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) -@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) +@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) +@I::"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) Verilog syntax check successful! Compiler output is up to date. No re-compile necessary @@ -66,41 +66,41 @@ Compiler output is up to date. No re-compile necessary Selecting top level module RAM2GS @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... -Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. +Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. Running optimization stage 1 on REFB ....... -Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB) +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2GS ....... -Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on REFB ....... -Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) +Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on EFB ....... -Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) +Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VLO ....... -Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) +Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VHI ....... -Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) +Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Wed Aug 16 20:59:29 2023 +# Sat Aug 19 21:54:48 2023 ###########################################################] ###########################################################[ @@ -115,48 +115,65 @@ Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 -Hostname: ZANEPC +Hostname: ZANEMACWIN11 Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode -Linker output is up to date. No re-linking necessary - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Wed Aug 16 20:59:29 2023 +# Sat Aug 19 21:54:48 2023 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv @END -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Wed Aug 16 20:59:29 2023 +# Sat Aug 19 21:54:48 2023 ###########################################################] +###########################################################[ -@A: multi_srs_gen output is up to date. No run necessary. -To force a re-synthesis, select [Resynthesize All] in menu [Run]. -Click link to view previous log file. -Multi-srs Generator Report -@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr" -Premap Report +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 -# Wed Aug 16 20:59:30 2023 +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sat Aug 19 21:54:50 2023 + +###########################################################] +# Sat Aug 19 21:54:50 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -169,69 +186,70 @@ Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 -Hostname: ZANEPC +Hostname: ZANEMACWIN11 Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB) -Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt -See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt" +Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt +See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt" @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) @N: FX493 |Applying initial value "0" on instance InitReady. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance Ready. @N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "1" on instance nRCAS. -@N: FX493 |Applying initial value "0" on instance CmdLEDEN. -@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. -@N: FX493 |Applying initial value "1" on instance nRCS. @N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance CmdUFMShift. +@N: FX493 |Applying initial value "0" on instance CmdUFMWrite. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "0" on instance CmdValid. +@N: FX493 |Applying initial value "1" on instance nRCS. @N: FX493 |Applying initial value "1" on instance nRRAS. -@N: FX493 |Applying initial value "0" on instance CMDUFMWrite. @N: FX493 |Applying initial value "0" on instance CmdUFMData. @N: FX493 |Applying initial value "0" on instance C1Submitted. -@N: FX493 |Applying initial value "0" on instance CmdSubmitted. @N: FX493 |Applying initial value "0" on instance ADSubmitted. @N: FX493 |Applying initial value "0" on instance XOR8MEG. @N: FX493 |Applying initial value "0" on instance CmdEnable. @N: FX493 |Applying initial value "1" on instance nRWE. -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @@ -243,7 +261,7 @@ Level Clock Frequency Period Type Group ---------------------------------------------------------------------------------------- 0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 -0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18 +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 @@ -262,7 +280,7 @@ Clock Load Pin Seq Example Seq Example Comb Exam ----------------------------------------------------------------------------------------- RCLK 65 RCLK(port) CASr2.C - - -PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) @@ -283,7 +301,7 @@ For details review file gcc_ICG_report.rpt #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ -4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s) +4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks @@ -291,7 +309,7 @@ For details review file gcc_ICG_report.rpt Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @KP:ckid0_0 RCLK port 65 nRWE -@KP:ckid0_1 PHI2 port 18 RA11 +@KP:ckid0_1 PHI2 port 19 RA11 @KP:ckid0_2 nCCAS port 8 WRD[7:0] @KP:ckid0_3 nCRAS port 14 RowA[9:0] ======================================================================================= @@ -302,25 +320,23 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) Pre-mapping successful! -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB) +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 16 20:59:32 2023 +# Sat Aug 19 21:54:51 2023 ###########################################################] -Map & Optimize Report - -# Wed Aug 16 20:59:32 2023 +# Sat Aug 19 21:54:51 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -333,117 +349,118 @@ Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 -Hostname: ZANEPC +Hostname: ZANEMACWIN11 Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) -@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":149:4:149:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @N: FX493 |Applying initial value "0" on instance IS[0]. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance IS[1]. @N: FX493 |Applying initial value "0" on instance IS[2]. @N: FX493 |Applying initial value "0" on instance IS[3]. -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) Available hyper_sources - for debug and ip models None Found -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) +Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -2.34ns 199 / 105 - 2 0h:00m:01s -2.34ns 208 / 105 - 3 0h:00m:01s -2.34ns 208 / 105 -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. + 1 0h:00m:01s -2.36ns 191 / 106 + 2 0h:00m:01s -2.36ns 206 / 106 + 3 0h:00m:01s -2.36ns 202 / 106 +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. Timing driven replication report -Added 4 Registers via timing driven replication -Added 1 LUTs via timing driven replication +Added 5 Registers via timing driven replication +Added 3 LUTs via timing driven replication - 4 0h:00m:01s -1.83ns 210 / 109 + 4 0h:00m:01s -1.83ns 206 / 111 - 5 0h:00m:01s -1.83ns 211 / 109 - 6 0h:00m:01s -1.83ns 212 / 109 - 7 0h:00m:01s -1.83ns 212 / 109 + 5 0h:00m:02s -1.83ns 207 / 111 + 6 0h:00m:02s -1.83ns 208 / 111 + 7 0h:00m:02s -1.83ns 208 / 111 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB) -Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm +Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi +@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB) +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB) -@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT246 :"y:\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @N: MT615 |Found clock nCRAS with period 350.00ns @@ -451,7 +468,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Wed Aug 16 20:59:35 2023 +# Timing report written on Sat Aug 19 21:54:55 2023 # @@ -459,7 +476,7 @@ Top view: RAM2GS Requested Frequency: 2.9 MHz Wire load mode: top Paths requested: 5 -Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc +Constraint File(s): Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @@ -471,23 +488,23 @@ Performance Summary ******************* -Worst slack in design: -1.832 +Worst slack in design: -1.828 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------- -PHI2 2.9 MHz 1.0 MHz 350.000 991.270 -1.832 declared default_clkgroup -RCLK 62.5 MHz 22.1 MHz 16.000 45.315 -0.784 declared default_clkgroup +PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup +RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.876 declared default_clkgroup nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup nCRAS 2.9 MHz 1.0 MHz 350.000 953.610 -1.725 declared default_clkgroup -System 100.0 MHz NA 10.000 NA 15.472 system system_clkgroup +System 100.0 MHz NA 10.000 NA 13.991 system system_clkgroup =================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @@ -500,13 +517,13 @@ Clocks | rise to rise | fall to fall | rise to --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- -System RCLK | 16.000 15.472 | No paths - | No paths - | No paths - -RCLK System | 16.000 14.892 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 8.605 | No paths - | No paths - | No paths - -RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths - +System RCLK | 16.000 13.991 | No paths - | No paths - | No paths - +RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.535 | No paths - | No paths - | No paths - +RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.876 | No paths - RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - -PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.832 -PHI2 PHI2 | No paths - | 350.000 346.115 | 175.000 168.921 | 175.000 173.428 +PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 +PHI2 PHI2 | No paths - | 350.000 347.059 | 175.000 168.905 | 175.000 173.428 nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.725 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. @@ -530,21 +547,21 @@ Detailed Report for Clock: PHI2 Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------- -CMDUFMWrite PHI2 FD1P3AX Q CMDUFMWrite 1.044 -1.832 -CmdSubmitted_fast PHI2 FD1S3AX Q CmdSubmitted_fast 1.044 -1.832 -CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -1.708 -CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 -Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 -CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.921 -Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.921 -Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 168.921 -Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 168.921 -================================================================================================== + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------ +CmdUFMShift_fast PHI2 FD1P3AX Q CmdUFMShift_fast 1.044 -1.828 +CmdValid_fast PHI2 FD1S3AX Q CmdValid_fast 1.044 -1.828 +CmdUFMShift PHI2 FD1P3AX Q CmdUFMShift 1.108 -1.810 +CmdValid PHI2 FD1S3AX Q CmdValid 1.108 -1.810 +CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -1.746 +CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 +Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 +CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.905 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.905 +================================================================================================ Ending Points with Worst Slack @@ -554,16 +571,16 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- -wb_adr[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[1] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[2] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[3] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[4] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[5] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[6] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[7] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_cyc_stb PHI2 FD1P3IX SP un1_wb_clk32_i 0.528 -1.832 -wb_dati[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 +wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 ======================================================================================= @@ -578,26 +595,26 @@ Path information for path number 1: + Clock delay at ending point: 0.000 (ideal) = Required time: 0.528 - - Propagation time: 2.361 + - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 + = Slack (critical) : -1.828 Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q + Starting point: CmdUFMShift_fast / Q Ending point: wb_adr[0] / SP The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[0] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[0] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ Path information for path number 2: @@ -606,26 +623,26 @@ Path information for path number 2: + Clock delay at ending point: 0.000 (ideal) = Required time: 0.528 - - Propagation time: 2.361 + - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 + = Slack (critical) : -1.828 Number of logic level(s): 1 - Starting point: CmdSubmitted_fast / Q + Starting point: CmdValid_fast / Q Ending point: wb_adr[0] / SP The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CmdSubmitted_fast FD1S3AX Q Out 1.044 1.044 r - -CmdSubmitted_fast Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 B In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 r - -un1_wb_clk32_i Net - - - - 18 -wb_adr[0] FD1P3AX SP In 0.000 2.361 r - -======================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdValid_fast FD1S3AX Q Out 1.044 1.044 r - +CmdValid_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 B In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[0] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ Path information for path number 3: @@ -634,26 +651,26 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: 0.528 - - Propagation time: 2.361 + - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 + = Slack (critical) : -1.828 Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q + Starting point: CmdUFMShift_fast / Q Ending point: wb_adr[7] / SP The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[7] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[7] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ Path information for path number 4: @@ -662,26 +679,26 @@ Path information for path number 4: + Clock delay at ending point: 0.000 (ideal) = Required time: 0.528 - - Propagation time: 2.361 + - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 + = Slack (critical) : -1.828 Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q + Starting point: CmdUFMShift_fast / Q Ending point: wb_adr[6] / SP The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[6] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[6] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ Path information for path number 5: @@ -690,26 +707,26 @@ Path information for path number 5: + Clock delay at ending point: 0.000 (ideal) = Required time: 0.528 - - Propagation time: 2.361 + - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 + = Slack (critical) : -1.828 Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q + Starting point: CmdUFMShift_fast / Q Ending point: wb_adr[5] / SP The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[5] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[5] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ @@ -727,16 +744,16 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.876 Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 -LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636 n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 -FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.605 -FS[15] RCLK FD1S3AX Q FS[15] 1.108 8.605 -FS[16] RCLK FD1S3AX Q FS[16] 1.108 8.605 -FS[6] RCLK FD1S3AX Q FS[6] 1.268 8.872 -FS[5] RCLK FD1S3AX Q FS[5] 1.228 8.912 -FS[12] RCLK FD1S3AX Q FS[12] 1.302 9.679 -FS[10] RCLK FD1S3AX Q FS[10] 1.299 9.682 +InitReady RCLK FD1S3AX Q InitReady 1.321 9.535 +FS[15] RCLK FD1S3AX Q FS[15] 1.180 9.677 +FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.677 +FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.677 +S[1] RCLK FD1S3IX Q S[1] 1.244 9.913 +S[0] RCLK FD1S3IX Q CO0 1.228 9.929 +FS[12] RCLK FD1S3AX Q FS[12] 1.284 10.121 ================================================================================== @@ -747,6 +764,7 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------ +XOR8MEG RCLK FD1P3AX D XOR8MEG_3 1.462 -0.876 RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 @@ -756,7 +774,6 @@ RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0 RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 -RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784 ==================================================================================== @@ -767,6 +784,37 @@ Worst Path Information Path information for path number 1: Requested Period: 1.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.462 + + - Propagation time: 2.339 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.876 + + Number of logic level(s): 2 + Starting point: LEDEN / Q + Ending point: XOR8MEG / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.108 1.108 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_bm ORCALUT4 A In 0.000 1.108 r - +XOR8MEG_3_u_0_bm ORCALUT4 Z Out 1.017 2.125 f - +XOR8MEG_3_u_0_bm Net - - - - 1 +XOR8MEG_3_u_0 PFUMX ALUT In 0.000 2.125 f - +XOR8MEG_3_u_0 PFUMX Z Out 0.214 2.339 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.339 f - +=================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 @@ -793,7 +841,7 @@ RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - ================================================================================= -Path information for path number 2: +Path information for path number 3: Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) @@ -821,7 +869,7 @@ RowA[9] FD1S3AX D In 0.000 1.873 f - ================================================================================= -Path information for path number 3: +Path information for path number 4: Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) @@ -849,7 +897,7 @@ RowA[8] FD1S3AX D In 0.000 1.873 r - ================================================================================= -Path information for path number 4: +Path information for path number 5: Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) @@ -877,34 +925,6 @@ RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - ================================================================================= -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[6] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[6] ORCALUT4 B In 0.000 1.256 r - -RowAd[6] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[6] Net - - - - 1 -RowA[6] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - ==================================== @@ -934,11 +954,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- -nRCAS_0io nCRAS OFS1P3BX D N_186_i 1.089 -1.725 -nRWE_0io nCRAS OFS1P3BX D N_44_i 1.089 -1.725 +nRCAS_0io nCRAS OFS1P3BX D N_249_i 1.089 -1.725 +nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.725 nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693 RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.653 -nRCS_0io nCRAS OFS1P3BX D N_32_i 1.089 -1.653 +nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.653 ======================================================================================== @@ -973,7 +993,7 @@ nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - nRCAS_0_sqmuxa_1 Net - - - - 2 nRCAS_0io_RNO ORCALUT4 B In 0.000 2.197 r - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.813 f - -N_186_i Net - - - - 1 +N_249_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 2.813 f - ======================================================================================== @@ -1004,7 +1024,7 @@ nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - nRCAS_0_sqmuxa_1 Net - - - - 2 nRWE_0io_RNO ORCALUT4 C In 0.000 2.197 r - nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.813 r - -N_44_i Net - - - - 1 +N_37_i Net - - - - 1 nRWE_0io OFS1P3BX D In 0.000 2.813 r - ======================================================================================== @@ -1035,7 +1055,7 @@ nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - nRCAS_0io_RNO_0 Net - - - - 1 nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_186_i Net - - - - 1 +N_249_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 2.781 r - ================================================================================== @@ -1063,7 +1083,7 @@ CBR FD1S3AX Q Out 1.148 1.148 r - CBR Net - - - - 4 nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r - nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f - -N_97 Net - - - - 1 +N_265 Net - - - - 1 nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f - nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f - nRowColSel_0_0 Net - - - - 1 @@ -1117,6 +1137,7 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 13.991 ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 15.472 ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 15.472 ========================================================================================= @@ -1125,13 +1146,16 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------- -LEDEN System FD1P3AX D LEDEN_6_i_m2 16.089 15.472 -n8MEGEN System FD1P3AX D n8MEGEN_6_i_m2 16.089 15.472 -===================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------- +LEDEN System FD1P3AX SP un1_FS_38_i 15.528 13.991 +n8MEGEN System FD1P3AX SP un1_FS_38_i 15.528 13.991 +wb_cyc_stb System FD1P3IX SP un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i 15.528 14.297 +LEDEN System FD1P3AX D LEDEN_6 16.089 15.472 +n8MEGEN System FD1P3AX D n8MEGEN_6 16.089 15.472 +========================================================================================================== @@ -1141,31 +1165,34 @@ Worst Path Information Path information for path number 1: Requested Period: 16.000 - - Setup time: -0.089 + - Setup time: 0.472 + Clock delay at ending point: 0.000 (ideal) - = Required time: 16.089 + = Required time: 15.528 - - Propagation time: 0.617 + - Propagation time: 1.538 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 15.472 + = Slack (non-critical) : 13.991 - Number of logic level(s): 1 - Starting point: ufmefb.EFBInst_0 / WBDATO0 - Ending point: n8MEGEN / D + Number of logic level(s): 2 + Starting point: ufmefb.EFBInst_0 / WBACKO + Ending point: LEDEN / SP The start point is clocked by System [rising] The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -ufmefb.EFBInst_0 EFB WBDATO0 Out 0.000 0.000 r - -wb_dato[0] Net - - - - 1 -n8MEGEN_6_i_m2 ORCALUT4 C In 0.000 0.000 r - -n8MEGEN_6_i_m2 ORCALUT4 Z Out 0.617 0.617 r - -n8MEGEN_6_i_m2 Net - - - - 1 -n8MEGEN FD1P3AX D In 0.000 0.617 r - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - +wb_ack Net - - - - 2 +ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 D In 0.000 0.000 r - +ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 Z Out 0.449 0.449 r - +d_N_5_mux Net - - - - 1 +CmdValid_fast_RNITQBM1 ORCALUT4 C In 0.000 0.449 r - +CmdValid_fast_RNITQBM1 ORCALUT4 Z Out 1.089 1.538 r - +un1_FS_38_i Net - - - - 2 +LEDEN FD1P3AX SP In 0.000 1.538 r - +============================================================================================= @@ -1173,16 +1200,16 @@ n8MEGEN FD1P3AX D In 0.000 0.617 r - Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB) +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB) +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) --------------------------------------- Resource Usage Report Part: lcmxo2_640hc-4 -Register bits: 109 of 640 (17%) +Register bits: 111 of 640 (17%) PIC Latch: 0 I/O cells: 63 @@ -1191,29 +1218,29 @@ Details: BB: 8 CCU2D: 10 EFB: 1 -FD1P3AX: 27 -FD1P3IX: 3 -FD1S3AX: 51 -FD1S3IX: 3 +FD1P3AX: 28 +FD1P3IX: 2 +FD1S3AX: 52 +FD1S3IX: 4 GSR: 1 IB: 25 IFS1P3DX: 9 -INV: 8 +INV: 6 OB: 30 OFS1P3BX: 4 OFS1P3DX: 11 OFS1P3JX: 1 -ORCALUT4: 206 -PFUMX: 1 +ORCALUT4: 199 +PFUMX: 3 PUR: 1 VHI: 2 VLO: 2 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB) +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Wed Aug 16 20:59:35 2023 +# Sat Aug 19 21:54:55 2023 ###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf index 2b0f89b..ca24d6c 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf @@ -1,24 +1,24 @@ -# -# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R. -# - -# Period Constraints -FREQUENCY PORT "PHI2" 2.9 MHz; -FREQUENCY PORT "nCCAS" 2.9 MHz; -FREQUENCY PORT "nCRAS" 2.9 MHz; -FREQUENCY PORT "RCLK" 62.5 MHz; - - -# Output Constraints - -# Input Constraints - -# Point-to-point Delay Constraints - - - -# Block Path Constraints - -BLOCK ASYNCPATHS; - -# End of generated Logical Preferences. +# +# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R. +# + +# Period Constraints +FREQUENCY PORT "PHI2" 2.9 MHz; +FREQUENCY PORT "nCCAS" 2.9 MHz; +FREQUENCY PORT "nCRAS" 2.9 MHz; +FREQUENCY PORT "RCLK" 62.5 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl index daed2e3..9818542 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl @@ -1,66 +1,66 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file - -#device options -set_option -technology MACHXO2 -set_option -part LCMXO2_640HC -set_option -package TG100C -set_option -speed_grade -4 - -#compilation/mapping options -set_option -symbolic_fsm_compiler true -set_option -resource_sharing true - -#use verilog 2001 standard option -set_option -vlog_std v2001 - -#map options -set_option -frequency 100 -set_option -maxfan 1000 -set_option -auto_constrain_io 0 -set_option -disable_io_insertion false -set_option -retiming false; set_option -pipe true -set_option -force_gsr false -set_option -compiler_compatible 0 -set_option -dup false - -add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc} -set_option -default_enum_encoding default - -#simulation options - - -#timing analysis options - - - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#synplifyPro options -set_option -fix_gated_and_generated_clocks 1 -set_option -update_models_cp 0 -set_option -resolve_multiple_driver 0 - - -set_option -seqshift_no_replicate 0 - -#-- add_file options -set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC} -add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v} -add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v} - -#-- top module name -set_option -top_module RAM2GS - -#-- set result format/file last -project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi} - -#-- error message log file -project -log_file {LCMXO2_640HC_impl1.srf} - -#-- set any command lines input by customer - - -#-- run Synplify with 'arrange HDL file' -project -run +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file + +#device options +set_option -technology MACHXO2 +set_option -part LCMXO2_640HC +set_option -package TG100C +set_option -speed_grade -4 + +#compilation/mapping options +set_option -symbolic_fsm_compiler true +set_option -resource_sharing true + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -maxfan 1000 +set_option -auto_constrain_io 0 +set_option -disable_io_insertion false +set_option -retiming false; set_option -pipe true +set_option -force_gsr false +set_option -compiler_compatible 0 +set_option -dup false + +add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc} +set_option -default_enum_encoding default + +#simulation options + + +#timing analysis options + + + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#synplifyPro options +set_option -fix_gated_and_generated_clocks 1 +set_option -update_models_cp 0 +set_option -resolve_multiple_driver 0 + + +set_option -seqshift_no_replicate 0 + +#-- add_file options +set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC} +add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v} +add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v} + +#-- top module name +set_option -top_module RAM2GS + +#-- set result format/file last +project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi} + +#-- error message log file +project -log_file {LCMXO2_640HC_impl1.srf} + +#-- set any command lines input by customer + + +#-- run Synplify with 'arrange HDL file' +project -run -clean diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_tw1.html new file mode 100644 index 0000000..ea2704d --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_tw1.html @@ -0,0 +1,512 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 21:54:58 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf 
+Design file:     lcmxo2_640hc_impl1_map.ncd
+Preference file: lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             158 items scored, 0 timing errors detected.
+Report:   53.254MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             844 items scored, 0 timing errors detected.
+Report:  102.312MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            158 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[2]  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               9.223ns  (33.1% logic, 66.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
+    172.414ns delay constraint less
+      0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
+
+ Physical Path Details:
+
+      Data path Din[2]_MGIOL to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
+ROUTE         1   e 1.234 *n[2]_MGIOL.IN to    SLICE_37.A1 Bank[2]
+CTOF_DEL    ---     0.495    SLICE_37.A1 to    SLICE_37.F1 SLICE_37
+ROUTE         1   e 1.234    SLICE_37.F1 to    SLICE_94.D0 un1_Bank_1_4
+CTOF_DEL    ---     0.495    SLICE_94.D0 to    SLICE_94.F0 SLICE_94
+ROUTE         2   e 1.234    SLICE_94.F0 to    SLICE_90.D0 N_304
+CTOF_DEL    ---     0.495    SLICE_90.D0 to    SLICE_90.F0 SLICE_90
+ROUTE         5   e 1.234    SLICE_90.F0 to    SLICE_91.C1 C1WR_7
+CTOF_DEL    ---     0.495    SLICE_91.C1 to    SLICE_91.F1 SLICE_91
+ROUTE         2   e 1.234    SLICE_91.F1 to    SLICE_10.B0 un1_ADWR
+CTOF_DEL    ---     0.495    SLICE_10.B0 to    SLICE_10.F0 SLICE_10
+ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    9.223   (33.1% logic, 66.9% route), 6 logic levels.
+
+Report:   53.254MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 338.168ns
+         The internal maximum frequency of the following component is 150.150 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCCAS
+
+   Delay:               6.660ns -- based on Minimum Pulse Width
+
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 338.168ns
+         The internal maximum frequency of the following component is 150.150 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCRAS
+
+   Delay:               6.660ns -- based on Minimum Pulse Width
+
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            844 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.226ns
+         The internal maximum frequency of the following component is 102.312 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    EFB        WBCLKI         ufmefb/EFBInst_0
+
+   Delay:               9.774ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 6.270ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_0io  (to RCLK_c +)
+
+   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
+     16.000ns delay constraint less
+      0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to nRCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_16.CLK to    SLICE_16.Q0 SLICE_16 (from RCLK_c)
+ROUTE         9   e 1.234    SLICE_16.Q0 to    SLICE_45.A0 CO0
+CTOF_DEL    ---     0.495    SLICE_45.A0 to    SLICE_45.F0 SLICE_45
+ROUTE         4   e 0.480    SLICE_45.F0 to    SLICE_45.A1 N_41
+CTOF_DEL    ---     0.495    SLICE_45.A1 to    SLICE_45.F1 SLICE_45
+ROUTE         2   e 1.234    SLICE_45.F1 to    SLICE_77.D0 nRRAS_5_u_i_0
+CTOF_DEL    ---     0.495    SLICE_77.D0 to    SLICE_77.F0 SLICE_77
+ROUTE         1   e 1.234    SLICE_77.F0 to   SLICE_117.B1 N_25
+CTOF_DEL    ---     0.495   SLICE_117.B1 to   SLICE_117.F1 SLICE_117
+ROUTE         1   e 1.234   SLICE_117.F1 to    SLICE_88.C1 N_28_i_sn
+CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.234    SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
+                  --------
+                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
+
+Report:  102.312MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   53.254 MHz|   6  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  102.312 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 22
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 21:54:58 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf 
+Design file:     lcmxo2_640hc_impl1_map.ncd
+Preference file: lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             158 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             844 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            158 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_10 to SLICE_10 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_10.CLK to    SLICE_10.Q0 SLICE_10 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_10.Q0 to    SLICE_10.A0 ADSubmitted
+CTOF_DEL    ---     0.101    SLICE_10.A0 to    SLICE_10.F0 SLICE_10
+ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            844 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_12 to SLICE_12 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_12 to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_12.CLK to    SLICE_12.Q0 SLICE_12 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_12.Q0 to    SLICE_12.M1 CASr (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 22
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_twr.html new file mode 100644 index 0000000..afe4a72 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_twr.html @@ -0,0 +1,2308 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 21:55:11 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf 
+Design file:     lcmxo2_640hc_impl1.ncd
+Preference file: lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             158 items scored, 0 timing errors detected.
+Report:   47.556MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             844 items scored, 0 timing errors detected.
+Report:  102.312MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            158 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.900ns (weighted slack = 323.800ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:              10.175ns  (30.0% logic, 70.0% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.175ns physical path delay Din[6]_MGIOL to SLICE_10 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 161.900ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.029       R5C8B.F0 to       R5C8D.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C8D.B1 to       R5C8D.F1 SLICE_11
+ROUTE         3     1.018       R5C8D.F1 to       R4C8D.B0 CmdEnable16
+CTOF_DEL    ---     0.495       R4C8D.B0 to       R4C8D.F0 SLICE_10
+ROUTE         1     0.000       R4C8D.F0 to      R4C8D.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                   10.175   (30.0% logic, 70.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.099ns (weighted slack = 324.198ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdValid  (to PHI2_c -)
+
+   Delay:               9.976ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.976ns physical path delay Din[6]_MGIOL to SLICE_23 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.099ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.040       R5C8B.F0 to       R5C7A.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C7A.B1 to       R5C7A.F1 SLICE_24
+ROUTE         8     0.808       R5C7A.F1 to       R5C6D.C0 XOR8MEG18
+CTOF_DEL    ---     0.495       R5C6D.C0 to       R5C6D.F0 SLICE_23
+ROUTE         1     0.000       R5C6D.F0 to      R5C6D.DI0 CmdValid_r (to PHI2_c)
+                  --------
+                    9.976   (30.6% logic, 69.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R5C6D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
+
+   Delay:               9.821ns  (26.0% logic, 74.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.821ns physical path delay Din[6]_MGIOL to SLICE_18 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.040       R5C8B.F0 to       R5C7A.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C7A.B1 to       R5C7A.F1 SLICE_24
+ROUTE         8     1.148       R5C7A.F1 to       R4C6C.CE XOR8MEG18 (to PHI2_c)
+                  --------
+                    9.821   (26.0% logic, 74.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R4C6C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)
+
+   Delay:               9.821ns  (26.0% logic, 74.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.821ns physical path delay Din[6]_MGIOL to SLICE_25 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.040       R5C8B.F0 to       R5C7A.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C7A.B1 to       R5C7A.F1 SLICE_24
+ROUTE         8     1.148       R5C7A.F1 to       R4C6A.CE XOR8MEG18 (to PHI2_c)
+                  --------
+                    9.821   (26.0% logic, 74.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R4C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.197ns (weighted slack = 324.394ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdValid_fast  (to PHI2_c -)
+
+   Delay:               9.878ns  (30.9% logic, 69.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.878ns physical path delay Din[6]_MGIOL to SLICE_24 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.197ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.040       R5C8B.F0 to       R5C7A.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C7A.B1 to       R5C7A.F1 SLICE_24
+ROUTE         8     0.710       R5C7A.F1 to       R5C7A.B0 XOR8MEG18
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_24
+ROUTE         1     0.000       R5C7A.F0 to      R5C7A.DI0 N_36_fast (to PHI2_c)
+                  --------
+                    9.878   (30.9% logic, 69.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R5C7A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.260ns (weighted slack = 324.520ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[5]  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               9.815ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.815ns physical path delay Din[5]_MGIOL to SLICE_10 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.260ns
+
+ Physical Path Details:
+
+      Data path Din[5]_MGIOL to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_T6B.CLK to     IOL_T6B.IN Din[5]_MGIOL (from PHI2_c)
+ROUTE         1     1.753     IOL_T6B.IN to       R4C7B.B1 Bank[5]
+CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.029       R5C8B.F0 to       R5C8D.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C8D.B1 to       R5C8D.F1 SLICE_11
+ROUTE         3     1.018       R5C8D.F1 to       R4C8D.B0 CmdEnable16
+CTOF_DEL    ---     0.495       R4C8D.B0 to       R4C8D.F0 SLICE_10
+ROUTE         1     0.000       R4C8D.F0 to      R4C8D.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    9.815   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_T6B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.335ns (weighted slack = 324.670ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               9.740ns  (31.3% logic, 68.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.740ns physical path delay Din[7]_MGIOL to SLICE_10 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.335ns
+
+ Physical Path Details:
+
+      Data path Din[7]_MGIOL to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2A.CLK to     IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
+ROUTE         1     1.678     IOL_L2A.IN to       R4C7B.D1 Bank[7]
+CTOF_DEL    ---     0.495       R4C7B.D1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.029       R5C8B.F0 to       R5C8D.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C8D.B1 to       R5C8D.F1 SLICE_11
+ROUTE         3     1.018       R5C8D.F1 to       R4C8D.B0 CmdEnable16
+CTOF_DEL    ---     0.495       R4C8D.B0 to       R4C8D.F0 SLICE_10
+ROUTE         1     0.000       R4C8D.F0 to      R4C8D.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    9.740   (31.3% logic, 68.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[7]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2A.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.452ns (weighted slack = 324.904ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               9.623ns  (30.5% logic, 69.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.623ns physical path delay Din[6]_MGIOL to SLICE_17 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.452ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.029       R5C8B.F0 to       R5C8D.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C8D.B1 to       R5C8D.F1 SLICE_11
+ROUTE         3     0.585       R5C8D.F1 to       R5C8A.M0 CmdEnable16
+MTOOFX_DEL  ---     0.376       R5C8A.M0 to     R5C8A.OFX0 SLICE_17
+ROUTE         1     0.000     R5C8A.OFX0 to      R5C8A.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    9.623   (30.5% logic, 69.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.459ns (weighted slack = 324.918ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[5]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdValid  (to PHI2_c -)
+
+   Delay:               9.616ns  (31.7% logic, 68.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.616ns physical path delay Din[5]_MGIOL to SLICE_23 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.459ns
+
+ Physical Path Details:
+
+      Data path Din[5]_MGIOL to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_T6B.CLK to     IOL_T6B.IN Din[5]_MGIOL (from PHI2_c)
+ROUTE         1     1.753     IOL_T6B.IN to       R4C7B.B1 Bank[5]
+CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.040       R5C8B.F0 to       R5C7A.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C7A.B1 to       R5C7A.F1 SLICE_24
+ROUTE         8     0.808       R5C7A.F1 to       R5C6D.C0 XOR8MEG18
+CTOF_DEL    ---     0.495       R5C6D.C0 to       R5C6D.F0 SLICE_23
+ROUTE         1     0.000       R5C6D.F0 to      R5C6D.DI0 CmdValid_r (to PHI2_c)
+                  --------
+                    9.616   (31.7% logic, 68.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[5]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_T6B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R5C6D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.465ns (weighted slack = 324.930ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
+
+   Delay:               9.610ns  (31.8% logic, 68.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.610ns physical path delay Din[6]_MGIOL to SLICE_11 meets
+    172.414ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 172.075ns) by 162.465ns
+
+ Physical Path Details:
+
+      Data path Din[6]_MGIOL to SLICE_11:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+C2INP_DEL   ---     0.577    IOL_L2B.CLK to     IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE         1     2.113     IOL_L2B.IN to       R4C7B.A1 Bank[6]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_37
+ROUTE         1     1.336       R4C7B.F1 to       R2C6D.B0 un1_Bank_1_4
+CTOF_DEL    ---     0.495       R2C6D.B0 to       R2C6D.F0 SLICE_94
+ROUTE         2     1.627       R2C6D.F0 to       R5C8B.C0 N_304
+CTOF_DEL    ---     0.495       R5C8B.C0 to       R5C8B.F0 SLICE_90
+ROUTE         5     1.029       R5C8B.F0 to       R5C8D.B1 C1WR_7
+CTOF_DEL    ---     0.495       R5C8D.B1 to       R5C8D.F1 SLICE_11
+ROUTE         3     0.453       R5C8D.F1 to       R5C8D.C0 CmdEnable16
+CTOF_DEL    ---     0.495       R5C8D.C0 to       R5C8D.F0 SLICE_11
+ROUTE         1     0.000       R5C8D.F0 to      R5C8D.DI0 C1Submitted_s (to PHI2_c)
+                  --------
+                    9.610   (31.8% logic, 68.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to Din[6]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.712        8.PADDI to    IOL_L2B.CLK PHI2_c
+                  --------
+                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_11:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     3.539        8.PADDI to      R5C8D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   47.556MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 338.168ns
+         The internal maximum frequency of the following component is 150.150 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCCAS
+
+   Delay:               6.660ns -- based on Minimum Pulse Width
+
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 338.168ns
+         The internal maximum frequency of the following component is 150.150 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCRAS
+
+   Delay:               6.660ns -- based on Minimum Pulse Width
+
+Report:  150.150MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            844 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.226ns
+         The internal maximum frequency of the following component is 102.312 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    EFB        WBCLKI         ufmefb/EFBInst_0
+
+   Delay:               9.774ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 6.966ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)
+
+   Delay:               8.868ns  (33.0% logic, 67.0% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.868ns physical path delay SLICE_2 to SLICE_57 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 6.966ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q0 SLICE_2 (from RCLK_c)
+ROUTE         5     1.615       R6C5A.Q0 to       R4C5D.C1 FS[15]
+CTOF_DEL    ---     0.495       R4C5D.C1 to       R4C5D.F1 SLICE_76
+ROUTE        18     1.137       R4C5D.F1 to       R2C3D.D0 wb_rst11
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_109
+ROUTE         4     1.749       R2C3D.F0 to       R3C3D.A0 N_119
+CTOF_DEL    ---     0.495       R3C3D.A0 to       R3C3D.F0 SLICE_83
+ROUTE         1     0.747       R3C3D.F0 to       R3C3B.C0 N_91
+CTOF_DEL    ---     0.495       R3C3B.C0 to       R3C3B.F0 SLICE_81
+ROUTE         1     0.693       R3C3B.F0 to       R3C3A.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL    ---     0.495       R3C3A.B1 to       R3C3A.F1 SLICE_57
+ROUTE         1     0.000       R3C3A.F1 to      R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
+                  --------
+                    8.868   (33.0% logic, 67.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C5A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R3C3A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.141ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[16]  (from RCLK_c +)
+   Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)
+
+   Delay:               8.693ns  (33.7% logic, 66.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.693ns physical path delay SLICE_2 to SLICE_57 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 7.141ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q1 SLICE_2 (from RCLK_c)
+ROUTE         5     1.440       R6C5A.Q1 to       R4C5D.B1 FS[16]
+CTOF_DEL    ---     0.495       R4C5D.B1 to       R4C5D.F1 SLICE_76
+ROUTE        18     1.137       R4C5D.F1 to       R2C3D.D0 wb_rst11
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_109
+ROUTE         4     1.749       R2C3D.F0 to       R3C3D.A0 N_119
+CTOF_DEL    ---     0.495       R3C3D.A0 to       R3C3D.F0 SLICE_83
+ROUTE         1     0.747       R3C3D.F0 to       R3C3B.C0 N_91
+CTOF_DEL    ---     0.495       R3C3B.C0 to       R3C3B.F0 SLICE_81
+ROUTE         1     0.693       R3C3B.F0 to       R3C3A.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL    ---     0.495       R3C3A.B1 to       R3C3A.F1 SLICE_57
+ROUTE         1     0.000       R3C3A.F1 to      R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
+                  --------
+                    8.693   (33.7% logic, 66.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C5A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R3C3A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.241ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[17]  (from RCLK_c +)
+   Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)
+
+   Delay:               8.593ns  (34.1% logic, 65.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.593ns physical path delay SLICE_1 to SLICE_57 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 7.241ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5     1.340       R6C5B.Q0 to       R4C5D.A1 FS[17]
+CTOF_DEL    ---     0.495       R4C5D.A1 to       R4C5D.F1 SLICE_76
+ROUTE        18     1.137       R4C5D.F1 to       R2C3D.D0 wb_rst11
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_109
+ROUTE         4     1.749       R2C3D.F0 to       R3C3D.A0 N_119
+CTOF_DEL    ---     0.495       R3C3D.A0 to       R3C3D.F0 SLICE_83
+ROUTE         1     0.747       R3C3D.F0 to       R3C3B.C0 N_91
+CTOF_DEL    ---     0.495       R3C3B.C0 to       R3C3B.F0 SLICE_81
+ROUTE         1     0.693       R3C3B.F0 to       R3C3A.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL    ---     0.495       R3C3A.B1 to       R3C3A.F1 SLICE_57
+ROUTE         1     0.000       R3C3A.F1 to      R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
+                  --------
+                    8.593   (34.1% logic, 65.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C5B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R3C3A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.305ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_0io  (to RCLK_c +)
+
+   Delay:               8.715ns  (33.6% logic, 66.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.715ns physical path delay SLICE_16 to nRCS_MGIOL meets
+     16.000ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 16.020ns) by 7.305ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to nRCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_16 (from RCLK_c)
+ROUTE         9     1.105      R5C11B.Q0 to      R6C10D.C0 CO0
+CTOF_DEL    ---     0.495      R6C10D.C0 to      R6C10D.F0 SLICE_45
+ROUTE         4     0.461      R6C10D.F0 to      R6C10D.C1 N_41
+CTOF_DEL    ---     0.495      R6C10D.C1 to      R6C10D.F1 SLICE_45
+ROUTE         2     0.972      R6C10D.F1 to      R5C11A.D0 nRRAS_5_u_i_0
+CTOF_DEL    ---     0.495      R5C11A.D0 to      R5C11A.F0 SLICE_77
+ROUTE         1     0.693      R5C11A.F0 to      R5C10C.B1 N_25
+CTOF_DEL    ---     0.495      R5C10C.B1 to      R5C10C.F1 SLICE_117
+ROUTE         1     0.958      R5C10C.F1 to      R6C11A.D1 N_28_i_sn
+CTOF_DEL    ---     0.495      R6C11A.D1 to      R6C11A.F1 SLICE_88
+ROUTE         1     1.599      R6C11A.F1 to   IOL_R6D.OPOS N_28_i (to RCLK_c)
+                  --------
+                    8.715   (33.6% logic, 66.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to nRCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.243       62.PADDI to    IOL_R6D.CLK RCLK_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.392ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         EFB        Port           ufmefb/EFBInst_0(ASIC)  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
+
+   Delay:               8.269ns  (81.9% logic, 18.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      8.269ns physical path delay ufmefb/EFBInst_0 to SLICE_47 meets
+     16.000ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 15.661ns) by 7.392ns
+
+ Physical Path Details:
+
+      Data path ufmefb/EFBInst_0 to SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+WCLKI2WBDA  ---     6.278     EFB.WBCLKI to    EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
+ROUTE         1     1.496    EFB.WBDATO0 to       R4C5B.C0 wb_dato[0]
+CTOF_DEL    ---     0.495       R4C5B.C0 to       R4C5B.F0 SLICE_47
+ROUTE         1     0.000       R4C5B.F0 to      R4C5B.DI0 n8MEGEN_6 (to RCLK_c)
+                  --------
+                    8.269   (81.9% logic, 18.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.243       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R4C5B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.416ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              InitReady  (from RCLK_c +)
+   Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)
+
+   Delay:               8.418ns  (34.8% logic, 65.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.418ns physical path delay SLICE_31 to SLICE_57 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 7.416ns
+
+ Physical Path Details:
+
+      Data path SLICE_31 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C4D.CLK to       R5C4D.Q0 SLICE_31 (from RCLK_c)
+ROUTE        33     1.165       R5C4D.Q0 to       R4C5D.D1 InitReady
+CTOF_DEL    ---     0.495       R4C5D.D1 to       R4C5D.F1 SLICE_76
+ROUTE        18     1.137       R4C5D.F1 to       R2C3D.D0 wb_rst11
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_109
+ROUTE         4     1.749       R2C3D.F0 to       R3C3D.A0 N_119
+CTOF_DEL    ---     0.495       R3C3D.A0 to       R3C3D.F0 SLICE_83
+ROUTE         1     0.747       R3C3D.F0 to       R3C3B.C0 N_91
+CTOF_DEL    ---     0.495       R3C3B.C0 to       R3C3B.F0 SLICE_81
+ROUTE         1     0.693       R3C3B.F0 to       R3C3A.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL    ---     0.495       R3C3A.B1 to       R3C3A.F1 SLICE_57
+ROUTE         1     0.000       R3C3A.F1 to      R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
+                  --------
+                    8.418   (34.8% logic, 65.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R3C3A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.490ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         EFB        Port           ufmefb/EFBInst_0(ASIC)  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
+
+   Delay:               8.171ns  (72.9% logic, 27.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      8.171ns physical path delay ufmefb/EFBInst_0 to SLICE_32 meets
+     16.000ns delay constraint less
+      0.173ns skew and
+      0.166ns DIN_SET requirement (totaling 15.661ns) by 7.490ns
+
+ Physical Path Details:
+
+      Data path ufmefb/EFBInst_0 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+WCLKI2WBDA  ---     5.461     EFB.WBCLKI to    EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c)
+ROUTE         1     2.215    EFB.WBDATO1 to       R4C6D.A0 wb_dato[1]
+CTOF_DEL    ---     0.495       R4C6D.A0 to       R4C6D.F0 SLICE_32
+ROUTE         1     0.000       R4C6D.F0 to      R4C6D.DI0 LEDEN_6 (to RCLK_c)
+                  --------
+                    8.171   (72.9% logic, 27.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.243       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R4C6D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.546ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)
+
+   Delay:               8.288ns  (29.3% logic, 70.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.288ns physical path delay SLICE_3 to SLICE_49 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 7.546ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
+ROUTE        22     2.071       R6C4D.Q0 to       R4C5A.B1 FS[13]
+CTOF_DEL    ---     0.495       R4C5A.B1 to       R4C5A.F1 SLICE_82
+ROUTE         2     0.982       R4C5A.F1 to       R4C5C.A0 un1_FS_20_3
+CTOF_DEL    ---     0.495       R4C5C.A0 to       R4C5C.F0 SLICE_87
+ROUTE         2     0.993       R4C5C.F0 to       R4C4B.A0 wb_we95
+CTOF_DEL    ---     0.495       R4C4B.A0 to       R4C4B.F0 SLICE_84
+ROUTE         1     1.810       R4C4B.F0 to       R2C2A.A1 N_181
+CTOF_DEL    ---     0.495       R2C2A.A1 to       R2C2A.F1 SLICE_49
+ROUTE         1     0.000       R2C2A.F1 to      R2C2A.DI1 wb_adr_5[1] (to RCLK_c)
+                  --------
+                    8.288   (29.3% logic, 70.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C4D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.583ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        wb_dati[6]  (to RCLK_c +)
+
+   Delay:               8.251ns  (35.5% logic, 64.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.251ns physical path delay SLICE_2 to SLICE_57 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 7.583ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q0 SLICE_2 (from RCLK_c)
+ROUTE         5     1.615       R6C5A.Q0 to       R4C5D.C1 FS[15]
+CTOF_DEL    ---     0.495       R4C5D.C1 to       R4C5D.F1 SLICE_76
+ROUTE        18     1.137       R4C5D.F1 to       R2C3D.D1 wb_rst11
+CTOF_DEL    ---     0.495       R2C3D.D1 to       R2C3D.F1 SLICE_109
+ROUTE         2     0.982       R2C3D.F1 to       R2C3A.A1 N_246
+CTOF_DEL    ---     0.495       R2C3A.A1 to       R2C3A.F1 SLICE_74
+ROUTE         1     0.967       R2C3A.F1 to       R2C3A.A0 N_98
+CTOF_DEL    ---     0.495       R2C3A.A0 to       R2C3A.F0 SLICE_74
+ROUTE         1     0.623       R2C3A.F0 to       R3C3A.D0 wb_dati_5_1_iv_0_1[6]
+CTOF_DEL    ---     0.495       R3C3A.D0 to       R3C3A.F0 SLICE_57
+ROUTE         1     0.000       R3C3A.F0 to      R3C3A.DI0 wb_dati_5[6] (to RCLK_c)
+                  --------
+                    8.251   (35.5% logic, 64.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C5A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R3C3A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.586ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_0io  (to RCLK_c +)
+
+   Delay:               8.434ns  (28.8% logic, 71.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.434ns physical path delay SLICE_34 to nRCS_MGIOL meets
+     16.000ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 16.020ns) by 7.586ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to nRCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_34 (from RCLK_c)
+ROUTE        10     1.972       R6C7A.Q1 to      R5C11C.A1 RASr2
+CTOF_DEL    ---     0.495      R5C11C.A1 to      R5C11C.F1 SLICE_63
+ROUTE         7     0.780      R5C11C.F1 to      R5C11A.C0 N_250
+CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_77
+ROUTE         1     0.693      R5C11A.F0 to      R5C10C.B1 N_25
+CTOF_DEL    ---     0.495      R5C10C.B1 to      R5C10C.F1 SLICE_117
+ROUTE         1     0.958      R5C10C.F1 to      R6C11A.D1 N_28_i_sn
+CTOF_DEL    ---     0.495      R6C11A.D1 to      R6C11A.F1 SLICE_88
+ROUTE         1     1.599      R6C11A.F1 to   IOL_R6D.OPOS N_28_i (to RCLK_c)
+                  --------
+                    8.434   (28.8% logic, 71.2% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.070       62.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to nRCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     3.243       62.PADDI to    IOL_R6D.CLK RCLK_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  102.312MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   47.556 MHz|   6  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  102.312 MHz|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 22
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 21:55:11 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf 
+Design file:     lcmxo2_640hc_impl1.ncd
+Preference file: lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             158 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             844 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            158 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_10 to SLICE_10 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_10 (from PHI2_c)
+ROUTE         2     0.132       R4C8D.Q0 to       R4C8D.A0 ADSubmitted
+CTOF_DEL    ---     0.101       R4C8D.A0 to       R4C8D.F0 SLICE_10
+ROUTE         1     0.000       R4C8D.F0 to      R4C8D.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdUFMShift_fast  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift_fast  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_21 to SLICE_21 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_21 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C6B.CLK to       R5C6B.Q0 SLICE_21 (from PHI2_c)
+ROUTE         2     0.132       R5C6B.Q0 to       R5C6B.A0 CmdUFMShift_fast
+CTOF_DEL    ---     0.101       R5C6B.A0 to       R5C6B.F0 SLICE_21
+ROUTE         1     0.000       R5C6B.F0 to      R5C6B.DI0 CmdUFMShift_3_fast (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdUFMWrite  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMWrite  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_22 to SLICE_22 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_22 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C6A.CLK to       R5C6A.Q0 SLICE_22 (from PHI2_c)
+ROUTE         2     0.132       R5C6A.Q0 to       R5C6A.A0 CmdUFMWrite
+CTOF_DEL    ---     0.101       R5C6A.A0 to       R5C6A.F0 SLICE_22
+ROUTE         1     0.000       R5C6A.F0 to      R5C6A.DI0 CmdUFMWrite_3 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_46 to SLICE_46 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_46 to SLICE_46:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7C.CLK to       R5C7C.Q0 SLICE_46 (from PHI2_c)
+ROUTE         2     0.132       R5C7C.Q0 to       R5C7C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R5C7C.A0 to       R5C7C.F0 SLICE_46
+ROUTE         1     0.000       R5C7C.F0 to      R5C7C.DI0 XOR8MEG_3 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_46:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C7C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_46:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C7C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.380ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdUFMShift  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift  (to PHI2_c -)
+
+   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.367ns physical path delay SLICE_20 to SLICE_20 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.380ns
+
+ Physical Path Details:
+
+      Data path SLICE_20 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C6C.CLK to       R5C6C.Q0 SLICE_20 (from PHI2_c)
+ROUTE         3     0.133       R5C6C.Q0 to       R5C6C.A0 CmdUFMShift
+CTOF_DEL    ---     0.101       R5C6C.A0 to       R5C6C.F0 SLICE_20
+ROUTE         1     0.000       R5C6C.F0 to      R5C6C.DI0 CmdUFMShift_3 (to PHI2_c)
+                  --------
+                    0.367   (63.8% logic, 36.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C6C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.435ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.422ns  (68.5% logic, 31.5% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.422ns physical path delay SLICE_17 to SLICE_17 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.435ns
+
+ Physical Path Details:
+
+      Data path SLICE_17 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_17 (from PHI2_c)
+ROUTE         4     0.133       R5C8A.Q0 to       R5C8A.A0 CmdEnable
+CTOOFX_DEL  ---     0.156       R5C8A.A0 to     R5C8A.OFX0 SLICE_17
+ROUTE         1     0.000     R5C8A.OFX0 to      R5C8A.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.422   (68.5% logic, 31.5% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
+
+   Delay:               0.458ns  (51.1% logic, 48.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.458ns physical path delay SLICE_11 to SLICE_11 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.471ns
+
+ Physical Path Details:
+
+      Data path SLICE_11 to SLICE_11:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8D.CLK to       R5C8D.Q0 SLICE_11 (from PHI2_c)
+ROUTE         2     0.224       R5C8D.Q0 to       R5C8D.B0 C1Submitted
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_11
+ROUTE         1     0.000       R5C8D.F0 to      R5C8D.DI0 C1Submitted_s (to PHI2_c)
+                  --------
+                    0.458   (51.1% logic, 48.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_11:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_11:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.527ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.514ns  (56.2% logic, 43.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.514ns physical path delay SLICE_17 to SLICE_17 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.527ns
+
+ Physical Path Details:
+
+      Data path SLICE_17 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_17 (from PHI2_c)
+ROUTE         4     0.225       R5C8A.Q0 to       R5C8A.B1 CmdEnable
+CTOOFX_DEL  ---     0.156       R5C8A.B1 to     R5C8A.OFX0 SLICE_17
+ROUTE         1     0.000     R5C8A.OFX0 to      R5C8A.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.514   (56.2% logic, 43.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.550ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.537ns  (53.8% logic, 46.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.537ns physical path delay SLICE_10 to SLICE_17 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.550ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_10 (from PHI2_c)
+ROUTE         2     0.248       R4C8D.Q0 to       R5C8A.D1 ADSubmitted
+CTOOFX_DEL  ---     0.156       R5C8A.D1 to     R5C8A.OFX0 SLICE_17
+ROUTE         1     0.000     R5C8A.OFX0 to      R5C8A.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.537   (53.8% logic, 46.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R4C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.550ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)
+
+   Delay:               0.522ns  (44.8% logic, 55.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.522ns physical path delay SLICE_17 to SLICE_46 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.550ns
+
+ Physical Path Details:
+
+      Data path SLICE_17 to SLICE_46:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_17 (from PHI2_c)
+ROUTE         4     0.142       R5C8A.Q0 to       R5C7A.C1 CmdEnable
+CTOF_DEL    ---     0.101       R5C7A.C1 to       R5C7A.F1 SLICE_24
+ROUTE         8     0.146       R5C7A.F1 to       R5C7C.CE XOR8MEG18 (to PHI2_c)
+                  --------
+                    0.522   (44.8% logic, 55.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_46:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        22     1.240        8.PADDI to      R5C7C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            844 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_12 to SLICE_12 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_12 to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9A.CLK to       R5C9A.Q0 SLICE_12 (from RCLK_c)
+ROUTE         1     0.152       R5C9A.Q0 to       R5C9A.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr2  (from RCLK_c +)
+   Destination:    FF         Data in        CASr3  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_12 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_12 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9A.CLK to       R5C9A.Q1 SLICE_12 (from RCLK_c)
+ROUTE         4     0.154       R5C9A.Q1 to       R5C9D.M0 CASr2 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_34 to SLICE_34 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C7A.CLK to       R6C7A.Q0 SLICE_34 (from RCLK_c)
+ROUTE         2     0.154       R6C7A.Q0 to       R6C7A.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.313ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[6]  (from RCLK_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to RCLK_c +)
+
+   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.307ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets
+     -0.060ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.006ns) by 0.313ns
+
+ Physical Path Details:
+
+      Data path SLICE_52 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C2C.CLK to       R2C2C.Q0 SLICE_52 (from RCLK_c)
+ROUTE         2     0.174       R2C2C.Q0 to    EFB.WBADRI6 wb_adr[6] (to RCLK_c)
+                  --------
+                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R2C2C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.113       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.318ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[7]  (from RCLK_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to RCLK_c +)
+
+   Delay:               0.304ns  (43.8% logic, 56.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.304ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets
+     -0.068ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.014ns) by 0.318ns
+
+ Physical Path Details:
+
+      Data path SLICE_52 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C2C.CLK to       R2C2C.Q1 SLICE_52 (from RCLK_c)
+ROUTE         1     0.171       R2C2C.Q1 to    EFB.WBADRI7 wb_adr[7] (to RCLK_c)
+                  --------
+                    0.304   (43.8% logic, 56.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R2C2C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.113       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.334ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[2]  (from RCLK_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to RCLK_c +)
+
+   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.307ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets
+     -0.081ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.027ns) by 0.334ns
+
+ Physical Path Details:
+
+      Data path SLICE_50 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C2B.CLK to       R2C2B.Q0 SLICE_50 (from RCLK_c)
+ROUTE         2     0.174       R2C2B.Q0 to    EFB.WBADRI2 wb_adr[2] (to RCLK_c)
+                  --------
+                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R2C2B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.113       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.355ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[1]  (from RCLK_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to RCLK_c +)
+
+   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.307ns physical path delay SLICE_49 to ufmefb/EFBInst_0 meets
+     -0.102ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.048ns) by 0.355ns
+
+ Physical Path Details:
+
+      Data path SLICE_49 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C2A.CLK to       R2C2A.Q1 SLICE_49 (from RCLK_c)
+ROUTE         2     0.174       R2C2A.Q1 to    EFB.WBADRI1 wb_adr[1] (to RCLK_c)
+                  --------
+                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.113       62.PADDI to     EFB.WBCLKI RCLK_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[0]  (from RCLK_c +)
+   Destination:    FF         Data in        FS[0]  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C3A.CLK to       R6C3A.Q1 SLICE_0 (from RCLK_c)
+ROUTE         3     0.132       R6C3A.Q1 to       R6C3A.A1 FS[0]
+CTOF_DEL    ---     0.101       R6C3A.A1 to       R6C3A.F1 SLICE_0
+ROUTE         1     0.000       R6C3A.F1 to      R6C3A.DI1 FS_s[0] (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[17]  (from RCLK_c +)
+   Destination:    FF         Data in        FS[17]  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5     0.132       R6C5B.Q0 to       R6C5B.A0 FS[17]
+CTOF_DEL    ---     0.101       R6C5B.A0 to       R6C5B.F0 SLICE_1
+ROUTE         1     0.000       R6C5B.F0 to      R6C5B.DI0 FS_s[17] (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C5B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C5B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[16]  (from RCLK_c +)
+   Destination:    FF         Data in        FS[16]  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_2 to SLICE_2 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C5A.CLK to       R6C5A.Q1 SLICE_2 (from RCLK_c)
+ROUTE         5     0.132       R6C5A.Q1 to       R6C5A.A1 FS[16]
+CTOF_DEL    ---     0.101       R6C5A.A1 to       R6C5A.F1 SLICE_2
+ROUTE         1     0.000       R6C5A.F1 to      R6C5A.DI1 FS_s[16] (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C5A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        47     1.059       62.PADDI to      R6C5A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 22
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.sdf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.sdf new file mode 100644 index 0000000..bf6abc0 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.sdf @@ -0,0 +1,4442 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Sat Aug 19 21:55:20 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_11") + (INSTANCE SLICE_11I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_12") + (INSTANCE SLICE_12I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_17") + (INSTANCE SLICE_17I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20I) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_21") + (INSTANCE SLICE_21I) + (DELAY + (ABSOLUTE + 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"RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO RBA1 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_MGIOL") + (INSTANCE RBA_1_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO RBA0 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_MGIOL") + (INSTANCE RBA_0_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (2371:2455:2540)(2371:2455:2540)) + ) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (1007:1069:1132)(1007:1069:1132)) + ) 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(2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_MGIOL") + (INSTANCE Din_7_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_MGIOL") + (INSTANCE Din_6_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_MGIOL") + (INSTANCE Din_5_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_MGIOL") + (INSTANCE Din_4_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_MGIOL") + (INSTANCE Din_3_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_MGIOL") + (INSTANCE Din_2_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_MGIOL") + (INSTANCE Din_1_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_MGIOL") + (INSTANCE Din_0_MGIOLI) + (DELAY + (ABSOLUTE + (IOPATH CLK INP (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_0I/Q1 SLICE_89I/B1 (781:909:1037)(781:909:1037)) + (INTERCONNECT SLICE_0I/Q1 SLICE_96I/A0 (749:874:1000)(749:874:1000)) + (INTERCONNECT SLICE_0I/F1 SLICE_0I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_12I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_12I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_16I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_28I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_37I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_38I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_39I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_45I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_47I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_48I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_49I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_49I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_53I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_54I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_54I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_55I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_55I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_57I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_57I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_106I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI SLICE_118I/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLKI/PADDI PHI2_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI nRCAS_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI nRRAS_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI nRWE_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI nRCS_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI RA_10_MGIOLI/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLKI/PADDI ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBCLKIin + (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT SLICE_0I/FCO SLICE_9I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_1I/Q0 SLICE_47I/C1 (812:966:1120)(812:966:1120)) + (INTERCONNECT SLICE_1I/Q0 SLICE_76I/A1 (1011:1175:1340)(1011:1175:1340)) + (INTERCONNECT SLICE_1I/Q0 SLICE_102I/B1 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_1I/Q0 SLICE_102I/B0 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_1I/F0 SLICE_1I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2I/Q1 SLICE_47I/B1 (786:914:1043)(786:914:1043)) + (INTERCONNECT SLICE_2I/Q1 SLICE_76I/B1 (1113:1276:1440)(1113:1276:1440)) + (INTERCONNECT SLICE_2I/Q1 SLICE_102I/D1 (882:979:1077)(882:979:1077)) + (INTERCONNECT SLICE_2I/Q1 SLICE_102I/D0 (882:979:1077)(882:979:1077)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2I/Q0 SLICE_47I/A1 (1446:1640:1835)(1446:1640:1835)) + (INTERCONNECT SLICE_2I/Q0 SLICE_76I/C1 (1247:1431:1615)(1247:1431:1615)) + (INTERCONNECT SLICE_2I/Q0 SLICE_102I/A1 (2137:2398:2659)(2137:2398:2659)) + (INTERCONNECT SLICE_2I/Q0 SLICE_102I/C0 (539:652:765)(539:652:765)) + (INTERCONNECT SLICE_2I/F1 SLICE_2I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F0 SLICE_2I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3I/Q1 SLICE_31I/C1 (543:680:817)(543:680:817)) + (INTERCONNECT SLICE_3I/Q1 SLICE_58I/C1 (543:680:817)(543:680:817)) + (INTERCONNECT SLICE_3I/Q1 SLICE_59I/A0 (742:889:1037)(742:889:1037)) + (INTERCONNECT SLICE_3I/Q1 SLICE_65I/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3I/Q1 SLICE_70I/D1 (1244:1399:1555)(1244:1399:1555)) + (INTERCONNECT SLICE_3I/Q1 SLICE_71I/D0 (1619:1807:1995)(1619:1807:1995)) + (INTERCONNECT SLICE_3I/Q1 SLICE_72I/C1 (1256:1465:1675)(1256:1465:1675)) + (INTERCONNECT SLICE_3I/Q1 SLICE_75I/B1 (1814:2071:2329)(1814:2071:2329)) + (INTERCONNECT SLICE_3I/Q1 SLICE_79I/C1 (1256:1465:1675)(1256:1465:1675)) + (INTERCONNECT SLICE_3I/Q1 SLICE_82I/A1 (1444:1663:1882)(1444:1663:1882)) + (INTERCONNECT SLICE_3I/Q1 SLICE_83I/C0 (1630:1873:2116)(1630:1873:2116)) + (INTERCONNECT SLICE_3I/Q1 SLICE_84I/B1 (1384:1606:1828)(1384:1606:1828)) + (INTERCONNECT SLICE_3I/Q1 SLICE_86I/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3I/Q1 SLICE_93I/C0 (815:987:1159)(815:987:1159)) + (INTERCONNECT SLICE_3I/Q1 SLICE_100I/D1 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3I/Q1 SLICE_100I/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3I/Q1 SLICE_103I/A0 (1829:2082:2336)(1829:2082:2336)) + (INTERCONNECT SLICE_3I/Q1 SLICE_109I/A1 (1448:1668:1889)(1448:1668:1889)) + (INTERCONNECT SLICE_3I/Q1 SLICE_110I/A0 (1352:1571:1791)(1352:1571:1791)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3I/Q0 SLICE_31I/A1 (1101:1264:1427)(1101:1264:1427)) + (INTERCONNECT SLICE_3I/Q0 SLICE_58I/A1 (774:902:1030)(774:902:1030)) + (INTERCONNECT SLICE_3I/Q0 SLICE_65I/B1 (1981:2222:2464)(1981:2222:2464)) + (INTERCONNECT SLICE_3I/Q0 SLICE_67I/B1 (1518:1717:1916)(1518:1717:1916)) + (INTERCONNECT SLICE_3I/Q0 SLICE_70I/B1 (1986:2228:2470)(1986:2228:2470)) + (INTERCONNECT SLICE_3I/Q0 SLICE_71I/C0 (2483:2784:3085)(2483:2784:3085)) + (INTERCONNECT SLICE_3I/Q0 SLICE_72I/B1 (1191:1355:1519)(1191:1355:1519)) + (INTERCONNECT SLICE_3I/Q0 SLICE_78I/B0 (2366:2641:2916)(2366:2641:2916)) + (INTERCONNECT SLICE_3I/Q0 SLICE_79I/B1 (1191:1355:1519)(1191:1355:1519)) + (INTERCONNECT SLICE_3I/Q0 SLICE_80I/A1 (2281:2555:2830)(2281:2555:2830)) + (INTERCONNECT SLICE_3I/Q0 SLICE_82I/B1 (1657:1864:2071)(1657:1864:2071)) + (INTERCONNECT SLICE_3I/Q0 SLICE_83I/B0 (2693:3003:3313)(2693:3003:3313)) + (INTERCONNECT SLICE_3I/Q0 SLICE_84I/C1 (902:1054:1207)(902:1054:1207)) + (INTERCONNECT SLICE_3I/Q0 SLICE_86I/B0 (1981:2222:2464)(1981:2222:2464)) + (INTERCONNECT SLICE_3I/Q0 SLICE_93I/B0 (2730:3036:3343)(2730:3036:3343)) + (INTERCONNECT SLICE_3I/Q0 SLICE_99I/B1 (1529:1730:1931)(1529:1730:1931)) + (INTERCONNECT SLICE_3I/Q0 SLICE_99I/B0 (1529:1730:1931)(1529:1730:1931)) + (INTERCONNECT SLICE_3I/Q0 SLICE_100I/C1 (1667:1879:2091)(1667:1879:2091)) + (INTERCONNECT SLICE_3I/Q0 SLICE_103I/D1 (2472:2718:2964)(2472:2718:2964)) + (INTERCONNECT SLICE_3I/Q0 SLICE_103I/D0 (2472:2718:2964)(2472:2718:2964)) + (INTERCONNECT SLICE_3I/Q0 SLICE_110I/D0 (564:626:689)(564:626:689)) + (INTERCONNECT SLICE_3I/F1 SLICE_3I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F0 SLICE_3I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_4I/Q1 SLICE_58I/B1 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_4I/Q1 SLICE_65I/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4I/Q1 SLICE_70I/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4I/Q1 SLICE_71I/B0 (1859:2096:2333)(1859:2096:2333)) + (INTERCONNECT SLICE_4I/Q1 SLICE_72I/D0 (1180:1312:1444)(1180:1312:1444)) + (INTERCONNECT SLICE_4I/Q1 SLICE_74I/B1 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4I/Q1 SLICE_78I/C1 (1976:2239:2502)(1976:2239:2502)) + (INTERCONNECT SLICE_4I/Q1 SLICE_80I/D1 (1574:1746:1918)(1574:1746:1918)) + (INTERCONNECT SLICE_4I/Q1 SLICE_81I/D1 (1965:2173:2381)(1965:2173:2381)) + (INTERCONNECT SLICE_4I/Q1 SLICE_82I/B0 (1433:1634:1835)(1433:1634:1835)) + (INTERCONNECT SLICE_4I/Q1 SLICE_83I/B1 (2207:2483:2759)(2207:2483:2759)) + (INTERCONNECT SLICE_4I/Q1 SLICE_86I/A1 (1784:2021:2259)(1784:2021:2259)) + (INTERCONNECT SLICE_4I/Q1 SLICE_87I/B0 (1433:1634:1835)(1433:1634:1835)) + (INTERCONNECT SLICE_4I/Q1 SLICE_99I/C1 (1165:1357:1550)(1165:1357:1550)) + (INTERCONNECT SLICE_4I/Q1 SLICE_99I/C0 (1165:1357:1550)(1165:1357:1550)) + (INTERCONNECT SLICE_4I/Q1 SLICE_100I/B1 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4I/Q1 SLICE_100I/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4I/Q1 SLICE_102I/C1 (1566:1785:2005)(1566:1785:2005)) + (INTERCONNECT SLICE_4I/Q1 SLICE_110I/B1 (1058:1226:1395)(1058:1226:1395)) + (INTERCONNECT SLICE_4I/Q1 SLICE_110I/B0 (1058:1226:1395)(1058:1226:1395)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_4I/Q0 SLICE_65I/A0 (1567:1770:1973)(1567:1770:1973)) + (INTERCONNECT SLICE_4I/Q0 SLICE_70I/C0 (1445:1632:1819)(1445:1632:1819)) + (INTERCONNECT SLICE_4I/Q0 SLICE_71I/A1 (2024:2254:2485)(2024:2254:2485)) + (INTERCONNECT SLICE_4I/Q0 SLICE_72I/C0 (1004:1165:1326)(1004:1165:1326)) + (INTERCONNECT SLICE_4I/Q0 SLICE_75I/D1 (993:1099:1205)(993:1099:1205)) + (INTERCONNECT SLICE_4I/Q0 SLICE_82I/D0 (1721:1890:2059)(1721:1890:2059)) + (INTERCONNECT SLICE_4I/Q0 SLICE_83I/A1 (2351:2616:2882)(2351:2616:2882)) + (INTERCONNECT SLICE_4I/Q0 SLICE_86I/D1 (1357:1494:1632)(1357:1494:1632)) + (INTERCONNECT SLICE_4I/Q0 SLICE_87I/D0 (1428:1559:1691)(1428:1559:1691)) + (INTERCONNECT SLICE_4I/Q0 SLICE_100I/A1 (1573:1776:1980)(1573:1776:1980)) + (INTERCONNECT SLICE_4I/Q0 SLICE_100I/A0 (1573:1776:1980)(1573:1776:1980)) + (INTERCONNECT SLICE_4I/Q0 SLICE_103I/B1 (2056:2289:2522)(2056:2289:2522)) + (INTERCONNECT SLICE_4I/Q0 SLICE_103I/B0 (2056:2289:2522)(2056:2289:2522)) + (INTERCONNECT SLICE_4I/Q0 SLICE_110I/C1 (546:662:779)(546:662:779)) + (INTERCONNECT SLICE_4I/F1 SLICE_4I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F0 SLICE_4I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_5I/Q1 SLICE_65I/C1 (1364:1555:1746)(1364:1555:1746)) + (INTERCONNECT SLICE_5I/Q1 SLICE_70I/A0 (1665:1863:2062)(1665:1863:2062)) + (INTERCONNECT SLICE_5I/Q1 SLICE_71I/C1 (1830:2049:2269)(1830:2049:2269)) + (INTERCONNECT SLICE_5I/Q1 SLICE_72I/A0 (1199:1369:1539)(1199:1369:1539)) + (INTERCONNECT SLICE_5I/Q1 SLICE_74I/C1 (1466:1654:1842)(1466:1654:1842)) + (INTERCONNECT SLICE_5I/Q1 SLICE_78I/A1 (1665:1863:2062)(1665:1863:2062)) + (INTERCONNECT SLICE_5I/Q1 SLICE_80I/B1 (1697:1898:2099)(1697:1898:2099)) + (INTERCONNECT SLICE_5I/Q1 SLICE_81I/B1 (1697:1898:2099)(1697:1898:2099)) + (INTERCONNECT SLICE_5I/Q1 SLICE_83I/D1 (1455:1588:1721)(1455:1588:1721)) + (INTERCONNECT SLICE_5I/Q1 SLICE_85I/D0 (1353:1489:1625)(1353:1489:1625)) + (INTERCONNECT SLICE_5I/Q1 SLICE_86I/B1 (1595:1799:2003)(1595:1799:2003)) + (INTERCONNECT SLICE_5I/Q1 SLICE_87I/B1 (1042:1199:1356)(1042:1199:1356)) + (INTERCONNECT SLICE_5I/Q1 SLICE_99I/D1 (989:1093:1198)(989:1093:1198)) + (INTERCONNECT SLICE_5I/Q1 SLICE_99I/D0 (989:1093:1198)(989:1093:1198)) + (INTERCONNECT SLICE_5I/Q1 SLICE_100I/C0 (1175:1350:1526)(1175:1350:1526)) + (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_5I/Q0 SLICE_65I/A1 (1885:2121:2357)(1885:2121:2357)) + (INTERCONNECT SLICE_5I/Q0 SLICE_65I/C0 (1359:1549:1740)(1359:1549:1740)) + (INTERCONNECT SLICE_5I/Q0 SLICE_67I/C1 (1005:1165:1325)(1005:1165:1325)) + (INTERCONNECT SLICE_5I/Q0 SLICE_72I/B0 (1563:1771:1979)(1563:1771:1979)) + (INTERCONNECT SLICE_5I/Q0 SLICE_78I/B1 (1226:1398:1570)(1226:1398:1570)) + (INTERCONNECT SLICE_5I/Q0 SLICE_80I/C1 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5I/Q0 SLICE_85I/A0 (1901:2138:2376)(1901:2138:2376)) + (INTERCONNECT SLICE_5I/Q0 SLICE_86I/C1 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5I/Q0 SLICE_87I/D1 (796:890:985)(796:890:985)) + (INTERCONNECT SLICE_5I/Q0 SLICE_99I/A1 (1443:1639:1835)(1443:1639:1835)) + (INTERCONNECT SLICE_5I/Q0 SLICE_99I/A0 (1443:1639:1835)(1443:1639:1835)) + (INTERCONNECT SLICE_5I/Q0 SLICE_103I/C1 (1365:1556:1747)(1365:1556:1747)) + (INTERCONNECT SLICE_5I/Q0 SLICE_103I/C0 (1365:1556:1747)(1365:1556:1747)) + (INTERCONNECT SLICE_5I/Q0 SLICE_109I/C0 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5I/F1 SLICE_5I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/F0 SLICE_5I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6I/Q1 SLICE_96I/C1 (803:944:1086)(803:944:1086)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6I/Q0 SLICE_35I/A1 (1177:1341:1505)(1177:1341:1505)) + (INTERCONNECT SLICE_6I/F1 SLICE_6I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F0 SLICE_6I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_7I/Q1 SLICE_96I/D1 (526:578:630)(526:578:630)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_7I/Q0 SLICE_53I/C1 (871:1020:1170)(871:1020:1170)) + (INTERCONNECT SLICE_7I/F1 SLICE_7I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/F0 SLICE_7I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_8I/Q1 SLICE_53I/A1 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_8I/Q0 SLICE_35I/D1 (1223:1345:1467)(1223:1345:1467)) + (INTERCONNECT SLICE_8I/F1 SLICE_8I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F0 SLICE_8I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_9I/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_9I/Q1 SLICE_53I/B1 (1102:1264:1427)(1102:1264:1427)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_9I/Q0 SLICE_96I/A1 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 SLICE_10I/D1 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_94I/F0 SLICE_10I/C1 (911:1055:1200)(911:1055:1200)) + (INTERCONNECT SLICE_94I/F0 SLICE_90I/C0 (1275:1451:1627)(1275:1451:1627)) + (INTERCONNECT SLICE_91I/F0 SLICE_10I/B1 (777:908:1040)(777:908:1040)) + (INTERCONNECT SLICE_91I/F0 SLICE_90I/B1 (767:894:1021)(767:894:1021)) + (INTERCONNECT SLICE_91I/F0 SLICE_91I/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_104I/F0 SLICE_10I/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_10I/F1 SLICE_10I/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_10I/F1 SLICE_17I/B0 (775:903:1032)(775:903:1032)) + (INTERCONNECT SLICE_91I/F1 SLICE_10I/C0 (537:645:753)(537:645:753)) + (INTERCONNECT SLICE_91I/F1 SLICE_11I/A0 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_11I/F1 SLICE_10I/B0 (770:894:1018)(770:894:1018)) + (INTERCONNECT SLICE_11I/F1 SLICE_11I/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_11I/F1 SLICE_17I/M0 (490:537:585)(490:537:585)) + (INTERCONNECT SLICE_10I/Q0 SLICE_10I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_10I/Q0 SLICE_17I/D1 (860:954:1049)(860:954:1049)) + (INTERCONNECT SLICE_10I/F0 SLICE_10I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_10I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_11I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_17I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_23I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_24I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_25I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_46I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2I/PADDI PHI2_MGIOLI/DI (424:441:459)(424:441:459)) + (INTERCONNECT PHI2I/PADDI RA_11_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_7_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_6_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_5_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_4_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_3_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_2_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_1_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2I/PADDI Din_0_MGIOLI/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT SLICE_92I/F0 SLICE_11I/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_92I/F0 SLICE_90I/A1 (1081:1244:1407)(1081:1244:1407)) + (INTERCONNECT SLICE_92I/F0 SLICE_91I/A1 (1081:1244:1407)(1081:1244:1407)) + (INTERCONNECT SLICE_104I/F1 SLICE_11I/C1 (975:1126:1278)(975:1126:1278)) + (INTERCONNECT SLICE_90I/F0 SLICE_11I/B1 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_90I/F0 SLICE_24I/B1 (774:907:1040)(774:907:1040)) + (INTERCONNECT SLICE_90I/F0 SLICE_73I/D0 (532:597:662)(532:597:662)) + (INTERCONNECT SLICE_90I/F0 SLICE_90I/C1 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_90I/F0 SLICE_91I/B1 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_106I/F0 SLICE_11I/A1 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_11I/Q0 SLICE_11I/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_11I/Q0 SLICE_17I/C0 (1234:1411:1588)(1234:1411:1588)) + (INTERCONNECT SLICE_11I/F0 SLICE_11I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_12I/A0 (3665:4068:4471)(3665:4068:4471)) + (INTERCONNECT nCCASI/PADDI SLICE_26I/C1 (3200:3558:3916)(3200:3558:3916)) + (INTERCONNECT nCCASI/PADDI RD_0_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_7_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_6_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_5_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_4_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_3_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_2_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCASI/PADDI RD_1_MGIOLI/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT SLICE_12I/F0 SLICE_12I/DI0 (3:6:9)(3:6:9)) + (INTERCONNECT SLICE_12I/F0 SLICE_105I/M0 (499:545:592)(499:545:592)) + (INTERCONNECT SLICE_12I/F0 SLICE_105I/M1 (499:545:592)(499:545:592)) + (INTERCONNECT SLICE_12I/Q0 SLICE_12I/M1 (485:526:568)(485:526:568)) + (INTERCONNECT SLICE_12I/Q1 SLICE_88I/C0 (919:1066:1213)(919:1066:1213)) + (INTERCONNECT SLICE_12I/Q1 SLICE_98I/A1 (1445:1637:1830)(1445:1637:1830)) + (INTERCONNECT SLICE_12I/Q1 SLICE_106I/M0 (488:531:575)(488:531:575)) + (INTERCONNECT SLICE_12I/Q1 SLICE_117I/A0 (1482:1671:1860)(1482:1671:1860)) + (INTERCONNECT SLICE_16I/Q0 SLICE_16I/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_16I/Q0 SLICE_16I/D0 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_16I/Q0 SLICE_45I/C0 (813:959:1105)(813:959:1105)) + (INTERCONNECT SLICE_16I/Q0 SLICE_48I/A0 (743:876:1010)(743:876:1010)) + (INTERCONNECT SLICE_16I/Q0 SLICE_63I/C1 (559:677:795)(559:677:795)) + (INTERCONNECT SLICE_16I/Q0 SLICE_69I/A0 (743:876:1010)(743:876:1010)) + (INTERCONNECT SLICE_16I/Q0 SLICE_88I/D0 (537:600:664)(537:600:664)) + (INTERCONNECT SLICE_16I/Q0 SLICE_98I/B1 (1371:1565:1759)(1371:1565:1759)) + (INTERCONNECT SLICE_16I/Q0 SLICE_117I/C0 (544:667:790)(544:667:790)) + (INTERCONNECT SLICE_30I/Q0 SLICE_16I/C1 (550:665:780)(550:665:780)) + (INTERCONNECT SLICE_30I/Q0 SLICE_28I/B1 (1215:1382:1549)(1215:1382:1549)) + (INTERCONNECT SLICE_30I/Q0 SLICE_30I/D0 (973:1072:1171)(973:1072:1171)) + (INTERCONNECT SLICE_30I/Q0 SLICE_77I/C1 (550:665:780)(550:665:780)) + (INTERCONNECT SLICE_34I/Q1 SLICE_16I/B1 (1602:1805:2009)(1602:1805:2009)) + (INTERCONNECT SLICE_34I/Q1 SLICE_16I/LSR (1706:1880:2055)(1706:1880:2055)) + (INTERCONNECT SLICE_34I/Q1 SLICE_35I/M0 (1097:1211:1325)(1097:1211:1325)) + (INTERCONNECT SLICE_34I/Q1 SLICE_36I/C1 (1735:1957:2179)(1735:1957:2179)) + (INTERCONNECT SLICE_34I/Q1 SLICE_37I/D0 (1132:1257:1383)(1132:1257:1383)) + (INTERCONNECT SLICE_34I/Q1 SLICE_45I/A1 (1010:1164:1319)(1010:1164:1319)) + (INTERCONNECT SLICE_34I/Q1 SLICE_45I/LSR (1146:1274:1402)(1146:1274:1402)) + (INTERCONNECT SLICE_34I/Q1 SLICE_63I/A1 (1570:1771:1972)(1570:1771:1972)) + (INTERCONNECT SLICE_34I/Q1 SLICE_64I/C0 (991:1148:1306)(991:1148:1306)) + (INTERCONNECT SLICE_34I/Q1 SLICE_69I/A1 (1184:1351:1519)(1184:1351:1519)) + (INTERCONNECT SLICE_45I/Q0 SLICE_16I/A1 (1028:1196:1364)(1028:1196:1364)) + (INTERCONNECT SLICE_45I/Q0 SLICE_16I/A0 (1028:1196:1364)(1028:1196:1364)) + (INTERCONNECT SLICE_45I/Q0 SLICE_45I/D0 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_45I/Q0 SLICE_48I/D0 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_45I/Q0 SLICE_63I/D1 (818:920:1023)(818:920:1023)) + (INTERCONNECT SLICE_45I/Q0 SLICE_63I/D0 (818:920:1023)(818:920:1023)) + (INTERCONNECT SLICE_45I/Q0 SLICE_66I/D1 (531:597:663)(531:597:663)) + (INTERCONNECT SLICE_45I/Q0 SLICE_66I/D0 (531:597:663)(531:597:663)) + (INTERCONNECT SLICE_45I/Q0 SLICE_69I/B0 (770:892:1014)(770:892:1014)) + (INTERCONNECT SLICE_45I/Q0 SLICE_98I/D1 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_45I/Q0 SLICE_117I/D1 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_45I/Q0 SLICE_117I/D0 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_16I/F0 SLICE_16I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F1 SLICE_38I/B0 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_16I/F1 SLICE_39I/B1 (775:903:1032)(775:903:1032)) + (INTERCONNECT SLICE_17I/Q0 SLICE_17I/B1 (767:892:1017)(767:892:1017)) + (INTERCONNECT SLICE_17I/Q0 SLICE_17I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_17I/Q0 SLICE_24I/C1 (541:656:771)(541:656:771)) + (INTERCONNECT SLICE_17I/Q0 SLICE_73I/A0 (740:865:991)(740:865:991)) + (INTERCONNECT SLICE_90I/F1 SLICE_17I/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_17I/OFX0 SLICE_17I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_18I/D1 (532:597:662)(532:597:662)) + (INTERCONNECT SLICE_23I/F1 SLICE_20I/B0 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_23I/F1 SLICE_21I/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23I/F1 SLICE_22I/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23I/F1 SLICE_23I/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23I/F1 SLICE_24I/A0 (483:582:681)(483:582:681)) + (INTERCONNECT SLICE_23I/F1 SLICE_25I/D1 (532:597:662)(532:597:662)) + (INTERCONNECT Din_1_I/PADDI SLICE_18I/C1 (1536:1702:1869)(1536:1702:1869)) + (INTERCONNECT Din_1_I/PADDI SLICE_20I/C0 (1916:2115:2315)(1916:2115:2315)) + (INTERCONNECT Din_1_I/PADDI SLICE_21I/D0 (1905:2049:2194)(1905:2049:2194)) + (INTERCONNECT Din_1_I/PADDI SLICE_22I/A1 (2115:2325:2535)(2115:2325:2535)) + (INTERCONNECT Din_1_I/PADDI SLICE_46I/C1 (2656:2919:3183)(2656:2919:3183)) + (INTERCONNECT Din_1_I/PADDI SLICE_104I/C1 (3353:3683:4014)(3353:3683:4014)) + (INTERCONNECT Din_1_I/PADDI SLICE_104I/A0 (3225:3531:3837)(3225:3531:3837)) + (INTERCONNECT Din_1_I/PADDI RD_1_MGIOLI/OPOS (3120:3370:3621)(3120:3370:3621)) + (INTERCONNECT Din_1_I/PADDI Din_1_MGIOLI/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_18I/Q0 SLICE_18I/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_18I/Q0 SLICE_32I/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_18I/F1 SLICE_18I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_73I/F1 SLICE_18I/B0 (1044:1206:1368)(1044:1206:1368)) + (INTERCONNECT SLICE_73I/F1 SLICE_20I/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73I/F1 SLICE_21I/C0 (881:1038:1195)(881:1038:1195)) + (INTERCONNECT SLICE_73I/F1 SLICE_22I/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73I/F1 SLICE_23I/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73I/F1 SLICE_24I/D0 (273:306:340)(273:306:340)) + (INTERCONNECT SLICE_73I/F1 SLICE_25I/D0 (1129:1258:1387)(1129:1258:1387)) + (INTERCONNECT SLICE_73I/F1 SLICE_73I/B0 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_32I/Q0 SLICE_18I/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_32I/Q0 SLICE_34I/C1 (809:951:1093)(809:951:1093)) + (INTERCONNECT SLICE_32I/Q0 SLICE_46I/A1 (1008:1160:1313)(1008:1160:1313)) + (INTERCONNECT SLICE_18I/F0 SLICE_18I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_18I/CE (945:1046:1148)(945:1046:1148)) + (INTERCONNECT SLICE_24I/F1 SLICE_20I/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24I/F1 SLICE_21I/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24I/F1 SLICE_22I/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24I/F1 SLICE_23I/C0 (567:687:808)(567:687:808)) + (INTERCONNECT SLICE_24I/F1 SLICE_24I/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_24I/F1 SLICE_25I/CE (945:1046:1148)(945:1046:1148)) + (INTERCONNECT SLICE_24I/F1 SLICE_46I/CE (544:607:670)(544:607:670)) + (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_20I/Q0 wb_cyc_stb_RNO_SLICE_61I/B1 (770:892:1014) + (770:892:1014)) + (INTERCONNECT SLICE_20I/Q0 SLICE_95I/C0 (539:648:757)(539:648:757)) + (INTERCONNECT SLICE_20I/F0 SLICE_20I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_21I/Q0 SLICE_21I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_21I/Q0 SLICE_97I/B0 (775:902:1030)(775:902:1030)) + (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_22I/C1 (2041:2255:2470)(2041:2255:2470)) + (INTERCONNECT Din_0_I/PADDI SLICE_25I/C1 (1590:1776:1963)(1590:1776:1963)) + (INTERCONNECT Din_0_I/PADDI SLICE_46I/B1 (2653:2913:3174)(2653:2913:3174)) + (INTERCONNECT Din_0_I/PADDI SLICE_73I/M0 (2703:2919:3135)(2703:2919:3135)) + (INTERCONNECT Din_0_I/PADDI SLICE_104I/D1 (3164:3436:3708)(3164:3436:3708)) + (INTERCONNECT Din_0_I/PADDI SLICE_104I/C0 (2848:3140:3432)(2848:3140:3432)) + (INTERCONNECT Din_0_I/PADDI RD_0_MGIOLI/OPOS (2849:3087:3325)(2849:3087:3325)) + (INTERCONNECT Din_0_I/PADDI Din_0_MGIOLI/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_22I/F1 SLICE_22I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_22I/Q0 wb_cyc_stb_RNO_SLICE_61I/C1 (544:658:773)(544:658:773)) + (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_23I/D1 (1994:2141:2289)(1994:2141:2289)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/C1 (2349:2589:2829)(2349:2589:2829)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/C0 (2349:2589:2829)(2349:2589:2829)) + (INTERCONNECT Din_4_I/PADDI SLICE_106I/A0 (2950:3227:3505)(2950:3227:3505)) + (INTERCONNECT Din_4_I/PADDI SLICE_116I/B0 (2612:2860:3108)(2612:2860:3108)) + (INTERCONNECT Din_4_I/PADDI RD_4_MGIOLI/OPOS (4276:4628:4981)(4276:4628:4981)) + (INTERCONNECT Din_4_I/PADDI Din_4_MGIOLI/DI (544:554:565)(544:554:565)) + (INTERCONNECT Din_7_I/PADDI SLICE_23I/C1 (2329:2578:2828)(2329:2578:2828)) + (INTERCONNECT Din_7_I/PADDI SLICE_73I/D1 (2645:2874:3104)(2645:2874:3104)) + (INTERCONNECT Din_7_I/PADDI SLICE_101I/D1 (3020:3283:3546)(3020:3283:3546)) + (INTERCONNECT Din_7_I/PADDI SLICE_101I/D0 (3020:3283:3546)(3020:3283:3546)) + (INTERCONNECT Din_7_I/PADDI SLICE_106I/C0 (2699:2980:3262)(2699:2980:3262)) + (INTERCONNECT Din_7_I/PADDI RD_7_MGIOLI/OPOS (3911:4259:4607)(3911:4259:4607)) + (INTERCONNECT Din_7_I/PADDI Din_7_MGIOLI/DI (424:441:459)(424:441:459)) + (INTERCONNECT Din_5_I/PADDI SLICE_23I/B1 (1882:2067:2252)(1882:2067:2252)) + (INTERCONNECT Din_5_I/PADDI SLICE_73I/A1 (2214:2428:2642)(2214:2428:2642)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/A1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/A0 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din_5_I/PADDI SLICE_104I/A1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din_5_I/PADDI RD_5_MGIOLI/OPOS (2982:3212:3442)(2982:3212:3442)) + (INTERCONNECT Din_5_I/PADDI Din_5_MGIOLI/DI (544:554:565)(544:554:565)) + (INTERCONNECT Din_6_I/PADDI SLICE_23I/A1 (2235:2458:2682)(2235:2458:2682)) + (INTERCONNECT Din_6_I/PADDI SLICE_101I/B0 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din_6_I/PADDI SLICE_104I/B1 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din_6_I/PADDI SLICE_104I/B0 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din_6_I/PADDI SLICE_116I/D1 (3641:3936:4231)(3641:3936:4231)) + (INTERCONNECT Din_6_I/PADDI SLICE_116I/A0 (3072:3357:3642)(3072:3357:3642)) + (INTERCONNECT Din_6_I/PADDI RD_6_MGIOLI/OPOS (3403:3658:3913)(3403:3658:3913)) + (INTERCONNECT Din_6_I/PADDI Din_6_MGIOLI/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_23I/F0 SLICE_23I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/Q0 SLICE_59I/B1 (1110:1271:1433)(1110:1271:1433)) + (INTERCONNECT SLICE_23I/Q0 wb_cyc_stb_RNO_SLICE_61I/D1 (541:599:658)(541:599:658)) + (INTERCONNECT SLICE_23I/Q0 SLICE_95I/D0 (541:599:658)(541:599:658)) + (INTERCONNECT SLICE_105I/F0 SLICE_24I/A1 (751:875:999)(751:875:999)) + (INTERCONNECT SLICE_105I/F0 SLICE_73I/C0 (879:1027:1176)(879:1027:1176)) + (INTERCONNECT SLICE_105I/F0 SLICE_90I/D1 (868:961:1055)(868:961:1055)) + (INTERCONNECT SLICE_24I/F0 SLICE_24I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/Q0 SLICE_62I/B1 (1105:1266:1427)(1105:1266:1427)) + (INTERCONNECT SLICE_24I/Q0 SLICE_97I/D0 (1227:1351:1476)(1227:1351:1476)) + (INTERCONNECT SLICE_25I/Q0 SLICE_25I/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_25I/Q0 SLICE_47I/A0 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_47I/Q0 SLICE_25I/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_47I/Q0 SLICE_116I/C1 (1233:1414:1595)(1233:1414:1595)) + (INTERCONNECT SLICE_25I/F1 SLICE_25I/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_26I/D1 (2286:2472:2659)(2286:2472:2659)) + (INTERCONNECT nFWEI/PADDI SLICE_26I/C0 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT nFWEI/PADDI SLICE_92I/D0 (1851:2013:2175)(1851:2013:2175)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/D1 (1851:2013:2175)(1851:2013:2175)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/B0 (2082:2310:2538)(2082:2310:2538)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (3:6:9)(3:6:9)) + (INTERCONNECT SLICE_26I/F0 SLICE_108I/M0 (1515:1661:1808)(1515:1661:1808)) + (INTERCONNECT nCRASI/PADDI SLICE_26I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_34I/D1 (3175:3429:3683)(3175:3429:3683)) + (INTERCONNECT nCRASI/PADDI SLICE_34I/D0 (3175:3429:3683)(3175:3429:3683)) + (INTERCONNECT nCRASI/PADDI SLICE_40I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_40I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_41I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_41I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_42I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_42I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_43I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_43I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_44I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_44I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_105I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_105I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI SLICE_108I/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRASI/PADDI RBA_1_MGIOLI/CLK (3072:3306:3541)(3072:3306:3541)) + (INTERCONNECT nCRASI/PADDI RBA_0_MGIOLI/CLK (3072:3306:3541)(3072:3306:3541)) + (INTERCONNECT SLICE_26I/Q0 SLICE_48I/C1 (984:1138:1292)(984:1138:1292)) + (INTERCONNECT SLICE_26I/Q0 SLICE_98I/D0 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_26I/Q0 SLICE_117I/B0 (1215:1382:1549)(1215:1382:1549)) + (INTERCONNECT SLICE_26I/F1 RD_0_I/PADDT (950:1056:1162)(950:1056:1162)) + (INTERCONNECT SLICE_26I/F1 RD_7_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26I/F1 RD_6_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26I/F1 RD_5_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26I/F1 RD_4_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26I/F1 RD_3_I/PADDT (675:751:828)(675:751:828)) + (INTERCONNECT SLICE_26I/F1 RD_2_I/PADDT (675:751:828)(675:751:828)) + (INTERCONNECT SLICE_26I/F1 RD_1_I0/PADDT (950:1056:1162)(950:1056:1162)) + (INTERCONNECT SLICE_28I/Q0 SLICE_28I/D1 (538:599:660)(538:599:660)) + (INTERCONNECT SLICE_28I/Q0 SLICE_28I/D0 (538:599:660)(538:599:660)) + (INTERCONNECT SLICE_28I/Q0 SLICE_29I/C1 (543:660:777)(543:660:777)) + (INTERCONNECT SLICE_28I/Q0 SLICE_29I/C0 (543:660:777)(543:660:777)) + (INTERCONNECT SLICE_28I/Q0 SLICE_30I/C0 (886:1040:1195)(886:1040:1195)) + (INTERCONNECT SLICE_28I/Q0 SLICE_38I/C1 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_28I/Q0 SLICE_68I/B0 (1524:1720:1916)(1524:1720:1916)) + (INTERCONNECT SLICE_28I/Q0 SLICE_77I/A0 (1492:1685:1879)(1492:1685:1879)) + (INTERCONNECT SLICE_28I/Q0 SLICE_108I/B1 (772:896:1020)(772:896:1020)) + (INTERCONNECT SLICE_38I/Q0 SLICE_28I/C1 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_38I/Q0 SLICE_28I/C0 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_38I/Q0 SLICE_36I/D1 (906:1009:1113)(906:1009:1113)) + (INTERCONNECT SLICE_38I/Q0 SLICE_36I/A0 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38I/Q0 SLICE_38I/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_38I/Q0 SLICE_39I/A1 (737:861:986)(737:861:986)) + (INTERCONNECT SLICE_38I/Q0 SLICE_45I/B1 (1174:1340:1506)(1174:1340:1506)) + (INTERCONNECT SLICE_38I/Q0 SLICE_48I/A1 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38I/Q0 SLICE_48I/C0 (906:1062:1219)(906:1062:1219)) + (INTERCONNECT SLICE_38I/Q0 SLICE_63I/A0 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38I/Q0 SLICE_64I/D1 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_38I/Q0 SLICE_64I/D0 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_38I/Q0 SLICE_68I/A1 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38I/Q0 SLICE_69I/D0 (906:1009:1113)(906:1009:1113)) + (INTERCONNECT SLICE_38I/Q0 SLICE_88I/A1 (1128:1290:1452)(1128:1290:1452)) + (INTERCONNECT SLICE_38I/Q0 SLICE_108I/D0 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_63I/F1 SLICE_28I/A1 (1014:1176:1339)(1014:1176:1339)) + (INTERCONNECT SLICE_63I/F1 SLICE_28I/A0 (1014:1176:1339)(1014:1176:1339)) + (INTERCONNECT SLICE_63I/F1 SLICE_63I/C0 (286:377:469)(286:377:469)) + (INTERCONNECT SLICE_63I/F1 SLICE_68I/A0 (485:587:689)(485:587:689)) + (INTERCONNECT SLICE_63I/F1 SLICE_77I/C0 (540:660:780)(540:660:780)) + (INTERCONNECT SLICE_63I/F1 SLICE_108I/D1 (872:977:1082)(872:977:1082)) + (INTERCONNECT SLICE_63I/F1 SLICE_108I/C0 (556:681:806)(556:681:806)) + (INTERCONNECT SLICE_28I/F0 SLICE_28I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28I/F1 RA_10_MGIOLI/LSR (1427:1573:1720)(1427:1573:1720)) + (INTERCONNECT SLICE_29I/Q0 SLICE_29I/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29I/Q0 SLICE_30I/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_29I/Q0 SLICE_38I/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29I/Q0 SLICE_68I/C0 (881:1035:1189)(881:1035:1189)) + (INTERCONNECT SLICE_29I/Q0 SLICE_77I/D1 (543:607:671)(543:607:671)) + (INTERCONNECT SLICE_29I/Q1 SLICE_29I/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_29I/Q1 SLICE_30I/A1 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29I/Q1 SLICE_30I/A0 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29I/Q1 SLICE_38I/A1 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29I/Q1 SLICE_68I/D0 (530:590:650)(530:590:650)) + (INTERCONNECT SLICE_29I/Q1 SLICE_77I/B1 (772:900:1028)(772:900:1028)) + (INTERCONNECT SLICE_29I/F1 SLICE_29I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108I/F0 SLICE_29I/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_108I/F0 SLICE_29I/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_108I/F0 SLICE_30I/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F1 RA_10_MGIOLI/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT SLICE_71I/F1 SLICE_31I/D1 (794:887:981)(794:887:981)) + (INTERCONNECT SLICE_71I/F1 SLICE_71I/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_71I/F1 SLICE_110I/C0 (539:653:767)(539:653:767)) + (INTERCONNECT SLICE_102I/F1 SLICE_31I/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_31I/F1 SLICE_31I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (489:591:693)(489:591:693)) + (INTERCONNECT SLICE_31I/Q0 SLICE_32I/D0 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31I/Q0 SLICE_36I/B1 (1481:1681:1882)(1481:1681:1882)) + (INTERCONNECT SLICE_31I/Q0 SLICE_38I/D0 (1609:1773:1938)(1609:1773:1938)) + (INTERCONNECT SLICE_31I/Q0 SLICE_39I/D1 (1609:1773:1938)(1609:1773:1938)) + (INTERCONNECT SLICE_31I/Q0 SLICE_47I/D1 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31I/Q0 SLICE_47I/D0 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31I/Q0 SLICE_49I/B1 (1591:1799:2007)(1591:1799:2007)) + (INTERCONNECT SLICE_31I/Q0 SLICE_49I/B0 (1591:1799:2007)(1591:1799:2007)) + (INTERCONNECT SLICE_31I/Q0 SLICE_50I/A1 (1559:1764:1970)(1559:1764:1970)) + (INTERCONNECT SLICE_31I/Q0 SLICE_50I/A0 (1559:1764:1970)(1559:1764:1970)) + (INTERCONNECT SLICE_31I/Q0 SLICE_51I/C1 (1360:1555:1750)(1360:1555:1750)) + (INTERCONNECT SLICE_31I/Q0 SLICE_51I/C0 (1360:1555:1750)(1360:1555:1750)) + (INTERCONNECT SLICE_31I/Q0 SLICE_52I/D1 (1349:1489:1629)(1349:1489:1629)) + (INTERCONNECT SLICE_31I/Q0 SLICE_52I/D0 (1349:1489:1629)(1349:1489:1629)) + (INTERCONNECT SLICE_31I/Q0 SLICE_54I/B0 (816:956:1097)(816:956:1097)) + (INTERCONNECT SLICE_31I/Q0 SLICE_55I/A0 (1159:1329:1500)(1159:1329:1500)) + (INTERCONNECT SLICE_31I/Q0 SLICE_56I/C1 (960:1120:1280)(960:1120:1280)) + (INTERCONNECT SLICE_31I/Q0 SLICE_56I/C0 (960:1120:1280)(960:1120:1280)) + (INTERCONNECT SLICE_31I/Q0 SLICE_59I/C1 (555:677:799)(555:677:799)) + (INTERCONNECT SLICE_31I/Q0 SLICE_60I/B0 (816:956:1097)(816:956:1097)) + (INTERCONNECT SLICE_31I/Q0 wb_cyc_stb_RNO_SLICE_61I/M0 (866:965:1064) + (866:965:1064)) + (INTERCONNECT SLICE_31I/Q0 SLICE_62I/A1 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31I/Q0 SLICE_62I/A0 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31I/Q0 SLICE_63I/B1 (1546:1757:1969)(1546:1757:1969)) + (INTERCONNECT SLICE_31I/Q0 SLICE_74I/B0 (1555:1759:1964)(1555:1759:1964)) + (INTERCONNECT SLICE_31I/Q0 SLICE_75I/A0 (784:922:1060)(784:922:1060)) + (INTERCONNECT SLICE_31I/Q0 SLICE_76I/D1 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31I/Q0 SLICE_79I/D0 (574:646:719)(574:646:719)) + (INTERCONNECT SLICE_31I/Q0 SLICE_81I/D0 (949:1054:1159)(949:1054:1159)) + (INTERCONNECT SLICE_31I/Q0 SLICE_89I/D0 (536:598:660)(536:598:660)) + (INTERCONNECT SLICE_31I/Q0 SLICE_95I/A0 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31I/Q0 SLICE_97I/C0 (555:677:799)(555:677:799)) + (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb_EFBInst_0I/WBDATO1 SLICE_32I/A0 (1806:2010:2215) + (1806:2010:2215)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_32I/CE (1138:1264:1391)(1138:1264:1391)) + (INTERCONNECT SLICE_62I/F1 SLICE_47I/CE (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_105I/Q0 SLICE_34I/A1 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_105I/Q0 SLICE_36I/D0 (866:961:1056)(866:961:1056)) + (INTERCONNECT SLICE_105I/Q0 SLICE_48I/B1 (1108:1271:1434)(1108:1271:1434)) + (INTERCONNECT SLICE_105I/Q0 SLICE_66I/A1 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_34I/F0 SLICE_34I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/Q0 SLICE_34I/M1 (488:531:575)(488:531:575)) + (INTERCONNECT SLICE_34I/Q0 SLICE_37I/B0 (775:902:1030)(775:902:1030)) + (INTERCONNECT SLICE_34I/F1 LEDI/PADDO (936:1038:1140)(936:1038:1140)) + (INTERCONNECT SLICE_42I/Q0 SLICE_35I/D0 (530:587:645)(530:587:645)) + (INTERCONNECT MAin_4_I/PADDI SLICE_35I/C0 (1975:2181:2387)(1975:2181:2387)) + (INTERCONNECT MAin_4_I/PADDI SLICE_42I/C0 (2339:2576:2814)(2339:2576:2814)) + (INTERCONNECT MAin_4_I/PADDI SLICE_92I/D1 (2692:2906:3120)(2692:2906:3120)) + (INTERCONNECT MAin_4_I/PADDI SLICE_111I/D0 (2291:2477:2663)(2291:2477:2663)) + (INTERCONNECT SLICE_48I/Q0 SLICE_35I/A0 (1183:1347:1512)(1183:1347:1512)) + (INTERCONNECT SLICE_48I/Q0 SLICE_107I/C1 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48I/Q0 SLICE_107I/C0 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48I/Q0 SLICE_111I/B1 (1590:1789:1989)(1590:1789:1989)) + (INTERCONNECT SLICE_48I/Q0 SLICE_112I/C1 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48I/Q0 SLICE_112I/D0 (1315:1450:1586)(1315:1450:1586)) + (INTERCONNECT SLICE_48I/Q0 SLICE_113I/A1 (1568:1766:1964)(1568:1766:1964)) + (INTERCONNECT SLICE_48I/Q0 SLICE_113I/A0 (1568:1766:1964)(1568:1766:1964)) + (INTERCONNECT SLICE_48I/Q0 SLICE_114I/A1 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT SLICE_48I/Q0 SLICE_114I/A0 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT SLICE_48I/Q0 SLICE_115I/B1 (1590:1789:1989)(1590:1789:1989)) + (INTERCONNECT SLICE_48I/Q0 SLICE_115I/A0 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT PHI2_MGIOLI/INP SLICE_35I/M1 (1442:1578:1714)(1442:1578:1714)) + (INTERCONNECT SLICE_35I/F0 RA_4_I/PADDO (1552:1738:1924)(1552:1738:1924)) + (INTERCONNECT SLICE_35I/Q0 SLICE_37I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_35I/F1 SLICE_53I/D1 (1220:1340:1460)(1220:1340:1460)) + (INTERCONNECT SLICE_35I/Q1 SLICE_59I/A1 (1188:1353:1518)(1188:1353:1518)) + (INTERCONNECT SLICE_35I/Q1 SLICE_95I/A1 (1552:1748:1945)(1552:1748:1945)) + (INTERCONNECT SLICE_35I/Q1 SLICE_97I/C1 (989:1143:1298)(989:1143:1298)) + (INTERCONNECT SLICE_35I/Q1 SLICE_118I/M0 (825:908:991)(825:908:991)) + (INTERCONNECT SLICE_45I/F0 SLICE_36I/A1 (740:864:989)(740:864:989)) + (INTERCONNECT SLICE_45I/F0 SLICE_45I/C1 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_45I/F0 SLICE_45I/DI0 (7:16:25)(7:16:25)) + (INTERCONNECT SLICE_45I/F0 SLICE_64I/A0 (483:582:681)(483:582:681)) + (INTERCONNECT SLICE_117I/F0 SLICE_36I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_36I/F1 SLICE_36I/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_37I/C0 (975:1126:1278)(975:1126:1278)) + (INTERCONNECT Din_7_MGIOLI/INP SLICE_37I/D1 (1406:1542:1678)(1406:1542:1678)) + (INTERCONNECT Din_2_MGIOLI/INP SLICE_37I/C1 (1161:1328:1496)(1161:1328:1496)) + (INTERCONNECT Din_5_MGIOLI/INP SLICE_37I/B1 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT Din_6_MGIOLI/INP SLICE_37I/A1 (1687:1900:2113)(1687:1900:2113)) + (INTERCONNECT SLICE_37I/F0 SLICE_37I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_45I/D1 (975:1073:1172)(975:1073:1172)) + (INTERCONNECT SLICE_37I/Q0 SLICE_69I/D1 (975:1073:1172)(975:1073:1172)) + (INTERCONNECT SLICE_37I/Q0 RCKEI/PADDO (1905:2099:2293)(1905:2099:2293)) + (INTERCONNECT SLICE_37I/F1 SLICE_94I/B0 (1031:1183:1336)(1031:1183:1336)) + (INTERCONNECT SLICE_38I/F1 SLICE_38I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_38I/F1 SLICE_39I/C1 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_38I/F0 SLICE_38I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_39I/F1 SLICE_39I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_39I/Q0 SLICE_39I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_39I/Q0 SLICE_40I/B1 (774:914:1054)(774:914:1054)) + (INTERCONNECT SLICE_39I/Q0 SLICE_40I/B0 (774:914:1054)(774:914:1054)) + (INTERCONNECT SLICE_39I/Q0 SLICE_41I/D1 (995:1099:1203)(995:1099:1203)) + (INTERCONNECT SLICE_39I/Q0 SLICE_41I/D0 (995:1099:1203)(995:1099:1203)) + (INTERCONNECT SLICE_39I/Q0 SLICE_42I/A1 (1205:1374:1544)(1205:1374:1544)) + (INTERCONNECT SLICE_39I/Q0 SLICE_42I/A0 (1205:1374:1544)(1205:1374:1544)) + (INTERCONNECT SLICE_39I/Q0 SLICE_43I/B1 (1607:1811:2015)(1607:1811:2015)) + (INTERCONNECT SLICE_39I/Q0 SLICE_43I/B0 (1607:1811:2015)(1607:1811:2015)) + (INTERCONNECT SLICE_39I/Q0 SLICE_44I/D1 (532:604:676)(532:604:676)) + (INTERCONNECT SLICE_39I/Q0 SLICE_44I/D0 (532:604:676)(532:604:676)) + (INTERCONNECT SLICE_39I/Q0 SLICE_116I/B1 (1222:1392:1563)(1222:1392:1563)) + (INTERCONNECT SLICE_39I/Q0 SLICE_118I/C1 (1361:1550:1740)(1361:1550:1740)) + (INTERCONNECT SLICE_39I/Q0 SLICE_118I/C0 (1361:1550:1740)(1361:1550:1740)) + (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_40I/C1 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/C0 (1524:1704:1884)(1524:1704:1884)) + (INTERCONNECT MAin_1_I/PADDI SLICE_92I/A0 (2093:2315:2538)(2093:2315:2538)) + (INTERCONNECT MAin_1_I/PADDI SLICE_105I/D0 (2210:2402:2594)(2210:2402:2594)) + (INTERCONNECT MAin_1_I/PADDI SLICE_113I/C0 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT MAin_0_I/PADDI SLICE_40I/C0 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT MAin_0_I/PADDI SLICE_92I/B0 (2652:2898:3145)(2652:2898:3145)) + (INTERCONNECT MAin_0_I/PADDI SLICE_105I/A1 (2620:2864:3108)(2620:2864:3108)) + (INTERCONNECT MAin_0_I/PADDI SLICE_105I/A0 (2620:2864:3108)(2620:2864:3108)) + (INTERCONNECT MAin_0_I/PADDI SLICE_112I/C0 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT SLICE_40I/F1 SLICE_40I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_40I/F0 SLICE_40I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_40I/Q0 SLICE_112I/B0 (1099:1259:1420)(1099:1259:1420)) + (INTERCONNECT SLICE_40I/Q1 SLICE_113I/D0 (520:573:626)(520:573:626)) + (INTERCONNECT MAin_3_I/PADDI SLICE_41I/B1 (2206:2426:2646)(2206:2426:2646)) + (INTERCONNECT MAin_3_I/PADDI SLICE_91I/D0 (2198:2389:2580)(2198:2389:2580)) + (INTERCONNECT MAin_3_I/PADDI SLICE_92I/C1 (2339:2577:2816)(2339:2577:2816)) + (INTERCONNECT MAin_3_I/PADDI SLICE_115I/B0 (2206:2426:2646)(2206:2426:2646)) + (INTERCONNECT MAin_2_I/PADDI SLICE_41I/C0 (1975:2182:2389)(1975:2182:2389)) + (INTERCONNECT MAin_2_I/PADDI SLICE_92I/B1 (1749:1941:2134)(1749:1941:2134)) + (INTERCONNECT MAin_2_I/PADDI SLICE_111I/C0 (1975:2182:2389)(1975:2182:2389)) + (INTERCONNECT MAin_2_I/PADDI SLICE_114I/C0 (1975:2182:2389)(1975:2182:2389)) + (INTERCONNECT SLICE_41I/F1 SLICE_41I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_41I/Q0 SLICE_114I/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_41I/Q1 SLICE_115I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT MAin_5_I/PADDI SLICE_42I/D1 (1878:2033:2189)(1878:2033:2189)) + (INTERCONNECT MAin_5_I/PADDI SLICE_90I/B0 (2120:2343:2567)(2120:2343:2567)) + (INTERCONNECT MAin_5_I/PADDI SLICE_111I/B0 (2120:2343:2567)(2120:2343:2567)) + (INTERCONNECT MAin_5_I/PADDI SLICE_115I/A1 (2088:2309:2530)(2088:2309:2530)) + (INTERCONNECT SLICE_42I/F1 SLICE_42I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42I/Q1 SLICE_115I/D1 (520:573:626)(520:573:626)) + (INTERCONNECT MAin_7_I/PADDI SLICE_43I/C1 (1888:2098:2309)(1888:2098:2309)) + (INTERCONNECT MAin_7_I/PADDI SLICE_90I/A0 (3179:3494:3810)(3179:3494:3810)) + (INTERCONNECT MAin_7_I/PADDI SLICE_111I/A1 (2425:2683:2941)(2425:2683:2941)) + (INTERCONNECT MAin_7_I/PADDI SLICE_111I/A0 (2425:2683:2941)(2425:2683:2941)) + (INTERCONNECT MAin_6_I/PADDI SLICE_43I/C0 (1970:2175:2381)(1970:2175:2381)) + (INTERCONNECT MAin_6_I/PADDI SLICE_90I/D0 (3020:3269:3518)(3020:3269:3518)) + (INTERCONNECT MAin_6_I/PADDI SLICE_105I/C1 (2667:2939:3212)(2667:2939:3212)) + (INTERCONNECT MAin_6_I/PADDI SLICE_114I/C1 (1970:2175:2381)(1970:2175:2381)) + (INTERCONNECT SLICE_43I/F1 SLICE_43I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/Q0 SLICE_114I/D1 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_43I/Q1 SLICE_111I/C1 (531:639:747)(531:639:747)) + (INTERCONNECT MAin_9_I/PADDI SLICE_44I/B1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT MAin_9_I/PADDI SLICE_107I/B1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT MAin_9_I/PADDI SLICE_107I/B0 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT MAin_9_I/PADDI SLICE_112I/B1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT MAin_8_I/PADDI SLICE_44I/A0 (2420:2659:2898)(2420:2659:2898)) + (INTERCONNECT MAin_8_I/PADDI SLICE_113I/C1 (2221:2449:2678)(2221:2449:2678)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 SLICE_113I/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_44I/Q1 SLICE_107I/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_45I/F1 SLICE_77I/D0 (791:881:972)(791:881:972)) + (INTERCONNECT SLICE_45I/F1 SLICE_108I/C1 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_106I/F1 SLICE_46I/D1 (530:587:645)(530:587:645)) + (INTERCONNECT SLICE_46I/F1 SLICE_46I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_101I/F0 SLICE_46I/B0 (1206:1370:1535)(1206:1370:1535)) + (INTERCONNECT SLICE_46I/Q0 SLICE_46I/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_46I/Q0 SLICE_116I/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_46I/F0 SLICE_46I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb_EFBInst_0I/WBDATO0 SLICE_47I/C0 (1161:1328:1496) + (1161:1328:1496)) + (INTERCONNECT SLICE_47I/F0 SLICE_47I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_47I/F1 SLICE_53I/LSR (1319:1458:1597)(1319:1458:1597)) + (INTERCONNECT SLICE_47I/F1 SLICE_58I/LSR (1330:1471:1612)(1330:1471:1612)) + (INTERCONNECT SLICE_47I/F1 SLICE_59I/D0 (1311:1448:1585)(1311:1448:1585)) + (INTERCONNECT SLICE_47I/F1 SLICE_60I/LSR (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_106I/Q0 SLICE_48I/D1 (528:586:644)(528:586:644)) + (INTERCONNECT SLICE_106I/Q0 SLICE_88I/B0 (1139:1298:1457)(1139:1298:1457)) + (INTERCONNECT SLICE_106I/Q0 SLICE_98I/C1 (1236:1419:1602)(1236:1419:1602)) + (INTERCONNECT SLICE_48I/F1 SLICE_48I/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_48I/F0 SLICE_48I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_48I/LSR (542:602:662)(542:602:662)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_76I/F1 SLICE_49I/D1 (1324:1453:1583)(1324:1453:1583)) + (INTERCONNECT SLICE_76I/F1 SLICE_51I/D1 (1324:1453:1583)(1324:1453:1583)) + (INTERCONNECT SLICE_76I/F1 SLICE_51I/D0 (1324:1453:1583)(1324:1453:1583)) + (INTERCONNECT SLICE_76I/F1 SLICE_52I/C0 (1662:1881:2101)(1662:1881:2101)) + (INTERCONNECT SLICE_76I/F1 SLICE_53I/D0 (1334:1472:1610)(1334:1472:1610)) + (INTERCONNECT SLICE_76I/F1 SLICE_55I/D1 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_76I/F1 SLICE_58I/D0 (1334:1472:1610)(1334:1472:1610)) + (INTERCONNECT SLICE_76I/F1 SLICE_67I/D1 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_76I/F1 SLICE_67I/D0 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_76I/F1 SLICE_72I/D1 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_76I/F1 SLICE_75I/A1 (1472:1669:1866)(1472:1669:1866)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_76I/F1 SLICE_79I/A1 (1472:1669:1866)(1472:1669:1866)) + (INTERCONNECT SLICE_76I/F1 SLICE_81I/A1 (1461:1656:1851)(1461:1656:1851)) + (INTERCONNECT SLICE_76I/F1 SLICE_85I/B1 (791:921:1051)(791:921:1051)) + (INTERCONNECT SLICE_76I/F1 SLICE_93I/C1 (1299:1480:1661)(1299:1480:1661)) + (INTERCONNECT SLICE_76I/F1 SLICE_109I/D1 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_76I/F1 SLICE_109I/D0 (944:1040:1137)(944:1040:1137)) + (INTERCONNECT SLICE_49I/Q0 SLICE_49I/C1 (534:644:754)(534:644:754)) + (INTERCONNECT SLICE_49I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI0in (1378:1511:1645) + (1378:1511:1645)) + (INTERCONNECT SLICE_84I/F0 SLICE_49I/A1 (1431:1620:1810)(1431:1620:1810)) + (INTERCONNECT SLICE_85I/F1 SLICE_49I/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_57I/Q1 SLICE_49I/A0 (1002:1154:1306)(1002:1154:1306)) + (INTERCONNECT SLICE_57I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI7in (909:1006:1104) + (909:1006:1104)) + (INTERCONNECT SLICE_49I/F1 SLICE_49I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F0 SLICE_49I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_49I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_49I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_50I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_50I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_51I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_51I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_52I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_52I/CE (1577:1735:1893)(1577:1735:1893)) + (INTERCONNECT SLICE_97I/F0 SLICE_54I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_54I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_55I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_55I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_56I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_56I/CE (827:920:1013)(827:920:1013)) + (INTERCONNECT SLICE_97I/F0 SLICE_57I/CE (1197:1322:1447)(1197:1322:1447)) + (INTERCONNECT SLICE_97I/F0 SLICE_57I/CE (1197:1322:1447)(1197:1322:1447)) + (INTERCONNECT SLICE_97I/F0 SLICE_60I/CE (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_49I/Q1 SLICE_50I/C0 (534:644:754)(534:644:754)) + (INTERCONNECT SLICE_49I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI1in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_50I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI2in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_50I/F1 SLICE_50I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/Q1 SLICE_51I/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_50I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI3in (909:1006:1104) + (909:1006:1104)) + (INTERCONNECT SLICE_51I/Q0 SLICE_51I/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_51I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI4in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_51I/F1 SLICE_51I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_51I/Q1 SLICE_52I/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_51I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI5in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_52I/Q0 SLICE_52I/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_52I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI6in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_52I/F1 SLICE_52I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBADRI7in (640:701:762) + (640:701:762)) + (INTERCONNECT SLICE_95I/F0 SLICE_53I/C0 (541:653:766)(541:653:766)) + (INTERCONNECT SLICE_53I/F1 SLICE_53I/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_53I/F1 SLICE_89I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_96I/F0 SLICE_53I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_53I/F0 SLICE_53I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT wb_cyc_stb_RNO_SLICE_61I/OFX0 SLICE_53I/CE (808:896:985) + (808:896:985)) + (INTERCONNECT SLICE_53I/Q0 ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBCYCIin + (1343:1474:1606)(1343:1474:1606)) + (INTERCONNECT SLICE_53I/Q0 ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBSTBIin + (1689:1859:2030)(1689:1859:2030)) + (INTERCONNECT SLICE_79I/F0 SLICE_54I/D1 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_67I/F1 SLICE_54I/C1 (546:664:783)(546:664:783)) + (INTERCONNECT SLICE_67I/F1 SLICE_55I/A1 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_67I/F1 SLICE_67I/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_75I/F1 SLICE_54I/B1 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_75I/F1 SLICE_57I/B0 (772:899:1026)(772:899:1026)) + (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_75I/F1 SLICE_78I/C0 (541:655:769)(541:655:769)) + (INTERCONNECT SLICE_99I/F1 SLICE_54I/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_99I/F1 SLICE_57I/C0 (871:1021:1172)(871:1021:1172)) + (INTERCONNECT SLICE_110I/F0 SLICE_54I/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_60I/Q0 SLICE_54I/C0 (981:1133:1285)(981:1133:1285)) + (INTERCONNECT SLICE_60I/Q0 ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBWEIin + (2142:2348:2554)(2142:2348:2554)) + (INTERCONNECT SLICE_109I/F0 SLICE_54I/A0 (1008:1161:1315)(1008:1161:1315)) + (INTERCONNECT SLICE_109I/F0 SLICE_57I/A1 (1378:1563:1749)(1378:1563:1749)) + (INTERCONNECT SLICE_109I/F0 SLICE_70I/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_109I/F0 SLICE_83I/A0 (1378:1563:1749)(1378:1563:1749)) + (INTERCONNECT SLICE_54I/F1 SLICE_54I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54I/F0 SLICE_54I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54I/Q0 SLICE_79I/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_54I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI0in (1411:1555:1700) + (1411:1555:1700)) + (INTERCONNECT SLICE_54I/Q1 SLICE_55I/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_54I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI1in (1339:1476:1613) + (1339:1476:1613)) + (INTERCONNECT SLICE_75I/F0 SLICE_55I/C1 (541:653:766)(541:653:766)) + (INTERCONNECT SLICE_82I/F0 SLICE_55I/B1 (1472:1667:1863)(1472:1667:1863)) + (INTERCONNECT SLICE_82I/F0 SLICE_67I/C0 (914:1061:1209)(914:1061:1209)) + (INTERCONNECT SLICE_82I/F0 SLICE_76I/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_67I/F0 SLICE_55I/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_67I/F0 SLICE_56I/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_72I/F1 SLICE_55I/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72I/F1 SLICE_56I/B1 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_55I/F1 SLICE_55I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55I/F0 SLICE_55I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55I/Q0 SLICE_75I/B0 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_55I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI2in (1339:1476:1613) + (1339:1476:1613)) + (INTERCONNECT SLICE_55I/Q1 SLICE_56I/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_55I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI3in (1084:1193:1303) + (1084:1193:1303)) + (INTERCONNECT SLICE_56I/Q0 SLICE_56I/A1 (1110:1265:1420)(1110:1265:1420)) + (INTERCONNECT SLICE_56I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI4in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_76I/F0 SLICE_56I/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_80I/F0 SLICE_56I/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_56I/F1 SLICE_56I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F0 SLICE_56I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q1 SLICE_74I/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_56I/Q1 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI5in (908:1009:1111) + (908:1009:1111)) + (INTERCONNECT SLICE_78I/F0 SLICE_57I/D1 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_71I/F0 SLICE_57I/C1 (1231:1406:1581)(1231:1406:1581)) + (INTERCONNECT SLICE_81I/F0 SLICE_57I/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_74I/F0 SLICE_57I/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_57I/F1 SLICE_57I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_81I/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_57I/Q0 + ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBDATI6in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_58I/F1 SLICE_58I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_58I/F1 SLICE_93I/A1 (1177:1342:1507)(1177:1342:1507)) + (INTERCONNECT SLICE_59I/F1 SLICE_58I/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_59I/F1 SLICE_59I/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_58I/Q0 SLICE_58I/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_58I/Q0 SLICE_89I/A1 (738:857:977)(738:857:977)) + (INTERCONNECT SLICE_58I/Q0 SLICE_96I/B0 (777:906:1036)(777:906:1036)) + (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118I/Q0 SLICE_59I/D1 (975:1072:1170)(975:1072:1170)) + (INTERCONNECT SLICE_118I/Q0 SLICE_95I/B1 (1581:1778:1975)(1581:1778:1975)) + (INTERCONNECT SLICE_118I/Q0 SLICE_97I/B1 (1217:1382:1548)(1217:1382:1548)) + (INTERCONNECT SLICE_59I/Q0 SLICE_59I/C0 (1426:1605:1785)(1426:1605:1785)) + (INTERCONNECT SLICE_59I/Q0 ufmefb_EFBInst_0I/ufmefb_EFBInst_0_EFB/INST20/WBRSTIin + (1616:1766:1917)(1616:1766:1917)) + (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_60I/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_84I/F1 SLICE_62I/D0 (794:884:975)(794:884:975)) + (INTERCONNECT SLICE_84I/F1 SLICE_84I/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_87I/F0 SLICE_60I/A1 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_87I/F0 SLICE_84I/A0 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_73I/Q0 SLICE_60I/D0 (1153:1269:1385)(1153:1269:1385)) + (INTERCONNECT SLICE_93I/F1 SLICE_60I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_60I/F1 SLICE_60I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 wb_cyc_stb_RNO_SLICE_61I/A1 (481:577:673)(481:577:673)) + (INTERCONNECT SLICE_95I/F1 SLICE_62I/D1 (525:584:643)(525:584:643)) + (INTERCONNECT SLICE_95I/F1 SLICE_95I/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_89I/F0 wb_cyc_stb_RNO_SLICE_61I/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_102I/F0 wb_cyc_stb_RNO_SLICE_61I/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_102I/F0 SLICE_62I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT ufmefb_EFBInst_0I/WBACKO wb_cyc_stb_RNO_SLICE_61I/A0 + (1729:1940:2151)(1729:1940:2151)) + (INTERCONNECT ufmefb_EFBInst_0I/WBACKO SLICE_62I/B0 (1761:1974:2188) + (1761:1974:2188)) + (INTERCONNECT SLICE_62I/F0 SLICE_62I/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_77I/F1 SLICE_63I/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_77I/F1 SLICE_77I/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_77I/F1 SLICE_108I/A1 (745:874:1003)(745:874:1003)) + (INTERCONNECT SLICE_63I/F0 SLICE_66I/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_64I/F0 SLICE_66I/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_98I/F0 SLICE_64I/B1 (1099:1259:1420)(1099:1259:1420)) + (INTERCONNECT SLICE_68I/F1 SLICE_64I/A1 (740:863:986)(740:863:986)) + (INTERCONNECT SLICE_105I/Q1 SLICE_64I/B0 (1472:1666:1861)(1472:1666:1861)) + (INTERCONNECT SLICE_105I/Q1 SLICE_98I/A0 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_105I/Q1 SLICE_117I/C1 (537:644:751)(537:644:751)) + (INTERCONNECT SLICE_64I/F1 nRWE_MGIOLI/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_65I/F1 SLICE_85I/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_66I/F1 SLICE_66I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_88I/F0 SLICE_66I/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_66I/F0 nRCAS_MGIOLI/OPOS (1445:1584:1723)(1445:1584:1723)) + (INTERCONNECT SLICE_100I/F0 SLICE_67I/A1 (1067:1225:1383)(1067:1225:1383)) + (INTERCONNECT SLICE_69I/F1 SLICE_68I/D1 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_68I/F0 SLICE_68I/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_70I/F0 SLICE_70I/A1 (1104:1258:1413)(1104:1258:1413)) + (INTERCONNECT SLICE_70I/F1 SLICE_74I/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_70I/F1 SLICE_80I/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72I/F0 SLICE_72I/A1 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_72I/F0 SLICE_79I/A0 (738:859:981)(738:859:981)) + (INTERCONNECT SLICE_72I/F0 SLICE_80I/D0 (528:584:640)(528:584:640)) + (INTERCONNECT Din_3_I/PADDI SLICE_73I/C1 (2075:2285:2495)(2075:2285:2495)) + (INTERCONNECT Din_3_I/PADDI SLICE_101I/B1 (3414:3733:4052)(3414:3733:4052)) + (INTERCONNECT Din_3_I/PADDI SLICE_106I/B1 (2686:2942:3198)(2686:2942:3198)) + (INTERCONNECT Din_3_I/PADDI SLICE_106I/B0 (2686:2942:3198)(2686:2942:3198)) + (INTERCONNECT Din_3_I/PADDI RD_3_MGIOLI/OPOS (3289:3551:3813)(3289:3551:3813)) + (INTERCONNECT Din_3_I/PADDI Din_3_MGIOLI/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_116I/F0 SLICE_73I/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_73I/F0 SLICE_73I/CE (539:596:653)(539:596:653)) + (INTERCONNECT SLICE_103I/F1 SLICE_74I/D1 (530:587:645)(530:587:645)) + (INTERCONNECT SLICE_109I/F1 SLICE_74I/A1 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_109I/F1 SLICE_80I/A0 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_74I/F1 SLICE_74I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_99I/F0 SLICE_75I/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_77I/F0 SLICE_117I/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_78I/F1 SLICE_78I/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_103I/F0 SLICE_81I/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_83I/F0 SLICE_81I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_82I/F1 SLICE_82I/C0 (542:652:762)(542:652:762)) + (INTERCONNECT SLICE_82I/F1 SLICE_87I/A0 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_87I/F1 SLICE_82I/A0 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_87I/F1 SLICE_84I/D1 (530:592:654)(530:592:654)) + (INTERCONNECT SLICE_87I/F1 SLICE_87I/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_87I/F1 SLICE_93I/D0 (530:592:654)(530:592:654)) + (INTERCONNECT SLICE_83I/F1 SLICE_83I/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_110I/F1 SLICE_84I/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_110I/F1 SLICE_93I/A0 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_93I/F0 SLICE_84I/D0 (531:586:641)(531:586:641)) + (INTERCONNECT SLICE_93I/F0 SLICE_93I/D1 (531:586:641)(531:586:641)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/A1 (476:566:656)(476:566:656)) + (INTERCONNECT SLICE_86I/F0 SLICE_85I/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_100I/F1 SLICE_85I/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_117I/F1 SLICE_88I/D1 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_108I/F1 SLICE_88I/C1 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_108I/F1 nRRAS_MGIOLI/OPOS (1448:1590:1732)(1448:1590:1732)) + (INTERCONNECT SLICE_108I/Q0 SLICE_88I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_88I/F1 nRCS_MGIOLI/OPOS (1337:1468:1599)(1337:1468:1599)) + (INTERCONNECT SLICE_96I/F1 SLICE_89I/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_96I/F1 SLICE_96I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_89I/F1 SLICE_89I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_105I/F1 SLICE_91I/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_111I/F0 SLICE_91I/A0 (1174:1336:1498)(1174:1336:1498)) + (INTERCONNECT SLICE_92I/F1 SLICE_92I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_92I/F1 SLICE_105I/C0 (280:362:445)(280:362:445)) + (INTERCONNECT Din_0_MGIOLI/INP SLICE_94I/B1 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT Din_1_MGIOLI/INP SLICE_94I/A1 (926:1065:1204)(926:1065:1204)) + (INTERCONNECT Din_4_MGIOLI/INP SLICE_94I/D0 (716:789:863)(716:789:863)) + (INTERCONNECT SLICE_94I/F1 SLICE_94I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din_3_MGIOLI/INP SLICE_94I/A0 (926:1065:1204)(926:1065:1204)) + (INTERCONNECT SLICE_97I/F1 SLICE_97I/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_98I/F1 SLICE_98I/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din_2_I/PADDI SLICE_104I/D0 (1961:2109:2258)(1961:2109:2258)) + (INTERCONNECT Din_2_I/PADDI SLICE_106I/D1 (2331:2511:2692)(2331:2511:2692)) + (INTERCONNECT Din_2_I/PADDI SLICE_106I/D0 (2331:2511:2692)(2331:2511:2692)) + (INTERCONNECT Din_2_I/PADDI RD_2_MGIOLI/OPOS (2436:2626:2817)(2436:2626:2817)) + (INTERCONNECT Din_2_I/PADDI Din_2_MGIOLI/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_107I/F0 RA_9_I/PADDO (1279:1433:1587)(1279:1433:1587)) + (INTERCONNECT SLICE_107I/F1 RDQMHI/PADDO (1454:1620:1786)(1454:1620:1786)) + (INTERCONNECT SLICE_111I/F1 RA_7_I/PADDO (1834:2056:2279)(1834:2056:2279)) + (INTERCONNECT SLICE_112I/F0 RA_0_I/PADDO (1400:1583:1767)(1400:1583:1767)) + (INTERCONNECT SLICE_112I/F1 RDQMLI/PADDO (936:1038:1140)(936:1038:1140)) + (INTERCONNECT SLICE_113I/F0 RA_1_I/PADDO (1106:1265:1425)(1106:1265:1425)) + (INTERCONNECT SLICE_113I/F1 RA_8_I/PADDO (1279:1433:1587)(1279:1433:1587)) + (INTERCONNECT SLICE_114I/F0 RA_2_I/PADDO (1815:2042:2270)(1815:2042:2270)) + (INTERCONNECT SLICE_114I/F1 RA_6_I/PADDO (1879:2100:2321)(1879:2100:2321)) + (INTERCONNECT SLICE_115I/F0 RA_3_I/PADDO (1552:1738:1924)(1552:1738:1924)) + (INTERCONNECT SLICE_115I/F1 RA_5_I/PADDO (1815:2042:2270)(1815:2042:2270)) + (INTERCONNECT SLICE_116I/F1 RA_11_MGIOLI/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT CROW_0_I/PADDI SLICE_118I/B1 (2262:2486:2711)(2262:2486:2711)) + (INTERCONNECT CROW_1_I/PADDI SLICE_118I/B0 (1744:1935:2126)(1744:1935:2126)) + (INTERCONNECT SLICE_118I/F0 RBA_1_MGIOLI/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_118I/F1 RBA_0_MGIOLI/OPOS (1790:1965:2141)(1790:1965:2141)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD_0_MGIOLI/IOLDO RD_0_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT nRCAS_MGIOLI/IOLDO nRCASI/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRRAS_MGIOLI/IOLDO nRRASI/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRWE_MGIOLI/IOLDO nRWEI/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT nRCS_MGIOLI/IOLDO nRCSI/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (2632:2848:3064)(2632:2848:3064)) + (INTERCONNECT RD_7_MGIOLI/IOLDO RD_7_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD_6_MGIOLI/IOLDO RD_6_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD_5_MGIOLI/IOLDO RD_5_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD_4_MGIOLI/IOLDO RD_4_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (2632:2848:3064)(2632:2848:3064)) + (INTERCONNECT RD_3_MGIOLI/IOLDO RD_3_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD_2_MGIOLI/IOLDO RD_2_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD_1_MGIOLI/IOLDO RD_1_I0/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RA_11_MGIOLI/IOLDO RA_11_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA_10_MGIOLI/IOLDO RA_10_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA_1_MGIOLI/IOLDO RBA_1_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA_0_MGIOLI/IOLDO RBA_0_I/IOLDO (9:36:63)(9:36:63)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.vho b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.vho new file mode 100644 index 0000000..420b323 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vho.vho @@ -0,0 +1,38189 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o LCMXO2_640HC_impl1_vho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd +-- Netlist created on Sat Aug 19 21:54:57 2023 +-- Netlist written on Sat Aug 19 21:55:20 2023 +-- Design is for device LCMXO2-640HC +-- Design is for package TQFP100 +-- Design is for performance grade 4 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_cry_0_0: ccu2B0 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out) + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_s_0_17: ccu20001 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_15: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_13: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_11: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_9: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_7: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_5: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_3: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_1: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"3302") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + CmdEnable17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + ADSubmitted_r: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"F4F4") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_11 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_11 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_11"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_11 : ENTITY IS TRUE; + + end SLICE_11; + + architecture Structure of SLICE_11 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + C1Submitted_s: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + C1Submitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_12 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_12 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_12"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_12 : ENTITY IS TRUE; + + end SLICE_12; + + architecture Structure of SLICE_12 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nCCAS_pad_RNISUR8: lut40006 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + begin + INST10: ROM16X1A + generic map (initval => X"AAFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0009 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0009 : ENTITY IS TRUE; + + end vmuxregsre0009; + + architecture Structure of vmuxregsre0009 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3_2: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_RNO_0: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_0: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"FFCC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"C8AA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_17 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_17 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_17"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE; + + end SLICE_17; + + architecture Structure of SLICE_17 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_17_SLICE_17_K1_H1: Std_logic; + signal SLICE_17_CmdEnable_s_GATE_H0: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_17_K1: lut40010 + port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, + Z=>SLICE_17_SLICE_17_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdEnable_s_GATE: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_17_CmdEnable_s_GATE_H0); + CmdEnable: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + SLICE_17_K0K1MUX: selmux2 + port map (D0=>SLICE_17_CmdEnable_s_GATE_H0, D1=>SLICE_17_SLICE_17_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"F0AA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"B8B8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdLEDEN_4_0: lut40012 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdLEDEN_4_u: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + CmdLEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"0322") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMShift_3_u: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMShift: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"0232") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_21 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_21 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_21"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE; + + end SLICE_21; + + architecture Structure of SLICE_21 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMShift_3_u_fast: lut40015 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMShift_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"0A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"3022") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_22 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_22 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_22"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE; + + end SLICE_22; + + architecture Structure of SLICE_22 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMWrite_2: lut40016 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMWrite_3_u: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMWrite: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"0100") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"F0C0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG11: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdValid_r: lut40019 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdValid: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"CC88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG18: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdValid_r_fast: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); + CmdValid_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"0FAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"F0CC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Cmdn8MEGEN_4_0: lut40022 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_4_u: lut40023 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"FFF0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"0F0F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nCCAS_pad_RNI01SJ: lut40024 + port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nFWE_pad_RNI420B: lut40025 + port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + FWEr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, C0_ipd, DI0_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"FA05") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_28 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_28 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_28"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_28 : ENTITY IS TRUE; + + end SLICE_28; + + architecture Structure of SLICE_28 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_0io_RNO: lut40026 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_RNO_0: lut40027 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"5AAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"5A5A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_29 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_29 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_29"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE; + + end SLICE_29; + + architecture Structure of SLICE_29 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_RNO_2: lut40028 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_n1_0_x2: lut40029 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"FFAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + begin + INST10: ROM16X1A + generic map (initval => X"7F80") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_2_sqmuxa_0_o2: lut40030 + port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_RNO_3: lut40031 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"FAFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + InitReady3_0_a3: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + InitReady_RNO: lut40033 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"CCAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LEDEN_6: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"FFAF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"00FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LED_pad_RNO: lut40035 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr_RNO: lut40036 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); + RASr2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"0055") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"F5A0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: lut40037 + port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_4: lut40038 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"05CC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"CCEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_8_u_RNO: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKEEN_8_u: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RCKEEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"F0EA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_Bank_1_4: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKE_2_0: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RCKE: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"5FFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"AEAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_38 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_38 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_38"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE; + + end SLICE_38; + + architecture Structure of SLICE_38 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_o2: lut40043 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_RNO: lut40044 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Ready: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"0400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_39 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_39 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_39"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE; + + end SLICE_39; + + architecture Structure of SLICE_39 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + Ready_fast_RNO: lut40033 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_40 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_40 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_40"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE; + + end SLICE_40; + + architecture Structure of SLICE_40 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_1: lut40046 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_0: lut40046 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"CC00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"F000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_41 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_41 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_41"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE; + + end SLICE_41; + + architecture Structure of SLICE_41 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_3: lut40047 + port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_2: lut40048 + port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"FF55") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"A0A0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_42 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_42 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_42"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE; + + end SLICE_42; + + architecture Structure of SLICE_42 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_5: lut40049 + port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_4: lut40050 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_7: lut40046 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_6: lut40046 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"CCFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"AA00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_9: lut40051 + port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_8: lut40052 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); + RowA_9: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_8: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"0C08") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRRAS_5_u_i_0: lut40053 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_0_i_o2_1: lut40024 + port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_1: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"4C00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"E2E2") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_46 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_46 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_46"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE; + + end SLICE_46; + + architecture Structure of SLICE_46 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG_3_u_0_bm: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + XOR8MEG_3_u_0_GATE: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + XOR8MEG: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"AAF0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_47 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_47 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_47"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE; + + end SLICE_47; + + architecture Structure of SLICE_47 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_rst10: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_6: lut40057 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"DCEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_48 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_48 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_48"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE; + + end SLICE_48; + + architecture Structure of SLICE_48 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRowColSel_0_0_a3_0: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRowColSel_0_0: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"D1C0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"BB88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_1: lut40060 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_adr_5_0: lut40061 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, + A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"A0A0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_3: lut40062 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_2: lut40063 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + wb_adr_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"AFA0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_51 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_51 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_51"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE; + + end SLICE_51; + + architecture Structure of SLICE_51 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_5: lut40064 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_4: lut40064 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_adr_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, + DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"AA00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"CCF0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_52 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_52 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_52"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE; + + end SLICE_52; + + architecture Structure of SLICE_52 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_5_7: lut40065 + port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_adr_5_6: lut40066 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_adr_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_adr_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, DI1_dly, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"0100") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + begin + INST10: ROM16X1A + generic map (initval => X"F8F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_53 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_53 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_53"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE; + + end SLICE_53; + + architecture Structure of SLICE_53 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_2: lut40067 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_wb_cyc_stb_1_sqmuxa_0: lut40068 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_cyc_stb: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + begin + INST10: ROM16X1A + generic map (initval => X"FFF8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + begin + INST10: ROM16X1A + generic map (initval => X"EAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_54 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_54 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_54"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE; + + end SLICE_54; + + architecture Structure of SLICE_54 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_1: lut40069 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_0_iv_0_0: lut40070 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_55 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_55 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_55"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE; + + end SLICE_55; + + architecture Structure of SLICE_55 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_3: lut40071 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_2: lut40072 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + begin + INST10: ROM16X1A + generic map (initval => X"EFEA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_5: lut40073 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_4: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_dati_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, + F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40076 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40076 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE; + + end lut40076; + + architecture Structure of lut40076 is + begin + INST10: ROM16X1A + generic map (initval => X"FFC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40076 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_7: lut40075 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_6: lut40076 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + wb_dati_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40077 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40077 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE; + + end lut40077; + + architecture Structure of lut40077 is + begin + INST10: ROM16X1A + generic map (initval => X"2E22") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + FS_RNIVOOA_14: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_reqe: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_req: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40078 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40078 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE; + + end lut40078; + + architecture Structure of lut40078 is + begin + INST10: ROM16X1A + generic map (initval => X"4F0F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40079 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40079 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE; + + end lut40079; + + architecture Structure of lut40079 is + begin + INST10: ROM16X1A + generic map (initval => X"7430") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40078 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40079 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + PHI2r3_RNIS5A51: lut40078 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_rste: lut40079 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_rst: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40080 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40080 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE; + + end lut40080; + + architecture Structure of lut40080 is + begin + INST10: ROM16X1A + generic map (initval => X"CD05") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0009 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40080 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_adr_0_sqmuxa_2: lut40033 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we_0: lut40080 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + wb_we: vmuxregsre0009 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40081 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40081 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE; + + end lut40081; + + architecture Structure of lut40081 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40082 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40082 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE; + + end lut40082; + + architecture Structure of lut40082 is + begin + INST10: ROM16X1A + generic map (initval => X"FFAF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity wb_cyc_stb_RNO_SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity wb_cyc_stb_RNO_SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "wb_cyc_stb_RNO_SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF wb_cyc_stb_RNO_SLICE_61 : ENTITY IS TRUE; + + end wb_cyc_stb_RNO_SLICE_61; + + architecture Structure of wb_cyc_stb_RNO_SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40081 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40082 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_cyc_stb_RNO_SLICE_61_K1: lut40081 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1); + wb_cyc_stb_RNO_GATE: lut40082 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, + Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_cyc_stb_RNO_SLICE_61_K0K1MUX: selmux2 + port map (D0=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0, + D1=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40083 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40083 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE; + + end lut40083; + + architecture Structure of lut40083 is + begin + INST10: ROM16X1A + generic map (initval => X"D8F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40084 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40084 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE; + + end lut40084; + + architecture Structure of lut40084 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40083 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40084 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdValid_fast_RNITQBM1: lut40083 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + ufmefb_EFBInst_0_RNI9PBJ: lut40084 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40085 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40085 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE; + + end lut40085; + + architecture Structure of lut40085 is + begin + INST10: ROM16X1A + generic map (initval => X"FFF7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40086 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40086 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE; + + end lut40086; + + architecture Structure of lut40086 is + begin + INST10: ROM16X1A + generic map (initval => X"51FB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40085 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40086 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_0_sqmuxa_0_o2_0: lut40085 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_nRCAS_6_sqmuxa_i_0: lut40086 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40087 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40087 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE; + + end lut40087; + + architecture Structure of lut40087 is + begin + INST10: ROM16X1A + generic map (initval => X"F1FA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40088 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40088 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE; + + end lut40088; + + architecture Structure of lut40088 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40087 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40088 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO: lut40087 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_0_sqmuxa_1_0_a3: lut40088 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40089 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40089 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE; + + end lut40089; + + architecture Structure of lut40089 is + begin + INST10: ROM16X1A + generic map (initval => X"0520") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40090 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40090 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE; + + end lut40090; + + architecture Structure of lut40090 is + begin + INST10: ROM16X1A + generic map (initval => X"7071") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40089 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40090 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_0: lut40089 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_40_1_0_1: lut40090 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40091 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40091 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE; + + end lut40091; + + architecture Structure of lut40091 is + begin + INST10: ROM16X1A + generic map (initval => X"1133") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40092 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40092 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE; + + end lut40092; + + architecture Structure of lut40092 is + begin + INST10: ROM16X1A + generic map (initval => X"1303") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40091 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40092 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCAS_0io_RNO_0: lut40091 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_0io_RNO: lut40092 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40093 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40093 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE; + + end lut40093; + + architecture Structure of lut40093 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40094 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40094 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE; + + end lut40094; + + architecture Structure of lut40094 is + begin + INST10: ROM16X1A + generic map (initval => X"FCCC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40093 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40094 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_1: lut40093 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_o3_2: lut40094 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40095 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40095 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE; + + end lut40095; + + architecture Structure of lut40095 is + begin + INST10: ROM16X1A + generic map (initval => X"05AA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40096 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40096 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE; + + end lut40096; + + architecture Structure of lut40096 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40095 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40096 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_1: lut40095 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_0io_RNO_4: lut40096 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40097 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40097 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE; + + end lut40097; + + architecture Structure of lut40097 is + begin + INST10: ROM16X1A + generic map (initval => X"AFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40098 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40098 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE; + + end lut40098; + + architecture Structure of lut40098 is + begin + INST10: ROM16X1A + generic map (initval => X"1100") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40097 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40098 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_3: lut40097 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_RNICVV51_0: lut40098 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40099 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40099 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE; + + end lut40099; + + architecture Structure of lut40099 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40100 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE; + + end lut40100; + + architecture Structure of lut40100 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40099 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40100 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_4: lut40099 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_a3_RNO_4: lut40100 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40101 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE; + + end lut40101; + + architecture Structure of lut40101 is + begin + INST10: ROM16X1A + generic map (initval => X"2002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE; + + end SLICE_71; + + architecture Structure of SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40101 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_we113_i_a2: lut40050 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_RNO_7: lut40101 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40102 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE; + + end lut40102; + + architecture Structure of lut40102 is + begin + INST10: ROM16X1A + generic map (initval => X"8A00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40103 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE; + + end lut40103; + + architecture Structure of lut40103 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40102 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40103 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_2: lut40102 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + FS_RNI3V8E_9: lut40103 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40104 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE; + + end lut40104; + + architecture Structure of lut40104 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40105 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE; + + end lut40105; + + architecture Structure of lut40105 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40104 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40105 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG14: lut40104 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdUFMData_RNO: lut40105 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMData: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40106 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE; + + end lut40106; + + architecture Structure of lut40106 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40107 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40107 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE; + + end lut40107; + + architecture Structure of lut40107 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40106 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40107 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_6: lut40106 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_6: lut40107 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40108 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40108 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE; + + end lut40108; + + architecture Structure of lut40108 is + begin + INST10: ROM16X1A + generic map (initval => X"0022") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40109 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40109 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE; + + end lut40109; + + architecture Structure of lut40109 is + begin + INST10: ROM16X1A + generic map (initval => X"F888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40108 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40109 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_0_3: lut40108 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_0_3: lut40109 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40110 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40110 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE; + + end lut40110; + + architecture Structure of lut40110 is + begin + INST10: ROM16X1A + generic map (initval => X"0010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40110 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_cnst_sn_m2_0_a3: lut40110 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_RNO_4: lut40063 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40111 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40111 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE; + + end lut40111; + + architecture Structure of lut40111 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40112 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40112 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE; + + end lut40112; + + architecture Structure of lut40112 is + begin + INST10: ROM16X1A + generic map (initval => X"FF0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40111 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40112 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_nRCAS_6_sqmuxa_i_o2: lut40111 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRRAS_5_u_i: lut40112 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40113 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40113 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE; + + end lut40113; + + architecture Structure of lut40113 is + begin + INST10: ROM16X1A + generic map (initval => X"B5B5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40114 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40114 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE; + + end lut40114; + + architecture Structure of lut40114 is + begin + INST10: ROM16X1A + generic map (initval => X"C000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40113 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40114 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_m3_7: lut40113 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_7: lut40114 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40115 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40115 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE; + + end lut40115; + + architecture Structure of lut40115 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40116 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40116 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE; + + end lut40116; + + architecture Structure of lut40116 is + begin + INST10: ROM16X1A + generic map (initval => X"ECA0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40115 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40116 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_2_0_1: lut40115 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_0_1: lut40116 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40117 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40117 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40117 : ENTITY IS TRUE; + + end lut40117; + + architecture Structure of lut40117 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40118 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40118 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40118 : ENTITY IS TRUE; + + end lut40118; + + architecture Structure of lut40118 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40117 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40118 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_1_1_4: lut40117 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_4: lut40118 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40119 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40119 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40119 : ENTITY IS TRUE; + + end lut40119; + + architecture Structure of lut40119 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40120 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40120 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40120 : ENTITY IS TRUE; + + end lut40120; + + architecture Structure of lut40120 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40119 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40120 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_3_7: lut40119 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_1_7: lut40120 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40121 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40121 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40121 : ENTITY IS TRUE; + + end lut40121; + + architecture Structure of lut40121 is + begin + INST10: ROM16X1A + generic map (initval => X"1111") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40122 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40122 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40122 : ENTITY IS TRUE; + + end lut40122; + + architecture Structure of lut40122 is + begin + INST10: ROM16X1A + generic map (initval => X"9040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40121 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40122 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_we95_0_0: lut40121 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_we95_1: lut40122 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40123 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40123 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40123 : ENTITY IS TRUE; + + end lut40123; + + architecture Structure of lut40123 is + begin + INST10: ROM16X1A + generic map (initval => X"0011") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40102 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40123 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_7: lut40123 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_1_7: lut40102 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40124 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40124 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40124 : ENTITY IS TRUE; + + end lut40124; + + architecture Structure of lut40124 is + begin + INST10: ROM16X1A + generic map (initval => X"0010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40125 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40125 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40125 : ENTITY IS TRUE; + + end lut40125; + + architecture Structure of lut40125 is + begin + INST10: ROM16X1A + generic map (initval => X"0500") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40124 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40125 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_29: lut40124 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_adr_cnst_sn_m4_32: lut40125 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40126 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40126 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40126 : ENTITY IS TRUE; + + end lut40126; + + architecture Structure of lut40126 is + begin + INST10: ROM16X1A + generic map (initval => X"8484") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40127 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40127 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40127 : ENTITY IS TRUE; + + end lut40127; + + architecture Structure of lut40127 is + begin + INST10: ROM16X1A + generic map (initval => X"F4F8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40126 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40127 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_adr_cnst_0_0: lut40126 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_FS_40_1_1_1: lut40127 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40128 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40128 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40128 : ENTITY IS TRUE; + + end lut40128; + + architecture Structure of lut40128 is + begin + INST10: ROM16X1A + generic map (initval => X"FBAB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40114 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40128 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_o6: lut40128 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_40_1_a6: lut40114 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40129 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40129 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40129 : ENTITY IS TRUE; + + end lut40129; + + architecture Structure of lut40129 is + begin + INST10: ROM16X1A + generic map (initval => X"33FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40130 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40130 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40130 : ENTITY IS TRUE; + + end lut40130; + + architecture Structure of lut40130 is + begin + INST10: ROM16X1A + generic map (initval => X"8008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40129 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40130 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_21_1_i: lut40129 + port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we95: lut40130 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40131 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40131 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40131 : ENTITY IS TRUE; + + end lut40131; + + architecture Structure of lut40131 is + begin + INST10: ROM16X1A + generic map (initval => X"77F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40132 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40132 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40132 : ENTITY IS TRUE; + + end lut40132; + + architecture Structure of lut40132 is + begin + INST10: ROM16X1A + generic map (initval => X"2055") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40131 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40132 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_0io_RNO: lut40131 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_r_i_a3_1_1_tz: lut40132 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40133 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40133 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40133 : ENTITY IS TRUE; + + end lut40133; + + architecture Structure of lut40133 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40134 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40134 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40134 : ENTITY IS TRUE; + + end lut40134; + + architecture Structure of lut40134 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40133 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40134 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_o3: lut40133 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_2_sqmuxa_i_a3: lut40134 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40135 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40135 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40135 : ENTITY IS TRUE; + + end lut40135; + + architecture Structure of lut40135 is + begin + INST10: ROM16X1A + generic map (initval => X"F0E0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40136 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40136 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40136 : ENTITY IS TRUE; + + end lut40136; + + architecture Structure of lut40136 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40135 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40136 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_CMDWR: lut40135 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + C1WR_7: lut40136 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40137 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40137 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40137 : ENTITY IS TRUE; + + end lut40137; + + architecture Structure of lut40137 is + begin + INST10: ROM16X1A + generic map (initval => X"C8C8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40105 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40137 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_ADWR: lut40137 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADWR_7: lut40105 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40138 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40138 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40138 : ENTITY IS TRUE; + + end lut40138; + + architecture Structure of lut40138 is + begin + INST10: ROM16X1A + generic map (initval => X"C000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40139 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40139 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40139 : ENTITY IS TRUE; + + end lut40139; + + architecture Structure of lut40139 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40138 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40139 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + C1WR_0: lut40138 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + C1WR_2: lut40139 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40140 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40140 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40140 : ENTITY IS TRUE; + + end lut40140; + + architecture Structure of lut40140 is + begin + INST10: ROM16X1A + generic map (initval => X"AFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40141 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40141 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40141 : ENTITY IS TRUE; + + end lut40141; + + architecture Structure of lut40141 is + begin + INST10: ROM16X1A + generic map (initval => X"CFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40140 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40141 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_adr_0_sqmuxa_3: lut40140 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_we113_i_0: lut40141 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40142 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40142 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40142 : ENTITY IS TRUE; + + end lut40142; + + architecture Structure of lut40142 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40143 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40143 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40143 : ENTITY IS TRUE; + + end lut40143; + + architecture Structure of lut40143 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40142 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40143 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_Bank_1_3: lut40142 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_Bank_1: lut40143 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40144 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40144 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40144 : ENTITY IS TRUE; + + end lut40144; + + architecture Structure of lut40144 is + begin + INST10: ROM16X1A + generic map (initval => X"4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40145 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40145 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40145 : ENTITY IS TRUE; + + end lut40145; + + architecture Structure of lut40145 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40144 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40145 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_PHI2r3_0: lut40144 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_1_sqmuxa_0_a3: lut40145 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40146 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40146 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40146 : ENTITY IS TRUE; + + end lut40146; + + architecture Structure of lut40146 is + begin + INST10: ROM16X1A + generic map (initval => X"0005") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40147 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40147 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40147 : ENTITY IS TRUE; + + end lut40147; + + architecture Structure of lut40147 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40146 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40147 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_wb_cyc_stb_2_sqmuxa_i_a3_1: lut40146 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2: lut40147 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40148 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40148 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40148 : ENTITY IS TRUE; + + end lut40148; + + architecture Structure of lut40148 is + begin + INST10: ROM16X1A + generic map (initval => X"0C0C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40149 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40149 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40149 : ENTITY IS TRUE; + + end lut40149; + + architecture Structure of lut40149 is + begin + INST10: ROM16X1A + generic map (initval => X"8F0F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40148 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40149 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + PHI2r3_RNIFT0I: lut40148 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMShift_fast_RNIG9JD1: lut40149 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40150 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40150 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40150 : ENTITY IS TRUE; + + end lut40150; + + architecture Structure of lut40150 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40151 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40151 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40151 : ENTITY IS TRUE; + + end lut40151; + + architecture Structure of lut40151 is + begin + INST10: ROM16X1A + generic map (initval => X"5000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40150 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40151 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_2: lut40150 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_0io_RNO_0: lut40151 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40152 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40152 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40152 : ENTITY IS TRUE; + + end lut40152; + + architecture Structure of lut40152 is + begin + INST10: ROM16X1A + generic map (initval => X"8100") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40143 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40152 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_0_0_0_1: lut40143 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_a3_0_0_3: lut40152 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40153 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40153 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40153 : ENTITY IS TRUE; + + end lut40153; + + architecture Structure of lut40153 is + begin + INST10: ROM16X1A + generic map (initval => X"4042") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40154 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40154 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40154 : ENTITY IS TRUE; + + end lut40154; + + architecture Structure of lut40154 is + begin + INST10: ROM16X1A + generic map (initval => X"2004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40153 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40154 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_40_1_1_tz: lut40153 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + wb_dati_5_1_iv_0_o3_1: lut40154 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40155 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40155 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40155 : ENTITY IS TRUE; + + end lut40155; + + architecture Structure of lut40155 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40156 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40156 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40156 : ENTITY IS TRUE; + + end lut40156; + + architecture Structure of lut40156 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40155 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40156 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable17_5: lut40155 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_Din_2: lut40156 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40157 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40157 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40157 : ENTITY IS TRUE; + + end lut40157; + + architecture Structure of lut40157 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40158 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40158 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40158 : ENTITY IS TRUE; + + end lut40158; + + architecture Structure of lut40158 is + begin + INST10: ROM16X1A + generic map (initval => X"0030") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40157 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40158 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + InitReady3_0_a3_2: lut40157 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_11: lut40158 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40159 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40159 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40159 : ENTITY IS TRUE; + + end lut40159; + + architecture Structure of lut40159 is + begin + INST10: ROM16X1A + generic map (initval => X"C030") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40160 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40160 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40160 : ENTITY IS TRUE; + + end lut40160; + + architecture Structure of lut40160 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40159 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40160 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a3_0_0_6: lut40159 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a3_3_0_7: lut40160 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40161 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40161 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40161 : ENTITY IS TRUE; + + end lut40161; + + architecture Structure of lut40161 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40161 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable16_4: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdEnable17_4: lut40161 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40162 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40162 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40162 : ENTITY IS TRUE; + + end lut40162; + + architecture Structure of lut40162 is + begin + INST10: ROM16X1A + generic map (initval => X"00A0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40163 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40163 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40163 : ENTITY IS TRUE; + + end lut40163; + + architecture Structure of lut40163 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40162 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40163 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + ADWR_4: lut40162 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CMDWR_2: lut40163 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CBR_fast: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40164 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40164 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40164 : ENTITY IS TRUE; + + end lut40164; + + architecture Structure of lut40164 is + begin + INST10: ROM16X1A + generic map (initval => X"00CC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40165 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40165 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40165 : ENTITY IS TRUE; + + end lut40165; + + architecture Structure of lut40165 is + begin + INST10: ROM16X1A + generic map (initval => X"0010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40164 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40165 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG9_1: lut40164 + port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdEnable16_5: lut40165 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40166 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40166 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40166 : ENTITY IS TRUE; + + end lut40166; + + architecture Structure of lut40166 is + begin + INST10: ROM16X1A + generic map (initval => X"CFCF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40167 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40167 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40167 : ENTITY IS TRUE; + + end lut40167; + + architecture Structure of lut40167 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_107 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_107 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_107"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_107 : ENTITY IS TRUE; + + end SLICE_107; + + architecture Structure of SLICE_107 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40166 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40167 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQMH: lut40166 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_9: lut40167 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40168 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40168 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40168 : ENTITY IS TRUE; + + end lut40168; + + architecture Structure of lut40168 is + begin + INST10: ROM16X1A + generic map (initval => X"0F01") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40169 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40169 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40169 : ENTITY IS TRUE; + + end lut40169; + + architecture Structure of lut40169 is + begin + INST10: ROM16X1A + generic map (initval => X"000F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_108 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_108 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_108"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_108 : ENTITY IS TRUE; + + end SLICE_108; + + architecture Structure of SLICE_108 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40168 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40169 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRRAS_5_u_i_0_RNILD5I: lut40168 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_0_sqmuxa_0_o2_0_RNIS63D: lut40169 + port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FWEr_fast: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40170 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40170 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40170 : ENTITY IS TRUE; + + end lut40170; + + architecture Structure of lut40170 is + begin + INST10: ROM16X1A + generic map (initval => X"5500") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40171 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40171 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40171 : ENTITY IS TRUE; + + end lut40171; + + architecture Structure of lut40171 is + begin + INST10: ROM16X1A + generic map (initval => X"0F00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_109 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_109 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_109"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_109 : ENTITY IS TRUE; + + end SLICE_109; + + architecture Structure of SLICE_109 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40170 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40171 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + wb_dati_5_1_iv_0_a2_4: lut40170 + port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_1_iv_0_a2_0_4: lut40171 + port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40172 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40172 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40172 : ENTITY IS TRUE; + + end lut40172; + + architecture Structure of lut40172 is + begin + INST10: ROM16X1A + generic map (initval => X"3F3F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40173 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40173 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40173 : ENTITY IS TRUE; + + end lut40173; + + architecture Structure of lut40173 is + begin + INST10: ROM16X1A + generic map (initval => X"6000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_110 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_110 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_110"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_110 : ENTITY IS TRUE; + + end SLICE_110; + + architecture Structure of SLICE_110 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40172 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40173 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_22_1_i: lut40172 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + wb_dati_5_0_iv_0_a3_1_0: lut40173 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40174 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40174 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40174 : ENTITY IS TRUE; + + end lut40174; + + architecture Structure of lut40174 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_111 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_111 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_111"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_111 : ENTITY IS TRUE; + + end SLICE_111; + + architecture Structure of SLICE_111 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40174 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_7: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADWR_5: lut40174 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40175 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40175 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40175 : ENTITY IS TRUE; + + end lut40175; + + architecture Structure of lut40175 is + begin + INST10: ROM16X1A + generic map (initval => X"3F3F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40176 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40176 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40176 : ENTITY IS TRUE; + + end lut40176; + + architecture Structure of lut40176 is + begin + INST10: ROM16X1A + generic map (initval => X"F0CC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_112 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_112 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_112"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_112 : ENTITY IS TRUE; + + end SLICE_112; + + architecture Structure of SLICE_112 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40175 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40176 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQML: lut40175 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_0: lut40176 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_113 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_113 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_113"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_113 : ENTITY IS TRUE; + + end SLICE_113; + + architecture Structure of SLICE_113 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_8: lut40038 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_1: lut40038 + port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40177 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40177 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40177 : ENTITY IS TRUE; + + end lut40177; + + architecture Structure of lut40177 is + begin + INST10: ROM16X1A + generic map (initval => X"E4E4") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_114 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_114 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_114"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_114 : ENTITY IS TRUE; + + end SLICE_114; + + architecture Structure of SLICE_114 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40177 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_6: lut40038 + port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_2: lut40177 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40178 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40178 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40178 : ENTITY IS TRUE; + + end lut40178; + + architecture Structure of lut40178 is + begin + INST10: ROM16X1A + generic map (initval => X"BB88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40179 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40179 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40179 : ENTITY IS TRUE; + + end lut40179; + + architecture Structure of lut40179 is + begin + INST10: ROM16X1A + generic map (initval => X"D8D8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_115 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_115 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_115"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_115 : ENTITY IS TRUE; + + end SLICE_115; + + architecture Structure of SLICE_115 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40178 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40179 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_5: lut40178 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_3: lut40179 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40180 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40180 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40180 : ENTITY IS TRUE; + + end lut40180; + + architecture Structure of lut40180 is + begin + INST10: ROM16X1A + generic map (initval => X"8488") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40181 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40181 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40181 : ENTITY IS TRUE; + + end lut40181; + + architecture Structure of lut40181 is + begin + INST10: ROM16X1A + generic map (initval => X"4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_116 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_116 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_116"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_116 : ENTITY IS TRUE; + + end SLICE_116; + + architecture Structure of SLICE_116 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40180 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40181 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA11d: lut40180 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + XOR8MEG14_1: lut40181 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40182 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40182 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40182 : ENTITY IS TRUE; + + end lut40182; + + architecture Structure of lut40182 is + begin + INST10: ROM16X1A + generic map (initval => X"0300") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40183 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40183 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40183 : ENTITY IS TRUE; + + end lut40183; + + architecture Structure of lut40183 is + begin + INST10: ROM16X1A + generic map (initval => X"4CF3") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_117 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_117 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_117"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_117 : ENTITY IS TRUE; + + end SLICE_117; + + architecture Structure of SLICE_117 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40182 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40183 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_0io_RNO_0: lut40182 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_8_u_1_0: lut40183 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40184 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40184 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40184 : ENTITY IS TRUE; + + end lut40184; + + architecture Structure of lut40184 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_118 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_118 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_118"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_118 : ENTITY IS TRUE; + + end SLICE_118; + + architecture Structure of SLICE_118 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40184 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RBAd_0: lut40184 + port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBAd_1: lut40184 + port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + PHI2r3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, M0_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IB + port map (I=>PADI, O=>Z); + INST2: OBW + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_0: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE; + + end mfflsre; + + architecture Structure of mfflsre is + begin + INST01: FD1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity RD_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE; + + end RD_0_MGIOL; + + architecture Structure of RD_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0185 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0185 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0185 : ENTITY IS TRUE; + + end xo2iobuf0185; + + architecture Structure of xo2iobuf0185 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0186 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0186 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0186 : ENTITY IS TRUE; + + end xo2iobuf0186; + + architecture Structure of xo2iobuf0186 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0186 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0186 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity smuxlregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity smuxlregsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE; + + end smuxlregsre; + + architecture Structure of smuxlregsre is + begin + INST01: IFS1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity PHI2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE; + + end PHI2_MGIOL; + + architecture Structure of PHI2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + PHI2r_0io: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RDQMLS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RDQMHS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>nRCASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre0187 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0187 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0187 : ENTITY IS TRUE; + + end mfflsre0187; + + architecture Structure of mfflsre0187 is + begin + INST01: FD1P3BX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity nRCAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE; + + end nRCAS_MGIOL; + + architecture Structure of nRCAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0187 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCAS_0io: mfflsre0187 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>nRRASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE; + + end nRRAS_MGIOL; + + architecture Structure of nRRAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0187 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRRAS_0io: mfflsre0187 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>nRWES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWE_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWE_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWE_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE; + + end nRWE_MGIOL; + + architecture Structure of nRWE_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0187 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRWE_0io: mfflsre0187 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RCKES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0188 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0188 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0188 : ENTITY IS TRUE; + + end xo2iobuf0188; + + architecture Structure of xo2iobuf0188 is + begin + INST1: IB + port map (I=>PAD, O=>Z); + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>nRCSS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE; + + end nRCS_MGIOL; + + architecture Structure of nRCS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0187 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCS_0io: mfflsre0187 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_7: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_7_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE; + + end RD_7_MGIOL; + + architecture Structure of RD_7_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_7: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_6: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE; + + end RD_6_MGIOL; + + architecture Structure of RD_6_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_6: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_5: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE; + + end RD_5_MGIOL; + + architecture Structure of RD_5_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_5: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_4: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE; + + end RD_4_MGIOL; + + architecture Structure of RD_4_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_4: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_3: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE; + + end RD_3_MGIOL; + + architecture Structure of RD_3_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_3: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_2: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE; + + end RD_2_MGIOL; + + architecture Structure of RD_2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_2: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + RD_pad_1: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE; + + end RD_1_MGIOL; + + architecture Structure of RD_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>RA11_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE; + + end RA_11_MGIOL; + + architecture Structure of RA_11_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA11_0io: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>RA10_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre0189 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0189 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0189 : ENTITY IS TRUE; + + end mfflsre0189; + + architecture Structure of mfflsre0189 is + begin + INST01: FD1P3JX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity RA_10_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE; + + end RA_10_MGIOL; + + architecture Structure of RA_10_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component mfflsre0189 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA10_0io: mfflsre0189 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, + Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA9_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA8_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA7_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA6_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA5_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA4_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA3_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA2_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>RA0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>RBA1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE; + + end RBA_1_MGIOL; + + architecture Structure of RBA_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RBA_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0185 + port map (I=>IOLDO_ipd, PAD=>RBA0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE; + + end RBA_0_MGIOL; + + architecture Structure of RBA_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RBA_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0190 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0190 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0190 : ENTITY IS TRUE; + + end xo2iobuf0190; + + architecture Structure of xo2iobuf0190 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + component xo2iobuf0190 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0190 + port map (I=>PADDO_ipd, PAD=>LEDS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0191 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0191 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0191 : ENTITY IS TRUE; + + end xo2iobuf0191; + + architecture Structure of xo2iobuf0191 is + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0191 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0191 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0191 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0191 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0191 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0191 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout7_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout6_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout5_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout4_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout3_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout2_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + component xo2iobuf0185 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0185 + port map (I=>PADDO_ipd, PAD=>Dout1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE; + + end Din_7_MGIOL; + + architecture Structure of Din_7_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_7: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE; + + end Din_6_MGIOL; + + architecture Structure of Din_6_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_6: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE; + + end Din_5_MGIOL; + + architecture Structure of Din_5_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_5: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE; + + end Din_4_MGIOL; + + architecture Structure of Din_4_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_4: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE; + + end Din_3_MGIOL; + + architecture Structure of Din_3_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_3: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE; + + end Din_2_MGIOL; + + architecture Structure of Din_2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_2: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE; + + end Din_1_MGIOL; + + architecture Structure of Din_1_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_1: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE; + + end Din_0_MGIOL; + + architecture Structure of Din_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + Bank_0io_0: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0188 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0188 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity EFB_Buffer_Block + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity EFB_Buffer_Block is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "EFB_Buffer_Block"; + + tipd_WBCLKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBRSTIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBCYCIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBSTBIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBWEIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBADRI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0DATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0ACKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1DATI0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1ACKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCSNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCCLKIin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCRSTNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCICin : VitalDelayType01 := (0 ns, 0 ns); + tipd_UFMSNin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBDATO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBACKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLCLKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLRSTOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL0STBOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLL1STBOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLWEOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLADRO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_PLLDATO0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SCLOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1SDAOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SCLOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2SDAOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C1IRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_I2C2IRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPISCKENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMISOENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMOSIENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN0in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN1in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN2in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN3in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN4in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN5in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN6in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIMCSN7in : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPICSNENin : VitalDelayType01 := (0 ns, 0 ns); + tipd_SPIIRQOin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCINTin : VitalDelayType01 := (0 ns, 0 ns); + tipd_TCOCin : VitalDelayType01 := (0 ns, 0 ns); + tipd_WBCUFMIRQin : VitalDelayType01 := (0 ns, 0 ns); + tipd_CFGWAKEin : VitalDelayType01 := (0 ns, 0 ns); + tipd_CFGSTDBYin : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBDATO0out : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBDATO1out : VitalDelayType01 := (0 ns, 0 ns); + tpd_WBCLKIin_WBACKOout : VitalDelayType01 := (0 ns, 0 ns); + ticd_WBCLKIin : VitalDelayType := 0 ns; + tisd_WBRSTIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBCYCIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBSTBIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBWEIin_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI0in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI1in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI2in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI3in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI4in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI5in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI6in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBADRI7in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI0in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI1in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI2in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI3in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI4in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI5in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI6in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tisd_WBDATI7in_WBCLKIin : VitalDelayType := 0 ns; + tsetup_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + thold_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns; + tperiod_WBCLKIin : VitalDelayType := 0 ns; + tpw_WBCLKIin_posedge : VitalDelayType := 0 ns; + tpw_WBCLKIin_negedge : VitalDelayType := 0 ns); + + port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic; + WBRSTIin: in Std_logic; WBRSTIout: out Std_logic; + WBCYCIin: in Std_logic; WBCYCIout: out Std_logic; + WBSTBIin: in Std_logic; WBSTBIout: out Std_logic; + WBWEIin: in Std_logic; WBWEIout: out Std_logic; + WBADRI7in: in Std_logic; WBADRI7out: out Std_logic; + WBADRI6in: in Std_logic; WBADRI6out: out Std_logic; + WBADRI5in: in Std_logic; WBADRI5out: out Std_logic; + WBADRI4in: in Std_logic; WBADRI4out: out Std_logic; + WBADRI3in: in Std_logic; WBADRI3out: out Std_logic; + WBADRI2in: in Std_logic; WBADRI2out: out Std_logic; + WBADRI1in: in Std_logic; WBADRI1out: out Std_logic; + WBADRI0in: in Std_logic; WBADRI0out: out Std_logic; + WBDATI7in: in Std_logic; WBDATI7out: out Std_logic; + WBDATI6in: in Std_logic; WBDATI6out: out Std_logic; + WBDATI5in: in Std_logic; WBDATI5out: out Std_logic; + WBDATI4in: in Std_logic; WBDATI4out: out Std_logic; + WBDATI3in: in Std_logic; WBDATI3out: out Std_logic; + WBDATI2in: in Std_logic; WBDATI2out: out Std_logic; + WBDATI1in: in Std_logic; WBDATI1out: out Std_logic; + WBDATI0in: in Std_logic; WBDATI0out: out Std_logic; + PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic; + PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic; + PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic; + PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic; + PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic; + PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic; + PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic; + PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic; + PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic; + PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic; + PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic; + PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic; + PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic; + PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic; + PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic; + PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic; + PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic; + PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic; + I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic; + I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic; + I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic; + I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic; + SPISCKIin: in Std_logic; SPISCKIout: out Std_logic; + SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic; + SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic; + SPISCSNin: in Std_logic; SPISCSNout: out Std_logic; + TCCLKIin: in Std_logic; TCCLKIout: out Std_logic; + TCRSTNin: in Std_logic; TCRSTNout: out Std_logic; + TCICin: in Std_logic; TCICout: out Std_logic; UFMSNin: in Std_logic; + UFMSNout: out Std_logic; WBDATO7out: out Std_logic; + WBDATO7in: in Std_logic; WBDATO6out: out Std_logic; + WBDATO6in: in Std_logic; WBDATO5out: out Std_logic; + WBDATO5in: in Std_logic; WBDATO4out: out Std_logic; + WBDATO4in: in Std_logic; WBDATO3out: out Std_logic; + WBDATO3in: in Std_logic; WBDATO2out: out Std_logic; + WBDATO2in: in Std_logic; WBDATO1out: out Std_logic; + WBDATO1in: in Std_logic; WBDATO0out: out Std_logic; + WBDATO0in: in Std_logic; WBACKOout: out Std_logic; + WBACKOin: in Std_logic; PLLCLKOout: out Std_logic; + PLLCLKOin: in Std_logic; PLLRSTOout: out Std_logic; + PLLRSTOin: in Std_logic; PLL0STBOout: out Std_logic; + PLL0STBOin: in Std_logic; PLL1STBOout: out Std_logic; + PLL1STBOin: in Std_logic; PLLWEOout: out Std_logic; + PLLWEOin: in Std_logic; PLLADRO4out: out Std_logic; + PLLADRO4in: in Std_logic; PLLADRO3out: out Std_logic; + PLLADRO3in: in Std_logic; PLLADRO2out: out Std_logic; + PLLADRO2in: in Std_logic; PLLADRO1out: out Std_logic; + PLLADRO1in: in Std_logic; PLLADRO0out: out Std_logic; + PLLADRO0in: in Std_logic; PLLDATO7out: out Std_logic; + PLLDATO7in: in Std_logic; PLLDATO6out: out Std_logic; + PLLDATO6in: in Std_logic; PLLDATO5out: out Std_logic; + PLLDATO5in: in Std_logic; PLLDATO4out: out Std_logic; + PLLDATO4in: in Std_logic; PLLDATO3out: out Std_logic; + PLLDATO3in: in Std_logic; PLLDATO2out: out Std_logic; + PLLDATO2in: in Std_logic; PLLDATO1out: out Std_logic; + PLLDATO1in: in Std_logic; PLLDATO0out: out Std_logic; + PLLDATO0in: in Std_logic; I2C1SCLOout: out Std_logic; + I2C1SCLOin: in Std_logic; I2C1SCLOENout: out Std_logic; + I2C1SCLOENin: in Std_logic; I2C1SDAOout: out Std_logic; + I2C1SDAOin: in Std_logic; I2C1SDAOENout: out Std_logic; + I2C1SDAOENin: in Std_logic; I2C2SCLOout: out Std_logic; + I2C2SCLOin: in Std_logic; I2C2SCLOENout: out Std_logic; + I2C2SCLOENin: in Std_logic; I2C2SDAOout: out Std_logic; + I2C2SDAOin: in Std_logic; I2C2SDAOENout: out Std_logic; + I2C2SDAOENin: in Std_logic; I2C1IRQOout: out Std_logic; + I2C1IRQOin: in Std_logic; I2C2IRQOout: out Std_logic; + I2C2IRQOin: in Std_logic; SPISCKOout: out Std_logic; + SPISCKOin: in Std_logic; SPISCKENout: out Std_logic; + SPISCKENin: in Std_logic; SPIMISOOout: out Std_logic; + SPIMISOOin: in Std_logic; SPIMISOENout: out Std_logic; + SPIMISOENin: in Std_logic; SPIMOSIOout: out Std_logic; + SPIMOSIOin: in Std_logic; SPIMOSIENout: out Std_logic; + SPIMOSIENin: in Std_logic; SPIMCSN0out: out Std_logic; + SPIMCSN0in: in Std_logic; SPIMCSN1out: out Std_logic; + SPIMCSN1in: in Std_logic; SPIMCSN2out: out Std_logic; + SPIMCSN2in: in Std_logic; SPIMCSN3out: out Std_logic; + SPIMCSN3in: in Std_logic; SPIMCSN4out: out Std_logic; + SPIMCSN4in: in Std_logic; SPIMCSN5out: out Std_logic; + SPIMCSN5in: in Std_logic; SPIMCSN6out: out Std_logic; + SPIMCSN6in: in Std_logic; SPIMCSN7out: out Std_logic; + SPIMCSN7in: in Std_logic; SPICSNENout: out Std_logic; + SPICSNENin: in Std_logic; SPIIRQOout: out Std_logic; + SPIIRQOin: in Std_logic; TCINTout: out Std_logic; + TCINTin: in Std_logic; TCOCout: out Std_logic; TCOCin: in Std_logic; + WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic; + CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic; + CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic); + + ATTRIBUTE Vital_Level0 OF EFB_Buffer_Block : ENTITY IS TRUE; + + end EFB_Buffer_Block; + + architecture Structure of EFB_Buffer_Block is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal WBCLKIin_ipd : std_logic := 'X'; + signal WBCLKIin_dly : std_logic := 'X'; + signal WBCLKIout_out : std_logic := 'X'; + signal WBRSTIin_ipd : std_logic := 'X'; + signal WBRSTIin_dly : std_logic := 'X'; + signal WBRSTIout_out : std_logic := 'X'; + signal WBCYCIin_ipd : std_logic := 'X'; + signal WBCYCIin_dly : std_logic := 'X'; + signal WBCYCIout_out : std_logic := 'X'; + signal WBSTBIin_ipd : std_logic := 'X'; + signal WBSTBIin_dly : std_logic := 'X'; + signal WBSTBIout_out : std_logic := 'X'; + signal WBWEIin_ipd : std_logic := 'X'; + signal WBWEIin_dly : std_logic := 'X'; + signal WBWEIout_out : std_logic := 'X'; + signal WBADRI7in_ipd : std_logic := 'X'; + signal WBADRI7in_dly : std_logic := 'X'; + signal WBADRI7out_out : std_logic := 'X'; + signal WBADRI6in_ipd : std_logic := 'X'; + signal WBADRI6in_dly : std_logic := 'X'; + signal WBADRI6out_out : std_logic := 'X'; + signal WBADRI5in_ipd : std_logic := 'X'; + signal WBADRI5in_dly : std_logic := 'X'; + signal WBADRI5out_out : std_logic := 'X'; + signal WBADRI4in_ipd : std_logic := 'X'; + signal WBADRI4in_dly : std_logic := 'X'; + signal WBADRI4out_out : std_logic := 'X'; + signal WBADRI3in_ipd : std_logic := 'X'; + signal WBADRI3in_dly : std_logic := 'X'; + signal WBADRI3out_out : std_logic := 'X'; + signal WBADRI2in_ipd : std_logic := 'X'; + signal WBADRI2in_dly : std_logic := 'X'; + signal WBADRI2out_out : std_logic := 'X'; + signal WBADRI1in_ipd : std_logic := 'X'; + signal WBADRI1in_dly : std_logic := 'X'; + signal WBADRI1out_out : std_logic := 'X'; + signal WBADRI0in_ipd : std_logic := 'X'; + signal WBADRI0in_dly : std_logic := 'X'; + signal WBADRI0out_out : std_logic := 'X'; + signal WBDATI7in_ipd : std_logic := 'X'; + signal WBDATI7in_dly : std_logic := 'X'; + signal WBDATI7out_out : std_logic := 'X'; + signal WBDATI6in_ipd : std_logic := 'X'; + signal WBDATI6in_dly : std_logic := 'X'; + signal WBDATI6out_out : std_logic := 'X'; + signal WBDATI5in_ipd : std_logic := 'X'; + signal WBDATI5in_dly : std_logic := 'X'; + signal WBDATI5out_out : std_logic := 'X'; + signal WBDATI4in_ipd : std_logic := 'X'; + signal WBDATI4in_dly : std_logic := 'X'; + signal WBDATI4out_out : std_logic := 'X'; + signal WBDATI3in_ipd : std_logic := 'X'; + signal WBDATI3in_dly : std_logic := 'X'; + signal WBDATI3out_out : std_logic := 'X'; + signal WBDATI2in_ipd : std_logic := 'X'; + signal WBDATI2in_dly : std_logic := 'X'; + signal WBDATI2out_out : std_logic := 'X'; + signal WBDATI1in_ipd : std_logic := 'X'; + signal WBDATI1in_dly : std_logic := 'X'; + signal WBDATI1out_out : std_logic := 'X'; + signal WBDATI0in_ipd : std_logic := 'X'; + signal WBDATI0in_dly : std_logic := 'X'; + signal WBDATI0out_out : std_logic := 'X'; + signal PLL0DATI7in_ipd : std_logic := 'X'; + signal PLL0DATI7out_out : std_logic := 'X'; + signal PLL0DATI6in_ipd : std_logic := 'X'; + signal PLL0DATI6out_out : std_logic := 'X'; + signal PLL0DATI5in_ipd : std_logic := 'X'; + signal PLL0DATI5out_out : std_logic := 'X'; + signal PLL0DATI4in_ipd : std_logic := 'X'; + signal PLL0DATI4out_out : std_logic := 'X'; + signal PLL0DATI3in_ipd : std_logic := 'X'; + signal PLL0DATI3out_out : std_logic := 'X'; + signal PLL0DATI2in_ipd : std_logic := 'X'; + signal PLL0DATI2out_out : std_logic := 'X'; + signal PLL0DATI1in_ipd : std_logic := 'X'; + signal PLL0DATI1out_out : std_logic := 'X'; + signal PLL0DATI0in_ipd : std_logic := 'X'; + signal PLL0DATI0out_out : std_logic := 'X'; + signal PLL0ACKIin_ipd : std_logic := 'X'; + signal PLL0ACKIout_out : std_logic := 'X'; + signal PLL1DATI7in_ipd : std_logic := 'X'; + signal PLL1DATI7out_out : std_logic := 'X'; + signal PLL1DATI6in_ipd : std_logic := 'X'; + signal PLL1DATI6out_out : std_logic := 'X'; + signal PLL1DATI5in_ipd : std_logic := 'X'; + signal PLL1DATI5out_out : std_logic := 'X'; + signal PLL1DATI4in_ipd : std_logic := 'X'; + signal PLL1DATI4out_out : std_logic := 'X'; + signal PLL1DATI3in_ipd : std_logic := 'X'; + signal PLL1DATI3out_out : std_logic := 'X'; + signal PLL1DATI2in_ipd : std_logic := 'X'; + signal PLL1DATI2out_out : std_logic := 'X'; + signal PLL1DATI1in_ipd : std_logic := 'X'; + signal PLL1DATI1out_out : std_logic := 'X'; + signal PLL1DATI0in_ipd : std_logic := 'X'; + signal PLL1DATI0out_out : std_logic := 'X'; + signal PLL1ACKIin_ipd : std_logic := 'X'; + signal PLL1ACKIout_out : std_logic := 'X'; + signal I2C1SCLIin_ipd : std_logic := 'X'; + signal I2C1SCLIout_out : std_logic := 'X'; + signal I2C1SDAIin_ipd : std_logic := 'X'; + signal I2C1SDAIout_out : std_logic := 'X'; + signal I2C2SCLIin_ipd : std_logic := 'X'; + signal I2C2SCLIout_out : std_logic := 'X'; + signal I2C2SDAIin_ipd : std_logic := 'X'; + signal I2C2SDAIout_out : std_logic := 'X'; + signal SPISCKIin_ipd : std_logic := 'X'; + signal SPISCKIout_out : std_logic := 'X'; + signal SPIMISOIin_ipd : std_logic := 'X'; + signal SPIMISOIout_out : std_logic := 'X'; + signal SPIMOSIIin_ipd : std_logic := 'X'; + signal SPIMOSIIout_out : std_logic := 'X'; + signal SPISCSNin_ipd : std_logic := 'X'; + signal SPISCSNout_out : std_logic := 'X'; + signal TCCLKIin_ipd : std_logic := 'X'; + signal TCCLKIout_out : std_logic := 'X'; + signal TCRSTNin_ipd : std_logic := 'X'; + signal TCRSTNout_out : std_logic := 'X'; + signal TCICin_ipd : std_logic := 'X'; + signal TCICout_out : std_logic := 'X'; + signal UFMSNin_ipd : std_logic := 'X'; + signal UFMSNout_out : std_logic := 'X'; + signal WBDATO7out_out : std_logic := 'X'; + signal WBDATO7in_ipd : std_logic := 'X'; + signal WBDATO6out_out : std_logic := 'X'; + signal WBDATO6in_ipd : std_logic := 'X'; + signal WBDATO5out_out : std_logic := 'X'; + signal WBDATO5in_ipd : std_logic := 'X'; + signal WBDATO4out_out : std_logic := 'X'; + signal WBDATO4in_ipd : std_logic := 'X'; + signal WBDATO3out_out : std_logic := 'X'; + signal WBDATO3in_ipd : std_logic := 'X'; + signal WBDATO2out_out : std_logic := 'X'; + signal WBDATO2in_ipd : std_logic := 'X'; + signal WBDATO1out_out : std_logic := 'X'; + signal WBDATO1in_ipd : std_logic := 'X'; + signal WBDATO0out_out : std_logic := 'X'; + signal WBDATO0in_ipd : std_logic := 'X'; + signal WBACKOout_out : std_logic := 'X'; + signal WBACKOin_ipd : std_logic := 'X'; + signal PLLCLKOout_out : std_logic := 'X'; + signal PLLCLKOin_ipd : std_logic := 'X'; + signal PLLRSTOout_out : std_logic := 'X'; + signal PLLRSTOin_ipd : std_logic := 'X'; + signal PLL0STBOout_out : std_logic := 'X'; + signal PLL0STBOin_ipd : std_logic := 'X'; + signal PLL1STBOout_out : std_logic := 'X'; + signal PLL1STBOin_ipd : std_logic := 'X'; + signal PLLWEOout_out : std_logic := 'X'; + signal PLLWEOin_ipd : std_logic := 'X'; + signal PLLADRO4out_out : std_logic := 'X'; + signal PLLADRO4in_ipd : std_logic := 'X'; + signal PLLADRO3out_out : std_logic := 'X'; + signal PLLADRO3in_ipd : std_logic := 'X'; + signal PLLADRO2out_out : std_logic := 'X'; + signal PLLADRO2in_ipd : std_logic := 'X'; + signal PLLADRO1out_out : std_logic := 'X'; + signal PLLADRO1in_ipd : std_logic := 'X'; + signal PLLADRO0out_out : std_logic := 'X'; + signal PLLADRO0in_ipd : std_logic := 'X'; + signal PLLDATO7out_out : std_logic := 'X'; + signal PLLDATO7in_ipd : std_logic := 'X'; + signal PLLDATO6out_out : std_logic := 'X'; + signal PLLDATO6in_ipd : std_logic := 'X'; + signal PLLDATO5out_out : std_logic := 'X'; + signal PLLDATO5in_ipd : std_logic := 'X'; + signal PLLDATO4out_out : std_logic := 'X'; + signal PLLDATO4in_ipd : std_logic := 'X'; + signal PLLDATO3out_out : std_logic := 'X'; + signal PLLDATO3in_ipd : std_logic := 'X'; + signal PLLDATO2out_out : std_logic := 'X'; + signal PLLDATO2in_ipd : std_logic := 'X'; + signal PLLDATO1out_out : std_logic := 'X'; + signal PLLDATO1in_ipd : std_logic := 'X'; + signal PLLDATO0out_out : std_logic := 'X'; + signal PLLDATO0in_ipd : std_logic := 'X'; + signal I2C1SCLOout_out : std_logic := 'X'; + signal I2C1SCLOin_ipd : std_logic := 'X'; + signal I2C1SCLOENout_out : std_logic := 'X'; + signal I2C1SCLOENin_ipd : std_logic := 'X'; + signal I2C1SDAOout_out : std_logic := 'X'; + signal I2C1SDAOin_ipd : std_logic := 'X'; + signal I2C1SDAOENout_out : std_logic := 'X'; + signal I2C1SDAOENin_ipd : std_logic := 'X'; + signal I2C2SCLOout_out : std_logic := 'X'; + signal I2C2SCLOin_ipd : std_logic := 'X'; + signal I2C2SCLOENout_out : std_logic := 'X'; + signal I2C2SCLOENin_ipd : std_logic := 'X'; + signal I2C2SDAOout_out : std_logic := 'X'; + signal I2C2SDAOin_ipd : std_logic := 'X'; + signal I2C2SDAOENout_out : std_logic := 'X'; + signal I2C2SDAOENin_ipd : std_logic := 'X'; + signal I2C1IRQOout_out : std_logic := 'X'; + signal I2C1IRQOin_ipd : std_logic := 'X'; + signal I2C2IRQOout_out : std_logic := 'X'; + signal I2C2IRQOin_ipd : std_logic := 'X'; + signal SPISCKOout_out : std_logic := 'X'; + signal SPISCKOin_ipd : std_logic := 'X'; + signal SPISCKENout_out : std_logic := 'X'; + signal SPISCKENin_ipd : std_logic := 'X'; + signal SPIMISOOout_out : std_logic := 'X'; + signal SPIMISOOin_ipd : std_logic := 'X'; + signal SPIMISOENout_out : std_logic := 'X'; + signal SPIMISOENin_ipd : std_logic := 'X'; + signal SPIMOSIOout_out : std_logic := 'X'; + signal SPIMOSIOin_ipd : std_logic := 'X'; + signal SPIMOSIENout_out : std_logic := 'X'; + signal SPIMOSIENin_ipd : std_logic := 'X'; + signal SPIMCSN0out_out : std_logic := 'X'; + signal SPIMCSN0in_ipd : std_logic := 'X'; + signal SPIMCSN1out_out : std_logic := 'X'; + signal SPIMCSN1in_ipd : std_logic := 'X'; + signal SPIMCSN2out_out : std_logic := 'X'; + signal SPIMCSN2in_ipd : std_logic := 'X'; + signal SPIMCSN3out_out : std_logic := 'X'; + signal SPIMCSN3in_ipd : std_logic := 'X'; + signal SPIMCSN4out_out : std_logic := 'X'; + signal SPIMCSN4in_ipd : std_logic := 'X'; + signal SPIMCSN5out_out : std_logic := 'X'; + signal SPIMCSN5in_ipd : std_logic := 'X'; + signal SPIMCSN6out_out : std_logic := 'X'; + signal SPIMCSN6in_ipd : std_logic := 'X'; + signal SPIMCSN7out_out : std_logic := 'X'; + signal SPIMCSN7in_ipd : std_logic := 'X'; + signal SPICSNENout_out : std_logic := 'X'; + signal SPICSNENin_ipd : std_logic := 'X'; + signal SPIIRQOout_out : std_logic := 'X'; + signal SPIIRQOin_ipd : std_logic := 'X'; + signal TCINTout_out : std_logic := 'X'; + signal TCINTin_ipd : std_logic := 'X'; + signal TCOCout_out : std_logic := 'X'; + signal TCOCin_ipd : std_logic := 'X'; + signal WBCUFMIRQout_out : std_logic := 'X'; + signal WBCUFMIRQin_ipd : std_logic := 'X'; + signal CFGWAKEout_out : std_logic := 'X'; + signal CFGWAKEin_ipd : std_logic := 'X'; + signal CFGSTDBYout_out : std_logic := 'X'; + signal CFGSTDBYin_ipd : std_logic := 'X'; + + begin + WBCLKI_buf: BUFBA + port map (A=>WBCLKIin_dly, Z=>WBCLKIout_out); + WBRSTI_buf: BUFBA + port map (A=>WBRSTIin_dly, Z=>WBRSTIout_out); + WBCYCI_buf: BUFBA + port map (A=>WBCYCIin_dly, Z=>WBCYCIout_out); + WBSTBI_buf: BUFBA + port map (A=>WBSTBIin_dly, Z=>WBSTBIout_out); + WBWEI_buf: BUFBA + port map (A=>WBWEIin_dly, Z=>WBWEIout_out); + WBADRI7_buf: BUFBA + port map (A=>WBADRI7in_dly, Z=>WBADRI7out_out); + WBADRI6_buf: BUFBA + port map (A=>WBADRI6in_dly, Z=>WBADRI6out_out); + WBADRI5_buf: BUFBA + port map (A=>WBADRI5in_dly, Z=>WBADRI5out_out); + WBADRI4_buf: BUFBA + port map (A=>WBADRI4in_dly, Z=>WBADRI4out_out); + WBADRI3_buf: BUFBA + port map (A=>WBADRI3in_dly, Z=>WBADRI3out_out); + WBADRI2_buf: BUFBA + port map (A=>WBADRI2in_dly, Z=>WBADRI2out_out); + WBADRI1_buf: BUFBA + port map (A=>WBADRI1in_dly, Z=>WBADRI1out_out); + WBADRI0_buf: BUFBA + port map (A=>WBADRI0in_dly, Z=>WBADRI0out_out); + WBDATI7_buf: BUFBA + port map (A=>WBDATI7in_dly, Z=>WBDATI7out_out); + WBDATI6_buf: BUFBA + port map (A=>WBDATI6in_dly, Z=>WBDATI6out_out); + WBDATI5_buf: BUFBA + port map (A=>WBDATI5in_dly, Z=>WBDATI5out_out); + WBDATI4_buf: BUFBA + port map (A=>WBDATI4in_dly, Z=>WBDATI4out_out); + WBDATI3_buf: BUFBA + port map (A=>WBDATI3in_dly, Z=>WBDATI3out_out); + WBDATI2_buf: BUFBA + port map (A=>WBDATI2in_dly, Z=>WBDATI2out_out); + WBDATI1_buf: BUFBA + port map (A=>WBDATI1in_dly, Z=>WBDATI1out_out); + WBDATI0_buf: BUFBA + port map (A=>WBDATI0in_dly, Z=>WBDATI0out_out); + PLL0DATI7_buf: BUFBA + port map (A=>PLL0DATI7in_ipd, Z=>PLL0DATI7out_out); + PLL0DATI6_buf: BUFBA + port map (A=>PLL0DATI6in_ipd, Z=>PLL0DATI6out_out); + PLL0DATI5_buf: BUFBA + port map (A=>PLL0DATI5in_ipd, Z=>PLL0DATI5out_out); + PLL0DATI4_buf: BUFBA + port map (A=>PLL0DATI4in_ipd, Z=>PLL0DATI4out_out); + PLL0DATI3_buf: BUFBA + port map (A=>PLL0DATI3in_ipd, Z=>PLL0DATI3out_out); + PLL0DATI2_buf: BUFBA + port map (A=>PLL0DATI2in_ipd, Z=>PLL0DATI2out_out); + PLL0DATI1_buf: BUFBA + port map (A=>PLL0DATI1in_ipd, Z=>PLL0DATI1out_out); + PLL0DATI0_buf: BUFBA + port map (A=>PLL0DATI0in_ipd, Z=>PLL0DATI0out_out); + PLL0ACKI_buf: BUFBA + port map (A=>PLL0ACKIin_ipd, Z=>PLL0ACKIout_out); + PLL1DATI7_buf: BUFBA + port map (A=>PLL1DATI7in_ipd, Z=>PLL1DATI7out_out); + PLL1DATI6_buf: BUFBA + port map (A=>PLL1DATI6in_ipd, Z=>PLL1DATI6out_out); + PLL1DATI5_buf: BUFBA + port map (A=>PLL1DATI5in_ipd, Z=>PLL1DATI5out_out); + PLL1DATI4_buf: BUFBA + port map (A=>PLL1DATI4in_ipd, Z=>PLL1DATI4out_out); + PLL1DATI3_buf: BUFBA + port map (A=>PLL1DATI3in_ipd, Z=>PLL1DATI3out_out); + PLL1DATI2_buf: BUFBA + port map (A=>PLL1DATI2in_ipd, Z=>PLL1DATI2out_out); + PLL1DATI1_buf: BUFBA + port map (A=>PLL1DATI1in_ipd, Z=>PLL1DATI1out_out); + PLL1DATI0_buf: BUFBA + port map (A=>PLL1DATI0in_ipd, Z=>PLL1DATI0out_out); + PLL1ACKI_buf: BUFBA + port map (A=>PLL1ACKIin_ipd, Z=>PLL1ACKIout_out); + I2C1SCLI_buf: BUFBA + port map (A=>I2C1SCLIin_ipd, Z=>I2C1SCLIout_out); + I2C1SDAI_buf: BUFBA + port map (A=>I2C1SDAIin_ipd, Z=>I2C1SDAIout_out); + I2C2SCLI_buf: BUFBA + port map (A=>I2C2SCLIin_ipd, Z=>I2C2SCLIout_out); + I2C2SDAI_buf: BUFBA + port map (A=>I2C2SDAIin_ipd, Z=>I2C2SDAIout_out); + SPISCKI_buf: BUFBA + port map (A=>SPISCKIin_ipd, Z=>SPISCKIout_out); + SPIMISOI_buf: BUFBA + port map (A=>SPIMISOIin_ipd, Z=>SPIMISOIout_out); + SPIMOSII_buf: BUFBA + port map (A=>SPIMOSIIin_ipd, Z=>SPIMOSIIout_out); + SPISCSN_buf: BUFBA + port map (A=>SPISCSNin_ipd, Z=>SPISCSNout_out); + TCCLKI_buf: BUFBA + port map (A=>TCCLKIin_ipd, Z=>TCCLKIout_out); + TCRSTN_buf: BUFBA + port map (A=>TCRSTNin_ipd, Z=>TCRSTNout_out); + TCIC_buf: BUFBA + port map (A=>TCICin_ipd, Z=>TCICout_out); + UFMSN_buf: BUFBA + port map (A=>UFMSNin_ipd, Z=>UFMSNout_out); + WBDATO7_buf: BUFBA + port map (A=>WBDATO7in_ipd, Z=>WBDATO7out_out); + WBDATO6_buf: BUFBA + port map (A=>WBDATO6in_ipd, Z=>WBDATO6out_out); + WBDATO5_buf: BUFBA + port map (A=>WBDATO5in_ipd, Z=>WBDATO5out_out); + WBDATO4_buf: BUFBA + port map (A=>WBDATO4in_ipd, Z=>WBDATO4out_out); + WBDATO3_buf: BUFBA + port map (A=>WBDATO3in_ipd, Z=>WBDATO3out_out); + WBDATO2_buf: BUFBA + port map (A=>WBDATO2in_ipd, Z=>WBDATO2out_out); + WBDATO1_buf: BUFBA + port map (A=>WBDATO1in_ipd, Z=>WBDATO1out_out); + WBDATO0_buf: BUFBA + port map (A=>WBDATO0in_ipd, Z=>WBDATO0out_out); + WBACKO_buf: BUFBA + port map (A=>WBACKOin_ipd, Z=>WBACKOout_out); + PLLCLKO_buf: BUFBA + port map (A=>PLLCLKOin_ipd, Z=>PLLCLKOout_out); + PLLRSTO_buf: BUFBA + port map (A=>PLLRSTOin_ipd, Z=>PLLRSTOout_out); + PLL0STBO_buf: BUFBA + port map (A=>PLL0STBOin_ipd, Z=>PLL0STBOout_out); + PLL1STBO_buf: BUFBA + port map (A=>PLL1STBOin_ipd, Z=>PLL1STBOout_out); + PLLWEO_buf: BUFBA + port map (A=>PLLWEOin_ipd, Z=>PLLWEOout_out); + PLLADRO4_buf: BUFBA + port map (A=>PLLADRO4in_ipd, Z=>PLLADRO4out_out); + PLLADRO3_buf: BUFBA + port map (A=>PLLADRO3in_ipd, Z=>PLLADRO3out_out); + PLLADRO2_buf: BUFBA + port map (A=>PLLADRO2in_ipd, Z=>PLLADRO2out_out); + PLLADRO1_buf: BUFBA + port map (A=>PLLADRO1in_ipd, Z=>PLLADRO1out_out); + PLLADRO0_buf: BUFBA + port map (A=>PLLADRO0in_ipd, Z=>PLLADRO0out_out); + PLLDATO7_buf: BUFBA + port map (A=>PLLDATO7in_ipd, Z=>PLLDATO7out_out); + PLLDATO6_buf: BUFBA + port map (A=>PLLDATO6in_ipd, Z=>PLLDATO6out_out); + PLLDATO5_buf: BUFBA + port map (A=>PLLDATO5in_ipd, Z=>PLLDATO5out_out); + PLLDATO4_buf: BUFBA + port map (A=>PLLDATO4in_ipd, Z=>PLLDATO4out_out); + PLLDATO3_buf: BUFBA + port map (A=>PLLDATO3in_ipd, Z=>PLLDATO3out_out); + PLLDATO2_buf: BUFBA + port map (A=>PLLDATO2in_ipd, Z=>PLLDATO2out_out); + PLLDATO1_buf: BUFBA + port map (A=>PLLDATO1in_ipd, Z=>PLLDATO1out_out); + PLLDATO0_buf: BUFBA + port map (A=>PLLDATO0in_ipd, Z=>PLLDATO0out_out); + I2C1SCLO_buf: BUFBA + port map (A=>I2C1SCLOin_ipd, Z=>I2C1SCLOout_out); + I2C1SCLOEN_buf: BUFBA + port map (A=>I2C1SCLOENin_ipd, Z=>I2C1SCLOENout_out); + I2C1SDAO_buf: BUFBA + port map (A=>I2C1SDAOin_ipd, Z=>I2C1SDAOout_out); + I2C1SDAOEN_buf: BUFBA + port map (A=>I2C1SDAOENin_ipd, Z=>I2C1SDAOENout_out); + I2C2SCLO_buf: BUFBA + port map (A=>I2C2SCLOin_ipd, Z=>I2C2SCLOout_out); + I2C2SCLOEN_buf: BUFBA + port map (A=>I2C2SCLOENin_ipd, Z=>I2C2SCLOENout_out); + I2C2SDAO_buf: BUFBA + port map (A=>I2C2SDAOin_ipd, Z=>I2C2SDAOout_out); + I2C2SDAOEN_buf: BUFBA + port map (A=>I2C2SDAOENin_ipd, Z=>I2C2SDAOENout_out); + I2C1IRQO_buf: BUFBA + port map (A=>I2C1IRQOin_ipd, Z=>I2C1IRQOout_out); + I2C2IRQO_buf: BUFBA + port map (A=>I2C2IRQOin_ipd, Z=>I2C2IRQOout_out); + SPISCKO_buf: BUFBA + port map (A=>SPISCKOin_ipd, Z=>SPISCKOout_out); + SPISCKEN_buf: BUFBA + port map (A=>SPISCKENin_ipd, Z=>SPISCKENout_out); + SPIMISOO_buf: BUFBA + port map (A=>SPIMISOOin_ipd, Z=>SPIMISOOout_out); + SPIMISOEN_buf: BUFBA + port map (A=>SPIMISOENin_ipd, Z=>SPIMISOENout_out); + SPIMOSIO_buf: BUFBA + port map (A=>SPIMOSIOin_ipd, Z=>SPIMOSIOout_out); + SPIMOSIEN_buf: BUFBA + port map (A=>SPIMOSIENin_ipd, Z=>SPIMOSIENout_out); + SPIMCSN0_buf: BUFBA + port map (A=>SPIMCSN0in_ipd, Z=>SPIMCSN0out_out); + SPIMCSN1_buf: BUFBA + port map (A=>SPIMCSN1in_ipd, Z=>SPIMCSN1out_out); + SPIMCSN2_buf: BUFBA + port map (A=>SPIMCSN2in_ipd, Z=>SPIMCSN2out_out); + SPIMCSN3_buf: BUFBA + port map (A=>SPIMCSN3in_ipd, Z=>SPIMCSN3out_out); + SPIMCSN4_buf: BUFBA + port map (A=>SPIMCSN4in_ipd, Z=>SPIMCSN4out_out); + SPIMCSN5_buf: BUFBA + port map (A=>SPIMCSN5in_ipd, Z=>SPIMCSN5out_out); + SPIMCSN6_buf: BUFBA + port map (A=>SPIMCSN6in_ipd, Z=>SPIMCSN6out_out); + SPIMCSN7_buf: BUFBA + port map (A=>SPIMCSN7in_ipd, Z=>SPIMCSN7out_out); + SPICSNEN_buf: BUFBA + port map (A=>SPICSNENin_ipd, Z=>SPICSNENout_out); + SPIIRQO_buf: BUFBA + port map (A=>SPIIRQOin_ipd, Z=>SPIIRQOout_out); + TCINT_buf: BUFBA + port map (A=>TCINTin_ipd, Z=>TCINTout_out); + TCOC_buf: BUFBA + port map (A=>TCOCin_ipd, Z=>TCOCout_out); + WBCUFMIRQ_buf: BUFBA + port map (A=>WBCUFMIRQin_ipd, Z=>WBCUFMIRQout_out); + CFGWAKE_buf: BUFBA + port map (A=>CFGWAKEin_ipd, Z=>CFGWAKEout_out); + CFGSTDBY_buf: BUFBA + port map (A=>CFGSTDBYin_ipd, Z=>CFGSTDBYout_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(WBCLKIin_ipd, WBCLKIin, tipd_WBCLKIin); + VitalWireDelay(WBRSTIin_ipd, WBRSTIin, tipd_WBRSTIin); + VitalWireDelay(WBCYCIin_ipd, WBCYCIin, tipd_WBCYCIin); + VitalWireDelay(WBSTBIin_ipd, WBSTBIin, tipd_WBSTBIin); + VitalWireDelay(WBWEIin_ipd, WBWEIin, tipd_WBWEIin); + VitalWireDelay(WBADRI7in_ipd, WBADRI7in, tipd_WBADRI7in); + VitalWireDelay(WBADRI6in_ipd, WBADRI6in, tipd_WBADRI6in); + VitalWireDelay(WBADRI5in_ipd, WBADRI5in, tipd_WBADRI5in); + VitalWireDelay(WBADRI4in_ipd, WBADRI4in, tipd_WBADRI4in); + VitalWireDelay(WBADRI3in_ipd, WBADRI3in, tipd_WBADRI3in); + VitalWireDelay(WBADRI2in_ipd, WBADRI2in, tipd_WBADRI2in); + VitalWireDelay(WBADRI1in_ipd, WBADRI1in, tipd_WBADRI1in); + VitalWireDelay(WBADRI0in_ipd, WBADRI0in, tipd_WBADRI0in); + VitalWireDelay(WBDATI7in_ipd, WBDATI7in, tipd_WBDATI7in); + VitalWireDelay(WBDATI6in_ipd, WBDATI6in, tipd_WBDATI6in); + VitalWireDelay(WBDATI5in_ipd, WBDATI5in, tipd_WBDATI5in); + VitalWireDelay(WBDATI4in_ipd, WBDATI4in, tipd_WBDATI4in); + VitalWireDelay(WBDATI3in_ipd, WBDATI3in, tipd_WBDATI3in); + VitalWireDelay(WBDATI2in_ipd, WBDATI2in, tipd_WBDATI2in); + VitalWireDelay(WBDATI1in_ipd, WBDATI1in, tipd_WBDATI1in); + VitalWireDelay(WBDATI0in_ipd, WBDATI0in, tipd_WBDATI0in); + VitalWireDelay(PLL0DATI7in_ipd, PLL0DATI7in, tipd_PLL0DATI7in); + VitalWireDelay(PLL0DATI6in_ipd, PLL0DATI6in, tipd_PLL0DATI6in); + VitalWireDelay(PLL0DATI5in_ipd, PLL0DATI5in, tipd_PLL0DATI5in); + VitalWireDelay(PLL0DATI4in_ipd, PLL0DATI4in, tipd_PLL0DATI4in); + VitalWireDelay(PLL0DATI3in_ipd, PLL0DATI3in, tipd_PLL0DATI3in); + VitalWireDelay(PLL0DATI2in_ipd, PLL0DATI2in, tipd_PLL0DATI2in); + VitalWireDelay(PLL0DATI1in_ipd, PLL0DATI1in, tipd_PLL0DATI1in); + VitalWireDelay(PLL0DATI0in_ipd, PLL0DATI0in, tipd_PLL0DATI0in); + VitalWireDelay(PLL0ACKIin_ipd, PLL0ACKIin, tipd_PLL0ACKIin); + VitalWireDelay(PLL1DATI7in_ipd, PLL1DATI7in, tipd_PLL1DATI7in); + VitalWireDelay(PLL1DATI6in_ipd, PLL1DATI6in, tipd_PLL1DATI6in); + VitalWireDelay(PLL1DATI5in_ipd, PLL1DATI5in, tipd_PLL1DATI5in); + VitalWireDelay(PLL1DATI4in_ipd, PLL1DATI4in, tipd_PLL1DATI4in); + VitalWireDelay(PLL1DATI3in_ipd, PLL1DATI3in, tipd_PLL1DATI3in); + VitalWireDelay(PLL1DATI2in_ipd, PLL1DATI2in, tipd_PLL1DATI2in); + VitalWireDelay(PLL1DATI1in_ipd, PLL1DATI1in, tipd_PLL1DATI1in); + VitalWireDelay(PLL1DATI0in_ipd, PLL1DATI0in, tipd_PLL1DATI0in); + VitalWireDelay(PLL1ACKIin_ipd, PLL1ACKIin, tipd_PLL1ACKIin); + VitalWireDelay(I2C1SCLIin_ipd, I2C1SCLIin, tipd_I2C1SCLIin); + VitalWireDelay(I2C1SDAIin_ipd, I2C1SDAIin, tipd_I2C1SDAIin); + VitalWireDelay(I2C2SCLIin_ipd, I2C2SCLIin, tipd_I2C2SCLIin); + VitalWireDelay(I2C2SDAIin_ipd, I2C2SDAIin, tipd_I2C2SDAIin); + VitalWireDelay(SPISCKIin_ipd, SPISCKIin, tipd_SPISCKIin); + VitalWireDelay(SPIMISOIin_ipd, SPIMISOIin, tipd_SPIMISOIin); + VitalWireDelay(SPIMOSIIin_ipd, SPIMOSIIin, tipd_SPIMOSIIin); + VitalWireDelay(SPISCSNin_ipd, SPISCSNin, tipd_SPISCSNin); + VitalWireDelay(TCCLKIin_ipd, TCCLKIin, tipd_TCCLKIin); + VitalWireDelay(TCRSTNin_ipd, TCRSTNin, tipd_TCRSTNin); + VitalWireDelay(TCICin_ipd, TCICin, tipd_TCICin); + VitalWireDelay(UFMSNin_ipd, UFMSNin, tipd_UFMSNin); + VitalWireDelay(WBDATO7in_ipd, WBDATO7in, tipd_WBDATO7in); + VitalWireDelay(WBDATO6in_ipd, WBDATO6in, tipd_WBDATO6in); + VitalWireDelay(WBDATO5in_ipd, WBDATO5in, tipd_WBDATO5in); + VitalWireDelay(WBDATO4in_ipd, WBDATO4in, tipd_WBDATO4in); + VitalWireDelay(WBDATO3in_ipd, WBDATO3in, tipd_WBDATO3in); + VitalWireDelay(WBDATO2in_ipd, WBDATO2in, tipd_WBDATO2in); + VitalWireDelay(WBDATO1in_ipd, WBDATO1in, tipd_WBDATO1in); + VitalWireDelay(WBDATO0in_ipd, WBDATO0in, tipd_WBDATO0in); + VitalWireDelay(WBACKOin_ipd, WBACKOin, tipd_WBACKOin); + VitalWireDelay(PLLCLKOin_ipd, PLLCLKOin, tipd_PLLCLKOin); + VitalWireDelay(PLLRSTOin_ipd, PLLRSTOin, tipd_PLLRSTOin); + VitalWireDelay(PLL0STBOin_ipd, PLL0STBOin, tipd_PLL0STBOin); + VitalWireDelay(PLL1STBOin_ipd, PLL1STBOin, tipd_PLL1STBOin); + VitalWireDelay(PLLWEOin_ipd, PLLWEOin, tipd_PLLWEOin); + VitalWireDelay(PLLADRO4in_ipd, PLLADRO4in, tipd_PLLADRO4in); + VitalWireDelay(PLLADRO3in_ipd, PLLADRO3in, tipd_PLLADRO3in); + VitalWireDelay(PLLADRO2in_ipd, PLLADRO2in, tipd_PLLADRO2in); + VitalWireDelay(PLLADRO1in_ipd, PLLADRO1in, tipd_PLLADRO1in); + VitalWireDelay(PLLADRO0in_ipd, PLLADRO0in, tipd_PLLADRO0in); + VitalWireDelay(PLLDATO7in_ipd, PLLDATO7in, tipd_PLLDATO7in); + VitalWireDelay(PLLDATO6in_ipd, PLLDATO6in, tipd_PLLDATO6in); + VitalWireDelay(PLLDATO5in_ipd, PLLDATO5in, tipd_PLLDATO5in); + VitalWireDelay(PLLDATO4in_ipd, PLLDATO4in, tipd_PLLDATO4in); + VitalWireDelay(PLLDATO3in_ipd, PLLDATO3in, tipd_PLLDATO3in); + VitalWireDelay(PLLDATO2in_ipd, PLLDATO2in, tipd_PLLDATO2in); + VitalWireDelay(PLLDATO1in_ipd, PLLDATO1in, tipd_PLLDATO1in); + VitalWireDelay(PLLDATO0in_ipd, PLLDATO0in, tipd_PLLDATO0in); + VitalWireDelay(I2C1SCLOin_ipd, I2C1SCLOin, tipd_I2C1SCLOin); + VitalWireDelay(I2C1SCLOENin_ipd, I2C1SCLOENin, tipd_I2C1SCLOENin); + VitalWireDelay(I2C1SDAOin_ipd, I2C1SDAOin, tipd_I2C1SDAOin); + VitalWireDelay(I2C1SDAOENin_ipd, I2C1SDAOENin, tipd_I2C1SDAOENin); + VitalWireDelay(I2C2SCLOin_ipd, I2C2SCLOin, tipd_I2C2SCLOin); + VitalWireDelay(I2C2SCLOENin_ipd, I2C2SCLOENin, tipd_I2C2SCLOENin); + VitalWireDelay(I2C2SDAOin_ipd, I2C2SDAOin, tipd_I2C2SDAOin); + VitalWireDelay(I2C2SDAOENin_ipd, I2C2SDAOENin, tipd_I2C2SDAOENin); + VitalWireDelay(I2C1IRQOin_ipd, I2C1IRQOin, tipd_I2C1IRQOin); + VitalWireDelay(I2C2IRQOin_ipd, I2C2IRQOin, tipd_I2C2IRQOin); + VitalWireDelay(SPISCKOin_ipd, SPISCKOin, tipd_SPISCKOin); + VitalWireDelay(SPISCKENin_ipd, SPISCKENin, tipd_SPISCKENin); + VitalWireDelay(SPIMISOOin_ipd, SPIMISOOin, tipd_SPIMISOOin); + VitalWireDelay(SPIMISOENin_ipd, SPIMISOENin, tipd_SPIMISOENin); + VitalWireDelay(SPIMOSIOin_ipd, SPIMOSIOin, tipd_SPIMOSIOin); + VitalWireDelay(SPIMOSIENin_ipd, SPIMOSIENin, tipd_SPIMOSIENin); + VitalWireDelay(SPIMCSN0in_ipd, SPIMCSN0in, tipd_SPIMCSN0in); + VitalWireDelay(SPIMCSN1in_ipd, SPIMCSN1in, tipd_SPIMCSN1in); + VitalWireDelay(SPIMCSN2in_ipd, SPIMCSN2in, tipd_SPIMCSN2in); + VitalWireDelay(SPIMCSN3in_ipd, SPIMCSN3in, tipd_SPIMCSN3in); + VitalWireDelay(SPIMCSN4in_ipd, SPIMCSN4in, tipd_SPIMCSN4in); + VitalWireDelay(SPIMCSN5in_ipd, SPIMCSN5in, tipd_SPIMCSN5in); + VitalWireDelay(SPIMCSN6in_ipd, SPIMCSN6in, tipd_SPIMCSN6in); + VitalWireDelay(SPIMCSN7in_ipd, SPIMCSN7in, tipd_SPIMCSN7in); + VitalWireDelay(SPICSNENin_ipd, SPICSNENin, tipd_SPICSNENin); + VitalWireDelay(SPIIRQOin_ipd, SPIIRQOin, tipd_SPIIRQOin); + VitalWireDelay(TCINTin_ipd, TCINTin, tipd_TCINTin); + VitalWireDelay(TCOCin_ipd, TCOCin, tipd_TCOCin); + VitalWireDelay(WBCUFMIRQin_ipd, WBCUFMIRQin, tipd_WBCUFMIRQin); + VitalWireDelay(CFGWAKEin_ipd, CFGWAKEin, tipd_CFGWAKEin); + VitalWireDelay(CFGSTDBYin_ipd, CFGSTDBYin, tipd_CFGSTDBYin); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(WBCLKIin_dly, WBCLKIin_ipd, ticd_WBCLKIin); + VitalSignalDelay(WBRSTIin_dly, WBRSTIin_ipd, tisd_WBRSTIin_WBCLKIin); + VitalSignalDelay(WBCYCIin_dly, WBCYCIin_ipd, tisd_WBCYCIin_WBCLKIin); + VitalSignalDelay(WBSTBIin_dly, WBSTBIin_ipd, tisd_WBSTBIin_WBCLKIin); + VitalSignalDelay(WBWEIin_dly, WBWEIin_ipd, tisd_WBWEIin_WBCLKIin); + VitalSignalDelay(WBADRI7in_dly, WBADRI7in_ipd, tisd_WBADRI7in_WBCLKIin); + VitalSignalDelay(WBADRI6in_dly, WBADRI6in_ipd, tisd_WBADRI6in_WBCLKIin); + VitalSignalDelay(WBADRI5in_dly, WBADRI5in_ipd, tisd_WBADRI5in_WBCLKIin); + VitalSignalDelay(WBADRI4in_dly, WBADRI4in_ipd, tisd_WBADRI4in_WBCLKIin); + VitalSignalDelay(WBADRI3in_dly, WBADRI3in_ipd, tisd_WBADRI3in_WBCLKIin); + VitalSignalDelay(WBADRI2in_dly, WBADRI2in_ipd, tisd_WBADRI2in_WBCLKIin); + VitalSignalDelay(WBADRI1in_dly, WBADRI1in_ipd, tisd_WBADRI1in_WBCLKIin); + VitalSignalDelay(WBADRI0in_dly, WBADRI0in_ipd, tisd_WBADRI0in_WBCLKIin); + VitalSignalDelay(WBDATI7in_dly, WBDATI7in_ipd, tisd_WBDATI7in_WBCLKIin); + VitalSignalDelay(WBDATI6in_dly, WBDATI6in_ipd, tisd_WBDATI6in_WBCLKIin); + VitalSignalDelay(WBDATI5in_dly, WBDATI5in_ipd, tisd_WBDATI5in_WBCLKIin); + VitalSignalDelay(WBDATI4in_dly, WBDATI4in_ipd, tisd_WBDATI4in_WBCLKIin); + VitalSignalDelay(WBDATI3in_dly, WBDATI3in_ipd, tisd_WBDATI3in_WBCLKIin); + VitalSignalDelay(WBDATI2in_dly, WBDATI2in_ipd, tisd_WBDATI2in_WBCLKIin); + VitalSignalDelay(WBDATI1in_dly, WBDATI1in_ipd, tisd_WBDATI1in_WBCLKIin); + VitalSignalDelay(WBDATI0in_dly, WBDATI0in_ipd, tisd_WBDATI0in_WBCLKIin); + END BLOCK; + + VitalBehavior : PROCESS (WBCLKIin_dly, WBCLKIout_out, WBRSTIin_dly, + WBRSTIout_out, WBCYCIin_dly, WBCYCIout_out, WBSTBIin_dly, WBSTBIout_out, + WBWEIin_dly, WBWEIout_out, WBADRI7in_dly, WBADRI7out_out, WBADRI6in_dly, + WBADRI6out_out, WBADRI5in_dly, WBADRI5out_out, WBADRI4in_dly, + WBADRI4out_out, WBADRI3in_dly, WBADRI3out_out, WBADRI2in_dly, + WBADRI2out_out, WBADRI1in_dly, WBADRI1out_out, WBADRI0in_dly, + WBADRI0out_out, WBDATI7in_dly, WBDATI7out_out, WBDATI6in_dly, + WBDATI6out_out, WBDATI5in_dly, WBDATI5out_out, WBDATI4in_dly, + WBDATI4out_out, WBDATI3in_dly, WBDATI3out_out, WBDATI2in_dly, + WBDATI2out_out, WBDATI1in_dly, WBDATI1out_out, WBDATI0in_dly, + WBDATI0out_out, PLL0DATI7in_ipd, PLL0DATI7out_out, PLL0DATI6in_ipd, + PLL0DATI6out_out, PLL0DATI5in_ipd, PLL0DATI5out_out, PLL0DATI4in_ipd, + PLL0DATI4out_out, PLL0DATI3in_ipd, PLL0DATI3out_out, PLL0DATI2in_ipd, + PLL0DATI2out_out, PLL0DATI1in_ipd, PLL0DATI1out_out, PLL0DATI0in_ipd, + PLL0DATI0out_out, PLL0ACKIin_ipd, PLL0ACKIout_out, PLL1DATI7in_ipd, + PLL1DATI7out_out, PLL1DATI6in_ipd, PLL1DATI6out_out, PLL1DATI5in_ipd, + PLL1DATI5out_out, PLL1DATI4in_ipd, PLL1DATI4out_out, PLL1DATI3in_ipd, + PLL1DATI3out_out, PLL1DATI2in_ipd, PLL1DATI2out_out, PLL1DATI1in_ipd, + PLL1DATI1out_out, PLL1DATI0in_ipd, PLL1DATI0out_out, PLL1ACKIin_ipd, + PLL1ACKIout_out, I2C1SCLIin_ipd, I2C1SCLIout_out, I2C1SDAIin_ipd, + I2C1SDAIout_out, I2C2SCLIin_ipd, I2C2SCLIout_out, I2C2SDAIin_ipd, + I2C2SDAIout_out, SPISCKIin_ipd, SPISCKIout_out, SPIMISOIin_ipd, + SPIMISOIout_out, SPIMOSIIin_ipd, SPIMOSIIout_out, SPISCSNin_ipd, + SPISCSNout_out, TCCLKIin_ipd, TCCLKIout_out, TCRSTNin_ipd, TCRSTNout_out, + TCICin_ipd, TCICout_out, UFMSNin_ipd, UFMSNout_out, WBDATO7out_out, + WBDATO7in_ipd, WBDATO6out_out, WBDATO6in_ipd, WBDATO5out_out, + WBDATO5in_ipd, WBDATO4out_out, WBDATO4in_ipd, WBDATO3out_out, + WBDATO3in_ipd, WBDATO2out_out, WBDATO2in_ipd, WBDATO1out_out, + WBDATO1in_ipd, WBDATO0out_out, WBDATO0in_ipd, WBACKOout_out, + WBACKOin_ipd, PLLCLKOout_out, PLLCLKOin_ipd, PLLRSTOout_out, + PLLRSTOin_ipd, PLL0STBOout_out, PLL0STBOin_ipd, PLL1STBOout_out, + PLL1STBOin_ipd, PLLWEOout_out, PLLWEOin_ipd, PLLADRO4out_out, + PLLADRO4in_ipd, PLLADRO3out_out, PLLADRO3in_ipd, PLLADRO2out_out, + PLLADRO2in_ipd, PLLADRO1out_out, PLLADRO1in_ipd, PLLADRO0out_out, + PLLADRO0in_ipd, PLLDATO7out_out, PLLDATO7in_ipd, PLLDATO6out_out, + PLLDATO6in_ipd, PLLDATO5out_out, PLLDATO5in_ipd, PLLDATO4out_out, + PLLDATO4in_ipd, PLLDATO3out_out, PLLDATO3in_ipd, PLLDATO2out_out, + PLLDATO2in_ipd, PLLDATO1out_out, PLLDATO1in_ipd, PLLDATO0out_out, + PLLDATO0in_ipd, I2C1SCLOout_out, I2C1SCLOin_ipd, I2C1SCLOENout_out, + I2C1SCLOENin_ipd, I2C1SDAOout_out, I2C1SDAOin_ipd, I2C1SDAOENout_out, + I2C1SDAOENin_ipd, I2C2SCLOout_out, I2C2SCLOin_ipd, I2C2SCLOENout_out, + I2C2SCLOENin_ipd, I2C2SDAOout_out, I2C2SDAOin_ipd, I2C2SDAOENout_out, + I2C2SDAOENin_ipd, I2C1IRQOout_out, I2C1IRQOin_ipd, I2C2IRQOout_out, + I2C2IRQOin_ipd, SPISCKOout_out, SPISCKOin_ipd, SPISCKENout_out, + SPISCKENin_ipd, SPIMISOOout_out, SPIMISOOin_ipd, SPIMISOENout_out, + SPIMISOENin_ipd, SPIMOSIOout_out, SPIMOSIOin_ipd, SPIMOSIENout_out, + SPIMOSIENin_ipd, SPIMCSN0out_out, SPIMCSN0in_ipd, SPIMCSN1out_out, + SPIMCSN1in_ipd, SPIMCSN2out_out, SPIMCSN2in_ipd, SPIMCSN3out_out, + SPIMCSN3in_ipd, SPIMCSN4out_out, SPIMCSN4in_ipd, SPIMCSN5out_out, + SPIMCSN5in_ipd, SPIMCSN6out_out, SPIMCSN6in_ipd, SPIMCSN7out_out, + SPIMCSN7in_ipd, SPICSNENout_out, SPICSNENin_ipd, SPIIRQOout_out, + SPIIRQOin_ipd, TCINTout_out, TCINTin_ipd, TCOCout_out, TCOCin_ipd, + WBCUFMIRQout_out, WBCUFMIRQin_ipd, CFGWAKEout_out, CFGWAKEin_ipd, + CFGSTDBYout_out, CFGSTDBYin_ipd) + VARIABLE WBDATO1out_zd : std_logic := 'X'; + VARIABLE WBDATO1out_GlitchData : VitalGlitchDataType; + VARIABLE WBDATO0out_zd : std_logic := 'X'; + VARIABLE WBDATO0out_GlitchData : VitalGlitchDataType; + VARIABLE WBACKOout_zd : std_logic := 'X'; + VARIABLE WBACKOout_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_WBRSTIin_WBCLKIin : x01 := '0'; + VARIABLE WBRSTIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBCYCIin_WBCLKIin : x01 := '0'; + VARIABLE WBCYCIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBSTBIin_WBCLKIin : x01 := '0'; + VARIABLE WBSTBIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBWEIin_WBCLKIin : x01 := '0'; + VARIABLE WBWEIin_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI0in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI0in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI1in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI1in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI2in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI2in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI3in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI3in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI4in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI4in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI5in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI5in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI6in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI6in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBADRI7in_WBCLKIin : x01 := '0'; + VARIABLE WBADRI7in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI0in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI0in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI1in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI1in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI2in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI2in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI3in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI3in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI4in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI4in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI5in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI5in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI6in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI6in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBDATI7in_WBCLKIin : x01 := '0'; + VARIABLE WBDATI7in_WBCLKIin_TimingDatash : VitalTimingDataType; + VARIABLE tviol_WBCLKIin_WBCLKIin : x01 := '0'; + VARIABLE periodcheckinfo_WBCLKIin : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => WBRSTIin_dly, + TestSignalName => "WBRSTIin", + TestDelay => tisd_WBRSTIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBRSTIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBRSTIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBRSTIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBRSTIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBRSTIin_WBCLKIin_TimingDatash, + Violation => tviol_WBRSTIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBCYCIin_dly, + TestSignalName => "WBCYCIin", + TestDelay => tisd_WBCYCIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBCYCIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBCYCIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBCYCIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBCYCIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBCYCIin_WBCLKIin_TimingDatash, + Violation => tviol_WBCYCIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBSTBIin_dly, + TestSignalName => "WBSTBIin", + TestDelay => tisd_WBSTBIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBSTBIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBSTBIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBSTBIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBSTBIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBSTBIin_WBCLKIin_TimingDatash, + Violation => tviol_WBSTBIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBWEIin_dly, + TestSignalName => "WBWEIin", + TestDelay => tisd_WBWEIin_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBWEIin_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBWEIin_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBWEIin_WBCLKIin_noedge_posedge, + HoldLow => thold_WBWEIin_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBWEIin_WBCLKIin_TimingDatash, + Violation => tviol_WBWEIin_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI0in_dly, + TestSignalName => "WBADRI0in", + TestDelay => tisd_WBADRI0in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI0in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI0in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI0in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI0in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI0in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI0in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI1in_dly, + TestSignalName => "WBADRI1in", + TestDelay => tisd_WBADRI1in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI1in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI1in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI1in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI1in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI1in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI1in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI2in_dly, + TestSignalName => "WBADRI2in", + TestDelay => tisd_WBADRI2in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI2in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI2in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI2in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI2in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI2in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI2in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI3in_dly, + TestSignalName => "WBADRI3in", + TestDelay => tisd_WBADRI3in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI3in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI3in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI3in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI3in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI3in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI3in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI4in_dly, + TestSignalName => "WBADRI4in", + TestDelay => tisd_WBADRI4in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI4in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI4in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI4in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI4in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI4in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI4in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI5in_dly, + TestSignalName => "WBADRI5in", + TestDelay => tisd_WBADRI5in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI5in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI5in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI5in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI5in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI5in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI5in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI6in_dly, + TestSignalName => "WBADRI6in", + TestDelay => tisd_WBADRI6in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI6in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI6in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI6in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI6in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI6in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI6in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBADRI7in_dly, + TestSignalName => "WBADRI7in", + TestDelay => tisd_WBADRI7in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBADRI7in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBADRI7in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBADRI7in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBADRI7in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBADRI7in_WBCLKIin_TimingDatash, + Violation => tviol_WBADRI7in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI0in_dly, + TestSignalName => "WBDATI0in", + TestDelay => tisd_WBDATI0in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI0in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI0in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI0in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI0in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI0in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI0in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI1in_dly, + TestSignalName => "WBDATI1in", + TestDelay => tisd_WBDATI1in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI1in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI1in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI1in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI1in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI1in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI1in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI2in_dly, + TestSignalName => "WBDATI2in", + TestDelay => tisd_WBDATI2in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI2in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI2in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI2in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI2in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI2in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI2in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI3in_dly, + TestSignalName => "WBDATI3in", + TestDelay => tisd_WBDATI3in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI3in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI3in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI3in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI3in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI3in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI3in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI4in_dly, + TestSignalName => "WBDATI4in", + TestDelay => tisd_WBDATI4in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI4in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI4in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI4in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI4in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI4in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI4in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI5in_dly, + TestSignalName => "WBDATI5in", + TestDelay => tisd_WBDATI5in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI5in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI5in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI5in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI5in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI5in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI5in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI6in_dly, + TestSignalName => "WBDATI6in", + TestDelay => tisd_WBDATI6in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI6in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI6in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI6in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI6in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI6in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI6in_WBCLKIin, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => WBDATI7in_dly, + TestSignalName => "WBDATI7in", + TestDelay => tisd_WBDATI7in_WBCLKIin, + RefSignal => WBCLKIin_dly, + RefSignalName => "WBCLKIin", + RefDelay => ticd_WBCLKIin, + SetupHigh => tsetup_WBDATI7in_WBCLKIin_noedge_posedge, + SetupLow => tsetup_WBDATI7in_WBCLKIin_noedge_posedge, + HoldHigh => thold_WBDATI7in_WBCLKIin_noedge_posedge, + HoldLow => thold_WBDATI7in_WBCLKIin_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => WBDATI7in_WBCLKIin_TimingDatash, + Violation => tviol_WBDATI7in_WBCLKIin, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => WBCLKIin_ipd, + TestSignalName => "WBCLKIin", + Period => tperiod_WBCLKIin, + PulseWidthHigh => tpw_WBCLKIin_posedge, + PulseWidthLow => tpw_WBCLKIin_negedge, + PeriodData => periodcheckinfo_WBCLKIin, + Violation => tviol_WBCLKIin_WBCLKIin, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + WBCLKIout <= WBCLKIout_out; + WBRSTIout <= WBRSTIout_out; + WBCYCIout <= WBCYCIout_out; + WBSTBIout <= WBSTBIout_out; + WBWEIout <= WBWEIout_out; + WBADRI7out <= WBADRI7out_out; + WBADRI6out <= WBADRI6out_out; + WBADRI5out <= WBADRI5out_out; + WBADRI4out <= WBADRI4out_out; + WBADRI3out <= WBADRI3out_out; + WBADRI2out <= WBADRI2out_out; + WBADRI1out <= WBADRI1out_out; + WBADRI0out <= WBADRI0out_out; + WBDATI7out <= WBDATI7out_out; + WBDATI6out <= WBDATI6out_out; + WBDATI5out <= WBDATI5out_out; + WBDATI4out <= WBDATI4out_out; + WBDATI3out <= WBDATI3out_out; + WBDATI2out <= WBDATI2out_out; + WBDATI1out <= WBDATI1out_out; + WBDATI0out <= WBDATI0out_out; + PLL0DATI7out <= PLL0DATI7out_out; + PLL0DATI6out <= PLL0DATI6out_out; + PLL0DATI5out <= PLL0DATI5out_out; + PLL0DATI4out <= PLL0DATI4out_out; + PLL0DATI3out <= PLL0DATI3out_out; + PLL0DATI2out <= PLL0DATI2out_out; + PLL0DATI1out <= PLL0DATI1out_out; + PLL0DATI0out <= PLL0DATI0out_out; + PLL0ACKIout <= PLL0ACKIout_out; + PLL1DATI7out <= PLL1DATI7out_out; + PLL1DATI6out <= PLL1DATI6out_out; + PLL1DATI5out <= PLL1DATI5out_out; + PLL1DATI4out <= PLL1DATI4out_out; + PLL1DATI3out <= PLL1DATI3out_out; + PLL1DATI2out <= PLL1DATI2out_out; + PLL1DATI1out <= PLL1DATI1out_out; + PLL1DATI0out <= PLL1DATI0out_out; + PLL1ACKIout <= PLL1ACKIout_out; + I2C1SCLIout <= I2C1SCLIout_out; + I2C1SDAIout <= I2C1SDAIout_out; + I2C2SCLIout <= I2C2SCLIout_out; + I2C2SDAIout <= I2C2SDAIout_out; + SPISCKIout <= SPISCKIout_out; + SPIMISOIout <= SPIMISOIout_out; + SPIMOSIIout <= SPIMOSIIout_out; + SPISCSNout <= SPISCSNout_out; + TCCLKIout <= TCCLKIout_out; + TCRSTNout <= TCRSTNout_out; + TCICout <= TCICout_out; + UFMSNout <= UFMSNout_out; + WBDATO7out <= WBDATO7out_out; + WBDATO6out <= WBDATO6out_out; + WBDATO5out <= WBDATO5out_out; + WBDATO4out <= WBDATO4out_out; + WBDATO3out <= WBDATO3out_out; + WBDATO2out <= WBDATO2out_out; + WBDATO1out_zd := WBDATO1out_out; + WBDATO0out_zd := WBDATO0out_out; + WBACKOout_zd := WBACKOout_out; + PLLCLKOout <= PLLCLKOout_out; + PLLRSTOout <= PLLRSTOout_out; + PLL0STBOout <= PLL0STBOout_out; + PLL1STBOout <= PLL1STBOout_out; + PLLWEOout <= PLLWEOout_out; + PLLADRO4out <= PLLADRO4out_out; + PLLADRO3out <= PLLADRO3out_out; + PLLADRO2out <= PLLADRO2out_out; + PLLADRO1out <= PLLADRO1out_out; + PLLADRO0out <= PLLADRO0out_out; + PLLDATO7out <= PLLDATO7out_out; + PLLDATO6out <= PLLDATO6out_out; + PLLDATO5out <= PLLDATO5out_out; + PLLDATO4out <= PLLDATO4out_out; + PLLDATO3out <= PLLDATO3out_out; + PLLDATO2out <= PLLDATO2out_out; + PLLDATO1out <= PLLDATO1out_out; + PLLDATO0out <= PLLDATO0out_out; + I2C1SCLOout <= I2C1SCLOout_out; + I2C1SCLOENout <= I2C1SCLOENout_out; + I2C1SDAOout <= I2C1SDAOout_out; + I2C1SDAOENout <= I2C1SDAOENout_out; + I2C2SCLOout <= I2C2SCLOout_out; + I2C2SCLOENout <= I2C2SCLOENout_out; + I2C2SDAOout <= I2C2SDAOout_out; + I2C2SDAOENout <= I2C2SDAOENout_out; + I2C1IRQOout <= I2C1IRQOout_out; + I2C2IRQOout <= I2C2IRQOout_out; + SPISCKOout <= SPISCKOout_out; + SPISCKENout <= SPISCKENout_out; + SPIMISOOout <= SPIMISOOout_out; + SPIMISOENout <= SPIMISOENout_out; + SPIMOSIOout <= SPIMOSIOout_out; + SPIMOSIENout <= SPIMOSIENout_out; + SPIMCSN0out <= SPIMCSN0out_out; + SPIMCSN1out <= SPIMCSN1out_out; + SPIMCSN2out <= SPIMCSN2out_out; + SPIMCSN3out <= SPIMCSN3out_out; + SPIMCSN4out <= SPIMCSN4out_out; + SPIMCSN5out <= SPIMCSN5out_out; + SPIMCSN6out <= SPIMCSN6out_out; + SPIMCSN7out <= SPIMCSN7out_out; + SPICSNENout <= SPICSNENout_out; + SPIIRQOout <= SPIIRQOout_out; + TCINTout <= TCINTout_out; + TCOCout <= TCOCout_out; + WBCUFMIRQout <= WBCUFMIRQout_out; + CFGWAKEout <= CFGWAKEout_out; + CFGSTDBYout <= CFGSTDBYout_out; + + VitalPathDelay01 ( + + OutSignal => WBDATO0out, OutSignalName => "WBDATO0out", OutTemp => WBDATO0out_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBDATO0out, + PathCondition => TRUE)), + GlitchData => WBDATO0out_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + + OutSignal => WBDATO1out, OutSignalName => "WBDATO1out", OutTemp => WBDATO1out_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBDATO1out, + PathCondition => TRUE)), + GlitchData => WBDATO1out_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => WBACKOout, OutSignalName => "WBACKOout", OutTemp => WBACKOout_zd, + Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event, + PathDelay => tpd_WBCLKIin_WBACKOout, + PathCondition => TRUE)), + GlitchData => WBACKOout_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity EFBB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity EFBB is + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic; + WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic; + WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic; + WBDATO0: out Std_logic; WBDATO1: out Std_logic; + WBDATO2: out Std_logic; WBDATO3: out Std_logic; + WBDATO4: out Std_logic; WBDATO5: out Std_logic; + WBDATO6: out Std_logic; WBDATO7: out Std_logic; + WBACKO: out Std_logic; WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic; + CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic; + I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic; + I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic; + I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic; + I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic; + I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic; + I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic; + I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic; + SPISCKI: in Std_logic; SPISCKO: out Std_logic; + SPISCKEN: out Std_logic; SPIMISOI: in Std_logic; + SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic; + SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic; + SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic; + SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic; + SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic; + SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic; + SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic; + SPISCSN: in Std_logic; SPIIRQO: out Std_logic; TCCLKI: in Std_logic; + TCRSTN: in Std_logic; TCIC: in Std_logic; TCINT: out Std_logic; + TCOC: out Std_logic; PLLCLKO: out Std_logic; PLLRSTO: out Std_logic; + PLL0STBO: out Std_logic; PLL1STBO: out Std_logic; + PLLWEO: out Std_logic; PLLADRO0: out Std_logic; + PLLADRO1: out Std_logic; PLLADRO2: out Std_logic; + PLLADRO3: out Std_logic; PLLADRO4: out Std_logic; + PLLDATO0: out Std_logic; PLLDATO1: out Std_logic; + PLLDATO2: out Std_logic; PLLDATO3: out Std_logic; + PLLDATO4: out Std_logic; PLLDATO5: out Std_logic; + PLLDATO6: out Std_logic; PLLDATO7: out Std_logic; + PLL0DATI0: in Std_logic; PLL0DATI1: in Std_logic; + PLL0DATI2: in Std_logic; PLL0DATI3: in Std_logic; + PLL0DATI4: in Std_logic; PLL0DATI5: in Std_logic; + PLL0DATI6: in Std_logic; PLL0DATI7: in Std_logic; + PLL0ACKI: in Std_logic; PLL1DATI0: in Std_logic; + PLL1DATI1: in Std_logic; PLL1DATI2: in Std_logic; + PLL1DATI3: in Std_logic; PLL1DATI4: in Std_logic; + PLL1DATI5: in Std_logic; PLL1DATI6: in Std_logic; + PLL1DATI7: in Std_logic; PLL1ACKI: in Std_logic); + + + + end EFBB; + + architecture Structure of EFBB is + signal WBCLKI_buf: Std_logic; + signal WBRSTI_buf: Std_logic; + signal WBCYCI_buf: Std_logic; + signal WBSTBI_buf: Std_logic; + signal WBWEI_buf: Std_logic; + signal WBADRI7_buf: Std_logic; + signal WBADRI6_buf: Std_logic; + signal WBADRI5_buf: Std_logic; + signal WBADRI4_buf: Std_logic; + signal WBADRI3_buf: Std_logic; + signal WBADRI2_buf: Std_logic; + signal WBADRI1_buf: Std_logic; + signal WBADRI0_buf: Std_logic; + signal WBDATI7_buf: Std_logic; + signal WBDATI6_buf: Std_logic; + signal WBDATI5_buf: Std_logic; + signal WBDATI4_buf: Std_logic; + signal WBDATI3_buf: Std_logic; + signal WBDATI2_buf: Std_logic; + signal WBDATI1_buf: Std_logic; + signal WBDATI0_buf: Std_logic; + signal PLL0DATI7_buf: Std_logic; + signal PLL0DATI6_buf: Std_logic; + signal PLL0DATI5_buf: Std_logic; + signal PLL0DATI4_buf: Std_logic; + signal PLL0DATI3_buf: Std_logic; + signal PLL0DATI2_buf: Std_logic; + signal PLL0DATI1_buf: Std_logic; + signal PLL0DATI0_buf: Std_logic; + signal PLL0ACKI_buf: Std_logic; + signal PLL1DATI7_buf: Std_logic; + signal PLL1DATI6_buf: Std_logic; + signal PLL1DATI5_buf: Std_logic; + signal PLL1DATI4_buf: Std_logic; + signal PLL1DATI3_buf: Std_logic; + signal PLL1DATI2_buf: Std_logic; + signal PLL1DATI1_buf: Std_logic; + signal PLL1DATI0_buf: Std_logic; + signal PLL1ACKI_buf: Std_logic; + signal I2C1SCLI_buf: Std_logic; + signal I2C1SDAI_buf: Std_logic; + signal I2C2SCLI_buf: Std_logic; + signal I2C2SDAI_buf: Std_logic; + signal SPISCKI_buf: Std_logic; + signal SPIMISOI_buf: Std_logic; + signal SPIMOSII_buf: Std_logic; + signal SPISCSN_buf: Std_logic; + signal TCCLKI_buf: Std_logic; + signal TCRSTN_buf: Std_logic; + signal TCIC_buf: Std_logic; + signal UFMSN_buf: Std_logic; + signal WBDATO7_buf: Std_logic; + signal WBDATO6_buf: Std_logic; + signal WBDATO5_buf: Std_logic; + signal WBDATO4_buf: Std_logic; + signal WBDATO3_buf: Std_logic; + signal WBDATO2_buf: Std_logic; + signal WBDATO1_buf: Std_logic; + signal WBDATO0_buf: Std_logic; + signal WBACKO_buf: Std_logic; + signal PLLCLKO_buf: Std_logic; + signal PLLRSTO_buf: Std_logic; + signal PLL0STBO_buf: Std_logic; + signal PLL1STBO_buf: Std_logic; + signal PLLWEO_buf: Std_logic; + signal PLLADRO4_buf: Std_logic; + signal PLLADRO3_buf: Std_logic; + signal PLLADRO2_buf: Std_logic; + signal PLLADRO1_buf: Std_logic; + signal PLLADRO0_buf: Std_logic; + signal PLLDATO7_buf: Std_logic; + signal PLLDATO6_buf: Std_logic; + signal PLLDATO5_buf: Std_logic; + signal PLLDATO4_buf: Std_logic; + signal PLLDATO3_buf: Std_logic; + signal PLLDATO2_buf: Std_logic; + signal PLLDATO1_buf: Std_logic; + signal PLLDATO0_buf: Std_logic; + signal I2C1SCLO_buf: Std_logic; + signal I2C1SCLOEN_buf: Std_logic; + signal I2C1SDAO_buf: Std_logic; + signal I2C1SDAOEN_buf: Std_logic; + signal I2C2SCLO_buf: Std_logic; + signal I2C2SCLOEN_buf: Std_logic; + signal I2C2SDAO_buf: Std_logic; + signal I2C2SDAOEN_buf: Std_logic; + signal I2C1IRQO_buf: Std_logic; + signal I2C2IRQO_buf: Std_logic; + signal SPISCKO_buf: Std_logic; + signal SPISCKEN_buf: Std_logic; + signal SPIMISOO_buf: Std_logic; + signal SPIMISOEN_buf: Std_logic; + signal SPIMOSIO_buf: Std_logic; + signal SPIMOSIEN_buf: Std_logic; + signal SPIMCSN0_buf: Std_logic; + signal SPIMCSN1_buf: Std_logic; + signal SPIMCSN2_buf: Std_logic; + signal SPIMCSN3_buf: Std_logic; + signal SPIMCSN4_buf: Std_logic; + signal SPIMCSN5_buf: Std_logic; + signal SPIMCSN6_buf: Std_logic; + signal SPIMCSN7_buf: Std_logic; + signal SPICSNEN_buf: Std_logic; + signal SPIIRQO_buf: Std_logic; + signal TCINT_buf: Std_logic; + signal TCOC_buf: Std_logic; + signal WBCUFMIRQ_buf: Std_logic; + signal CFGWAKE_buf: Std_logic; + signal CFGSTDBY_buf: Std_logic; + component EFB_Buffer_Block + port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic; + WBRSTIin: in Std_logic; WBRSTIout: out Std_logic; + WBCYCIin: in Std_logic; WBCYCIout: out Std_logic; + WBSTBIin: in Std_logic; WBSTBIout: out Std_logic; + WBWEIin: in Std_logic; WBWEIout: out Std_logic; + WBADRI7in: in Std_logic; WBADRI7out: out Std_logic; + WBADRI6in: in Std_logic; WBADRI6out: out Std_logic; + WBADRI5in: in Std_logic; WBADRI5out: out Std_logic; + WBADRI4in: in Std_logic; WBADRI4out: out Std_logic; + WBADRI3in: in Std_logic; WBADRI3out: out Std_logic; + WBADRI2in: in Std_logic; WBADRI2out: out Std_logic; + WBADRI1in: in Std_logic; WBADRI1out: out Std_logic; + WBADRI0in: in Std_logic; WBADRI0out: out Std_logic; + WBDATI7in: in Std_logic; WBDATI7out: out Std_logic; + WBDATI6in: in Std_logic; WBDATI6out: out Std_logic; + WBDATI5in: in Std_logic; WBDATI5out: out Std_logic; + WBDATI4in: in Std_logic; WBDATI4out: out Std_logic; + WBDATI3in: in Std_logic; WBDATI3out: out Std_logic; + WBDATI2in: in Std_logic; WBDATI2out: out Std_logic; + WBDATI1in: in Std_logic; WBDATI1out: out Std_logic; + WBDATI0in: in Std_logic; WBDATI0out: out Std_logic; + PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic; + PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic; + PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic; + PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic; + PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic; + PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic; + PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic; + PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic; + PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic; + PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic; + PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic; + PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic; + PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic; + PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic; + PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic; + PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic; + PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic; + PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic; + I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic; + I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic; + I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic; + I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic; + SPISCKIin: in Std_logic; SPISCKIout: out Std_logic; + SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic; + SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic; + SPISCSNin: in Std_logic; SPISCSNout: out Std_logic; + TCCLKIin: in Std_logic; TCCLKIout: out Std_logic; + TCRSTNin: in Std_logic; TCRSTNout: out Std_logic; + TCICin: in Std_logic; TCICout: out Std_logic; + UFMSNin: in Std_logic; UFMSNout: out Std_logic; + WBDATO7out: out Std_logic; WBDATO7in: in Std_logic; + WBDATO6out: out Std_logic; WBDATO6in: in Std_logic; + WBDATO5out: out Std_logic; WBDATO5in: in Std_logic; + WBDATO4out: out Std_logic; WBDATO4in: in Std_logic; + WBDATO3out: out Std_logic; WBDATO3in: in Std_logic; + WBDATO2out: out Std_logic; WBDATO2in: in Std_logic; + WBDATO1out: out Std_logic; WBDATO1in: in Std_logic; + WBDATO0out: out Std_logic; WBDATO0in: in Std_logic; + WBACKOout: out Std_logic; WBACKOin: in Std_logic; + PLLCLKOout: out Std_logic; PLLCLKOin: in Std_logic; + PLLRSTOout: out Std_logic; PLLRSTOin: in Std_logic; + PLL0STBOout: out Std_logic; PLL0STBOin: in Std_logic; + PLL1STBOout: out Std_logic; PLL1STBOin: in Std_logic; + PLLWEOout: out Std_logic; PLLWEOin: in Std_logic; + PLLADRO4out: out Std_logic; PLLADRO4in: in Std_logic; + PLLADRO3out: out Std_logic; PLLADRO3in: in Std_logic; + PLLADRO2out: out Std_logic; PLLADRO2in: in Std_logic; + PLLADRO1out: out Std_logic; PLLADRO1in: in Std_logic; + PLLADRO0out: out Std_logic; PLLADRO0in: in Std_logic; + PLLDATO7out: out Std_logic; PLLDATO7in: in Std_logic; + PLLDATO6out: out Std_logic; PLLDATO6in: in Std_logic; + PLLDATO5out: out Std_logic; PLLDATO5in: in Std_logic; + PLLDATO4out: out Std_logic; PLLDATO4in: in Std_logic; + PLLDATO3out: out Std_logic; PLLDATO3in: in Std_logic; + PLLDATO2out: out Std_logic; PLLDATO2in: in Std_logic; + PLLDATO1out: out Std_logic; PLLDATO1in: in Std_logic; + PLLDATO0out: out Std_logic; PLLDATO0in: in Std_logic; + I2C1SCLOout: out Std_logic; I2C1SCLOin: in Std_logic; + I2C1SCLOENout: out Std_logic; I2C1SCLOENin: in Std_logic; + I2C1SDAOout: out Std_logic; I2C1SDAOin: in Std_logic; + I2C1SDAOENout: out Std_logic; I2C1SDAOENin: in Std_logic; + I2C2SCLOout: out Std_logic; I2C2SCLOin: in Std_logic; + I2C2SCLOENout: out Std_logic; I2C2SCLOENin: in Std_logic; + I2C2SDAOout: out Std_logic; I2C2SDAOin: in Std_logic; + I2C2SDAOENout: out Std_logic; I2C2SDAOENin: in Std_logic; + I2C1IRQOout: out Std_logic; I2C1IRQOin: in Std_logic; + I2C2IRQOout: out Std_logic; I2C2IRQOin: in Std_logic; + SPISCKOout: out Std_logic; SPISCKOin: in Std_logic; + SPISCKENout: out Std_logic; SPISCKENin: in Std_logic; + SPIMISOOout: out Std_logic; SPIMISOOin: in Std_logic; + SPIMISOENout: out Std_logic; SPIMISOENin: in Std_logic; + SPIMOSIOout: out Std_logic; SPIMOSIOin: in Std_logic; + SPIMOSIENout: out Std_logic; SPIMOSIENin: in Std_logic; + SPIMCSN0out: out Std_logic; SPIMCSN0in: in Std_logic; + SPIMCSN1out: out Std_logic; SPIMCSN1in: in Std_logic; + SPIMCSN2out: out Std_logic; SPIMCSN2in: in Std_logic; + SPIMCSN3out: out Std_logic; SPIMCSN3in: in Std_logic; + SPIMCSN4out: out Std_logic; SPIMCSN4in: in Std_logic; + SPIMCSN5out: out Std_logic; SPIMCSN5in: in Std_logic; + SPIMCSN6out: out Std_logic; SPIMCSN6in: in Std_logic; + SPIMCSN7out: out Std_logic; SPIMCSN7in: in Std_logic; + SPICSNENout: out Std_logic; SPICSNENin: in Std_logic; + SPIIRQOout: out Std_logic; SPIIRQOin: in Std_logic; + TCINTout: out Std_logic; TCINTin: in Std_logic; + TCOCout: out Std_logic; TCOCin: in Std_logic; + WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic; + CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic; + CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic); + end component; + begin + INST10: EFB + generic map (DEV_DENSITY => "640L", EFB_I2C1 => "DISABLED", + EFB_I2C2 => "DISABLED", EFB_SPI => "DISABLED", + EFB_TC => "DISABLED", EFB_TC_PORTMODE => "WB", + EFB_UFM => "ENABLED", EFB_WB_CLK_FREQ => "66.7", + GSR => "ENABLED", I2C1_ADDRESSING => "7BIT", + I2C1_BUS_PERF => "100kHz", I2C1_CLK_DIVIDER => 1, + I2C1_GEN_CALL => "DISABLED", I2C1_SLAVE_ADDR => "0b1000001", + I2C1_WAKEUP => "DISABLED", I2C2_ADDRESSING => "7BIT", + I2C2_BUS_PERF => "100kHz", I2C2_CLK_DIVIDER => 1, + I2C2_GEN_CALL => "DISABLED", I2C2_SLAVE_ADDR => "0b1000010", + I2C2_WAKEUP => "DISABLED", SPI_CLK_DIVIDER => 1, + SPI_CLK_INV => "DISABLED", SPI_INTR_RXOVR => "DISABLED", + SPI_INTR_RXRDY => "DISABLED", SPI_INTR_TXOVR => "DISABLED", + SPI_INTR_TXRDY => "DISABLED", SPI_LSB_FIRST => "DISABLED", + SPI_MODE => "MASTER", SPI_PHASE_ADJ => "DISABLED", + SPI_SLAVE_HANDSHAKE => "DISABLED", SPI_WAKEUP => "DISABLED", + TC_CCLK_SEL => 1, TC_ICAPTURE => "DISABLED", + TC_ICR_INT => "OFF", TC_MODE => "CTCM", TC_OCR_INT => "OFF", + TC_OCR_SET => 32767, TC_OC_MODE => "TOGGLE", + TC_OVERFLOW => "DISABLED", TC_OV_INT => "OFF", + TC_RESETN => "ENABLED", TC_SCLK_SEL => "PCLOCK", + TC_TOP_SEL => "OFF", TC_TOP_SET => 65535, + UFM_INIT_ALL_ZEROS => "DISABLED", + UFM_INIT_FILE_FORMAT => "HEX", + UFM_INIT_FILE_NAME => "../RAM2GS-LCMXO2.mem", + UFM_INIT_PAGES => 1, UFM_INIT_START_PAGE => 190) + port map (WBCLKI=>WBCLKI_buf, WBRSTI=>WBRSTI_buf, WBCYCI=>WBCYCI_buf, + WBSTBI=>WBSTBI_buf, WBWEI=>WBWEI_buf, WBADRI7=>WBADRI7_buf, + WBADRI6=>WBADRI6_buf, WBADRI5=>WBADRI5_buf, + WBADRI4=>WBADRI4_buf, WBADRI3=>WBADRI3_buf, + WBADRI2=>WBADRI2_buf, WBADRI1=>WBADRI1_buf, + WBADRI0=>WBADRI0_buf, WBDATI7=>WBDATI7_buf, + WBDATI6=>WBDATI6_buf, WBDATI5=>WBDATI5_buf, + WBDATI4=>WBDATI4_buf, WBDATI3=>WBDATI3_buf, + WBDATI2=>WBDATI2_buf, WBDATI1=>WBDATI1_buf, + WBDATI0=>WBDATI0_buf, PLL0DATI7=>PLL0DATI7_buf, + PLL0DATI6=>PLL0DATI6_buf, PLL0DATI5=>PLL0DATI5_buf, + PLL0DATI4=>PLL0DATI4_buf, PLL0DATI3=>PLL0DATI3_buf, + PLL0DATI2=>PLL0DATI2_buf, PLL0DATI1=>PLL0DATI1_buf, + PLL0DATI0=>PLL0DATI0_buf, PLL0ACKI=>PLL0ACKI_buf, + PLL1DATI7=>PLL1DATI7_buf, PLL1DATI6=>PLL1DATI6_buf, + PLL1DATI5=>PLL1DATI5_buf, PLL1DATI4=>PLL1DATI4_buf, + PLL1DATI3=>PLL1DATI3_buf, PLL1DATI2=>PLL1DATI2_buf, + PLL1DATI1=>PLL1DATI1_buf, PLL1DATI0=>PLL1DATI0_buf, + PLL1ACKI=>PLL1ACKI_buf, I2C1SCLI=>I2C1SCLI_buf, + I2C1SDAI=>I2C1SDAI_buf, I2C2SCLI=>I2C2SCLI_buf, + I2C2SDAI=>I2C2SDAI_buf, SPISCKI=>SPISCKI_buf, + SPIMISOI=>SPIMISOI_buf, SPIMOSII=>SPIMOSII_buf, + SPISCSN=>SPISCSN_buf, TCCLKI=>TCCLKI_buf, TCRSTN=>TCRSTN_buf, + TCIC=>TCIC_buf, UFMSN=>UFMSN_buf, WBDATO7=>WBDATO7_buf, + WBDATO6=>WBDATO6_buf, WBDATO5=>WBDATO5_buf, + WBDATO4=>WBDATO4_buf, WBDATO3=>WBDATO3_buf, + WBDATO2=>WBDATO2_buf, WBDATO1=>WBDATO1_buf, + WBDATO0=>WBDATO0_buf, WBACKO=>WBACKO_buf, PLLCLKO=>PLLCLKO_buf, + PLLRSTO=>PLLRSTO_buf, PLL0STBO=>PLL0STBO_buf, + PLL1STBO=>PLL1STBO_buf, PLLWEO=>PLLWEO_buf, + PLLADRO4=>PLLADRO4_buf, PLLADRO3=>PLLADRO3_buf, + PLLADRO2=>PLLADRO2_buf, PLLADRO1=>PLLADRO1_buf, + PLLADRO0=>PLLADRO0_buf, PLLDATO7=>PLLDATO7_buf, + PLLDATO6=>PLLDATO6_buf, PLLDATO5=>PLLDATO5_buf, + PLLDATO4=>PLLDATO4_buf, PLLDATO3=>PLLDATO3_buf, + PLLDATO2=>PLLDATO2_buf, PLLDATO1=>PLLDATO1_buf, + PLLDATO0=>PLLDATO0_buf, I2C1SCLO=>I2C1SCLO_buf, + I2C1SCLOEN=>I2C1SCLOEN_buf, I2C1SDAO=>I2C1SDAO_buf, + I2C1SDAOEN=>I2C1SDAOEN_buf, I2C2SCLO=>I2C2SCLO_buf, + I2C2SCLOEN=>I2C2SCLOEN_buf, I2C2SDAO=>I2C2SDAO_buf, + I2C2SDAOEN=>I2C2SDAOEN_buf, I2C1IRQO=>I2C1IRQO_buf, + I2C2IRQO=>I2C2IRQO_buf, SPISCKO=>SPISCKO_buf, + SPISCKEN=>SPISCKEN_buf, SPIMISOO=>SPIMISOO_buf, + SPIMISOEN=>SPIMISOEN_buf, SPIMOSIO=>SPIMOSIO_buf, + SPIMOSIEN=>SPIMOSIEN_buf, SPIMCSN0=>SPIMCSN0_buf, + SPIMCSN1=>SPIMCSN1_buf, SPIMCSN2=>SPIMCSN2_buf, + SPIMCSN3=>SPIMCSN3_buf, SPIMCSN4=>SPIMCSN4_buf, + SPIMCSN5=>SPIMCSN5_buf, SPIMCSN6=>SPIMCSN6_buf, + SPIMCSN7=>SPIMCSN7_buf, SPICSNEN=>SPICSNEN_buf, + SPIIRQO=>SPIIRQO_buf, TCINT=>TCINT_buf, TCOC=>TCOC_buf, + WBCUFMIRQ=>WBCUFMIRQ_buf, CFGWAKE=>CFGWAKE_buf, + CFGSTDBY=>CFGSTDBY_buf); + INST20: EFB_Buffer_Block + port map (WBCLKIin=>WBCLKI, WBCLKIout=>WBCLKI_buf, WBRSTIin=>WBRSTI, + WBRSTIout=>WBRSTI_buf, WBCYCIin=>WBCYCI, WBCYCIout=>WBCYCI_buf, + WBSTBIin=>WBSTBI, WBSTBIout=>WBSTBI_buf, WBWEIin=>WBWEI, + WBWEIout=>WBWEI_buf, WBADRI7in=>WBADRI7, + WBADRI7out=>WBADRI7_buf, WBADRI6in=>WBADRI6, + WBADRI6out=>WBADRI6_buf, WBADRI5in=>WBADRI5, + WBADRI5out=>WBADRI5_buf, WBADRI4in=>WBADRI4, + WBADRI4out=>WBADRI4_buf, WBADRI3in=>WBADRI3, + WBADRI3out=>WBADRI3_buf, WBADRI2in=>WBADRI2, + WBADRI2out=>WBADRI2_buf, WBADRI1in=>WBADRI1, + WBADRI1out=>WBADRI1_buf, WBADRI0in=>WBADRI0, + WBADRI0out=>WBADRI0_buf, WBDATI7in=>WBDATI7, + WBDATI7out=>WBDATI7_buf, WBDATI6in=>WBDATI6, + WBDATI6out=>WBDATI6_buf, WBDATI5in=>WBDATI5, + WBDATI5out=>WBDATI5_buf, WBDATI4in=>WBDATI4, + WBDATI4out=>WBDATI4_buf, WBDATI3in=>WBDATI3, + WBDATI3out=>WBDATI3_buf, WBDATI2in=>WBDATI2, + WBDATI2out=>WBDATI2_buf, WBDATI1in=>WBDATI1, + WBDATI1out=>WBDATI1_buf, WBDATI0in=>WBDATI0, + WBDATI0out=>WBDATI0_buf, PLL0DATI7in=>PLL0DATI7, + PLL0DATI7out=>PLL0DATI7_buf, PLL0DATI6in=>PLL0DATI6, + PLL0DATI6out=>PLL0DATI6_buf, PLL0DATI5in=>PLL0DATI5, + PLL0DATI5out=>PLL0DATI5_buf, PLL0DATI4in=>PLL0DATI4, + PLL0DATI4out=>PLL0DATI4_buf, PLL0DATI3in=>PLL0DATI3, + PLL0DATI3out=>PLL0DATI3_buf, PLL0DATI2in=>PLL0DATI2, + PLL0DATI2out=>PLL0DATI2_buf, PLL0DATI1in=>PLL0DATI1, + PLL0DATI1out=>PLL0DATI1_buf, PLL0DATI0in=>PLL0DATI0, + PLL0DATI0out=>PLL0DATI0_buf, PLL0ACKIin=>PLL0ACKI, + PLL0ACKIout=>PLL0ACKI_buf, PLL1DATI7in=>PLL1DATI7, + PLL1DATI7out=>PLL1DATI7_buf, PLL1DATI6in=>PLL1DATI6, + PLL1DATI6out=>PLL1DATI6_buf, PLL1DATI5in=>PLL1DATI5, + PLL1DATI5out=>PLL1DATI5_buf, PLL1DATI4in=>PLL1DATI4, + PLL1DATI4out=>PLL1DATI4_buf, PLL1DATI3in=>PLL1DATI3, + PLL1DATI3out=>PLL1DATI3_buf, PLL1DATI2in=>PLL1DATI2, + PLL1DATI2out=>PLL1DATI2_buf, PLL1DATI1in=>PLL1DATI1, + PLL1DATI1out=>PLL1DATI1_buf, PLL1DATI0in=>PLL1DATI0, + PLL1DATI0out=>PLL1DATI0_buf, PLL1ACKIin=>PLL1ACKI, + PLL1ACKIout=>PLL1ACKI_buf, I2C1SCLIin=>I2C1SCLI, + I2C1SCLIout=>I2C1SCLI_buf, I2C1SDAIin=>I2C1SDAI, + I2C1SDAIout=>I2C1SDAI_buf, I2C2SCLIin=>I2C2SCLI, + I2C2SCLIout=>I2C2SCLI_buf, I2C2SDAIin=>I2C2SDAI, + I2C2SDAIout=>I2C2SDAI_buf, SPISCKIin=>SPISCKI, + SPISCKIout=>SPISCKI_buf, SPIMISOIin=>SPIMISOI, + SPIMISOIout=>SPIMISOI_buf, SPIMOSIIin=>SPIMOSII, + SPIMOSIIout=>SPIMOSII_buf, SPISCSNin=>SPISCSN, + SPISCSNout=>SPISCSN_buf, TCCLKIin=>TCCLKI, + TCCLKIout=>TCCLKI_buf, TCRSTNin=>TCRSTN, TCRSTNout=>TCRSTN_buf, + TCICin=>TCIC, TCICout=>TCIC_buf, UFMSNin=>UFMSN, + UFMSNout=>UFMSN_buf, WBDATO7out=>WBDATO7, + WBDATO7in=>WBDATO7_buf, WBDATO6out=>WBDATO6, + WBDATO6in=>WBDATO6_buf, WBDATO5out=>WBDATO5, + WBDATO5in=>WBDATO5_buf, WBDATO4out=>WBDATO4, + WBDATO4in=>WBDATO4_buf, WBDATO3out=>WBDATO3, + WBDATO3in=>WBDATO3_buf, WBDATO2out=>WBDATO2, + WBDATO2in=>WBDATO2_buf, WBDATO1out=>WBDATO1, + WBDATO1in=>WBDATO1_buf, WBDATO0out=>WBDATO0, + WBDATO0in=>WBDATO0_buf, WBACKOout=>WBACKO, + WBACKOin=>WBACKO_buf, PLLCLKOout=>PLLCLKO, + PLLCLKOin=>PLLCLKO_buf, PLLRSTOout=>PLLRSTO, + PLLRSTOin=>PLLRSTO_buf, PLL0STBOout=>PLL0STBO, + PLL0STBOin=>PLL0STBO_buf, PLL1STBOout=>PLL1STBO, + PLL1STBOin=>PLL1STBO_buf, PLLWEOout=>PLLWEO, + PLLWEOin=>PLLWEO_buf, PLLADRO4out=>PLLADRO4, + PLLADRO4in=>PLLADRO4_buf, PLLADRO3out=>PLLADRO3, + PLLADRO3in=>PLLADRO3_buf, PLLADRO2out=>PLLADRO2, + PLLADRO2in=>PLLADRO2_buf, PLLADRO1out=>PLLADRO1, + PLLADRO1in=>PLLADRO1_buf, PLLADRO0out=>PLLADRO0, + PLLADRO0in=>PLLADRO0_buf, PLLDATO7out=>PLLDATO7, + PLLDATO7in=>PLLDATO7_buf, PLLDATO6out=>PLLDATO6, + PLLDATO6in=>PLLDATO6_buf, PLLDATO5out=>PLLDATO5, + PLLDATO5in=>PLLDATO5_buf, PLLDATO4out=>PLLDATO4, + PLLDATO4in=>PLLDATO4_buf, PLLDATO3out=>PLLDATO3, + PLLDATO3in=>PLLDATO3_buf, PLLDATO2out=>PLLDATO2, + PLLDATO2in=>PLLDATO2_buf, PLLDATO1out=>PLLDATO1, + PLLDATO1in=>PLLDATO1_buf, PLLDATO0out=>PLLDATO0, + PLLDATO0in=>PLLDATO0_buf, I2C1SCLOout=>I2C1SCLO, + I2C1SCLOin=>I2C1SCLO_buf, I2C1SCLOENout=>I2C1SCLOEN, + I2C1SCLOENin=>I2C1SCLOEN_buf, I2C1SDAOout=>I2C1SDAO, + I2C1SDAOin=>I2C1SDAO_buf, I2C1SDAOENout=>I2C1SDAOEN, + I2C1SDAOENin=>I2C1SDAOEN_buf, I2C2SCLOout=>I2C2SCLO, + I2C2SCLOin=>I2C2SCLO_buf, I2C2SCLOENout=>I2C2SCLOEN, + I2C2SCLOENin=>I2C2SCLOEN_buf, I2C2SDAOout=>I2C2SDAO, + I2C2SDAOin=>I2C2SDAO_buf, I2C2SDAOENout=>I2C2SDAOEN, + I2C2SDAOENin=>I2C2SDAOEN_buf, I2C1IRQOout=>I2C1IRQO, + I2C1IRQOin=>I2C1IRQO_buf, I2C2IRQOout=>I2C2IRQO, + I2C2IRQOin=>I2C2IRQO_buf, SPISCKOout=>SPISCKO, + SPISCKOin=>SPISCKO_buf, SPISCKENout=>SPISCKEN, + SPISCKENin=>SPISCKEN_buf, SPIMISOOout=>SPIMISOO, + SPIMISOOin=>SPIMISOO_buf, SPIMISOENout=>SPIMISOEN, + SPIMISOENin=>SPIMISOEN_buf, SPIMOSIOout=>SPIMOSIO, + SPIMOSIOin=>SPIMOSIO_buf, SPIMOSIENout=>SPIMOSIEN, + SPIMOSIENin=>SPIMOSIEN_buf, SPIMCSN0out=>SPIMCSN0, + SPIMCSN0in=>SPIMCSN0_buf, SPIMCSN1out=>SPIMCSN1, + SPIMCSN1in=>SPIMCSN1_buf, SPIMCSN2out=>SPIMCSN2, + SPIMCSN2in=>SPIMCSN2_buf, SPIMCSN3out=>SPIMCSN3, + SPIMCSN3in=>SPIMCSN3_buf, SPIMCSN4out=>SPIMCSN4, + SPIMCSN4in=>SPIMCSN4_buf, SPIMCSN5out=>SPIMCSN5, + SPIMCSN5in=>SPIMCSN5_buf, SPIMCSN6out=>SPIMCSN6, + SPIMCSN6in=>SPIMCSN6_buf, SPIMCSN7out=>SPIMCSN7, + SPIMCSN7in=>SPIMCSN7_buf, SPICSNENout=>SPICSNEN, + SPICSNENin=>SPICSNEN_buf, SPIIRQOout=>SPIIRQO, + SPIIRQOin=>SPIIRQO_buf, TCINTout=>TCINT, TCINTin=>TCINT_buf, + TCOCout=>TCOC, TCOCin=>TCOC_buf, WBCUFMIRQout=>WBCUFMIRQ, + WBCUFMIRQin=>WBCUFMIRQ_buf, CFGWAKEout=>CFGWAKE, + CFGWAKEin=>CFGWAKE_buf, CFGSTDBYout=>CFGSTDBY, + CFGSTDBYin=>CFGSTDBY_buf); + end Structure; + +-- entity ufmefb_EFBInst_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ufmefb_EFBInst_0 is + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic; + WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic; + WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic; + WBDATO0: out Std_logic; WBDATO1: out Std_logic; + WBACKO: out Std_logic); + + + + end ufmefb_EFBInst_0; + + architecture Structure of ufmefb_EFBInst_0 is + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component EFBB + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; + WBADRI3: in Std_logic; WBADRI4: in Std_logic; + WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; + WBDATI1: in Std_logic; WBDATI2: in Std_logic; + WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; + WBDATI7: in Std_logic; WBDATO0: out Std_logic; + WBDATO1: out Std_logic; WBDATO2: out Std_logic; + WBDATO3: out Std_logic; WBDATO4: out Std_logic; + WBDATO5: out Std_logic; WBDATO6: out Std_logic; + WBDATO7: out Std_logic; WBACKO: out Std_logic; + WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic; + CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic; + I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic; + I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic; + I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic; + I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic; + I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic; + I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic; + I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic; + SPISCKI: in Std_logic; SPISCKO: out Std_logic; + SPISCKEN: out Std_logic; SPIMISOI: in Std_logic; + SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic; + SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic; + SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic; + SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic; + SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic; + SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic; + SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic; + SPISCSN: in Std_logic; SPIIRQO: out Std_logic; + TCCLKI: in Std_logic; TCRSTN: in Std_logic; TCIC: in Std_logic; + TCINT: out Std_logic; TCOC: out Std_logic; PLLCLKO: out Std_logic; + PLLRSTO: out Std_logic; PLL0STBO: out Std_logic; + PLL1STBO: out Std_logic; PLLWEO: out Std_logic; + PLLADRO0: out Std_logic; PLLADRO1: out Std_logic; + PLLADRO2: out Std_logic; PLLADRO3: out Std_logic; + PLLADRO4: out Std_logic; PLLDATO0: out Std_logic; + PLLDATO1: out Std_logic; PLLDATO2: out Std_logic; + PLLDATO3: out Std_logic; PLLDATO4: out Std_logic; + PLLDATO5: out Std_logic; PLLDATO6: out Std_logic; + PLLDATO7: out Std_logic; PLL0DATI0: in Std_logic; + PLL0DATI1: in Std_logic; PLL0DATI2: in Std_logic; + PLL0DATI3: in Std_logic; PLL0DATI4: in Std_logic; + PLL0DATI5: in Std_logic; PLL0DATI6: in Std_logic; + PLL0DATI7: in Std_logic; PLL0ACKI: in Std_logic; + PLL1DATI0: in Std_logic; PLL1DATI1: in Std_logic; + PLL1DATI2: in Std_logic; PLL1DATI3: in Std_logic; + PLL1DATI4: in Std_logic; PLL1DATI5: in Std_logic; + PLL1DATI6: in Std_logic; PLL1DATI7: in Std_logic; + PLL1ACKI: in Std_logic); + end component; + begin + ufmefb_EFBInst_0_EFB: EFBB + port map (WBCLKI=>WBCLKI, WBRSTI=>WBRSTI, WBCYCI=>WBCYCI, WBSTBI=>WBSTBI, + WBWEI=>WBWEI, WBADRI0=>WBADRI0, WBADRI1=>WBADRI1, + WBADRI2=>WBADRI2, WBADRI3=>WBADRI3, WBADRI4=>WBADRI4, + WBADRI5=>WBADRI5, WBADRI6=>WBADRI6, WBADRI7=>WBADRI7, + WBDATI0=>WBDATI0, WBDATI1=>WBDATI1, WBDATI2=>WBDATI2, + WBDATI3=>WBDATI3, WBDATI4=>WBDATI4, WBDATI5=>WBDATI5, + WBDATI6=>WBDATI6, WBDATI7=>WBDATI7, WBDATO0=>WBDATO0, + WBDATO1=>WBDATO1, WBDATO2=>open, WBDATO3=>open, WBDATO4=>open, + WBDATO5=>open, WBDATO6=>open, WBDATO7=>open, WBACKO=>WBACKO, + WBCUFMIRQ=>open, UFMSN=>VCCI, CFGWAKE=>open, CFGSTDBY=>open, + I2C1SCLI=>GNDI, I2C1SCLO=>open, I2C1SCLOEN=>open, + I2C1SDAI=>GNDI, I2C1SDAO=>open, I2C1SDAOEN=>open, + I2C2SCLI=>GNDI, I2C2SCLO=>open, I2C2SCLOEN=>open, + I2C2SDAI=>GNDI, I2C2SDAO=>open, I2C2SDAOEN=>open, + I2C1IRQO=>open, I2C2IRQO=>open, SPISCKI=>GNDI, SPISCKO=>open, + SPISCKEN=>open, SPIMISOI=>GNDI, SPIMISOO=>open, + SPIMISOEN=>open, SPIMOSII=>GNDI, SPIMOSIO=>open, + SPIMOSIEN=>open, SPIMCSN0=>open, SPIMCSN1=>open, + SPIMCSN2=>open, SPIMCSN3=>open, SPIMCSN4=>open, SPIMCSN5=>open, + SPIMCSN6=>open, SPIMCSN7=>open, SPICSNEN=>open, SPISCSN=>GNDI, + SPIIRQO=>open, TCCLKI=>GNDI, TCRSTN=>GNDI, TCIC=>GNDI, + TCINT=>open, TCOC=>open, PLLCLKO=>open, PLLRSTO=>open, + PLL0STBO=>open, PLL1STBO=>open, PLLWEO=>open, PLLADRO0=>open, + PLLADRO1=>open, PLLADRO2=>open, PLLADRO3=>open, PLLADRO4=>open, + PLLDATO0=>open, PLLDATO1=>open, PLLDATO2=>open, PLLDATO3=>open, + PLLDATO4=>open, PLLDATO5=>open, PLLDATO6=>open, PLLDATO7=>open, + PLL0DATI0=>GNDI, PLL0DATI1=>GNDI, PLL0DATI2=>GNDI, + PLL0DATI3=>GNDI, PLL0DATI4=>GNDI, PLL0DATI5=>GNDI, + PLL0DATI6=>GNDI, PLL0DATI7=>GNDI, PLL0ACKI=>GNDI, + PLL1DATI0=>GNDI, PLL1DATI1=>GNDI, PLL1DATI2=>GNDI, + PLL1DATI3=>GNDI, PLL1DATI4=>GNDI, PLL1DATI5=>GNDI, + PLL1DATI6=>GNDI, PLL1DATI7=>GNDI, PLL1ACKI=>GNDI); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_0: Std_logic; + signal FS_s_0: Std_logic; + signal RCLK_c: Std_logic; + signal FS_cry_0: Std_logic; + signal FS_17: Std_logic; + signal FS_s_17: Std_logic; + signal FS_cry_16: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal FS_s_16: Std_logic; + signal FS_s_15: Std_logic; + signal FS_cry_14: Std_logic; + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal FS_s_14: Std_logic; + signal FS_s_13: Std_logic; + signal FS_cry_12: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal FS_s_12: Std_logic; + signal FS_s_11: Std_logic; + signal FS_cry_10: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal FS_s_10: Std_logic; + signal FS_s_9: Std_logic; + signal FS_cry_8: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal FS_s_8: Std_logic; + signal FS_s_7: Std_logic; + signal FS_cry_6: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal FS_s_6: Std_logic; + signal FS_s_5: Std_logic; + signal FS_cry_4: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal FS_s_4: Std_logic; + signal FS_s_3: Std_logic; + signal FS_cry_2: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal FS_s_2: Std_logic; + signal FS_s_1: Std_logic; + signal CmdEnable17_5: Std_logic; + signal N_304: Std_logic; + signal ADWR_7: Std_logic; + signal CmdEnable17_4: Std_logic; + signal CmdEnable17: Std_logic; + signal un1_ADWR: Std_logic; + signal CmdEnable16: Std_logic; + signal ADSubmitted: Std_logic; + signal ADSubmitted_r: Std_logic; + signal PHI2_c: Std_logic; + signal C1WR_2: Std_logic; + signal CmdEnable16_4: Std_logic; + signal C1WR_7: Std_logic; + signal CmdEnable16_5: Std_logic; + signal C1Submitted: Std_logic; + signal C1Submitted_s: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_c_i: Std_logic; + signal CASr: Std_logic; + signal CASr2: Std_logic; + signal CO0: Std_logic; + signal IS_3: Std_logic; + signal RASr2: Std_logic; + signal S_1: Std_logic; + signal N_79_i: Std_logic; + signal Ready_0_sqmuxa_0_a3_2: Std_logic; + signal CmdEnable: Std_logic; + signal un1_CMDWR: Std_logic; + signal CmdEnable_s: Std_logic; + signal XOR8MEG11: Std_logic; + signal Din_c_1: Std_logic; + signal CmdLEDEN: Std_logic; + signal N_75: Std_logic; + signal XOR8MEG14: Std_logic; + signal LEDEN: Std_logic; + signal CmdLEDEN_4: Std_logic; + signal XOR8MEG18: Std_logic; + signal CmdUFMShift: Std_logic; + signal CmdUFMShift_3: Std_logic; + signal CmdUFMShift_fast: Std_logic; + signal CmdUFMShift_3_fast: Std_logic; + signal Din_c_0: Std_logic; + signal CmdUFMWrite_2: Std_logic; + signal CmdUFMWrite: Std_logic; + signal CmdUFMWrite_3: Std_logic; + signal Din_c_4: Std_logic; + signal Din_c_7: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_6: Std_logic; + signal CmdValid_r: Std_logic; + signal CmdValid: Std_logic; + signal CMDWR_2: Std_logic; + signal N_36_fast: Std_logic; + signal CmdValid_fast: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal n8MEGEN: Std_logic; + signal N_93: Std_logic; + signal Cmdn8MEGEN_4: Std_logic; + signal nFWE_c: Std_logic; + signal nFWE_c_i: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal RD_1_i: Std_logic; + signal IS_0: Std_logic; + signal Ready: Std_logic; + signal N_250: Std_logic; + signal N_60_i_i: Std_logic; + signal RA10s_i: Std_logic; + signal IS_1: Std_logic; + signal IS_2: Std_logic; + signal N_57_i_i: Std_logic; + signal IS_n1_0_x2: Std_logic; + signal N_253_i: Std_logic; + signal N_58_i_i: Std_logic; + signal N_45: Std_logic; + signal N_116: Std_logic; + signal InitReady3_0_a3_2: Std_logic; + signal InitReady3: Std_logic; + signal InitReady: Std_logic; + signal N_487_0: Std_logic; + signal wb_dato_1: Std_logic; + signal LEDEN_6: Std_logic; + signal un1_FS_38_i: Std_logic; + signal CBR: Std_logic; + signal nCRAS_c_i_0: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal RowA_4: Std_logic; + signal MAin_c_4: Std_logic; + signal nRowColSel: Std_logic; + signal PHI2r: Std_logic; + signal RA_c_4: Std_logic; + signal RASr3: Std_logic; + signal un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: Std_logic; + signal PHI2r2: Std_logic; + signal N_41: Std_logic; + signal RCKEEN_8_u_1_0: Std_logic; + signal RCKEEN_8_u_0_0: Std_logic; + signal RCKEEN_8: Std_logic; + signal RCKEEN: Std_logic; + signal Bank_7: Std_logic; + signal Bank_2: Std_logic; + signal Bank_5: Std_logic; + signal Bank_6: Std_logic; + signal RCKE_2: Std_logic; + signal RCKE_c: Std_logic; + signal un1_Bank_1_4: Std_logic; + signal N_258: Std_logic; + signal N_486_0: Std_logic; + signal Ready_0_sqmuxa: Std_logic; + signal Ready_fast: Std_logic; + signal N_489_0: Std_logic; + signal MAin_c_1: Std_logic; + signal MAin_c_0: Std_logic; + signal RowAd_0_1: Std_logic; + signal RowAd_0_0: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal MAin_c_3: Std_logic; + signal MAin_c_2: Std_logic; + signal RowAd_0_3: Std_logic; + signal RowAd_0_2: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal MAin_c_5: Std_logic; + signal RowAd_0_5: Std_logic; + signal RowAd_0_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowAd_0_7: Std_logic; + signal RowAd_0_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowAd_0_9: Std_logic; + signal RowAd_0_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal nRRAS_5_u_i_0: Std_logic; + signal XOR8MEG9_1: Std_logic; + signal XOR8MEG_3_u_0_bm: Std_logic; + signal un1_Din_2: Std_logic; + signal XOR8MEG: Std_logic; + signal XOR8MEG_3: Std_logic; + signal wb_dato_0: Std_logic; + signal n8MEGEN_6: Std_logic; + signal wb_rst10: Std_logic; + signal CASr3: Std_logic; + signal N_265: Std_logic; + signal nRowColSel_0_0: Std_logic; + signal nRRAS_0_sqmuxa: Std_logic; + signal wb_rst11: Std_logic; + signal wb_adr_0: Std_logic; + signal N_181: Std_logic; + signal wb_adr_cnst_m2_0: Std_logic; + signal wb_dati_7: Std_logic; + signal wb_adr_5_1: Std_logic; + signal wb_adr_5_0: Std_logic; + signal un1_wb_rst14_i: Std_logic; + signal wb_adr_1: Std_logic; + signal wb_adr_2: Std_logic; + signal wb_adr_5_3: Std_logic; + signal wb_adr_5_2: Std_logic; + signal wb_adr_3: Std_logic; + signal wb_adr_4: Std_logic; + signal wb_adr_5_5: Std_logic; + signal wb_adr_5_4: Std_logic; + signal wb_adr_5: Std_logic; + signal wb_adr_6: Std_logic; + signal wb_adr_5_7: Std_logic; + signal wb_adr_5_6: Std_logic; + signal wb_adr_7: Std_logic; + signal N_245: Std_logic; + signal N_102_2: Std_logic; + signal un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1: Std_logic; + signal un1_wb_cyc_stb_1_sqmuxa_0: Std_logic; + signal un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: Std_logic; + signal wb_cyc_stb: Std_logic; + signal wb_dati_5_1_iv_0_0_1: Std_logic; + signal N_94: Std_logic; + signal N_128: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_0_1: Std_logic; + signal wb_dati_5_0_iv_0_a3_1_0: Std_logic; + signal wb_we: Std_logic; + signal N_119: Std_logic; + signal wb_dati_5_1: Std_logic; + signal wb_dati_5_0: Std_logic; + signal wb_dati_0: Std_logic; + signal wb_dati_1: Std_logic; + signal wb_dati_5_1_iv_0_0_3: Std_logic; + signal un1_wb_we95_1: Std_logic; + signal N_49: Std_logic; + signal N_240: Std_logic; + signal wb_dati_5_3: Std_logic; + signal wb_dati_5_2: Std_logic; + signal wb_dati_2: Std_logic; + signal wb_dati_3: Std_logic; + signal wb_dati_4: Std_logic; + signal un1_wb_rst11_1_s6_1: Std_logic; + signal wb_dati_5_1_iv_0_1_4: Std_logic; + signal wb_dati_5_5: Std_logic; + signal wb_dati_5_4: Std_logic; + signal wb_dati_5: Std_logic; + signal N_89: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_0_7: Std_logic; + signal wb_dati_5_1_iv_0_1_7: Std_logic; + signal wb_dati_5_1_iv_0_1_6: Std_logic; + signal wb_dati_5_7: Std_logic; + signal wb_dati_5_6: Std_logic; + signal wb_dati_6: Std_logic; + signal un1_FS_37_i_0: Std_logic; + signal N_78_i: Std_logic; + signal wb_req: Std_logic; + signal wb_reqe_0: Std_logic; + signal PHI2r3: Std_logic; + signal wb_rst: Std_logic; + signal wb_rste_0: Std_logic; + signal un1_FS_29: Std_logic; + signal wb_we95: Std_logic; + signal CmdUFMData: Std_logic; + signal un1_wb_adr_0_sqmuxa_3: Std_logic; + signal un1_wb_adr_0_sqmuxa_2: Std_logic; + signal wb_we_0: Std_logic; + signal un1_PHI2r3_0: Std_logic; + signal N_102: Std_logic; + signal un1_FS_11: Std_logic; + signal wb_ack: Std_logic; + signal d_N_5_mux: Std_logic; + signal N_254: Std_logic; + signal N_39: Std_logic; + signal nRCAS_0_sqmuxa_1: Std_logic; + signal N_37_i_1: Std_logic; + signal nRWE_0io_RNO_1: Std_logic; + signal CBR_fast: Std_logic; + signal N_37_i: Std_logic; + signal un1_FS_40_1_0_1: Std_logic; + signal un1_FS_40_1_0: Std_logic; + signal nRCAS_0io_RNO_0: Std_logic; + signal N_28_i_1: Std_logic; + signal N_249_i: Std_logic; + signal N_230: Std_logic; + signal nRWE_0io_RNO_3: Std_logic; + signal nRWE_0io_RNO_4: Std_logic; + signal N_131: Std_logic; + signal N_85: Std_logic; + signal N_248: Std_logic; + signal Din_c_3: Std_logic; + signal XOR8MEG14_1: Std_logic; + signal CmdUFMData_1_sqmuxa: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_6: Std_logic; + signal N_246: Std_logic; + signal N_98: Std_logic; + signal wb_dati_5_1_iv_0_a3_0_3: Std_logic; + signal N_25: Std_logic; + signal N_59: Std_logic; + signal wb_dati_5_1_iv_0_a3_2_0_1: Std_logic; + signal wb_dati_5_1_iv_0_a3_1_1_4: Std_logic; + signal wb_dati_5_1_iv_0_a3_3_0_7: Std_logic; + signal N_91: Std_logic; + signal N_242: Std_logic; + signal un1_FS_20_3: Std_logic; + signal wb_we95_0_tz_tz_tz: Std_logic; + signal N_120: Std_logic; + signal N_228: Std_logic; + signal wb_we113_i: Std_logic; + signal un1_FS_40_1_1_1: Std_logic; + signal N_139: Std_logic; + signal un1_FS_40_1_1_tz: Std_logic; + signal N_136: Std_logic; + signal N_28_i_sn: Std_logic; + signal N_25_i: Std_logic; + signal FWEr_fast: Std_logic; + signal N_28_i: Std_logic; + signal N_102_1: Std_logic; + signal N_233: Std_logic; + signal ADWR_4: Std_logic; + signal ADWR_5: Std_logic; + signal C1WR_0: Std_logic; + signal Bank_0: Std_logic; + signal Bank_1: Std_logic; + signal Bank_4: Std_logic; + signal un1_Bank_1_3: Std_logic; + signal Bank_3: Std_logic; + signal G_8_0_a3_0_0: Std_logic; + signal nRWE_0io_RNO_2: Std_logic; + signal Din_c_2: Std_logic; + signal RA_c_9: Std_logic; + signal RDQMH_c: Std_logic; + signal RA_c_7: Std_logic; + signal RA_c_0: Std_logic; + signal RDQML_c: Std_logic; + signal RA_c_1: Std_logic; + signal RA_c_8: Std_logic; + signal RA_c_2: Std_logic; + signal RA_c_6: Std_logic; + signal RA_c_3: Std_logic; + signal RA_c_5: Std_logic; + signal RA11d_0: Std_logic; + signal CROW_c_0: Std_logic; + signal CROW_c_1: Std_logic; + signal RBAd_0_1: Std_logic; + signal RBAd_0_0: Std_logic; + signal RD_in_0: Std_logic; + signal WRD_0: Std_logic; + signal nRCAS_c: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_c: Std_logic; + signal nRCS_c: Std_logic; + signal RD_in_7: Std_logic; + signal WRD_7: Std_logic; + signal RD_in_6: Std_logic; + signal WRD_6: Std_logic; + signal RD_in_5: Std_logic; + signal WRD_5: Std_logic; + signal RD_in_4: Std_logic; + signal WRD_4: Std_logic; + signal RD_in_3: Std_logic; + signal WRD_3: Std_logic; + signal RD_in_2: Std_logic; + signal WRD_2: Std_logic; + signal RD_in_1: Std_logic; + signal WRD_1: Std_logic; + signal RA_c_11: Std_logic; + signal RA_c_10: Std_logic; + signal RBA_c_1: Std_logic; + signal RBA_c_0: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_11 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_12 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_16 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_17 + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_18 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_21 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_22 + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_25 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_26 + port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_28 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_29 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_30 + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_34 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_35 + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_36 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_37 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_38 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_39 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_40 + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_41 + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_42 + port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_43 + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_46 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_47 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_48 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_50 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_51 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; + DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_52 + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_53 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_54 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_55 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_56 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_58 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_60 + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component wb_cyc_stb_RNO_SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_64 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_66 + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_69 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_71 + port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_75 + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_78 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_80 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_81 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_82 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_85 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_86 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_87 + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_89 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_92 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_93 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_96 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_98 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_101 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_102 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_103 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_104 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_105 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_106 + port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_107 + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_108 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_109 + port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_110 + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_111 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_112 + port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_113 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_114 + port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_115 + port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_116 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_117 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_118 + port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD0: inout Std_logic); + end component; + component RD_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component PHI2_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component nRCASB + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + end component; + component nRCAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRRASB + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRRAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRWEB + port (IOLDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRWE_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component nRCSB + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + end component; + component nRCS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_7_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_6_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_5_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_4_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_3_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_2_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RA_11_B + port (IOLDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_11_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RA_10_B + port (IOLDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_10_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component RBA_1_B + port (IOLDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RBA_0_B + port (IOLDO: in Std_logic; RBA0: out Std_logic); + end component; + component RBA_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_7_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_6_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_5_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_4_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_3_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_2_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_1_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component Din_0_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component ufmefb_EFBInst_0 + port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic; + WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic; + WBADRI1: in Std_logic; WBADRI2: in Std_logic; + WBADRI3: in Std_logic; WBADRI4: in Std_logic; + WBADRI5: in Std_logic; WBADRI6: in Std_logic; + WBADRI7: in Std_logic; WBDATI0: in Std_logic; + WBDATI1: in Std_logic; WBDATI2: in Std_logic; + WBDATI3: in Std_logic; WBDATI4: in Std_logic; + WBDATI5: in Std_logic; WBDATI6: in Std_logic; + WBDATI7: in Std_logic; WBDATO0: out Std_logic; + WBDATO1: out Std_logic; WBACKO: out Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0, + FCO=>FS_cry_0); + SLICE_1I: SLICE_1 + port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16, + F0=>FS_s_17, Q0=>FS_17); + SLICE_2I: SLICE_2 + port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c, + FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16, + FCO=>FS_cry_16); + SLICE_3I: SLICE_3 + port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c, + FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14, + FCO=>FS_cry_14); + SLICE_4I: SLICE_4 + port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c, + FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12, + FCO=>FS_cry_12); + SLICE_5I: SLICE_5 + port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c, + FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10, + FCO=>FS_cry_10); + SLICE_6I: SLICE_6 + port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c, + FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8, + FCO=>FS_cry_8); + SLICE_7I: SLICE_7 + port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c, + FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6, + FCO=>FS_cry_6); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c, + FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4, + FCO=>FS_cry_4); + SLICE_9I: SLICE_9 + port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c, + FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2, + FCO=>FS_cry_2); + SLICE_10I: SLICE_10 + port map (D1=>CmdEnable17_5, C1=>N_304, B1=>ADWR_7, A1=>CmdEnable17_4, + D0=>CmdEnable17, C0=>un1_ADWR, B0=>CmdEnable16, + A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c, + F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17); + SLICE_11I: SLICE_11 + port map (D1=>C1WR_2, C1=>CmdEnable16_4, B1=>C1WR_7, A1=>CmdEnable16_5, + C0=>CmdEnable16, B0=>C1Submitted, A0=>un1_ADWR, + DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s, + Q0=>C1Submitted, F1=>CmdEnable16); + SLICE_12I: SLICE_12 + port map (A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_c_i, Q0=>CASr, Q1=>CASr2); + SLICE_16I: SLICE_16 + port map (D1=>CO0, C1=>IS_3, B1=>RASr2, A1=>S_1, D0=>CO0, A0=>S_1, + DI0=>N_79_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_79_i, Q0=>CO0, + F1=>Ready_0_sqmuxa_0_a3_2); + SLICE_17I: SLICE_17 + port map (D1=>ADSubmitted, B1=>CmdEnable, D0=>un1_CMDWR, C0=>C1Submitted, + B0=>CmdEnable17, A0=>CmdEnable, DI0=>CmdEnable_s, + M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable); + SLICE_18I: SLICE_18 + port map (D1=>XOR8MEG11, C1=>Din_c_1, A1=>CmdLEDEN, C0=>N_75, + B0=>XOR8MEG14, A0=>LEDEN, DI0=>CmdLEDEN_4, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>CmdLEDEN_4, Q0=>CmdLEDEN, F1=>N_75); + SLICE_20I: SLICE_20 + port map (D0=>XOR8MEG14, C0=>Din_c_1, B0=>XOR8MEG11, A0=>CmdUFMShift, + DI0=>CmdUFMShift_3, CE=>XOR8MEG18, CLK=>PHI2_c, + F0=>CmdUFMShift_3, Q0=>CmdUFMShift); + SLICE_21I: SLICE_21 + port map (D0=>Din_c_1, C0=>XOR8MEG14, B0=>XOR8MEG11, + A0=>CmdUFMShift_fast, DI0=>CmdUFMShift_3_fast, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>CmdUFMShift_3_fast, Q0=>CmdUFMShift_fast); + SLICE_22I: SLICE_22 + port map (C1=>Din_c_0, A1=>Din_c_1, D0=>XOR8MEG14, C0=>CmdUFMWrite_2, + B0=>XOR8MEG11, A0=>CmdUFMWrite, DI0=>CmdUFMWrite_3, + CE=>XOR8MEG18, CLK=>PHI2_c, F0=>CmdUFMWrite_3, Q0=>CmdUFMWrite, + F1=>CmdUFMWrite_2); + SLICE_23I: SLICE_23 + port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_5, A1=>Din_c_6, + D0=>XOR8MEG14, C0=>XOR8MEG18, B0=>XOR8MEG11, DI0=>CmdValid_r, + CLK=>PHI2_c, F0=>CmdValid_r, Q0=>CmdValid, F1=>XOR8MEG11); + SLICE_24I: SLICE_24 + port map (C1=>CmdEnable, B1=>C1WR_7, A1=>CMDWR_2, D0=>XOR8MEG14, + B0=>XOR8MEG18, A0=>XOR8MEG11, DI0=>N_36_fast, CLK=>PHI2_c, + F0=>N_36_fast, Q0=>CmdValid_fast, F1=>XOR8MEG18); + SLICE_25I: SLICE_25 + port map (D1=>XOR8MEG11, C1=>Din_c_0, A1=>Cmdn8MEGEN, D0=>XOR8MEG14, + C0=>n8MEGEN, B0=>N_93, DI0=>Cmdn8MEGEN_4, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>Cmdn8MEGEN_4, Q0=>Cmdn8MEGEN, F1=>N_93); + SLICE_26I: SLICE_26 + port map (D1=>nFWE_c, C1=>nCCAS_c, C0=>nFWE_c, DI0=>nFWE_c_i, + CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, F1=>RD_1_i); + SLICE_28I: SLICE_28 + port map (D1=>IS_0, C1=>Ready, B1=>IS_3, A1=>N_250, D0=>IS_0, C0=>Ready, + A0=>N_250, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0, + F1=>RA10s_i); + SLICE_29I: SLICE_29 + port map (D1=>IS_1, C1=>IS_0, A1=>IS_2, C0=>IS_0, A0=>IS_1, + DI1=>N_57_i_i, DI0=>IS_n1_0_x2, CE=>N_253_i, CLK=>RCLK_c, + F0=>IS_n1_0_x2, Q0=>IS_1, F1=>N_57_i_i, Q1=>IS_2); + SLICE_30I: SLICE_30 + port map (D1=>IS_1, A1=>IS_2, D0=>IS_3, C0=>IS_0, B0=>IS_1, A0=>IS_2, + DI0=>N_58_i_i, CE=>N_253_i, CLK=>RCLK_c, F0=>N_58_i_i, + Q0=>IS_3, F1=>N_45); + SLICE_31I: SLICE_31 + port map (D1=>N_116, C1=>FS_14, B1=>InitReady3_0_a3_2, A1=>FS_13, + C0=>InitReady3, A0=>InitReady, DI0=>N_487_0, CLK=>RCLK_c, + F0=>N_487_0, Q0=>InitReady, F1=>InitReady3); + SLICE_32I: SLICE_32 + port map (D0=>InitReady, B0=>CmdLEDEN, A0=>wb_dato_1, DI0=>LEDEN_6, + CE=>un1_FS_38_i, CLK=>RCLK_c, F0=>LEDEN_6, Q0=>LEDEN); + SLICE_34I: SLICE_34 + port map (D1=>nCRAS_c, C1=>LEDEN, A1=>CBR, D0=>nCRAS_c, DI0=>nCRAS_c_i_0, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_35I: SLICE_35 + port map (D1=>FS_3, A1=>FS_7, D0=>RowA_4, C0=>MAin_c_4, A0=>nRowColSel, + M1=>PHI2r, M0=>RASr2, CLK=>RCLK_c, F0=>RA_c_4, Q0=>RASr3, + F1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, Q1=>PHI2r2); + SLICE_36I: SLICE_36 + port map (D1=>Ready, C1=>RASr2, B1=>InitReady, A1=>N_41, D0=>CBR, + C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>Ready, + DI0=>RCKEEN_8, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, + F1=>RCKEEN_8_u_0_0); + SLICE_37I: SLICE_37 + port map (D1=>Bank_7, C1=>Bank_2, B1=>Bank_5, A1=>Bank_6, D0=>RASr2, + C0=>RCKEEN, B0=>RASr, A0=>RASr3, DI0=>RCKE_2, CLK=>RCLK_c, + F0=>RCKE_2, Q0=>RCKE_c, F1=>un1_Bank_1_4); + SLICE_38I: SLICE_38 + port map (D1=>IS_1, C1=>IS_0, A1=>IS_2, D0=>InitReady, C0=>N_258, + B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_486_0, + CLK=>RCLK_c, F0=>N_486_0, Q0=>Ready, F1=>N_258); + SLICE_39I: SLICE_39 + port map (D1=>InitReady, C1=>N_258, B1=>Ready_0_sqmuxa_0_a3_2, A1=>Ready, + C0=>Ready_0_sqmuxa, A0=>Ready_fast, DI0=>N_489_0, CLK=>RCLK_c, + F0=>N_489_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa); + SLICE_40I: SLICE_40 + port map (C1=>MAin_c_1, B1=>Ready_fast, C0=>MAin_c_0, B0=>Ready_fast, + DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0, + Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1); + SLICE_41I: SLICE_41 + port map (D1=>Ready_fast, B1=>MAin_c_3, D0=>Ready_fast, C0=>MAin_c_2, + DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2, + Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3); + SLICE_42I: SLICE_42 + port map (D1=>MAin_c_5, A1=>Ready_fast, C0=>MAin_c_4, A0=>Ready_fast, + DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4, + Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5); + SLICE_43I: SLICE_43 + port map (C1=>MAin_c_7, B1=>Ready_fast, C0=>MAin_c_6, B0=>Ready_fast, + DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6, + Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7); + SLICE_44I: SLICE_44 + port map (D1=>Ready_fast, B1=>MAin_c_9, D0=>Ready_fast, A0=>MAin_c_8, + DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8, + Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9); + SLICE_45I: SLICE_45 + port map (D1=>RCKE_c, C1=>N_41, B1=>Ready, A1=>RASr2, D0=>S_1, C0=>CO0, + DI0=>N_41, LSR=>RASr2, CLK=>RCLK_c, F0=>N_41, Q0=>S_1, + F1=>nRRAS_5_u_i_0); + SLICE_46I: SLICE_46 + port map (D1=>XOR8MEG9_1, C1=>Din_c_1, B1=>Din_c_0, A1=>LEDEN, + C0=>XOR8MEG_3_u_0_bm, B0=>un1_Din_2, A0=>XOR8MEG, + DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, + Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_bm); + SLICE_47I: SLICE_47 + port map (D1=>InitReady, C1=>FS_17, B1=>FS_16, A1=>FS_15, D0=>InitReady, + C0=>wb_dato_0, A0=>Cmdn8MEGEN, DI0=>n8MEGEN_6, CE=>un1_FS_38_i, + CLK=>RCLK_c, F0=>n8MEGEN_6, Q0=>n8MEGEN, F1=>wb_rst10); + SLICE_48I: SLICE_48 + port map (D1=>CASr3, C1=>FWEr, B1=>CBR, A1=>Ready, D0=>S_1, C0=>Ready, + B0=>N_265, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, + CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_265); + SLICE_49I: SLICE_49 + port map (D1=>wb_rst11, C1=>wb_adr_0, B1=>InitReady, A1=>N_181, + D0=>wb_adr_cnst_m2_0, B0=>InitReady, A0=>wb_dati_7, + DI1=>wb_adr_5_1, DI0=>wb_adr_5_0, CE=>un1_wb_rst14_i, + CLK=>RCLK_c, F0=>wb_adr_5_0, Q0=>wb_adr_0, F1=>wb_adr_5_1, + Q1=>wb_adr_1); + SLICE_50I: SLICE_50 + port map (B1=>wb_adr_2, A1=>InitReady, C0=>wb_adr_1, A0=>InitReady, + DI1=>wb_adr_5_3, DI0=>wb_adr_5_2, CE=>un1_wb_rst14_i, + CLK=>RCLK_c, F0=>wb_adr_5_2, Q0=>wb_adr_2, F1=>wb_adr_5_3, + Q1=>wb_adr_3); + SLICE_51I: SLICE_51 + port map (D1=>wb_rst11, C1=>InitReady, A1=>wb_adr_4, D0=>wb_rst11, + C0=>InitReady, A0=>wb_adr_3, DI1=>wb_adr_5_5, DI0=>wb_adr_5_4, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_4, Q0=>wb_adr_4, + F1=>wb_adr_5_5, Q1=>wb_adr_5); + SLICE_52I: SLICE_52 + port map (D1=>InitReady, A1=>wb_adr_6, D0=>InitReady, C0=>wb_rst11, + B0=>wb_adr_5, DI1=>wb_adr_5_7, DI0=>wb_adr_5_6, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_6, Q0=>wb_adr_6, + F1=>wb_adr_5_7, Q1=>wb_adr_7); + SLICE_53I: SLICE_53 + port map (D1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, C1=>FS_5, B1=>FS_2, + A1=>FS_4, D0=>wb_rst11, C0=>N_245, B0=>N_102_2, + A0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, + DI0=>un1_wb_cyc_stb_1_sqmuxa_0, + CE=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, LSR=>wb_rst10, + CLK=>RCLK_c, F0=>un1_wb_cyc_stb_1_sqmuxa_0, Q0=>wb_cyc_stb, + F1=>N_102_2); + SLICE_54I: SLICE_54 + port map (D1=>wb_dati_5_1_iv_0_0_1, C1=>N_94, B1=>N_128, + A1=>wb_dati_5_1_iv_0_a3_0_0_1, D0=>wb_dati_5_0_iv_0_a3_1_0, + C0=>wb_we, B0=>InitReady, A0=>N_119, DI1=>wb_dati_5_1, + DI0=>wb_dati_5_0, CE=>un1_wb_rst14_i, CLK=>RCLK_c, + F0=>wb_dati_5_0, Q0=>wb_dati_0, F1=>wb_dati_5_1, Q1=>wb_dati_1); + SLICE_55I: SLICE_55 + port map (D1=>wb_rst11, C1=>wb_dati_5_1_iv_0_0_3, B1=>un1_wb_we95_1, + A1=>N_94, D0=>N_49, C0=>wb_dati_1, B0=>N_240, A0=>InitReady, + DI1=>wb_dati_5_3, DI0=>wb_dati_5_2, CE=>un1_wb_rst14_i, + CLK=>RCLK_c, F0=>wb_dati_5_2, Q0=>wb_dati_2, F1=>wb_dati_5_3, + Q1=>wb_dati_3); + SLICE_56I: SLICE_56 + port map (D1=>N_49, C1=>InitReady, B1=>N_240, A1=>wb_dati_4, + D0=>un1_wb_rst11_1_s6_1, C0=>InitReady, B0=>wb_dati_3, + A0=>wb_dati_5_1_iv_0_1_4, DI1=>wb_dati_5_5, DI0=>wb_dati_5_4, + CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_dati_5_4, + Q0=>wb_dati_4, F1=>wb_dati_5_5, Q1=>wb_dati_5); + SLICE_57I: SLICE_57 + port map (D1=>N_89, C1=>wb_dati_5_1_iv_0_a3_0_0_7, + B1=>wb_dati_5_1_iv_0_1_7, A1=>N_119, D0=>wb_dati_5_1_iv_0_1_6, + C0=>wb_dati_5_1_iv_0_a3_0_0_1, B0=>N_128, DI1=>wb_dati_5_7, + DI0=>wb_dati_5_6, CE=>un1_wb_rst14_i, CLK=>RCLK_c, + F0=>wb_dati_5_6, Q0=>wb_dati_6, F1=>wb_dati_5_7, Q1=>wb_dati_7); + SLICE_58I: SLICE_58 + port map (C1=>FS_14, B1=>FS_12, A1=>FS_13, D0=>wb_rst11, + C0=>un1_FS_37_i_0, B0=>N_78_i, A0=>wb_req, DI0=>wb_reqe_0, + LSR=>wb_rst10, CLK=>RCLK_c, F0=>wb_reqe_0, Q0=>wb_req, + F1=>un1_FS_37_i_0); + SLICE_59I: SLICE_59 + port map (D1=>PHI2r3, C1=>InitReady, B1=>CmdValid, A1=>PHI2r2, + D0=>wb_rst10, C0=>wb_rst, B0=>N_78_i, A0=>FS_14, + DI0=>wb_rste_0, CLK=>RCLK_c, F0=>wb_rste_0, Q0=>wb_rst, + F1=>N_78_i); + SLICE_60I: SLICE_60 + port map (C1=>un1_FS_29, A1=>wb_we95, D0=>CmdUFMData, + C0=>un1_wb_adr_0_sqmuxa_3, B0=>InitReady, + A0=>un1_wb_adr_0_sqmuxa_2, DI0=>wb_we_0, CE=>un1_wb_rst14_i, + LSR=>wb_rst10, CLK=>RCLK_c, F0=>wb_we_0, Q0=>wb_we, + F1=>un1_wb_adr_0_sqmuxa_2); + wb_cyc_stb_RNO_SLICE_61I: wb_cyc_stb_RNO_SLICE_61 + port map (D1=>CmdValid, C1=>CmdUFMWrite, B1=>CmdUFMShift, + A1=>un1_PHI2r3_0, D0=>N_102, C0=>un1_FS_11, A0=>wb_ack, + M0=>InitReady, OFX0=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i); + SLICE_62I: SLICE_62 + port map (D1=>un1_PHI2r3_0, C1=>d_N_5_mux, B1=>CmdValid_fast, + A1=>InitReady, D0=>un1_FS_29, C0=>un1_FS_11, B0=>wb_ack, + A0=>InitReady, F0=>d_N_5_mux, F1=>un1_FS_38_i); + SLICE_63I: SLICE_63 + port map (D1=>S_1, C1=>CO0, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>N_250, + B0=>N_254, A0=>Ready, F0=>N_39, F1=>N_250); + SLICE_64I: SLICE_64 + port map (D1=>Ready, C1=>nRCAS_0_sqmuxa_1, B1=>N_37_i_1, + A1=>nRWE_0io_RNO_1, D0=>Ready, C0=>RASr2, B0=>CBR_fast, + A0=>N_41, F0=>nRCAS_0_sqmuxa_1, F1=>N_37_i); + SLICE_65I: SLICE_65 + port map (D1=>un1_FS_40_1_0_1, C1=>FS_10, B1=>FS_13, A1=>FS_9, D0=>FS_14, + C0=>FS_9, B0=>FS_12, A0=>FS_11, F0=>un1_FS_40_1_0_1, + F1=>un1_FS_40_1_0); + SLICE_66I: SLICE_66 + port map (D1=>S_1, B1=>N_39, A1=>CBR, D0=>S_1, C0=>nRCAS_0io_RNO_0, + B0=>nRCAS_0_sqmuxa_1, A0=>N_28_i_1, F0=>N_249_i, + F1=>nRCAS_0io_RNO_0); + SLICE_67I: SLICE_67 + port map (D1=>wb_rst11, C1=>FS_9, B1=>FS_13, A1=>N_230, D0=>wb_rst11, + C0=>un1_wb_we95_1, B0=>N_94, F0=>N_49, F1=>N_94); + SLICE_68I: SLICE_68 + port map (D1=>nRWE_0io_RNO_3, C1=>nRWE_0io_RNO_4, A1=>Ready, D0=>IS_2, + C0=>IS_1, B0=>IS_0, A0=>N_250, F0=>nRWE_0io_RNO_4, + F1=>nRWE_0io_RNO_1); + SLICE_69I: SLICE_69 + port map (D1=>RCKE_c, C1=>nRRAS_0_sqmuxa, A1=>RASr2, D0=>Ready, B0=>S_1, + A0=>CO0, F0=>nRRAS_0_sqmuxa, F1=>nRWE_0io_RNO_3); + SLICE_70I: SLICE_70 + port map (D1=>FS_14, C1=>N_119, B1=>FS_13, A1=>N_131, C0=>FS_11, + B0=>FS_12, A0=>FS_10, F0=>N_131, F1=>N_85); + SLICE_71I: SLICE_71 + port map (C1=>FS_10, A1=>FS_11, D0=>FS_14, C0=>FS_13, B0=>FS_12, + A0=>N_116, F0=>wb_dati_5_1_iv_0_a3_0_0_7, F1=>N_116); + SLICE_72I: SLICE_72 + port map (D1=>wb_rst11, C1=>FS_14, B1=>FS_13, A1=>N_248, D0=>FS_12, + C0=>FS_11, B0=>FS_9, A0=>FS_10, F0=>N_248, F1=>N_240); + SLICE_73I: SLICE_73 + port map (D1=>Din_c_7, C1=>Din_c_3, B1=>XOR8MEG14_1, A1=>Din_c_5, + D0=>C1WR_7, C0=>CMDWR_2, B0=>XOR8MEG14, A0=>CmdEnable, + M0=>Din_c_0, CE=>CmdUFMData_1_sqmuxa, CLK=>PHI2_c, + F0=>CmdUFMData_1_sqmuxa, Q0=>CmdUFMData, F1=>XOR8MEG14); + SLICE_74I: SLICE_74 + port map (D1=>wb_dati_5_1_iv_0_a3_0_6, C1=>FS_10, B1=>FS_12, A1=>N_246, + D0=>N_85, C0=>wb_dati_5, B0=>InitReady, A0=>N_98, + F0=>wb_dati_5_1_iv_0_1_6, F1=>N_98); + SLICE_75I: SLICE_75 + port map (D1=>FS_11, B1=>FS_14, A1=>wb_rst11, + D0=>wb_dati_5_1_iv_0_a3_0_3, C0=>N_128, B0=>wb_dati_2, + A0=>InitReady, F0=>wb_dati_5_1_iv_0_0_3, F1=>N_128); + SLICE_76I: SLICE_76 + port map (D1=>InitReady, C1=>FS_15, B1=>FS_16, A1=>FS_17, C0=>wb_rst11, + A0=>un1_wb_we95_1, F0=>un1_wb_rst11_1_s6_1, F1=>wb_rst11); + SLICE_77I: SLICE_77 + port map (D1=>IS_1, C1=>IS_3, B1=>IS_2, D0=>nRRAS_5_u_i_0, C0=>N_250, + B0=>N_254, A0=>IS_0, F0=>N_25, F1=>N_254); + SLICE_78I: SLICE_78 + port map (C1=>FS_12, B1=>FS_9, A1=>FS_10, D0=>N_59, C0=>N_128, B0=>FS_13, + F0=>N_89, F1=>N_59); + SLICE_79I: SLICE_79 + port map (C1=>FS_14, B1=>FS_13, A1=>wb_rst11, D0=>InitReady, + C0=>wb_dati_5_1_iv_0_a3_2_0_1, B0=>wb_dati_0, A0=>N_248, + F0=>wb_dati_5_1_iv_0_0_1, F1=>wb_dati_5_1_iv_0_a3_2_0_1); + SLICE_80I: SLICE_80 + port map (D1=>FS_12, C1=>FS_9, B1=>FS_10, A1=>FS_13, D0=>N_248, + C0=>wb_dati_5_1_iv_0_a3_1_1_4, B0=>N_85, A0=>N_246, + F0=>wb_dati_5_1_iv_0_1_4, F1=>wb_dati_5_1_iv_0_a3_1_1_4); + SLICE_81I: SLICE_81 + port map (D1=>FS_12, C1=>wb_dati_5_1_iv_0_a3_3_0_7, B1=>FS_10, + A1=>wb_rst11, D0=>InitReady, C0=>N_91, B0=>N_242, + A0=>wb_dati_6, F0=>wb_dati_5_1_iv_0_1_7, F1=>N_242); + SLICE_82I: SLICE_82 + port map (B1=>FS_13, A1=>FS_14, D0=>FS_11, C0=>un1_FS_20_3, B0=>FS_12, + A0=>wb_we95_0_tz_tz_tz, F0=>un1_wb_we95_1, F1=>un1_FS_20_3); + SLICE_83I: SLICE_83 + port map (D1=>FS_10, B1=>FS_12, A1=>FS_11, D0=>N_120, C0=>FS_14, + B0=>FS_13, A0=>N_119, F0=>N_91, F1=>N_120); + SLICE_84I: SLICE_84 + port map (D1=>wb_we95_0_tz_tz_tz, C1=>FS_13, B1=>FS_14, A1=>N_228, + D0=>wb_we113_i, C0=>un1_FS_29, A0=>wb_we95, F0=>N_181, + F1=>un1_FS_29); + SLICE_85I: SLICE_85 + port map (C1=>un1_FS_40_1_0, B1=>wb_rst11, A1=>un1_FS_40_1_1_1, + D0=>FS_10, C0=>N_139, B0=>un1_FS_40_1_1_tz, A0=>FS_9, + F0=>un1_FS_40_1_1_1, F1=>wb_adr_cnst_m2_0); + SLICE_86I: SLICE_86 + port map (D1=>FS_11, C1=>FS_9, B1=>FS_10, A1=>FS_12, D0=>FS_14, + C0=>N_136, B0=>FS_13, F0=>N_139, F1=>N_136); + SLICE_87I: SLICE_87 + port map (D1=>FS_9, B1=>FS_10, D0=>FS_11, C0=>wb_we95_0_tz_tz_tz, + B0=>FS_12, A0=>un1_FS_20_3, F0=>wb_we95, + F1=>wb_we95_0_tz_tz_tz); + SLICE_88I: SLICE_88 + port map (D1=>N_28_i_sn, C1=>N_25_i, B1=>N_28_i_1, A1=>Ready, D0=>CO0, + C0=>CASr2, B0=>CASr3, A0=>FWEr_fast, F0=>N_28_i_1, F1=>N_28_i); + SLICE_89I: SLICE_89 + port map (B1=>FS_0, A1=>wb_req, D0=>InitReady, C0=>N_102_2, B0=>N_102_1, + A0=>N_233, F0=>N_102, F1=>N_233); + SLICE_90I: SLICE_90 + port map (D1=>CMDWR_2, C1=>C1WR_7, B1=>ADWR_7, A1=>C1WR_2, D0=>MAin_c_6, + C0=>N_304, B0=>MAin_c_5, A0=>MAin_c_7, F0=>C1WR_7, + F1=>un1_CMDWR); + SLICE_91I: SLICE_91 + port map (C1=>ADWR_7, B1=>C1WR_7, A1=>C1WR_2, D0=>MAin_c_3, C0=>MAin_c_1, + B0=>ADWR_4, A0=>ADWR_5, F0=>ADWR_7, F1=>un1_ADWR); + SLICE_92I: SLICE_92 + port map (D1=>MAin_c_4, C1=>MAin_c_3, B1=>MAin_c_2, D0=>nFWE_c, + C0=>C1WR_0, B0=>MAin_c_0, A0=>MAin_c_1, F0=>C1WR_2, F1=>C1WR_0); + SLICE_93I: SLICE_93 + port map (D1=>wb_we113_i, C1=>wb_rst11, A1=>un1_FS_37_i_0, + D0=>wb_we95_0_tz_tz_tz, C0=>FS_14, B0=>FS_13, A0=>N_228, + F0=>wb_we113_i, F1=>un1_wb_adr_0_sqmuxa_3); + SLICE_94I: SLICE_94 + port map (B1=>Bank_0, A1=>Bank_1, D0=>Bank_4, C0=>un1_Bank_1_3, + B0=>un1_Bank_1_4, A0=>Bank_3, F0=>N_304, F1=>un1_Bank_1_3); + SLICE_95I: SLICE_95 + port map (B1=>PHI2r3, A1=>PHI2r2, D0=>CmdValid, C0=>CmdUFMShift, + B0=>un1_PHI2r3_0, A0=>InitReady, F0=>N_245, F1=>un1_PHI2r3_0); + SLICE_96I: SLICE_96 + port map (D1=>FS_6, C1=>FS_8, A1=>FS_1, C0=>N_102_1, B0=>wb_req, + A0=>FS_0, F0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, F1=>N_102_1); + SLICE_97I: SLICE_97 + port map (C1=>PHI2r2, B1=>PHI2r3, D0=>CmdValid_fast, C0=>InitReady, + B0=>CmdUFMShift_fast, A0=>G_8_0_a3_0_0, F0=>un1_wb_rst14_i, + F1=>G_8_0_a3_0_0); + SLICE_98I: SLICE_98 + port map (D1=>S_1, C1=>CASr3, B1=>CO0, A1=>CASr2, D0=>FWEr, + C0=>nRWE_0io_RNO_2, A0=>CBR_fast, F0=>N_37_i_1, + F1=>nRWE_0io_RNO_2); + SLICE_99I: SLICE_99 + port map (D1=>FS_10, C1=>FS_12, B1=>FS_13, A1=>FS_9, D0=>FS_10, + C0=>FS_12, B0=>FS_13, A0=>FS_9, F0=>wb_dati_5_1_iv_0_a3_0_3, + F1=>wb_dati_5_1_iv_0_a3_0_0_1); + SLICE_100I: SLICE_100 + port map (D1=>FS_14, C1=>FS_13, B1=>FS_12, A1=>FS_11, D0=>FS_14, + C0=>FS_10, B0=>FS_12, A0=>FS_11, F0=>N_230, + F1=>un1_FS_40_1_1_tz); + SLICE_101I: SLICE_101 + port map (D1=>Din_c_7, C1=>Din_c_4, B1=>Din_c_3, A1=>Din_c_5, + D0=>Din_c_7, C0=>Din_c_4, B0=>Din_c_6, A0=>Din_c_5, + F0=>un1_Din_2, F1=>CmdEnable17_5); + SLICE_102I: SLICE_102 + port map (D1=>FS_16, C1=>FS_12, B1=>FS_17, A1=>FS_15, D0=>FS_16, + C0=>FS_15, B0=>FS_17, F0=>un1_FS_11, F1=>InitReady3_0_a3_2); + SLICE_103I: SLICE_103 + port map (D1=>FS_13, C1=>FS_9, B1=>FS_11, D0=>FS_13, C0=>FS_9, B0=>FS_11, + A0=>FS_14, F0=>wb_dati_5_1_iv_0_a3_3_0_7, + F1=>wb_dati_5_1_iv_0_a3_0_6); + SLICE_104I: SLICE_104 + port map (D1=>Din_c_0, C1=>Din_c_1, B1=>Din_c_6, A1=>Din_c_5, + D0=>Din_c_2, C0=>Din_c_0, B0=>Din_c_6, A0=>Din_c_1, + F0=>CmdEnable17_4, F1=>CmdEnable16_4); + SLICE_105I: SLICE_105 + port map (D1=>nFWE_c, C1=>MAin_c_6, A1=>MAin_c_0, D0=>MAin_c_1, + C0=>C1WR_0, B0=>nFWE_c, A0=>MAin_c_0, M1=>nCCAS_c_i, + M0=>nCCAS_c_i, CLK=>nCRAS_c, F0=>CMDWR_2, Q0=>CBR, F1=>ADWR_4, + Q1=>CBR_fast); + SLICE_106I: SLICE_106 + port map (D1=>Din_c_2, B1=>Din_c_3, D0=>Din_c_2, C0=>Din_c_7, + B0=>Din_c_3, A0=>Din_c_4, M0=>CASr2, CLK=>RCLK_c, + F0=>CmdEnable16_5, Q0=>CASr3, F1=>XOR8MEG9_1); + SLICE_107I: SLICE_107 + port map (C1=>nRowColSel, B1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, + A0=>RowA_9, F0=>RA_c_9, F1=>RDQMH_c); + SLICE_108I: SLICE_108 + port map (D1=>N_250, C1=>nRRAS_5_u_i_0, B1=>IS_0, A1=>N_254, D0=>Ready, + C0=>N_250, M0=>nFWE_c_i, CLK=>nCRAS_c, F0=>N_253_i, + Q0=>FWEr_fast, F1=>N_25_i); + SLICE_109I: SLICE_109 + port map (D1=>wb_rst11, A1=>FS_14, D0=>wb_rst11, C0=>FS_9, F0=>N_119, + F1=>N_246); + SLICE_110I: SLICE_110 + port map (C1=>FS_11, B1=>FS_12, D0=>FS_13, C0=>N_116, B0=>FS_12, + A0=>FS_14, F0=>wb_dati_5_0_iv_0_a3_1_0, F1=>N_228); + SLICE_111I: SLICE_111 + port map (C1=>RowA_7, B1=>nRowColSel, A1=>MAin_c_7, D0=>MAin_c_4, + C0=>MAin_c_2, B0=>MAin_c_5, A0=>MAin_c_7, F0=>ADWR_5, + F1=>RA_c_7); + SLICE_112I: SLICE_112 + port map (C1=>nRowColSel, B1=>MAin_c_9, D0=>nRowColSel, C0=>MAin_c_0, + B0=>RowA_0, F0=>RA_c_0, F1=>RDQML_c); + SLICE_113I: SLICE_113 + port map (D1=>RowA_8, C1=>MAin_c_8, A1=>nRowColSel, D0=>RowA_1, + C0=>MAin_c_1, A0=>nRowColSel, F0=>RA_c_1, F1=>RA_c_8); + SLICE_114I: SLICE_114 + port map (D1=>RowA_6, C1=>MAin_c_6, A1=>nRowColSel, C0=>MAin_c_2, + B0=>RowA_2, A0=>nRowColSel, F0=>RA_c_2, F1=>RA_c_6); + SLICE_115I: SLICE_115 + port map (D1=>RowA_5, B1=>nRowColSel, A1=>MAin_c_5, C0=>RowA_3, + B0=>MAin_c_3, A0=>nRowColSel, F0=>RA_c_3, F1=>RA_c_5); + SLICE_116I: SLICE_116 + port map (D1=>Din_c_6, C1=>n8MEGEN, B1=>Ready_fast, A1=>XOR8MEG, + B0=>Din_c_4, A0=>Din_c_6, F0=>XOR8MEG14_1, F1=>RA11d_0); + SLICE_117I: SLICE_117 + port map (D1=>S_1, C1=>CBR_fast, B1=>N_25, D0=>S_1, C0=>CO0, B0=>FWEr, + A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>N_28_i_sn); + SLICE_118I: SLICE_118 + port map (C1=>Ready_fast, B1=>CROW_c_0, C0=>Ready_fast, B0=>CROW_c_1, + M0=>PHI2r2, CLK=>RCLK_c, F0=>RBAd_0_1, Q0=>PHI2r3, + F1=>RBAd_0_0); + RD_0_I: RD_0_B + port map (PADDI=>RD_in_0, IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0)); + RD_0_MGIOLI: RD_0_MGIOL + port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c); + Dout_0_I: Dout_0_B + port map (PADDO=>RD_in_0, Dout0=>Dout(0)); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + PHI2_MGIOLI: PHI2_MGIOL + port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + nRCASI: nRCASB + port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS); + nRCAS_MGIOLI: nRCAS_MGIOL + port map (IOLDO=>nRCAS_c, OPOS=>N_249_i, CLK=>RCLK_c); + nRRASI: nRRASB + port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS); + nRRAS_MGIOLI: nRRAS_MGIOL + port map (IOLDO=>nRRAS_c, OPOS=>N_25_i, CLK=>RCLK_c); + nRWEI: nRWEB + port map (IOLDO=>nRWE_c, nRWES=>nRWE); + nRWE_MGIOLI: nRWE_MGIOL + port map (IOLDO=>nRWE_c, OPOS=>N_37_i, CLK=>RCLK_c); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + nRCSI: nRCSB + port map (IOLDO=>nRCS_c, nRCSS=>nRCS); + nRCS_MGIOLI: nRCS_MGIOL + port map (IOLDO=>nRCS_c, OPOS=>N_28_i, CLK=>RCLK_c); + RD_7_I: RD_7_B + port map (PADDI=>RD_in_7, IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7)); + RD_7_MGIOLI: RD_7_MGIOL + port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c); + RD_6_I: RD_6_B + port map (PADDI=>RD_in_6, IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6)); + RD_6_MGIOLI: RD_6_MGIOL + port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c); + RD_5_I: RD_5_B + port map (PADDI=>RD_in_5, IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5)); + RD_5_MGIOLI: RD_5_MGIOL + port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c); + RD_4_I: RD_4_B + port map (PADDI=>RD_in_4, IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4)); + RD_4_MGIOLI: RD_4_MGIOL + port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c); + RD_3_I: RD_3_B + port map (PADDI=>RD_in_3, IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3)); + RD_3_MGIOLI: RD_3_MGIOL + port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c); + RD_2_I: RD_2_B + port map (PADDI=>RD_in_2, IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2)); + RD_2_MGIOLI: RD_2_MGIOL + port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c); + RD_1_I0: RD_1_B + port map (PADDI=>RD_in_1, IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1)); + RD_1_MGIOLI: RD_1_MGIOL + port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c); + RA_11_I: RA_11_B + port map (IOLDO=>RA_c_11, RA11=>RA(11)); + RA_11_MGIOLI: RA_11_MGIOL + port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c); + RA_10_I: RA_10_B + port map (IOLDO=>RA_c_10, RA10=>RA(10)); + RA_10_MGIOLI: RA_10_MGIOL + port map (IOLDO=>RA_c_10, OPOS=>N_45, LSR=>RA10s_i, CLK=>RCLK_c); + RA_9_I: RA_9_B + port map (PADDO=>RA_c_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_c_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_c_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_c_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_c_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_c_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_c_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_c_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_c_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_c_0, RA0=>RA(0)); + RBA_1_I: RBA_1_B + port map (IOLDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_1_MGIOLI: RBA_1_MGIOL + port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c); + RBA_0_I: RBA_0_B + port map (IOLDO=>RBA_c_0, RBA0=>RBA(0)); + RBA_0_MGIOLI: RBA_0_MGIOL + port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + Dout_7_I: Dout_7_B + port map (PADDO=>RD_in_7, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>RD_in_6, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>RD_in_5, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>RD_in_4, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>RD_in_3, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>RD_in_2, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>RD_in_1, Dout1=>Dout(1)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_7_MGIOLI: Din_7_MGIOL + port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_6_MGIOLI: Din_6_MGIOL + port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_5_MGIOLI: Din_5_MGIOL + port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_4_MGIOLI: Din_4_MGIOL + port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_3_MGIOLI: Din_3_MGIOL + port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_2_MGIOLI: Din_2_MGIOL + port map (DI=>Din_c_2, CLK=>PHI2_c, INP=>Bank_2); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_1_MGIOLI: Din_1_MGIOL + port map (DI=>Din_c_1, CLK=>PHI2_c, INP=>Bank_1); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + Din_0_MGIOLI: Din_0_MGIOL + port map (DI=>Din_c_0, CLK=>PHI2_c, INP=>Bank_0); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + ufmefb_EFBInst_0I: ufmefb_EFBInst_0 + port map (WBCLKI=>RCLK_c, WBRSTI=>wb_rst, WBCYCI=>wb_cyc_stb, + WBSTBI=>wb_cyc_stb, WBWEI=>wb_we, WBADRI0=>wb_adr_0, + WBADRI1=>wb_adr_1, WBADRI2=>wb_adr_2, WBADRI3=>wb_adr_3, + WBADRI4=>wb_adr_4, WBADRI5=>wb_adr_5, WBADRI6=>wb_adr_6, + WBADRI7=>wb_adr_7, WBDATI0=>wb_dati_0, WBDATI1=>wb_dati_1, + WBDATI2=>wb_dati_2, WBDATI3=>wb_dati_3, WBDATI4=>wb_dati_4, + WBDATI5=>wb_dati_5, WBDATI6=>wb_dati_6, WBDATI7=>wb_dati_7, + WBDATO0=>wb_dato_0, WBDATO1=>wb_dato_1, WBACKO=>wb_ack); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.sdf new file mode 100644 index 0000000..45ee471 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.sdf @@ -0,0 +1,4440 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Sat Aug 19 21:55:18 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI 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PADDO Dout1 (2927:3031:3136)(2927:3031:3136)) + ) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7__MGIOL") + (INSTANCE Din\[7\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6__MGIOL") + (INSTANCE Din\[6\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5__MGIOL") + (INSTANCE Din\[5\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4__MGIOL") + (INSTANCE Din\[4\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3__MGIOL") + (INSTANCE Din\[3\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2__MGIOL") + (INSTANCE Din\[2\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1__MGIOL") + (INSTANCE Din\[1\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0__MGIOL") + (INSTANCE Din\[0\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/B1 (781:909:1037)(781:909:1037)) + (INTERCONNECT SLICE_0/Q1 SLICE_96/A0 (749:874:1000)(749:874:1000)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_39/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_49/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_49/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_54/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_54/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI SLICE_118/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT RCLK_I/PADDI + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (2813:3028:3243) + (2813:3028:3243)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_1/Q0 SLICE_47/C1 (812:966:1120)(812:966:1120)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/A1 (1011:1175:1340)(1011:1175:1340)) + (INTERCONNECT SLICE_1/Q0 SLICE_102/B1 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_1/Q0 SLICE_102/B0 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2/Q1 SLICE_47/B1 (786:914:1043)(786:914:1043)) + (INTERCONNECT SLICE_2/Q1 SLICE_76/B1 (1113:1276:1440)(1113:1276:1440)) + (INTERCONNECT SLICE_2/Q1 SLICE_102/D1 (882:979:1077)(882:979:1077)) + (INTERCONNECT SLICE_2/Q1 SLICE_102/D0 (882:979:1077)(882:979:1077)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2/Q0 SLICE_47/A1 (1446:1640:1835)(1446:1640:1835)) + (INTERCONNECT SLICE_2/Q0 SLICE_76/C1 (1247:1431:1615)(1247:1431:1615)) + (INTERCONNECT SLICE_2/Q0 SLICE_102/A1 (2137:2398:2659)(2137:2398:2659)) + (INTERCONNECT SLICE_2/Q0 SLICE_102/C0 (539:652:765)(539:652:765)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q1 SLICE_31/C1 (543:680:817)(543:680:817)) + (INTERCONNECT SLICE_3/Q1 SLICE_58/C1 (543:680:817)(543:680:817)) + (INTERCONNECT SLICE_3/Q1 SLICE_59/A0 (742:889:1037)(742:889:1037)) + (INTERCONNECT SLICE_3/Q1 SLICE_65/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3/Q1 SLICE_70/D1 (1244:1399:1555)(1244:1399:1555)) + (INTERCONNECT SLICE_3/Q1 SLICE_71/D0 (1619:1807:1995)(1619:1807:1995)) + (INTERCONNECT SLICE_3/Q1 SLICE_72/C1 (1256:1465:1675)(1256:1465:1675)) + (INTERCONNECT SLICE_3/Q1 SLICE_75/B1 (1814:2071:2329)(1814:2071:2329)) + (INTERCONNECT SLICE_3/Q1 SLICE_79/C1 (1256:1465:1675)(1256:1465:1675)) + (INTERCONNECT SLICE_3/Q1 SLICE_82/A1 (1444:1663:1882)(1444:1663:1882)) + (INTERCONNECT SLICE_3/Q1 SLICE_83/C0 (1630:1873:2116)(1630:1873:2116)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/B1 (1384:1606:1828)(1384:1606:1828)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3/Q1 SLICE_93/C0 (815:987:1159)(815:987:1159)) + (INTERCONNECT SLICE_3/Q1 SLICE_100/D1 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3/Q1 SLICE_100/D0 (1254:1410:1567)(1254:1410:1567)) + (INTERCONNECT SLICE_3/Q1 SLICE_103/A0 (1829:2082:2336)(1829:2082:2336)) + (INTERCONNECT SLICE_3/Q1 SLICE_109/A1 (1448:1668:1889)(1448:1668:1889)) + (INTERCONNECT SLICE_3/Q1 SLICE_110/A0 (1352:1571:1791)(1352:1571:1791)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q0 SLICE_31/A1 (1101:1264:1427)(1101:1264:1427)) + (INTERCONNECT SLICE_3/Q0 SLICE_58/A1 (774:902:1030)(774:902:1030)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/B1 (1981:2222:2464)(1981:2222:2464)) + (INTERCONNECT SLICE_3/Q0 SLICE_67/B1 (1518:1717:1916)(1518:1717:1916)) + (INTERCONNECT SLICE_3/Q0 SLICE_70/B1 (1986:2228:2470)(1986:2228:2470)) + (INTERCONNECT SLICE_3/Q0 SLICE_71/C0 (2483:2784:3085)(2483:2784:3085)) + (INTERCONNECT SLICE_3/Q0 SLICE_72/B1 (1191:1355:1519)(1191:1355:1519)) + (INTERCONNECT SLICE_3/Q0 SLICE_78/B0 (2366:2641:2916)(2366:2641:2916)) + (INTERCONNECT SLICE_3/Q0 SLICE_79/B1 (1191:1355:1519)(1191:1355:1519)) + (INTERCONNECT SLICE_3/Q0 SLICE_80/A1 (2281:2555:2830)(2281:2555:2830)) + (INTERCONNECT SLICE_3/Q0 SLICE_82/B1 (1657:1864:2071)(1657:1864:2071)) + (INTERCONNECT SLICE_3/Q0 SLICE_83/B0 (2693:3003:3313)(2693:3003:3313)) + (INTERCONNECT SLICE_3/Q0 SLICE_84/C1 (902:1054:1207)(902:1054:1207)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/B0 (1981:2222:2464)(1981:2222:2464)) + (INTERCONNECT SLICE_3/Q0 SLICE_93/B0 (2730:3036:3343)(2730:3036:3343)) + (INTERCONNECT SLICE_3/Q0 SLICE_99/B1 (1529:1730:1931)(1529:1730:1931)) + (INTERCONNECT SLICE_3/Q0 SLICE_99/B0 (1529:1730:1931)(1529:1730:1931)) + (INTERCONNECT SLICE_3/Q0 SLICE_100/C1 (1667:1879:2091)(1667:1879:2091)) + (INTERCONNECT SLICE_3/Q0 SLICE_103/D1 (2472:2718:2964)(2472:2718:2964)) + (INTERCONNECT SLICE_3/Q0 SLICE_103/D0 (2472:2718:2964)(2472:2718:2964)) + (INTERCONNECT SLICE_3/Q0 SLICE_110/D0 (564:626:689)(564:626:689)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_4/Q1 SLICE_58/B1 (771:903:1035)(771:903:1035)) + (INTERCONNECT SLICE_4/Q1 SLICE_65/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4/Q1 SLICE_70/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4/Q1 SLICE_71/B0 (1859:2096:2333)(1859:2096:2333)) + (INTERCONNECT SLICE_4/Q1 SLICE_72/D0 (1180:1312:1444)(1180:1312:1444)) + (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4/Q1 SLICE_78/C1 (1976:2239:2502)(1976:2239:2502)) + (INTERCONNECT SLICE_4/Q1 SLICE_80/D1 (1574:1746:1918)(1574:1746:1918)) + (INTERCONNECT SLICE_4/Q1 SLICE_81/D1 (1965:2173:2381)(1965:2173:2381)) + (INTERCONNECT SLICE_4/Q1 SLICE_82/B0 (1433:1634:1835)(1433:1634:1835)) + (INTERCONNECT SLICE_4/Q1 SLICE_83/B1 (2207:2483:2759)(2207:2483:2759)) + (INTERCONNECT SLICE_4/Q1 SLICE_86/A1 (1784:2021:2259)(1784:2021:2259)) + (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (1433:1634:1835)(1433:1634:1835)) + (INTERCONNECT SLICE_4/Q1 SLICE_99/C1 (1165:1357:1550)(1165:1357:1550)) + (INTERCONNECT SLICE_4/Q1 SLICE_99/C0 (1165:1357:1550)(1165:1357:1550)) + (INTERCONNECT SLICE_4/Q1 SLICE_100/B1 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4/Q1 SLICE_100/B0 (1489:1694:1899)(1489:1694:1899)) + (INTERCONNECT SLICE_4/Q1 SLICE_102/C1 (1566:1785:2005)(1566:1785:2005)) + (INTERCONNECT SLICE_4/Q1 SLICE_110/B1 (1058:1226:1395)(1058:1226:1395)) + (INTERCONNECT SLICE_4/Q1 SLICE_110/B0 (1058:1226:1395)(1058:1226:1395)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_4/Q0 SLICE_65/A0 (1567:1770:1973)(1567:1770:1973)) + (INTERCONNECT SLICE_4/Q0 SLICE_70/C0 (1445:1632:1819)(1445:1632:1819)) + (INTERCONNECT SLICE_4/Q0 SLICE_71/A1 (2024:2254:2485)(2024:2254:2485)) + (INTERCONNECT SLICE_4/Q0 SLICE_72/C0 (1004:1165:1326)(1004:1165:1326)) + (INTERCONNECT SLICE_4/Q0 SLICE_75/D1 (993:1099:1205)(993:1099:1205)) + (INTERCONNECT SLICE_4/Q0 SLICE_82/D0 (1721:1890:2059)(1721:1890:2059)) + (INTERCONNECT SLICE_4/Q0 SLICE_83/A1 (2351:2616:2882)(2351:2616:2882)) + (INTERCONNECT SLICE_4/Q0 SLICE_86/D1 (1357:1494:1632)(1357:1494:1632)) + (INTERCONNECT SLICE_4/Q0 SLICE_87/D0 (1428:1559:1691)(1428:1559:1691)) + (INTERCONNECT SLICE_4/Q0 SLICE_100/A1 (1573:1776:1980)(1573:1776:1980)) + (INTERCONNECT SLICE_4/Q0 SLICE_100/A0 (1573:1776:1980)(1573:1776:1980)) + (INTERCONNECT SLICE_4/Q0 SLICE_103/B1 (2056:2289:2522)(2056:2289:2522)) + (INTERCONNECT SLICE_4/Q0 SLICE_103/B0 (2056:2289:2522)(2056:2289:2522)) + (INTERCONNECT SLICE_4/Q0 SLICE_110/C1 (546:662:779)(546:662:779)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_5/Q1 SLICE_65/C1 (1364:1555:1746)(1364:1555:1746)) + (INTERCONNECT SLICE_5/Q1 SLICE_70/A0 (1665:1863:2062)(1665:1863:2062)) + (INTERCONNECT SLICE_5/Q1 SLICE_71/C1 (1830:2049:2269)(1830:2049:2269)) + (INTERCONNECT SLICE_5/Q1 SLICE_72/A0 (1199:1369:1539)(1199:1369:1539)) + (INTERCONNECT SLICE_5/Q1 SLICE_74/C1 (1466:1654:1842)(1466:1654:1842)) + (INTERCONNECT SLICE_5/Q1 SLICE_78/A1 (1665:1863:2062)(1665:1863:2062)) + (INTERCONNECT SLICE_5/Q1 SLICE_80/B1 (1697:1898:2099)(1697:1898:2099)) + (INTERCONNECT SLICE_5/Q1 SLICE_81/B1 (1697:1898:2099)(1697:1898:2099)) + (INTERCONNECT SLICE_5/Q1 SLICE_83/D1 (1455:1588:1721)(1455:1588:1721)) + (INTERCONNECT SLICE_5/Q1 SLICE_85/D0 (1353:1489:1625)(1353:1489:1625)) + (INTERCONNECT SLICE_5/Q1 SLICE_86/B1 (1595:1799:2003)(1595:1799:2003)) + (INTERCONNECT SLICE_5/Q1 SLICE_87/B1 (1042:1199:1356)(1042:1199:1356)) + (INTERCONNECT SLICE_5/Q1 SLICE_99/D1 (989:1093:1198)(989:1093:1198)) + (INTERCONNECT SLICE_5/Q1 SLICE_99/D0 (989:1093:1198)(989:1093:1198)) + (INTERCONNECT SLICE_5/Q1 SLICE_100/C0 (1175:1350:1526)(1175:1350:1526)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_5/Q0 SLICE_65/A1 (1885:2121:2357)(1885:2121:2357)) + (INTERCONNECT SLICE_5/Q0 SLICE_65/C0 (1359:1549:1740)(1359:1549:1740)) + (INTERCONNECT SLICE_5/Q0 SLICE_67/C1 (1005:1165:1325)(1005:1165:1325)) + (INTERCONNECT SLICE_5/Q0 SLICE_72/B0 (1563:1771:1979)(1563:1771:1979)) + (INTERCONNECT SLICE_5/Q0 SLICE_78/B1 (1226:1398:1570)(1226:1398:1570)) + (INTERCONNECT SLICE_5/Q0 SLICE_80/C1 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5/Q0 SLICE_85/A0 (1901:2138:2376)(1901:2138:2376)) + (INTERCONNECT SLICE_5/Q0 SLICE_86/C1 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5/Q0 SLICE_87/D1 (796:890:985)(796:890:985)) + (INTERCONNECT SLICE_5/Q0 SLICE_99/A1 (1443:1639:1835)(1443:1639:1835)) + (INTERCONNECT SLICE_5/Q0 SLICE_99/A0 (1443:1639:1835)(1443:1639:1835)) + (INTERCONNECT SLICE_5/Q0 SLICE_103/C1 (1365:1556:1747)(1365:1556:1747)) + (INTERCONNECT SLICE_5/Q0 SLICE_103/C0 (1365:1556:1747)(1365:1556:1747)) + (INTERCONNECT SLICE_5/Q0 SLICE_109/C0 (1375:1567:1759)(1375:1567:1759)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6/Q1 SLICE_96/C1 (803:944:1086)(803:944:1086)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6/Q0 SLICE_35/A1 (1177:1341:1505)(1177:1341:1505)) + (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_7/Q1 SLICE_96/D1 (526:578:630)(526:578:630)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_7/Q0 SLICE_53/C1 (871:1020:1170)(871:1020:1170)) + (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_8/Q1 SLICE_53/A1 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_8/Q0 SLICE_35/D1 (1223:1345:1467)(1223:1345:1467)) + (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_9/Q1 SLICE_53/B1 (1102:1264:1427)(1102:1264:1427)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_9/Q0 SLICE_96/A1 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 SLICE_10/D1 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_94/F0 SLICE_10/C1 (911:1055:1200)(911:1055:1200)) + (INTERCONNECT SLICE_94/F0 SLICE_90/C0 (1275:1451:1627)(1275:1451:1627)) + (INTERCONNECT SLICE_91/F0 SLICE_10/B1 (777:908:1040)(777:908:1040)) + (INTERCONNECT SLICE_91/F0 SLICE_90/B1 (767:894:1021)(767:894:1021)) + (INTERCONNECT SLICE_91/F0 SLICE_91/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_104/F0 SLICE_10/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_10/F1 SLICE_10/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_10/F1 SLICE_17/B0 (775:903:1032)(775:903:1032)) + (INTERCONNECT SLICE_91/F1 SLICE_10/C0 (537:645:753)(537:645:753)) + (INTERCONNECT SLICE_91/F1 SLICE_11/A0 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_11/F1 SLICE_10/B0 (770:894:1018)(770:894:1018)) + (INTERCONNECT SLICE_11/F1 SLICE_11/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_11/F1 SLICE_17/M0 (490:537:585)(490:537:585)) + (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_10/Q0 SLICE_17/D1 (860:954:1049)(860:954:1049)) + (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_17/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_25/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_46/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[6\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[5\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[4\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[3\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) + (INTERCONNECT SLICE_92/F0 SLICE_11/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_92/F0 SLICE_90/A1 (1081:1244:1407)(1081:1244:1407)) + (INTERCONNECT SLICE_92/F0 SLICE_91/A1 (1081:1244:1407)(1081:1244:1407)) + (INTERCONNECT SLICE_104/F1 SLICE_11/C1 (975:1126:1278)(975:1126:1278)) + (INTERCONNECT SLICE_90/F0 SLICE_11/B1 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_90/F0 SLICE_24/B1 (774:907:1040)(774:907:1040)) + (INTERCONNECT SLICE_90/F0 SLICE_73/D0 (532:597:662)(532:597:662)) + (INTERCONNECT SLICE_90/F0 SLICE_90/C1 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_90/F0 SLICE_91/B1 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_106/F0 SLICE_11/A1 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_11/Q0 SLICE_17/C0 (1234:1411:1588)(1234:1411:1588)) + (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_12/A0 (3665:4068:4471)(3665:4068:4471)) + (INTERCONNECT nCCAS_I/PADDI SLICE_26/C1 (3200:3558:3916)(3200:3558:3916)) + (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[5\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[4\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[3\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (2813:3079:3345)(2813:3079:3345)) + (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (3:6:9)(3:6:9)) + (INTERCONNECT SLICE_12/F0 SLICE_105/M0 (499:545:592)(499:545:592)) + (INTERCONNECT SLICE_12/F0 SLICE_105/M1 (499:545:592)(499:545:592)) + (INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (485:526:568)(485:526:568)) + (INTERCONNECT SLICE_12/Q1 SLICE_88/C0 (919:1066:1213)(919:1066:1213)) + (INTERCONNECT SLICE_12/Q1 SLICE_98/A1 (1445:1637:1830)(1445:1637:1830)) + (INTERCONNECT SLICE_12/Q1 SLICE_106/M0 (488:531:575)(488:531:575)) + (INTERCONNECT SLICE_12/Q1 SLICE_117/A0 (1482:1671:1860)(1482:1671:1860)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/D0 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_16/Q0 SLICE_45/C0 (813:959:1105)(813:959:1105)) + (INTERCONNECT SLICE_16/Q0 SLICE_48/A0 (743:876:1010)(743:876:1010)) + (INTERCONNECT SLICE_16/Q0 SLICE_63/C1 (559:677:795)(559:677:795)) + (INTERCONNECT SLICE_16/Q0 SLICE_69/A0 (743:876:1010)(743:876:1010)) + (INTERCONNECT SLICE_16/Q0 SLICE_88/D0 (537:600:664)(537:600:664)) + (INTERCONNECT SLICE_16/Q0 SLICE_98/B1 (1371:1565:1759)(1371:1565:1759)) + (INTERCONNECT SLICE_16/Q0 SLICE_117/C0 (544:667:790)(544:667:790)) + (INTERCONNECT SLICE_30/Q0 SLICE_16/C1 (550:665:780)(550:665:780)) + (INTERCONNECT SLICE_30/Q0 SLICE_28/B1 (1215:1382:1549)(1215:1382:1549)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/D0 (973:1072:1171)(973:1072:1171)) + (INTERCONNECT SLICE_30/Q0 SLICE_77/C1 (550:665:780)(550:665:780)) + (INTERCONNECT SLICE_34/Q1 SLICE_16/B1 (1602:1805:2009)(1602:1805:2009)) + (INTERCONNECT SLICE_34/Q1 SLICE_16/LSR (1706:1880:2055)(1706:1880:2055)) + (INTERCONNECT SLICE_34/Q1 SLICE_35/M0 (1097:1211:1325)(1097:1211:1325)) + (INTERCONNECT SLICE_34/Q1 SLICE_36/C1 (1735:1957:2179)(1735:1957:2179)) + (INTERCONNECT SLICE_34/Q1 SLICE_37/D0 (1132:1257:1383)(1132:1257:1383)) + (INTERCONNECT SLICE_34/Q1 SLICE_45/A1 (1010:1164:1319)(1010:1164:1319)) + (INTERCONNECT SLICE_34/Q1 SLICE_45/LSR (1146:1274:1402)(1146:1274:1402)) + (INTERCONNECT SLICE_34/Q1 SLICE_63/A1 (1570:1771:1972)(1570:1771:1972)) + (INTERCONNECT SLICE_34/Q1 SLICE_64/C0 (991:1148:1306)(991:1148:1306)) + (INTERCONNECT SLICE_34/Q1 SLICE_69/A1 (1184:1351:1519)(1184:1351:1519)) + (INTERCONNECT SLICE_45/Q0 SLICE_16/A1 (1028:1196:1364)(1028:1196:1364)) + (INTERCONNECT SLICE_45/Q0 SLICE_16/A0 (1028:1196:1364)(1028:1196:1364)) + (INTERCONNECT SLICE_45/Q0 SLICE_45/D0 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_45/Q0 SLICE_48/D0 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_45/Q0 SLICE_63/D1 (818:920:1023)(818:920:1023)) + (INTERCONNECT SLICE_45/Q0 SLICE_63/D0 (818:920:1023)(818:920:1023)) + (INTERCONNECT SLICE_45/Q0 SLICE_66/D1 (531:597:663)(531:597:663)) + (INTERCONNECT SLICE_45/Q0 SLICE_66/D0 (531:597:663)(531:597:663)) + (INTERCONNECT SLICE_45/Q0 SLICE_69/B0 (770:892:1014)(770:892:1014)) + (INTERCONNECT SLICE_45/Q0 SLICE_98/D1 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_45/Q0 SLICE_117/D1 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_45/Q0 SLICE_117/D0 (1193:1328:1463)(1193:1328:1463)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F1 SLICE_38/B0 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_16/F1 SLICE_39/B1 (775:903:1032)(775:903:1032)) + (INTERCONNECT SLICE_17/Q0 SLICE_17/B1 (767:892:1017)(767:892:1017)) + (INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_17/Q0 SLICE_24/C1 (541:656:771)(541:656:771)) + (INTERCONNECT SLICE_17/Q0 SLICE_73/A0 (740:865:991)(740:865:991)) + (INTERCONNECT SLICE_90/F1 SLICE_17/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_17/OFX0 SLICE_17/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_18/D1 (532:597:662)(532:597:662)) + (INTERCONNECT SLICE_23/F1 SLICE_20/B0 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_23/F1 SLICE_21/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23/F1 SLICE_22/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23/F1 SLICE_23/B0 (790:924:1058)(790:924:1058)) + (INTERCONNECT SLICE_23/F1 SLICE_24/A0 (483:582:681)(483:582:681)) + (INTERCONNECT SLICE_23/F1 SLICE_25/D1 (532:597:662)(532:597:662)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_18/C1 (1536:1702:1869)(1536:1702:1869)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/C0 (1916:2115:2315)(1916:2115:2315)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/D0 (1905:2049:2194)(1905:2049:2194)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_22/A1 (2115:2325:2535)(2115:2325:2535)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_46/C1 (2656:2919:3183)(2656:2919:3183)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_104/C1 (3353:3683:4014)(3353:3683:4014)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_104/A0 (3225:3531:3837)(3225:3531:3837)) + (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (3120:3370:3621)(3120:3370:3621)) + (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_18/Q0 SLICE_18/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_18/Q0 SLICE_32/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_73/F1 SLICE_18/B0 (1044:1206:1368)(1044:1206:1368)) + (INTERCONNECT SLICE_73/F1 SLICE_20/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73/F1 SLICE_21/C0 (881:1038:1195)(881:1038:1195)) + (INTERCONNECT SLICE_73/F1 SLICE_22/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73/F1 SLICE_23/D0 (891:997:1103)(891:997:1103)) + (INTERCONNECT SLICE_73/F1 SLICE_24/D0 (273:306:340)(273:306:340)) + (INTERCONNECT SLICE_73/F1 SLICE_25/D0 (1129:1258:1387)(1129:1258:1387)) + (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_32/Q0 SLICE_18/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_32/Q0 SLICE_34/C1 (809:951:1093)(809:951:1093)) + (INTERCONNECT SLICE_32/Q0 SLICE_46/A1 (1008:1160:1313)(1008:1160:1313)) + (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_18/CE (945:1046:1148)(945:1046:1148)) + (INTERCONNECT SLICE_24/F1 SLICE_20/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24/F1 SLICE_21/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24/F1 SLICE_22/CE (575:644:714)(575:644:714)) + (INTERCONNECT SLICE_24/F1 SLICE_23/C0 (567:687:808)(567:687:808)) + (INTERCONNECT SLICE_24/F1 SLICE_24/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_24/F1 SLICE_25/CE (945:1046:1148)(945:1046:1148)) + (INTERCONNECT SLICE_24/F1 SLICE_46/CE (544:607:670)(544:607:670)) + (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_20/Q0 wb_cyc_stb_RNO\/SLICE_61/B1 (770:892:1014)(770:892:1014)) + (INTERCONNECT SLICE_20/Q0 SLICE_95/C0 (539:648:757)(539:648:757)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_21/Q0 SLICE_21/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_21/Q0 SLICE_97/B0 (775:902:1030)(775:902:1030)) + (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_22/C1 (2041:2255:2470)(2041:2255:2470)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_25/C1 (1590:1776:1963)(1590:1776:1963)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_46/B1 (2653:2913:3174)(2653:2913:3174)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_73/M0 (2703:2919:3135)(2703:2919:3135)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_104/D1 (3164:3436:3708)(3164:3436:3708)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_104/C0 (2848:3140:3432)(2848:3140:3432)) + (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (2849:3087:3325)(2849:3087:3325)) + (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_22/F1 SLICE_22/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_22/Q0 wb_cyc_stb_RNO\/SLICE_61/C1 (544:658:773)(544:658:773)) + (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_23/D1 (1994:2141:2289)(1994:2141:2289)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/C1 (2349:2589:2829)(2349:2589:2829)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/C0 (2349:2589:2829)(2349:2589:2829)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_106/A0 (2950:3227:3505)(2950:3227:3505)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_116/B0 (2612:2860:3108)(2612:2860:3108)) + (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (4276:4628:4981)(4276:4628:4981)) + (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_23/C1 (2329:2578:2828)(2329:2578:2828)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_73/D1 (2645:2874:3104)(2645:2874:3104)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/D1 (3020:3283:3546)(3020:3283:3546)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/D0 (3020:3283:3546)(3020:3283:3546)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_106/C0 (2699:2980:3262)(2699:2980:3262)) + (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (3911:4259:4607)(3911:4259:4607)) + (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_23/B1 (1882:2067:2252)(1882:2067:2252)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_73/A1 (2214:2428:2642)(2214:2428:2642)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/A1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/A0 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_104/A1 (2225:2440:2655)(2225:2440:2655)) + (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (2982:3212:3442)(2982:3212:3442)) + (INTERCONNECT Din\[5\]_I/PADDI Din\[5\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_23/A1 (2235:2458:2682)(2235:2458:2682)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_101/B0 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/B1 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/B0 (2734:2989:3245)(2734:2989:3245)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_116/D1 (3641:3936:4231)(3641:3936:4231)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_116/A0 (3072:3357:3642)(3072:3357:3642)) + (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (3403:3658:3913)(3403:3658:3913)) + (INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/Q0 SLICE_59/B1 (1110:1271:1433)(1110:1271:1433)) + (INTERCONNECT SLICE_23/Q0 wb_cyc_stb_RNO\/SLICE_61/D1 (541:599:658)(541:599:658)) + (INTERCONNECT SLICE_23/Q0 SLICE_95/D0 (541:599:658)(541:599:658)) + (INTERCONNECT SLICE_105/F0 SLICE_24/A1 (751:875:999)(751:875:999)) + (INTERCONNECT SLICE_105/F0 SLICE_73/C0 (879:1027:1176)(879:1027:1176)) + (INTERCONNECT SLICE_105/F0 SLICE_90/D1 (868:961:1055)(868:961:1055)) + (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/Q0 SLICE_62/B1 (1105:1266:1427)(1105:1266:1427)) + (INTERCONNECT SLICE_24/Q0 SLICE_97/D0 (1227:1351:1476)(1227:1351:1476)) + (INTERCONNECT SLICE_25/Q0 SLICE_25/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_25/Q0 SLICE_47/A0 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_47/Q0 SLICE_25/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_47/Q0 SLICE_116/C1 (1233:1414:1595)(1233:1414:1595)) + (INTERCONNECT SLICE_25/F1 SLICE_25/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_26/D1 (2286:2472:2659)(2286:2472:2659)) + (INTERCONNECT nFWE_I/PADDI SLICE_26/C0 (1970:2176:2383)(1970:2176:2383)) + (INTERCONNECT nFWE_I/PADDI SLICE_92/D0 (1851:2013:2175)(1851:2013:2175)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/D1 (1851:2013:2175)(1851:2013:2175)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/B0 (2082:2310:2538)(2082:2310:2538)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (3:6:9)(3:6:9)) + (INTERCONNECT SLICE_26/F0 SLICE_108/M0 (1515:1661:1808)(1515:1661:1808)) + (INTERCONNECT nCRAS_I/PADDI SLICE_26/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_34/D1 (3175:3429:3683)(3175:3429:3683)) + (INTERCONNECT nCRAS_I/PADDI SLICE_34/D0 (3175:3429:3683)(3175:3429:3683)) + (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_44/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_44/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_105/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_105/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI SLICE_108/CLK (2925:3147:3369)(2925:3147:3369)) + (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (3072:3306:3541)(3072:3306:3541)) + (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (3072:3306:3541)(3072:3306:3541)) + (INTERCONNECT SLICE_26/Q0 SLICE_48/C1 (984:1138:1292)(984:1138:1292)) + (INTERCONNECT SLICE_26/Q0 SLICE_98/D0 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_26/Q0 SLICE_117/B0 (1215:1382:1549)(1215:1382:1549)) + (INTERCONNECT SLICE_26/F1 RD\[0\]_I/PADDT (950:1056:1162)(950:1056:1162)) + (INTERCONNECT SLICE_26/F1 RD\[7\]_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26/F1 RD\[6\]_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26/F1 RD\[5\]_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26/F1 RD\[4\]_I/PADDT (1330:1469:1608)(1330:1469:1608)) + (INTERCONNECT SLICE_26/F1 RD\[3\]_I/PADDT (675:751:828)(675:751:828)) + (INTERCONNECT SLICE_26/F1 RD\[2\]_I/PADDT (675:751:828)(675:751:828)) + (INTERCONNECT SLICE_26/F1 RD\[1\]_I/PADDT (950:1056:1162)(950:1056:1162)) + (INTERCONNECT SLICE_28/Q0 SLICE_28/D1 (538:599:660)(538:599:660)) + (INTERCONNECT SLICE_28/Q0 SLICE_28/D0 (538:599:660)(538:599:660)) + (INTERCONNECT SLICE_28/Q0 SLICE_29/C1 (543:660:777)(543:660:777)) + (INTERCONNECT SLICE_28/Q0 SLICE_29/C0 (543:660:777)(543:660:777)) + (INTERCONNECT SLICE_28/Q0 SLICE_30/C0 (886:1040:1195)(886:1040:1195)) + (INTERCONNECT SLICE_28/Q0 SLICE_38/C1 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_28/Q0 SLICE_68/B0 (1524:1720:1916)(1524:1720:1916)) + (INTERCONNECT SLICE_28/Q0 SLICE_77/A0 (1492:1685:1879)(1492:1685:1879)) + (INTERCONNECT SLICE_28/Q0 SLICE_108/B1 (772:896:1020)(772:896:1020)) + (INTERCONNECT SLICE_38/Q0 SLICE_28/C1 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_38/Q0 SLICE_28/C0 (559:678:798)(559:678:798)) + (INTERCONNECT SLICE_38/Q0 SLICE_36/D1 (906:1009:1113)(906:1009:1113)) + (INTERCONNECT SLICE_38/Q0 SLICE_36/A0 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38/Q0 SLICE_38/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_38/Q0 SLICE_39/A1 (737:861:986)(737:861:986)) + (INTERCONNECT SLICE_38/Q0 SLICE_45/B1 (1174:1340:1506)(1174:1340:1506)) + (INTERCONNECT SLICE_38/Q0 SLICE_48/A1 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38/Q0 SLICE_48/C0 (906:1062:1219)(906:1062:1219)) + (INTERCONNECT SLICE_38/Q0 SLICE_63/A0 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38/Q0 SLICE_64/D1 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_38/Q0 SLICE_64/D0 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_38/Q0 SLICE_68/A1 (778:910:1042)(778:910:1042)) + (INTERCONNECT SLICE_38/Q0 SLICE_69/D0 (906:1009:1113)(906:1009:1113)) + (INTERCONNECT SLICE_38/Q0 SLICE_88/A1 (1128:1290:1452)(1128:1290:1452)) + (INTERCONNECT SLICE_38/Q0 SLICE_108/D0 (1266:1401:1537)(1266:1401:1537)) + (INTERCONNECT SLICE_63/F1 SLICE_28/A1 (1014:1176:1339)(1014:1176:1339)) + (INTERCONNECT SLICE_63/F1 SLICE_28/A0 (1014:1176:1339)(1014:1176:1339)) + (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (286:377:469)(286:377:469)) + (INTERCONNECT SLICE_63/F1 SLICE_68/A0 (485:587:689)(485:587:689)) + (INTERCONNECT SLICE_63/F1 SLICE_77/C0 (540:660:780)(540:660:780)) + (INTERCONNECT SLICE_63/F1 SLICE_108/D1 (872:977:1082)(872:977:1082)) + (INTERCONNECT SLICE_63/F1 SLICE_108/C0 (556:681:806)(556:681:806)) + (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/F1 RA\[10\]_MGIOL/LSR (1427:1573:1720)(1427:1573:1720)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_29/Q0 SLICE_38/D1 (548:611:674)(548:611:674)) + (INTERCONNECT SLICE_29/Q0 SLICE_68/C0 (881:1035:1189)(881:1035:1189)) + (INTERCONNECT SLICE_29/Q0 SLICE_77/D1 (543:607:671)(543:607:671)) + (INTERCONNECT SLICE_29/Q1 SLICE_29/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_29/Q1 SLICE_30/A1 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29/Q1 SLICE_30/A0 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29/Q1 SLICE_38/A1 (756:882:1009)(756:882:1009)) + (INTERCONNECT SLICE_29/Q1 SLICE_68/D0 (530:590:650)(530:590:650)) + (INTERCONNECT SLICE_29/Q1 SLICE_77/B1 (772:900:1028)(772:900:1028)) + (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F0 SLICE_29/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_108/F0 SLICE_29/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_108/F0 SLICE_30/CE (1146:1271:1397)(1146:1271:1397)) + (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F1 RA\[10\]_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT SLICE_71/F1 SLICE_31/D1 (794:887:981)(794:887:981)) + (INTERCONNECT SLICE_71/F1 SLICE_71/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_71/F1 SLICE_110/C0 (539:653:767)(539:653:767)) + (INTERCONNECT SLICE_102/F1 SLICE_31/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_31/F1 SLICE_31/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (489:591:693)(489:591:693)) + (INTERCONNECT SLICE_31/Q0 SLICE_32/D0 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31/Q0 SLICE_36/B1 (1481:1681:1882)(1481:1681:1882)) + (INTERCONNECT SLICE_31/Q0 SLICE_38/D0 (1609:1773:1938)(1609:1773:1938)) + (INTERCONNECT SLICE_31/Q0 SLICE_39/D1 (1609:1773:1938)(1609:1773:1938)) + (INTERCONNECT SLICE_31/Q0 SLICE_47/D1 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31/Q0 SLICE_47/D0 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31/Q0 SLICE_49/B1 (1591:1799:2007)(1591:1799:2007)) + (INTERCONNECT SLICE_31/Q0 SLICE_49/B0 (1591:1799:2007)(1591:1799:2007)) + (INTERCONNECT SLICE_31/Q0 SLICE_50/A1 (1559:1764:1970)(1559:1764:1970)) + (INTERCONNECT SLICE_31/Q0 SLICE_50/A0 (1559:1764:1970)(1559:1764:1970)) + (INTERCONNECT SLICE_31/Q0 SLICE_51/C1 (1360:1555:1750)(1360:1555:1750)) + (INTERCONNECT SLICE_31/Q0 SLICE_51/C0 (1360:1555:1750)(1360:1555:1750)) + (INTERCONNECT SLICE_31/Q0 SLICE_52/D1 (1349:1489:1629)(1349:1489:1629)) + (INTERCONNECT SLICE_31/Q0 SLICE_52/D0 (1349:1489:1629)(1349:1489:1629)) + (INTERCONNECT SLICE_31/Q0 SLICE_54/B0 (816:956:1097)(816:956:1097)) + (INTERCONNECT SLICE_31/Q0 SLICE_55/A0 (1159:1329:1500)(1159:1329:1500)) + (INTERCONNECT SLICE_31/Q0 SLICE_56/C1 (960:1120:1280)(960:1120:1280)) + (INTERCONNECT SLICE_31/Q0 SLICE_56/C0 (960:1120:1280)(960:1120:1280)) + (INTERCONNECT SLICE_31/Q0 SLICE_59/C1 (555:677:799)(555:677:799)) + (INTERCONNECT SLICE_31/Q0 SLICE_60/B0 (816:956:1097)(816:956:1097)) + (INTERCONNECT SLICE_31/Q0 wb_cyc_stb_RNO\/SLICE_61/M0 (866:965:1064)(866:965:1064)) + (INTERCONNECT SLICE_31/Q0 SLICE_62/A1 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31/Q0 SLICE_62/A0 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31/Q0 SLICE_63/B1 (1546:1757:1969)(1546:1757:1969)) + (INTERCONNECT SLICE_31/Q0 SLICE_74/B0 (1555:1759:1964)(1555:1759:1964)) + (INTERCONNECT SLICE_31/Q0 SLICE_75/A0 (784:922:1060)(784:922:1060)) + (INTERCONNECT SLICE_31/Q0 SLICE_76/D1 (954:1059:1165)(954:1059:1165)) + (INTERCONNECT SLICE_31/Q0 SLICE_79/D0 (574:646:719)(574:646:719)) + (INTERCONNECT SLICE_31/Q0 SLICE_81/D0 (949:1054:1159)(949:1054:1159)) + (INTERCONNECT SLICE_31/Q0 SLICE_89/D0 (536:598:660)(536:598:660)) + (INTERCONNECT SLICE_31/Q0 SLICE_95/A0 (1111:1287:1463)(1111:1287:1463)) + (INTERCONNECT SLICE_31/Q0 SLICE_97/C0 (555:677:799)(555:677:799)) + (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_32/A0 (1806:2010:2215) + (1806:2010:2215)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_32/CE (1138:1264:1391)(1138:1264:1391)) + (INTERCONNECT SLICE_62/F1 SLICE_47/CE (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_105/Q0 SLICE_34/A1 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_105/Q0 SLICE_36/D0 (866:961:1056)(866:961:1056)) + (INTERCONNECT SLICE_105/Q0 SLICE_48/B1 (1108:1271:1434)(1108:1271:1434)) + (INTERCONNECT SLICE_105/Q0 SLICE_66/A1 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/Q0 SLICE_34/M1 (488:531:575)(488:531:575)) + (INTERCONNECT SLICE_34/Q0 SLICE_37/B0 (775:902:1030)(775:902:1030)) + (INTERCONNECT SLICE_34/F1 LED_I/PADDO (936:1038:1140)(936:1038:1140)) + (INTERCONNECT SLICE_42/Q0 SLICE_35/D0 (530:587:645)(530:587:645)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_35/C0 (1975:2181:2387)(1975:2181:2387)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_42/C0 (2339:2576:2814)(2339:2576:2814)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_92/D1 (2692:2906:3120)(2692:2906:3120)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_111/D0 (2291:2477:2663)(2291:2477:2663)) + (INTERCONNECT SLICE_48/Q0 SLICE_35/A0 (1183:1347:1512)(1183:1347:1512)) + (INTERCONNECT SLICE_48/Q0 SLICE_107/C1 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48/Q0 SLICE_107/C0 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48/Q0 SLICE_111/B1 (1590:1789:1989)(1590:1789:1989)) + (INTERCONNECT SLICE_48/Q0 SLICE_112/C1 (999:1154:1310)(999:1154:1310)) + (INTERCONNECT SLICE_48/Q0 SLICE_112/D0 (1315:1450:1586)(1315:1450:1586)) + (INTERCONNECT SLICE_48/Q0 SLICE_113/A1 (1568:1766:1964)(1568:1766:1964)) + (INTERCONNECT SLICE_48/Q0 SLICE_113/A0 (1568:1766:1964)(1568:1766:1964)) + (INTERCONNECT SLICE_48/Q0 SLICE_114/A1 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT SLICE_48/Q0 SLICE_114/A0 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT SLICE_48/Q0 SLICE_115/B1 (1590:1789:1989)(1590:1789:1989)) + (INTERCONNECT SLICE_48/Q0 SLICE_115/A0 (1906:2142:2378)(1906:2142:2378)) + (INTERCONNECT PHI2_MGIOL/IN SLICE_35/M1 (1442:1578:1714)(1442:1578:1714)) + (INTERCONNECT SLICE_35/F0 RA\[4\]_I/PADDO (1552:1738:1924)(1552:1738:1924)) + (INTERCONNECT SLICE_35/Q0 SLICE_37/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_35/F1 SLICE_53/D1 (1220:1340:1460)(1220:1340:1460)) + (INTERCONNECT SLICE_35/Q1 SLICE_59/A1 (1188:1353:1518)(1188:1353:1518)) + (INTERCONNECT SLICE_35/Q1 SLICE_95/A1 (1552:1748:1945)(1552:1748:1945)) + (INTERCONNECT SLICE_35/Q1 SLICE_97/C1 (989:1143:1298)(989:1143:1298)) + (INTERCONNECT SLICE_35/Q1 SLICE_118/M0 (825:908:991)(825:908:991)) + (INTERCONNECT SLICE_45/F0 SLICE_36/A1 (740:864:989)(740:864:989)) + (INTERCONNECT SLICE_45/F0 SLICE_45/C1 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (7:16:25)(7:16:25)) + (INTERCONNECT SLICE_45/F0 SLICE_64/A0 (483:582:681)(483:582:681)) + (INTERCONNECT SLICE_117/F0 SLICE_36/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_36/F1 SLICE_36/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_37/C0 (975:1126:1278)(975:1126:1278)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_37/D1 (1406:1542:1678)(1406:1542:1678)) + (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_37/C1 (1161:1328:1496)(1161:1328:1496)) + (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_37/B1 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_37/A1 (1687:1900:2113)(1687:1900:2113)) + (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_45/D1 (975:1073:1172)(975:1073:1172)) + (INTERCONNECT SLICE_37/Q0 SLICE_69/D1 (975:1073:1172)(975:1073:1172)) + (INTERCONNECT SLICE_37/Q0 RCKE_I/PADDO (1905:2099:2293)(1905:2099:2293)) + (INTERCONNECT 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SLICE_75/F1 SLICE_78/C0 (541:655:769)(541:655:769)) + (INTERCONNECT SLICE_99/F1 SLICE_54/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_99/F1 SLICE_57/C0 (871:1021:1172)(871:1021:1172)) + (INTERCONNECT SLICE_110/F0 SLICE_54/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_60/Q0 SLICE_54/C0 (981:1133:1285)(981:1133:1285)) + (INTERCONNECT SLICE_60/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin + (2142:2348:2554)(2142:2348:2554)) + (INTERCONNECT SLICE_109/F0 SLICE_54/A0 (1008:1161:1315)(1008:1161:1315)) + (INTERCONNECT SLICE_109/F0 SLICE_57/A1 (1378:1563:1749)(1378:1563:1749)) + (INTERCONNECT SLICE_109/F0 SLICE_70/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_109/F0 SLICE_83/A0 (1378:1563:1749)(1378:1563:1749)) + (INTERCONNECT SLICE_54/F1 SLICE_54/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54/F0 SLICE_54/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54/Q0 SLICE_79/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_54/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1411:1555:1700) + (1411:1555:1700)) + (INTERCONNECT SLICE_54/Q1 SLICE_55/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_54/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1339:1476:1613) + (1339:1476:1613)) + (INTERCONNECT SLICE_75/F0 SLICE_55/C1 (541:653:766)(541:653:766)) + (INTERCONNECT SLICE_82/F0 SLICE_55/B1 (1472:1667:1863)(1472:1667:1863)) + (INTERCONNECT SLICE_82/F0 SLICE_67/C0 (914:1061:1209)(914:1061:1209)) + (INTERCONNECT SLICE_82/F0 SLICE_76/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_67/F0 SLICE_55/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_67/F0 SLICE_56/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_72/F1 SLICE_55/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72/F1 SLICE_56/B1 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_55/F1 SLICE_55/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55/F0 SLICE_55/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55/Q0 SLICE_75/B0 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_55/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1339:1476:1613) + (1339:1476:1613)) + (INTERCONNECT SLICE_55/Q1 SLICE_56/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_55/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (1084:1193:1303) + (1084:1193:1303)) + (INTERCONNECT SLICE_56/Q0 SLICE_56/A1 (1110:1265:1420)(1110:1265:1420)) + (INTERCONNECT SLICE_56/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_76/F0 SLICE_56/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_80/F0 SLICE_56/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_56/F1 SLICE_56/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q1 SLICE_74/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_56/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (908:1009:1111) + (908:1009:1111)) + (INTERCONNECT SLICE_78/F0 SLICE_57/D1 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_71/F0 SLICE_57/C1 (1231:1406:1581)(1231:1406:1581)) + (INTERCONNECT SLICE_81/F0 SLICE_57/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_74/F0 SLICE_57/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_57/F1 SLICE_57/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_81/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_57/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_58/F1 SLICE_58/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_58/F1 SLICE_93/A1 (1177:1342:1507)(1177:1342:1507)) + (INTERCONNECT SLICE_59/F1 SLICE_58/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_59/F1 SLICE_59/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_58/Q0 SLICE_58/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_58/Q0 SLICE_89/A1 (738:857:977)(738:857:977)) + (INTERCONNECT SLICE_58/Q0 SLICE_96/B0 (777:906:1036)(777:906:1036)) + (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/Q0 SLICE_59/D1 (975:1072:1170)(975:1072:1170)) + (INTERCONNECT SLICE_118/Q0 SLICE_95/B1 (1581:1778:1975)(1581:1778:1975)) + (INTERCONNECT SLICE_118/Q0 SLICE_97/B1 (1217:1382:1548)(1217:1382:1548)) + (INTERCONNECT SLICE_59/Q0 SLICE_59/C0 (1426:1605:1785)(1426:1605:1785)) + (INTERCONNECT SLICE_59/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin + (1616:1766:1917)(1616:1766:1917)) + (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_60/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_84/F1 SLICE_62/D0 (794:884:975)(794:884:975)) + (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_87/F0 SLICE_60/A1 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_87/F0 SLICE_84/A0 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_73/Q0 SLICE_60/D0 (1153:1269:1385)(1153:1269:1385)) + (INTERCONNECT SLICE_93/F1 SLICE_60/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_60/F1 SLICE_60/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 wb_cyc_stb_RNO\/SLICE_61/A1 (481:577:673)(481:577:673)) + (INTERCONNECT SLICE_95/F1 SLICE_62/D1 (525:584:643)(525:584:643)) + (INTERCONNECT SLICE_95/F1 SLICE_95/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_89/F0 wb_cyc_stb_RNO\/SLICE_61/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_102/F0 wb_cyc_stb_RNO\/SLICE_61/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_102/F0 SLICE_62/C0 (280:362:445)(280:362:445)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO wb_cyc_stb_RNO\/SLICE_61/A0 + (1729:1940:2151)(1729:1940:2151)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_62/B0 (1761:1974:2188) + (1761:1974:2188)) + (INTERCONNECT SLICE_62/F0 SLICE_62/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_77/F1 SLICE_63/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_77/F1 SLICE_108/A1 (745:874:1003)(745:874:1003)) + (INTERCONNECT SLICE_63/F0 SLICE_66/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_64/F0 SLICE_64/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_64/F0 SLICE_66/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_98/F0 SLICE_64/B1 (1099:1259:1420)(1099:1259:1420)) + (INTERCONNECT SLICE_68/F1 SLICE_64/A1 (740:863:986)(740:863:986)) + (INTERCONNECT SLICE_105/Q1 SLICE_64/B0 (1472:1666:1861)(1472:1666:1861)) + (INTERCONNECT SLICE_105/Q1 SLICE_98/A0 (1113:1270:1427)(1113:1270:1427)) + (INTERCONNECT SLICE_105/Q1 SLICE_117/C1 (537:644:751)(537:644:751)) + (INTERCONNECT SLICE_64/F1 nRWE_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT SLICE_65/F0 SLICE_65/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_65/F1 SLICE_85/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_88/F0 SLICE_66/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_88/F0 SLICE_88/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_66/F0 nRCAS_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) + (INTERCONNECT SLICE_100/F0 SLICE_67/A1 (1067:1225:1383)(1067:1225:1383)) + (INTERCONNECT SLICE_69/F1 SLICE_68/D1 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_68/F0 SLICE_68/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_70/F0 SLICE_70/A1 (1104:1258:1413)(1104:1258:1413)) + (INTERCONNECT SLICE_70/F1 SLICE_74/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_70/F1 SLICE_80/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72/F0 SLICE_72/A1 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_72/F0 SLICE_79/A0 (738:859:981)(738:859:981)) + (INTERCONNECT SLICE_72/F0 SLICE_80/D0 (528:584:640)(528:584:640)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_73/C1 (2075:2285:2495)(2075:2285:2495)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_101/B1 (3414:3733:4052)(3414:3733:4052)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_106/B1 (2686:2942:3198)(2686:2942:3198)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_106/B0 (2686:2942:3198)(2686:2942:3198)) + (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (3289:3551:3813)(3289:3551:3813)) + (INTERCONNECT Din\[3\]_I/PADDI Din\[3\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_116/F0 SLICE_73/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_73/F0 SLICE_73/CE (539:596:653)(539:596:653)) + (INTERCONNECT SLICE_103/F1 SLICE_74/D1 (530:587:645)(530:587:645)) + (INTERCONNECT SLICE_109/F1 SLICE_74/A1 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_109/F1 SLICE_80/A0 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_74/F1 SLICE_74/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_99/F0 SLICE_75/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_77/F0 SLICE_117/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_78/F1 SLICE_78/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_103/F0 SLICE_81/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_83/F0 SLICE_81/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_82/F1 SLICE_82/C0 (542:652:762)(542:652:762)) + (INTERCONNECT SLICE_82/F1 SLICE_87/A0 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_87/F1 SLICE_82/A0 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_87/F1 SLICE_84/D1 (530:592:654)(530:592:654)) + (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_87/F1 SLICE_93/D0 (530:592:654)(530:592:654)) + (INTERCONNECT SLICE_83/F1 SLICE_83/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_110/F1 SLICE_84/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_110/F1 SLICE_93/A0 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_93/F0 SLICE_84/D0 (531:586:641)(531:586:641)) + (INTERCONNECT SLICE_93/F0 SLICE_93/D1 (531:586:641)(531:586:641)) + (INTERCONNECT SLICE_85/F0 SLICE_85/A1 (476:566:656)(476:566:656)) + (INTERCONNECT SLICE_86/F0 SLICE_85/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_100/F1 SLICE_85/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_117/F1 SLICE_88/D1 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_108/F1 SLICE_88/C1 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_108/F1 nRRAS_MGIOL/OPOS (1448:1590:1732)(1448:1590:1732)) + (INTERCONNECT SLICE_108/Q0 SLICE_88/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_88/F1 nRCS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) + (INTERCONNECT SLICE_96/F1 SLICE_89/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_96/F1 SLICE_96/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_89/F1 SLICE_89/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_105/F1 SLICE_91/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_111/F0 SLICE_91/A0 (1174:1336:1498)(1174:1336:1498)) + (INTERCONNECT SLICE_92/F1 SLICE_92/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_92/F1 SLICE_105/C0 (280:362:445)(280:362:445)) + (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_94/B1 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_94/A1 (926:1065:1204)(926:1065:1204)) + (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_94/D0 (716:789:863)(716:789:863)) + (INTERCONNECT SLICE_94/F1 SLICE_94/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_94/A0 (926:1065:1204)(926:1065:1204)) + (INTERCONNECT SLICE_97/F1 SLICE_97/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_98/F1 SLICE_98/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_104/D0 (1961:2109:2258)(1961:2109:2258)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/D1 (2331:2511:2692)(2331:2511:2692)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/D0 (2331:2511:2692)(2331:2511:2692)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (2436:2626:2817)(2436:2626:2817)) + (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_107/F0 RA\[9\]_I/PADDO (1279:1433:1587)(1279:1433:1587)) + (INTERCONNECT SLICE_107/F1 RDQMH_I/PADDO (1454:1620:1786)(1454:1620:1786)) + (INTERCONNECT SLICE_111/F1 RA\[7\]_I/PADDO (1834:2056:2279)(1834:2056:2279)) + (INTERCONNECT SLICE_112/F0 RA\[0\]_I/PADDO (1400:1583:1767)(1400:1583:1767)) + (INTERCONNECT SLICE_112/F1 RDQML_I/PADDO (936:1038:1140)(936:1038:1140)) + (INTERCONNECT SLICE_113/F0 RA\[1\]_I/PADDO (1106:1265:1425)(1106:1265:1425)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (1279:1433:1587)(1279:1433:1587)) + (INTERCONNECT SLICE_114/F0 RA\[2\]_I/PADDO (1815:2042:2270)(1815:2042:2270)) + (INTERCONNECT SLICE_114/F1 RA\[6\]_I/PADDO (1879:2100:2321)(1879:2100:2321)) + (INTERCONNECT SLICE_115/F0 RA\[3\]_I/PADDO (1552:1738:1924)(1552:1738:1924)) + (INTERCONNECT SLICE_115/F1 RA\[5\]_I/PADDO (1815:2042:2270)(1815:2042:2270)) + (INTERCONNECT SLICE_116/F1 RA\[11\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_118/B1 (2262:2486:2711)(2262:2486:2711)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_118/B0 (1744:1935:2126)(1744:1935:2126)) + (INTERCONNECT SLICE_118/F0 RBA\[1\]_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_118/F1 RBA\[0\]_MGIOL/OPOS (1790:1965:2141)(1790:1965:2141)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2632:2848:3064)(2632:2848:3064)) + (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2632:2848:3064)(2632:2848:3064)) + (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (9:36:63)(9:36:63)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.vo new file mode 100644 index 0000000..e74518f --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_vo.vo @@ -0,0 +1,5926 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd +// Netlist created on Sat Aug 19 21:54:57 2023 +// Netlist written on Sat Aug 19 21:55:18 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , + \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , + CmdEnable17_5, N_304, ADWR_7, CmdEnable17_4, CmdEnable17, un1_ADWR, + CmdEnable16, ADSubmitted, ADSubmitted_r, PHI2_c, C1WR_2, + CmdEnable16_4, C1WR_7, CmdEnable16_5, C1Submitted, C1Submitted_s, + nCCAS_c, nCCAS_c_i, CASr, CASr2, CO0, \IS[3] , RASr2, \S[1] , N_79_i, + Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, XOR8MEG11, + \Din_c[1] , CmdLEDEN, N_75, XOR8MEG14, LEDEN, CmdLEDEN_4, XOR8MEG18, + CmdUFMShift, CmdUFMShift_3, CmdUFMShift_fast, CmdUFMShift_3_fast, + \Din_c[0] , CmdUFMWrite_2, CmdUFMWrite, CmdUFMWrite_3, \Din_c[4] , + \Din_c[7] , \Din_c[5] , \Din_c[6] , CmdValid_r, CmdValid, CMDWR_2, + N_36_fast, CmdValid_fast, Cmdn8MEGEN, n8MEGEN, N_93, Cmdn8MEGEN_4, + nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, \IS[0] , Ready, N_250, + N_60_i_i, RA10s_i, \IS[1] , \IS[2] , N_57_i_i, IS_n1_0_x2, N_253_i, + N_58_i_i, N_45, N_116, InitReady3_0_a3_2, InitReady3, InitReady, + N_487_0, \wb_dato[1] , LEDEN_6, un1_FS_38_i, CBR, nCRAS_c_i_0, RASr, + LED_c, \RowA[4] , \MAin_c[4] , nRowColSel, PHI2r, \RA_c[4] , RASr3, + un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, PHI2r2, N_41, RCKEEN_8_u_1_0, + RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, \Bank[7] , \Bank[2] , \Bank[5] , + \Bank[6] , RCKE_2, RCKE_c, un1_Bank_1_4, N_258, N_486_0, + Ready_0_sqmuxa, Ready_fast, N_489_0, \MAin_c[1] , \MAin_c[0] , + \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , + \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \RowA[3] , + \MAin_c[5] , \RowAd_0[5] , \RowAd_0[4] , \RowA[5] , \MAin_c[7] , + \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , + \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , + \RowA[9] , nRRAS_5_u_i_0, XOR8MEG9_1, XOR8MEG_3_u_0_bm, un1_Din_2, + XOR8MEG, XOR8MEG_3, \wb_dato[0] , n8MEGEN_6, wb_rst10, CASr3, N_265, + nRowColSel_0_0, nRRAS_0_sqmuxa, wb_rst11, \wb_adr[0] , N_181, + \wb_adr_cnst_m2[0] , \wb_dati[7] , \wb_adr_5[1] , \wb_adr_5[0] , + un1_wb_rst14_i, \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , + \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , \wb_adr_5[5] , \wb_adr_5[4] , + \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , + N_245, N_102_2, un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, + un1_wb_cyc_stb_1_sqmuxa_0, un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, + wb_cyc_stb, \wb_dati_5_1_iv_0_0[1] , N_94, N_128, + \wb_dati_5_1_iv_0_a3_0_0[1] , \wb_dati_5_0_iv_0_a3_1[0] , wb_we, + N_119, \wb_dati_5[1] , \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , + \wb_dati_5_1_iv_0_0[3] , un1_wb_we95_1, N_49, N_240, \wb_dati_5[3] , + \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , + un1_wb_rst11_1_s6_1, \wb_dati_5_1_iv_0_1[4] , \wb_dati_5[5] , + \wb_dati_5[4] , \wb_dati[5] , N_89, \wb_dati_5_1_iv_0_a3_0_0[7] , + \wb_dati_5_1_iv_0_1[7] , \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , + \wb_dati_5[6] , \wb_dati[6] , un1_FS_37_i_0, N_78_i, wb_req, + wb_reqe_0, PHI2r3, wb_rst, wb_rste_0, un1_FS_29, wb_we95, CmdUFMData, + un1_wb_adr_0_sqmuxa_3, un1_wb_adr_0_sqmuxa_2, wb_we_0, un1_PHI2r3_0, + N_102, un1_FS_11, wb_ack, d_N_5_mux, N_254, N_39, nRCAS_0_sqmuxa_1, + N_37_i_1, nRWE_0io_RNO_1, CBR_fast, N_37_i, un1_FS_40_1_0_1, + un1_FS_40_1_0, nRCAS_0io_RNO_0, N_28_i_1, N_249_i, N_230, + nRWE_0io_RNO_3, nRWE_0io_RNO_4, N_131, N_85, N_248, \Din_c[3] , + XOR8MEG14_1, CmdUFMData_1_sqmuxa, \wb_dati_5_1_iv_0_a3_0[6] , N_246, + N_98, \wb_dati_5_1_iv_0_a3_0[3] , N_25, N_59, + \wb_dati_5_1_iv_0_a3_2_0[1] , \wb_dati_5_1_iv_0_a3_1_1[4] , + \wb_dati_5_1_iv_0_a3_3_0[7] , N_91, N_242, un1_FS_20_3, + wb_we95_0_tz_tz_tz, N_120, N_228, wb_we113_i, un1_FS_40_1_1_1, N_139, + un1_FS_40_1_1_tz, N_136, N_28_i_sn, N_25_i, FWEr_fast, N_28_i, + N_102_1, N_233, ADWR_4, ADWR_5, C1WR_0, \Bank[0] , \Bank[1] , + \Bank[4] , un1_Bank_1_3, \Bank[3] , G_8_0_a3_0_0, nRWE_0io_RNO_2, + \Din_c[2] , \RA_c[9] , RDQMH_c, \RA_c[7] , \RA_c[0] , RDQML_c, + \RA_c[1] , \RA_c[8] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , + RA11d_0, \CROW_c[0] , \CROW_c[1] , \RBAd_0[1] , \RBAd_0[0] , + \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] , + \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] , + \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] , + \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c), + .FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] )); + SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ), + .DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), + .Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] )); + SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_10 SLICE_10( .D1(CmdEnable17_5), .C1(N_304), .B1(ADWR_7), + .A1(CmdEnable17_4), .D0(CmdEnable17), .C0(un1_ADWR), .B0(CmdEnable16), + .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), + .Q0(ADSubmitted), .F1(CmdEnable17)); + SLICE_11 SLICE_11( .D1(C1WR_2), .C1(CmdEnable16_4), .B1(C1WR_7), + .A1(CmdEnable16_5), .C0(CmdEnable16), .B0(C1Submitted), .A0(un1_ADWR), + .DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted), + .F1(CmdEnable16)); + SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); + SLICE_16 SLICE_16( .D1(CO0), .C1(\IS[3] ), .B1(RASr2), .A1(\S[1] ), .D0(CO0), + .A0(\S[1] ), .DI0(N_79_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_79_i), + .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); + SLICE_17 SLICE_17( .D1(ADSubmitted), .B1(CmdEnable), .D0(un1_CMDWR), + .C0(C1Submitted), .B0(CmdEnable17), .A0(CmdEnable), .DI0(CmdEnable_s), + .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); + SLICE_18 SLICE_18( .D1(XOR8MEG11), .C1(\Din_c[1] ), .A1(CmdLEDEN), .C0(N_75), + .B0(XOR8MEG14), .A0(LEDEN), .DI0(CmdLEDEN_4), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(CmdLEDEN_4), .Q0(CmdLEDEN), .F1(N_75)); + SLICE_20 SLICE_20( .D0(XOR8MEG14), .C0(\Din_c[1] ), .B0(XOR8MEG11), + .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(CmdUFMShift_3), .Q0(CmdUFMShift)); + SLICE_21 SLICE_21( .D0(\Din_c[1] ), .C0(XOR8MEG14), .B0(XOR8MEG11), + .A0(CmdUFMShift_fast), .DI0(CmdUFMShift_3_fast), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(CmdUFMShift_3_fast), .Q0(CmdUFMShift_fast)); + SLICE_22 SLICE_22( .C1(\Din_c[0] ), .A1(\Din_c[1] ), .D0(XOR8MEG14), + .C0(CmdUFMWrite_2), .B0(XOR8MEG11), .A0(CmdUFMWrite), .DI0(CmdUFMWrite_3), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), + .F1(CmdUFMWrite_2)); + SLICE_23 SLICE_23( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[5] ), + .A1(\Din_c[6] ), .D0(XOR8MEG14), .C0(XOR8MEG18), .B0(XOR8MEG11), + .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), + .F1(XOR8MEG11)); + SLICE_24 SLICE_24( .C1(CmdEnable), .B1(C1WR_7), .A1(CMDWR_2), .D0(XOR8MEG14), + .B0(XOR8MEG18), .A0(XOR8MEG11), .DI0(N_36_fast), .CLK(PHI2_c), + .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_25 SLICE_25( .D1(XOR8MEG11), .C1(\Din_c[0] ), .A1(Cmdn8MEGEN), + .D0(XOR8MEG14), .C0(n8MEGEN), .B0(N_93), .DI0(Cmdn8MEGEN_4), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(Cmdn8MEGEN_4), .Q0(Cmdn8MEGEN), + .F1(N_93)); + SLICE_26 SLICE_26( .D1(nFWE_c), .C1(nCCAS_c), .C0(nFWE_c), .DI0(nFWE_c_i), + .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); + SLICE_28 SLICE_28( .D1(\IS[0] ), .C1(Ready), .B1(\IS[3] ), .A1(N_250), + .D0(\IS[0] ), .C0(Ready), .A0(N_250), .DI0(N_60_i_i), .CLK(RCLK_c), + .F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i)); + SLICE_29 SLICE_29( .D1(\IS[1] ), .C1(\IS[0] ), .A1(\IS[2] ), .C0(\IS[0] ), + .A0(\IS[1] ), .DI1(N_57_i_i), .DI0(IS_n1_0_x2), .CE(N_253_i), .CLK(RCLK_c), + .F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] )); + SLICE_30 SLICE_30( .D1(\IS[1] ), .A1(\IS[2] ), .D0(\IS[3] ), .C0(\IS[0] ), + .B0(\IS[1] ), .A0(\IS[2] ), .DI0(N_58_i_i), .CE(N_253_i), .CLK(RCLK_c), + .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_45)); + SLICE_31 SLICE_31( .D1(N_116), .C1(\FS[14] ), .B1(InitReady3_0_a3_2), + .A1(\FS[13] ), .C0(InitReady3), .A0(InitReady), .DI0(N_487_0), + .CLK(RCLK_c), .F0(N_487_0), .Q0(InitReady), .F1(InitReady3)); + SLICE_32 SLICE_32( .D0(InitReady), .B0(CmdLEDEN), .A0(\wb_dato[1] ), + .DI0(LEDEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(LEDEN_6), .Q0(LEDEN)); + SLICE_34 SLICE_34( .D1(nCRAS_c), .C1(LEDEN), .A1(CBR), .D0(nCRAS_c), + .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_35 SLICE_35( .D1(\FS[3] ), .A1(\FS[7] ), .D0(\RowA[4] ), + .C0(\MAin_c[4] ), .A0(nRowColSel), .M1(PHI2r), .M0(RASr2), .CLK(RCLK_c), + .F0(\RA_c[4] ), .Q0(RASr3), .F1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), + .Q1(PHI2r2)); + SLICE_36 SLICE_36( .D1(Ready), .C1(RASr2), .B1(InitReady), .A1(N_41), + .D0(CBR), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(Ready), + .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), + .F1(RCKEEN_8_u_0_0)); + SLICE_37 SLICE_37( .D1(\Bank[7] ), .C1(\Bank[2] ), .B1(\Bank[5] ), + .A1(\Bank[6] ), .D0(RASr2), .C0(RCKEEN), .B0(RASr), .A0(RASr3), + .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(un1_Bank_1_4)); + SLICE_38 SLICE_38( .D1(\IS[1] ), .C1(\IS[0] ), .A1(\IS[2] ), .D0(InitReady), + .C0(N_258), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_486_0), + .CLK(RCLK_c), .F0(N_486_0), .Q0(Ready), .F1(N_258)); + SLICE_39 SLICE_39( .D1(InitReady), .C1(N_258), .B1(Ready_0_sqmuxa_0_a3_2), + .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_489_0), + .CLK(RCLK_c), .F0(N_489_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); + SLICE_40 SLICE_40( .C1(\MAin_c[1] ), .B1(Ready_fast), .C0(\MAin_c[0] ), + .B0(Ready_fast), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), + .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); + SLICE_41 SLICE_41( .D1(Ready_fast), .B1(\MAin_c[3] ), .D0(Ready_fast), + .C0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), + .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); + SLICE_42 SLICE_42( .D1(\MAin_c[5] ), .A1(Ready_fast), .C0(\MAin_c[4] ), + .A0(Ready_fast), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), + .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); + SLICE_43 SLICE_43( .C1(\MAin_c[7] ), .B1(Ready_fast), .C0(\MAin_c[6] ), + .B0(Ready_fast), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), + .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); + SLICE_44 SLICE_44( .D1(Ready_fast), .B1(\MAin_c[9] ), .D0(Ready_fast), + .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), + .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); + SLICE_45 SLICE_45( .D1(RCKE_c), .C1(N_41), .B1(Ready), .A1(RASr2), + .D0(\S[1] ), .C0(CO0), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41), + .Q0(\S[1] ), .F1(nRRAS_5_u_i_0)); + SLICE_46 SLICE_46( .D1(XOR8MEG9_1), .C1(\Din_c[1] ), .B1(\Din_c[0] ), + .A1(LEDEN), .C0(XOR8MEG_3_u_0_bm), .B0(un1_Din_2), .A0(XOR8MEG), + .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), + .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_bm)); + SLICE_47 SLICE_47( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), + .A1(\FS[15] ), .D0(InitReady), .C0(\wb_dato[0] ), .A0(Cmdn8MEGEN), + .DI0(n8MEGEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(n8MEGEN_6), + .Q0(n8MEGEN), .F1(wb_rst10)); + SLICE_48 SLICE_48( .D1(CASr3), .C1(FWEr), .B1(CBR), .A1(Ready), .D0(\S[1] ), + .C0(Ready), .B0(N_265), .A0(CO0), .DI0(nRowColSel_0_0), + .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), + .F1(N_265)); + SLICE_49 SLICE_49( .D1(wb_rst11), .C1(\wb_adr[0] ), .B1(InitReady), + .A1(N_181), .D0(\wb_adr_cnst_m2[0] ), .B0(InitReady), .A0(\wb_dati[7] ), + .DI1(\wb_adr_5[1] ), .DI0(\wb_adr_5[0] ), .CE(un1_wb_rst14_i), + .CLK(RCLK_c), .F0(\wb_adr_5[0] ), .Q0(\wb_adr[0] ), .F1(\wb_adr_5[1] ), + .Q1(\wb_adr[1] )); + SLICE_50 SLICE_50( .B1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ), + .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), + .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); + SLICE_51 SLICE_51( .D1(wb_rst11), .C1(InitReady), .A1(\wb_adr[4] ), + .D0(wb_rst11), .C0(InitReady), .A0(\wb_adr[3] ), .DI1(\wb_adr_5[5] ), + .DI0(\wb_adr_5[4] ), .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[4] ), + .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_52 SLICE_52( .D1(InitReady), .A1(\wb_adr[6] ), .D0(InitReady), + .C0(wb_rst11), .B0(\wb_adr[5] ), .DI1(\wb_adr_5[7] ), .DI0(\wb_adr_5[6] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), .Q0(\wb_adr[6] ), + .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); + SLICE_53 SLICE_53( .D1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), .C1(\FS[5] ), + .B1(\FS[2] ), .A1(\FS[4] ), .D0(wb_rst11), .C0(N_245), .B0(N_102_2), + .A0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), .DI0(un1_wb_cyc_stb_1_sqmuxa_0), + .CE(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(un1_wb_cyc_stb_1_sqmuxa_0), .Q0(wb_cyc_stb), .F1(N_102_2)); + SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_0[1] ), .C1(N_94), .B1(N_128), + .A1(\wb_dati_5_1_iv_0_a3_0_0[1] ), .D0(\wb_dati_5_0_iv_0_a3_1[0] ), + .C0(wb_we), .B0(InitReady), .A0(N_119), .DI1(\wb_dati_5[1] ), + .DI0(\wb_dati_5[0] ), .CE(un1_wb_rst14_i), .CLK(RCLK_c), + .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), + .Q1(\wb_dati[1] )); + SLICE_55 SLICE_55( .D1(wb_rst11), .C1(\wb_dati_5_1_iv_0_0[3] ), + .B1(un1_wb_we95_1), .A1(N_94), .D0(N_49), .C0(\wb_dati[1] ), .B0(N_240), + .A0(InitReady), .DI1(\wb_dati_5[3] ), .DI0(\wb_dati_5[2] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), + .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); + SLICE_56 SLICE_56( .D1(N_49), .C1(InitReady), .B1(N_240), .A1(\wb_dati[4] ), + .D0(un1_wb_rst11_1_s6_1), .C0(InitReady), .B0(\wb_dati[3] ), + .A0(\wb_dati_5_1_iv_0_1[4] ), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), + .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), + .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); + SLICE_57 SLICE_57( .D1(N_89), .C1(\wb_dati_5_1_iv_0_a3_0_0[7] ), + .B1(\wb_dati_5_1_iv_0_1[7] ), .A1(N_119), .D0(\wb_dati_5_1_iv_0_1[6] ), + .C0(\wb_dati_5_1_iv_0_a3_0_0[1] ), .B0(N_128), .DI1(\wb_dati_5[7] ), + .DI0(\wb_dati_5[6] ), .CE(un1_wb_rst14_i), .CLK(RCLK_c), + .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), + .Q1(\wb_dati[7] )); + SLICE_58 SLICE_58( .C1(\FS[14] ), .B1(\FS[12] ), .A1(\FS[13] ), + .D0(wb_rst11), .C0(un1_FS_37_i_0), .B0(N_78_i), .A0(wb_req), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_FS_37_i_0)); + SLICE_59 SLICE_59( .D1(PHI2r3), .C1(InitReady), .B1(CmdValid), .A1(PHI2r2), + .D0(wb_rst10), .C0(wb_rst), .B0(N_78_i), .A0(\FS[14] ), .DI0(wb_rste_0), + .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(N_78_i)); + SLICE_60 SLICE_60( .C1(un1_FS_29), .A1(wb_we95), .D0(CmdUFMData), + .C0(un1_wb_adr_0_sqmuxa_3), .B0(InitReady), .A0(un1_wb_adr_0_sqmuxa_2), + .DI0(wb_we_0), .CE(un1_wb_rst14_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(wb_we_0), .Q0(wb_we), .F1(un1_wb_adr_0_sqmuxa_2)); + wb_cyc_stb_RNO_SLICE_61 \wb_cyc_stb_RNO/SLICE_61 ( .D1(CmdValid), + .C1(CmdUFMWrite), .B1(CmdUFMShift), .A1(un1_PHI2r3_0), .D0(N_102), + .C0(un1_FS_11), .A0(wb_ack), .M0(InitReady), + .OFX0(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i)); + SLICE_62 SLICE_62( .D1(un1_PHI2r3_0), .C1(d_N_5_mux), .B1(CmdValid_fast), + .A1(InitReady), .D0(un1_FS_29), .C0(un1_FS_11), .B0(wb_ack), + .A0(InitReady), .F0(d_N_5_mux), .F1(un1_FS_38_i)); + SLICE_63 SLICE_63( .D1(\S[1] ), .C1(CO0), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(N_250), .B0(N_254), .A0(Ready), .F0(N_39), .F1(N_250)); + SLICE_64 SLICE_64( .D1(Ready), .C1(nRCAS_0_sqmuxa_1), .B1(N_37_i_1), + .A1(nRWE_0io_RNO_1), .D0(Ready), .C0(RASr2), .B0(CBR_fast), .A0(N_41), + .F0(nRCAS_0_sqmuxa_1), .F1(N_37_i)); + SLICE_65 SLICE_65( .D1(un1_FS_40_1_0_1), .C1(\FS[10] ), .B1(\FS[13] ), + .A1(\FS[9] ), .D0(\FS[14] ), .C0(\FS[9] ), .B0(\FS[12] ), .A0(\FS[11] ), + .F0(un1_FS_40_1_0_1), .F1(un1_FS_40_1_0)); + SLICE_66 SLICE_66( .D1(\S[1] ), .B1(N_39), .A1(CBR), .D0(\S[1] ), + .C0(nRCAS_0io_RNO_0), .B0(nRCAS_0_sqmuxa_1), .A0(N_28_i_1), .F0(N_249_i), + .F1(nRCAS_0io_RNO_0)); + SLICE_67 SLICE_67( .D1(wb_rst11), .C1(\FS[9] ), .B1(\FS[13] ), .A1(N_230), + .D0(wb_rst11), .C0(un1_wb_we95_1), .B0(N_94), .F0(N_49), .F1(N_94)); + SLICE_68 SLICE_68( .D1(nRWE_0io_RNO_3), .C1(nRWE_0io_RNO_4), .A1(Ready), + .D0(\IS[2] ), .C0(\IS[1] ), .B0(\IS[0] ), .A0(N_250), .F0(nRWE_0io_RNO_4), + .F1(nRWE_0io_RNO_1)); + SLICE_69 SLICE_69( .D1(RCKE_c), .C1(nRRAS_0_sqmuxa), .A1(RASr2), .D0(Ready), + .B0(\S[1] ), .A0(CO0), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_3)); + SLICE_70 SLICE_70( .D1(\FS[14] ), .C1(N_119), .B1(\FS[13] ), .A1(N_131), + .C0(\FS[11] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_131), .F1(N_85)); + SLICE_71 SLICE_71( .C1(\FS[10] ), .A1(\FS[11] ), .D0(\FS[14] ), + .C0(\FS[13] ), .B0(\FS[12] ), .A0(N_116), + .F0(\wb_dati_5_1_iv_0_a3_0_0[7] ), .F1(N_116)); + SLICE_72 SLICE_72( .D1(wb_rst11), .C1(\FS[14] ), .B1(\FS[13] ), .A1(N_248), + .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_248), + .F1(N_240)); + SLICE_73 SLICE_73( .D1(\Din_c[7] ), .C1(\Din_c[3] ), .B1(XOR8MEG14_1), + .A1(\Din_c[5] ), .D0(C1WR_7), .C0(CMDWR_2), .B0(XOR8MEG14), .A0(CmdEnable), + .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CmdUFMData), .F1(XOR8MEG14)); + SLICE_74 SLICE_74( .D1(\wb_dati_5_1_iv_0_a3_0[6] ), .C1(\FS[10] ), + .B1(\FS[12] ), .A1(N_246), .D0(N_85), .C0(\wb_dati[5] ), .B0(InitReady), + .A0(N_98), .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_98)); + SLICE_75 SLICE_75( .D1(\FS[11] ), .B1(\FS[14] ), .A1(wb_rst11), + .D0(\wb_dati_5_1_iv_0_a3_0[3] ), .C0(N_128), .B0(\wb_dati[2] ), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[3] ), .F1(N_128)); + SLICE_76 SLICE_76( .D1(InitReady), .C1(\FS[15] ), .B1(\FS[16] ), + .A1(\FS[17] ), .C0(wb_rst11), .A0(un1_wb_we95_1), .F0(un1_wb_rst11_1_s6_1), + .F1(wb_rst11)); + SLICE_77 SLICE_77( .D1(\IS[1] ), .C1(\IS[3] ), .B1(\IS[2] ), + .D0(nRRAS_5_u_i_0), .C0(N_250), .B0(N_254), .A0(\IS[0] ), .F0(N_25), + .F1(N_254)); + SLICE_78 SLICE_78( .C1(\FS[12] ), .B1(\FS[9] ), .A1(\FS[10] ), .D0(N_59), + .C0(N_128), .B0(\FS[13] ), .F0(N_89), .F1(N_59)); + SLICE_79 SLICE_79( .C1(\FS[14] ), .B1(\FS[13] ), .A1(wb_rst11), + .D0(InitReady), .C0(\wb_dati_5_1_iv_0_a3_2_0[1] ), .B0(\wb_dati[0] ), + .A0(N_248), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\wb_dati_5_1_iv_0_a3_2_0[1] )); + SLICE_80 SLICE_80( .D1(\FS[12] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[13] ), + .D0(N_248), .C0(\wb_dati_5_1_iv_0_a3_1_1[4] ), .B0(N_85), .A0(N_246), + .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(\wb_dati_5_1_iv_0_a3_1_1[4] )); + SLICE_81 SLICE_81( .D1(\FS[12] ), .C1(\wb_dati_5_1_iv_0_a3_3_0[7] ), + .B1(\FS[10] ), .A1(wb_rst11), .D0(InitReady), .C0(N_91), .B0(N_242), + .A0(\wb_dati[6] ), .F0(\wb_dati_5_1_iv_0_1[7] ), .F1(N_242)); + SLICE_82 SLICE_82( .B1(\FS[13] ), .A1(\FS[14] ), .D0(\FS[11] ), + .C0(un1_FS_20_3), .B0(\FS[12] ), .A0(wb_we95_0_tz_tz_tz), + .F0(un1_wb_we95_1), .F1(un1_FS_20_3)); + SLICE_83 SLICE_83( .D1(\FS[10] ), .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_120), + .C0(\FS[14] ), .B0(\FS[13] ), .A0(N_119), .F0(N_91), .F1(N_120)); + SLICE_84 SLICE_84( .D1(wb_we95_0_tz_tz_tz), .C1(\FS[13] ), .B1(\FS[14] ), + .A1(N_228), .D0(wb_we113_i), .C0(un1_FS_29), .A0(wb_we95), .F0(N_181), + .F1(un1_FS_29)); + SLICE_85 SLICE_85( .C1(un1_FS_40_1_0), .B1(wb_rst11), .A1(un1_FS_40_1_1_1), + .D0(\FS[10] ), .C0(N_139), .B0(un1_FS_40_1_1_tz), .A0(\FS[9] ), + .F0(un1_FS_40_1_1_1), .F1(\wb_adr_cnst_m2[0] )); + SLICE_86 SLICE_86( .D1(\FS[11] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), + .D0(\FS[14] ), .C0(N_136), .B0(\FS[13] ), .F0(N_139), .F1(N_136)); + SLICE_87 SLICE_87( .D1(\FS[9] ), .B1(\FS[10] ), .D0(\FS[11] ), + .C0(wb_we95_0_tz_tz_tz), .B0(\FS[12] ), .A0(un1_FS_20_3), .F0(wb_we95), + .F1(wb_we95_0_tz_tz_tz)); + SLICE_88 SLICE_88( .D1(N_28_i_sn), .C1(N_25_i), .B1(N_28_i_1), .A1(Ready), + .D0(CO0), .C0(CASr2), .B0(CASr3), .A0(FWEr_fast), .F0(N_28_i_1), + .F1(N_28_i)); + SLICE_89 SLICE_89( .B1(\FS[0] ), .A1(wb_req), .D0(InitReady), .C0(N_102_2), + .B0(N_102_1), .A0(N_233), .F0(N_102), .F1(N_233)); + SLICE_90 SLICE_90( .D1(CMDWR_2), .C1(C1WR_7), .B1(ADWR_7), .A1(C1WR_2), + .D0(\MAin_c[6] ), .C0(N_304), .B0(\MAin_c[5] ), .A0(\MAin_c[7] ), + .F0(C1WR_7), .F1(un1_CMDWR)); + SLICE_91 SLICE_91( .C1(ADWR_7), .B1(C1WR_7), .A1(C1WR_2), .D0(\MAin_c[3] ), + .C0(\MAin_c[1] ), .B0(ADWR_4), .A0(ADWR_5), .F0(ADWR_7), .F1(un1_ADWR)); + SLICE_92 SLICE_92( .D1(\MAin_c[4] ), .C1(\MAin_c[3] ), .B1(\MAin_c[2] ), + .D0(nFWE_c), .C0(C1WR_0), .B0(\MAin_c[0] ), .A0(\MAin_c[1] ), .F0(C1WR_2), + .F1(C1WR_0)); + SLICE_93 SLICE_93( .D1(wb_we113_i), .C1(wb_rst11), .A1(un1_FS_37_i_0), + .D0(wb_we95_0_tz_tz_tz), .C0(\FS[14] ), .B0(\FS[13] ), .A0(N_228), + .F0(wb_we113_i), .F1(un1_wb_adr_0_sqmuxa_3)); + SLICE_94 SLICE_94( .B1(\Bank[0] ), .A1(\Bank[1] ), .D0(\Bank[4] ), + .C0(un1_Bank_1_3), .B0(un1_Bank_1_4), .A0(\Bank[3] ), .F0(N_304), + .F1(un1_Bank_1_3)); + SLICE_95 SLICE_95( .B1(PHI2r3), .A1(PHI2r2), .D0(CmdValid), .C0(CmdUFMShift), + .B0(un1_PHI2r3_0), .A0(InitReady), .F0(N_245), .F1(un1_PHI2r3_0)); + SLICE_96 SLICE_96( .D1(\FS[6] ), .C1(\FS[8] ), .A1(\FS[1] ), .C0(N_102_1), + .B0(wb_req), .A0(\FS[0] ), .F0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), + .F1(N_102_1)); + SLICE_97 SLICE_97( .C1(PHI2r2), .B1(PHI2r3), .D0(CmdValid_fast), + .C0(InitReady), .B0(CmdUFMShift_fast), .A0(G_8_0_a3_0_0), + .F0(un1_wb_rst14_i), .F1(G_8_0_a3_0_0)); + SLICE_98 SLICE_98( .D1(\S[1] ), .C1(CASr3), .B1(CO0), .A1(CASr2), .D0(FWEr), + .C0(nRWE_0io_RNO_2), .A0(CBR_fast), .F0(N_37_i_1), .F1(nRWE_0io_RNO_2)); + SLICE_99 SLICE_99( .D1(\FS[10] ), .C1(\FS[12] ), .B1(\FS[13] ), .A1(\FS[9] ), + .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[13] ), .A0(\FS[9] ), + .F0(\wb_dati_5_1_iv_0_a3_0[3] ), .F1(\wb_dati_5_1_iv_0_a3_0_0[1] )); + SLICE_100 SLICE_100( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), + .A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[11] ), + .F0(N_230), .F1(un1_FS_40_1_1_tz)); + SLICE_101 SLICE_101( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), + .A1(\Din_c[5] ), .D0(\Din_c[7] ), .C0(\Din_c[4] ), .B0(\Din_c[6] ), + .A0(\Din_c[5] ), .F0(un1_Din_2), .F1(CmdEnable17_5)); + SLICE_102 SLICE_102( .D1(\FS[16] ), .C1(\FS[12] ), .B1(\FS[17] ), + .A1(\FS[15] ), .D0(\FS[16] ), .C0(\FS[15] ), .B0(\FS[17] ), .F0(un1_FS_11), + .F1(InitReady3_0_a3_2)); + SLICE_103 SLICE_103( .D1(\FS[13] ), .C1(\FS[9] ), .B1(\FS[11] ), + .D0(\FS[13] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[14] ), + .F0(\wb_dati_5_1_iv_0_a3_3_0[7] ), .F1(\wb_dati_5_1_iv_0_a3_0[6] )); + SLICE_104 SLICE_104( .D1(\Din_c[0] ), .C1(\Din_c[1] ), .B1(\Din_c[6] ), + .A1(\Din_c[5] ), .D0(\Din_c[2] ), .C0(\Din_c[0] ), .B0(\Din_c[6] ), + .A0(\Din_c[1] ), .F0(CmdEnable17_4), .F1(CmdEnable16_4)); + SLICE_105 SLICE_105( .D1(nFWE_c), .C1(\MAin_c[6] ), .A1(\MAin_c[0] ), + .D0(\MAin_c[1] ), .C0(C1WR_0), .B0(nFWE_c), .A0(\MAin_c[0] ), + .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CMDWR_2), .Q0(CBR), + .F1(ADWR_4), .Q1(CBR_fast)); + SLICE_106 SLICE_106( .D1(\Din_c[2] ), .B1(\Din_c[3] ), .D0(\Din_c[2] ), + .C0(\Din_c[7] ), .B0(\Din_c[3] ), .A0(\Din_c[4] ), .M0(CASr2), + .CLK(RCLK_c), .F0(CmdEnable16_5), .Q0(CASr3), .F1(XOR8MEG9_1)); + SLICE_107 SLICE_107( .C1(nRowColSel), .B1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\MAin_c[9] ), .A0(\RowA[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_108 SLICE_108( .D1(N_250), .C1(nRRAS_5_u_i_0), .B1(\IS[0] ), + .A1(N_254), .D0(Ready), .C0(N_250), .M0(nFWE_c_i), .CLK(nCRAS_c), + .F0(N_253_i), .Q0(FWEr_fast), .F1(N_25_i)); + SLICE_109 SLICE_109( .D1(wb_rst11), .A1(\FS[14] ), .D0(wb_rst11), + .C0(\FS[9] ), .F0(N_119), .F1(N_246)); + SLICE_110 SLICE_110( .C1(\FS[11] ), .B1(\FS[12] ), .D0(\FS[13] ), .C0(N_116), + .B0(\FS[12] ), .A0(\FS[14] ), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), .F1(N_228)); + SLICE_111 SLICE_111( .C1(\RowA[7] ), .B1(nRowColSel), .A1(\MAin_c[7] ), + .D0(\MAin_c[4] ), .C0(\MAin_c[2] ), .B0(\MAin_c[5] ), .A0(\MAin_c[7] ), + .F0(ADWR_5), .F1(\RA_c[7] )); + SLICE_112 SLICE_112( .C1(nRowColSel), .B1(\MAin_c[9] ), .D0(nRowColSel), + .C0(\MAin_c[0] ), .B0(\RowA[0] ), .F0(\RA_c[0] ), .F1(RDQML_c)); + SLICE_113 SLICE_113( .D1(\RowA[8] ), .C1(\MAin_c[8] ), .A1(nRowColSel), + .D0(\RowA[1] ), .C0(\MAin_c[1] ), .A0(nRowColSel), .F0(\RA_c[1] ), + .F1(\RA_c[8] )); + SLICE_114 SLICE_114( .D1(\RowA[6] ), .C1(\MAin_c[6] ), .A1(nRowColSel), + .C0(\MAin_c[2] ), .B0(\RowA[2] ), .A0(nRowColSel), .F0(\RA_c[2] ), + .F1(\RA_c[6] )); + SLICE_115 SLICE_115( .D1(\RowA[5] ), .B1(nRowColSel), .A1(\MAin_c[5] ), + .C0(\RowA[3] ), .B0(\MAin_c[3] ), .A0(nRowColSel), .F0(\RA_c[3] ), + .F1(\RA_c[5] )); + SLICE_116 SLICE_116( .D1(\Din_c[6] ), .C1(n8MEGEN), .B1(Ready_fast), + .A1(XOR8MEG), .B0(\Din_c[4] ), .A0(\Din_c[6] ), .F0(XOR8MEG14_1), + .F1(RA11d_0)); + SLICE_117 SLICE_117( .D1(\S[1] ), .C1(CBR_fast), .B1(N_25), .D0(\S[1] ), + .C0(CO0), .B0(FWEr), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(N_28_i_sn)); + SLICE_118 SLICE_118( .C1(Ready_fast), .B1(\CROW_c[0] ), .C0(Ready_fast), + .B0(\CROW_c[1] ), .M0(PHI2r2), .CLK(RCLK_c), .F0(\RBAd_0[1] ), .Q0(PHI2r3), + .F1(\RBAd_0[0] )); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), + .RD0(RD[0])); + RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), + .CLK(nCCAS_c)); + Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_249_i), .CLK(RCLK_c)); + nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), + .RD7(RD[7])); + RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), + .CLK(nCCAS_c)); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .IOLDO(\WRD[6] ), .PADDT(RD_1_i), + .RD6(RD[6])); + RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ), + .CLK(nCCAS_c)); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .IOLDO(\WRD[5] ), .PADDT(RD_1_i), + .RD5(RD[5])); + RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ), + .CLK(nCCAS_c)); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .IOLDO(\WRD[4] ), .PADDT(RD_1_i), + .RD4(RD[4])); + RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ), + .CLK(nCCAS_c)); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .IOLDO(\WRD[3] ), .PADDT(RD_1_i), + .RD3(RD[3])); + RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ), + .CLK(nCCAS_c)); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .IOLDO(\WRD[2] ), .PADDT(RD_1_i), + .RD2(RD[2])); + RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ), + .CLK(nCCAS_c)); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .IOLDO(\WRD[1] ), .PADDT(RD_1_i), + .RD1(RD[1])); + RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ), + .CLK(nCCAS_c)); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0), + .CLK(PHI2_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_45), .LSR(RA10s_i), + .CLK(RCLK_c)); + RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1])); + RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ), + .CLK(nCRAS_c)); + RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0])); + RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ), + .CLK(nCRAS_c)); + LED LED_I( .PADDO(LED_c), .LED(LED)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] )); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] )); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] )); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] )); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] )); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CLK(PHI2_c), .IN(\Bank[2] )); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CLK(PHI2_c), .IN(\Bank[1] )); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CLK(PHI2_c), .IN(\Bank[0] )); + CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0])); + MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0])); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(RCLK_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; + + lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_11 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40004 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40006 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input D1, C1, B1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40007 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 \S_RNO[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_17 ( input D1, B1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); + wire GNDI, \SLICE_17/SLICE_17_K1_H1 , \SLICE_17/CmdEnable_s/GATE_H0 , VCCI, + CLK_NOTIN, DI0_dly, CLK_dly; + + lut40010 SLICE_17_K1( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(\SLICE_17/SLICE_17_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_17/CmdEnable_s/GATE_H0 )); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + selmux2 SLICE_17_K0K1MUX( .D0(\SLICE_17/CmdEnable_s/GATE_H0 ), + .D1(\SLICE_17/SLICE_17_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_18 ( input D1, C1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 CmdLEDEN_4_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 CmdLEDEN_4_u( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40014 CmdUFMShift_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40015 CmdUFMShift_3_u_fast( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMShift_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40016 CmdUFMWrite_2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 CmdUFMWrite_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40018 XOR8MEG11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 CmdValid_r( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40020 XOR8MEG18( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40022 Cmdn8MEGEN_4_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 Cmdn8MEGEN_4_u( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input D1, C1, C0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; + + lut40024 nCCAS_pad_RNI01SJ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 nFWE_pad_RNI420B( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40026 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 \IS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFA05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_29 ( input D1, C1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40028 \IS_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 IS_n1_0_x2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5A5A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_30 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40030 RA10_2_sqmuxa_0_o2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40031 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40032 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input D0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 LEDEN_6( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, A1, D0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40035 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 RASr_RNO( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40037 un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1( .A(A1), .B(GNDI), .C(GNDI), + .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \un9_RA[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40039 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h05CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40041 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40043 Ready_0_sqmuxa_0_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40045 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40046 \RowAd[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \RowAd[0] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input D1, B1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40047 \RowAd[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40048 \RowAd[2] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40049 \RowAd[5] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \RowAd[4] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40046 \RowAd[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \RowAd[6] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_44 ( input D1, B1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40051 \RowAd[9] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 \RowAd[8] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40053 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 \S_0_i_o2[1] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40054 XOR8MEG_3_u_0_bm( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 \XOR8MEG_3_u_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40056 wb_rst10( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 n8MEGEN_6( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40058 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40060 \wb_adr_5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40061 \wb_adr_5[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD1C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40062 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40063 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40064 \wb_adr_5[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 \wb_adr_5[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40065 \wb_adr_5[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 \wb_adr_5[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40067 un1_wb_cyc_stb_2_sqmuxa_i_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40068 un1_wb_cyc_stb_1_sqmuxa_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40069 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40071 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40073 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40075 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 \wb_dati_5_1_iv_0[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40020 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 wb_reqe( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2E22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40078 PHI2r3_RNIS5A51( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input C1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40033 un1_wb_adr_0_sqmuxa_2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 wb_we_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_cyc_stb_RNO_SLICE_61 ( input D1, C1, B1, A1, D0, C0, A0, M0, output + OFX0 ); + wire \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 , GNDI, + \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ; + + lut40081 \wb_cyc_stb_RNO/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 )); + lut40082 \wb_cyc_stb_RNO/GATE ( .A(A0), .B(GNDI), .C(C0), .D(D0), + .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \wb_cyc_stb_RNO/SLICE_61_K0K1MUX ( + .D0(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ), + .D1(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40083 CmdValid_fast_RNITQBM1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40084 \ufmefb/EFBInst_0_RNI9PBJ ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40085 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40086 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h51FB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40087 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 nRCAS_0_sqmuxa_1_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40089 un1_FS_40_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40090 un1_FS_40_1_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0520) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7071) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40091 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40092 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40093 \wb_dati_5_1_iv_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 \wb_dati_5_1_iv_0_o3[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40095 nRWE_0io_RNO_1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40096 nRWE_0io_RNO_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h05AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40097 nRWE_0io_RNO_3( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40098 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40099 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 \wb_dati_5_1_iv_0_a3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40050 wb_we113_i_a2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40102 \wb_dati_5_1_iv_0_a3[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 \FS_RNI3V8E[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40104 XOR8MEG14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 CmdUFMData_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40106 \wb_dati_5_1_iv_0_a3[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40107 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40108 \wb_dati_5_1_iv_0_a2_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 \wb_dati_5_1_iv_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, C0, A0, output F0, F1 ); + wire GNDI; + + lut40110 \wb_adr_cnst_sn.m2_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40063 \wb_dati_5_1_iv_0_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40111 un1_nRCAS_6_sqmuxa_i_o2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40113 \wb_dati_5_1_iv_0_m3[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40114 \wb_dati_5_1_iv_0_a3[7] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB5B5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40115 \wb_dati_5_1_iv_0_a3_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40117 \wb_dati_5_1_iv_0_a3_1_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40118 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40119 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40120 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40121 wb_we95_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40122 un1_wb_we95_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40122 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40123 \wb_dati_5_1_iv_0_a2[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 \wb_dati_5_1_iv_0_a3_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40124 un1_FS_29( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40125 \wb_adr_cnst_sn.m4_32 ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40124 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40125 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40126 \wb_adr_cnst_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 un1_FS_40_1_1_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8484) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40128 un1_FS_40_1_o6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40114 un1_FS_40_1_a6( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40129 un1_FS_21_1_i( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40130 wb_we95( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40131 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40132 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h77F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40132 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40133 un1_wb_cyc_stb_2_sqmuxa_i_o3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40134 un1_wb_cyc_stb_2_sqmuxa_i_a3( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40133 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40134 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40135 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40136 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40135 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40136 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40137 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40105 ADWR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40137 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40138 C1WR_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40139 C1WR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40138 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40139 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40140 un1_wb_adr_0_sqmuxa_3( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40141 wb_we113_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40140 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40141 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40142 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40143 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40142 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40143 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40144 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40145 un1_wb_cyc_stb_1_sqmuxa_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40144 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40145 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40146 un1_wb_cyc_stb_2_sqmuxa_i_a3_1( .A(A1), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40147 un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40147 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40148 PHI2r3_RNIFT0I( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 CmdUFMShift_fast_RNIG9JD1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40148 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40149 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40150 nRWE_0io_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40151 nRWE_0io_RNO_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40150 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40143 \wb_dati_5_1_iv_0_a3_0_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40152 \wb_dati_5_1_iv_0_a3_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40152 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40153 un1_FS_40_1_1_tz( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40154 \wb_dati_5_1_iv_0_o3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40153 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4042) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40154 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40155 CmdEnable17_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40156 un1_Din_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40155 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40156 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40157 InitReady3_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40158 un1_FS_11( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40157 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40158 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40159 \wb_dati_5_1_iv_0_a3_0_0[6] ( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40160 \wb_dati_5_1_iv_0_a3_3_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40159 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40160 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40045 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40161 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40161 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40162 ADWR_4( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40163 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40162 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40163 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input D1, B1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40164 XOR8MEG9_1( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40165 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input C1, B1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40166 RDQMH( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40166 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40167 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input D1, C1, B1, A1, D0, C0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly; + + lut40168 nRRAS_5_u_i_0_RNILD5I( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40169 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40168 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40169 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, A1, D0, C0, output F0, F1 ); + wire GNDI; + + lut40170 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40171 \wb_dati_5_1_iv_0_a2_0[4] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40171 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_110 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40172 un1_FS_22_1_i( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40173 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40172 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40173 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40013 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40174 ADWR_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40174 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input C1, B1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40175 RDQML( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40176 \un9_RA[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40175 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40176 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40038 \un9_RA[8] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \un9_RA[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40038 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40177 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_115 ( input D1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40178 \un9_RA[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40179 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40178 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40180 RA11d( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40181 XOR8MEG14_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40180 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8488) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40182 nRCS_0io_RNO_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40183 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40183 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4CF3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input C1, B1, C0, B0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40184 \RBAd[0] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40184 \RBAd[1] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre PHI2r3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40184 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (IOLDO => RD0) = (0:0:0,0:0:0); + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + + xo2iobuf0185 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0185 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0186 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0186 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module PHI2_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RDQML ( input PADDO, output RDQML ); + + xo2iobuf0185 RDQML_pad( .I(PADDO), .PAD(RDQML)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + + xo2iobuf0185 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input IOLDO, output nRCAS ); + + xo2iobuf0185 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + + specify + (IOLDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0187 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0187 ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module nRRAS ( input IOLDO, output nRRAS ); + + xo2iobuf0185 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + + specify + (IOLDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0187 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0185 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0187 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + + xo2iobuf0185 RCKE_pad( .I(PADDO), .PAD(RCKE)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0188 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0188 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module nRCS ( input IOLDO, output nRCS ); + + xo2iobuf0185 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + + specify + (IOLDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0187 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input IOLDO, PADDT, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (IOLDO => RD7) = (0:0:0,0:0:0); + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_7__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input IOLDO, PADDT, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (IOLDO => RD6) = (0:0:0,0:0:0); + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_6__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input IOLDO, PADDT, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (IOLDO => RD5) = (0:0:0,0:0:0); + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_5__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input IOLDO, PADDT, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (IOLDO => RD4) = (0:0:0,0:0:0); + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_4__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input IOLDO, PADDT, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (IOLDO => RD3) = (0:0:0,0:0:0); + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_3__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input IOLDO, PADDT, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (IOLDO => RD2) = (0:0:0,0:0:0); + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_2__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input IOLDO, PADDT, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (IOLDO => RD1) = (0:0:0,0:0:0); + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0185 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0185 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0189 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0189 ( input D0, SP, CK, LSR, output Q ); + + FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + + xo2iobuf0185 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + + xo2iobuf0185 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + + xo2iobuf0185 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + + xo2iobuf0185 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + + xo2iobuf0185 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + + xo2iobuf0185 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0185 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + + xo2iobuf0185 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + + xo2iobuf0185 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0185 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input IOLDO, output RBA1 ); + + xo2iobuf0185 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + + specify + (IOLDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RBA_0_ ( input IOLDO, output RBA0 ); + + xo2iobuf0185 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + + specify + (IOLDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0190 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0190 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0191 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0191 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0191 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0191 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + + xo2iobuf0185 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + + xo2iobuf0185 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + + xo2iobuf0185 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + + xo2iobuf0185 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + + xo2iobuf0185 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + + xo2iobuf0185 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + + xo2iobuf0185 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0188 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_7__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0188 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_6__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0188 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_5__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0188 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_4__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0188 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_3__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0188 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_2__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[2] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0188 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_1__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[1] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0188 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Din_0__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0188 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0188 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0188 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0188 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0188 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0188 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0188 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0188 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0188 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0188 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0188 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0188 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(), .WBDATO3(), .WBDATO4(), .WBDATO5(), + .WBDATO6(), .WBDATO7(), .WBACKO(WBACKO), .WBCUFMIRQ(), .UFMSN(VCCI), + .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLI(GNDI), .I2C2SCLO(), + .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), .I2C2SDAOEN(), .I2C1IRQO(), + .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), .SPISCKEN(), .SPIMISOI(GNDI), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), .SPIMOSIO(), .SPIMOSIEN(), + .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), .SPIMCSN3(), .SPIMCSN4(), + .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), .SPICSNEN(), .SPISCSN(GNDI), + .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), .TCIC(GNDI), .TCINT(), .TCOC(), + .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), .PLLWEO(), .PLLADRO0(), + .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), .PLLADRO4(), .PLLDATO0(), + .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), .PLLDATO4(), .PLLDATO5(), + .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), .PLL0DATI1(GNDI), + .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), .PLL0DATI5(GNDI), + .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), .PLL1DATI0(GNDI), + .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), .PLL1DATI4(GNDI), + .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "640L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "66.7"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 1; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC/impl1/automake.log index db8f14d..2b8a5b1 100644 --- a/CPLD/LCMXO2-640HC/impl1/automake.log +++ b/CPLD/LCMXO2-640HC/impl1/automake.log @@ -1,1701 +1,2717 @@ synpwrap -msg -prj "LCMXO2_640HC_impl1_synplify.tcl" -log "LCMXO2_640HC_impl1.srf" -Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved. -Lattice Diamond Version 3.12.1.454 - - -==contents of LCMXO2_640HC_impl1.srf -#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 -#install: C:\lscc\diamond\3.12\synpbase -#OS: Windows 8 6.2 -#Hostname: ZANEPC - -# Wed Aug 16 20:59:29 2023 - -#Implementation: impl1 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 -Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) -@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) -@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) -Verilog syntax check successful! - -Compiler output is up to date. No re-compile necessary - -Selecting top level module RAM2GS -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. -Running optimization stage 1 on EFB ....... -Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. -Running optimization stage 1 on REFB ....... -Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB) -@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. -Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB) -Running optimization stage 2 on RAM2GS ....... -Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) -Running optimization stage 2 on REFB ....... -Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) -Running optimization stage 2 on EFB ....... -Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) -Running optimization stage 2 on VLO ....... -Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) -Running optimization stage 2 on VHI ....... -Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) - -For a summary of runtime and memory usage per design unit, please see file: -========================================================== -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv - - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Aug 16 20:59:29 2023 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode - -Linker output is up to date. No re-linking necessary - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Aug 16 20:59:29 2023 - -###########################################################] - -For a summary of runtime and memory usage for all design units, please see file: -========================================================== -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv - -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Aug 16 20:59:29 2023 - -###########################################################] - -@A: multi_srs_gen output is up to date. No run necessary. -To force a re-synthesis, select [Resynthesize All] in menu [Run]. -Click link to view previous log file. -Multi-srs Generator Report -@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr" -Premap Report - -# Wed Aug 16 20:59:30 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) - - -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) - -Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc -@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt -See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt" -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -@N: FX493 |Applying initial value "0" on instance InitReady. -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -@N: FX493 |Applying initial value "0" on instance Ready. -@N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "1" on instance nRCAS. -@N: FX493 |Applying initial value "0" on instance CmdLEDEN. -@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. -@N: FX493 |Applying initial value "1" on instance nRCS. -@N: FX493 |Applying initial value "0" on instance LEDEN. -@N: FX493 |Applying initial value "0" on instance n8MEGEN. -@N: FX493 |Applying initial value "1" on instance nRRAS. -@N: FX493 |Applying initial value "0" on instance CMDUFMWrite. -@N: FX493 |Applying initial value "0" on instance CmdUFMData. -@N: FX493 |Applying initial value "0" on instance C1Submitted. -@N: FX493 |Applying initial value "0" on instance CmdSubmitted. -@N: FX493 |Applying initial value "0" on instance ADSubmitted. -@N: FX493 |Applying initial value "0" on instance XOR8MEG. -@N: FX493 |Applying initial value "0" on instance CmdEnable. -@N: FX493 |Applying initial value "1" on instance nRWE. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) - -@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS - -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 - -0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18 - -0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 - -0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------ -RCLK 65 RCLK(port) CASr2.C - - - -PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) - -nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) - -nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) - -System 0 - - - - -========================================================================================= - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -For details review file gcc_ICG_report.rpt - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -=========================== Non-Gated/Non-Generated Clocks ============================ -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- -@KP:ckid0_0 RCLK port 65 nRWE -@KP:ckid0_1 PHI2 port 18 RA11 -@KP:ckid0_2 nCCAS port 8 WRD[7:0] -@KP:ckid0_3 nCRAS port 14 RowA[9:0] -======================================================================================= - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB) - - -Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 16 20:59:32 2023 - -###########################################################] -Map & Optimize Report - -# Wed Aug 16 20:59:32 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEPC - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) - -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) - -@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] -@N: FX493 |Applying initial value "0" on instance IS[0]. -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -@N: FX493 |Applying initial value "0" on instance IS[1]. -@N: FX493 |Applying initial value "0" on instance IS[2]. -@N: FX493 |Applying initial value "0" on instance IS[3]. - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s -2.34ns 199 / 105 - 2 0h:00m:01s -2.34ns 208 / 105 - 3 0h:00m:01s -2.34ns 208 / 105 -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -Timing driven replication report -Added 4 Registers via timing driven replication -Added 1 LUTs via timing driven replication - - 4 0h:00m:01s -1.83ns 210 / 109 - - - 5 0h:00m:01s -1.83ns 211 / 109 - 6 0h:00m:01s -1.83ns 212 / 109 - 7 0h:00m:01s -1.83ns 212 / 109 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB) - -Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB) - - -Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB) - -@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@N: MT615 |Found clock RCLK with period 16.00ns -@N: MT615 |Found clock PHI2 with period 350.00ns -@N: MT615 |Found clock nCRAS with period 350.00ns -@N: MT615 |Found clock nCCAS with period 350.00ns - - -##### START OF TIMING REPORT #####[ -# Timing report written on Wed Aug 16 20:59:35 2023 -# - - -Top view: RAM2GS -Requested Frequency: 2.9 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: -1.832 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------- -PHI2 2.9 MHz 1.0 MHz 350.000 991.270 -1.832 declared default_clkgroup -RCLK 62.5 MHz 22.1 MHz 16.000 45.315 -0.784 declared default_clkgroup -nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup -nCRAS 2.9 MHz 1.0 MHz 350.000 953.610 -1.725 declared default_clkgroup -System 100.0 MHz NA 10.000 NA 15.472 system system_clkgroup -=================================================================================================================== -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - -@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. -@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. -@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. -@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------- -System RCLK | 16.000 15.472 | No paths - | No paths - | No paths - -RCLK System | 16.000 14.892 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 8.605 | No paths - | No paths - | No paths - -RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths - -RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - -PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.832 -PHI2 PHI2 | No paths - | 350.000 346.115 | 175.000 168.921 | 175.000 173.428 -nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.725 -=============================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: PHI2 -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------- -CMDUFMWrite PHI2 FD1P3AX Q CMDUFMWrite 1.044 -1.832 -CmdSubmitted_fast PHI2 FD1S3AX Q CmdSubmitted_fast 1.044 -1.832 -CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -1.708 -CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 -Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 -CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.921 -Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.921 -Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 168.921 -Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 168.921 -================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------- -wb_adr[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[1] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[2] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[3] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[4] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[5] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[6] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_adr[7] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -wb_cyc_stb PHI2 FD1P3IX SP un1_wb_clk32_i 0.528 -1.832 -wb_dati[0] PHI2 FD1P3AX SP un1_wb_clk32_i 0.528 -1.832 -======================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 1.000 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 0.528 - - - Propagation time: 2.361 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 - - Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q - Ending point: wb_adr[0] / SP - The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[0] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= - - -Path information for path number 2: - Requested Period: 1.000 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 0.528 - - - Propagation time: 2.361 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 - - Number of logic level(s): 1 - Starting point: CmdSubmitted_fast / Q - Ending point: wb_adr[0] / SP - The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CmdSubmitted_fast FD1S3AX Q Out 1.044 1.044 r - -CmdSubmitted_fast Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 B In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 r - -un1_wb_clk32_i Net - - - - 18 -wb_adr[0] FD1P3AX SP In 0.000 2.361 r - -======================================================================================= - - -Path information for path number 3: - Requested Period: 1.000 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 0.528 - - - Propagation time: 2.361 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 - - Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q - Ending point: wb_adr[7] / SP - The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[7] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= - - -Path information for path number 4: - Requested Period: 1.000 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 0.528 - - - Propagation time: 2.361 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 - - Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q - Ending point: wb_adr[6] / SP - The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[6] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= - - -Path information for path number 5: - Requested Period: 1.000 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 0.528 - - - Propagation time: 2.361 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.832 - - Number of logic level(s): 1 - Starting point: CMDUFMWrite / Q - Ending point: wb_adr[5] / SP - The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- -CMDUFMWrite FD1P3AX Q Out 1.044 1.044 r - -CMDUFMWrite Net - - - - 2 -CMDUFMWrite_RNIHQ1E1 ORCALUT4 A In 0.000 1.044 r - -CMDUFMWrite_RNIHQ1E1 ORCALUT4 Z Out 1.317 2.361 f - -un1_wb_clk32_i Net - - - - 18 -wb_adr[5] FD1P3AX SP In 0.000 2.361 f - -======================================================================================= - - - - -==================================== -Detailed Report for Clock: RCLK -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------- -Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 -LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636 -n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 -FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.605 -FS[15] RCLK FD1S3AX Q FS[15] 1.108 8.605 -FS[16] RCLK FD1S3AX Q FS[16] 1.108 8.605 -FS[6] RCLK FD1S3AX Q FS[6] 1.268 8.872 -FS[5] RCLK FD1S3AX Q FS[5] 1.228 8.912 -FS[12] RCLK FD1S3AX Q FS[12] 1.302 9.679 -FS[10] RCLK FD1S3AX Q FS[10] 1.299 9.682 -================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------- -RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 -RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 -RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 -RowA[1] RCLK FD1S3AX D RowAd_0[1] 1.089 -0.784 -RowA[2] RCLK FD1S3AX D RowAd_0[2] 1.089 -0.784 -RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0.784 -RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 -RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 -RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 -RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784 -==================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RBA_0io[0] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RBAd[0] ORCALUT4 B In 0.000 1.256 r - -RBAd[0] ORCALUT4 Z Out 0.617 1.873 r - -RBAd_0[0] Net - - - - 1 -RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - -================================================================================= - - -Path information for path number 2: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[9] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[9] ORCALUT4 B In 0.000 1.256 r - -RowAd[9] ORCALUT4 Z Out 0.617 1.873 f - -RowAd_0[9] Net - - - - 1 -RowA[9] FD1S3AX D In 0.000 1.873 f - -================================================================================= - - -Path information for path number 3: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[8] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[8] ORCALUT4 B In 0.000 1.256 r - -RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[8] Net - - - - 1 -RowA[8] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RBA_0io[1] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RBAd[1] ORCALUT4 B In 0.000 1.256 r - -RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - -RBAd_0[1] Net - - - - 1 -RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - -================================================================================= - - -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[6] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[6] ORCALUT4 B In 0.000 1.256 r - -RowAd[6] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[6] Net - - - - 1 -RowA[6] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - - - -==================================== -Detailed Report for Clock: nCRAS -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------- -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.108 -1.725 -CBR nCRAS FD1S3AX Q CBR 1.148 -1.693 -FWEr nCRAS FD1S3AX Q FWEr 1.108 -1.653 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589 -================================================================================ - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------- -nRCAS_0io nCRAS OFS1P3BX D N_186_i 1.089 -1.725 -nRWE_0io nCRAS OFS1P3BX D N_44_i 1.089 -1.725 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.653 -nRCS_0io nCRAS OFS1P3BX D N_32_i 1.089 -1.653 -======================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.813 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.725 - - Number of logic level(s): 2 - Starting point: CBR_fast / Q - Ending point: nRCAS_0io / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.108 1.108 r - -CBR_fast Net - - - - 3 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.108 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRCAS_0io_RNO ORCALUT4 B In 0.000 2.197 r - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.813 f - -N_186_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.813 f - -======================================================================================== - - -Path information for path number 2: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.813 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.725 - - Number of logic level(s): 2 - Starting point: CBR_fast / Q - Ending point: nRWE_0io / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.108 1.108 r - -CBR_fast Net - - - - 3 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.108 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRWE_0io_RNO ORCALUT4 C In 0.000 2.197 r - -nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.813 r - -N_44_i Net - - - - 1 -nRWE_0io OFS1P3BX D In 0.000 2.813 r - -======================================================================================== - - -Path information for path number 3: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRCAS_0io / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r - -nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - -nRCAS_0io_RNO_0 Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_186_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.781 r - -================================================================================== - - -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f - -N_97 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 2.781 f - -====================================================================================== - - -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.741 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.653 - - Number of logic level(s): 2 - Starting point: FWEr / Q - Ending point: RCKEEN / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.108 1.108 r - -FWEr Net - - - - 3 -RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.108 r - -RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.125 r - -RCKEEN_8_u_1_0 Net - - - - 1 -RCKEEN_8_u ORCALUT4 C In 0.000 2.125 r - -RCKEEN_8_u ORCALUT4 Z Out 0.617 2.741 r - -RCKEEN_8 Net - - - - 1 -RCKEEN FD1S3AX D In 0.000 2.741 r - -================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------ -ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 15.472 -ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 15.472 -========================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------- -LEDEN System FD1P3AX D LEDEN_6_i_m2 16.089 15.472 -n8MEGEN System FD1P3AX D n8MEGEN_6_i_m2 16.089 15.472 -===================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 16.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 16.089 - - - Propagation time: 0.617 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 15.472 - - Number of logic level(s): 1 - Starting point: ufmefb.EFBInst_0 / WBDATO0 - Ending point: n8MEGEN / D - The start point is clocked by System [rising] - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -ufmefb.EFBInst_0 EFB WBDATO0 Out 0.000 0.000 r - -wb_dato[0] Net - - - - 1 -n8MEGEN_6_i_m2 ORCALUT4 C In 0.000 0.000 r - -n8MEGEN_6_i_m2 ORCALUT4 Z Out 0.617 0.617 r - -n8MEGEN_6_i_m2 Net - - - - 1 -n8MEGEN FD1P3AX D In 0.000 0.617 r - -====================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied - -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB) - - -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB) - ---------------------------------------- -Resource Usage Report -Part: lcmxo2_640hc-4 - -Register bits: 109 of 640 (17%) -PIC Latch: 0 -I/O cells: 63 - - -Details: -BB: 8 -CCU2D: 10 -EFB: 1 -FD1P3AX: 27 -FD1P3IX: 3 -FD1S3AX: 51 -FD1S3IX: 3 -GSR: 1 -IB: 25 -IFS1P3DX: 9 -INV: 8 -OB: 30 -OFS1P3BX: 4 -OFS1P3DX: 11 -OFS1P3JX: 1 -ORCALUT4: 206 -PFUMX: 1 -PUR: 1 -VHI: 2 -VLO: 2 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB) - -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Wed Aug 16 20:59:35 2023 - -###########################################################] - - -Synthesis exit by 0. - -edif2ngd -l "MachXO2" -d LCMXO2-640HC -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi" "LCMXO2_640HC_impl1.ngo" -edif2ngd: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Writing the design to LCMXO2_640HC_impl1.ngo... - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 11 MB - - -ngdbuild -a "MachXO2" -d LCMXO2-640HC -p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" "LCMXO2_640HC_impl1.ngo" "LCMXO2_640HC_impl1.ngd" -ngdbuild: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Reading 'LCMXO2_640HC_impl1.ngo' ... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 403 blocks expanded -Complete the first expansion. -Writing 'LCMXO2_640HC_impl1.ngd' ... -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 19 MB - - -map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "LCMXO2_640HC_impl1.ngd" -o "LCMXO2_640HC_impl1_map.ncd" -pr "LCMXO2_640HC_impl1.prf" -mp "LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf" -c 0 -map: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - Process the file: LCMXO2_640HC_impl1.ngd - Picdevice="LCMXO2-640HC" - - Pictype="TQFP100" - - Picspeed=4 - - Remove unused logic - - Do not produce over sized NCDs. - -Part used: LCMXO2-640HCTQFP100, Performance used: 4. - -Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. - -Running general design DRC... - -Removing unused logic... - -Optimizing... - -1 CCU2 constant inputs absorbed. - - - - - -Design Summary: - Number of registers: 109 out of 877 (12%) - PFU registers: 84 out of 640 (13%) - PIO registers: 25 out of 237 (11%) - Number of SLICEs: 117 out of 320 (37%) - SLICEs as Logic/ROM: 117 out of 320 (37%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 230 out of 640 (36%) - Number used as logic LUTs: 210 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. - Number of clocks: 5 - Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) - Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk ) - Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 7 - Net N_245_i: 1 loads, 1 LSLICEs - Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs - Net InitReady: 1 loads, 1 LSLICEs - Net un1_wb_clk32_i: 10 loads, 10 LSLICEs - Net N_18: 2 loads, 2 LSLICEs - Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_193_i: 2 loads, 2 LSLICEs - Number of LSRs: 5 - Net RA10s_i: 1 loads, 0 LSLICEs - Net wb_clk23: 3 loads, 3 LSLICEs - Net wb_rst: 1 loads, 0 LSLICEs - Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 42 loads - Net FS[12]: 27 loads - Net FS[10]: 25 loads - Net FS[11]: 22 loads - Net FS[7]: 17 loads - Net FS[6]: 16 loads - Net Ready: 15 loads - Net Ready_fast: 14 loads - Net nRowColSel: 12 loads - Net S[1]: 12 loads - - - Number of warnings: 1 - Number of errors: 0 - - - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 37 MB - -Dumping design to file LCMXO2_640HC_impl1_map.ncd. +Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved. +Lattice Diamond Version 3.12.1.454 + + +==contents of LCMXO2_640HC_impl1.srf +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEMACWIN11 + +# Sat Aug 19 21:54:48 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) +@I::"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) +Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + +Selecting top level module RAM2GS +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. +Running optimization stage 1 on VHI ....... +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. +Running optimization stage 1 on VLO ....... +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. +Running optimization stage 1 on EFB ....... +Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. +Running optimization stage 1 on REFB ....... +Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) +Running optimization stage 2 on RAM2GS ....... +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on REFB ....... +Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on EFB ....... +Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on VLO ....... +Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on VHI ....... +Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) + +For a summary of runtime and memory usage per design unit, please see file: +========================================================== +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv + + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sat Aug 19 21:54:48 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sat Aug 19 21:54:48 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sat Aug 19 21:54:48 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sat Aug 19 21:54:50 2023 + +###########################################################] +# Sat Aug 19 21:54:50 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB) + +Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc +@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt +See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) + +@N: FX493 |Applying initial value "0" on instance InitReady. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance RCKE. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance CmdUFMShift. +@N: FX493 |Applying initial value "0" on instance CmdUFMWrite. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "0" on instance CmdValid. +@N: FX493 |Applying initial value "1" on instance nRCS. +@N: FX493 |Applying initial value "1" on instance nRRAS. +@N: FX493 |Applying initial value "0" on instance CmdUFMData. +@N: FX493 |Applying initial value "0" on instance C1Submitted. +@N: FX493 |Applying initial value "0" on instance ADSubmitted. +@N: FX493 |Applying initial value "0" on instance XOR8MEG. +@N: FX493 |Applying initial value "0" on instance CmdEnable. +@N: FX493 |Applying initial value "1" on instance nRWE. + +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +======================================================================================== + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +----------------------------------------------------------------------------------------- +RCLK 65 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) + +System 0 - - - - +========================================================================================= + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 RCLK port 65 nRWE +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sat Aug 19 21:54:51 2023 + +###########################################################] +# Sat Aug 19 21:54:51 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) + +@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":149:4:149:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: FX493 |Applying initial value "0" on instance IS[0]. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance IS[1]. +@N: FX493 |Applying initial value "0" on instance IS[2]. +@N: FX493 |Applying initial value "0" on instance IS[3]. + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s -2.36ns 191 / 106 + 2 0h:00m:01s -2.36ns 206 / 106 + 3 0h:00m:01s -2.36ns 202 / 106 +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +Timing driven replication report +Added 5 Registers via timing driven replication +Added 3 LUTs via timing driven replication + + 4 0h:00m:01s -1.83ns 206 / 111 + + + 5 0h:00m:02s -1.83ns 207 / 111 + 6 0h:00m:02s -1.83ns 208 / 111 + 7 0h:00m:02s -1.83ns 208 / 111 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB) + +Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB) + +@W: MT246 :"y:\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@N: MT615 |Found clock RCLK with period 16.00ns +@N: MT615 |Found clock PHI2 with period 350.00ns +@N: MT615 |Found clock nCRAS with period 350.00ns +@N: MT615 |Found clock nCCAS with period 350.00ns + + +##### START OF TIMING REPORT #####[ +# Timing report written on Sat Aug 19 21:54:55 2023 +# + + +Top view: RAM2GS +Requested Frequency: 2.9 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: -1.828 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------- +PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup +RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.876 declared default_clkgroup +nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +nCRAS 2.9 MHz 1.0 MHz 350.000 953.610 -1.725 declared default_clkgroup +System 100.0 MHz NA 10.000 NA 13.991 system system_clkgroup +=================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + +@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------------- +System RCLK | 16.000 13.991 | No paths - | No paths - | No paths - +RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.535 | No paths - | No paths - | No paths - +RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.876 | No paths - +RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - +PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 +PHI2 PHI2 | No paths - | 350.000 347.059 | 175.000 168.905 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.725 +=============================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------ +CmdUFMShift_fast PHI2 FD1P3AX Q CmdUFMShift_fast 1.044 -1.828 +CmdValid_fast PHI2 FD1S3AX Q CmdValid_fast 1.044 -1.828 +CmdUFMShift PHI2 FD1P3AX Q CmdUFMShift 1.108 -1.810 +CmdValid PHI2 FD1S3AX Q CmdValid 1.108 -1.810 +CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -1.746 +CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 +Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 +CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 168.905 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 168.905 +================================================================================================ + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------- +wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i 0.528 -1.828 +======================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.357 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -1.828 + + Number of logic level(s): 1 + Starting point: CmdUFMShift_fast / Q + Ending point: wb_adr[0] / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[0] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.357 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -1.828 + + Number of logic level(s): 1 + Starting point: CmdValid_fast / Q + Ending point: wb_adr[0] / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdValid_fast FD1S3AX Q Out 1.044 1.044 r - +CmdValid_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 B In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[0] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.357 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -1.828 + + Number of logic level(s): 1 + Starting point: CmdUFMShift_fast / Q + Ending point: wb_adr[7] / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[7] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.357 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -1.828 + + Number of logic level(s): 1 + Starting point: CmdUFMShift_fast / Q + Ending point: wb_adr[6] / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[6] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.357 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -1.828 + + Number of logic level(s): 1 + Starting point: CmdUFMShift_fast / Q + Ending point: wb_adr[5] / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +CmdUFMShift_fast FD1P3AX Q Out 1.044 1.044 r - +CmdUFMShift_fast Net - - - - 2 +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 A In 0.000 1.044 r - +CmdUFMShift_fast_RNIG9JD1 ORCALUT4 Z Out 1.313 2.357 r - +un1_wb_rst14_i Net - - - - 17 +wb_adr[5] FD1P3AX SP In 0.000 2.357 r - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: RCLK +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.876 +Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 +InitReady RCLK FD1S3AX Q InitReady 1.321 9.535 +FS[15] RCLK FD1S3AX Q FS[15] 1.180 9.677 +FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.677 +FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.677 +S[1] RCLK FD1S3IX Q S[1] 1.244 9.913 +S[0] RCLK FD1S3IX Q CO0 1.228 9.929 +FS[12] RCLK FD1S3AX Q FS[12] 1.284 10.121 +================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------ +XOR8MEG RCLK FD1P3AX D XOR8MEG_3 1.462 -0.876 +RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 +RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 +RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 +RowA[1] RCLK FD1S3AX D RowAd_0[1] 1.089 -0.784 +RowA[2] RCLK FD1S3AX D RowAd_0[2] 1.089 -0.784 +RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0.784 +RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 +RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 +RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 +==================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.462 + + - Propagation time: 2.339 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.876 + + Number of logic level(s): 2 + Starting point: LEDEN / Q + Ending point: XOR8MEG / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.108 1.108 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_bm ORCALUT4 A In 0.000 1.108 r - +XOR8MEG_3_u_0_bm ORCALUT4 Z Out 1.017 2.125 f - +XOR8MEG_3_u_0_bm Net - - - - 1 +XOR8MEG_3_u_0 PFUMX ALUT In 0.000 2.125 f - +XOR8MEG_3_u_0 PFUMX Z Out 0.214 2.339 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.339 f - +=================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[0] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[0] ORCALUT4 B In 0.000 1.256 r - +RBAd[0] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[0] Net - - - - 1 +RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[9] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[9] ORCALUT4 B In 0.000 1.256 r - +RowAd[9] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[9] Net - - - - 1 +RowA[9] FD1S3AX D In 0.000 1.873 f - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[8] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[8] ORCALUT4 B In 0.000 1.256 r - +RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[8] Net - - - - 1 +RowA[8] FD1S3AX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: nCRAS +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +CBR_fast nCRAS FD1S3AX Q CBR_fast 1.108 -1.725 +CBR nCRAS FD1S3AX Q CBR 1.148 -1.693 +FWEr nCRAS FD1S3AX Q FWEr 1.108 -1.653 +FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589 +================================================================================ + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_249_i 1.089 -1.725 +nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.725 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.653 +nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.653 +======================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.813 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.725 + + Number of logic level(s): 2 + Starting point: CBR_fast / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.108 1.108 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.108 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.197 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.813 f - +N_249_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.813 f - +======================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.813 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.725 + + Number of logic level(s): 2 + Starting point: CBR_fast / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.108 1.108 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.108 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.197 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 C In 0.000 2.197 r - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.813 r - +N_37_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.813 r - +======================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.781 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.693 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.148 1.148 r - +CBR Net - - - - 4 +nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r - +nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - +nRCAS_0io_RNO_0 Net - - - - 1 +nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - +N_249_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.781 r - +================================================================================== + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.781 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.693 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRowColSel / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.148 1.148 r - +CBR Net - - - - 4 +nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r - +nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f - +N_265 Net - - - - 1 +nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f - +nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f - +nRowColSel_0_0 Net - - - - 1 +nRowColSel FD1S3IX D In 0.000 2.781 f - +====================================================================================== + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.741 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.653 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: RCKEEN / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.108 1.108 r - +FWEr Net - - - - 3 +RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.108 r - +RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.125 r - +RCKEEN_8_u_1_0 Net - - - - 1 +RCKEEN_8_u ORCALUT4 C In 0.000 2.125 r - +RCKEEN_8_u ORCALUT4 Z Out 0.617 2.741 r - +RCKEEN_8 Net - - - - 1 +RCKEEN FD1S3AX D In 0.000 2.741 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 13.991 +ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 15.472 +ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 15.472 +========================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------- +LEDEN System FD1P3AX SP un1_FS_38_i 15.528 13.991 +n8MEGEN System FD1P3AX SP un1_FS_38_i 15.528 13.991 +wb_cyc_stb System FD1P3IX SP un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i 15.528 14.297 +LEDEN System FD1P3AX D LEDEN_6 16.089 15.472 +n8MEGEN System FD1P3AX D n8MEGEN_6 16.089 15.472 +========================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 16.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 15.528 + + - Propagation time: 1.538 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 13.991 + + Number of logic level(s): 2 + Starting point: ufmefb.EFBInst_0 / WBACKO + Ending point: LEDEN / SP + The start point is clocked by System [rising] + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - +wb_ack Net - - - - 2 +ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 D In 0.000 0.000 r - +ufmefb.EFBInst_0_RNI9PBJ ORCALUT4 Z Out 0.449 0.449 r - +d_N_5_mux Net - - - - 1 +CmdValid_fast_RNITQBM1 ORCALUT4 C In 0.000 0.449 r - +CmdValid_fast_RNITQBM1 ORCALUT4 Z Out 1.089 1.538 r - +un1_FS_38_i Net - - - - 2 +LEDEN FD1P3AX SP In 0.000 1.538 r - +============================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 111 of 640 (17%) +PIC Latch: 0 +I/O cells: 63 + + +Details: +BB: 8 +CCU2D: 10 +EFB: 1 +FD1P3AX: 28 +FD1P3IX: 2 +FD1S3AX: 52 +FD1S3IX: 4 +GSR: 1 +IB: 25 +IFS1P3DX: 9 +INV: 6 +OB: 30 +OFS1P3BX: 4 +OFS1P3DX: 11 +OFS1P3JX: 1 +ORCALUT4: 199 +PFUMX: 3 +PUR: 1 +VHI: 2 +VLO: 2 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Sat Aug 19 21:54:55 2023 + +###########################################################] + + +Synthesis exit by 0. + +edif2ngd -l "MachXO2" -d LCMXO2-640HC -path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1" -path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC" "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi" "LCMXO2_640HC_impl1.ngo" +edif2ngd: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Writing the design to LCMXO2_640HC_impl1.ngo... + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + + +ngdbuild -a "MachXO2" -d LCMXO2-640HC -p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" -p "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1" -p "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC" "LCMXO2_640HC_impl1.ngo" "LCMXO2_640HC_impl1.ngd" +ngdbuild: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Reading 'LCMXO2_640HC_impl1.ngo' ... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 398 blocks expanded +Complete the first expansion. +Writing 'LCMXO2_640HC_impl1.ngd' ... +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 37 MB + + +map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "LCMXO2_640HC_impl1.ngd" -o "LCMXO2_640HC_impl1_map.ncd" -pr "LCMXO2_640HC_impl1.prf" -mp "LCMXO2_640HC_impl1.mrp" -lpf "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf" -lpf "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: LCMXO2_640HC_impl1.ngd + Picdevice="LCMXO2-640HC" + + Pictype="TQFP100" + + Picspeed=4 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO2-640HCTQFP100, Performance used: 4. + +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. + +Running general design DRC... + +Removing unused logic... + +Optimizing... + +1 CCU2 constant inputs absorbed. + + + + + +Design Summary: + Number of registers: 111 out of 877 (13%) + PFU registers: 86 out of 640 (13%) + PIO registers: 25 out of 237 (11%) + Number of SLICEs: 113 out of 320 (35%) + SLICEs as Logic/ROM: 113 out of 320 (35%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 222 out of 640 (35%) + Number used as logic LUTs: 202 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : Yes + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 ) + Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 6 + Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs + Net XOR8MEG18: 6 loads, 6 LSLICEs + Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs + Net un1_wb_rst14_i: 9 loads, 9 LSLICEs + Net un1_FS_38_i: 2 loads, 2 LSLICEs + Net N_253_i: 2 loads, 2 LSLICEs + Number of LSRs: 5 + Net RA10s_i: 1 loads, 0 LSLICEs + Net wb_rst10: 3 loads, 3 LSLICEs + Net wb_rst: 1 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 2 loads, 2 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net InitReady: 33 loads + Net FS[13]: 22 loads + Net FS[12]: 21 loads + Net FS[14]: 20 loads + Net wb_rst11: 18 loads + Net FS[10]: 16 loads + Net Ready: 16 loads + Net FS[11]: 15 loads + Net FS[9]: 15 loads + Net Ready_fast: 14 loads + + + Number of warnings: 1 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 57 MB + +Dumping design to file LCMXO2_640HC_impl1_map.ncd. + +trce -f "LCMXO2_640HC_impl1.mt" -o "LCMXO2_640HC_impl1.tw1" "LCMXO2_640HC_impl1_map.ncd" "LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:54:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1_map.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:54:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1_map.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 60 MB + + +ldbanno "LCMXO2_640HC_impl1_map.ncd" -n Verilog -o "LCMXO2_640HC_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file LCMXO2_640HC_impl1_mapvo.vo +Writing SDF timing to file LCMXO2_640HC_impl1_mapvo.sdf + +Total CPU Time: 1 secs +Total REAL Time: 0 secs +Peak Memory Usage: 60 MB + +ldbanno "LCMXO2_640HC_impl1_map.ncd" -n VHDL -o "LCMXO2_640HC_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file LCMXO2_640HC_impl1_mapvho.vho +Writing SDF timing to file LCMXO2_640HC_impl1_mapvho.sdf + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 60 MB mpartrce -p "LCMXO2_640HC_impl1.p2t" -f "LCMXO2_640HC_impl1.p3t" -tf "LCMXO2_640HC_impl1.pt" "LCMXO2_640HC_impl1_map.ncd" "LCMXO2_640HC_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" +Sat Aug 19 21:55:01 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf +Preference file: LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 63+4(JTAG)/80 84% used + 63+4(JTAG)/79 85% bonded + IOLOGIC 25/80 31% used + + SLICE 113/320 35% used + + EFB 1/1 100% used + + +Number of Signals: 374 +Number of Connections: 978 + +Pin Constraint Summary: + 63 out of 63 pins locked (100% locked). + +The following 3 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 47) + PHI2_c (driver: PHI2, clk load #: 21) + nCRAS_c (driver: nCRAS, clk load #: 10) + + + + + +The following 1 signal is selected to use the secondary clock routing resources: + nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) + + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +............ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.................... +Placer score = 53481. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 53406 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 4 out of 80 (5%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 + SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 + + PRIMARY : 3 out of 8 (37%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. + 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. + Number of PIO comps: 63; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 3.3V | - | +| 1 | 20 / 20 (100%) | 3.3V | - | +| 2 | 12 / 20 ( 60%) | 3.3V | - | +| 3 | 18 / 20 ( 90%) | 3.3V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 5 secs + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 978 unrouted. +Starting router resource preassignment + + + +Completed router resource preassignment. Real time: 8 secs + +Start NBR router at 21:55:09 08/19/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:55:09 08/19/23 + +Start NBR section for initial routing at 21:55:10 08/19/23 +Level 1, iteration 1 +0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.085ns/0.000ns; real time: 9 secs +Level 2, iteration 1 +0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.138ns/0.000ns; real time: 9 secs +Level 3, iteration 1 +0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.276ns/0.000ns; real time: 9 secs +Level 4, iteration 1 +10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:55:10 08/19/23 +Level 4, iteration 1 +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23 + +Start NBR section for re-routing at 21:55:10 08/19/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for post-routing at 21:55:10 08/19/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 6.966ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 9 secs +Total REAL time: 9 secs +Completely routed. +End of route. 978 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 6.966 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 9 secs +Total REAL time to completion: 10 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 ----- MParTrce Tool ---- -Removing old design directory at request of -rem command line option to this program. -Running par. Please wait . . . +trce -f "LCMXO2_640HC_impl1.pt" -o "LCMXO2_640HC_impl1.twr" "LCMXO2_640HC_impl1.ncd" "LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:55:11 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Sat Aug 19 21:55:11 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf +Design file: lcmxo2_640hc_impl1.ncd +Preference file: lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 60 MB + -Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" -Wed Aug 16 20:59:37 2023 +iotiming "LCMXO2_640HC_impl1.ncd" "LCMXO2_640HC_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 6 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf -Preference file: LCMXO2_640HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 +ibisgen "LCMXO2_640HC_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo2.ibs" +IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454 + +Sat Aug 19 21:55:13 2023 + +Comp: CROW[0] + Site: 10 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: CROW[1] + Site: 16 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[0] + Site: 3 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[1] + Site: 96 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[2] + Site: 88 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[3] + Site: 97 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[4] + Site: 99 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[5] + Site: 98 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[6] + Site: 2 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Din[7] + Site: 1 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: Dout[0] + Site: 76 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[1] + Site: 86 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[2] + Site: 87 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[3] + Site: 85 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[4] + Site: 83 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[5] + Site: 84 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[6] + Site: 78 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: Dout[7] + Site: 82 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: LED + Site: 34 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=24mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: MAin[0] + Site: 14 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[1] + Site: 12 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[2] + Site: 13 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[3] + Site: 21 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[4] + Site: 20 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[5] + Site: 19 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[6] + Site: 24 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[7] + Site: 18 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[8] + Site: 25 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: MAin[9] + Site: 32 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: PHI2 + Site: 8 + Type: IN + IO_TYPE=LVCMOS33 + PULL=DOWN + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: RA[0] + Site: 66 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[10] + Site: 64 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[11] + Site: 59 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[1] + Site: 67 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[2] + Site: 69 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[3] + Site: 71 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[4] + Site: 74 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[5] + Site: 70 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[6] + Site: 68 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[7] + Site: 75 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[8] + Site: 65 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RA[9] + Site: 63 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RBA[0] + Site: 58 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RBA[1] + Site: 60 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RCKE + Site: 53 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RCLK + Site: 62 + Type: IN + IO_TYPE=LVCMOS33 + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: RDQMH + Site: 51 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RDQML + Site: 48 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: RD[0] + Site: 36 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[1] + Site: 37 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[2] + Site: 38 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[3] + Site: 39 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[4] + Site: 40 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[5] + Site: 41 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[6] + Site: 42 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: RD[7] + Site: 43 + Type: BIDI + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + CLAMP=ON + HYSTERESIS=SMALL + SLEW=SLOW +----------------------- +Comp: nCCAS + Site: 9 + Type: IN + IO_TYPE=LVCMOS33 + PULL=UP + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: nCRAS + Site: 17 + Type: IN + IO_TYPE=LVCMOS33 + PULL=UP + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: nFWE + Site: 15 + Type: IN + IO_TYPE=LVCMOS33 + PULL=UP + CLAMP=ON + HYSTERESIS=SMALL +----------------------- +Comp: nRCAS + Site: 52 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: nRCS + Site: 57 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: nRRAS + Site: 54 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Comp: nRWE + Site: 49 + Type: OUT + IO_TYPE=LVCMOS33 + DRIVE=4mA + PULL=KEEPER + SLEW=SLOW +----------------------- +Created design models. + + +Generating: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\IBIS\LCMXO2_640HC_impl1.ibs + + + -Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -License checked out. +ldbanno "LCMXO2_640HC_impl1.ncd" -n Verilog -o "LCMXO2_640HC_impl1_vo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the LCMXO2_640HC_impl1 design file. + + +Loading design for application ldbanno from file LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design LCMXO2_640HC_impl1.ncd into .ldb format. +Loading preferences from lcmxo2_640hc_impl1.prf. +Writing Verilog netlist to file LCMXO2_640HC_impl1_vo.vo +Writing SDF timing to file LCMXO2_640HC_impl1_vo.sdf + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 63 MB +ldbanno "LCMXO2_640HC_impl1.ncd" -n VHDL -o "LCMXO2_640HC_impl1_vho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the LCMXO2_640HC_impl1 design file. + + +Loading design for application ldbanno from file LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design LCMXO2_640HC_impl1.ncd into .ldb format. +Loading preferences from lcmxo2_640hc_impl1.prf. +Writing VHDL netlist to file LCMXO2_640HC_impl1_vho.vho +Writing SDF timing to file LCMXO2_640HC_impl1_vho.sdf + +Total CPU Time: 1 secs +Total REAL Time: 0 secs +Peak Memory Usage: 63 MB -Ignore Preference Error(s): True -Device utilization summary: +tmcheck -par "LCMXO2_640HC_impl1.par" - PIO (prelim) 63+4(JTAG)/80 84% used - 63+4(JTAG)/79 85% bonded - IOLOGIC 25/80 31% used - - SLICE 117/320 36% used - - EFB 1/1 100% used - - -Number of Signals: 380 -Number of Connections: 1008 - -Pin Constraint Summary: - 63 out of 63 pins locked (100% locked). - -The following 3 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 46) - PHI2_c (driver: PHI2, clk load #: 19) - nCRAS_c (driver: nCRAS, clk load #: 10) - - - - - -The following 2 signals are selected to use the secondary clock routing resources: - nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) - un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10) - - -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -.............. -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 55012. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 54994 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 4 out of 80 (5%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 - SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 - SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 - - PRIMARY : 3 out of 8 (37%) - SECONDARY: 2 out of 8 (25%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. - 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. - Number of PIO comps: 63; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 3.3V | - | -| 1 | 20 / 20 (100%) | 3.3V | - | -| 2 | 12 / 20 ( 60%) | 3.3V | - | -| 3 | 18 / 20 ( 90%) | 3.3V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - -0 connections routed; 1008 unrouted. -Starting router resource preassignment - - - - - -Completed router resource preassignment. Real time: 5 secs - -Start NBR router at 20:59:43 08/16/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 20:59:43 08/16/23 - -Start NBR section for initial routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23 -Level 4, iteration 0 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs -Level 4, iteration 0 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs - -Start NBR section for re-routing at 20:59:44 08/16/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs - -Start NBR section for post-routing at 20:59:44 08/16/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 4.922ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - - - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 1008 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 4.922 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.088 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Exiting par with exit code 0 -Exiting mpartrce with exit code 0 +bitgen -f "LCMXO2_640HC_impl1.t2b" -w "LCMXO2_640HC_impl1.ncd" "LCMXO2_640HC_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "LCMXO2_640HC_impl1.bit". +Total CPU Time: 3 secs +Total REAL Time: 3 secs +Peak Memory Usage: 266 MB tmcheck -par "LCMXO2_640HC_impl1.par" bitgen -f "LCMXO2_640HC_impl1.t2b" -w "LCMXO2_640HC_impl1.ncd" -jedec "LCMXO2_640HC_impl1.prf" - - -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - - -Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from LCMXO2_640HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "LCMXO2_640HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 191 Pages (128*191 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). -Initialized UFM Pages: 1 Page (Page 190). - -Total CPU Time: 1 secs -Total REAL Time: 2 secs -Peak Memory Usage: 245 MB + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 1 Page (Page 190). + +Total CPU Time: 3 secs +Total REAL Time: 3 secs +Peak Memory Usage: 266 MB diff --git a/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm index 72b5d0e..5720a2a 100644 --- a/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm +++ b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm @@ -1,197 +1,199 @@ -%%% protect protected_file -@EG -- -]17p0Osk0CksRsPC#MHF=3"4j -"> -!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> -S -S"/ -S1S -SF<1kCsOR"b=BD:\#\OO8lHNF\M8d.34\M#$b#LNCH\DLD\PFko\lOs_NlbH3RP"Nd=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S -S"/ -S1S"/ -< -S/k1Fs#OC>S - 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
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-735,10) (VERI-9000) elaborating module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-614,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.xcf b/CPLD/LCMXO2-640HC/impl1/impl1.xcf
new file mode 100644
index 0000000..384a941
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/impl1.xcf
@@ -0,0 +1,49 @@
+
+
+
+	
+	
+		JTAG
+		
+			
+			1
+			Lattice
+			MachXO2
+			LCMXO2-640HC
+			0x012b9043
+			All
+			LCMXO2-640HC
+			
+				8
+				11111111
+				1
+				0
+			
+			Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
+			08/19/23 07:23:26
+			0xC8BF
+			FLASH Erase,Program,Verify
+			
+		
+	
+	
+		SEQUENTIAL
+		ENTIRED CHAIN
+		No Override
+		TLR
+		TLR
+		
+		1
+	
+	
+		USB2
+		FTUSB-0
+	
+
diff --git a/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1.ior
new file mode 100644
index 0000000..786199b
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1.ior
@@ -0,0 +1,135 @@
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Sat Aug 19 21:55:13 2023
+// M: Minimum Performance Grade
+// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     2.553      4      -0.117     M
+CROW[1] nCRAS F     2.019      4       0.001     M
+Din[0]  PHI2  F     4.715      4       3.636     4
+Din[0]  nCCAS F     0.790      4       0.535     4
+Din[1]  PHI2  F     5.021      4       3.516     4
+Din[1]  nCCAS F     1.086      4       0.264     4
+Din[2]  PHI2  F     3.385      4       3.516     4
+Din[2]  nCCAS F     0.282      4       0.948     4
+Din[3]  PHI2  F     4.644      4       3.516     4
+Din[3]  nCCAS F     1.278      4       0.095     4
+Din[4]  PHI2  F     4.335      4       3.516     4
+Din[4]  nCCAS F     2.446      4      -0.199     M
+Din[5]  PHI2  F     3.662      4       3.516     4
+Din[5]  nCCAS F     0.907      4       0.402     4
+Din[6]  PHI2  F     4.869      4       3.636     4
+Din[6]  nCCAS F     1.378      4       0.023     M
+Din[7]  PHI2  F     4.138      4       3.636     4
+Din[7]  nCCAS F     2.072      4      -0.120     M
+MAin[0] PHI2  F     5.613      4       0.006     M
+MAin[0] nCRAS F     0.244      4       1.146     4
+MAin[1] PHI2  F     3.409      4       0.354     6
+MAin[1] nCRAS F     0.244      4       1.146     4
+MAin[2] PHI2  F     5.391      4       0.132     M
+MAin[2] nCRAS F     0.250      4       1.141     4
+MAin[3] PHI2  F     4.627      4       0.087     M
+MAin[3] nCRAS F     0.507      4       0.910     4
+MAin[4] PHI2  F     5.665      4      -0.133     M
+MAin[4] nCRAS F     0.675      4       0.777     4
+MAin[5] PHI2  F     5.569      4       0.129     M
+MAin[5] nCRAS F     0.050      4       1.238     4
+MAin[6] PHI2  F     5.717      4      -0.141     M
+MAin[6] nCRAS F     0.242      4       1.146     4
+MAin[7] PHI2  F     5.943      4      -0.173     M
+MAin[7] nCRAS F     0.170      4       1.228     4
+MAin[8] nCRAS F     0.759      4       0.696     4
+MAin[9] nCRAS F     0.516      4       0.891     4
+PHI2    RCLK  R    -0.312      M       3.167     4
+nCCAS   RCLK  R     2.600      4      -0.176     M
+nCCAS   nCRAS F     3.106      4      -0.235     M
+nCRAS   RCLK  R     1.803      4      -0.055     M
+nFWE    PHI2  F     4.680      4       0.261     M
+nFWE    nCRAS F     2.234      4       1.143     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     9.922         4        2.878          M
+LED    nCRAS F    10.555         4        3.057          M
+RA[0]  RCLK  R    11.638         4        3.406          M
+RA[0]  nCRAS F    11.771         4        3.430          M
+RA[10] RCLK  R     8.141         4        2.620          M
+RA[11] PHI2  R     8.610         4        2.756          M
+RA[1]  RCLK  R    11.674         4        3.407          M
+RA[1]  nCRAS F    10.635         4        3.155          M
+RA[2]  RCLK  R    12.933         4        3.729          M
+RA[2]  nCRAS F    11.858         4        3.449          M
+RA[3]  RCLK  R    12.587         4        3.664          M
+RA[3]  nCRAS F    11.255         4        3.298          M
+RA[4]  RCLK  R    11.721         4        3.433          M
+RA[4]  nCRAS F    11.153         4        3.297          M
+RA[5]  RCLK  R    12.544         4        3.620          M
+RA[5]  nCRAS F    11.480         4        3.360          M
+RA[6]  RCLK  R    12.984         4        3.775          M
+RA[6]  nCRAS F    11.528         4        3.407          M
+RA[7]  RCLK  R    12.553         4        3.625          M
+RA[7]  nCRAS F    11.610         4        3.368          M
+RA[8]  RCLK  R    11.836         4        3.453          M
+RA[8]  nCRAS F    10.797         4        3.201          M
+RA[9]  RCLK  R    11.182         4        3.271          M
+RA[9]  nCRAS F    11.135         4        3.279          M
+RBA[0] nCRAS F     8.439         4        2.703          M
+RBA[1] nCRAS F     8.439         4        2.703          M
+RCKE   RCLK  R    10.083         4        3.081          M
+RDQMH  RCLK  R    11.381         4        3.325          M
+RDQML  RCLK  R    10.735         4        3.173          M
+RD[0]  nCCAS F     8.223         4        2.594          M
+RD[1]  nCCAS F     8.223         4        2.594          M
+RD[2]  nCCAS F     8.223         4        2.594          M
+RD[3]  nCCAS F     8.223         4        2.594          M
+RD[4]  nCCAS F     8.223         4        2.594          M
+RD[5]  nCCAS F     8.223         4        2.594          M
+RD[6]  nCCAS F     8.223         4        2.594          M
+RD[7]  nCCAS F     8.223         4        2.594          M
+nRCAS  RCLK  R     8.141         4        2.620          M
+nRCS   RCLK  R     8.141         4        2.620          M
+nRRAS  RCLK  R     8.141         4        2.620          M
+nRWE   RCLK  R     8.121         4        2.627          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd
new file mode 100644
index 0000000..5e71898
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd
@@ -0,0 +1,17 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Fmax_0 = 47.556 MHz (2.900 MHz);
+Fmax_1 = 150.150 MHz (2.900 MHz);
+Fmax_2 = 150.150 MHz (2.900 MHz);
+Fmax_3 = 102.312 MHz (62.500 MHz);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Fmax_0 = - (-);
+Fmax_1 = - (-);
+Fmax_2 = - (-);
+Fmax_3 = - (-);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO2-640HC/impl1/run_options.txt b/CPLD/LCMXO2-640HC/impl1/run_options.txt
index fa2c1d6..7621b1f 100644
--- a/CPLD/LCMXO2-640HC/impl1/run_options.txt
+++ b/CPLD/LCMXO2-640HC/impl1/run_options.txt
@@ -1,81 +1,81 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
-#--  Written on Wed Aug 16 20:59:29 2023
-
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
-
-
-#implementation: "impl1"
-impl -add impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_640HC
-set_option -package TG100C
-set_option -speed_grade -4
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 100
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./LCMXO2_640HC_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
+#--  Written on Sat Aug 19 21:54:48 2023
+
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
+
+
+#implementation: "impl1"
+impl -add impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
+
+#device options
+set_option -technology MACHXO2
+set_option -part LCMXO2_640HC
+set_option -package TG100C
+set_option -speed_grade -4
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./LCMXO2_640HC_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO2-640HC/impl1/scratchproject.prs b/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
index 8d7cd5a..5b68d2a 100644
--- a/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
+++ b/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
@@ -1,80 +1,80 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
-
-
-#implementation: "impl1"
-impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_640HC
-set_option -package TG100C
-set_option -speed_grade -4
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 100
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
+
+
+#implementation: "impl1"
+impl -add Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
+
+#device options
+set_option -technology MACHXO2
+set_option -part LCMXO2_640HC
+set_option -package TG100C
+set_option -speed_grade -4
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log b/CPLD/LCMXO2-640HC/impl1/stdout.log
index 61eeca9..52c7b44 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log
@@ -1,82 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:59:29 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:59:29 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:59:29 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:59:29 2023
-
-compiler completed
-# Wed Aug 16 20:59:30 2023
-
-Return Code: 0
-Run Time:00h:00m:01s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 20:59:30 2023
-Up-To-Date: multi_srs_gen. No run necessary
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 20:59:30 2023
-
-premap completed with warnings
-# Wed Aug 16 20:59:32 2023
-
-Return Code: 1
-Run Time:00h:00m:02s
-Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 20:59:32 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 20:59:32 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Wed Aug 16 20:59:35 2023
-
-Return Code: 1
-Run Time:00h:00m:03s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 21:54:47 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 21:54:48 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 21:54:48 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 21:54:48 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 21:54:49 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 21:54:49 2023
+
+multi_srs_gen completed
+# Sat Aug 19 21:54:50 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 21:54:50 2023
+
+premap completed with warnings
+# Sat Aug 19 21:54:51 2023
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 21:54:51 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 21:54:51 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 21:54:55 2023
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
index 0e70380..b6fc644 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
@@ -1,89 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:57:40 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:57:40 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:57:40 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:57:40 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
-
-compiler completed
-# Wed Aug 16 20:57:43 2023
-
-Return Code: 0
-Run Time:00h:00m:03s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 20:57:43 2023
-
-multi_srs_gen completed
-# Wed Aug 16 20:57:43 2023
-
-Return Code: 0
-Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 20:57:43 2023
-
-premap completed with warnings
-# Wed Aug 16 20:57:45 2023
-
-Return Code: 1
-Run Time:00h:00m:02s
-Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 20:57:45 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 20:57:45 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Wed Aug 16 20:57:49 2023
-
-Return Code: 1
-Run Time:00h:00m:04s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 07:28:27 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 07:28:28 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 07:28:28 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 07:28:28 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 07:28:29 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 07:28:29 2023
+
+multi_srs_gen completed
+# Sat Aug 19 07:28:29 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 07:28:29 2023
+
+premap completed with warnings
+# Sat Aug 19 07:28:31 2023
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 07:28:31 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 07:28:31 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 07:28:34 2023
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
index 01eeeba..101760a 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
@@ -1,59 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:52:48 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:52:48 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:52:48 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:52:48 2023
-compiler exited with errors
-Job failed on: proj_1|impl1
-
-Job: "compiler" terminated with error status: 2
-See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
-# Wed Aug 16 20:52:49 2023
-
-Return Code: 2
-Run Time:00h:00m:01s
-Complete: Compile Process on proj_1|impl1
-Complete: Compile on proj_1|impl1
-Complete: Logic Synthesis on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Error: At line 65 while processing "LCMXO2_640HC_impl1_synplify.tcl"
-2
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=9
-exit status=9
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 07:27:36 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 07:27:37 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 07:27:37 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 07:27:37 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 07:27:38 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 07:27:38 2023
+
+multi_srs_gen completed
+# Sat Aug 19 07:27:38 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 07:27:38 2023
+
+premap completed with warnings
+# Sat Aug 19 07:27:40 2023
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 07:27:40 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 07:27:40 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 07:27:43 2023
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
index 71d9674..179c910 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
@@ -1,59 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:52:31 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:52:32 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:52:32 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:52:32 2023
-compiler exited with errors
-Job failed on: proj_1|impl1
-
-Job: "compiler" terminated with error status: 2
-See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
-# Wed Aug 16 20:52:32 2023
-
-Return Code: 2
-Run Time:00h:00m:00s
-Complete: Compile Process on proj_1|impl1
-Complete: Compile on proj_1|impl1
-Complete: Logic Synthesis on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
-2
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=9
-exit status=9
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 07:26:21 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 07:26:21 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 07:26:21 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 07:26:21 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 07:26:23 2023
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 07:26:23 2023
+
+multi_srs_gen completed
+# Sat Aug 19 07:26:23 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 07:26:23 2023
+
+premap completed with warnings
+# Sat Aug 19 07:26:24 2023
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 07:26:25 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 07:26:25 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 07:26:28 2023
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
index 5c65ff4..d430644 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
@@ -1,89 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:44:48 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:44:49 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:44:49 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:44:49 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
-
-compiler completed
-# Wed Aug 16 20:44:51 2023
-
-Return Code: 0
-Run Time:00h:00m:02s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 20:44:51 2023
-
-multi_srs_gen completed
-# Wed Aug 16 20:44:52 2023
-
-Return Code: 0
-Run Time:00h:00m:01s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 20:44:52 2023
-
-premap completed with warnings
-# Wed Aug 16 20:44:54 2023
-
-Return Code: 1
-Run Time:00h:00m:02s
-Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 20:44:54 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 20:44:54 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Wed Aug 16 20:44:57 2023
-
-Return Code: 1
-Run Time:00h:00m:03s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 07:25:17 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 07:25:18 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 07:25:18 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 07:25:18 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 07:25:20 2023
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 07:25:20 2023
+
+multi_srs_gen completed
+# Sat Aug 19 07:25:20 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 07:25:20 2023
+
+premap completed with warnings
+# Sat Aug 19 07:25:21 2023
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 07:25:21 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 07:25:21 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 07:25:25 2023
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
index 1110f0a..5963ad8 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
@@ -1,59 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 20:41:46 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 20:41:47 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 20:41:47 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 20:41:47 2023
-compiler exited with errors
-Job failed on: proj_1|impl1
-
-Job: "compiler" terminated with error status: 2
-See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
-# Wed Aug 16 20:41:47 2023
-
-Return Code: 2
-Run Time:00h:00m:00s
-Complete: Compile Process on proj_1|impl1
-Complete: Compile on proj_1|impl1
-Complete: Logic Synthesis on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
-Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
-2
-TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
-TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
-exit status=9
-exit status=9
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 07:23:03 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 07:23:04 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 07:23:04 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 07:23:04 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+
+compiler completed
+# Sat Aug 19 07:23:05 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 07:23:05 2023
+
+multi_srs_gen completed
+# Sat Aug 19 07:23:05 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 07:23:05 2023
+
+premap completed with warnings
+# Sat Aug 19 07:23:07 2023
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 07:23:07 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 07:23:07 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 07:23:11 2023
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog.tcl b/CPLD/LCMXO2-640HC/impl1/synlog.tcl
index 08b4740..d3eb8ba 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog.tcl
+++ b/CPLD/LCMXO2-640HC/impl1/synlog.tcl
@@ -1 +1 @@
-run_tcl -fg LCMXO2_640HC_impl1_synplify.tcl
+run_tcl -fg LCMXO2_640HC_impl1_synplify.tcl
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap
index ac358a3..59f4d85 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap
@@ -1 +1 @@
-./synwork/LCMXO2_640HC_impl1_comp.rt.csv,LCMXO2_640HC_impl1_comp.rt.csv,Module Runtime Summary
+./synwork/LCMXO2_640HC_impl1_comp.rt.csv,LCMXO2_640HC_impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
index c6bd2e5..bbc040f 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
@@ -1,132 +1,129 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
-Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
-Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-Linker output is up to date. No re-linking necessary
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db
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T0ssI2|NjF3L~#yax+nqw@DhJZ

diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
index 3622db3..33f4e1a 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
@@ -1,28 +1,28 @@
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:58:39 2023
-
-###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:50 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
index c10e02c..721bf3d 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
@@ -1,162 +1,163 @@
-# Wed Aug 16 20:59:30 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
-@N: FX493 |Applying initial value "0" on instance CmdUFMData.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-
-
-Clock Summary
-******************
-
-          Start      Requested     Requested     Clock        Clock                Clock
-Level     Clock      Frequency     Period        Type         Group                Load 
-----------------------------------------------------------------------------------------
-0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
-                                                                                        
-0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
-                                                                                        
-0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                        
-0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
-                                                                                        
-0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
-========================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
------------------------------------------------------------------------------------------
-RCLK       65        RCLK(port)      CASr2.C         -                 -                 
-                                                                                         
-PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                         
-nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                         
-nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-                                                                                         
-System     0         -               -               -                 -                 
-=========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   65         nRWE           
-@KP:ckid0_1       PHI2                port                   18         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 20:59:32 2023
-
-###########################################################]
+# Sat Aug 19 21:54:50 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance CmdUFMShift.
+@N: FX493 |Applying initial value "0" on instance CmdUFMWrite.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "0" on instance CmdValid.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 21:54:51 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db
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diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr
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diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck
index 465056f..44fa3d9 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck
@@ -1,4 +1,4 @@
-ckid0_0:@|S:RCLK@|E:nRWE@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
-ckid0_1:@|S:PHI2@|E:RA11@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
-ckid0_2:@|S:nCCAS@|E:WRD[7:0]@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2
-ckid0_3:@|S:nCRAS@|E:RowA[9:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
+ckid0_0:@|S:RCLK@|E:nRWE@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
+ckid0_1:@|S:PHI2@|E:RA11@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
+ckid0_2:@|S:nCCAS@|E:WRD[7:0]@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2
+ckid0_3:@|S:nCRAS@|E:RowA[9:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/incr_compile.rpt.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/incr_compile.rpt.rptmap
index dbb7528..37531b6 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/incr_compile.rpt.rptmap
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/incr_compile.rpt.rptmap
@@ -1 +1 @@
-./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
+./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/layer0.tlg.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/layer0.tlg.rptmap
index 3910cac..2caf2f3 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/layer0.tlg.rptmap
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/layer0.tlg.rptmap
@@ -1 +1 @@
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
index 05efd23..3dd04db 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
@@ -1,2 +1,2 @@
-@E: CS168 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":72:15:72:15|Port WBCLKI does not exist
-
+@E:Internal Error in c_hdl.exe
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt
index a4cc1cf..016b1a0 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt
@@ -1,9 +1,9 @@
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-@N|Running in 64-bit mode
-
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N|Running in 64-bit mode
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
index 76f0d50..9ba1f89 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
@@ -1,22 +1,23 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":149:4:149:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9|Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":162:4:162:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":120:4:120:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
index be4701a..f383de6 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
@@ -1,28 +1,28 @@
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 109 of 640 (17%)
-PIC Latch:       0
-I/O cells:       63
-
-Details:
-BB:             8
-CCU2D:          10
-EFB:            1
-FD1P3AX:        27
-FD1P3IX:        3
-FD1S3AX:        51
-FD1S3IX:        3
-GSR:            1
-IB:             25
-IFS1P3DX:       9
-INV:            8
-OB:             30
-OFS1P3BX:       4
-OFS1P3DX:       11
-OFS1P3JX:       1
-ORCALUT4:       206
-PFUMX:          1
-PUR:            1
-VHI:            2
-VLO:            2
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 111 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        28
+FD1P3IX:        2
+FD1S3AX:        52
+FD1S3IX:        4
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            6
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       199
+PFUMX:          3
+PUR:            1
+VHI:            2
+VLO:            2
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
index d66136f..dd3742e 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
@@ -1,7 +1,7 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@W: MT246 :"y:\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
index 19787e5..8038930 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
@@ -1,24 +1,24 @@
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   65         nRWE           
-@KP:ckid0_1       PHI2                port                   18         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
index dad55c4..64c9200 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
@@ -1,23 +1,24 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
-@N: FX493 |Applying initial value "0" on instance CmdUFMData.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance CmdUFMShift.
+@N: FX493 |Applying initial value "0" on instance CmdUFMWrite.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "0" on instance CmdValid.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt
index 81e8ed8..860c24f 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt
@@ -1 +1 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db b/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db
index 4c612030f040a26847a3fee120b4c05e5efe5e4c..01f1037a06b54b8c49f69e8dcf6548481c308670 100644
GIT binary patch
delta 2587
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diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
index 4359284..3bce7fa 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
@@ -1 +1 @@
-./LCMXO2_640HC_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+./LCMXO2_640HC_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg
index 591b2fe..cbbec1a 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg
@@ -1,29 +1,29 @@
-@P:  Worst Slack : -1.832
-@P:  PHI2 - Estimated Frequency : 1.0 MHz
-@P:  PHI2 - Requested Frequency : 2.9 MHz
-@P:  PHI2 - Estimated Period : 991.270
-@P:  PHI2 - Requested Period : 350.000
-@P:  PHI2 - Slack : -1.832
-@P:  RCLK - Estimated Frequency : 22.1 MHz
-@P:  RCLK - Requested Frequency : 62.5 MHz
-@P:  RCLK - Estimated Period : 45.315
-@P:  RCLK - Requested Period : 16.000
-@P:  RCLK - Slack : -0.784
-@P:  nCCAS - Estimated Frequency : NA
-@P:  nCCAS - Requested Frequency : 2.9 MHz
-@P:  nCCAS - Estimated Period : NA
-@P:  nCCAS - Requested Period : 350.000
-@P:  nCCAS - Slack : NA
-@P:  nCRAS - Estimated Frequency : 1.0 MHz
-@P:  nCRAS - Requested Frequency : 2.9 MHz
-@P:  nCRAS - Estimated Period : 953.610
-@P:  nCRAS - Requested Period : 350.000
-@P:  nCRAS - Slack : -1.725
-@P:  System - Estimated Frequency : NA
-@P:  System - Requested Frequency : 100.0 MHz
-@P:  System - Estimated Period : NA
-@P:  System - Requested Period : 10.000
-@P:  System - Slack : 15.472
-@P:  Total Area : 214.0
-@P:  Total Area : 0.0
-@P:  CPU Time : 0h:00m:03s
+@P:  Worst Slack : -1.828
+@P:  PHI2 - Estimated Frequency : 1.0 MHz
+@P:  PHI2 - Requested Frequency : 2.9 MHz
+@P:  PHI2 - Estimated Period : 989.870
+@P:  PHI2 - Requested Period : 350.000
+@P:  PHI2 - Slack : -1.828
+@P:  RCLK - Estimated Frequency : 22.1 MHz
+@P:  RCLK - Requested Frequency : 62.5 MHz
+@P:  RCLK - Estimated Period : 45.251
+@P:  RCLK - Requested Period : 16.000
+@P:  RCLK - Slack : -0.876
+@P:  nCCAS - Estimated Frequency : NA
+@P:  nCCAS - Requested Frequency : 2.9 MHz
+@P:  nCCAS - Estimated Period : NA
+@P:  nCCAS - Requested Period : 350.000
+@P:  nCCAS - Slack : NA
+@P:  nCRAS - Estimated Frequency : 1.0 MHz
+@P:  nCRAS - Requested Frequency : 2.9 MHz
+@P:  nCRAS - Estimated Period : 953.610
+@P:  nCRAS - Requested Period : 350.000
+@P:  nCRAS - Slack : -1.725
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : NA
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 13.991
+@P:  Total Area : 205.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm
new file mode 100644
index 0000000..3c1cdbe
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm
@@ -0,0 +1,906 @@
+
    +
+# Sat Aug 19 06:58:28 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+
+@N:MO231 : ram2gs-lcmxo2.v(162) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-lcmxo2.v(149) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -2.34ns		 186 /       106
+   2		0h:00m:01s		    -2.34ns		 202 /       106
+   3		0h:00m:01s		    -2.34ns		 198 /       106
+@N:FX271 : ram2gs-lcmxo2.v(303) | Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(303) | Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(162) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(120) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(120) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+Timing driven replication report
+Added 5 Registers via timing driven replication
+Added 3 LUTs via timing driven replication
+
+   4		0h:00m:01s		    -1.83ns		 202 /       111
+
+
+   5		0h:00m:01s		    -1.83ns		 203 /       111
+   6		0h:00m:01s		    -1.83ns		 204 /       111
+   7		0h:00m:01s		    -1.83ns		 204 /       111
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 196MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 196MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 196MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 196MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB)
+
+@W:MT246 : refb.v(78) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 06:58:31 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -1.828
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       1.0 MHz       350.000       989.870       -1.828     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.251        -0.784     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            14.440     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      14.440  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.956  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      9.406   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.828 
+PHI2      PHI2    |  No paths    -       |  350.000     347.148  |  175.000     169.041  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                                Arrival            
+Instance             Reference     Type         Pin     Net                  Time        Slack  
+                     Clock                                                                      
+------------------------------------------------------------------------------------------------
+CmdUFMShift_fast     PHI2          FD1P3AX      Q       CmdUFMShift_fast     1.044       -1.828 
+CmdValid_fast        PHI2          FD1S3AX      Q       CmdValid_fast        1.044       -1.828 
+CmdValid             PHI2          FD1S3AX      Q       CmdValid             1.108       -1.725 
+CmdUFMShift          PHI2          FD1P3AX      Q       CmdUFMShift          1.108       -1.196 
+CmdUFMWrite          PHI2          FD1P3AX      Q       CmdUFMWrite          1.044       -1.132 
+CmdLEDEN             PHI2          FD1P3AX      Q       CmdLEDEN             1.044       -0.572 
+Cmdn8MEGEN           PHI2          FD1P3AX      Q       Cmdn8MEGEN           1.044       -0.572 
+CmdUFMData           PHI2          FD1P3AX      Q       CmdUFMData           0.972       -0.500 
+Bank_0io[1]          PHI2          IFS1P3DX     Q       Bank[1]              0.972       169.041
+Bank_0io[2]          PHI2          IFS1P3DX     Q       Bank[2]              0.972       169.041
+================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+wb_dati[1]     PHI2          FD1P3AX     SP      un1_wb_rst14_i_0     0.528        -1.828
+=========================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i_0              Net          -        -       -         -           17        
+wb_adr[0]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdValid_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdValid_fast                 FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdValid_fast                 Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     B        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i_0              Net          -        -       -         -           17        
+wb_adr[0]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[7] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i_0              Net          -        -       -         -           17        
+wb_adr[7]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[6] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i_0              Net          -        -       -         -           17        
+wb_adr[6]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[5] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i_0              Net          -        -       -         -           17        
+wb_adr[5]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+               Starting                                         Arrival           
+Instance       Reference     Type        Pin     Net            Time        Slack 
+               Clock                                                              
+----------------------------------------------------------------------------------
+Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
+LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
+n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
+InitReady      RCLK          FD1S3AX     Q       InitReady      1.314       9.406 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.180       9.540 
+FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.180       9.540 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.148       9.572 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.268       9.713 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.268       9.713 
+FS[9]          RCLK          FD1S3AX     Q       FS[9]          1.260       9.721 
+==================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required           
+Instance       Reference     Type         Pin     Net            Time         Slack 
+               Clock                                                                
+------------------------------------------------------------------------------------
+RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
+RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
+RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
+RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
+RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
+RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
+RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
+RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
+RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
+RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
+====================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[0] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[0]          Net          -        -       -         -           1         
+RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[9] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
+RowAd_0[9]         Net          -        -       -         -           1         
+RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[8] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[8]         Net          -        -       -         -           1         
+RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[1] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[1]          Net          -        -       -         -           1         
+RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[6] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[6]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[6]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[6]         Net          -        -       -         -           1         
+RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.108       -1.653
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required           
+Instance       Reference     Type         Pin     Net                Time         Slack 
+               Clock                                                                    
+----------------------------------------------------------------------------------------
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_74_i             1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_76_i             1.089        -1.725
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_242_i            1.089        -1.653
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.653
+========================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_0io_RNO             ORCALUT4     A        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_74_i                    Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
+========================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRWE_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_76_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
+========================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR                 Net          -        -       -         -           3         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.125 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     B        In      0.000     2.125 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.741 r     -         
+N_74_i              Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.741 r     -         
+==================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1       Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR_fast           FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast           Net          -        -       -         -           3         
+nRCS_0io_RNO_0     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.125 f     -         
+N_242_i_1_0        Net          -        -       -         -           1         
+nRCS_0io_RNO       ORCALUT4     C        In      0.000     2.125 f     -         
+nRCS_0io_RNO       ORCALUT4     Z        Out     0.617     2.741 r     -         
+N_242_i            Net          -        -       -         -           1         
+nRCS_0io           OFS1P3BX     D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       14.440
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                              Required           
+Instance     Reference     Type        Pin     Net                 Time         Slack 
+             Clock                                                                    
+--------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     SP      un1_FS_32_i_0_0     15.528       14.440
+n8MEGEN      System        FD1P3AX     SP      un1_FS_32_i_0_0     15.528       14.440
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2      16.089       15.472
+======================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         15.528
+
+    - Propagation time:                      1.089
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 14.440
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            LEDEN / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin        Pin               Arrival     No. of    
+Name                 Type         Name       Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack               Net          -          -       -         -           1         
+un1_FS_32_i_0_0      ORCALUT4     D          In      0.000     0.000 r     -         
+un1_FS_32_i_0_0      ORCALUT4     Z          Out     1.089     1.089 r     -         
+un1_FS_32_i_0_0      Net          -          -       -         -           2         
+LEDEN                FD1P3AX      SP         In      0.000     1.089 r     -         
+=====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 111 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        28
+FD1P3IX:        2
+FD1S3AX:        52
+FD1S3IX:        4
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            8
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       195
+PFUMX:          1
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 77MB peak: 197MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 06:58:32 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_toc.htm
new file mode 100644
index 0000000..097ee43
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_fpga_mapper_toc.htm
@@ -0,0 +1,54 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
index 6e98078..06d8f56 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
@@ -1,32 +1,32 @@
-
    -
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:58:39 2023
-
-###########################################################]
-
-
    
+
    +
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 06:58:26 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
index f7a9a65..78bc7ac 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
@@ -1,25 +1,25 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
  
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_srr.htm
new file mode 100644
index 0000000..5d018f5
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_srr.htm
@@ -0,0 +1,167 @@
+
    +
+# Sat Aug 19 06:58:27 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 139MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+Linked File:  LCMXO2_640HC_impl1_scck.rpt
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMShift. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMWrite. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "0" on instance CmdValid. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMData. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+ClockId_0_0       RCLK                port                   65         nRWE           
+ClockId_0_1       PHI2                port                   19         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 06:58:28 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_toc.htm
new file mode 100644
index 0000000..ac31184
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_premap_toc.htm
@@ -0,0 +1,28 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
index 741590b..440572e 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
@@ -1,1237 +1,1256 @@
-
    -
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 20:59:29 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N:CG364 : machxo2.v(1124) | Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N:CG364 : machxo2.v(1800) | Synthesizing module EFB in library work.
-Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N:CG364 : REFB.v(8) | Synthesizing module REFB in library work.
-Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N:CG364 : RAM2GS-LCMXO2.v(1) | Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-Linked File:  layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-
-Linker output is up to date. No re-linking necessary
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-Linked File:  LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 20:59:29 2023
-
-###########################################################]
-
-
    
-
    -
-
-@A: :  | multi_srs_gen output is up to date. No run necessary. 
-To force a re-synthesis, select [Resynthesize All] in menu [Run].
-Click link to view previous log file.
-Multi-srs Generator Report
-Linked File:  LCMXO2_640HC_impl1_multi_srs_gen.srr
-
-
    
-
    -
-Premap Report
-
-
-
    
-
    -
-# Wed Aug 16 20:59:30 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  LCMXO2_640HC_impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
-
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CMDUFMWrite. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMData. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-
-
-Clock Summary
-******************
-
-          Start      Requested     Requested     Clock        Clock                Clock
-Level     Clock      Frequency     Period        Type         Group                Load 
-----------------------------------------------------------------------------------------
-0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
-                                                                                        
-0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
-                                                                                        
-0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                        
-0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
-                                                                                        
-0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
-========================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
------------------------------------------------------------------------------------------
-RCLK       65        RCLK(port)      CASr2.C         -                 -                 
-                                                                                         
-PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                         
-nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                         
-nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-                                                                                         
-System     0         -               -               -                 -                 
-=========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   65         nRWE           
-ClockId_0_1       PHI2                port                   18         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 20:59:32 2023
-
-###########################################################]
-
-
    
-
    -
-Map & Optimize Report
-
-
-
    
-
    -
-# Wed Aug 16 20:59:32 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:MO231 : ram2gs-lcmxo2.v(161) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-lcmxo2.v(148) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 199 /       105
-   2		0h:00m:01s		    -2.34ns		 208 /       105
-   3		0h:00m:01s		    -2.34ns		 208 /       105
-@N:FX271 : ram2gs-lcmxo2.v(302) | Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-@N:FX271 : ram2gs-lcmxo2.v(161) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
-@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-Timing driven replication report
-Added 4 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -1.83ns		 210 /       109
-
-
-   5		0h:00m:01s		    -1.83ns		 211 /       109
-   6		0h:00m:01s		    -1.83ns		 212 /       109
-   7		0h:00m:01s		    -1.83ns		 212 /       109
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
-
-@W:MT246 : refb.v(78) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 20:59:35 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -1.832
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
-RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
-System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
-PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                      Starting                                                 Arrival            
-Instance              Reference     Type         Pin     Net                   Time        Slack  
-                      Clock                                                                       
---------------------------------------------------------------------------------------------------
-CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
-CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
-CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
-CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
-Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
-CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
-Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
-Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
-Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
-Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
-==================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
-wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
-=======================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.361
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -1.832
-
-    Number of logic level(s):                1
-    Starting point:                          CMDUFMWrite / Q
-    Ending point:                            wb_adr[0] / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                        Pin      Pin               Arrival     No. of    
-Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
-CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
-CMDUFMWrite              Net          -        -       -         -           2         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
-un1_wb_clk32_i           Net          -        -       -         -           18        
-wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
-=======================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.361
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -1.832
-
-    Number of logic level(s):                1
-    Starting point:                          CmdSubmitted_fast / Q
-    Ending point:                            wb_adr[0] / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                        Pin      Pin               Arrival     No. of    
-Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
-CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
-CmdSubmitted_fast        Net          -        -       -         -           2         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
-un1_wb_clk32_i           Net          -        -       -         -           18        
-wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
-=======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.361
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -1.832
-
-    Number of logic level(s):                1
-    Starting point:                          CMDUFMWrite / Q
-    Ending point:                            wb_adr[7] / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                        Pin      Pin               Arrival     No. of    
-Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
-CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
-CMDUFMWrite              Net          -        -       -         -           2         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
-un1_wb_clk32_i           Net          -        -       -         -           18        
-wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
-=======================================================================================
-
-
-Path information for path number 4: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.361
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -1.832
-
-    Number of logic level(s):                1
-    Starting point:                          CMDUFMWrite / Q
-    Ending point:                            wb_adr[6] / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                        Pin      Pin               Arrival     No. of    
-Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
-CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
-CMDUFMWrite              Net          -        -       -         -           2         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
-un1_wb_clk32_i           Net          -        -       -         -           18        
-wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
-=======================================================================================
-
-
-Path information for path number 5: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.361
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -1.832
-
-    Number of logic level(s):                1
-    Starting point:                          CMDUFMWrite / Q
-    Ending point:                            wb_adr[5] / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                        Pin      Pin               Arrival     No. of    
-Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
-CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
-CMDUFMWrite              Net          -        -       -         -           2         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
-CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
-un1_wb_clk32_i           Net          -        -       -         -           18        
-wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
-=======================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
-FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
-FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
-FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 4: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[1] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[1]          Net          -        -       -         -           1         
-RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 5: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[6] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[6]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[6]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[6]         Net          -        -       -         -           1         
-RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
-CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
-nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
-nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
-========================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.813
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.725
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
-CBR_fast                  Net          -        -       -         -           3         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
-N_186_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.813
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.725
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
-CBR_fast                  Net          -        -       -         -           3         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
-N_44_i                    Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.781
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.693
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
-CBR                 Net          -        -       -         -           4         
-nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
-nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
-nRCAS_0io_RNO_0     Net          -        -       -         -           1         
-nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
-nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
-N_186_i             Net          -        -       -         -           1         
-nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
-==================================================================================
-
-
-Path information for path number 4: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.781
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.693
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
-CBR                     Net          -        -       -         -           4         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
-N_97                    Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
-======================================================================================
-
-
-Path information for path number 5: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.741
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.653
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            RCKEEN / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
-FWEr               Net          -        -       -         -           3         
-RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
-RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
-RCKEEN_8_u_1_0     Net          -        -       -         -           1         
-RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
-RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
-RCKEEN_8           Net          -        -       -         -           1         
-RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                     Starting                                          Arrival           
-Instance             Reference     Type     Pin         Net            Time        Slack 
-                     Clock                                                               
------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
-ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
-=========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-             Starting                                             Required           
-Instance     Reference     Type        Pin     Net                Time         Slack 
-             Clock                                                                   
--------------------------------------------------------------------------------------
-LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
-n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
-=====================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      16.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         16.089
-
-    - Propagation time:                      0.617
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 15.472
-
-    Number of logic level(s):                1
-    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
-    Ending point:                            n8MEGEN / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin         Pin               Arrival     No. of    
-Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
-wb_dato[0]           Net          -           -       -         -           1         
-n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
-n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
-n8MEGEN_6_i_m2       Net          -           -       -         -           1         
-n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 109 of 640 (17%)
-PIC Latch:       0
-I/O cells:       63
-
-
-Details:
-BB:             8
-CCU2D:          10
-EFB:            1
-FD1P3AX:        27
-FD1P3IX:        3
-FD1S3AX:        51
-FD1S3IX:        3
-GSR:            1
-IB:             25
-IFS1P3DX:       9
-INV:            8
-OB:             30
-OFS1P3BX:       4
-OFS1P3DX:       11
-OFS1P3JX:       1
-ORCALUT4:       206
-PFUMX:          1
-PUR:            1
-VHI:            2
-VLO:            2
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 20:59:35 2023
-
-###########################################################]
-
-
    
+
    +
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 21:54:48 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2GS
+@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N:CG364 : machxo2.v(1124) | Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N:CG364 : machxo2.v(1800) | Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N:CG364 : REFB.v(8) | Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N:CG364 : RAM2GS-LCMXO2.v(1) | Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+Linked File:  layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+Linked File:  LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:48 2023
+
+###########################################################]
+
+
    
+
    +
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+File Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 21:54:50 2023
+
+###########################################################]
+
+
    
+
    +
+# Sat Aug 19 21:54:50 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+Linked File:  LCMXO2_640HC_impl1_scck.rpt
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMShift. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMWrite. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "0" on instance CmdValid. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMData. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+ClockId_0_0       RCLK                port                   65         nRWE           
+ClockId_0_1       PHI2                port                   19         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 21:54:51 2023
+
+###########################################################]
+
+
    
+
    +
+# Sat Aug 19 21:54:51 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+
+@N:MO231 : ram2gs-lcmxo2.v(162) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-lcmxo2.v(149) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -2.36ns		 191 /       106
+   2		0h:00m:01s		    -2.36ns		 206 /       106
+   3		0h:00m:01s		    -2.36ns		 202 /       106
+@N:FX271 : ram2gs-lcmxo2.v(303) | Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(303) | Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(162) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(120) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(120) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+Timing driven replication report
+Added 5 Registers via timing driven replication
+Added 3 LUTs via timing driven replication
+
+   4		0h:00m:01s		    -1.83ns		 206 /       111
+
+
+   5		0h:00m:02s		    -1.83ns		 207 /       111
+   6		0h:00m:02s		    -1.83ns		 208 /       111
+   7		0h:00m:02s		    -1.83ns		 208 /       111
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
+
+@W:MT246 : refb.v(78) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 21:54:55 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -1.828
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       1.0 MHz       350.000       989.870       -1.828     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.251        -0.876     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            13.991     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      13.991  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.956  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      9.535   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.876   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.828 
+PHI2      PHI2    |  No paths    -       |  350.000     347.059  |  175.000     168.905  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                                Arrival            
+Instance             Reference     Type         Pin     Net                  Time        Slack  
+                     Clock                                                                      
+------------------------------------------------------------------------------------------------
+CmdUFMShift_fast     PHI2          FD1P3AX      Q       CmdUFMShift_fast     1.044       -1.828 
+CmdValid_fast        PHI2          FD1S3AX      Q       CmdValid_fast        1.044       -1.828 
+CmdUFMShift          PHI2          FD1P3AX      Q       CmdUFMShift          1.108       -1.810 
+CmdValid             PHI2          FD1S3AX      Q       CmdValid             1.108       -1.810 
+CmdUFMWrite          PHI2          FD1P3AX      Q       CmdUFMWrite          1.044       -1.746 
+CmdLEDEN             PHI2          FD1P3AX      Q       CmdLEDEN             1.044       -0.572 
+Cmdn8MEGEN           PHI2          FD1P3AX      Q       Cmdn8MEGEN           1.044       -0.572 
+CmdUFMData           PHI2          FD1P3AX      Q       CmdUFMData           0.972       -0.500 
+Bank_0io[0]          PHI2          IFS1P3DX     Q       Bank[0]              0.972       168.905
+Bank_0io[1]          PHI2          IFS1P3DX     Q       Bank[1]              0.972       168.905
+================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+wb_dati[1]     PHI2          FD1P3AX     SP      un1_wb_rst14_i     0.528        -1.828
+=======================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i                Net          -        -       -         -           17        
+wb_adr[0]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdValid_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdValid_fast                 FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdValid_fast                 Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     B        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i                Net          -        -       -         -           17        
+wb_adr[0]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[7] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i                Net          -        -       -         -           17        
+wb_adr[7]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[6] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i                Net          -        -       -         -           17        
+wb_adr[6]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.357
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.828
+
+    Number of logic level(s):                1
+    Starting point:                          CmdUFMShift_fast / Q
+    Ending point:                            wb_adr[5] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+CmdUFMShift_fast              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CmdUFMShift_fast              Net          -        -       -         -           2         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     A        In      0.000     1.044 r     -         
+CmdUFMShift_fast_RNIG9JD1     ORCALUT4     Z        Out     1.313     2.357 r     -         
+un1_wb_rst14_i                Net          -        -       -         -           17        
+wb_adr[5]                     FD1P3AX      SP       In      0.000     2.357 r     -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+               Starting                                         Arrival           
+Instance       Reference     Type        Pin     Net            Time        Slack 
+               Clock                                                              
+----------------------------------------------------------------------------------
+LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.876
+Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
+n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
+InitReady      RCLK          FD1S3AX     Q       InitReady      1.321       9.535 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.180       9.677 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.180       9.677 
+FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.180       9.677 
+S[1]           RCLK          FD1S3IX     Q       S[1]           1.244       9.913 
+S[0]           RCLK          FD1S3IX     Q       CO0            1.228       9.929 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.284       10.121
+==================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required           
+Instance       Reference     Type         Pin     Net            Time         Slack 
+               Clock                                                                
+------------------------------------------------------------------------------------
+XOR8MEG        RCLK          FD1P3AX      D       XOR8MEG_3      1.462        -0.876
+RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
+RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
+RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
+RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
+RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
+RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
+RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
+RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
+RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
+====================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.462
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.462
+
+    - Propagation time:                      2.339
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.876
+
+    Number of logic level(s):                2
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+LEDEN                FD1P3AX      Q        Out     1.108     1.108 r     -         
+LEDEN                Net          -        -       -         -           3         
+XOR8MEG_3_u_0_bm     ORCALUT4     A        In      0.000     1.108 r     -         
+XOR8MEG_3_u_0_bm     ORCALUT4     Z        Out     1.017     2.125 f     -         
+XOR8MEG_3_u_0_bm     Net          -        -       -         -           1         
+XOR8MEG_3_u_0        PFUMX        ALUT     In      0.000     2.125 f     -         
+XOR8MEG_3_u_0        PFUMX        Z        Out     0.214     2.339 f     -         
+XOR8MEG_3            Net          -        -       -         -           1         
+XOR8MEG              FD1P3AX      D        In      0.000     2.339 f     -         
+===================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[0] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[0]          Net          -        -       -         -           1         
+RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[9] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
+RowAd_0[9]         Net          -        -       -         -           1         
+RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
+=================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[8] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[8]         Net          -        -       -         -           1         
+RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[1] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[1]          Net          -        -       -         -           1         
+RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required           
+Instance       Reference     Type         Pin     Net                Time         Slack 
+               Clock                                                                    
+----------------------------------------------------------------------------------------
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_249_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_37_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_28_i             1.089        -1.653
+========================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_249_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
+========================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRWE_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_37_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
+========================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_249_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_265                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
+======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       13.991
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                                                Required           
+Instance       Reference     Type        Pin     Net                                   Time         Slack 
+               Clock                                                                                      
+----------------------------------------------------------------------------------------------------------
+LEDEN          System        FD1P3AX     SP      un1_FS_38_i                           15.528       13.991
+n8MEGEN        System        FD1P3AX     SP      un1_FS_38_i                           15.528       13.991
+wb_cyc_stb     System        FD1P3IX     SP      un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i     15.528       14.297
+LEDEN          System        FD1P3AX     D       LEDEN_6                               16.089       15.472
+n8MEGEN        System        FD1P3AX     D       n8MEGEN_6                             16.089       15.472
+==========================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         15.528
+
+    - Propagation time:                      1.538
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 13.991
+
+    Number of logic level(s):                2
+    Starting point:                          ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            LEDEN / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                            Pin        Pin               Arrival     No. of    
+Name                         Type         Name       Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------
+ufmefb.EFBInst_0             EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                       Net          -          -       -         -           2         
+ufmefb.EFBInst_0_RNI9PBJ     ORCALUT4     D          In      0.000     0.000 r     -         
+ufmefb.EFBInst_0_RNI9PBJ     ORCALUT4     Z          Out     0.449     0.449 r     -         
+d_N_5_mux                    Net          -          -       -         -           1         
+CmdValid_fast_RNITQBM1       ORCALUT4     C          In      0.000     0.449 r     -         
+CmdValid_fast_RNITQBM1       ORCALUT4     Z          Out     1.089     1.538 r     -         
+un1_FS_38_i                  Net          -          -       -         -           2         
+LEDEN                        FD1P3AX      SP         In      0.000     1.538 r     -         
+=============================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 111 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        28
+FD1P3IX:        2
+FD1S3AX:        52
+FD1S3IX:        4
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            6
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       199
+PFUMX:          3
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 21:54:55 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
index d3b0487..399e623 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
@@ -1,60 +1,60 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
  
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
index b95cb8d..053f6d9 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v  -jobname  "compiler" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-LCMXO2.v -lib work -fv2001 ..\..\REFB.v -jobname "compiler"
-rc:0 success:1 runtime:1
-file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:o|time:1692233918|size:21157|exec:0|csum:
-file:..\synlog\LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692233969|size:6365|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\..\RAM2GS-LCMXO2.v|io:i|time:1692233914|size:28573|exec:0|csum:28E8FB7DCCB7771914C4CAAAD23A3A6B
-file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\REFB.v|io:i|time:1692233522|size:5624|exec:0|csum:AE22D4C116724FF57C15D0DA14242382
-file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
+C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC  -I Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v -lib work -fv2001 Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v  -jobname  "compiler" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-LCMXO2.v -lib work -fv2001 ..\..\REFB.v -jobname "compiler"
+rc:0 success:1 runtime:1
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:o|time:1692496488|size:21082|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692496488|size:6217|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\..\RAM2GS-LCMXO2.v|io:i|time:1692444754|size:21616|exec:0|csum:0F393AB914949E717BF46EC509D6B55E
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\REFB.v|io:i|time:1692444420|size:5679|exec:0|csum:0C5FF84B97A40274D01225BAA906AD7B
+file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
index 77a28d0..a0341eb 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -oedif ..\LCMXO2_640HC_impl1.edi -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
-rc:1 success:1 runtime:3
-file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233975|size:204145|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:i|time:1692233971|size:28839|exec:0|csum:6AF572CB579AF7B57405A148BF7BEB9E
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:LCMXO2_640HC_impl1.plg|io:o|time:1692233975|size:1070|exec:0|csum:
-file:..\LCMXO2_640HC_impl1.srm|io:o|time:1692233974|size:38081|exec:0|csum:
-file:..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692233975|size:50128|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi   -freq 100.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -oedif ..\LCMXO2_640HC_impl1.edi -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
+rc:1 success:1 runtime:4
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692496494|size:198884|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:i|time:1692496491|size:28530|exec:0|csum:855C700F2374B4E67FE967AE38B1E8E0
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692496495|size:1070|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.srm|io:o|time:1692496494|size:37759|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692496495|size:51516|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
index cf97934..22f83b3 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -1,7 +1,7 @@
-C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\LCMXO2_640HC_impl1_mult.srs -log ..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr
-rc:0 success:1 runtime:0
-file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:i|time:1692233918|size:21157|exec:0|csum:BB526DCCC65867AFD6AA24AF2B7D8510
-file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:o|time:1692233919|size:13269|exec:0|csum:
-file:..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692233919|size:1156|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
+C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -log  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\LCMXO2_640HC_impl1_mult.srs -log ..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr
+rc:0 success:1 runtime:1
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:i|time:1692496488|size:21082|exec:0|csum:836A652852FF4B083104CDAE3FE041B6
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:o|time:1692496490|size:13087|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692496490|size:1142|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
index 736b297..af8b4ba 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
@@ -1,14 +1,14 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_cck.rpt   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -oedif ..\LCMXO2_640HC_impl1.edi -conchk_prepass ..\LCMXO2_640HC_impl1_cck.rpt -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\synwork\LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
-rc:1 success:1 runtime:2
-file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233923|size:210943|exec:0|csum:
-file:..\LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692233972|size:4979|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:i|time:1692233919|size:13269|exec:0|csum:9E33176D7D9CB39EFA557E27492465CA
-file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:LCMXO2_640HC_impl1.plg|io:o|time:1692233970|size:0|exec:0|csum:
-file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
-file:..\synlog\LCMXO2_640HC_impl1_premap.srr|io:o|time:1692233972|size:8565|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi  -conchk_prepass  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_cck.rpt   -freq 100.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -oedif ..\LCMXO2_640HC_impl1.edi -conchk_prepass ..\LCMXO2_640HC_impl1_cck.rpt -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\synwork\LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
+rc:1 success:1 runtime:1
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692444765|size:198883|exec:0|csum:
+file:..\LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692496491|size:4865|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:i|time:1692496490|size:13087|exec:0|csum:61E80912990BDA14052126B047A737B2
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692496491|size:28530|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692496490|size:0|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692496491|size:28530|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_premap.srr|io:o|time:1692496491|size:8572|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
index 9175808..e1af418 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
@@ -1,114 +1,116 @@
- 
- 			 			
-			Project Status Summary Page
-			
-			
-			
-
- 			
- 			
-
     
- 
- 
-
- 		  
-		 
-
-
-
- 
- 
-  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO2 : LCMXO2_640HC 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  1  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
- 				   
-         
- 		
- 			
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- 
-
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-
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-
- 
-
- 		
-     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete800-00m:00s-8/16/2023
    8:59:29 PM
     (premap)Complete23100m:01s0m:01s175MB8/16/2023
    8:59:32 PM
     (fpga_mapper)Complete22700m:03s0m:03s193MB8/16/2023
    8:59:35 PM
    
- 
     
- 
- 				   
- 
-  
-  
-
-
-
- 
-
-
-
- 
-
- 
-
-    
    Area Summary
     
     
     
    Register bits 109I/O cells 63
    Block RAMs
-(v_ram) 0DSPs
-(dsp_used) 0
    ORCA LUTs
-(total_luts) 206

    
- 
- 				   
- 
-  
- 
-    
- 
- 
- 
- 
- 
- 
- 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz1.0 MHz-1.832
     RCLK62.5 MHz22.1 MHz-0.784
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz1.0 MHz-1.725
     System100.0 MHzNA15.472
    
-
    
- 
- 				   
-  
-
- 
-
-    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
-
     
-
     
+ 
+ 			 			
+			Project Status Summary Page
+			
+			
+			
+
+ 			
+ 			
+
     
+ 
+ 
+
+ 		  
+		 
+
+
+
+ 
+ 
+  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO2 : LCMXO2_640HC 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  1  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
+ 				   
+         
+ 		
+ 			
+			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+         
+  
+  
+ 
+
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+
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+  
+ 
+ 
+
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+
+
+  
+  
+     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete800-00m:00s-8/19/2023
    9:54:48 PM
     (premap)Complete24100m:01s0m:01s184MB8/19/2023
    9:54:51 PM
     (fpga_mapper)Complete23700m:03s0m:03s202MB8/19/2023
    9:54:55 PM
    Multi-srs GeneratorComplete00m:01s8/19/2023
    9:54:50 PM    		 		
    
+ 
     
+ 
+ 				   
+ 
+  
+  
+
+
+
+ 
+
+
+
+ 
+
+ 
+
+    
    Area Summary
     
     
     
    Register bits 111I/O cells 63
    Block RAMs
+(v_ram) 0DSPs
+(dsp_used) 0
    ORCA LUTs
+(total_luts) 199

    
+ 
+ 				   
+ 
+  
+ 
+    
+ 
+ 
+ 
+ 
+ 
+ 
+ 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz1.0 MHz-1.828
     RCLK62.5 MHz22.1 MHz-0.876
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz1.0 MHz-1.725
     System100.0 MHzNA13.991
    
+
    
+ 
+ 				   
+  
+
+ 
+
+    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
+
     
+
     
  
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer b/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer
index 5be0367a8d17ca95aac755314f30f037738728a8..56f0d3b9348388deefa6c4458abf1028991380fe 100644
GIT binary patch
delta 417
zcmV;S0bc&m1JDDIIe!w$s3)is<4Wrp_8qq8rj=SHfmLM$T7EqP2QFOk&Ck};`|SHO
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z+vO6vU&k+m0>ak?U3VTD%r_EGuG2fh&F~gaZ=N2yVd-GID1UJd;n2cR`ui~HUri8>
znQlEZEGLY4L?}U&GbKSPylzI66=E6A^X%eOr|?KSL7YuO8w1M0`WiQ7Y|$X&K7s>Q
zo)gy9Lq>HW!Bo*X_=c1XRwSubwO%0~0ljsyx===CwgAs3X5Q?!qJyTLM5~EoYdDmb
z9;1vPpQ_;+T7QPm$z|2@+ppbJ(lOV@R9Z)+OiFv#RY>hvd#3518%Q;oKs9#`D&^0g
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L#&GC@wE_SDG)v3;

delta 418
zcmV;T0bTyk1JMJJIe)Uis3)is<4Wrp`VQOkhLyHTLRXa$X!-RF9Jp|;Z+^C(-e(^!
zV64-%@Z{eK?8Z3}L-xK#Y%ItWHvusleI9YkTweK?7OWm*HRO5fy5n{p+Dy<-%P=Rr
zZs%+0ZW+E23J6a#y6&=VFx^T#yN>S&x7)Wky*YjDwsQyDM1P4>2=^@vr9XsG|7n7-
z&vfURVL4&Q140R+oGA%X;bk?VtPsm^o+cNkI)z8t2;yWC+89vot*>!Y#u^PW>>@Z|
z;VEHRJY-ZC5{wm{gRe;0U`3K@RqGY<9?&}{s|#gNW()9qX6DuIDmrM~NVJ+bwubxi
z++&ado))Z0RR63
M052JwOtk_403eCYVgLXD

diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
index 68dc0e5..084e3fa 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
@@ -1,21 +1,21 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
-1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
-#Dependency Lists(Uses List)
-0 1
-1 -1
-#Dependency Lists(Users Of)
-0 -1
-1 0
-#Design Unit to File Association
-module work REFB 1
-module work RAM2GS 0
+#OPTIONS:"|-layerid|0|-orig_srs|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692444754
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692444420
+0			"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work REFB 1
+module work RAM2GS 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
index 915b7cd..0b328e3 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
@@ -1 +1 @@
-Library, Design Unit, compile Time, Peak Mem Usage
+Library, Design Unit, compile Time, Peak Mem Usage
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs
index c9a54d2cd0f41663287e823860c8bf887f907c71..1216a87adac367e7b6b73734faacaa8f5c873afe 100644
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
index bf5564a..952e493 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
@@ -1,26 +1,26 @@
-i RCLK
-m 0 0
-u 30 65
-p {p:RCLK}{t:nRWE.C}
-e ckid0_0 {t:nRWE.C} dffs
-c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
-i PHI2
-m 0 0
-u 11 18
-p {p:PHI2}{t:RA11.C}
-e ckid0_1 {t:RA11.C} sdffr
-c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
-i nCCAS
-m 0 0
-u 1 8
-p {p:nCCAS}{t:CASr_2.I[0]}{t:CASr_2.OUT[0]}{t:WRD[7:0].C}
-e ckid0_2 {t:WRD[7:0].C} dff
-c ckid0_2 {p:nCCAS} port Unsupported/too complex instance on clock path
-i nCRAS
-m 0 0
-u 4 14
-p {p:nCRAS}{t:RASr_2.I[0]}{t:RASr_2.OUT[0]}{t:RowA[9:0].C}
-e ckid0_3 {t:RowA[9:0].C} sdffpatr
-c ckid0_3 {p:nCRAS} port Unsupported/too complex instance on clock path
-l 0 0 0 0 0 0
-r 0 0 0 0 0 0 0 0
+i RCLK
+m 0 0
+u 30 65
+p {p:RCLK}{t:nRWE.C}
+e ckid0_0 {t:nRWE.C} dffs
+c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
+i PHI2
+m 0 0
+u 12 19
+p {p:PHI2}{t:RA11.C}
+e ckid0_1 {t:RA11.C} sdffr
+c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
+i nCCAS
+m 0 0
+u 1 8
+p {p:nCCAS}{t:CASr_2.I[0]}{t:CASr_2.OUT[0]}{t:WRD[7:0].C}
+e ckid0_2 {t:WRD[7:0].C} dff
+c ckid0_2 {p:nCCAS} port Unsupported/too complex instance on clock path
+i nCRAS
+m 0 0
+u 4 14
+p {p:nCRAS}{t:RASr_2.I[0]}{t:RASr_2.OUT[0]}{t:RowA[9:0].C}
+e ckid0_3 {t:RowA[9:0].C} sdffpatr
+c ckid0_3 {p:nCRAS} port Unsupported/too complex instance on clock path
+l 0 0 0 0 0 0
+r 0 0 0 0 0 0 0 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs
index e9279133688462e42dc52dc7c6191e6ec2c8efc4..53b41edf41501d10c82c5b1730ba637a56454c1f 100644
GIT binary patch
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/1.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/1.srs
index ea524b7f32e20664cf280d32644c0dd8b76e0172..66bbae307d49dec447f45685a85e4356f5e4095f 100644
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/fileinfo.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/fileinfo.srs
index bdbde5add3ecfe5347053e4a5ed8d5a3e970c0ee..461334475a25b6771d7b4469d22e5b8f3b852710 100644
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z1=RL{S)}z+QktW-C(Klzv=>a?BJ~w7Iz~Tfp{0An%+b>RFbi_5w~vsHu`kT&MQZy=
zy%K4En1xCMU{0)38wewJdB{UvM>C5((qNcL719t%BSo^rRhl#u=G;7K7|e2?G#qBB
zMe2ZASt5;qfz}%-6i^!lQ%I3U!>lNi#z-$|(pZ?aK4~1xSryU&FlQ7<<6%A?k`9Df
zS0zn=xll{fFlVNy9VApFO_b5J-oY@d)6@=uSr(8Eg*n?IbqbY88JLR#QWoa?9LbjB
zRn37p$D`)LtSXR<^z4%kgIS}a9S(DzN9_oh3oKF&W=W28B+Le%bd-E^Q;~Eu%%uV8
z7??{UXlp+f=JE>ZIGFWHlcZjr+VN7aK$;Bm+cIei%i(R2j`9&4+m|O: 8.344ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.405ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:47 08/16/23
-Level 4, iteration 1
-5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:47 08/16/23
-
-Start NBR section for re-routing at 04:50:47 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 04:50:47 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 8.213ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 8.213
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:53:22 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            8.213        0            0.273        0            08           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Sat Aug 19 20:53:22 2023
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             69/128          53% used
+
+
+
+Number of Signals: 251
+Number of Connections: 633
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 32)
+    PHI2_c (driver: PHI2, clk load #: 14)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 582801.
+Finished Placer Phase 1.  REAL time: 7 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  582334
+Finished Placer Phase 2.  REAL time: 7 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 80 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 32
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 14
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 7 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 633 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 20:53:30 08/19/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 20:53:30 08/19/23
+
+Start NBR section for initial routing at 20:53:30 08/19/23
+Level 1, iteration 1
+0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 8 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.405ns/0.000ns; real time: 8 secs 
+Level 4, iteration 1
+10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 20:53:30 08/19/23
+Level 4, iteration 1
+5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:53:30 08/19/23
+
+Start NBR section for re-routing at 20:53:30 08/19/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Start NBR section for post-routing at 20:53:30 08/19/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 8.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Total CPU time 8 secs 
+Total REAL time: 8 secs 
+Completely routed.
+End of route.  633 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 8.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.273
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 8 secs 
+Total REAL time to completion: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
index 0733b95..3c20bac 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
@@ -1,79 +1,79 @@
-SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 04:50:40 2023
-
-SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "RD[7]" SITE "71" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-FREQUENCY PORT "PHI2" 2.900000 MHz ;
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-FREQUENCY PORT "RCLK" 62.500000 MHz ;
-SCHEMATIC END ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-COMMERCIAL ;
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 20:53:19 2023
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+FREQUENCY PORT "PHI2" 2.900000 MHz ;
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+FREQUENCY PORT "RCLK" 62.500000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srd
index ff7e47c3e975359ee9b1238bc4aa2ce57d4d4e55..49b09d37651a1a285a61e6c40852c3bdbdb00d7e 100644
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diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf
index 0ac6c6d..efe34bb 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf
@@ -1,966 +1,968 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:31 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:32 2023
-
-###########################################################]
-# Wed Aug 16 04:50:33 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
-
-###########################################################]
-# Wed Aug 16 04:50:35 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:01s		    -2.99ns		 127 /        92
-   9		0h:00m:01s		    -3.09ns		 127 /        92
-  10		0h:00m:01s		    -3.19ns		 127 /        92
-  11		0h:00m:01s		    -3.19ns		 127 /        92
-  12		0h:00m:01s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 20:53:10 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:12 2023
+
+###########################################################]
+Premap Report
+
+# Sat Aug 19 20:53:12 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:53:14 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Sat Aug 19 20:53:14 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:53:17 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo256c-3
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:53:17 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srm b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srm
index d2aeb3028d90946df4805ea9455def2497615121..75366db0c10135c7678851b3da36016dc99a23de 100644
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diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr
index 0ac6c6d..efe34bb 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr
@@ -1,966 +1,968 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:31 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:32 2023
-
-###########################################################]
-# Wed Aug 16 04:50:33 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
-
-###########################################################]
-# Wed Aug 16 04:50:35 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:01s		    -2.99ns		 127 /        92
-   9		0h:00m:01s		    -3.09ns		 127 /        92
-  10		0h:00m:01s		    -3.19ns		 127 /        92
-  11		0h:00m:01s		    -3.19ns		 127 /        92
-  12		0h:00m:01s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 20:53:10 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:12 2023
+
+###########################################################]
+Premap Report
+
+# Sat Aug 19 20:53:12 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:53:14 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Sat Aug 19 20:53:14 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:53:17 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo256c-3
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:53:17 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr.db b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr.db
index 63e67f1eb13cd1334eff0e1de1facd2f4ffac96b..19801ff03919adc71ac2c45cb2cf2b61e4aa8b1d 100644
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delta 36
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diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
index 5afabac..1bef7db 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
@@ -1,2922 +1,2922 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:41 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1_SLICE_65I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_B")
-    (INSTANCE RD_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_B")
-    (INSTANCE Dout_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2B")
-    (INSTANCE PHI2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2S) (1250:1250:1250))
-      (WIDTH (negedge PHI2S) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDOB")
-    (INSTANCE UFMSDOI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
-      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDIB")
-    (INSTANCE UFMSDII)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLKB")
-    (INSTANCE UFMCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCSB")
-    (INSTANCE nUFMCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMLB")
-    (INSTANCE RDQMLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMHB")
-    (INSTANCE RDQMHI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCASB")
-    (INSTANCE nRCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRASB")
-    (INSTANCE nRRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWEB")
-    (INSTANCE nRWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKEB")
-    (INSTANCE RCKEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLKB")
-    (INSTANCE RCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLKS) (1250:1250:1250))
-      (WIDTH (negedge RCLKS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCSB")
-    (INSTANCE nRCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_B")
-    (INSTANCE RD_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_B")
-    (INSTANCE RD_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_B")
-    (INSTANCE RD_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_B")
-    (INSTANCE RD_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_B")
-    (INSTANCE RD_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_B")
-    (INSTANCE RD_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_B")
-    (INSTANCE RD_1_I0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_B")
-    (INSTANCE RA_11_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_B")
-    (INSTANCE RA_10_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_B")
-    (INSTANCE RA_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_B")
-    (INSTANCE RA_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_B")
-    (INSTANCE RA_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_B")
-    (INSTANCE RA_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_B")
-    (INSTANCE RA_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_B")
-    (INSTANCE RA_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_B")
-    (INSTANCE RA_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_B")
-    (INSTANCE RA_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_B")
-    (INSTANCE RA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_B")
-    (INSTANCE RA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_B")
-    (INSTANCE RBA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_B")
-    (INSTANCE RBA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LEDB")
-    (INSTANCE LEDI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWEB")
-    (INSTANCE nFWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWES) (1250:1250:1250))
-      (WIDTH (negedge nFWES) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRASB")
-    (INSTANCE nCRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRASS) (1250:1250:1250))
-      (WIDTH (negedge nCRASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCASB")
-    (INSTANCE nCCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCASS) (1250:1250:1250))
-      (WIDTH (negedge nCCASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_B")
-    (INSTANCE Dout_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_B")
-    (INSTANCE Dout_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_B")
-    (INSTANCE Dout_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_B")
-    (INSTANCE Dout_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_B")
-    (INSTANCE Dout_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_B")
-    (INSTANCE Dout_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_B")
-    (INSTANCE Dout_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_B")
-    (INSTANCE Din_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_B")
-    (INSTANCE Din_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_B")
-    (INSTANCE Din_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_B")
-    (INSTANCE Din_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_B")
-    (INSTANCE Din_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_B")
-    (INSTANCE Din_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_B")
-    (INSTANCE Din_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_B")
-    (INSTANCE Din_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_B")
-    (INSTANCE CROW_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_B")
-    (INSTANCE CROW_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_B")
-    (INSTANCE MAin_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_B")
-    (INSTANCE MAin_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_B")
-    (INSTANCE MAin_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_B")
-    (INSTANCE MAin_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_B")
-    (INSTANCE MAin_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_B")
-    (INSTANCE MAin_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_B")
-    (INSTANCE MAin_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_B")
-    (INSTANCE MAin_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_B")
-    (INSTANCE MAin_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_B")
-    (INSTANCE MAin_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_9I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_67I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_90I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/F0 SLICE_9I/B1 (0:0:0)(0:0:0))
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-        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0))
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-        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (0:0:0)(0:0:0))
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-        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (0:0:0)(0:0:0))
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-        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (0:0:0)(0:0:0))
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-        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/F0 SLICE_31I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F1 SLICE_32I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/F0 SLICE_32I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F1 SLICE_32I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F1 SLICE_58I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F1 SLICE_64I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F1 SLICE_72I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F0 SLICE_32I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32I/F1 SLICE_87I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_33I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/F0 SLICE_39I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_39I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_75I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_78I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_I/PADDI SLICE_85I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_39I/F1 SLICE_57I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41I/F1 SLICE_41I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43I/F1 SLICE_41I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F0 SLICE_43I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F0 SLICE_61I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F0 SLICE_62I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/F0 SLICE_43I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/F0 SLICE_44I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F0 SLICE_51I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_51I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F1 SLICE_51I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_52I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_52I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_75I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/F1 SLICE_70I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_76I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_85I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F1 SLICE_57I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_57I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_85I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F0 SLICE_59I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 SLICE_59I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F1 SLICE_59I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F0 SLICE_62I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F1 SLICE_63I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F1 SLICE_64I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F1 SLICE_68I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F0 SLICE_69I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F0 SLICE_68I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F1 SLICE_69I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F1 SLICE_71I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F1 SLICE_72I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F1 SLICE_77I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F1 SLICE_80I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:53:22 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1_SLICE_65I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_B")
+    (INSTANCE RD_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_B")
+    (INSTANCE Dout_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2B")
+    (INSTANCE PHI2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2S) (1250:1250:1250))
+      (WIDTH (negedge PHI2S) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDOB")
+    (INSTANCE UFMSDOI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
+      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDIB")
+    (INSTANCE UFMSDII)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLKB")
+    (INSTANCE UFMCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCSB")
+    (INSTANCE nUFMCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMLB")
+    (INSTANCE RDQMLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMHB")
+    (INSTANCE RDQMHI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCASB")
+    (INSTANCE nRCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRASB")
+    (INSTANCE nRRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWEB")
+    (INSTANCE nRWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKEB")
+    (INSTANCE RCKEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLKB")
+    (INSTANCE RCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLKS) (1250:1250:1250))
+      (WIDTH (negedge RCLKS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCSB")
+    (INSTANCE nRCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_B")
+    (INSTANCE RD_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_B")
+    (INSTANCE RD_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_B")
+    (INSTANCE RD_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_B")
+    (INSTANCE RD_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_B")
+    (INSTANCE RD_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_B")
+    (INSTANCE RD_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_B")
+    (INSTANCE RD_1_I0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_B")
+    (INSTANCE RA_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_B")
+    (INSTANCE RA_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_B")
+    (INSTANCE RA_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_B")
+    (INSTANCE RA_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_B")
+    (INSTANCE RA_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_B")
+    (INSTANCE RA_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_B")
+    (INSTANCE RA_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_B")
+    (INSTANCE RA_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_B")
+    (INSTANCE RA_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_B")
+    (INSTANCE RA_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_B")
+    (INSTANCE RA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_B")
+    (INSTANCE RA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_B")
+    (INSTANCE RBA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_B")
+    (INSTANCE RBA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LEDB")
+    (INSTANCE LEDI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWEB")
+    (INSTANCE nFWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWES) (1250:1250:1250))
+      (WIDTH (negedge nFWES) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRASB")
+    (INSTANCE nCRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRASS) (1250:1250:1250))
+      (WIDTH (negedge nCRASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCASB")
+    (INSTANCE nCCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCASS) (1250:1250:1250))
+      (WIDTH (negedge nCCASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_B")
+    (INSTANCE Dout_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_B")
+    (INSTANCE Dout_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_B")
+    (INSTANCE Dout_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_B")
+    (INSTANCE Dout_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_B")
+    (INSTANCE Dout_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_B")
+    (INSTANCE Dout_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_B")
+    (INSTANCE Dout_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_B")
+    (INSTANCE Din_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_B")
+    (INSTANCE Din_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_B")
+    (INSTANCE Din_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_B")
+    (INSTANCE Din_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_B")
+    (INSTANCE Din_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_B")
+    (INSTANCE Din_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_B")
+    (INSTANCE Din_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_B")
+    (INSTANCE Din_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_B")
+    (INSTANCE CROW_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_B")
+    (INSTANCE CROW_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_B")
+    (INSTANCE MAin_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_B")
+    (INSTANCE MAin_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_B")
+    (INSTANCE MAin_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_B")
+    (INSTANCE MAin_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_B")
+    (INSTANCE MAin_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_B")
+    (INSTANCE MAin_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_B")
+    (INSTANCE MAin_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_B")
+    (INSTANCE MAin_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_B")
+    (INSTANCE MAin_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_B")
+    (INSTANCE MAin_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_9I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_67I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_90I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F0 SLICE_9I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F1 SLICE_9I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_9I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_14I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F1 SLICE_9I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F1 SLICE_20I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F0 SLICE_9I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F0 SLICE_14I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_43I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_44I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90I/F1 SLICE_20I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_21I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_67I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_21I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_67I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_75I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_85I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_21I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_57I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_67I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_78I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F1 SLICE_21I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F1 SLICE_26I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F0 SLICE_21I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/F1 SLICE_21I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_67I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_82I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/F0 SLICE_22I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_68I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_69I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F1 SLICE_78I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F1 SLICE_76I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/F1 SLICE_26I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F1 SLICE_29I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F1 SLICE_61I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_29I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_59I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_61I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_59I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_73I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_94I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F0 SLICE_31I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F1 SLICE_32I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/F0 SLICE_32I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_32I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_58I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_64I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_72I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F0 SLICE_32I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F1 SLICE_87I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_33I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F0 SLICE_39I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_39I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_75I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_78I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_85I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/F1 SLICE_57I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/F1 SLICE_41I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/F1 SLICE_41I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_43I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_61I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_62I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F0 SLICE_43I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F0 SLICE_44I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F0 SLICE_51I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F0 SLICE_51I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/F1 SLICE_51I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_52I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_52I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_75I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/F1 SLICE_70I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_76I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_85I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/F1 SLICE_57I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_57I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_85I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/F0 SLICE_59I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F1 SLICE_59I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/F1 SLICE_59I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/F0 SLICE_62I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/F1 SLICE_63I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F1 SLICE_64I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F1 SLICE_68I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F0 SLICE_69I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F0 SLICE_68I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F1 SLICE_69I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F1 SLICE_71I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F1 SLICE_72I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/F1 SLICE_77I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/F1 SLICE_80I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
index e485ff2..a828046 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
@@ -1,24885 +1,24885 @@
-
--- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
--- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
--- Netlist created on Wed Aug 16 04:50:39 2023
--- Netlist written on Wed Aug 16 04:50:41 2023
--- Design is for device LCMXO256C
--- Design is for package TQFP100
--- Design is for performance grade 3
-
--- entity vmuxregsre
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
-
-  end vmuxregsre;
-
-  architecture Structure of vmuxregsre is
-    component FL1P3DX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity vcc
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vcc is
-    port (PWR1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
-
-  end vcc;
-
-  architecture Structure of vcc is
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VHI
-      port map (Z=>PWR1);
-  end Structure;
-
--- entity gnd
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity gnd is
-    port (PWR0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
-
-  end gnd;
-
-  architecture Structure of gnd is
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VLO
-      port map (Z=>PWR0);
-  end Structure;
-
--- entity ccu2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu2B is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
-
-  end ccu2B;
-
-  architecture Structure of ccu2B is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_0
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_0 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_0";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
-
-  end SLICE_0;
-
-  architecture Structure of SLICE_0 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_0: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
-                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20001
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu20001 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
-
-  end ccu20001;
-
-  architecture Structure of ccu20001 is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_1
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_1 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_1";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
-
-  end SLICE_1;
-
-  architecture Structure of SLICE_1 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20001
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_17: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_16: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_16: ccu20001
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
-                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_2 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_2";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
-
-  end SLICE_2;
-
-  architecture Structure of SLICE_2 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_15: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_14: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_14: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
-                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_3
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_3 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_3";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
-
-  end SLICE_3;
-
-  architecture Structure of SLICE_3 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_13: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_12: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_12: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
-                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_4 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_4";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
-
-  end SLICE_4;
-
-  architecture Structure of SLICE_4 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_11: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_10: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_10: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
-                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_5
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_5 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_5";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
-
-  end SLICE_5;
-
-  architecture Structure of SLICE_5 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_9: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_8: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_8: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
-                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_6
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_6 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_6";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
-
-  end SLICE_6;
-
-  architecture Structure of SLICE_6 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_7: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_6: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_6: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
-                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_7
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_7 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_7";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
-
-  end SLICE_7;
-
-  architecture Structure of SLICE_7 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_5: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_4: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_4: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
-                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_8
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_8 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_8";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
-
-  end SLICE_8;
-
-  architecture Structure of SLICE_8 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_2: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
-                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut4 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
-
-  end lut4;
-
-  architecture Structure of lut4 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40002
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40002 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
-
-  end lut40002;
-
-  architecture Structure of lut40002 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00F2")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity inverter
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity inverter is
-    port (I: in Std_logic; Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
-
-  end inverter;
-
-  architecture Structure of inverter is
-    component INV
-      port (A: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    INST1: INV
-      port map (A=>I, Z=>Z);
-  end Structure;
-
--- entity SLICE_9
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_9 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_9";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
-
-  end SLICE_9;
-
-  architecture Structure of SLICE_9 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40002
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    ADSubmitted_r: lut40002
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    ADSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40003
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40003 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
-
-  end lut40003;
-
-  architecture Structure of lut40003 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40004
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40004 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
-
-  end lut40004;
-
-  architecture Structure of lut40004 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_14
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_14 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_14";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
-
-  end SLICE_14;
-
-  architecture Structure of SLICE_14 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40003
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2: lut40003
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1Submitted_RNO: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    C1Submitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40005
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40005 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
-
-  end lut40005;
-
-  architecture Structure of lut40005 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40006
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40006 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
-
-  end lut40006;
-
-  architecture Structure of lut40006 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDDDD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0007
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0007 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
-
-  end vmuxregsre0007;
-
-  architecture Structure of vmuxregsre0007 is
-    component FL1P3IY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3IY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_19
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_19 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_19";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
-
-  end SLICE_19;
-
-  architecture Structure of SLICE_19 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNO_0: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40008
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40008 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
-
-  end lut40008;
-
-  architecture Structure of lut40008 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40009
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40009 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
-
-  end lut40009;
-
-  architecture Structure of lut40009 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAC8C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity selmux2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity selmux2 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
-
-  end selmux2;
-
-  architecture Structure of selmux2 is
-    component MUX21
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    INST1: MUX21
-      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
-  end Structure;
-
--- entity SLICE_20
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_20 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_20";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
-
-  end SLICE_20;
-
-  architecture Structure of SLICE_20 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
-    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40009
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_20_K1: lut40008
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
-                Z=>SLICE_20_SLICE_20_K1_H1);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable_s_GATE: lut40009
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>SLICE_20_CmdEnable_s_GATE_H0);
-    CmdEnable: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    SLICE_20_K0K1MUX: selmux2
-      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40010
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40010 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
-
-  end lut40010;
-
-  architecture Structure of lut40010 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0404")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40011
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40011 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
-
-  end lut40011;
-
-  architecture Structure of lut40011 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0203")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_21
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_21 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_21";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
-
-  end SLICE_21;
-
-  architecture Structure of SLICE_21 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40010
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40011
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_a2_2: lut40010
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_RNO: lut40011
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdLEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40012
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40012 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
-
-  end lut40012;
-
-  architecture Structure of lut40012 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_22
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_22 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_22";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
-
-  end SLICE_22;
-
-  architecture Structure of SLICE_22 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40013
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40013 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
-
-  end lut40013;
-
-  architecture Structure of lut40013 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33AB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40014
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40014 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
-
-  end lut40014;
-
-  architecture Structure of lut40014 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5151")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_26
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_26 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_26";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
-
-  end SLICE_26;
-
-  architecture Structure of SLICE_26 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40014
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_0: lut40013
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_RNO: lut40014
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Cmdn8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40015
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40015 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
-
-  end lut40015;
-
-  architecture Structure of lut40015 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF32")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40016
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40016 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
-
-  end lut40016;
-
-  architecture Structure of lut40016 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA9A9")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_29
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_29 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_29";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
-
-  end SLICE_29;
-
-  architecture Structure of SLICE_29 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i: lut40015
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_0: lut40016
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40017
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40017 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
-
-  end lut40017;
-
-  architecture Structure of lut40017 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7878")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40018
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40018 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
-
-  end lut40018;
-
-  architecture Structure of lut40018 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x6666")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_30
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_30 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_30";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
-
-  end SLICE_30;
-
-  architecture Structure of SLICE_30 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40017
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40018
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_2: lut40017
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_n1_0_x2: lut40018
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    IS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    IS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40019
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40019 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
-
-  end lut40019;
-
-  architecture Structure of lut40019 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFEF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40020
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40020 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
-
-  end lut40020;
-
-  architecture Structure of lut40020 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x6AAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_31
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_31 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_31";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
-
-  end SLICE_31;
-
-  architecture Structure of SLICE_31 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40020
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_RNO: lut40019
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_3: lut40020
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    IS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40021
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40021 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
-
-  end lut40021;
-
-  architecture Structure of lut40021 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4555")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_32
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_32 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_32";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
-
-  end SLICE_32;
-
-  architecture Structure of SLICE_32 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40021
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a0: lut40021
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40022
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40022 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
-
-  end lut40022;
-
-  architecture Structure of lut40022 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFBFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40023
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40023 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
-
-  end lut40023;
-
-  architecture Structure of lut40023 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8B8B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_33
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_33 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_33";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
-
-  end SLICE_33;
-
-  architecture Structure of SLICE_33 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40022
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LED_pad_RNO: lut40022
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    LEDEN_5_i_m2: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    LEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40024
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40024 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
-
-  end lut40024;
-
-  architecture Structure of lut40024 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40025
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40025 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
-
-  end lut40025;
-
-  architecture Structure of lut40025 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xC6C6")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_39
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_39 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_39";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
-
-  end SLICE_39;
-
-  architecture Structure of SLICE_39 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40025
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_0: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RA11_2: lut40025
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RA11: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40026
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40026 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
-
-  end lut40026;
-
-  architecture Structure of lut40026 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x70CF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40027
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40027 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
-
-  end lut40027;
-
-  architecture Structure of lut40027 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCCC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_41
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_41 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_41";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
-
-  end SLICE_41;
-
-  architecture Structure of SLICE_41 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40026
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40027
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_1_0: lut40026
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u: lut40027
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40028
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40028 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
-
-  end lut40028;
-
-  architecture Structure of lut40028 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40029
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40029 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
-
-  end lut40029;
-
-  architecture Structure of lut40029 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFE30")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_42
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_42 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_42";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
-
-  end SLICE_42;
-
-  architecture Structure of SLICE_42 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40029
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_5: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKE_2_0: lut40029
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKE: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40030
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40030 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
-
-  end lut40030;
-
-  architecture Structure of lut40030 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5072")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40031
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40031 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
-
-  end lut40031;
-
-  architecture Structure of lut40031 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAEAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_43
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_43 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_43";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
-
-  end SLICE_43;
-
-  architecture Structure of SLICE_43 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40030
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40031
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_RNO: lut40030
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_RNO: lut40031
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_44
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_44 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_44";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
-
-  end SLICE_44;
-
-  architecture Structure of SLICE_44 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_fast_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RASr: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Ready_fast: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40032
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40032 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
-
-  end lut40032;
-
-  architecture Structure of lut40032 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0202")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_50
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_50 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_50";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
-
-  end SLICE_50;
-
-  architecture Structure of SLICE_50 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_RNO: lut40032
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0_i_o2_1: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    S_1: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40033
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40033 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
-
-  end lut40033;
-
-  architecture Structure of lut40033 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF2F7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40034
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40034 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
-
-  end lut40034;
-
-  architecture Structure of lut40034 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1032")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_51
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_51 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_51";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
-
-  end SLICE_51;
-
-  architecture Structure of SLICE_51 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40033
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_RNO_0: lut40033
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_RNO: lut40034
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40035
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40035 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
-
-  end lut40035;
-
-  architecture Structure of lut40035 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3B33")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40036
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40036 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
-
-  end lut40036;
-
-  architecture Structure of lut40036 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3210")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_52
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_52 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_52";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
-
-  end SLICE_52;
-
-  architecture Structure of SLICE_52 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40036
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    PHI2r3_RNITCN41: lut40035
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_RNO: lut40036
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMSDI: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40037
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40037 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
-
-  end lut40037;
-
-  architecture Structure of lut40037 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xACAC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_55
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_55 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_55";
-
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
-
-  end SLICE_55;
-
-  architecture Structure of SLICE_55 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_4: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
-      F0_out, Q0_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40038
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40038 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
-
-  end lut40038;
-
-  architecture Structure of lut40038 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40039
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40039 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
-
-  end lut40039;
-
-  architecture Structure of lut40039 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2C2C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_56
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_56 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_56";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
-
-  end SLICE_56;
-
-  architecture Structure of SLICE_56 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40039
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_11: lut40038
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_o2: lut40039
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40040
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40040 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
-
-  end lut40040;
-
-  architecture Structure of lut40040 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF7F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_57
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_57 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_57";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
-
-  end SLICE_57;
-
-  architecture Structure of SLICE_57 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG_3_u_0_a3_3: lut40040
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    XOR8MEG: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40041
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40041 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
-
-  end lut40041;
-
-  architecture Structure of lut40041 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0101")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_58
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_58 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_58";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
-
-  end SLICE_58;
-
-  architecture Structure of SLICE_58 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_en_ss0_0_a2_0: lut40041
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    n8MEGEN_5_i_m2: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    n8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40042
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40042 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
-
-  end lut40042;
-
-  architecture Structure of lut40042 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0BFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40043
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40043 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
-
-  end lut40043;
-
-  architecture Structure of lut40043 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2232")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0044
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0044 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0044 : ENTITY IS TRUE;
-
-  end vmuxregsre0044;
-
-  architecture Structure of vmuxregsre0044 is
-    component FL1P3BX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_59
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_59 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_59";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
-
-  end SLICE_59;
-
-  architecture Structure of SLICE_59 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40042
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40043
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_0: lut40042
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCAS_RNO: lut40043
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCAS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40045
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40045 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
-
-  end lut40045;
-
-  architecture Structure of lut40045 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xE6EE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40046
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40046 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
-
-  end lut40046;
-
-  architecture Structure of lut40046 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3233")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_60
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_60 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_60";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
-
-  end SLICE_60;
-
-  architecture Structure of SLICE_60 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40045
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40046
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_RNO_0: lut40045
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCS_RNO: lut40046
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40047
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40047 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
-
-  end lut40047;
-
-  architecture Structure of lut40047 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5400")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40048
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40048 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
-
-  end lut40048;
-
-  architecture Structure of lut40048 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5051")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_61
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_61 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_61";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
-
-  end SLICE_61;
-
-  architecture Structure of SLICE_61 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40047
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40048
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i_0: lut40047
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRRAS_RNO: lut40048
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRRAS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40049
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40049 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
-
-  end lut40049;
-
-  architecture Structure of lut40049 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40050
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40050 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
-
-  end lut40050;
-
-  architecture Structure of lut40050 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF4F7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_62
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_62 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_62";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
-
-  end SLICE_62;
-
-  architecture Structure of SLICE_62 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40050
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0_sqmuxa_1_0_a3: lut40049
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRWE_RNO: lut40050
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRWE: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40051
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40051 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
-
-  end lut40051;
-
-  architecture Structure of lut40051 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40052
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40052 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
-
-  end lut40052;
-
-  architecture Structure of lut40052 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCEC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_63
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_63 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_63";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
-
-  end SLICE_63;
-
-  architecture Structure of SLICE_63 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40051
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_0_0_a3_0: lut40051
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRowColSel_0_0: lut40052
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRowColSel: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40053
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40053 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
-
-  end lut40053;
-
-  architecture Structure of lut40053 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40054
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40054 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
-
-  end lut40054;
-
-  architecture Structure of lut40054 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_64
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_64 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_64";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
-
-  end SLICE_64;
-
-  architecture Structure of SLICE_64 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40054
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS15_0_a2: lut40053
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nUFMCS_s_0_N_5_i: lut40054
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nUFMCS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40055
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40055 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
-
-  end lut40055;
-
-  architecture Structure of lut40055 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40056
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40056 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
-
-  end lut40056;
-
-  architecture Structure of lut40056 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity nRWE_RNO_1_SLICE_65
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWE_RNO_1_SLICE_65 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          OFX0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
-
-  end nRWE_RNO_1_SLICE_65;
-
-  architecture Structure of nRWE_RNO_1_SLICE_65 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40055
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_1_SLICE_65_K1: lut40055
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
-    nRWE_RNO_1_GATE: lut40056
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
-    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
-      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
-                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
-                Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     7 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     8 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40057
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40057 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
-
-  end lut40057;
-
-  architecture Structure of lut40057 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0B0B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_66
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_66 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_66";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
-
-  end SLICE_66;
-
-  architecture Structure of SLICE_66 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS_s_0_N_5_i_N_2L1: lut40057
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_a2_2_2: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40058
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40058 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
-
-  end lut40058;
-
-  architecture Structure of lut40058 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0059
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0059 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0059 : ENTITY IS TRUE;
-
-  end vmuxregsre0059;
-
-  architecture Structure of vmuxregsre0059 is
-    component FL1P3JY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3JY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_67
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_67 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_67";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
-
-  end SLICE_67;
-
-  architecture Structure of SLICE_67 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK_1_sqmuxa_0_a2: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG18_0_a2: lut40005
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_5: vmuxregsre0059
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_4: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
-      Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40060
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40060 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
-
-  end lut40060;
-
-  architecture Structure of lut40060 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEAAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_68
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_68 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_68";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
-
-  end SLICE_68;
-
-  architecture Structure of SLICE_68 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0_1: lut40053
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_14_i_0: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40061
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40061 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
-
-  end lut40061;
-
-  architecture Structure of lut40061 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0100")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_69
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_69 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_69";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
-
-  end SLICE_69;
-
-  architecture Structure of SLICE_69 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_1: lut40061
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_0: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40062
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40062 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
-
-  end lut40062;
-
-  architecture Structure of lut40062 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8888")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_70
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_70 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_70";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
-
-  end SLICE_70;
-
-  architecture Structure of SLICE_70 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_71
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_71 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_71";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
-
-  end SLICE_71;
-
-  architecture Structure of SLICE_71 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_4: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2_0_10: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40063
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40063 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
-
-  end lut40063;
-
-  architecture Structure of lut40063 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFEFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40064
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40064 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
-
-  end lut40064;
-
-  architecture Structure of lut40064 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAAC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_72
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_72 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_72";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
-
-  end SLICE_72;
-
-  architecture Structure of SLICE_72 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0: lut40063
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_m2: lut40064
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_3: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_2: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40065
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40065 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
-
-  end lut40065;
-
-  architecture Structure of lut40065 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFF7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_73
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_73 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_73";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
-
-  end SLICE_73;
-
-  architecture Structure of SLICE_73 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40065
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0: lut40065
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_0_sqmuxa_0_o2: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdUFMCS: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CmdUFMCLK: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_74
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_74 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_74";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
-
-  end SLICE_74;
-
-  architecture Structure of SLICE_74 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    InitReady3_0_a2_3: lut40062
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady3_0_a2: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdUFMSDI: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40066
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40066 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
-
-  end lut40066;
-
-  architecture Structure of lut40066 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFDFD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_75
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_75 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_75";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
-
-  end SLICE_75;
-
-  architecture Structure of SLICE_75 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40066
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_o2_0: lut40066
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_4_u_i_a2_0: lut40041
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    CASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CASr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40067
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40067 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
-
-  end lut40067;
-
-  architecture Structure of lut40067 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0002")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_76
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_76 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_76";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
-
-  end SLICE_76;
-
-  architecture Structure of SLICE_76 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40067
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_4: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_4_0: lut40067
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40068
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40068 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
-
-  end lut40068;
-
-  architecture Structure of lut40068 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4444")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_77
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_77 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_77";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
-
-  end SLICE_77;
-
-  architecture Structure of SLICE_77 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40068
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_1: lut40068
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_5: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40069
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40069 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
-
-  end lut40069;
-
-  architecture Structure of lut40069 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7777")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_78
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_78 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_78";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
-
-  end SLICE_78;
-
-  architecture Structure of SLICE_78 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_o2: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable17_0_a2_4: lut40058
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CBR_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CBR: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40070
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40070 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
-
-  end lut40070;
-
-  architecture Structure of lut40070 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_79
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_79 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_79";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
-
-  end SLICE_79;
-
-  architecture Structure of SLICE_79 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40070
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_2: lut40070
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_RNO_0: lut40038
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40071
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40071 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
-
-  end lut40071;
-
-  architecture Structure of lut40071 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4101")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_80
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_80 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_80";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
-
-  end SLICE_80;
-
-  architecture Structure of SLICE_80 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40071
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_RNO_1: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRCAS_RNO_0: lut40071
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_9: vmuxregsre0059
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_8: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40072
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40072 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
-
-  end lut40072;
-
-  architecture Structure of lut40072 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_81
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_81 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_81";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
-
-  end SLICE_81;
-
-  architecture Structure of SLICE_81 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0_3: lut40072
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_5: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    FWEr_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    FWEr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40073
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40073 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
-
-  end lut40073;
-
-  architecture Structure of lut40073 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40074
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40074 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
-
-  end lut40074;
-
-  architecture Structure of lut40074 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_82
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_82 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_82";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
-
-  end SLICE_82;
-
-  architecture Structure of SLICE_82 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40073
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40074
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2: lut40073
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_1_sqmuxa_0_a2: lut40074
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr3: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40075
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40075 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
-
-  end lut40075;
-
-  architecture Structure of lut40075 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7F7F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_83
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_83 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_83";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
-
-  end SLICE_83;
-
-  architecture Structure of SLICE_83 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40075
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_o2: lut40063
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_0_sqmuxa_0_o2: lut40075
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RBA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RBA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_84
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_84 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_84";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
-
-  end SLICE_84;
-
-  architecture Structure of SLICE_84 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a2_4_2: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_a2_6: lut40061
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40076
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40076 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
-
-  end lut40076;
-
-  architecture Structure of lut40076 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0040")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_85
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_85 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_85";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
-
-  end SLICE_85;
-
-  architecture Structure of SLICE_85 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40076
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2_3: lut40076
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_Din_4: lut40053
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_86
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_86 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_86";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
-
-  end SLICE_86;
-
-  architecture Structure of SLICE_86 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQML: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_9: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40077
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40077 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
-
-  end lut40077;
-
-  architecture Structure of lut40077 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3232")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_87
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_87 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_87";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
-
-  end SLICE_87;
-
-  architecture Structure of SLICE_87 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_RNO_0: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_a2_8: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40078
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40078 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
-
-  end lut40078;
-
-  architecture Structure of lut40078 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0808")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_88
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_88 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_88";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
-
-  end SLICE_88;
-
-  architecture Structure of SLICE_88 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40078
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_3: lut40078
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nCCAS_pad_RNI01SJ: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_7: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_6: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, 
-      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40079
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40079 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
-
-  end lut40079;
-
-  architecture Structure of lut40079 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBBBB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_89
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_89 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_89";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
-
-  end SLICE_89;
-
-  architecture Structure of SLICE_89 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40079
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQMH: lut40079
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_8: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40080
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40080 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
-
-  end lut40080;
-
-  architecture Structure of lut40080 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA8A8")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_90
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_90 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_90";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
-
-  end SLICE_90;
-
-  architecture Structure of SLICE_90 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40080
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_CMDWR: lut40080
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_0: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_91
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_91 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_91";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
-
-  end SLICE_91;
-
-  architecture Structure of SLICE_91 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_7: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_1: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_92
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_92 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_92";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
-
-  end SLICE_92;
-
-  architecture Structure of SLICE_92 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_6: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_2: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_93
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_93 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_93";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
-
-  end SLICE_93;
-
-  architecture Structure of SLICE_93 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_5: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_3: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40081
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40081 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
-
-  end lut40081;
-
-  architecture Structure of lut40081 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1111")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_94
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_94 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_94";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
-
-  end SLICE_94;
-
-  architecture Structure of SLICE_94 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40081
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN_8_u_0_a2_1_s: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RA10: vmuxregsre0059
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf is
-    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-          PAD: out Std_logic; PADI: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
-
-  end mjiobuf;
-
-  architecture Structure of mjiobuf is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-    component OBW
-      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PADI, O=>Z);
-    INST2: OBW
-      port map (I=>I, T=>T, O=>PAD);
-  end Structure;
-
--- entity RD_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD0 	: VitalDelayType := 0 ns;
-      tpw_RD0_posedge	: VitalDelayType := 0 ns;
-      tpw_RD0_negedge	: VitalDelayType := 0 ns;
-      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD0: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
-
-  end RD_0_B;
-
-  architecture Structure of RD_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD0_ipd 	: std_logic := 'X';
-    signal RD0_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_0: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
-                PADI=>RD0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD0_zd         	: std_logic := 'X';
-    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD0_RD0          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD0_ipd,
-        TestSignalName => "RD0",
-        Period => tperiod_RD0,
-        PulseWidthHigh => tpw_RD0_posedge,
-        PulseWidthLow => tpw_RD0_negedge,
-        PeriodData => periodcheckinfo_RD0,
-        Violation => tviol_RD0_RD0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD0_zd 	:= RD0_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
-                           PathDelay => tpd_RD0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD0,
-                           PathCondition => TRUE)),
-      GlitchData => RD0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0082
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0082 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0082 : ENTITY IS TRUE;
-
-  end mjiobuf0082;
-
-  architecture Structure of mjiobuf0082 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity Dout_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
-
-  end Dout_0_B;
-
-  architecture Structure of Dout_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout0_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_0: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
-    VARIABLE Dout0_zd         	: std_logic := 'X';
-    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout0_zd 	:= Dout0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout0,
-                           PathCondition => TRUE)),
-      GlitchData => Dout0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0083
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0083 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0083 : ENTITY IS TRUE;
-
-  end mjiobuf0083;
-
-  architecture Structure of mjiobuf0083 is
-    component IBPD
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPD
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity PHI2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity PHI2B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2B";
-
-      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_PHI2S 	: VitalDelayType := 0 ns;
-      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
-      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; PHI2S: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
-
-  end PHI2B;
-
-  architecture Structure of PHI2B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PHI2S_ipd 	: std_logic := 'X';
-
-    component mjiobuf0083
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    PHI2_pad: mjiobuf0083
-      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
-    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => PHI2S_ipd,
-        TestSignalName => "PHI2S",
-        Period => tperiod_PHI2S,
-        PulseWidthHigh => tpw_PHI2S_posedge,
-        PulseWidthLow => tpw_PHI2S_negedge,
-        PeriodData => periodcheckinfo_PHI2S,
-        Violation => tviol_PHI2S_PHI2S,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
-                           PathDelay => tpd_PHI2S_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0084
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0084 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0084 : ENTITY IS TRUE;
-
-  end mjiobuf0084;
-
-  architecture Structure of mjiobuf0084 is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity UFMSDOB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDOB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDOB";
-
-      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
-
-  end UFMSDOB;
-
-  architecture Structure of UFMSDOB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal UFMSDOS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    UFMSDO_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
-    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => UFMSDOS_ipd,
-        TestSignalName => "UFMSDOS",
-        Period => tperiod_UFMSDOS,
-        PulseWidthHigh => tpw_UFMSDOS_posedge,
-        PulseWidthLow => tpw_UFMSDOS_negedge,
-        PeriodData => periodcheckinfo_UFMSDOS,
-        Violation => tviol_UFMSDOS_UFMSDOS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
-                           PathDelay => tpd_UFMSDOS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0085
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0085 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0085 : ENTITY IS TRUE;
-
-  end mjiobuf0085;
-
-  architecture Structure of mjiobuf0085 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity UFMSDIB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDIB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDIB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
-
-  end UFMSDIB;
-
-  architecture Structure of UFMSDIB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMSDIS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMSDI_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
-    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
-    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMSDIS_zd 	:= UFMSDIS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMSDIS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMSDIS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLKB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
-
-  end UFMCLKB;
-
-  architecture Structure of UFMCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMCLKS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMCLK_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
-    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
-    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMCLKS_zd 	:= UFMCLKS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMCLKS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMCLKS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nUFMCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nUFMCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
-
-  end nUFMCSB;
-
-  architecture Structure of nUFMCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nUFMCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nUFMCS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
-    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
-    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nUFMCSS_zd 	:= nUFMCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nUFMCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nUFMCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMLB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMLB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMLB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
-
-  end RDQMLB;
-
-  architecture Structure of RDQMLB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMLS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQML_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
-    VARIABLE RDQMLS_zd         	: std_logic := 'X';
-    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMLS_zd 	:= RDQMLS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMLS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMLS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMHB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMHB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMHB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
-
-  end RDQMHB;
-
-  architecture Structure of RDQMHB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMHS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQMH_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
-    VARIABLE RDQMHS_zd         	: std_logic := 'X';
-    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMHS_zd 	:= RDQMHS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMHS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMHS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
-
-  end nRCASB;
-
-  architecture Structure of nRCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCASS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCAS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
-    VARIABLE nRCASS_zd         	: std_logic := 'X';
-    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCASS_zd 	:= nRCASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRRASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
-
-  end nRRASB;
-
-  architecture Structure of nRRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRRASS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRRAS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
-    VARIABLE nRRASS_zd         	: std_logic := 'X';
-    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRRASS_zd 	:= nRRASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRRASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRRASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRWES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
-
-  end nRWEB;
-
-  architecture Structure of nRWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRWES_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRWE_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRWES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
-    VARIABLE nRWES_zd         	: std_logic := 'X';
-    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRWES_zd 	:= nRWES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRWES,
-                           PathCondition => TRUE)),
-      GlitchData => nRWES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCKEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RCKES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
-
-  end RCKEB;
-
-  architecture Structure of RCKEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RCKES_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RCKE_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RCKES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
-    VARIABLE RCKES_zd         	: std_logic := 'X';
-    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RCKES_zd 	:= RCKES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RCKES,
-                           PathCondition => TRUE)),
-      GlitchData => RCKES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCLKB";
-
-      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RCLKS 	: VitalDelayType := 0 ns;
-      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
-      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; RCLKS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
-
-  end RCLKB;
-
-  architecture Structure of RCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal RCLKS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    RCLK_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
-    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RCLKS_ipd,
-        TestSignalName => "RCLKS",
-        Period => tperiod_RCLKS,
-        PulseWidthHigh => tpw_RCLKS_posedge,
-        PulseWidthLow => tpw_RCLKS_negedge,
-        PeriodData => periodcheckinfo_RCLKS,
-        Violation => tviol_RCLKS_RCLKS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
-                           PathDelay => tpd_RCLKS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
-
-  end nRCSB;
-
-  architecture Structure of nRCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
-    VARIABLE nRCSS_zd         	: std_logic := 'X';
-    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCSS_zd 	:= nRCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD7 	: VitalDelayType := 0 ns;
-      tpw_RD7_posedge	: VitalDelayType := 0 ns;
-      tpw_RD7_negedge	: VitalDelayType := 0 ns;
-      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD7: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
-
-  end RD_7_B;
-
-  architecture Structure of RD_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD7_ipd 	: std_logic := 'X';
-    signal RD7_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_7: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
-                PADI=>RD7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD7_zd         	: std_logic := 'X';
-    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD7_RD7          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD7_ipd,
-        TestSignalName => "RD7",
-        Period => tperiod_RD7,
-        PulseWidthHigh => tpw_RD7_posedge,
-        PulseWidthLow => tpw_RD7_negedge,
-        PeriodData => periodcheckinfo_RD7,
-        Violation => tviol_RD7_RD7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD7_zd 	:= RD7_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
-                           PathDelay => tpd_RD7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD7,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD7,
-                           PathCondition => TRUE)),
-      GlitchData => RD7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD6 	: VitalDelayType := 0 ns;
-      tpw_RD6_posedge	: VitalDelayType := 0 ns;
-      tpw_RD6_negedge	: VitalDelayType := 0 ns;
-      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD6: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
-
-  end RD_6_B;
-
-  architecture Structure of RD_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD6_ipd 	: std_logic := 'X';
-    signal RD6_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_6: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
-                PADI=>RD6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD6_zd         	: std_logic := 'X';
-    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD6_RD6          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD6_ipd,
-        TestSignalName => "RD6",
-        Period => tperiod_RD6,
-        PulseWidthHigh => tpw_RD6_posedge,
-        PulseWidthLow => tpw_RD6_negedge,
-        PeriodData => periodcheckinfo_RD6,
-        Violation => tviol_RD6_RD6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD6_zd 	:= RD6_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
-                           PathDelay => tpd_RD6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD6,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD6,
-                           PathCondition => TRUE)),
-      GlitchData => RD6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD5 	: VitalDelayType := 0 ns;
-      tpw_RD5_posedge	: VitalDelayType := 0 ns;
-      tpw_RD5_negedge	: VitalDelayType := 0 ns;
-      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD5: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
-
-  end RD_5_B;
-
-  architecture Structure of RD_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD5_ipd 	: std_logic := 'X';
-    signal RD5_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_5: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
-                PADI=>RD5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD5_zd         	: std_logic := 'X';
-    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD5_RD5          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD5_ipd,
-        TestSignalName => "RD5",
-        Period => tperiod_RD5,
-        PulseWidthHigh => tpw_RD5_posedge,
-        PulseWidthLow => tpw_RD5_negedge,
-        PeriodData => periodcheckinfo_RD5,
-        Violation => tviol_RD5_RD5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD5_zd 	:= RD5_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
-                           PathDelay => tpd_RD5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD5,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD5,
-                           PathCondition => TRUE)),
-      GlitchData => RD5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD4 	: VitalDelayType := 0 ns;
-      tpw_RD4_posedge	: VitalDelayType := 0 ns;
-      tpw_RD4_negedge	: VitalDelayType := 0 ns;
-      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD4: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
-
-  end RD_4_B;
-
-  architecture Structure of RD_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD4_ipd 	: std_logic := 'X';
-    signal RD4_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_4: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
-                PADI=>RD4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD4_zd         	: std_logic := 'X';
-    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD4_RD4          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD4_ipd,
-        TestSignalName => "RD4",
-        Period => tperiod_RD4,
-        PulseWidthHigh => tpw_RD4_posedge,
-        PulseWidthLow => tpw_RD4_negedge,
-        PeriodData => periodcheckinfo_RD4,
-        Violation => tviol_RD4_RD4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD4_zd 	:= RD4_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
-                           PathDelay => tpd_RD4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD4,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD4,
-                           PathCondition => TRUE)),
-      GlitchData => RD4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD3 	: VitalDelayType := 0 ns;
-      tpw_RD3_posedge	: VitalDelayType := 0 ns;
-      tpw_RD3_negedge	: VitalDelayType := 0 ns;
-      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD3: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
-
-  end RD_3_B;
-
-  architecture Structure of RD_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD3_ipd 	: std_logic := 'X';
-    signal RD3_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_3: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
-                PADI=>RD3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD3_zd         	: std_logic := 'X';
-    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD3_RD3          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD3_ipd,
-        TestSignalName => "RD3",
-        Period => tperiod_RD3,
-        PulseWidthHigh => tpw_RD3_posedge,
-        PulseWidthLow => tpw_RD3_negedge,
-        PeriodData => periodcheckinfo_RD3,
-        Violation => tviol_RD3_RD3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD3_zd 	:= RD3_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
-                           PathDelay => tpd_RD3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD3,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD3,
-                           PathCondition => TRUE)),
-      GlitchData => RD3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD2 	: VitalDelayType := 0 ns;
-      tpw_RD2_posedge	: VitalDelayType := 0 ns;
-      tpw_RD2_negedge	: VitalDelayType := 0 ns;
-      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD2: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
-
-  end RD_2_B;
-
-  architecture Structure of RD_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD2_ipd 	: std_logic := 'X';
-    signal RD2_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_2: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
-                PADI=>RD2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD2_zd         	: std_logic := 'X';
-    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD2_RD2          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD2_ipd,
-        TestSignalName => "RD2",
-        Period => tperiod_RD2,
-        PulseWidthHigh => tpw_RD2_posedge,
-        PulseWidthLow => tpw_RD2_negedge,
-        PeriodData => periodcheckinfo_RD2,
-        Violation => tviol_RD2_RD2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD2_zd 	:= RD2_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
-                           PathDelay => tpd_RD2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD2,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD2,
-                           PathCondition => TRUE)),
-      GlitchData => RD2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD1 	: VitalDelayType := 0 ns;
-      tpw_RD1_posedge	: VitalDelayType := 0 ns;
-      tpw_RD1_negedge	: VitalDelayType := 0 ns;
-      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD1: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
-
-  end RD_1_B;
-
-  architecture Structure of RD_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD1_ipd 	: std_logic := 'X';
-    signal RD1_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_1: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
-                PADI=>RD1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD1_zd         	: std_logic := 'X';
-    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD1_RD1          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD1_ipd,
-        TestSignalName => "RD1",
-        Period => tperiod_RD1,
-        PulseWidthHigh => tpw_RD1_posedge,
-        PulseWidthLow => tpw_RD1_negedge,
-        PeriodData => periodcheckinfo_RD1,
-        Violation => tviol_RD1_RD1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD1_zd 	:= RD1_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
-                           PathDelay => tpd_RD1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD1,
-                           PathCondition => TRUE)),
-      GlitchData => RD1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_11_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA11: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
-
-  end RA_11_B;
-
-  architecture Structure of RA_11_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA11_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_11: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA11_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
-    VARIABLE RA11_zd         	: std_logic := 'X';
-    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA11_zd 	:= RA11_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA11,
-                           PathCondition => TRUE)),
-      GlitchData => RA11_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_10_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_10_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA10: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
-
-  end RA_10_B;
-
-  architecture Structure of RA_10_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA10_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_10: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA10_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
-    VARIABLE RA10_zd         	: std_logic := 'X';
-    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA10_zd 	:= RA10_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA10,
-                           PathCondition => TRUE)),
-      GlitchData => RA10_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_9_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA9: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
-
-  end RA_9_B;
-
-  architecture Structure of RA_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA9_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_9: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA9_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
-    VARIABLE RA9_zd         	: std_logic := 'X';
-    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA9_zd 	:= RA9_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA9,
-                           PathCondition => TRUE)),
-      GlitchData => RA9_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_8_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA8: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
-
-  end RA_8_B;
-
-  architecture Structure of RA_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA8_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_8: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA8_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
-    VARIABLE RA8_zd         	: std_logic := 'X';
-    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA8_zd 	:= RA8_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA8,
-                           PathCondition => TRUE)),
-      GlitchData => RA8_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
-
-  end RA_7_B;
-
-  architecture Structure of RA_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA7_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_7: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
-    VARIABLE RA7_zd         	: std_logic := 'X';
-    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA7_zd 	:= RA7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA7,
-                           PathCondition => TRUE)),
-      GlitchData => RA7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
-
-  end RA_6_B;
-
-  architecture Structure of RA_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA6_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_6: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
-    VARIABLE RA6_zd         	: std_logic := 'X';
-    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA6_zd 	:= RA6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA6,
-                           PathCondition => TRUE)),
-      GlitchData => RA6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
-
-  end RA_5_B;
-
-  architecture Structure of RA_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA5_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_5: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
-    VARIABLE RA5_zd         	: std_logic := 'X';
-    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA5_zd 	:= RA5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA5,
-                           PathCondition => TRUE)),
-      GlitchData => RA5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
-
-  end RA_4_B;
-
-  architecture Structure of RA_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA4_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_4: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
-    VARIABLE RA4_zd         	: std_logic := 'X';
-    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA4_zd 	:= RA4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA4,
-                           PathCondition => TRUE)),
-      GlitchData => RA4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
-
-  end RA_3_B;
-
-  architecture Structure of RA_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA3_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_3: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
-    VARIABLE RA3_zd         	: std_logic := 'X';
-    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA3_zd 	:= RA3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA3,
-                           PathCondition => TRUE)),
-      GlitchData => RA3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
-
-  end RA_2_B;
-
-  architecture Structure of RA_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA2_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_2: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
-    VARIABLE RA2_zd         	: std_logic := 'X';
-    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA2_zd 	:= RA2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA2,
-                           PathCondition => TRUE)),
-      GlitchData => RA2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
-
-  end RA_1_B;
-
-  architecture Structure of RA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA1_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_1: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
-    VARIABLE RA1_zd         	: std_logic := 'X';
-    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA1_zd 	:= RA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA1,
-                           PathCondition => TRUE)),
-      GlitchData => RA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
-
-  end RA_0_B;
-
-  architecture Structure of RA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA0_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_0: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
-    VARIABLE RA0_zd         	: std_logic := 'X';
-    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA0_zd 	:= RA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA0,
-                           PathCondition => TRUE)),
-      GlitchData => RA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
-
-  end RBA_1_B;
-
-  architecture Structure of RBA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA1_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_1: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RBA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
-    VARIABLE RBA1_zd         	: std_logic := 'X';
-    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA1_zd 	:= RBA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA1,
-                           PathCondition => TRUE)),
-      GlitchData => RBA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
-
-  end RBA_0_B;
-
-  architecture Structure of RBA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA0_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_0: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RBA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
-    VARIABLE RBA0_zd         	: std_logic := 'X';
-    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA0_zd 	:= RBA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA0,
-                           PathCondition => TRUE)),
-      GlitchData => RBA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0086
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0086 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0086 : ENTITY IS TRUE;
-
-  end mjiobuf0086;
-
-  architecture Structure of mjiobuf0086 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity LEDB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity LEDB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "LEDB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; LEDS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
-
-  end LEDB;
-
-  architecture Structure of LEDB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal LEDS_out 	: std_logic := 'X';
-
-    component mjiobuf0086
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    LED_pad: mjiobuf0086
-      port map (I=>PADDO_ipd, PAD=>LEDS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
-    VARIABLE LEDS_zd         	: std_logic := 'X';
-    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    LEDS_zd 	:= LEDS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_LEDS,
-                           PathCondition => TRUE)),
-      GlitchData => LEDS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nFWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nFWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nFWEB";
-
-      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nFWES 	: VitalDelayType := 0 ns;
-      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
-      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nFWES: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
-
-  end nFWEB;
-
-  architecture Structure of nFWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nFWES_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nFWE_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
-    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nFWES_ipd,
-        TestSignalName => "nFWES",
-        Period => tperiod_nFWES,
-        PulseWidthHigh => tpw_nFWES_posedge,
-        PulseWidthLow => tpw_nFWES_negedge,
-        PeriodData => periodcheckinfo_nFWES,
-        Violation => tviol_nFWES_nFWES,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
-                           PathDelay => tpd_nFWES_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0087
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0087 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0087 : ENTITY IS TRUE;
-
-  end mjiobuf0087;
-
-  architecture Structure of mjiobuf0087 is
-    component IBPU
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPU
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity nCRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCRASB";
-
-      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCRASS 	: VitalDelayType := 0 ns;
-      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCRASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
-
-  end nCRASB;
-
-  architecture Structure of nCRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCRASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0087
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCRAS_pad: mjiobuf0087
-      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCRASS_ipd,
-        TestSignalName => "nCRASS",
-        Period => tperiod_nCRASS,
-        PulseWidthHigh => tpw_nCRASS_posedge,
-        PulseWidthLow => tpw_nCRASS_negedge,
-        PeriodData => periodcheckinfo_nCRASS,
-        Violation => tviol_nCRASS_nCRASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
-                           PathDelay => tpd_nCRASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCCASB";
-
-      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCCASS 	: VitalDelayType := 0 ns;
-      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCCASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
-
-  end nCCASB;
-
-  architecture Structure of nCCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCCASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0087
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCCAS_pad: mjiobuf0087
-      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCCASS_ipd,
-        TestSignalName => "nCCASS",
-        Period => tperiod_nCCASS,
-        PulseWidthHigh => tpw_nCCASS_posedge,
-        PulseWidthLow => tpw_nCCASS_negedge,
-        PeriodData => periodcheckinfo_nCCASS,
-        Violation => tviol_nCCASS_nCCASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
-                           PathDelay => tpd_nCCASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
-
-  end Dout_7_B;
-
-  architecture Structure of Dout_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout7_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_7: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
-    VARIABLE Dout7_zd         	: std_logic := 'X';
-    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout7_zd 	:= Dout7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout7,
-                           PathCondition => TRUE)),
-      GlitchData => Dout7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
-
-  end Dout_6_B;
-
-  architecture Structure of Dout_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout6_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_6: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
-    VARIABLE Dout6_zd         	: std_logic := 'X';
-    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout6_zd 	:= Dout6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout6,
-                           PathCondition => TRUE)),
-      GlitchData => Dout6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
-
-  end Dout_5_B;
-
-  architecture Structure of Dout_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout5_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_5: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
-    VARIABLE Dout5_zd         	: std_logic := 'X';
-    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout5_zd 	:= Dout5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout5,
-                           PathCondition => TRUE)),
-      GlitchData => Dout5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
-
-  end Dout_4_B;
-
-  architecture Structure of Dout_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout4_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_4: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
-    VARIABLE Dout4_zd         	: std_logic := 'X';
-    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout4_zd 	:= Dout4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout4,
-                           PathCondition => TRUE)),
-      GlitchData => Dout4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
-
-  end Dout_3_B;
-
-  architecture Structure of Dout_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout3_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_3: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
-    VARIABLE Dout3_zd         	: std_logic := 'X';
-    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout3_zd 	:= Dout3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout3,
-                           PathCondition => TRUE)),
-      GlitchData => Dout3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
-
-  end Dout_2_B;
-
-  architecture Structure of Dout_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout2_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_2: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
-    VARIABLE Dout2_zd         	: std_logic := 'X';
-    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout2_zd 	:= Dout2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout2,
-                           PathCondition => TRUE)),
-      GlitchData => Dout2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
-
-  end Dout_1_B;
-
-  architecture Structure of Dout_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout1_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_1: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
-    VARIABLE Dout1_zd         	: std_logic := 'X';
-    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout1_zd 	:= Dout1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout1,
-                           PathCondition => TRUE)),
-      GlitchData => Dout1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_B";
-
-      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din7 	: VitalDelayType := 0 ns;
-      tpw_Din7_posedge	: VitalDelayType := 0 ns;
-      tpw_Din7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
-
-  end Din_7_B;
-
-  architecture Structure of Din_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_7: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din7_Din7          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din7_ipd,
-        TestSignalName => "Din7",
-        Period => tperiod_Din7,
-        PulseWidthHigh => tpw_Din7_posedge,
-        PulseWidthLow => tpw_Din7_negedge,
-        PeriodData => periodcheckinfo_Din7,
-        Violation => tviol_Din7_Din7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
-                           PathDelay => tpd_Din7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_B";
-
-      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din6 	: VitalDelayType := 0 ns;
-      tpw_Din6_posedge	: VitalDelayType := 0 ns;
-      tpw_Din6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
-
-  end Din_6_B;
-
-  architecture Structure of Din_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_6: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din6_Din6          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din6_ipd,
-        TestSignalName => "Din6",
-        Period => tperiod_Din6,
-        PulseWidthHigh => tpw_Din6_posedge,
-        PulseWidthLow => tpw_Din6_negedge,
-        PeriodData => periodcheckinfo_Din6,
-        Violation => tviol_Din6_Din6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
-                           PathDelay => tpd_Din6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_B";
-
-      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din5 	: VitalDelayType := 0 ns;
-      tpw_Din5_posedge	: VitalDelayType := 0 ns;
-      tpw_Din5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
-
-  end Din_5_B;
-
-  architecture Structure of Din_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_5: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din5_Din5          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din5_ipd,
-        TestSignalName => "Din5",
-        Period => tperiod_Din5,
-        PulseWidthHigh => tpw_Din5_posedge,
-        PulseWidthLow => tpw_Din5_negedge,
-        PeriodData => periodcheckinfo_Din5,
-        Violation => tviol_Din5_Din5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
-                           PathDelay => tpd_Din5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_B";
-
-      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din4 	: VitalDelayType := 0 ns;
-      tpw_Din4_posedge	: VitalDelayType := 0 ns;
-      tpw_Din4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
-
-  end Din_4_B;
-
-  architecture Structure of Din_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_4: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din4_Din4          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din4_ipd,
-        TestSignalName => "Din4",
-        Period => tperiod_Din4,
-        PulseWidthHigh => tpw_Din4_posedge,
-        PulseWidthLow => tpw_Din4_negedge,
-        PeriodData => periodcheckinfo_Din4,
-        Violation => tviol_Din4_Din4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
-                           PathDelay => tpd_Din4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_B";
-
-      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din3 	: VitalDelayType := 0 ns;
-      tpw_Din3_posedge	: VitalDelayType := 0 ns;
-      tpw_Din3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
-
-  end Din_3_B;
-
-  architecture Structure of Din_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_3: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din3_Din3          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din3_ipd,
-        TestSignalName => "Din3",
-        Period => tperiod_Din3,
-        PulseWidthHigh => tpw_Din3_posedge,
-        PulseWidthLow => tpw_Din3_negedge,
-        PeriodData => periodcheckinfo_Din3,
-        Violation => tviol_Din3_Din3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
-                           PathDelay => tpd_Din3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_B";
-
-      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din2 	: VitalDelayType := 0 ns;
-      tpw_Din2_posedge	: VitalDelayType := 0 ns;
-      tpw_Din2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
-
-  end Din_2_B;
-
-  architecture Structure of Din_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_2: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din2_Din2          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din2_ipd,
-        TestSignalName => "Din2",
-        Period => tperiod_Din2,
-        PulseWidthHigh => tpw_Din2_posedge,
-        PulseWidthLow => tpw_Din2_negedge,
-        PeriodData => periodcheckinfo_Din2,
-        Violation => tviol_Din2_Din2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
-                           PathDelay => tpd_Din2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_B";
-
-      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din1 	: VitalDelayType := 0 ns;
-      tpw_Din1_posedge	: VitalDelayType := 0 ns;
-      tpw_Din1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
-
-  end Din_1_B;
-
-  architecture Structure of Din_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din1_Din1          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din1_ipd,
-        TestSignalName => "Din1",
-        Period => tperiod_Din1,
-        PulseWidthHigh => tpw_Din1_posedge,
-        PulseWidthLow => tpw_Din1_negedge,
-        PeriodData => periodcheckinfo_Din1,
-        Violation => tviol_Din1_Din1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
-                           PathDelay => tpd_Din1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_B";
-
-      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din0 	: VitalDelayType := 0 ns;
-      tpw_Din0_posedge	: VitalDelayType := 0 ns;
-      tpw_Din0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
-
-  end Din_0_B;
-
-  architecture Structure of Din_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din0_Din0          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din0_ipd,
-        TestSignalName => "Din0",
-        Period => tperiod_Din0,
-        PulseWidthHigh => tpw_Din0_posedge,
-        PulseWidthLow => tpw_Din0_negedge,
-        PeriodData => periodcheckinfo_Din0,
-        Violation => tviol_Din0_Din0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
-                           PathDelay => tpd_Din0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_1_B";
-
-      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW1 	: VitalDelayType := 0 ns;
-      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
-
-  end CROW_1_B;
-
-  architecture Structure of CROW_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW1_ipd,
-        TestSignalName => "CROW1",
-        Period => tperiod_CROW1,
-        PulseWidthHigh => tpw_CROW1_posedge,
-        PulseWidthLow => tpw_CROW1_negedge,
-        PeriodData => periodcheckinfo_CROW1,
-        Violation => tviol_CROW1_CROW1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
-                           PathDelay => tpd_CROW1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_0_B";
-
-      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW0 	: VitalDelayType := 0 ns;
-      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
-
-  end CROW_0_B;
-
-  architecture Structure of CROW_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW0_ipd,
-        TestSignalName => "CROW0",
-        Period => tperiod_CROW0,
-        PulseWidthHigh => tpw_CROW0_posedge,
-        PulseWidthLow => tpw_CROW0_negedge,
-        PeriodData => periodcheckinfo_CROW0,
-        Violation => tviol_CROW0_CROW0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
-                           PathDelay => tpd_CROW0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_9_B";
-
-      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin9 	: VitalDelayType := 0 ns;
-      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin9: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
-
-  end MAin_9_B;
-
-  architecture Structure of MAin_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin9_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_9: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin9_ipd,
-        TestSignalName => "MAin9",
-        Period => tperiod_MAin9,
-        PulseWidthHigh => tpw_MAin9_posedge,
-        PulseWidthLow => tpw_MAin9_negedge,
-        PeriodData => periodcheckinfo_MAin9,
-        Violation => tviol_MAin9_MAin9,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
-                           PathDelay => tpd_MAin9_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_8_B";
-
-      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin8 	: VitalDelayType := 0 ns;
-      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin8: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
-
-  end MAin_8_B;
-
-  architecture Structure of MAin_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin8_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_8: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin8_ipd,
-        TestSignalName => "MAin8",
-        Period => tperiod_MAin8,
-        PulseWidthHigh => tpw_MAin8_posedge,
-        PulseWidthLow => tpw_MAin8_negedge,
-        PeriodData => periodcheckinfo_MAin8,
-        Violation => tviol_MAin8_MAin8,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
-                           PathDelay => tpd_MAin8_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_7_B";
-
-      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin7 	: VitalDelayType := 0 ns;
-      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
-
-  end MAin_7_B;
-
-  architecture Structure of MAin_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_7: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin7_ipd,
-        TestSignalName => "MAin7",
-        Period => tperiod_MAin7,
-        PulseWidthHigh => tpw_MAin7_posedge,
-        PulseWidthLow => tpw_MAin7_negedge,
-        PeriodData => periodcheckinfo_MAin7,
-        Violation => tviol_MAin7_MAin7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
-                           PathDelay => tpd_MAin7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_6_B";
-
-      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin6 	: VitalDelayType := 0 ns;
-      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
-
-  end MAin_6_B;
-
-  architecture Structure of MAin_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_6: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin6_ipd,
-        TestSignalName => "MAin6",
-        Period => tperiod_MAin6,
-        PulseWidthHigh => tpw_MAin6_posedge,
-        PulseWidthLow => tpw_MAin6_negedge,
-        PeriodData => periodcheckinfo_MAin6,
-        Violation => tviol_MAin6_MAin6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
-                           PathDelay => tpd_MAin6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_5_B";
-
-      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin5 	: VitalDelayType := 0 ns;
-      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
-
-  end MAin_5_B;
-
-  architecture Structure of MAin_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_5: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin5_ipd,
-        TestSignalName => "MAin5",
-        Period => tperiod_MAin5,
-        PulseWidthHigh => tpw_MAin5_posedge,
-        PulseWidthLow => tpw_MAin5_negedge,
-        PeriodData => periodcheckinfo_MAin5,
-        Violation => tviol_MAin5_MAin5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
-                           PathDelay => tpd_MAin5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_4_B";
-
-      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin4 	: VitalDelayType := 0 ns;
-      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
-
-  end MAin_4_B;
-
-  architecture Structure of MAin_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_4: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin4_ipd,
-        TestSignalName => "MAin4",
-        Period => tperiod_MAin4,
-        PulseWidthHigh => tpw_MAin4_posedge,
-        PulseWidthLow => tpw_MAin4_negedge,
-        PeriodData => periodcheckinfo_MAin4,
-        Violation => tviol_MAin4_MAin4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
-                           PathDelay => tpd_MAin4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_3_B";
-
-      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin3 	: VitalDelayType := 0 ns;
-      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
-
-  end MAin_3_B;
-
-  architecture Structure of MAin_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_3: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin3_ipd,
-        TestSignalName => "MAin3",
-        Period => tperiod_MAin3,
-        PulseWidthHigh => tpw_MAin3_posedge,
-        PulseWidthLow => tpw_MAin3_negedge,
-        PeriodData => periodcheckinfo_MAin3,
-        Violation => tviol_MAin3_MAin3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
-                           PathDelay => tpd_MAin3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_2_B";
-
-      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin2 	: VitalDelayType := 0 ns;
-      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
-
-  end MAin_2_B;
-
-  architecture Structure of MAin_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_2: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin2_ipd,
-        TestSignalName => "MAin2",
-        Period => tperiod_MAin2,
-        PulseWidthHigh => tpw_MAin2_posedge,
-        PulseWidthLow => tpw_MAin2_negedge,
-        PeriodData => periodcheckinfo_MAin2,
-        Violation => tviol_MAin2_MAin2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
-                           PathDelay => tpd_MAin2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_1_B";
-
-      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin1 	: VitalDelayType := 0 ns;
-      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
-
-  end MAin_1_B;
-
-  architecture Structure of MAin_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin1_ipd,
-        TestSignalName => "MAin1",
-        Period => tperiod_MAin1,
-        PulseWidthHigh => tpw_MAin1_posedge,
-        PulseWidthLow => tpw_MAin1_negedge,
-        PeriodData => periodcheckinfo_MAin1,
-        Violation => tviol_MAin1_MAin1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
-                           PathDelay => tpd_MAin1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_0_B";
-
-      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin0 	: VitalDelayType := 0 ns;
-      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
-
-  end MAin_0_B;
-
-  architecture Structure of MAin_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin0_ipd,
-        TestSignalName => "MAin0",
-        Period => tperiod_MAin0,
-        PulseWidthHigh => tpw_MAin0_posedge,
-        PulseWidthLow => tpw_MAin0_negedge,
-        PeriodData => periodcheckinfo_MAin0,
-        Violation => tviol_MAin0_MAin0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
-                           PathDelay => tpd_MAin0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RAM2GS
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RAM2GS is
-    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
-          CROW: in Std_logic_vector (1 downto 0); 
-          Din: in Std_logic_vector (7 downto 0); 
-          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
-          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
-          RBA: out Std_logic_vector (1 downto 0); 
-          RA: out Std_logic_vector (11 downto 0); 
-          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
-          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
-          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
-          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
-          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
-
-
-
-  end RAM2GS;
-
-  architecture Structure of RAM2GS is
-    signal FS_1: Std_logic;
-    signal FS_0: Std_logic;
-    signal RCLK_c: Std_logic;
-    signal FS_cry_1: Std_logic;
-    signal FS_17: Std_logic;
-    signal FS_16: Std_logic;
-    signal FS_cry_15: Std_logic;
-    signal FS_15: Std_logic;
-    signal FS_14: Std_logic;
-    signal FS_cry_13: Std_logic;
-    signal FS_13: Std_logic;
-    signal FS_12: Std_logic;
-    signal FS_cry_11: Std_logic;
-    signal FS_11: Std_logic;
-    signal FS_10: Std_logic;
-    signal FS_cry_9: Std_logic;
-    signal FS_9: Std_logic;
-    signal FS_8: Std_logic;
-    signal FS_cry_7: Std_logic;
-    signal FS_7: Std_logic;
-    signal FS_6: Std_logic;
-    signal FS_cry_5: Std_logic;
-    signal FS_5: Std_logic;
-    signal FS_4: Std_logic;
-    signal FS_cry_3: Std_logic;
-    signal FS_3: Std_logic;
-    signal FS_2: Std_logic;
-    signal N_147: Std_logic;
-    signal MAin_c_0: Std_logic;
-    signal CmdEnable17_0_a2_4: Std_logic;
-    signal CmdEnable17_0_a2_3: Std_logic;
-    signal CmdEnable16: Std_logic;
-    signal CmdEnable17: Std_logic;
-    signal C1WR_0_a2: Std_logic;
-    signal ADSubmitted: Std_logic;
-    signal ADSubmitted_r: Std_logic;
-    signal PHI2_c: Std_logic;
-    signal CmdEnable16_0_a2_5: Std_logic;
-    signal CmdEnable16_0_a2_4: Std_logic;
-    signal MAin_c_1: Std_logic;
-    signal C1Submitted: Std_logic;
-    signal C1Submitted_RNO: Std_logic;
-    signal S_1: Std_logic;
-    signal RASr2: Std_logic;
-    signal IS_3: Std_logic;
-    signal CO0: Std_logic;
-    signal N_177_i: Std_logic;
-    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
-    signal CmdEnable: Std_logic;
-    signal un1_CMDWR: Std_logic;
-    signal CmdEnable_s: Std_logic;
-    signal N_128: Std_logic;
-    signal Din_c_5: Std_logic;
-    signal Din_c_3: Std_logic;
-    signal N_152: Std_logic;
-    signal N_133: Std_logic;
-    signal N_132: Std_logic;
-    signal LEDEN: Std_logic;
-    signal N_21_i: Std_logic;
-    signal XOR8MEG18: Std_logic;
-    signal CmdLEDEN: Std_logic;
-    signal PHI2r3: Std_logic;
-    signal PHI2r2: Std_logic;
-    signal InitReady: Std_logic;
-    signal CmdSubmitted: Std_logic;
-    signal CmdSubmitted_1_sqmuxa: Std_logic;
-    signal N_460_0: Std_logic;
-    signal N_136: Std_logic;
-    signal N_43: Std_logic;
-    signal Cmdn8MEGEN: Std_logic;
-    signal CmdEnable16_4: Std_logic;
-    signal n8MEGEN: Std_logic;
-    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
-    signal N_19_i: Std_logic;
-    signal nRRAS_5_u_i_0: Std_logic;
-    signal N_160: Std_logic;
-    signal N_155: Std_logic;
-    signal IS_0: Std_logic;
-    signal Ready: Std_logic;
-    signal N_64_i_i: Std_logic;
-    signal N_24: Std_logic;
-    signal IS_2: Std_logic;
-    signal IS_1: Std_logic;
-    signal N_60_i_i: Std_logic;
-    signal N_56_i: Std_logic;
-    signal N_159_i: Std_logic;
-    signal N_159: Std_logic;
-    signal N_61_i_i: Std_logic;
-    signal RA10s_i: Std_logic;
-    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
-    signal N_126: Std_logic;
-    signal N_51: Std_logic;
-    signal InitReady3: Std_logic;
-    signal N_461_0: Std_logic;
-    signal UFMSDI_ens2_i_a0: Std_logic;
-    signal nCRAS_c: Std_logic;
-    signal CBR: Std_logic;
-    signal UFMSDO_c: Std_logic;
-    signal N_70: Std_logic;
-    signal N_33: Std_logic;
-    signal LED_c: Std_logic;
-    signal un1_Din_4: Std_logic;
-    signal XOR8MEG: Std_logic;
-    signal Din_c_6: Std_logic;
-    signal RA11_2: Std_logic;
-    signal Ready_fast: Std_logic;
-    signal RA_c_11: Std_logic;
-    signal N_171: Std_logic;
-    signal FWEr_fast: Std_logic;
-    signal CASr2: Std_logic;
-    signal RCKEEN_8_u_1: Std_logic;
-    signal RCKEEN_8_u_0_0: Std_logic;
-    signal RCKEEN_8: Std_logic;
-    signal PHI2r: Std_logic;
-    signal RCKEEN: Std_logic;
-    signal RASr3: Std_logic;
-    signal RASr: Std_logic;
-    signal RCKE_2: Std_logic;
-    signal RCKE_c: Std_logic;
-    signal m18_0_a3_3: Std_logic;
-    signal S_0_i_o2_1: Std_logic;
-    signal N_165: Std_logic;
-    signal N_462_0: Std_logic;
-    signal Ready_0_sqmuxa: Std_logic;
-    signal N_463_0: Std_logic;
-    signal nRRAS_0_sqmuxa: Std_logic;
-    signal N_129: Std_logic;
-    signal UFMCLK_r_i_a2_2_2: Std_logic;
-    signal CmdUFMCLK: Std_logic;
-    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
-    signal UFMCLK_c: Std_logic;
-    signal nUFMCS15: Std_logic;
-    signal N_139_i: Std_logic;
-    signal UFMCLK_RNO: Std_logic;
-    signal UFMSDI_r_xx_mm_1: Std_logic;
-    signal UFMSDI_c: Std_logic;
-    signal UFMSDI_RNO: Std_logic;
-    signal nRowColSel: Std_logic;
-    signal RowA_4: Std_logic;
-    signal MAin_c_4: Std_logic;
-    signal Din_c_4: Std_logic;
-    signal nCCAS_c: Std_logic;
-    signal RA_c_4: Std_logic;
-    signal WRD_4: Std_logic;
-    signal WRD_5: Std_logic;
-    signal Bank_7: Std_logic;
-    signal Bank_6: Std_logic;
-    signal Bank_5: Std_logic;
-    signal Bank_2: Std_logic;
-    signal Din_c_7: Std_logic;
-    signal WRD_6: Std_logic;
-    signal C1WR_0_a2_0_11: Std_logic;
-    signal WRD_7: Std_logic;
-    signal Din_c_2: Std_logic;
-    signal Din_c_0: Std_logic;
-    signal XOR8MEG_3_u_0_a3_2: Std_logic;
-    signal Din_c_1: Std_logic;
-    signal XOR8MEG_3: Std_logic;
-    signal N_69: Std_logic;
-    signal N_31: Std_logic;
-    signal N_151: Std_logic;
-    signal g0_1: Std_logic;
-    signal nRCAS_0_sqmuxa_1: Std_logic;
-    signal N_41: Std_logic;
-    signal N_37_i: Std_logic;
-    signal nRCAS_c: Std_logic;
-    signal CASr3: Std_logic;
-    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
-    signal N_28_i_1: Std_logic;
-    signal N_28_i: Std_logic;
-    signal nRCS_c: Std_logic;
-    signal N_24_i: Std_logic;
-    signal nRRAS_c: Std_logic;
-    signal CBR_fast: Std_logic;
-    signal m18_0_a2_1: Std_logic;
-    signal G_17_1: Std_logic;
-    signal FWEr: Std_logic;
-    signal N_39_i: Std_logic;
-    signal nRWE_c: Std_logic;
-    signal N_179: Std_logic;
-    signal nRowColSel_0_0: Std_logic;
-    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
-    signal nUFMCS_c: Std_logic;
-    signal nUFMCS_s_0_N_5_i: Std_logic;
-    signal CmdUFMCS: Std_logic;
-    signal N_95_5: Std_logic;
-    signal N_95_3: Std_logic;
-    signal RowA_0: Std_logic;
-    signal RowA_1: Std_logic;
-    signal MAin_c_5: Std_logic;
-    signal CmdUFMCLK_1_sqmuxa: Std_logic;
-    signal RowA_5: Std_logic;
-    signal un1_FS_14_i_a2_0_1: Std_logic;
-    signal N_137_8: Std_logic;
-    signal N_137_6: Std_logic;
-    signal un1_FS_13_i_a2_1: Std_logic;
-    signal C1WR_0_a2_0_10: Std_logic;
-    signal Bank_1: Std_logic;
-    signal Bank_0: Std_logic;
-    signal MAin_c_7: Std_logic;
-    signal MAin_c_6: Std_logic;
-    signal C1WR_0_a2_0_4: Std_logic;
-    signal C1WR_0_a2_0_3: Std_logic;
-    signal Bank_4: Std_logic;
-    signal Bank_3: Std_logic;
-    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
-    signal MAin_c_3: Std_logic;
-    signal MAin_c_2: Std_logic;
-    signal RowA_2: Std_logic;
-    signal RowA_3: Std_logic;
-    signal CmdUFMSDI: Std_logic;
-    signal CASr: Std_logic;
-    signal CmdEnable16_1: Std_logic;
-    signal m6_0_a2_2: Std_logic;
-    signal WRD_0: Std_logic;
-    signal WRD_1: Std_logic;
-    signal g4_0_0_0: Std_logic;
-    signal MAin_c_9: Std_logic;
-    signal MAin_c_8: Std_logic;
-    signal RowA_8: Std_logic;
-    signal RowA_9: Std_logic;
-    signal nFWE_c: Std_logic;
-    signal CROW_c_1: Std_logic;
-    signal CROW_c_0: Std_logic;
-    signal RBA_c_0: Std_logic;
-    signal RBA_c_1: Std_logic;
-    signal WRD_2: Std_logic;
-    signal WRD_3: Std_logic;
-    signal RA_c_9: Std_logic;
-    signal RDQML_c: Std_logic;
-    signal RD_1_i: Std_logic;
-    signal RowA_6: Std_logic;
-    signal RowA_7: Std_logic;
-    signal RA_c_8: Std_logic;
-    signal RDQMH_c: Std_logic;
-    signal RA_c_0: Std_logic;
-    signal RA_c_1: Std_logic;
-    signal RA_c_7: Std_logic;
-    signal RA_c_2: Std_logic;
-    signal RA_c_6: Std_logic;
-    signal RA_c_3: Std_logic;
-    signal RA_c_5: Std_logic;
-    signal RA_c_10: Std_logic;
-    signal RD_in_0: Std_logic;
-    signal RD_in_7: Std_logic;
-    signal RD_in_6: Std_logic;
-    signal RD_in_5: Std_logic;
-    signal RD_in_4: Std_logic;
-    signal RD_in_3: Std_logic;
-    signal RD_in_2: Std_logic;
-    signal RD_in_1: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI_TSALL: Std_logic;
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-    component PUR
-      port (PUR: in Std_logic);
-    end component;
-    component GSR
-      port (GSR: in Std_logic);
-    end component;
-    component TSALL
-      port (TSALL: in Std_logic);
-    end component;
-    component SLICE_0
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_1
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_2
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_3
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_4
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_5
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_6
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_7
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_8
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_9
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_14
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_19
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_20
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_21
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_22
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_26
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_29
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_30
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_31
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_32
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_33
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_39
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_41
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_42
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_43
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_44
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_50
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_51
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_52
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_55
-      port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_56
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_57
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_58
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_59
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_60
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_61
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_62
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_63
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_64
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component nRWE_RNO_1_SLICE_65
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            OFX0: out Std_logic);
-    end component;
-    component SLICE_66
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_67
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_68
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_69
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_70
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_71
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_72
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_73
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_74
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_75
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_76
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_77
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_78
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_79
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_80
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_81
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_82
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_83
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_84
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_85
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_86
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_87
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_88
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_89
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_90
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_91
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_92
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_93
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_94
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component RD_0_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD0: inout Std_logic);
-    end component;
-    component Dout_0_B
-      port (PADDO: in Std_logic; Dout0: out Std_logic);
-    end component;
-    component PHI2B
-      port (PADDI: out Std_logic; PHI2S: in Std_logic);
-    end component;
-    component UFMSDOB
-      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-    end component;
-    component UFMSDIB
-      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-    end component;
-    component UFMCLKB
-      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-    end component;
-    component nUFMCSB
-      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-    end component;
-    component RDQMLB
-      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-    end component;
-    component RDQMHB
-      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-    end component;
-    component nRCASB
-      port (PADDO: in Std_logic; nRCASS: out Std_logic);
-    end component;
-    component nRRASB
-      port (PADDO: in Std_logic; nRRASS: out Std_logic);
-    end component;
-    component nRWEB
-      port (PADDO: in Std_logic; nRWES: out Std_logic);
-    end component;
-    component RCKEB
-      port (PADDO: in Std_logic; RCKES: out Std_logic);
-    end component;
-    component RCLKB
-      port (PADDI: out Std_logic; RCLKS: in Std_logic);
-    end component;
-    component nRCSB
-      port (PADDO: in Std_logic; nRCSS: out Std_logic);
-    end component;
-    component RD_7_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD7: inout Std_logic);
-    end component;
-    component RD_6_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD6: inout Std_logic);
-    end component;
-    component RD_5_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD5: inout Std_logic);
-    end component;
-    component RD_4_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD4: inout Std_logic);
-    end component;
-    component RD_3_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD3: inout Std_logic);
-    end component;
-    component RD_2_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD2: inout Std_logic);
-    end component;
-    component RD_1_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD1: inout Std_logic);
-    end component;
-    component RA_11_B
-      port (PADDO: in Std_logic; RA11: out Std_logic);
-    end component;
-    component RA_10_B
-      port (PADDO: in Std_logic; RA10: out Std_logic);
-    end component;
-    component RA_9_B
-      port (PADDO: in Std_logic; RA9: out Std_logic);
-    end component;
-    component RA_8_B
-      port (PADDO: in Std_logic; RA8: out Std_logic);
-    end component;
-    component RA_7_B
-      port (PADDO: in Std_logic; RA7: out Std_logic);
-    end component;
-    component RA_6_B
-      port (PADDO: in Std_logic; RA6: out Std_logic);
-    end component;
-    component RA_5_B
-      port (PADDO: in Std_logic; RA5: out Std_logic);
-    end component;
-    component RA_4_B
-      port (PADDO: in Std_logic; RA4: out Std_logic);
-    end component;
-    component RA_3_B
-      port (PADDO: in Std_logic; RA3: out Std_logic);
-    end component;
-    component RA_2_B
-      port (PADDO: in Std_logic; RA2: out Std_logic);
-    end component;
-    component RA_1_B
-      port (PADDO: in Std_logic; RA1: out Std_logic);
-    end component;
-    component RA_0_B
-      port (PADDO: in Std_logic; RA0: out Std_logic);
-    end component;
-    component RBA_1_B
-      port (PADDO: in Std_logic; RBA1: out Std_logic);
-    end component;
-    component RBA_0_B
-      port (PADDO: in Std_logic; RBA0: out Std_logic);
-    end component;
-    component LEDB
-      port (PADDO: in Std_logic; LEDS: out Std_logic);
-    end component;
-    component nFWEB
-      port (PADDI: out Std_logic; nFWES: in Std_logic);
-    end component;
-    component nCRASB
-      port (PADDI: out Std_logic; nCRASS: in Std_logic);
-    end component;
-    component nCCASB
-      port (PADDI: out Std_logic; nCCASS: in Std_logic);
-    end component;
-    component Dout_7_B
-      port (PADDO: in Std_logic; Dout7: out Std_logic);
-    end component;
-    component Dout_6_B
-      port (PADDO: in Std_logic; Dout6: out Std_logic);
-    end component;
-    component Dout_5_B
-      port (PADDO: in Std_logic; Dout5: out Std_logic);
-    end component;
-    component Dout_4_B
-      port (PADDO: in Std_logic; Dout4: out Std_logic);
-    end component;
-    component Dout_3_B
-      port (PADDO: in Std_logic; Dout3: out Std_logic);
-    end component;
-    component Dout_2_B
-      port (PADDO: in Std_logic; Dout2: out Std_logic);
-    end component;
-    component Dout_1_B
-      port (PADDO: in Std_logic; Dout1: out Std_logic);
-    end component;
-    component Din_7_B
-      port (PADDI: out Std_logic; Din7: in Std_logic);
-    end component;
-    component Din_6_B
-      port (PADDI: out Std_logic; Din6: in Std_logic);
-    end component;
-    component Din_5_B
-      port (PADDI: out Std_logic; Din5: in Std_logic);
-    end component;
-    component Din_4_B
-      port (PADDI: out Std_logic; Din4: in Std_logic);
-    end component;
-    component Din_3_B
-      port (PADDI: out Std_logic; Din3: in Std_logic);
-    end component;
-    component Din_2_B
-      port (PADDI: out Std_logic; Din2: in Std_logic);
-    end component;
-    component Din_1_B
-      port (PADDI: out Std_logic; Din1: in Std_logic);
-    end component;
-    component Din_0_B
-      port (PADDI: out Std_logic; Din0: in Std_logic);
-    end component;
-    component CROW_1_B
-      port (PADDI: out Std_logic; CROW1: in Std_logic);
-    end component;
-    component CROW_0_B
-      port (PADDI: out Std_logic; CROW0: in Std_logic);
-    end component;
-    component MAin_9_B
-      port (PADDI: out Std_logic; MAin9: in Std_logic);
-    end component;
-    component MAin_8_B
-      port (PADDI: out Std_logic; MAin8: in Std_logic);
-    end component;
-    component MAin_7_B
-      port (PADDI: out Std_logic; MAin7: in Std_logic);
-    end component;
-    component MAin_6_B
-      port (PADDI: out Std_logic; MAin6: in Std_logic);
-    end component;
-    component MAin_5_B
-      port (PADDI: out Std_logic; MAin5: in Std_logic);
-    end component;
-    component MAin_4_B
-      port (PADDI: out Std_logic; MAin4: in Std_logic);
-    end component;
-    component MAin_3_B
-      port (PADDI: out Std_logic; MAin3: in Std_logic);
-    end component;
-    component MAin_2_B
-      port (PADDI: out Std_logic; MAin2: in Std_logic);
-    end component;
-    component MAin_1_B
-      port (PADDI: out Std_logic; MAin1: in Std_logic);
-    end component;
-    component MAin_0_B
-      port (PADDI: out Std_logic; MAin0: in Std_logic);
-    end component;
-  begin
-    SLICE_0I: SLICE_0
-      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
-                FCO=>FS_cry_1);
-    SLICE_1I: SLICE_1
-      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
-                Q1=>FS_17);
-    SLICE_2I: SLICE_2
-      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
-                Q1=>FS_15, FCO=>FS_cry_15);
-    SLICE_3I: SLICE_3
-      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
-                Q1=>FS_13, FCO=>FS_cry_13);
-    SLICE_4I: SLICE_4
-      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
-                Q1=>FS_11, FCO=>FS_cry_11);
-    SLICE_5I: SLICE_5
-      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
-                Q1=>FS_9, FCO=>FS_cry_9);
-    SLICE_6I: SLICE_6
-      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
-                Q1=>FS_7, FCO=>FS_cry_7);
-    SLICE_7I: SLICE_7
-      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
-                Q1=>FS_5, FCO=>FS_cry_5);
-    SLICE_8I: SLICE_8
-      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
-                Q1=>FS_3, FCO=>FS_cry_3);
-    SLICE_9I: SLICE_9
-      port map (D1=>N_147, C1=>MAin_c_0, B1=>CmdEnable17_0_a2_4, 
-                A1=>CmdEnable17_0_a2_3, D0=>CmdEnable16, C0=>CmdEnable17, 
-                B0=>C1WR_0_a2, A0=>ADSubmitted, DI0=>ADSubmitted_r, 
-                CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted, 
-                F1=>CmdEnable17);
-    SLICE_14I: SLICE_14
-      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
-                D0=>MAin_c_1, C0=>N_147, B0=>C1Submitted, A0=>CmdEnable16, 
-                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
-                Q0=>C1Submitted, F1=>CmdEnable16);
-    SLICE_19I: SLICE_19
-      port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, 
-                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
-                F1=>Ready_0_sqmuxa_0_a3_2);
-    SLICE_20I: SLICE_20
-      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, 
-                B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, 
-                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
-    SLICE_21I: SLICE_21
-      port map (C1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_152, C0=>N_133, 
-                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
-                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
-    SLICE_22I: SLICE_22
-      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
-                B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_460_0, 
-                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
-    SLICE_26I: SLICE_26
-      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
-                C0=>n8MEGEN, B0=>N_152, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_19_i, 
-                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
-                F1=>Cmdn8MEGEN_4_u_i_0);
-    SLICE_29I: SLICE_29
-      port map (D1=>nRRAS_5_u_i_0, C1=>N_160, B1=>N_155, A1=>IS_0, C0=>N_155, 
-                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
-                Q0=>IS_0, F1=>N_24);
-    SLICE_30I: SLICE_30
-      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, 
-                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
-    SLICE_31I: SLICE_31
-      port map (D1=>N_159, C1=>IS_3, B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, 
-                B0=>IS_2, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
-    SLICE_32I: SLICE_32
-      port map (D1=>UFMSDI_ens2_i_a2_4_2, C1=>N_126, B1=>N_51, A1=>InitReady, 
-                B0=>InitReady, A0=>InitReady3, DI0=>N_461_0, CLK=>RCLK_c, 
-                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
-    SLICE_33I: SLICE_33
-      port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, C0=>UFMSDO_c, B0=>InitReady, 
-                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
-                Q0=>LEDEN, F1=>LED_c);
-    SLICE_39I: SLICE_39
-      port map (B1=>un1_Din_4, A1=>XOR8MEG, C0=>n8MEGEN, B0=>XOR8MEG, 
-                A0=>Din_c_6, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
-                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
-    SLICE_41I: SLICE_41
-      port map (D1=>S_1, C1=>FWEr_fast, B1=>CO0, A1=>CASr2, D0=>Ready, 
-                C0=>RCKEEN_8_u_1, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, 
-                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
-                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
-    SLICE_42I: SLICE_42
-      port map (D1=>RASr2, C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>RCKEEN, C0=>RASr3, 
-                B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
-                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
-    SLICE_43I: SLICE_43
-      port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, 
-                D0=>InitReady, C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, 
-                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
-                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
-    SLICE_44I: SLICE_44
-      port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_165, A1=>InitReady, 
-                B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_463_0, M1=>nCRAS_c, 
-                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
-                Q1=>RASr);
-    SLICE_50I: SLICE_50
-      port map (C1=>CO0, B1=>S_1, A1=>Ready, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1, 
-                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
-                F1=>nRRAS_0_sqmuxa);
-    SLICE_51I: SLICE_51
-      port map (D1=>N_129, C1=>UFMCLK_r_i_a2_2_2, B1=>CmdUFMCLK, A1=>InitReady, 
-                D0=>UFMCLK_r_i_m4_xx_mm_1, C0=>UFMCLK_c, B0=>nUFMCS15, 
-                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
-                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
-                Q1=>RASr2);
-    SLICE_52I: SLICE_52
-      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
-                D0=>UFMSDI_r_xx_mm_1, C0=>UFMSDI_c, B0=>nUFMCS15, A0=>N_139_i, 
-                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
-                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
-    SLICE_55I: SLICE_55
-      port map (C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, M1=>Din_c_5, 
-                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
-    SLICE_56I: SLICE_56
-      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, C0=>FS_9, 
-                B0=>FS_7, A0=>FS_5, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
-                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
-    SLICE_57I: SLICE_57
-      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
-                D0=>XOR8MEG_3_u_0_a3_2, C0=>N_171, B0=>LEDEN, A0=>Din_c_1, 
-                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
-                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
-    SLICE_58I: SLICE_58
-      port map (C1=>N_51, B1=>InitReady, A1=>FS_8, C0=>UFMSDO_c, B0=>InitReady, 
-                A0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
-                Q0=>n8MEGEN, F1=>N_151);
-    SLICE_59I: SLICE_59
-      port map (D1=>S_1, C1=>Ready, B1=>N_160, A1=>N_155, D0=>g0_1, C0=>S_1, 
-                B0=>nRCAS_0_sqmuxa_1, A0=>N_41, DI0=>N_37_i, CLK=>RCLK_c, 
-                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
-    SLICE_60I: SLICE_60
-      port map (D1=>CASr2, C1=>CASr3, B1=>CO0, A1=>FWEr_fast, 
-                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
-                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
-    SLICE_61I: SLICE_61
-      port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, D0=>IS_0, 
-                C0=>N_155, B0=>N_160, A0=>nRRAS_5_u_i_0, DI0=>N_24_i, 
-                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
-    SLICE_62I: SLICE_62
-      port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR_fast, 
-                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>G_17_1, A0=>FWEr, 
-                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
-                F1=>nRCAS_0_sqmuxa_1);
-    SLICE_63I: SLICE_63
-      port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, 
-                B0=>N_179, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
-                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
-    SLICE_64I: SLICE_64
-      port map (D1=>N_51, C1=>InitReady, B1=>FS_11, A1=>FS_10, 
-                D0=>nUFMCS_s_0_N_5_i_N_2L1, C0=>nUFMCS_c, B0=>nUFMCS15, 
-                A0=>N_139_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, 
-                F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS15);
-    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
-      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>InitReady, 
-                C0=>m18_0_a3_3, B0=>CO0, A0=>S_1, M0=>Ready, OFX0=>m18_0_a2_1);
-    SLICE_66I: SLICE_66
-      port map (C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, A1=>CmdUFMCS, D0=>N_95_5, 
-                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
-                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
-                Q1=>RowA_1);
-    SLICE_67I: SLICE_67
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_128, A1=>XOR8MEG18, D0=>N_147, 
-                C0=>MAin_c_1, B0=>MAin_c_0, A0=>CmdEnable, M1=>MAin_c_5, 
-                M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, F0=>XOR8MEG18, 
-                Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
-    SLICE_68I: SLICE_68
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_14_i_a2_0_1, 
-                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_31, 
-                F1=>un1_FS_14_i_a2_0_1);
-    SLICE_69I: SLICE_69
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_13_i_a2_1, 
-                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_33, 
-                F1=>un1_FS_13_i_a2_1);
-    SLICE_70I: SLICE_70
-      port map (D1=>C1WR_0_a2_0_11, C1=>C1WR_0_a2_0_10, B1=>Bank_1, A1=>Bank_0, 
-                B0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
-                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
-    SLICE_71I: SLICE_71
-      port map (D1=>MAin_c_7, C1=>MAin_c_6, B1=>MAin_c_5, A1=>MAin_c_4, 
-                D0=>C1WR_0_a2_0_4, C0=>C1WR_0_a2_0_3, B0=>Bank_4, A0=>Bank_3, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
-                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
-    SLICE_72I: SLICE_72
-      port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_12, D0=>N_51, 
-                C0=>FS_11, B0=>FS_4, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
-                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
-                Q1=>RowA_3);
-    SLICE_73I: SLICE_73
-      port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, B0=>Ready, 
-                A0=>N_155, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
-                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
-    SLICE_74I: SLICE_74
-      port map (B1=>FS_14, A1=>FS_11, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
-                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
-    SLICE_75I: SLICE_75
-      port map (C1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, C0=>N_128, B0=>Din_c_5, 
-                A0=>Din_c_1, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
-                Q0=>CASr, F1=>N_128, Q1=>CASr2);
-    SLICE_76I: SLICE_76
-      port map (B1=>Din_c_5, A1=>Din_c_0, D0=>MAin_c_0, C0=>Din_c_3, 
-                B0=>Din_c_1, A0=>CmdEnable16_4, M1=>Din_c_5, M0=>Din_c_4, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
-                F1=>CmdEnable16_4, Q1=>Bank_5);
-    SLICE_77I: SLICE_77
-      port map (B1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>Din_c_6, 
-                B0=>Din_c_2, A0=>CmdEnable16_1, M1=>Din_c_7, M0=>Din_c_6, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
-                F1=>CmdEnable16_1, Q1=>Bank_7);
-    SLICE_78I: SLICE_78
-      port map (B1=>Din_c_5, A1=>Din_c_3, D0=>N_43, C0=>MAin_c_1, B0=>Din_c_6, 
-                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
-                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
-    SLICE_79I: SLICE_79
-      port map (C1=>Ready, B1=>CASr3, A1=>CASr2, D0=>m6_0_a2_2, C0=>S_1, 
-                B0=>CO0, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
-                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
-    SLICE_80I: SLICE_80
-      port map (B1=>CASr3, A1=>CASr2, D0=>g4_0_0_0, C0=>FWEr, B0=>CO0, 
-                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
-    SLICE_81I: SLICE_81
-      port map (D1=>FS_17, C1=>FS_15, B1=>FS_14, A1=>FS_13, D0=>FS_17, 
-                C0=>FS_15, B0=>FS_13, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
-                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
-                Q1=>FWEr_fast);
-    SLICE_82I: SLICE_82
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>CmdLEDEN, A1=>N_128, D0=>Din_c_3, 
-                C0=>Din_c_5, B0=>N_128, A0=>XOR8MEG18, M0=>CASr2, CLK=>RCLK_c, 
-                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
-    SLICE_83I: SLICE_83
-      port map (C1=>IS_3, B1=>IS_2, A1=>IS_1, C0=>IS_2, B0=>IS_1, A0=>IS_0, 
-                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
-    SLICE_84I: SLICE_84
-      port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>FS_10, C0=>FS_7, 
-                B0=>FS_6, A0=>FS_1, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
-    SLICE_85I: SLICE_85
-      port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_0, A1=>Din_c_1, 
-                D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
-                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
-    SLICE_86I: SLICE_86
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, 
-                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
-    SLICE_87I: SLICE_87
-      port map (C1=>N_151, B1=>UFMSDI_ens2_i_a0, A1=>CmdUFMSDI, D0=>N_151, 
-                C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_137_8, 
-                F1=>UFMSDI_r_xx_mm_1);
-    SLICE_88I: SLICE_88
-      port map (C1=>nFWE_c, B1=>MAin_c_3, A1=>MAin_c_2, B0=>nFWE_c, 
-                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
-                Q1=>RowA_7);
-    SLICE_89I: SLICE_89
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, 
-                A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
-    SLICE_90I: SLICE_90
-      port map (C1=>MAin_c_1, B1=>MAin_c_0, A1=>N_147, C0=>nRowColSel, 
-                B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>un1_CMDWR);
-    SLICE_91I: SLICE_91
-      port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, 
-                B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
-    SLICE_92I: SLICE_92
-      port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, 
-                B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
-    SLICE_93I: SLICE_93
-      port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, 
-                B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
-    SLICE_94I: SLICE_94
-      port map (B1=>N_155, A1=>Ready, B0=>S_1, A0=>Ready, M0=>IS_0, 
-                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
-                Q0=>RA_c_10, F1=>N_159_i);
-    RD_0_I: RD_0_B
-      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
-    Dout_0_I: Dout_0_B
-      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
-    PHI2I: PHI2B
-      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
-    UFMSDOI: UFMSDOB
-      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
-    UFMSDII: UFMSDIB
-      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
-    UFMCLKI: UFMCLKB
-      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
-    nUFMCSI: nUFMCSB
-      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
-    RDQMLI: RDQMLB
-      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
-    RDQMHI: RDQMHB
-      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
-    nRCASI: nRCASB
-      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
-    nRRASI: nRRASB
-      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
-    nRWEI: nRWEB
-      port map (PADDO=>nRWE_c, nRWES=>nRWE);
-    RCKEI: RCKEB
-      port map (PADDO=>RCKE_c, RCKES=>RCKE);
-    RCLKI: RCLKB
-      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
-    nRCSI: nRCSB
-      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
-    RD_7_I: RD_7_B
-      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
-    RD_6_I: RD_6_B
-      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
-    RD_5_I: RD_5_B
-      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
-    RD_4_I: RD_4_B
-      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
-    RD_3_I: RD_3_B
-      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
-    RD_2_I: RD_2_B
-      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
-    RD_1_I0: RD_1_B
-      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
-    RA_11_I: RA_11_B
-      port map (PADDO=>RA_c_11, RA11=>RA(11));
-    RA_10_I: RA_10_B
-      port map (PADDO=>RA_c_10, RA10=>RA(10));
-    RA_9_I: RA_9_B
-      port map (PADDO=>RA_c_9, RA9=>RA(9));
-    RA_8_I: RA_8_B
-      port map (PADDO=>RA_c_8, RA8=>RA(8));
-    RA_7_I: RA_7_B
-      port map (PADDO=>RA_c_7, RA7=>RA(7));
-    RA_6_I: RA_6_B
-      port map (PADDO=>RA_c_6, RA6=>RA(6));
-    RA_5_I: RA_5_B
-      port map (PADDO=>RA_c_5, RA5=>RA(5));
-    RA_4_I: RA_4_B
-      port map (PADDO=>RA_c_4, RA4=>RA(4));
-    RA_3_I: RA_3_B
-      port map (PADDO=>RA_c_3, RA3=>RA(3));
-    RA_2_I: RA_2_B
-      port map (PADDO=>RA_c_2, RA2=>RA(2));
-    RA_1_I: RA_1_B
-      port map (PADDO=>RA_c_1, RA1=>RA(1));
-    RA_0_I: RA_0_B
-      port map (PADDO=>RA_c_0, RA0=>RA(0));
-    RBA_1_I: RBA_1_B
-      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
-    RBA_0_I: RBA_0_B
-      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
-    LEDI: LEDB
-      port map (PADDO=>LED_c, LEDS=>LED);
-    nFWEI: nFWEB
-      port map (PADDI=>nFWE_c, nFWES=>nFWE);
-    nCRASI: nCRASB
-      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
-    nCCASI: nCCASB
-      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
-    Dout_7_I: Dout_7_B
-      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
-    Dout_6_I: Dout_6_B
-      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
-    Dout_5_I: Dout_5_B
-      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
-    Dout_4_I: Dout_4_B
-      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
-    Dout_3_I: Dout_3_B
-      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
-    Dout_2_I: Dout_2_B
-      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
-    Dout_1_I: Dout_1_B
-      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
-    Din_7_I: Din_7_B
-      port map (PADDI=>Din_c_7, Din7=>Din(7));
-    Din_6_I: Din_6_B
-      port map (PADDI=>Din_c_6, Din6=>Din(6));
-    Din_5_I: Din_5_B
-      port map (PADDI=>Din_c_5, Din5=>Din(5));
-    Din_4_I: Din_4_B
-      port map (PADDI=>Din_c_4, Din4=>Din(4));
-    Din_3_I: Din_3_B
-      port map (PADDI=>Din_c_3, Din3=>Din(3));
-    Din_2_I: Din_2_B
-      port map (PADDI=>Din_c_2, Din2=>Din(2));
-    Din_1_I: Din_1_B
-      port map (PADDI=>Din_c_1, Din1=>Din(1));
-    Din_0_I: Din_0_B
-      port map (PADDI=>Din_c_0, Din0=>Din(0));
-    CROW_1_I: CROW_1_B
-      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
-    CROW_0_I: CROW_0_B
-      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
-    MAin_9_I: MAin_9_B
-      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
-    MAin_8_I: MAin_8_B
-      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
-    MAin_7_I: MAin_7_B
-      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
-    MAin_6_I: MAin_6_B
-      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
-    MAin_5_I: MAin_5_B
-      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
-    MAin_4_I: MAin_4_B
-      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
-    MAin_3_I: MAin_3_B
-      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
-    MAin_2_I: MAin_2_B
-      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
-    MAin_1_I: MAin_1_B
-      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
-    MAin_0_I: MAin_0_B
-      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
-    VHI_INST: VHI
-      port map (Z=>VCCI);
-    PUR_INST: PUR
-      port map (PUR=>VCCI);
-    GSR_INST: GSR
-      port map (GSR=>VCCI);
-    VLO_INST: VLO
-      port map (Z=>GNDI_TSALL);
-    TSALL_INST: TSALL
-      port map (TSALL=>GNDI_TSALL);
-  end Structure;
-
-
-
-  library IEEE, vital2000, MACHXO;
-  configuration Structure_CON of RAM2GS is
-    for Structure
-    end for;
-  end Structure_CON;
-
-
+
+-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+-- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
+-- Netlist created on Sat Aug 19 20:53:19 2023
+-- Netlist written on Sat Aug 19 20:53:21 2023
+-- Design is for device LCMXO256C
+-- Design is for package TQFP100
+-- Design is for performance grade 3
+
+-- entity vmuxregsre
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
+
+  end vmuxregsre;
+
+  architecture Structure of vmuxregsre is
+    component FL1P3DX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity vcc
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vcc is
+    port (PWR1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
+
+  end vcc;
+
+  architecture Structure of vcc is
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VHI
+      port map (Z=>PWR1);
+  end Structure;
+
+-- entity gnd
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity gnd is
+    port (PWR0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
+
+  end gnd;
+
+  architecture Structure of gnd is
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VLO
+      port map (Z=>PWR0);
+  end Structure;
+
+-- entity ccu2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu2B is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
+
+  end ccu2B;
+
+  architecture Structure of ccu2B is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_0
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_0";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
+
+  end SLICE_0;
+
+  architecture Structure of SLICE_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_0: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
+                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20001
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu20001 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
+
+  end ccu20001;
+
+  architecture Structure of ccu20001 is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_1
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_1";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
+
+  end SLICE_1;
+
+  architecture Structure of SLICE_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu20001
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_17: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_16: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_16: ccu20001
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
+                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_2 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_2";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
+
+  end SLICE_2;
+
+  architecture Structure of SLICE_2 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_15: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_14: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_14: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
+                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_3
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_3 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_3";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
+
+  end SLICE_3;
+
+  architecture Structure of SLICE_3 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_13: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_12: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_12: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
+                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_4 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_4";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
+
+  end SLICE_4;
+
+  architecture Structure of SLICE_4 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_11: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_10: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_10: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
+                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_5
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_5 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_5";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
+
+  end SLICE_5;
+
+  architecture Structure of SLICE_5 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_9: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_8: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_8: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
+                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_6
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_6 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_6";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
+
+  end SLICE_6;
+
+  architecture Structure of SLICE_6 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_7: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_6: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_6: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
+                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_7
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_7 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_7";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
+
+  end SLICE_7;
+
+  architecture Structure of SLICE_7 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_5: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_4: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_4: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
+                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_8
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_8 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_8";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
+
+  end SLICE_8;
+
+  architecture Structure of SLICE_8 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_2: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
+                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut4 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
+
+  end lut4;
+
+  architecture Structure of lut4 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40002
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40002 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
+
+  end lut40002;
+
+  architecture Structure of lut40002 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00F2")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity inverter
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity inverter is
+    port (I: in Std_logic; Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
+
+  end inverter;
+
+  architecture Structure of inverter is
+    component INV
+      port (A: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    INST1: INV
+      port map (A=>I, Z=>Z);
+  end Structure;
+
+-- entity SLICE_9
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_9 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_9";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
+
+  end SLICE_9;
+
+  architecture Structure of SLICE_9 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40002
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    ADSubmitted_r: lut40002
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    ADSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40003
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40003 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
+
+  end lut40003;
+
+  architecture Structure of lut40003 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8080")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40004
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40004 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
+
+  end lut40004;
+
+  architecture Structure of lut40004 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_14
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_14 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_14";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
+
+  end SLICE_14;
+
+  architecture Structure of SLICE_14 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40003
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40004
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2: lut40003
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    C1Submitted_RNO: lut40004
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    C1Submitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40005
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40005 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
+
+  end lut40005;
+
+  architecture Structure of lut40005 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40006
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40006 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
+
+  end lut40006;
+
+  architecture Structure of lut40006 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDDDD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0007
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0007 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
+
+  end vmuxregsre0007;
+
+  architecture Structure of vmuxregsre0007 is
+    component FL1P3IY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3IY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_19
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_19 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_19";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
+
+  end SLICE_19;
+
+  architecture Structure of SLICE_19 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40006
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    S_RNO_0: lut40006
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40008
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40008 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
+
+  end lut40008;
+
+  architecture Structure of lut40008 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40009
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40009 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
+
+  end lut40009;
+
+  architecture Structure of lut40009 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAC8C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity selmux2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity selmux2 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
+
+  end selmux2;
+
+  architecture Structure of selmux2 is
+    component MUX21
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    INST1: MUX21
+      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
+  end Structure;
+
+-- entity SLICE_20
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_20 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_20";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
+
+  end SLICE_20;
+
+  architecture Structure of SLICE_20 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
+    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40008
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40009
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    SLICE_20_K1: lut40008
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
+                Z=>SLICE_20_SLICE_20_K1_H1);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable_s_GATE: lut40009
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>SLICE_20_CmdEnable_s_GATE_H0);
+    CmdEnable: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    SLICE_20_K0K1MUX: selmux2
+      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
+                SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40010
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40010 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
+
+  end lut40010;
+
+  architecture Structure of lut40010 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40011
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40011 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
+
+  end lut40011;
+
+  architecture Structure of lut40011 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0203")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_21
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_21 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_21";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
+
+  end SLICE_21;
+
+  architecture Structure of SLICE_21 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40010
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40011
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_a2_2: lut40010
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_RNO: lut40011
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdLEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40012
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40012 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
+
+  end lut40012;
+
+  architecture Structure of lut40012 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_22
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_22 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_22";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
+
+  end SLICE_22;
+
+  architecture Structure of SLICE_22 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40013
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40013 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
+
+  end lut40013;
+
+  architecture Structure of lut40013 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33AB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40014
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40014 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
+
+  end lut40014;
+
+  architecture Structure of lut40014 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5151")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_26
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_26 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_26";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
+
+  end SLICE_26;
+
+  architecture Structure of SLICE_26 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40014
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_0: lut40013
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Cmdn8MEGEN_RNO: lut40014
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Cmdn8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40015
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40015 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
+
+  end lut40015;
+
+  architecture Structure of lut40015 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF32")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40016
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40016 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
+
+  end lut40016;
+
+  architecture Structure of lut40016 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA9A9")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_29
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_29 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_29";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
+
+  end SLICE_29;
+
+  architecture Structure of SLICE_29 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40015
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40016
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i: lut40015
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_0: lut40016
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40017
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40017 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
+
+  end lut40017;
+
+  architecture Structure of lut40017 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7878")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40018
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40018 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
+
+  end lut40018;
+
+  architecture Structure of lut40018 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x6666")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_30
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_30 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_30";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
+
+  end SLICE_30;
+
+  architecture Structure of SLICE_30 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40017
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40018
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_RNO_2: lut40017
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_n1_0_x2: lut40018
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    IS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    IS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40019
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40019 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
+
+  end lut40019;
+
+  architecture Structure of lut40019 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40020
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40020 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
+
+  end lut40020;
+
+  architecture Structure of lut40020 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x6AAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_31
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_31 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_31";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
+
+  end SLICE_31;
+
+  architecture Structure of SLICE_31 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40019
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40020
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RA10_RNO: lut40019
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_3: lut40020
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    IS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40021
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40021 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
+
+  end lut40021;
+
+  architecture Structure of lut40021 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4555")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_32
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_32 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_32";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
+
+  end SLICE_32;
+
+  architecture Structure of SLICE_32 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40021
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a0: lut40021
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40022
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40022 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
+
+  end lut40022;
+
+  architecture Structure of lut40022 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFBFB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40023
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40023 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
+
+  end lut40023;
+
+  architecture Structure of lut40023 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8B8B")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_33
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_33 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_33";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
+
+  end SLICE_33;
+
+  architecture Structure of SLICE_33 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40022
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    LED_pad_RNO: lut40022
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    LEDEN_5_i_m2: lut40023
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    LEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40024
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40024 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
+
+  end lut40024;
+
+  architecture Structure of lut40024 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40025
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40025 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
+
+  end lut40025;
+
+  architecture Structure of lut40025 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xC6C6")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_39
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_39 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_39";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
+
+  end SLICE_39;
+
+  architecture Structure of SLICE_39 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40025
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_0: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RA11_2: lut40025
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RA11: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40026
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40026 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
+
+  end lut40026;
+
+  architecture Structure of lut40026 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x70CF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40027
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40027 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
+
+  end lut40027;
+
+  architecture Structure of lut40027 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_41
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_41 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_41";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
+
+  end SLICE_41;
+
+  architecture Structure of SLICE_41 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40026
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40027
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_1_0: lut40026
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKEEN_8_u: lut40027
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40028
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40028 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
+
+  end lut40028;
+
+  architecture Structure of lut40028 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40029
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40029 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
+
+  end lut40029;
+
+  architecture Structure of lut40029 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFE30")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_42
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_42 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_42";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
+
+  end SLICE_42;
+
+  architecture Structure of SLICE_42 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40029
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_5: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKE_2_0: lut40029
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKE: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40030
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40030 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
+
+  end lut40030;
+
+  architecture Structure of lut40030 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5072")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40031
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40031 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
+
+  end lut40031;
+
+  architecture Structure of lut40031 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAEAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_43
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_43 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_43";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
+
+  end SLICE_43;
+
+  architecture Structure of SLICE_43 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40030
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40031
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_RNO: lut40030
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_RNO: lut40031
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_44
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_44 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_44";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
+
+  end SLICE_44;
+
+  architecture Structure of SLICE_44 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_fast_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RASr: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Ready_fast: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40032
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40032 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
+
+  end lut40032;
+
+  architecture Structure of lut40032 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0202")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_50
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_50 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_50";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
+
+  end SLICE_50;
+
+  architecture Structure of SLICE_50 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40032
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_RNO: lut40032
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0_i_o2_1: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    S_1: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40033
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40033 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
+
+  end lut40033;
+
+  architecture Structure of lut40033 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF2F7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40034
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40034 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
+
+  end lut40034;
+
+  architecture Structure of lut40034 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1032")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_51
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_51 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_51";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
+
+  end SLICE_51;
+
+  architecture Structure of SLICE_51 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMCLK_RNO_0: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMCLK_RNO: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40035
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40035 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
+
+  end lut40035;
+
+  architecture Structure of lut40035 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3B33")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40036
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40036 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
+
+  end lut40036;
+
+  architecture Structure of lut40036 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3210")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_52
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_52 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_52";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
+
+  end SLICE_52;
+
+  architecture Structure of SLICE_52 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    PHI2r3_RNITCN41: lut40035
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_RNO: lut40036
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMSDI: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40037
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40037 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
+
+  end lut40037;
+
+  architecture Structure of lut40037 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xACAC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_55
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_55 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_55";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
+
+  end SLICE_55;
+
+  architecture Structure of SLICE_55 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_4: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40038
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40038 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
+
+  end lut40038;
+
+  architecture Structure of lut40038 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40039
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40039 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
+
+  end lut40039;
+
+  architecture Structure of lut40039 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2C2C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_56
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_56 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_56";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
+
+  end SLICE_56;
+
+  architecture Structure of SLICE_56 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40039
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_11: lut40038
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_ens2_i_o2: lut40039
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40040
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40040 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
+
+  end lut40040;
+
+  architecture Structure of lut40040 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF7F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_57
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_57 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_57";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
+
+  end SLICE_57;
+
+  architecture Structure of SLICE_57 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG_3_u_0_a3_3: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    XOR8MEG: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40041
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40041 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
+
+  end lut40041;
+
+  architecture Structure of lut40041 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0101")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_58
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_58 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_58";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
+
+  end SLICE_58;
+
+  architecture Structure of SLICE_58 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_en_ss0_0_a2_0: lut40041
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    n8MEGEN_5_i_m2: lut40023
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    n8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40042
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40042 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
+
+  end lut40042;
+
+  architecture Structure of lut40042 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0BFB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40043
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40043 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
+
+  end lut40043;
+
+  architecture Structure of lut40043 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2232")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0044
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0044 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0044 : ENTITY IS TRUE;
+
+  end vmuxregsre0044;
+
+  architecture Structure of vmuxregsre0044 is
+    component FL1P3BX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3BX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_59
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_59 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_59";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
+
+  end SLICE_59;
+
+  architecture Structure of SLICE_59 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40042
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_0: lut40042
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCAS_RNO: lut40043
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCAS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40045
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40045 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
+
+  end lut40045;
+
+  architecture Structure of lut40045 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xE6EE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40046
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40046 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
+
+  end lut40046;
+
+  architecture Structure of lut40046 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3233")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_60
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_60 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_60";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
+
+  end SLICE_60;
+
+  architecture Structure of SLICE_60 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCS_RNO_0: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCS_RNO: lut40046
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40047
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40047 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
+
+  end lut40047;
+
+  architecture Structure of lut40047 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5400")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40048
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40048 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
+
+  end lut40048;
+
+  architecture Structure of lut40048 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5051")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_61
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_61 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_61";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
+
+  end SLICE_61;
+
+  architecture Structure of SLICE_61 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40047
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i_0: lut40047
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRRAS_RNO: lut40048
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRRAS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40049
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40049 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
+
+  end lut40049;
+
+  architecture Structure of lut40049 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40050
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40050 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
+
+  end lut40050;
+
+  architecture Structure of lut40050 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF4F7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_62
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_62 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_62";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
+
+  end SLICE_62;
+
+  architecture Structure of SLICE_62 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40050
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_0_sqmuxa_1_0_a3: lut40049
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRWE_RNO: lut40050
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRWE: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40051
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40051 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
+
+  end lut40051;
+
+  architecture Structure of lut40051 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40052
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40052 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
+
+  end lut40052;
+
+  architecture Structure of lut40052 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCEC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_63
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_63 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_63";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
+
+  end SLICE_63;
+
+  architecture Structure of SLICE_63 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40051
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40052
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_0_0_a3_0: lut40051
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRowColSel_0_0: lut40052
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRowColSel: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40053
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40053 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
+
+  end lut40053;
+
+  architecture Structure of lut40053 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40054
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40054 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
+
+  end lut40054;
+
+  architecture Structure of lut40054 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_64
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_64 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_64";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
+
+  end SLICE_64;
+
+  architecture Structure of SLICE_64 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40054
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS15_0_a2: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nUFMCS_s_0_N_5_i: lut40054
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nUFMCS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40055
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40055 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
+
+  end lut40055;
+
+  architecture Structure of lut40055 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40056
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40056 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
+
+  end lut40056;
+
+  architecture Structure of lut40056 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity nRWE_RNO_1_SLICE_65
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWE_RNO_1_SLICE_65 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
+
+  end nRWE_RNO_1_SLICE_65;
+
+  architecture Structure of nRWE_RNO_1_SLICE_65 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40055
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40056
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_1_SLICE_65_K1: lut40055
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
+    nRWE_RNO_1_GATE: lut40056
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
+    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
+      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
+                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
+                Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40057
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40057 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
+
+  end lut40057;
+
+  architecture Structure of lut40057 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0B0B")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_66
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_66 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_66";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
+
+  end SLICE_66;
+
+  architecture Structure of SLICE_66 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS_s_0_N_5_i_N_2L1: lut40057
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_a2_2_2: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40058
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40058 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
+
+  end lut40058;
+
+  architecture Structure of lut40058 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0059
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0059 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0059 : ENTITY IS TRUE;
+
+  end vmuxregsre0059;
+
+  architecture Structure of vmuxregsre0059 is
+    component FL1P3JY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3JY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_67
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_67 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_67";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
+
+  end SLICE_67;
+
+  architecture Structure of SLICE_67 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    CmdUFMCLK_1_sqmuxa_0_a2: lut40058
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG18_0_a2: lut40005
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_5: vmuxregsre0059
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_4: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40060
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40060 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
+
+  end lut40060;
+
+  architecture Structure of lut40060 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEAAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_68
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_68 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_68";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
+
+  end SLICE_68;
+
+  architecture Structure of SLICE_68 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2_0_1: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_14_i_0: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40061
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40061 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
+
+  end lut40061;
+
+  architecture Structure of lut40061 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0100")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_69
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_69 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_69";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
+
+  end SLICE_69;
+
+  architecture Structure of SLICE_69 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_13_i_a2_1: lut40061
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_0: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40062
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40062 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
+
+  end lut40062;
+
+  architecture Structure of lut40062 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8888")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_70
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_70 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_70";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
+
+  end SLICE_70;
+
+  architecture Structure of SLICE_70 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2: lut40062
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_71
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_71 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_71";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
+
+  end SLICE_71;
+
+  architecture Structure of SLICE_71 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_4: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2_0_10: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40063
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40063 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
+
+  end lut40063;
+
+  architecture Structure of lut40063 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFEFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40064
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40064 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
+
+  end lut40064;
+
+  architecture Structure of lut40064 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAAC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_72
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_72 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_72";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
+
+  end SLICE_72;
+
+  architecture Structure of SLICE_72 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0: lut40063
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_m2: lut40064
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_3: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_2: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40065
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40065 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
+
+  end lut40065;
+
+  architecture Structure of lut40065 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFF7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_73
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_73 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_73";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
+
+  end SLICE_73;
+
+  architecture Structure of SLICE_73 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0: lut40065
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_0_sqmuxa_0_o2: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdUFMCS: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CmdUFMCLK: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_74
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_74 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_74";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
+
+  end SLICE_74;
+
+  architecture Structure of SLICE_74 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    InitReady3_0_a2_3: lut40062
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady3_0_a2: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdUFMSDI: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40066
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40066 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
+
+  end lut40066;
+
+  architecture Structure of lut40066 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFDFD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_75
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_75 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_75";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
+
+  end SLICE_75;
+
+  architecture Structure of SLICE_75 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_o2_0: lut40066
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_4_u_i_a2_0: lut40041
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    CASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CASr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40067
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40067 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
+
+  end lut40067;
+
+  architecture Structure of lut40067 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0002")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_76
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_76 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_76";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
+
+  end SLICE_76;
+
+  architecture Structure of SLICE_76 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40067
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_4: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_4_0: lut40067
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40068
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40068 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
+
+  end lut40068;
+
+  architecture Structure of lut40068 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4444")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_77
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_77 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_77";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
+
+  end SLICE_77;
+
+  architecture Structure of SLICE_77 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40068
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_1: lut40068
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_5: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40069
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40069 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
+
+  end lut40069;
+
+  architecture Structure of lut40069 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7777")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_78
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_78 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_78";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
+
+  end SLICE_78;
+
+  architecture Structure of SLICE_78 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_o2: lut40069
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable17_0_a2_4: lut40058
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CBR_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CBR: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40070
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40070 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
+
+  end lut40070;
+
+  architecture Structure of lut40070 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_79
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_79 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_79";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
+
+  end SLICE_79;
+
+  architecture Structure of SLICE_79 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40070
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_2: lut40070
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRWE_RNO_0: lut40038
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40071
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40071 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
+
+  end lut40071;
+
+  architecture Structure of lut40071 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4101")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_80
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_80 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_80";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
+
+  end SLICE_80;
+
+  architecture Structure of SLICE_80 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40071
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_RNO_1: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRCAS_RNO_0: lut40071
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_9: vmuxregsre0059
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_8: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40072
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40072 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
+
+  end lut40072;
+
+  architecture Structure of lut40072 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_81
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_81 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_81";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
+
+  end SLICE_81;
+
+  architecture Structure of SLICE_81 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0_3: lut40072
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady3_0_a2_5: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    FWEr_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    FWEr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40073
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40073 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
+
+  end lut40073;
+
+  architecture Structure of lut40073 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40074
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40074 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
+
+  end lut40074;
+
+  architecture Structure of lut40074 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_82
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_82 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_82";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
+
+  end SLICE_82;
+
+  architecture Structure of SLICE_82 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40073
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdLEDEN_4_u_i_a2: lut40073
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_1_sqmuxa_0_a2: lut40074
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr3: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40075
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40075 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
+
+  end lut40075;
+
+  architecture Structure of lut40075 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7F7F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_83
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_83 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_83";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
+
+  end SLICE_83;
+
+  architecture Structure of SLICE_83 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40075
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_o2: lut40063
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready_0_sqmuxa_0_o2: lut40075
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RBA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RBA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_84
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_84 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_84";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
+
+  end SLICE_84;
+
+  architecture Structure of SLICE_84 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a2_4_2: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_a2_6: lut40061
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40076
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40076 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
+
+  end lut40076;
+
+  architecture Structure of lut40076 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0040")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_85
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_85 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_85";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
+
+  end SLICE_85;
+
+  architecture Structure of SLICE_85 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40076
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2_3: lut40076
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_Din_4: lut40053
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_86
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_86 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_86";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
+
+  end SLICE_86;
+
+  architecture Structure of SLICE_86 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQML: lut40069
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_9: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40077
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40077 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
+
+  end lut40077;
+
+  architecture Structure of lut40077 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3232")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_87
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_87 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_87";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
+
+  end SLICE_87;
+
+  architecture Structure of SLICE_87 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40077
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_RNO_0: lut40077
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un1_FS_13_i_a2_8: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40078
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40078 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
+
+  end lut40078;
+
+  architecture Structure of lut40078 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0808")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_88
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_88 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_88";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
+
+  end SLICE_88;
+
+  architecture Structure of SLICE_88 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40078
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_3: lut40078
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nCCAS_pad_RNI01SJ: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    RowA_7: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_6: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, 
+      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40079
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40079 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
+
+  end lut40079;
+
+  architecture Structure of lut40079 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBBBB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_89
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_89 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_89";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
+
+  end SLICE_89;
+
+  architecture Structure of SLICE_89 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40079
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQMH: lut40079
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_8: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40080
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40080 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
+
+  end lut40080;
+
+  architecture Structure of lut40080 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA8A8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_90
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_90 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_90";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
+
+  end SLICE_90;
+
+  architecture Structure of SLICE_90 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40080
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_CMDWR: lut40080
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_0: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_91
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_91 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_91";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
+
+  end SLICE_91;
+
+  architecture Structure of SLICE_91 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_7: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_1: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_92
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_92 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_92";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
+
+  end SLICE_92;
+
+  architecture Structure of SLICE_92 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_6: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_2: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_93
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_93 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_93";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
+
+  end SLICE_93;
+
+  architecture Structure of SLICE_93 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_5: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_3: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40081
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40081 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
+
+  end lut40081;
+
+  architecture Structure of lut40081 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1111")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_94
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_94 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_94";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
+
+  end SLICE_94;
+
+  architecture Structure of SLICE_94 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN_8_u_0_a2_1_s: lut40062
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    RA10: vmuxregsre0059
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf is
+    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+          PAD: out Std_logic; PADI: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
+
+  end mjiobuf;
+
+  architecture Structure of mjiobuf is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+    component OBW
+      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PADI, O=>Z);
+    INST2: OBW
+      port map (I=>I, T=>T, O=>PAD);
+  end Structure;
+
+-- entity RD_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_0_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD0 	: VitalDelayType := 0 ns;
+      tpw_RD0_posedge	: VitalDelayType := 0 ns;
+      tpw_RD0_negedge	: VitalDelayType := 0 ns;
+      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD0: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
+
+  end RD_0_B;
+
+  architecture Structure of RD_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD0_ipd 	: std_logic := 'X';
+    signal RD0_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_0: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
+                PADI=>RD0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD0_zd         	: std_logic := 'X';
+    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD0_RD0          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD0_ipd,
+        TestSignalName => "RD0",
+        Period => tperiod_RD0,
+        PulseWidthHigh => tpw_RD0_posedge,
+        PulseWidthLow => tpw_RD0_negedge,
+        PeriodData => periodcheckinfo_RD0,
+        Violation => tviol_RD0_RD0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD0_zd 	:= RD0_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
+                           PathDelay => tpd_RD0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD0,
+                           PathCondition => TRUE)),
+      GlitchData => RD0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0082
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0082 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0082 : ENTITY IS TRUE;
+
+  end mjiobuf0082;
+
+  architecture Structure of mjiobuf0082 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity Dout_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
+
+  end Dout_0_B;
+
+  architecture Structure of Dout_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout0_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_0: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
+    VARIABLE Dout0_zd         	: std_logic := 'X';
+    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout0_zd 	:= Dout0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout0,
+                           PathCondition => TRUE)),
+      GlitchData => Dout0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0083
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0083 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0083 : ENTITY IS TRUE;
+
+  end mjiobuf0083;
+
+  architecture Structure of mjiobuf0083 is
+    component IBPD
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPD
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity PHI2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity PHI2B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "PHI2B";
+
+      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_PHI2S 	: VitalDelayType := 0 ns;
+      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
+      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; PHI2S: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
+
+  end PHI2B;
+
+  architecture Structure of PHI2B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PHI2S_ipd 	: std_logic := 'X';
+
+    component mjiobuf0083
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    PHI2_pad: mjiobuf0083
+      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
+    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => PHI2S_ipd,
+        TestSignalName => "PHI2S",
+        Period => tperiod_PHI2S,
+        PulseWidthHigh => tpw_PHI2S_posedge,
+        PulseWidthLow => tpw_PHI2S_negedge,
+        PeriodData => periodcheckinfo_PHI2S,
+        Violation => tviol_PHI2S_PHI2S,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
+                           PathDelay => tpd_PHI2S_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0084
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0084 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0084 : ENTITY IS TRUE;
+
+  end mjiobuf0084;
+
+  architecture Structure of mjiobuf0084 is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity UFMSDOB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDOB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDOB";
+
+      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
+
+  end UFMSDOB;
+
+  architecture Structure of UFMSDOB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal UFMSDOS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    UFMSDO_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
+    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => UFMSDOS_ipd,
+        TestSignalName => "UFMSDOS",
+        Period => tperiod_UFMSDOS,
+        PulseWidthHigh => tpw_UFMSDOS_posedge,
+        PulseWidthLow => tpw_UFMSDOS_negedge,
+        PeriodData => periodcheckinfo_UFMSDOS,
+        Violation => tviol_UFMSDOS_UFMSDOS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
+                           PathDelay => tpd_UFMSDOS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0085
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0085 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0085 : ENTITY IS TRUE;
+
+  end mjiobuf0085;
+
+  architecture Structure of mjiobuf0085 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity UFMSDIB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDIB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDIB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
+
+  end UFMSDIB;
+
+  architecture Structure of UFMSDIB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMSDIS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMSDI_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
+    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
+    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMSDIS_zd 	:= UFMSDIS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMSDIS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMSDIS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity UFMCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMCLKB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
+
+  end UFMCLKB;
+
+  architecture Structure of UFMCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMCLKS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMCLK_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
+    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
+    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMCLKS_zd 	:= UFMCLKS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMCLKS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMCLKS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nUFMCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nUFMCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nUFMCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
+
+  end nUFMCSB;
+
+  architecture Structure of nUFMCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nUFMCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nUFMCS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
+    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
+    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nUFMCSS_zd 	:= nUFMCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nUFMCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nUFMCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMLB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMLB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMLB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
+
+  end RDQMLB;
+
+  architecture Structure of RDQMLB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMLS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQML_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
+    VARIABLE RDQMLS_zd         	: std_logic := 'X';
+    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMLS_zd 	:= RDQMLS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMLS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMLS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMHB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMHB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMHB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
+
+  end RDQMHB;
+
+  architecture Structure of RDQMHB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMHS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQMH_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
+    VARIABLE RDQMHS_zd         	: std_logic := 'X';
+    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMHS_zd 	:= RDQMHS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMHS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMHS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
+
+  end nRCASB;
+
+  architecture Structure of nRCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCASS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCAS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
+    VARIABLE nRCASS_zd         	: std_logic := 'X';
+    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCASS_zd 	:= nRCASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRRASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRRASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
+
+  end nRRASB;
+
+  architecture Structure of nRRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRRASS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRRAS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
+    VARIABLE nRRASS_zd         	: std_logic := 'X';
+    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRRASS_zd 	:= nRRASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRRASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRRASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRWES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
+
+  end nRWEB;
+
+  architecture Structure of nRWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRWES_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRWE_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRWES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
+    VARIABLE nRWES_zd         	: std_logic := 'X';
+    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRWES_zd 	:= nRWES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRWES,
+                           PathCondition => TRUE)),
+      GlitchData => nRWES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCKEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCKEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCKEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RCKES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
+
+  end RCKEB;
+
+  architecture Structure of RCKEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RCKES_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RCKE_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RCKES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
+    VARIABLE RCKES_zd         	: std_logic := 'X';
+    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RCKES_zd 	:= RCKES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RCKES,
+                           PathCondition => TRUE)),
+      GlitchData => RCKES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCLKB";
+
+      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RCLKS 	: VitalDelayType := 0 ns;
+      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
+      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; RCLKS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
+
+  end RCLKB;
+
+  architecture Structure of RCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal RCLKS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    RCLK_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
+    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RCLKS_ipd,
+        TestSignalName => "RCLKS",
+        Period => tperiod_RCLKS,
+        PulseWidthHigh => tpw_RCLKS_posedge,
+        PulseWidthLow => tpw_RCLKS_negedge,
+        PeriodData => periodcheckinfo_RCLKS,
+        Violation => tviol_RCLKS_RCLKS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
+                           PathDelay => tpd_RCLKS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
+
+  end nRCSB;
+
+  architecture Structure of nRCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
+    VARIABLE nRCSS_zd         	: std_logic := 'X';
+    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCSS_zd 	:= nRCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_7_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD7 	: VitalDelayType := 0 ns;
+      tpw_RD7_posedge	: VitalDelayType := 0 ns;
+      tpw_RD7_negedge	: VitalDelayType := 0 ns;
+      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD7: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
+
+  end RD_7_B;
+
+  architecture Structure of RD_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD7_ipd 	: std_logic := 'X';
+    signal RD7_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_7: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
+                PADI=>RD7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD7_zd         	: std_logic := 'X';
+    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD7_RD7          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD7_ipd,
+        TestSignalName => "RD7",
+        Period => tperiod_RD7,
+        PulseWidthHigh => tpw_RD7_posedge,
+        PulseWidthLow => tpw_RD7_negedge,
+        PeriodData => periodcheckinfo_RD7,
+        Violation => tviol_RD7_RD7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD7_zd 	:= RD7_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
+                           PathDelay => tpd_RD7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD7,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD7,
+                           PathCondition => TRUE)),
+      GlitchData => RD7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_6_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD6 	: VitalDelayType := 0 ns;
+      tpw_RD6_posedge	: VitalDelayType := 0 ns;
+      tpw_RD6_negedge	: VitalDelayType := 0 ns;
+      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD6: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
+
+  end RD_6_B;
+
+  architecture Structure of RD_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD6_ipd 	: std_logic := 'X';
+    signal RD6_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_6: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
+                PADI=>RD6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD6_zd         	: std_logic := 'X';
+    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD6_RD6          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD6_ipd,
+        TestSignalName => "RD6",
+        Period => tperiod_RD6,
+        PulseWidthHigh => tpw_RD6_posedge,
+        PulseWidthLow => tpw_RD6_negedge,
+        PeriodData => periodcheckinfo_RD6,
+        Violation => tviol_RD6_RD6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD6_zd 	:= RD6_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
+                           PathDelay => tpd_RD6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD6,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD6,
+                           PathCondition => TRUE)),
+      GlitchData => RD6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_5_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD5 	: VitalDelayType := 0 ns;
+      tpw_RD5_posedge	: VitalDelayType := 0 ns;
+      tpw_RD5_negedge	: VitalDelayType := 0 ns;
+      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD5: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
+
+  end RD_5_B;
+
+  architecture Structure of RD_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD5_ipd 	: std_logic := 'X';
+    signal RD5_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_5: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
+                PADI=>RD5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD5_zd         	: std_logic := 'X';
+    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD5_RD5          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD5_ipd,
+        TestSignalName => "RD5",
+        Period => tperiod_RD5,
+        PulseWidthHigh => tpw_RD5_posedge,
+        PulseWidthLow => tpw_RD5_negedge,
+        PeriodData => periodcheckinfo_RD5,
+        Violation => tviol_RD5_RD5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD5_zd 	:= RD5_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
+                           PathDelay => tpd_RD5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD5,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD5,
+                           PathCondition => TRUE)),
+      GlitchData => RD5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_4_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD4 	: VitalDelayType := 0 ns;
+      tpw_RD4_posedge	: VitalDelayType := 0 ns;
+      tpw_RD4_negedge	: VitalDelayType := 0 ns;
+      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD4: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
+
+  end RD_4_B;
+
+  architecture Structure of RD_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD4_ipd 	: std_logic := 'X';
+    signal RD4_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_4: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
+                PADI=>RD4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD4_zd         	: std_logic := 'X';
+    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD4_RD4          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD4_ipd,
+        TestSignalName => "RD4",
+        Period => tperiod_RD4,
+        PulseWidthHigh => tpw_RD4_posedge,
+        PulseWidthLow => tpw_RD4_negedge,
+        PeriodData => periodcheckinfo_RD4,
+        Violation => tviol_RD4_RD4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD4_zd 	:= RD4_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
+                           PathDelay => tpd_RD4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD4,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD4,
+                           PathCondition => TRUE)),
+      GlitchData => RD4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_3_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD3 	: VitalDelayType := 0 ns;
+      tpw_RD3_posedge	: VitalDelayType := 0 ns;
+      tpw_RD3_negedge	: VitalDelayType := 0 ns;
+      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD3: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
+
+  end RD_3_B;
+
+  architecture Structure of RD_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD3_ipd 	: std_logic := 'X';
+    signal RD3_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_3: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
+                PADI=>RD3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD3_zd         	: std_logic := 'X';
+    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD3_RD3          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD3_ipd,
+        TestSignalName => "RD3",
+        Period => tperiod_RD3,
+        PulseWidthHigh => tpw_RD3_posedge,
+        PulseWidthLow => tpw_RD3_negedge,
+        PeriodData => periodcheckinfo_RD3,
+        Violation => tviol_RD3_RD3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD3_zd 	:= RD3_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
+                           PathDelay => tpd_RD3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD3,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD3,
+                           PathCondition => TRUE)),
+      GlitchData => RD3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_2_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD2 	: VitalDelayType := 0 ns;
+      tpw_RD2_posedge	: VitalDelayType := 0 ns;
+      tpw_RD2_negedge	: VitalDelayType := 0 ns;
+      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD2: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
+
+  end RD_2_B;
+
+  architecture Structure of RD_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD2_ipd 	: std_logic := 'X';
+    signal RD2_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_2: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
+                PADI=>RD2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD2_zd         	: std_logic := 'X';
+    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD2_RD2          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD2_ipd,
+        TestSignalName => "RD2",
+        Period => tperiod_RD2,
+        PulseWidthHigh => tpw_RD2_posedge,
+        PulseWidthLow => tpw_RD2_negedge,
+        PeriodData => periodcheckinfo_RD2,
+        Violation => tviol_RD2_RD2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD2_zd 	:= RD2_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
+                           PathDelay => tpd_RD2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD2,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD2,
+                           PathCondition => TRUE)),
+      GlitchData => RD2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_1_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD1 	: VitalDelayType := 0 ns;
+      tpw_RD1_posedge	: VitalDelayType := 0 ns;
+      tpw_RD1_negedge	: VitalDelayType := 0 ns;
+      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD1: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
+
+  end RD_1_B;
+
+  architecture Structure of RD_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD1_ipd 	: std_logic := 'X';
+    signal RD1_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_1: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
+                PADI=>RD1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD1_zd         	: std_logic := 'X';
+    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD1_RD1          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD1_ipd,
+        TestSignalName => "RD1",
+        Period => tperiod_RD1,
+        PulseWidthHigh => tpw_RD1_posedge,
+        PulseWidthLow => tpw_RD1_negedge,
+        PeriodData => periodcheckinfo_RD1,
+        Violation => tviol_RD1_RD1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD1_zd 	:= RD1_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
+                           PathDelay => tpd_RD1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD1,
+                           PathCondition => TRUE)),
+      GlitchData => RD1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_11_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
+
+  end RA_11_B;
+
+  architecture Structure of RA_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA11_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_11: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
+    VARIABLE RA11_zd         	: std_logic := 'X';
+    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA11_zd 	:= RA11_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA11,
+                           PathCondition => TRUE)),
+      GlitchData => RA11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_10_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
+
+  end RA_10_B;
+
+  architecture Structure of RA_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA10_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_10: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
+    VARIABLE RA10_zd         	: std_logic := 'X';
+    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA10_zd 	:= RA10_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA10,
+                           PathCondition => TRUE)),
+      GlitchData => RA10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
+
+  end RA_9_B;
+
+  architecture Structure of RA_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA9_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_9: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
+    VARIABLE RA9_zd         	: std_logic := 'X';
+    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA9_zd 	:= RA9_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA9,
+                           PathCondition => TRUE)),
+      GlitchData => RA9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
+
+  end RA_8_B;
+
+  architecture Structure of RA_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA8_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_8: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
+    VARIABLE RA8_zd         	: std_logic := 'X';
+    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA8_zd 	:= RA8_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA8,
+                           PathCondition => TRUE)),
+      GlitchData => RA8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
+
+  end RA_7_B;
+
+  architecture Structure of RA_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA7_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_7: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
+    VARIABLE RA7_zd         	: std_logic := 'X';
+    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA7_zd 	:= RA7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA7,
+                           PathCondition => TRUE)),
+      GlitchData => RA7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
+
+  end RA_6_B;
+
+  architecture Structure of RA_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA6_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_6: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
+    VARIABLE RA6_zd         	: std_logic := 'X';
+    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA6_zd 	:= RA6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA6,
+                           PathCondition => TRUE)),
+      GlitchData => RA6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
+
+  end RA_5_B;
+
+  architecture Structure of RA_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA5_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_5: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
+    VARIABLE RA5_zd         	: std_logic := 'X';
+    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA5_zd 	:= RA5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA5,
+                           PathCondition => TRUE)),
+      GlitchData => RA5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
+
+  end RA_4_B;
+
+  architecture Structure of RA_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA4_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_4: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
+    VARIABLE RA4_zd         	: std_logic := 'X';
+    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA4_zd 	:= RA4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA4,
+                           PathCondition => TRUE)),
+      GlitchData => RA4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
+
+  end RA_3_B;
+
+  architecture Structure of RA_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA3_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_3: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
+    VARIABLE RA3_zd         	: std_logic := 'X';
+    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA3_zd 	:= RA3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA3,
+                           PathCondition => TRUE)),
+      GlitchData => RA3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
+
+  end RA_2_B;
+
+  architecture Structure of RA_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA2_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_2: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
+    VARIABLE RA2_zd         	: std_logic := 'X';
+    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA2_zd 	:= RA2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA2,
+                           PathCondition => TRUE)),
+      GlitchData => RA2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
+
+  end RA_1_B;
+
+  architecture Structure of RA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA1_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_1: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
+    VARIABLE RA1_zd         	: std_logic := 'X';
+    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA1_zd 	:= RA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA1,
+                           PathCondition => TRUE)),
+      GlitchData => RA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
+
+  end RA_0_B;
+
+  architecture Structure of RA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA0_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_0: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
+    VARIABLE RA0_zd         	: std_logic := 'X';
+    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA0_zd 	:= RA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA0,
+                           PathCondition => TRUE)),
+      GlitchData => RA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
+
+  end RBA_1_B;
+
+  architecture Structure of RBA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA1_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_1: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RBA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
+    VARIABLE RBA1_zd         	: std_logic := 'X';
+    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA1_zd 	:= RBA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA1,
+                           PathCondition => TRUE)),
+      GlitchData => RBA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
+
+  end RBA_0_B;
+
+  architecture Structure of RBA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA0_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_0: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RBA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
+    VARIABLE RBA0_zd         	: std_logic := 'X';
+    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA0_zd 	:= RBA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA0,
+                           PathCondition => TRUE)),
+      GlitchData => RBA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0086
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0086 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0086 : ENTITY IS TRUE;
+
+  end mjiobuf0086;
+
+  architecture Structure of mjiobuf0086 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity LEDB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity LEDB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LEDB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; LEDS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
+
+  end LEDB;
+
+  architecture Structure of LEDB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal LEDS_out 	: std_logic := 'X';
+
+    component mjiobuf0086
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    LED_pad: mjiobuf0086
+      port map (I=>PADDO_ipd, PAD=>LEDS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
+    VARIABLE LEDS_zd         	: std_logic := 'X';
+    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    LEDS_zd 	:= LEDS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_LEDS,
+                           PathCondition => TRUE)),
+      GlitchData => LEDS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nFWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nFWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nFWEB";
+
+      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nFWES 	: VitalDelayType := 0 ns;
+      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
+      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nFWES: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
+
+  end nFWEB;
+
+  architecture Structure of nFWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nFWES_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nFWE_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
+    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nFWES_ipd,
+        TestSignalName => "nFWES",
+        Period => tperiod_nFWES,
+        PulseWidthHigh => tpw_nFWES_posedge,
+        PulseWidthLow => tpw_nFWES_negedge,
+        PeriodData => periodcheckinfo_nFWES,
+        Violation => tviol_nFWES_nFWES,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
+                           PathDelay => tpd_nFWES_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0087
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0087 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0087 : ENTITY IS TRUE;
+
+  end mjiobuf0087;
+
+  architecture Structure of mjiobuf0087 is
+    component IBPU
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPU
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity nCRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCRASB";
+
+      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCRASS 	: VitalDelayType := 0 ns;
+      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCRASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
+
+  end nCRASB;
+
+  architecture Structure of nCRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCRASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0087
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCRAS_pad: mjiobuf0087
+      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCRASS_ipd,
+        TestSignalName => "nCRASS",
+        Period => tperiod_nCRASS,
+        PulseWidthHigh => tpw_nCRASS_posedge,
+        PulseWidthLow => tpw_nCRASS_negedge,
+        PeriodData => periodcheckinfo_nCRASS,
+        Violation => tviol_nCRASS_nCRASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
+                           PathDelay => tpd_nCRASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nCCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCCASB";
+
+      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCCASS 	: VitalDelayType := 0 ns;
+      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCCASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
+
+  end nCCASB;
+
+  architecture Structure of nCCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCCASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0087
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCCAS_pad: mjiobuf0087
+      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCCASS_ipd,
+        TestSignalName => "nCCASS",
+        Period => tperiod_nCCASS,
+        PulseWidthHigh => tpw_nCCASS_posedge,
+        PulseWidthLow => tpw_nCCASS_negedge,
+        PeriodData => periodcheckinfo_nCCASS,
+        Violation => tviol_nCCASS_nCCASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
+                           PathDelay => tpd_nCCASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
+
+  end Dout_7_B;
+
+  architecture Structure of Dout_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout7_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_7: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
+    VARIABLE Dout7_zd         	: std_logic := 'X';
+    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout7_zd 	:= Dout7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout7,
+                           PathCondition => TRUE)),
+      GlitchData => Dout7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
+
+  end Dout_6_B;
+
+  architecture Structure of Dout_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout6_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_6: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
+    VARIABLE Dout6_zd         	: std_logic := 'X';
+    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout6_zd 	:= Dout6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout6,
+                           PathCondition => TRUE)),
+      GlitchData => Dout6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
+
+  end Dout_5_B;
+
+  architecture Structure of Dout_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout5_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_5: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
+    VARIABLE Dout5_zd         	: std_logic := 'X';
+    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout5_zd 	:= Dout5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout5,
+                           PathCondition => TRUE)),
+      GlitchData => Dout5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
+
+  end Dout_4_B;
+
+  architecture Structure of Dout_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout4_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_4: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
+    VARIABLE Dout4_zd         	: std_logic := 'X';
+    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout4_zd 	:= Dout4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout4,
+                           PathCondition => TRUE)),
+      GlitchData => Dout4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
+
+  end Dout_3_B;
+
+  architecture Structure of Dout_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout3_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_3: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
+    VARIABLE Dout3_zd         	: std_logic := 'X';
+    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout3_zd 	:= Dout3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout3,
+                           PathCondition => TRUE)),
+      GlitchData => Dout3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
+
+  end Dout_2_B;
+
+  architecture Structure of Dout_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout2_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_2: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
+    VARIABLE Dout2_zd         	: std_logic := 'X';
+    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout2_zd 	:= Dout2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout2,
+                           PathCondition => TRUE)),
+      GlitchData => Dout2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
+
+  end Dout_1_B;
+
+  architecture Structure of Dout_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout1_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_1: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
+    VARIABLE Dout1_zd         	: std_logic := 'X';
+    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout1_zd 	:= Dout1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout1,
+                           PathCondition => TRUE)),
+      GlitchData => Dout1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_7_B";
+
+      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din7 	: VitalDelayType := 0 ns;
+      tpw_Din7_posedge	: VitalDelayType := 0 ns;
+      tpw_Din7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
+
+  end Din_7_B;
+
+  architecture Structure of Din_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_7: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din7_Din7          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din7_ipd,
+        TestSignalName => "Din7",
+        Period => tperiod_Din7,
+        PulseWidthHigh => tpw_Din7_posedge,
+        PulseWidthLow => tpw_Din7_negedge,
+        PeriodData => periodcheckinfo_Din7,
+        Violation => tviol_Din7_Din7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
+                           PathDelay => tpd_Din7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_6_B";
+
+      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din6 	: VitalDelayType := 0 ns;
+      tpw_Din6_posedge	: VitalDelayType := 0 ns;
+      tpw_Din6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
+
+  end Din_6_B;
+
+  architecture Structure of Din_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_6: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din6_Din6          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din6_ipd,
+        TestSignalName => "Din6",
+        Period => tperiod_Din6,
+        PulseWidthHigh => tpw_Din6_posedge,
+        PulseWidthLow => tpw_Din6_negedge,
+        PeriodData => periodcheckinfo_Din6,
+        Violation => tviol_Din6_Din6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
+                           PathDelay => tpd_Din6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_5_B";
+
+      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din5 	: VitalDelayType := 0 ns;
+      tpw_Din5_posedge	: VitalDelayType := 0 ns;
+      tpw_Din5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
+
+  end Din_5_B;
+
+  architecture Structure of Din_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_5: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din5_Din5          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din5_ipd,
+        TestSignalName => "Din5",
+        Period => tperiod_Din5,
+        PulseWidthHigh => tpw_Din5_posedge,
+        PulseWidthLow => tpw_Din5_negedge,
+        PeriodData => periodcheckinfo_Din5,
+        Violation => tviol_Din5_Din5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
+                           PathDelay => tpd_Din5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_4_B";
+
+      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din4 	: VitalDelayType := 0 ns;
+      tpw_Din4_posedge	: VitalDelayType := 0 ns;
+      tpw_Din4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
+
+  end Din_4_B;
+
+  architecture Structure of Din_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_4: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din4_Din4          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din4_ipd,
+        TestSignalName => "Din4",
+        Period => tperiod_Din4,
+        PulseWidthHigh => tpw_Din4_posedge,
+        PulseWidthLow => tpw_Din4_negedge,
+        PeriodData => periodcheckinfo_Din4,
+        Violation => tviol_Din4_Din4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
+                           PathDelay => tpd_Din4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_3_B";
+
+      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din3 	: VitalDelayType := 0 ns;
+      tpw_Din3_posedge	: VitalDelayType := 0 ns;
+      tpw_Din3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
+
+  end Din_3_B;
+
+  architecture Structure of Din_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_3: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din3_Din3          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din3_ipd,
+        TestSignalName => "Din3",
+        Period => tperiod_Din3,
+        PulseWidthHigh => tpw_Din3_posedge,
+        PulseWidthLow => tpw_Din3_negedge,
+        PeriodData => periodcheckinfo_Din3,
+        Violation => tviol_Din3_Din3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
+                           PathDelay => tpd_Din3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_2_B";
+
+      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din2 	: VitalDelayType := 0 ns;
+      tpw_Din2_posedge	: VitalDelayType := 0 ns;
+      tpw_Din2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
+
+  end Din_2_B;
+
+  architecture Structure of Din_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_2: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din2_Din2          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din2_ipd,
+        TestSignalName => "Din2",
+        Period => tperiod_Din2,
+        PulseWidthHigh => tpw_Din2_posedge,
+        PulseWidthLow => tpw_Din2_negedge,
+        PeriodData => periodcheckinfo_Din2,
+        Violation => tviol_Din2_Din2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
+                           PathDelay => tpd_Din2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_1_B";
+
+      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din1 	: VitalDelayType := 0 ns;
+      tpw_Din1_posedge	: VitalDelayType := 0 ns;
+      tpw_Din1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
+
+  end Din_1_B;
+
+  architecture Structure of Din_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din1_Din1          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din1_ipd,
+        TestSignalName => "Din1",
+        Period => tperiod_Din1,
+        PulseWidthHigh => tpw_Din1_posedge,
+        PulseWidthLow => tpw_Din1_negedge,
+        PeriodData => periodcheckinfo_Din1,
+        Violation => tviol_Din1_Din1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
+                           PathDelay => tpd_Din1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_0_B";
+
+      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din0 	: VitalDelayType := 0 ns;
+      tpw_Din0_posedge	: VitalDelayType := 0 ns;
+      tpw_Din0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
+
+  end Din_0_B;
+
+  architecture Structure of Din_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din0_Din0          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din0_ipd,
+        TestSignalName => "Din0",
+        Period => tperiod_Din0,
+        PulseWidthHigh => tpw_Din0_posedge,
+        PulseWidthLow => tpw_Din0_negedge,
+        PeriodData => periodcheckinfo_Din0,
+        Violation => tviol_Din0_Din0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
+                           PathDelay => tpd_Din0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_1_B";
+
+      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW1 	: VitalDelayType := 0 ns;
+      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
+
+  end CROW_1_B;
+
+  architecture Structure of CROW_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW1_ipd,
+        TestSignalName => "CROW1",
+        Period => tperiod_CROW1,
+        PulseWidthHigh => tpw_CROW1_posedge,
+        PulseWidthLow => tpw_CROW1_negedge,
+        PeriodData => periodcheckinfo_CROW1,
+        Violation => tviol_CROW1_CROW1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
+                           PathDelay => tpd_CROW1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_0_B";
+
+      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW0 	: VitalDelayType := 0 ns;
+      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
+
+  end CROW_0_B;
+
+  architecture Structure of CROW_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW0_ipd,
+        TestSignalName => "CROW0",
+        Period => tperiod_CROW0,
+        PulseWidthHigh => tpw_CROW0_posedge,
+        PulseWidthLow => tpw_CROW0_negedge,
+        PeriodData => periodcheckinfo_CROW0,
+        Violation => tviol_CROW0_CROW0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
+                           PathDelay => tpd_CROW0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_9_B";
+
+      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin9 	: VitalDelayType := 0 ns;
+      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin9: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
+
+  end MAin_9_B;
+
+  architecture Structure of MAin_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin9_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_9: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin9_ipd,
+        TestSignalName => "MAin9",
+        Period => tperiod_MAin9,
+        PulseWidthHigh => tpw_MAin9_posedge,
+        PulseWidthLow => tpw_MAin9_negedge,
+        PeriodData => periodcheckinfo_MAin9,
+        Violation => tviol_MAin9_MAin9,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
+                           PathDelay => tpd_MAin9_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_8_B";
+
+      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin8 	: VitalDelayType := 0 ns;
+      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin8: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
+
+  end MAin_8_B;
+
+  architecture Structure of MAin_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin8_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_8: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin8_ipd,
+        TestSignalName => "MAin8",
+        Period => tperiod_MAin8,
+        PulseWidthHigh => tpw_MAin8_posedge,
+        PulseWidthLow => tpw_MAin8_negedge,
+        PeriodData => periodcheckinfo_MAin8,
+        Violation => tviol_MAin8_MAin8,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
+                           PathDelay => tpd_MAin8_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_7_B";
+
+      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin7 	: VitalDelayType := 0 ns;
+      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
+
+  end MAin_7_B;
+
+  architecture Structure of MAin_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_7: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin7_ipd,
+        TestSignalName => "MAin7",
+        Period => tperiod_MAin7,
+        PulseWidthHigh => tpw_MAin7_posedge,
+        PulseWidthLow => tpw_MAin7_negedge,
+        PeriodData => periodcheckinfo_MAin7,
+        Violation => tviol_MAin7_MAin7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
+                           PathDelay => tpd_MAin7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_6_B";
+
+      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin6 	: VitalDelayType := 0 ns;
+      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
+
+  end MAin_6_B;
+
+  architecture Structure of MAin_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_6: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin6_ipd,
+        TestSignalName => "MAin6",
+        Period => tperiod_MAin6,
+        PulseWidthHigh => tpw_MAin6_posedge,
+        PulseWidthLow => tpw_MAin6_negedge,
+        PeriodData => periodcheckinfo_MAin6,
+        Violation => tviol_MAin6_MAin6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
+                           PathDelay => tpd_MAin6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_5_B";
+
+      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin5 	: VitalDelayType := 0 ns;
+      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
+
+  end MAin_5_B;
+
+  architecture Structure of MAin_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_5: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin5_ipd,
+        TestSignalName => "MAin5",
+        Period => tperiod_MAin5,
+        PulseWidthHigh => tpw_MAin5_posedge,
+        PulseWidthLow => tpw_MAin5_negedge,
+        PeriodData => periodcheckinfo_MAin5,
+        Violation => tviol_MAin5_MAin5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
+                           PathDelay => tpd_MAin5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_4_B";
+
+      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin4 	: VitalDelayType := 0 ns;
+      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
+
+  end MAin_4_B;
+
+  architecture Structure of MAin_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_4: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin4_ipd,
+        TestSignalName => "MAin4",
+        Period => tperiod_MAin4,
+        PulseWidthHigh => tpw_MAin4_posedge,
+        PulseWidthLow => tpw_MAin4_negedge,
+        PeriodData => periodcheckinfo_MAin4,
+        Violation => tviol_MAin4_MAin4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
+                           PathDelay => tpd_MAin4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_3_B";
+
+      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin3 	: VitalDelayType := 0 ns;
+      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
+
+  end MAin_3_B;
+
+  architecture Structure of MAin_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_3: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin3_ipd,
+        TestSignalName => "MAin3",
+        Period => tperiod_MAin3,
+        PulseWidthHigh => tpw_MAin3_posedge,
+        PulseWidthLow => tpw_MAin3_negedge,
+        PeriodData => periodcheckinfo_MAin3,
+        Violation => tviol_MAin3_MAin3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
+                           PathDelay => tpd_MAin3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_2_B";
+
+      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin2 	: VitalDelayType := 0 ns;
+      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
+
+  end MAin_2_B;
+
+  architecture Structure of MAin_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_2: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin2_ipd,
+        TestSignalName => "MAin2",
+        Period => tperiod_MAin2,
+        PulseWidthHigh => tpw_MAin2_posedge,
+        PulseWidthLow => tpw_MAin2_negedge,
+        PeriodData => periodcheckinfo_MAin2,
+        Violation => tviol_MAin2_MAin2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
+                           PathDelay => tpd_MAin2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_1_B";
+
+      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin1 	: VitalDelayType := 0 ns;
+      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
+
+  end MAin_1_B;
+
+  architecture Structure of MAin_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin1_ipd,
+        TestSignalName => "MAin1",
+        Period => tperiod_MAin1,
+        PulseWidthHigh => tpw_MAin1_posedge,
+        PulseWidthLow => tpw_MAin1_negedge,
+        PeriodData => periodcheckinfo_MAin1,
+        Violation => tviol_MAin1_MAin1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
+                           PathDelay => tpd_MAin1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_0_B";
+
+      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin0 	: VitalDelayType := 0 ns;
+      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
+
+  end MAin_0_B;
+
+  architecture Structure of MAin_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin0_ipd,
+        TestSignalName => "MAin0",
+        Period => tperiod_MAin0,
+        PulseWidthHigh => tpw_MAin0_posedge,
+        PulseWidthLow => tpw_MAin0_negedge,
+        PeriodData => periodcheckinfo_MAin0,
+        Violation => tviol_MAin0_MAin0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
+                           PathDelay => tpd_MAin0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RAM2GS
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RAM2GS is
+    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
+          CROW: in Std_logic_vector (1 downto 0); 
+          Din: in Std_logic_vector (7 downto 0); 
+          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
+          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
+          RBA: out Std_logic_vector (1 downto 0); 
+          RA: out Std_logic_vector (11 downto 0); 
+          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
+          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
+          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
+          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
+          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
+
+
+
+  end RAM2GS;
+
+  architecture Structure of RAM2GS is
+    signal FS_1: Std_logic;
+    signal FS_0: Std_logic;
+    signal RCLK_c: Std_logic;
+    signal FS_cry_1: Std_logic;
+    signal FS_17: Std_logic;
+    signal FS_16: Std_logic;
+    signal FS_cry_15: Std_logic;
+    signal FS_15: Std_logic;
+    signal FS_14: Std_logic;
+    signal FS_cry_13: Std_logic;
+    signal FS_13: Std_logic;
+    signal FS_12: Std_logic;
+    signal FS_cry_11: Std_logic;
+    signal FS_11: Std_logic;
+    signal FS_10: Std_logic;
+    signal FS_cry_9: Std_logic;
+    signal FS_9: Std_logic;
+    signal FS_8: Std_logic;
+    signal FS_cry_7: Std_logic;
+    signal FS_7: Std_logic;
+    signal FS_6: Std_logic;
+    signal FS_cry_5: Std_logic;
+    signal FS_5: Std_logic;
+    signal FS_4: Std_logic;
+    signal FS_cry_3: Std_logic;
+    signal FS_3: Std_logic;
+    signal FS_2: Std_logic;
+    signal N_147: Std_logic;
+    signal MAin_c_0: Std_logic;
+    signal CmdEnable17_0_a2_4: Std_logic;
+    signal CmdEnable17_0_a2_3: Std_logic;
+    signal CmdEnable16: Std_logic;
+    signal CmdEnable17: Std_logic;
+    signal C1WR_0_a2: Std_logic;
+    signal ADSubmitted: Std_logic;
+    signal ADSubmitted_r: Std_logic;
+    signal PHI2_c: Std_logic;
+    signal CmdEnable16_0_a2_5: Std_logic;
+    signal CmdEnable16_0_a2_4: Std_logic;
+    signal MAin_c_1: Std_logic;
+    signal C1Submitted: Std_logic;
+    signal C1Submitted_RNO: Std_logic;
+    signal S_1: Std_logic;
+    signal RASr2: Std_logic;
+    signal IS_3: Std_logic;
+    signal CO0: Std_logic;
+    signal N_177_i: Std_logic;
+    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
+    signal CmdEnable: Std_logic;
+    signal un1_CMDWR: Std_logic;
+    signal CmdEnable_s: Std_logic;
+    signal N_128: Std_logic;
+    signal Din_c_5: Std_logic;
+    signal Din_c_3: Std_logic;
+    signal N_152: Std_logic;
+    signal N_133: Std_logic;
+    signal N_132: Std_logic;
+    signal LEDEN: Std_logic;
+    signal N_21_i: Std_logic;
+    signal XOR8MEG18: Std_logic;
+    signal CmdLEDEN: Std_logic;
+    signal PHI2r3: Std_logic;
+    signal PHI2r2: Std_logic;
+    signal InitReady: Std_logic;
+    signal CmdSubmitted: Std_logic;
+    signal CmdSubmitted_1_sqmuxa: Std_logic;
+    signal N_460_0: Std_logic;
+    signal N_136: Std_logic;
+    signal N_43: Std_logic;
+    signal Cmdn8MEGEN: Std_logic;
+    signal CmdEnable16_4: Std_logic;
+    signal n8MEGEN: Std_logic;
+    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
+    signal N_19_i: Std_logic;
+    signal nRRAS_5_u_i_0: Std_logic;
+    signal N_160: Std_logic;
+    signal N_155: Std_logic;
+    signal IS_0: Std_logic;
+    signal Ready: Std_logic;
+    signal N_64_i_i: Std_logic;
+    signal N_24: Std_logic;
+    signal IS_2: Std_logic;
+    signal IS_1: Std_logic;
+    signal N_60_i_i: Std_logic;
+    signal N_56_i: Std_logic;
+    signal N_159_i: Std_logic;
+    signal N_159: Std_logic;
+    signal N_61_i_i: Std_logic;
+    signal RA10s_i: Std_logic;
+    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
+    signal N_126: Std_logic;
+    signal N_51: Std_logic;
+    signal InitReady3: Std_logic;
+    signal N_461_0: Std_logic;
+    signal UFMSDI_ens2_i_a0: Std_logic;
+    signal nCRAS_c: Std_logic;
+    signal CBR: Std_logic;
+    signal UFMSDO_c: Std_logic;
+    signal N_70: Std_logic;
+    signal N_33: Std_logic;
+    signal LED_c: Std_logic;
+    signal un1_Din_4: Std_logic;
+    signal XOR8MEG: Std_logic;
+    signal Din_c_6: Std_logic;
+    signal RA11_2: Std_logic;
+    signal Ready_fast: Std_logic;
+    signal RA_c_11: Std_logic;
+    signal N_171: Std_logic;
+    signal FWEr_fast: Std_logic;
+    signal CASr2: Std_logic;
+    signal RCKEEN_8_u_1: Std_logic;
+    signal RCKEEN_8_u_0_0: Std_logic;
+    signal RCKEEN_8: Std_logic;
+    signal PHI2r: Std_logic;
+    signal RCKEEN: Std_logic;
+    signal RASr3: Std_logic;
+    signal RASr: Std_logic;
+    signal RCKE_2: Std_logic;
+    signal RCKE_c: Std_logic;
+    signal m18_0_a3_3: Std_logic;
+    signal S_0_i_o2_1: Std_logic;
+    signal N_165: Std_logic;
+    signal N_462_0: Std_logic;
+    signal Ready_0_sqmuxa: Std_logic;
+    signal N_463_0: Std_logic;
+    signal nRRAS_0_sqmuxa: Std_logic;
+    signal N_129: Std_logic;
+    signal UFMCLK_r_i_a2_2_2: Std_logic;
+    signal CmdUFMCLK: Std_logic;
+    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
+    signal UFMCLK_c: Std_logic;
+    signal nUFMCS15: Std_logic;
+    signal N_139_i: Std_logic;
+    signal UFMCLK_RNO: Std_logic;
+    signal UFMSDI_r_xx_mm_1: Std_logic;
+    signal UFMSDI_c: Std_logic;
+    signal UFMSDI_RNO: Std_logic;
+    signal nRowColSel: Std_logic;
+    signal RowA_4: Std_logic;
+    signal MAin_c_4: Std_logic;
+    signal Din_c_4: Std_logic;
+    signal nCCAS_c: Std_logic;
+    signal RA_c_4: Std_logic;
+    signal WRD_4: Std_logic;
+    signal WRD_5: Std_logic;
+    signal Bank_7: Std_logic;
+    signal Bank_6: Std_logic;
+    signal Bank_5: Std_logic;
+    signal Bank_2: Std_logic;
+    signal Din_c_7: Std_logic;
+    signal WRD_6: Std_logic;
+    signal C1WR_0_a2_0_11: Std_logic;
+    signal WRD_7: Std_logic;
+    signal Din_c_2: Std_logic;
+    signal Din_c_0: Std_logic;
+    signal XOR8MEG_3_u_0_a3_2: Std_logic;
+    signal Din_c_1: Std_logic;
+    signal XOR8MEG_3: Std_logic;
+    signal N_69: Std_logic;
+    signal N_31: Std_logic;
+    signal N_151: Std_logic;
+    signal g0_1: Std_logic;
+    signal nRCAS_0_sqmuxa_1: Std_logic;
+    signal N_41: Std_logic;
+    signal N_37_i: Std_logic;
+    signal nRCAS_c: Std_logic;
+    signal CASr3: Std_logic;
+    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
+    signal N_28_i_1: Std_logic;
+    signal N_28_i: Std_logic;
+    signal nRCS_c: Std_logic;
+    signal N_24_i: Std_logic;
+    signal nRRAS_c: Std_logic;
+    signal CBR_fast: Std_logic;
+    signal m18_0_a2_1: Std_logic;
+    signal G_17_1: Std_logic;
+    signal FWEr: Std_logic;
+    signal N_39_i: Std_logic;
+    signal nRWE_c: Std_logic;
+    signal N_179: Std_logic;
+    signal nRowColSel_0_0: Std_logic;
+    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
+    signal nUFMCS_c: Std_logic;
+    signal nUFMCS_s_0_N_5_i: Std_logic;
+    signal CmdUFMCS: Std_logic;
+    signal N_95_5: Std_logic;
+    signal N_95_3: Std_logic;
+    signal RowA_0: Std_logic;
+    signal RowA_1: Std_logic;
+    signal MAin_c_5: Std_logic;
+    signal CmdUFMCLK_1_sqmuxa: Std_logic;
+    signal RowA_5: Std_logic;
+    signal un1_FS_14_i_a2_0_1: Std_logic;
+    signal N_137_8: Std_logic;
+    signal N_137_6: Std_logic;
+    signal un1_FS_13_i_a2_1: Std_logic;
+    signal C1WR_0_a2_0_10: Std_logic;
+    signal Bank_1: Std_logic;
+    signal Bank_0: Std_logic;
+    signal MAin_c_7: Std_logic;
+    signal MAin_c_6: Std_logic;
+    signal C1WR_0_a2_0_4: Std_logic;
+    signal C1WR_0_a2_0_3: Std_logic;
+    signal Bank_4: Std_logic;
+    signal Bank_3: Std_logic;
+    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
+    signal MAin_c_3: Std_logic;
+    signal MAin_c_2: Std_logic;
+    signal RowA_2: Std_logic;
+    signal RowA_3: Std_logic;
+    signal CmdUFMSDI: Std_logic;
+    signal CASr: Std_logic;
+    signal CmdEnable16_1: Std_logic;
+    signal m6_0_a2_2: Std_logic;
+    signal WRD_0: Std_logic;
+    signal WRD_1: Std_logic;
+    signal g4_0_0_0: Std_logic;
+    signal MAin_c_9: Std_logic;
+    signal MAin_c_8: Std_logic;
+    signal RowA_8: Std_logic;
+    signal RowA_9: Std_logic;
+    signal nFWE_c: Std_logic;
+    signal CROW_c_1: Std_logic;
+    signal CROW_c_0: Std_logic;
+    signal RBA_c_0: Std_logic;
+    signal RBA_c_1: Std_logic;
+    signal WRD_2: Std_logic;
+    signal WRD_3: Std_logic;
+    signal RA_c_9: Std_logic;
+    signal RDQML_c: Std_logic;
+    signal RD_1_i: Std_logic;
+    signal RowA_6: Std_logic;
+    signal RowA_7: Std_logic;
+    signal RA_c_8: Std_logic;
+    signal RDQMH_c: Std_logic;
+    signal RA_c_0: Std_logic;
+    signal RA_c_1: Std_logic;
+    signal RA_c_7: Std_logic;
+    signal RA_c_2: Std_logic;
+    signal RA_c_6: Std_logic;
+    signal RA_c_3: Std_logic;
+    signal RA_c_5: Std_logic;
+    signal RA_c_10: Std_logic;
+    signal RD_in_0: Std_logic;
+    signal RD_in_7: Std_logic;
+    signal RD_in_6: Std_logic;
+    signal RD_in_5: Std_logic;
+    signal RD_in_4: Std_logic;
+    signal RD_in_3: Std_logic;
+    signal RD_in_2: Std_logic;
+    signal RD_in_1: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI_TSALL: Std_logic;
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+    component PUR
+      port (PUR: in Std_logic);
+    end component;
+    component GSR
+      port (GSR: in Std_logic);
+    end component;
+    component TSALL
+      port (TSALL: in Std_logic);
+    end component;
+    component SLICE_0
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component SLICE_1
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_2
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_3
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_4
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_5
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_6
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_7
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_8
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_9
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_14
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_19
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_20
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component SLICE_21
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_22
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_26
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_29
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_30
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_31
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_32
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_33
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_39
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_41
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_42
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_43
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_44
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_50
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_51
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_52
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_55
+      port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_56
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_57
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_58
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_59
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_60
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_61
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_62
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_63
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_64
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component nRWE_RNO_1_SLICE_65
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component SLICE_66
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_67
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_68
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_69
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_70
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_71
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_72
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_73
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_74
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_75
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_76
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_77
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_78
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_79
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_80
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_81
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_82
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_83
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_84
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_85
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_86
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_87
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_88
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_89
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_90
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_91
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_92
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_93
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_94
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component RD_0_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD0: inout Std_logic);
+    end component;
+    component Dout_0_B
+      port (PADDO: in Std_logic; Dout0: out Std_logic);
+    end component;
+    component PHI2B
+      port (PADDI: out Std_logic; PHI2S: in Std_logic);
+    end component;
+    component UFMSDOB
+      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+    end component;
+    component UFMSDIB
+      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+    end component;
+    component UFMCLKB
+      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+    end component;
+    component nUFMCSB
+      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+    end component;
+    component RDQMLB
+      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+    end component;
+    component RDQMHB
+      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+    end component;
+    component nRCASB
+      port (PADDO: in Std_logic; nRCASS: out Std_logic);
+    end component;
+    component nRRASB
+      port (PADDO: in Std_logic; nRRASS: out Std_logic);
+    end component;
+    component nRWEB
+      port (PADDO: in Std_logic; nRWES: out Std_logic);
+    end component;
+    component RCKEB
+      port (PADDO: in Std_logic; RCKES: out Std_logic);
+    end component;
+    component RCLKB
+      port (PADDI: out Std_logic; RCLKS: in Std_logic);
+    end component;
+    component nRCSB
+      port (PADDO: in Std_logic; nRCSS: out Std_logic);
+    end component;
+    component RD_7_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD7: inout Std_logic);
+    end component;
+    component RD_6_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD6: inout Std_logic);
+    end component;
+    component RD_5_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD5: inout Std_logic);
+    end component;
+    component RD_4_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD4: inout Std_logic);
+    end component;
+    component RD_3_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD3: inout Std_logic);
+    end component;
+    component RD_2_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD2: inout Std_logic);
+    end component;
+    component RD_1_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD1: inout Std_logic);
+    end component;
+    component RA_11_B
+      port (PADDO: in Std_logic; RA11: out Std_logic);
+    end component;
+    component RA_10_B
+      port (PADDO: in Std_logic; RA10: out Std_logic);
+    end component;
+    component RA_9_B
+      port (PADDO: in Std_logic; RA9: out Std_logic);
+    end component;
+    component RA_8_B
+      port (PADDO: in Std_logic; RA8: out Std_logic);
+    end component;
+    component RA_7_B
+      port (PADDO: in Std_logic; RA7: out Std_logic);
+    end component;
+    component RA_6_B
+      port (PADDO: in Std_logic; RA6: out Std_logic);
+    end component;
+    component RA_5_B
+      port (PADDO: in Std_logic; RA5: out Std_logic);
+    end component;
+    component RA_4_B
+      port (PADDO: in Std_logic; RA4: out Std_logic);
+    end component;
+    component RA_3_B
+      port (PADDO: in Std_logic; RA3: out Std_logic);
+    end component;
+    component RA_2_B
+      port (PADDO: in Std_logic; RA2: out Std_logic);
+    end component;
+    component RA_1_B
+      port (PADDO: in Std_logic; RA1: out Std_logic);
+    end component;
+    component RA_0_B
+      port (PADDO: in Std_logic; RA0: out Std_logic);
+    end component;
+    component RBA_1_B
+      port (PADDO: in Std_logic; RBA1: out Std_logic);
+    end component;
+    component RBA_0_B
+      port (PADDO: in Std_logic; RBA0: out Std_logic);
+    end component;
+    component LEDB
+      port (PADDO: in Std_logic; LEDS: out Std_logic);
+    end component;
+    component nFWEB
+      port (PADDI: out Std_logic; nFWES: in Std_logic);
+    end component;
+    component nCRASB
+      port (PADDI: out Std_logic; nCRASS: in Std_logic);
+    end component;
+    component nCCASB
+      port (PADDI: out Std_logic; nCCASS: in Std_logic);
+    end component;
+    component Dout_7_B
+      port (PADDO: in Std_logic; Dout7: out Std_logic);
+    end component;
+    component Dout_6_B
+      port (PADDO: in Std_logic; Dout6: out Std_logic);
+    end component;
+    component Dout_5_B
+      port (PADDO: in Std_logic; Dout5: out Std_logic);
+    end component;
+    component Dout_4_B
+      port (PADDO: in Std_logic; Dout4: out Std_logic);
+    end component;
+    component Dout_3_B
+      port (PADDO: in Std_logic; Dout3: out Std_logic);
+    end component;
+    component Dout_2_B
+      port (PADDO: in Std_logic; Dout2: out Std_logic);
+    end component;
+    component Dout_1_B
+      port (PADDO: in Std_logic; Dout1: out Std_logic);
+    end component;
+    component Din_7_B
+      port (PADDI: out Std_logic; Din7: in Std_logic);
+    end component;
+    component Din_6_B
+      port (PADDI: out Std_logic; Din6: in Std_logic);
+    end component;
+    component Din_5_B
+      port (PADDI: out Std_logic; Din5: in Std_logic);
+    end component;
+    component Din_4_B
+      port (PADDI: out Std_logic; Din4: in Std_logic);
+    end component;
+    component Din_3_B
+      port (PADDI: out Std_logic; Din3: in Std_logic);
+    end component;
+    component Din_2_B
+      port (PADDI: out Std_logic; Din2: in Std_logic);
+    end component;
+    component Din_1_B
+      port (PADDI: out Std_logic; Din1: in Std_logic);
+    end component;
+    component Din_0_B
+      port (PADDI: out Std_logic; Din0: in Std_logic);
+    end component;
+    component CROW_1_B
+      port (PADDI: out Std_logic; CROW1: in Std_logic);
+    end component;
+    component CROW_0_B
+      port (PADDI: out Std_logic; CROW0: in Std_logic);
+    end component;
+    component MAin_9_B
+      port (PADDI: out Std_logic; MAin9: in Std_logic);
+    end component;
+    component MAin_8_B
+      port (PADDI: out Std_logic; MAin8: in Std_logic);
+    end component;
+    component MAin_7_B
+      port (PADDI: out Std_logic; MAin7: in Std_logic);
+    end component;
+    component MAin_6_B
+      port (PADDI: out Std_logic; MAin6: in Std_logic);
+    end component;
+    component MAin_5_B
+      port (PADDI: out Std_logic; MAin5: in Std_logic);
+    end component;
+    component MAin_4_B
+      port (PADDI: out Std_logic; MAin4: in Std_logic);
+    end component;
+    component MAin_3_B
+      port (PADDI: out Std_logic; MAin3: in Std_logic);
+    end component;
+    component MAin_2_B
+      port (PADDI: out Std_logic; MAin2: in Std_logic);
+    end component;
+    component MAin_1_B
+      port (PADDI: out Std_logic; MAin1: in Std_logic);
+    end component;
+    component MAin_0_B
+      port (PADDI: out Std_logic; MAin0: in Std_logic);
+    end component;
+  begin
+    SLICE_0I: SLICE_0
+      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
+                FCO=>FS_cry_1);
+    SLICE_1I: SLICE_1
+      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
+                Q1=>FS_17);
+    SLICE_2I: SLICE_2
+      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
+                Q1=>FS_15, FCO=>FS_cry_15);
+    SLICE_3I: SLICE_3
+      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
+                Q1=>FS_13, FCO=>FS_cry_13);
+    SLICE_4I: SLICE_4
+      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
+                Q1=>FS_11, FCO=>FS_cry_11);
+    SLICE_5I: SLICE_5
+      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
+                Q1=>FS_9, FCO=>FS_cry_9);
+    SLICE_6I: SLICE_6
+      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
+                Q1=>FS_7, FCO=>FS_cry_7);
+    SLICE_7I: SLICE_7
+      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
+                Q1=>FS_5, FCO=>FS_cry_5);
+    SLICE_8I: SLICE_8
+      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
+                Q1=>FS_3, FCO=>FS_cry_3);
+    SLICE_9I: SLICE_9
+      port map (D1=>N_147, C1=>MAin_c_0, B1=>CmdEnable17_0_a2_4, 
+                A1=>CmdEnable17_0_a2_3, D0=>CmdEnable16, C0=>CmdEnable17, 
+                B0=>C1WR_0_a2, A0=>ADSubmitted, DI0=>ADSubmitted_r, 
+                CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted, 
+                F1=>CmdEnable17);
+    SLICE_14I: SLICE_14
+      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
+                D0=>MAin_c_1, C0=>N_147, B0=>C1Submitted, A0=>CmdEnable16, 
+                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
+                Q0=>C1Submitted, F1=>CmdEnable16);
+    SLICE_19I: SLICE_19
+      port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, 
+                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
+                F1=>Ready_0_sqmuxa_0_a3_2);
+    SLICE_20I: SLICE_20
+      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, 
+                B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, 
+                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
+    SLICE_21I: SLICE_21
+      port map (C1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_152, C0=>N_133, 
+                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
+                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
+    SLICE_22I: SLICE_22
+      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
+                B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_460_0, 
+                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
+    SLICE_26I: SLICE_26
+      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
+                C0=>n8MEGEN, B0=>N_152, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_19_i, 
+                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
+                F1=>Cmdn8MEGEN_4_u_i_0);
+    SLICE_29I: SLICE_29
+      port map (D1=>nRRAS_5_u_i_0, C1=>N_160, B1=>N_155, A1=>IS_0, C0=>N_155, 
+                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
+                Q0=>IS_0, F1=>N_24);
+    SLICE_30I: SLICE_30
+      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, 
+                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
+    SLICE_31I: SLICE_31
+      port map (D1=>N_159, C1=>IS_3, B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, 
+                B0=>IS_2, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
+    SLICE_32I: SLICE_32
+      port map (D1=>UFMSDI_ens2_i_a2_4_2, C1=>N_126, B1=>N_51, A1=>InitReady, 
+                B0=>InitReady, A0=>InitReady3, DI0=>N_461_0, CLK=>RCLK_c, 
+                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
+    SLICE_33I: SLICE_33
+      port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, C0=>UFMSDO_c, B0=>InitReady, 
+                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
+                Q0=>LEDEN, F1=>LED_c);
+    SLICE_39I: SLICE_39
+      port map (B1=>un1_Din_4, A1=>XOR8MEG, C0=>n8MEGEN, B0=>XOR8MEG, 
+                A0=>Din_c_6, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
+                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
+    SLICE_41I: SLICE_41
+      port map (D1=>S_1, C1=>FWEr_fast, B1=>CO0, A1=>CASr2, D0=>Ready, 
+                C0=>RCKEEN_8_u_1, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, 
+                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
+                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
+    SLICE_42I: SLICE_42
+      port map (D1=>RASr2, C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>RCKEEN, C0=>RASr3, 
+                B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
+                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
+    SLICE_43I: SLICE_43
+      port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, 
+                D0=>InitReady, C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, 
+                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
+                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
+    SLICE_44I: SLICE_44
+      port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_165, A1=>InitReady, 
+                B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_463_0, M1=>nCRAS_c, 
+                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
+                Q1=>RASr);
+    SLICE_50I: SLICE_50
+      port map (C1=>CO0, B1=>S_1, A1=>Ready, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1, 
+                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
+                F1=>nRRAS_0_sqmuxa);
+    SLICE_51I: SLICE_51
+      port map (D1=>N_129, C1=>UFMCLK_r_i_a2_2_2, B1=>CmdUFMCLK, A1=>InitReady, 
+                D0=>UFMCLK_r_i_m4_xx_mm_1, C0=>UFMCLK_c, B0=>nUFMCS15, 
+                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
+                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
+                Q1=>RASr2);
+    SLICE_52I: SLICE_52
+      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
+                D0=>UFMSDI_r_xx_mm_1, C0=>UFMSDI_c, B0=>nUFMCS15, A0=>N_139_i, 
+                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
+                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
+    SLICE_55I: SLICE_55
+      port map (C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, M1=>Din_c_5, 
+                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
+    SLICE_56I: SLICE_56
+      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, C0=>FS_9, 
+                B0=>FS_7, A0=>FS_5, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
+                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
+    SLICE_57I: SLICE_57
+      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
+                D0=>XOR8MEG_3_u_0_a3_2, C0=>N_171, B0=>LEDEN, A0=>Din_c_1, 
+                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
+                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
+    SLICE_58I: SLICE_58
+      port map (C1=>N_51, B1=>InitReady, A1=>FS_8, C0=>UFMSDO_c, B0=>InitReady, 
+                A0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
+                Q0=>n8MEGEN, F1=>N_151);
+    SLICE_59I: SLICE_59
+      port map (D1=>S_1, C1=>Ready, B1=>N_160, A1=>N_155, D0=>g0_1, C0=>S_1, 
+                B0=>nRCAS_0_sqmuxa_1, A0=>N_41, DI0=>N_37_i, CLK=>RCLK_c, 
+                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
+    SLICE_60I: SLICE_60
+      port map (D1=>CASr2, C1=>CASr3, B1=>CO0, A1=>FWEr_fast, 
+                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
+                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
+    SLICE_61I: SLICE_61
+      port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, D0=>IS_0, 
+                C0=>N_155, B0=>N_160, A0=>nRRAS_5_u_i_0, DI0=>N_24_i, 
+                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
+    SLICE_62I: SLICE_62
+      port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR_fast, 
+                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>G_17_1, A0=>FWEr, 
+                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
+                F1=>nRCAS_0_sqmuxa_1);
+    SLICE_63I: SLICE_63
+      port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, 
+                B0=>N_179, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
+                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
+    SLICE_64I: SLICE_64
+      port map (D1=>N_51, C1=>InitReady, B1=>FS_11, A1=>FS_10, 
+                D0=>nUFMCS_s_0_N_5_i_N_2L1, C0=>nUFMCS_c, B0=>nUFMCS15, 
+                A0=>N_139_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, 
+                F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS15);
+    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
+      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>InitReady, 
+                C0=>m18_0_a3_3, B0=>CO0, A0=>S_1, M0=>Ready, OFX0=>m18_0_a2_1);
+    SLICE_66I: SLICE_66
+      port map (C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, A1=>CmdUFMCS, D0=>N_95_5, 
+                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
+                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
+                Q1=>RowA_1);
+    SLICE_67I: SLICE_67
+      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_128, A1=>XOR8MEG18, D0=>N_147, 
+                C0=>MAin_c_1, B0=>MAin_c_0, A0=>CmdEnable, M1=>MAin_c_5, 
+                M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, F0=>XOR8MEG18, 
+                Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
+    SLICE_68I: SLICE_68
+      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_14_i_a2_0_1, 
+                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_31, 
+                F1=>un1_FS_14_i_a2_0_1);
+    SLICE_69I: SLICE_69
+      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_13_i_a2_1, 
+                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_33, 
+                F1=>un1_FS_13_i_a2_1);
+    SLICE_70I: SLICE_70
+      port map (D1=>C1WR_0_a2_0_11, C1=>C1WR_0_a2_0_10, B1=>Bank_1, A1=>Bank_0, 
+                B0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
+                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
+    SLICE_71I: SLICE_71
+      port map (D1=>MAin_c_7, C1=>MAin_c_6, B1=>MAin_c_5, A1=>MAin_c_4, 
+                D0=>C1WR_0_a2_0_4, C0=>C1WR_0_a2_0_3, B0=>Bank_4, A0=>Bank_3, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
+                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
+    SLICE_72I: SLICE_72
+      port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_12, D0=>N_51, 
+                C0=>FS_11, B0=>FS_4, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
+                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
+                Q1=>RowA_3);
+    SLICE_73I: SLICE_73
+      port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, B0=>Ready, 
+                A0=>N_155, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
+                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
+    SLICE_74I: SLICE_74
+      port map (B1=>FS_14, A1=>FS_11, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
+                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
+                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
+    SLICE_75I: SLICE_75
+      port map (C1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, C0=>N_128, B0=>Din_c_5, 
+                A0=>Din_c_1, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
+                Q0=>CASr, F1=>N_128, Q1=>CASr2);
+    SLICE_76I: SLICE_76
+      port map (B1=>Din_c_5, A1=>Din_c_0, D0=>MAin_c_0, C0=>Din_c_3, 
+                B0=>Din_c_1, A0=>CmdEnable16_4, M1=>Din_c_5, M0=>Din_c_4, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
+                F1=>CmdEnable16_4, Q1=>Bank_5);
+    SLICE_77I: SLICE_77
+      port map (B1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>Din_c_6, 
+                B0=>Din_c_2, A0=>CmdEnable16_1, M1=>Din_c_7, M0=>Din_c_6, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
+                F1=>CmdEnable16_1, Q1=>Bank_7);
+    SLICE_78I: SLICE_78
+      port map (B1=>Din_c_5, A1=>Din_c_3, D0=>N_43, C0=>MAin_c_1, B0=>Din_c_6, 
+                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
+                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
+    SLICE_79I: SLICE_79
+      port map (C1=>Ready, B1=>CASr3, A1=>CASr2, D0=>m6_0_a2_2, C0=>S_1, 
+                B0=>CO0, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
+                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
+    SLICE_80I: SLICE_80
+      port map (B1=>CASr3, A1=>CASr2, D0=>g4_0_0_0, C0=>FWEr, B0=>CO0, 
+                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
+    SLICE_81I: SLICE_81
+      port map (D1=>FS_17, C1=>FS_15, B1=>FS_14, A1=>FS_13, D0=>FS_17, 
+                C0=>FS_15, B0=>FS_13, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
+                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
+                Q1=>FWEr_fast);
+    SLICE_82I: SLICE_82
+      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>CmdLEDEN, A1=>N_128, D0=>Din_c_3, 
+                C0=>Din_c_5, B0=>N_128, A0=>XOR8MEG18, M0=>CASr2, CLK=>RCLK_c, 
+                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
+    SLICE_83I: SLICE_83
+      port map (C1=>IS_3, B1=>IS_2, A1=>IS_1, C0=>IS_2, B0=>IS_1, A0=>IS_0, 
+                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
+    SLICE_84I: SLICE_84
+      port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>FS_10, C0=>FS_7, 
+                B0=>FS_6, A0=>FS_1, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
+    SLICE_85I: SLICE_85
+      port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_0, A1=>Din_c_1, 
+                D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
+                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
+    SLICE_86I: SLICE_86
+      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, 
+                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
+    SLICE_87I: SLICE_87
+      port map (C1=>N_151, B1=>UFMSDI_ens2_i_a0, A1=>CmdUFMSDI, D0=>N_151, 
+                C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_137_8, 
+                F1=>UFMSDI_r_xx_mm_1);
+    SLICE_88I: SLICE_88
+      port map (C1=>nFWE_c, B1=>MAin_c_3, A1=>MAin_c_2, B0=>nFWE_c, 
+                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
+                Q1=>RowA_7);
+    SLICE_89I: SLICE_89
+      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, 
+                A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
+    SLICE_90I: SLICE_90
+      port map (C1=>MAin_c_1, B1=>MAin_c_0, A1=>N_147, C0=>nRowColSel, 
+                B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>un1_CMDWR);
+    SLICE_91I: SLICE_91
+      port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, 
+                B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
+    SLICE_92I: SLICE_92
+      port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, 
+                B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
+    SLICE_93I: SLICE_93
+      port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, 
+                B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
+    SLICE_94I: SLICE_94
+      port map (B1=>N_155, A1=>Ready, B0=>S_1, A0=>Ready, M0=>IS_0, 
+                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
+                Q0=>RA_c_10, F1=>N_159_i);
+    RD_0_I: RD_0_B
+      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
+    Dout_0_I: Dout_0_B
+      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
+    PHI2I: PHI2B
+      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
+    UFMSDOI: UFMSDOB
+      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
+    UFMSDII: UFMSDIB
+      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
+    UFMCLKI: UFMCLKB
+      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
+    nUFMCSI: nUFMCSB
+      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
+    RDQMLI: RDQMLB
+      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
+    RDQMHI: RDQMHB
+      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
+    nRCASI: nRCASB
+      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
+    nRRASI: nRRASB
+      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
+    nRWEI: nRWEB
+      port map (PADDO=>nRWE_c, nRWES=>nRWE);
+    RCKEI: RCKEB
+      port map (PADDO=>RCKE_c, RCKES=>RCKE);
+    RCLKI: RCLKB
+      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
+    nRCSI: nRCSB
+      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
+    RD_7_I: RD_7_B
+      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
+    RD_6_I: RD_6_B
+      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
+    RD_5_I: RD_5_B
+      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
+    RD_4_I: RD_4_B
+      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
+    RD_3_I: RD_3_B
+      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
+    RD_2_I: RD_2_B
+      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
+    RD_1_I0: RD_1_B
+      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
+    RA_11_I: RA_11_B
+      port map (PADDO=>RA_c_11, RA11=>RA(11));
+    RA_10_I: RA_10_B
+      port map (PADDO=>RA_c_10, RA10=>RA(10));
+    RA_9_I: RA_9_B
+      port map (PADDO=>RA_c_9, RA9=>RA(9));
+    RA_8_I: RA_8_B
+      port map (PADDO=>RA_c_8, RA8=>RA(8));
+    RA_7_I: RA_7_B
+      port map (PADDO=>RA_c_7, RA7=>RA(7));
+    RA_6_I: RA_6_B
+      port map (PADDO=>RA_c_6, RA6=>RA(6));
+    RA_5_I: RA_5_B
+      port map (PADDO=>RA_c_5, RA5=>RA(5));
+    RA_4_I: RA_4_B
+      port map (PADDO=>RA_c_4, RA4=>RA(4));
+    RA_3_I: RA_3_B
+      port map (PADDO=>RA_c_3, RA3=>RA(3));
+    RA_2_I: RA_2_B
+      port map (PADDO=>RA_c_2, RA2=>RA(2));
+    RA_1_I: RA_1_B
+      port map (PADDO=>RA_c_1, RA1=>RA(1));
+    RA_0_I: RA_0_B
+      port map (PADDO=>RA_c_0, RA0=>RA(0));
+    RBA_1_I: RBA_1_B
+      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
+    RBA_0_I: RBA_0_B
+      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
+    LEDI: LEDB
+      port map (PADDO=>LED_c, LEDS=>LED);
+    nFWEI: nFWEB
+      port map (PADDI=>nFWE_c, nFWES=>nFWE);
+    nCRASI: nCRASB
+      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
+    nCCASI: nCCASB
+      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
+    Dout_7_I: Dout_7_B
+      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
+    Dout_6_I: Dout_6_B
+      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
+    Dout_5_I: Dout_5_B
+      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
+    Dout_4_I: Dout_4_B
+      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
+    Dout_3_I: Dout_3_B
+      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
+    Dout_2_I: Dout_2_B
+      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
+    Dout_1_I: Dout_1_B
+      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
+    Din_7_I: Din_7_B
+      port map (PADDI=>Din_c_7, Din7=>Din(7));
+    Din_6_I: Din_6_B
+      port map (PADDI=>Din_c_6, Din6=>Din(6));
+    Din_5_I: Din_5_B
+      port map (PADDI=>Din_c_5, Din5=>Din(5));
+    Din_4_I: Din_4_B
+      port map (PADDI=>Din_c_4, Din4=>Din(4));
+    Din_3_I: Din_3_B
+      port map (PADDI=>Din_c_3, Din3=>Din(3));
+    Din_2_I: Din_2_B
+      port map (PADDI=>Din_c_2, Din2=>Din(2));
+    Din_1_I: Din_1_B
+      port map (PADDI=>Din_c_1, Din1=>Din(1));
+    Din_0_I: Din_0_B
+      port map (PADDI=>Din_c_0, Din0=>Din(0));
+    CROW_1_I: CROW_1_B
+      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
+    CROW_0_I: CROW_0_B
+      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
+    MAin_9_I: MAin_9_B
+      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
+    MAin_8_I: MAin_8_B
+      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
+    MAin_7_I: MAin_7_B
+      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
+    MAin_6_I: MAin_6_B
+      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
+    MAin_5_I: MAin_5_B
+      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
+    MAin_4_I: MAin_4_B
+      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
+    MAin_3_I: MAin_3_B
+      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
+    MAin_2_I: MAin_2_B
+      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
+    MAin_1_I: MAin_1_B
+      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
+    MAin_0_I: MAin_0_B
+      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
+    VHI_INST: VHI
+      port map (Z=>VCCI);
+    PUR_INST: PUR
+      port map (PUR=>VCCI);
+    GSR_INST: GSR
+      port map (GSR=>VCCI);
+    VLO_INST: VLO
+      port map (Z=>GNDI_TSALL);
+    TSALL_INST: TSALL
+      port map (TSALL=>GNDI_TSALL);
+  end Structure;
+
+
+
+  library IEEE, vital2000, MACHXO;
+  configuration Structure_CON of RAM2GS is
+    for Structure
+    end for;
+  end Structure_CON;
+
+
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
index 0c971b3..08a955b 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
@@ -1,2922 +1,2922 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:41 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1\/SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_")
-    (INSTANCE RD\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_")
-    (INSTANCE Dout\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2")
-    (INSTANCE PHI2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2) (1250:1250:1250))
-      (WIDTH (negedge PHI2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDO")
-    (INSTANCE UFMSDO_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDO) (1250:1250:1250))
-      (WIDTH (negedge UFMSDO) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI")
-    (INSTANCE UFMSDI_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK")
-    (INSTANCE UFMCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCS")
-    (INSTANCE nUFMCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQML")
-    (INSTANCE RDQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMH")
-    (INSTANCE RDQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCAS")
-    (INSTANCE nRCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRAS")
-    (INSTANCE nRRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE")
-    (INSTANCE RCKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLK")
-    (INSTANCE RCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLK) (1250:1250:1250))
-      (WIDTH (negedge RCLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCS")
-    (INSTANCE nRCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_")
-    (INSTANCE RD\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_")
-    (INSTANCE RD\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_")
-    (INSTANCE RD\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_")
-    (INSTANCE RD\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_")
-    (INSTANCE RD\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_")
-    (INSTANCE RD\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_")
-    (INSTANCE RD\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_")
-    (INSTANCE RBA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_")
-    (INSTANCE RBA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LED")
-    (INSTANCE LED_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWE")
-    (INSTANCE nFWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWE) (1250:1250:1250))
-      (WIDTH (negedge nFWE) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRAS")
-    (INSTANCE nCRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRAS) (1250:1250:1250))
-      (WIDTH (negedge nCRAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCAS")
-    (INSTANCE nCCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCAS) (1250:1250:1250))
-      (WIDTH (negedge nCCAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_")
-    (INSTANCE Dout\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_")
-    (INSTANCE Dout\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_")
-    (INSTANCE Dout\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_")
-    (INSTANCE Dout\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_")
-    (INSTANCE Dout\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_")
-    (INSTANCE Dout\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_")
-    (INSTANCE Dout\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_")
-    (INSTANCE Din\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_")
-    (INSTANCE Din\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_")
-    (INSTANCE Din\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_")
-    (INSTANCE Din\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_")
-    (INSTANCE Din\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_")
-    (INSTANCE Din\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_")
-    (INSTANCE Din\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_")
-    (INSTANCE Din\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_")
-    (INSTANCE CROW\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_")
-    (INSTANCE CROW\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_")
-    (INSTANCE MAin\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_")
-    (INSTANCE MAin\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_")
-    (INSTANCE MAin\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_")
-    (INSTANCE MAin\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_")
-    (INSTANCE MAin\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_")
-    (INSTANCE MAin\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_")
-    (INSTANCE MAin\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_")
-    (INSTANCE MAin\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_")
-    (INSTANCE MAin\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_")
-    (INSTANCE MAin\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_81/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_87/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_87/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_84/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_84/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_56/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_69/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q0 SLICE_72/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q1 SLICE_68/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_9/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_67/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F1 SLICE_90/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78/F0 SLICE_9/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85/F1 SLICE_9/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/F1 SLICE_9/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/F1 SLICE_14/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9/F1 SLICE_20/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/F0 SLICE_9/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/Q0 SLICE_20/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_41/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/Q0 SLICE_94/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:53:21 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1\/SLICE_65)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_")
+    (INSTANCE RD\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_")
+    (INSTANCE Dout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2")
+    (INSTANCE PHI2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2) (1250:1250:1250))
+      (WIDTH (negedge PHI2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDO")
+    (INSTANCE UFMSDO_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDO) (1250:1250:1250))
+      (WIDTH (negedge UFMSDO) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDI")
+    (INSTANCE UFMSDI_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLK")
+    (INSTANCE UFMCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCS")
+    (INSTANCE nUFMCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQML")
+    (INSTANCE RDQML_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMH")
+    (INSTANCE RDQMH_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCAS")
+    (INSTANCE nRCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRAS")
+    (INSTANCE nRRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE")
+    (INSTANCE nRWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKE")
+    (INSTANCE RCKE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLK")
+    (INSTANCE RCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLK) (1250:1250:1250))
+      (WIDTH (negedge RCLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCS")
+    (INSTANCE nRCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_")
+    (INSTANCE RD\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_")
+    (INSTANCE RD\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_")
+    (INSTANCE RD\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_")
+    (INSTANCE RD\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_")
+    (INSTANCE RD\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_")
+    (INSTANCE RD\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_")
+    (INSTANCE RD\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_")
+    (INSTANCE RA\[11\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_")
+    (INSTANCE RA\[10\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_")
+    (INSTANCE RA\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_")
+    (INSTANCE RA\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_")
+    (INSTANCE RA\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_")
+    (INSTANCE RA\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_")
+    (INSTANCE RA\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_")
+    (INSTANCE RA\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_")
+    (INSTANCE RA\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_")
+    (INSTANCE RA\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_")
+    (INSTANCE RA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_")
+    (INSTANCE RA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_")
+    (INSTANCE RBA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_")
+    (INSTANCE RBA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LED")
+    (INSTANCE LED_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWE")
+    (INSTANCE nFWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWE) (1250:1250:1250))
+      (WIDTH (negedge nFWE) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRAS")
+    (INSTANCE nCRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRAS) (1250:1250:1250))
+      (WIDTH (negedge nCRAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCAS")
+    (INSTANCE nCCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCAS) (1250:1250:1250))
+      (WIDTH (negedge nCCAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_")
+    (INSTANCE Dout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_")
+    (INSTANCE Dout\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_")
+    (INSTANCE Dout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_")
+    (INSTANCE Dout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_")
+    (INSTANCE Dout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_")
+    (INSTANCE Dout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_")
+    (INSTANCE Dout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_")
+    (INSTANCE Din\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_")
+    (INSTANCE Din\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_")
+    (INSTANCE Din\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_")
+    (INSTANCE Din\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_")
+    (INSTANCE Din\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_")
+    (INSTANCE Din\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_")
+    (INSTANCE Din\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_")
+    (INSTANCE Din\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_")
+    (INSTANCE CROW\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_")
+    (INSTANCE CROW\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_")
+    (INSTANCE MAin\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_")
+    (INSTANCE MAin\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_")
+    (INSTANCE MAin\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_")
+    (INSTANCE MAin\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_")
+    (INSTANCE MAin\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_")
+    (INSTANCE MAin\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_")
+    (INSTANCE MAin\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_")
+    (INSTANCE MAin\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_")
+    (INSTANCE MAin\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_")
+    (INSTANCE MAin\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_72/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_74/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_81/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_87/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_87/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q0 SLICE_84/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_84/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_56/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_69/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_72/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_68/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_9/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_67/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_90/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78/F0 SLICE_9/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85/F1 SLICE_9/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_9/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F1 SLICE_20/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F0 SLICE_9/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/Q0 SLICE_20/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_41/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_94/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_43/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_61/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_62/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_73/A1 (0:0:0)(0:0:0))
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+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
index 3408875..7551d74 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
@@ -1,3540 +1,3540 @@
-
-// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
-// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
-// Netlist created on Wed Aug 16 04:50:39 2023
-// Netlist written on Wed Aug 16 04:50:41 2023
-// Design is for device LCMXO256C
-// Design is for package TQFP100
-// Design is for performance grade 3
-
-`timescale 1 ns / 1 ps
-
-module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
-                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
-                UFMCLK, UFMSDI, UFMSDO );
-  input  PHI2;
-  input  [9:0] MAin;
-  input  [1:0] CROW;
-  input  [7:0] Din;
-  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
-  output [7:0] Dout;
-  output LED;
-  output [1:0] RBA;
-  output [11:0] RA;
-  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
-  inout  [7:0] RD;
-  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
-         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
-         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
-         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
-         \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, 
-         CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, 
-         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
-         \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , 
-         CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
-         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, 
-         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, 
-         CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
-         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
-         N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , 
-         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, 
-         UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, 
-         UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, 
-         un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, 
-         FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, 
-         RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, 
-         N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, 
-         UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, 
-         nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, 
-         nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , 
-         \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , 
-         \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , 
-         \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, 
-         N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, 
-         RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, 
-         CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, 
-         nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, 
-         CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , 
-         CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, 
-         un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , 
-         \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , 
-         UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , 
-         CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , 
-         g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, 
-         \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , 
-         \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, 
-         \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , 
-         \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
-         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
-
-  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
-    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
-  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
-  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
-  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
-  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
-  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
-    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
-  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
-    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
-  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
-    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
-  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
-    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
-  SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), 
-    .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), 
-    .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
-    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
-  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
-    .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), 
-    .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
-    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
-  SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
-    .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
-  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
-    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
-    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
-  SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), 
-    .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
-  SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
-    .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), 
-    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
-  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
-    .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), 
-    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
-    .F1(Cmdn8MEGEN_4_u_i_0));
-  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), 
-    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
-    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
-  SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
-    .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
-    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
-  SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), 
-    .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
-    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
-  SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), 
-    .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), 
-    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
-  SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), 
-    .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
-    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
-  SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), 
-    .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), 
-    .Q0(\RA_c[11] ), .F1(N_171));
-  SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), 
-    .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
-    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
-    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
-  SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), 
-    .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), 
-    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
-  SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), 
-    .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
-    .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
-    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
-  SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), 
-    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), 
-    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
-    .F1(Ready_0_sqmuxa), .Q1(RASr));
-  SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), 
-    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
-    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
-  SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), 
-    .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), 
-    .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), 
-    .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
-  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
-    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), 
-    .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
-    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
-  SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), 
-    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
-    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
-  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
-    .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
-    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
-  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), 
-    .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
-    .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
-  SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), 
-    .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
-    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
-  SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), 
-    .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), 
-    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
-  SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), 
-    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
-    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
-  SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), 
-    .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), 
-    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
-  SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), 
-    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), 
-    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
-    .F1(nRCAS_0_sqmuxa_1));
-  SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
-    .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), 
-    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
-    .F1(N_179));
-  SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), 
-    .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), 
-    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
-    .F1(nUFMCS15));
-  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
-    .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), 
-    .M0(Ready), .OFX0(m18_0_a2_1));
-  SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), 
-    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
-    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
-    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
-  SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), 
-    .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), 
-    .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
-    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
-    .Q1(\RowA[5] ));
-  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), 
-    .F1(un1_FS_14_i_a2_0_1));
-  SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), 
-    .F1(un1_FS_13_i_a2_1));
-  SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), 
-    .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
-    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
-    .Q1(\Bank[1] ));
-  SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), 
-    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), 
-    .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
-    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
-  SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), 
-    .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
-    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
-    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
-  SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
-    .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
-    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
-    .F1(N_155), .Q1(CmdUFMCS));
-  SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), 
-    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
-  SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
-    .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), 
-    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
-  SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), 
-    .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), 
-    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
-    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
-  SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
-    .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
-    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
-  SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), 
-    .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), 
-    .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), 
-    .Q1(CBR_fast));
-  SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), 
-    .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
-    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
-  SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), 
-    .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
-    .Q1(\RowA[9] ));
-  SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), 
-    .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), 
-    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
-    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
-  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), 
-    .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), 
-    .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), 
-    .F1(N_132));
-  SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), 
-    .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
-    .Q1(\RBA_c[1] ));
-  SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), 
-    .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), 
-    .F1(UFMSDI_ens2_i_a2_4_2));
-  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), 
-    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), 
-    .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
-    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
-  SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
-  SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), 
-    .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), 
-    .F1(UFMSDI_r_xx_mm_1));
-  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), 
-    .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
-    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
-  SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
-  SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), 
-    .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), 
-    .F1(un1_CMDWR));
-  SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
-    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
-    .F1(\RA_c[7] ));
-  SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
-    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
-    .F1(\RA_c[6] ));
-  SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
-    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
-    .F1(\RA_c[5] ));
-  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), 
-    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
-    .Q0(\RA_c[10] ), .F1(N_159_i));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
-    .RD0(RD[0]));
-  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
-  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
-  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
-  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
-  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
-  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
-  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
-  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
-  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
-  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
-  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
-  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
-  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
-  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
-    .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
-    .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
-    .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
-    .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
-    .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
-    .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
-    .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
-  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
-  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
-  LED LED_I( .PADDO(LED_c), .LED(LED));
-  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
-  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
-  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
-  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
-  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
-  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
-  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
-  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
-  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
-  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
-  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
-  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
-  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
-  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
-  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
-  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
-  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
-  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
-  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
-  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
-  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
-  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
-  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
-  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
-  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
-  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
-  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
-  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
-  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
-  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
-  VHI VHI_INST( .Z(VCCI));
-  PUR PUR_INST( .PUR(VCCI));
-  GSR GSR_INST( .GSR(VCCI));
-  VLO VLO_INST( .Z(GNDI_TSALL));
-  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
-endmodule
-
-module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
-         A1_dly, CLK_dly, A0_dly;
-
-  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
-    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-  endspecify
-
-endmodule
-
-module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module vcc ( output PWR1 );
-
-  VHI INST1( .Z(PWR1));
-endmodule
-
-module gnd ( output PWR0 );
-
-  VLO INST1( .Z(PWR0));
-endmodule
-
-module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h300a;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
-  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
-    .CO1());
-
-  specify
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h5002;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
-
-  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut4 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40002 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
-module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40003 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40004 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40005 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40006 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
-         CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(\SLICE_20/SLICE_20_K1_H1 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
-  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
-    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
-  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40012 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40014 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40017 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40022 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40026 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40027 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40028 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40039 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40040 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40050 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40053 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
-    OFX0 );
-  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
-         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
-
-  lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
-  lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
-  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
-    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
-    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (C1 => OFX0) = (0:0:0,0:0:0);
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40056 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
-
-  lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
-
-  lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
-
-  lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40066 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40071 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40072 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, M0_dly, CLK_dly;
-
-  lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40073 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40074 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40075 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40076 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
-
-  lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
-
-  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
-
-  specify
-    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD0) = (0:0:0,0:0:0);
-    (RD0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD0, 0:0:0);
-    $width (negedge RD0, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf ( input I, T, output Z, PAD, input PADI );
-
-  IB INST1( .I(PADI), .O(Z));
-  OBW INST2( .I(I), .T(T), .O(PAD));
-endmodule
-
-module Dout_0_ ( input PADDO, output Dout0 );
-
-  mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
-
-  specify
-    (PADDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0082 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module PHI2 ( output PADDI, input PHI2 );
-
-  mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2));
-
-  specify
-    (PHI2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge PHI2, 0:0:0);
-    $width (negedge PHI2, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0083 ( output Z, input PAD );
-
-  IBPD INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDO ( output PADDI, input UFMSDO );
-
-  mjiobuf0084 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
-
-  specify
-    (UFMSDO => PADDI) = (0:0:0,0:0:0);
-    $width (posedge UFMSDO, 0:0:0);
-    $width (negedge UFMSDO, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0084 ( output Z, input PAD );
-
-  IB INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDI ( input PADDO, output UFMSDI );
-
-  mjiobuf0085 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
-
-  specify
-    (PADDO => UFMSDI) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0085 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module UFMCLK ( input PADDO, output UFMCLK );
-
-  mjiobuf0085 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
-
-  specify
-    (PADDO => UFMCLK) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS ( input PADDO, output nUFMCS );
-
-  mjiobuf0085 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
-
-  specify
-    (PADDO => nUFMCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQML ( input PADDO, output RDQML );
-
-  mjiobuf0085 RDQML_pad( .I(PADDO), .PAD(RDQML));
-
-  specify
-    (PADDO => RDQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQMH ( input PADDO, output RDQMH );
-
-  mjiobuf0085 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
-
-  specify
-    (PADDO => RDQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS ( input PADDO, output nRCAS );
-
-  mjiobuf0085 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
-
-  specify
-    (PADDO => nRCAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS ( input PADDO, output nRRAS );
-
-  mjiobuf0085 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
-
-  specify
-    (PADDO => nRRAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE ( input PADDO, output nRWE );
-
-  mjiobuf0085 nRWE_pad( .I(PADDO), .PAD(nRWE));
-
-  specify
-    (PADDO => nRWE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE ( input PADDO, output RCKE );
-
-  mjiobuf0085 RCKE_pad( .I(PADDO), .PAD(RCKE));
-
-  specify
-    (PADDO => RCKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCLK ( output PADDI, input RCLK );
-
-  mjiobuf0084 RCLK_pad( .Z(PADDI), .PAD(RCLK));
-
-  specify
-    (RCLK => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RCLK, 0:0:0);
-    $width (negedge RCLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS ( input PADDO, output nRCS );
-
-  mjiobuf0085 nRCS_pad( .I(PADDO), .PAD(nRCS));
-
-  specify
-    (PADDO => nRCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
-
-  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
-
-  specify
-    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD7) = (0:0:0,0:0:0);
-    (RD7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD7, 0:0:0);
-    $width (negedge RD7, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
-
-  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
-
-  specify
-    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD6) = (0:0:0,0:0:0);
-    (RD6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD6, 0:0:0);
-    $width (negedge RD6, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
-
-  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
-
-  specify
-    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD5) = (0:0:0,0:0:0);
-    (RD5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD5, 0:0:0);
-    $width (negedge RD5, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
-
-  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
-
-  specify
-    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD4) = (0:0:0,0:0:0);
-    (RD4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD4, 0:0:0);
-    $width (negedge RD4, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
-
-  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
-
-  specify
-    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD3) = (0:0:0,0:0:0);
-    (RD3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD3, 0:0:0);
-    $width (negedge RD3, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
-
-  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
-
-  specify
-    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD2) = (0:0:0,0:0:0);
-    (RD2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD2, 0:0:0);
-    $width (negedge RD2, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
-
-  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
-
-  specify
-    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD1) = (0:0:0,0:0:0);
-    (RD1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD1, 0:0:0);
-    $width (negedge RD1, 0:0:0);
-  endspecify
-
-endmodule
-
-module RA_11_ ( input PADDO, output RA11 );
-
-  mjiobuf0085 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
-
-  specify
-    (PADDO => RA11) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10_ ( input PADDO, output RA10 );
-
-  mjiobuf0085 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
-
-  specify
-    (PADDO => RA10) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_9_ ( input PADDO, output RA9 );
-
-  mjiobuf0085 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
-
-  specify
-    (PADDO => RA9) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_8_ ( input PADDO, output RA8 );
-
-  mjiobuf0085 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
-
-  specify
-    (PADDO => RA8) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_7_ ( input PADDO, output RA7 );
-
-  mjiobuf0085 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
-
-  specify
-    (PADDO => RA7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_6_ ( input PADDO, output RA6 );
-
-  mjiobuf0085 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
-
-  specify
-    (PADDO => RA6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_5_ ( input PADDO, output RA5 );
-
-  mjiobuf0085 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
-
-  specify
-    (PADDO => RA5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_4_ ( input PADDO, output RA4 );
-
-  mjiobuf0085 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
-
-  specify
-    (PADDO => RA4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_3_ ( input PADDO, output RA3 );
-
-  mjiobuf0085 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
-
-  specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2_ ( input PADDO, output RA2 );
-
-  mjiobuf0085 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
-
-  specify
-    (PADDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_1_ ( input PADDO, output RA1 );
-
-  mjiobuf0085 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
-
-  specify
-    (PADDO => RA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_0_ ( input PADDO, output RA0 );
-
-  mjiobuf0085 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
-
-  specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1_ ( input PADDO, output RBA1 );
-
-  mjiobuf0085 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
-
-  specify
-    (PADDO => RBA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_0_ ( input PADDO, output RBA0 );
-
-  mjiobuf0085 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
-
-  specify
-    (PADDO => RBA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module LED ( input PADDO, output LED );
-
-  mjiobuf0086 LED_pad( .I(PADDO), .PAD(LED));
-
-  specify
-    (PADDO => LED) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0086 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module nFWE ( output PADDI, input nFWE );
-
-  mjiobuf0084 nFWE_pad( .Z(PADDI), .PAD(nFWE));
-
-  specify
-    (nFWE => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nFWE, 0:0:0);
-    $width (negedge nFWE, 0:0:0);
-  endspecify
-
-endmodule
-
-module nCRAS ( output PADDI, input nCRAS );
-
-  mjiobuf0087 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
-
-  specify
-    (nCRAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCRAS, 0:0:0);
-    $width (negedge nCRAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0087 ( output Z, input PAD );
-
-  IBPU INST1( .I(PAD), .O(Z));
-endmodule
-
-module nCCAS ( output PADDI, input nCCAS );
-
-  mjiobuf0087 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
-
-  specify
-    (nCCAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCCAS, 0:0:0);
-    $width (negedge nCCAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_7_ ( input PADDO, output Dout7 );
-
-  mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
-
-  specify
-    (PADDO => Dout7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_6_ ( input PADDO, output Dout6 );
-
-  mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
-
-  specify
-    (PADDO => Dout6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_5_ ( input PADDO, output Dout5 );
-
-  mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
-
-  specify
-    (PADDO => Dout5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_4_ ( input PADDO, output Dout4 );
-
-  mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
-
-  specify
-    (PADDO => Dout4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input PADDO, output Dout3 );
-
-  mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
-
-  specify
-    (PADDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input PADDO, output Dout2 );
-
-  mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
-
-  specify
-    (PADDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input PADDO, output Dout1 );
-
-  mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
-
-  specify
-    (PADDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7_ ( output PADDI, input Din7 );
-
-  mjiobuf0084 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
-
-  specify
-    (Din7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din7, 0:0:0);
-    $width (negedge Din7, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6_ ( output PADDI, input Din6 );
-
-  mjiobuf0084 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
-
-  specify
-    (Din6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din6, 0:0:0);
-    $width (negedge Din6, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5_ ( output PADDI, input Din5 );
-
-  mjiobuf0084 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
-
-  specify
-    (Din5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din5, 0:0:0);
-    $width (negedge Din5, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4_ ( output PADDI, input Din4 );
-
-  mjiobuf0084 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
-
-  specify
-    (Din4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din4, 0:0:0);
-    $width (negedge Din4, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3_ ( output PADDI, input Din3 );
-
-  mjiobuf0084 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
-
-  specify
-    (Din3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din3, 0:0:0);
-    $width (negedge Din3, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2_ ( output PADDI, input Din2 );
-
-  mjiobuf0084 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
-
-  specify
-    (Din2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din2, 0:0:0);
-    $width (negedge Din2, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_1_ ( output PADDI, input Din1 );
-
-  mjiobuf0084 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
-
-  specify
-    (Din1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din1, 0:0:0);
-    $width (negedge Din1, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_0_ ( output PADDI, input Din0 );
-
-  mjiobuf0084 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
-
-  specify
-    (Din0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din0, 0:0:0);
-    $width (negedge Din0, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_1_ ( output PADDI, input CROW1 );
-
-  mjiobuf0084 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
-
-  specify
-    (CROW1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW1, 0:0:0);
-    $width (negedge CROW1, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_0_ ( output PADDI, input CROW0 );
-
-  mjiobuf0084 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
-
-  specify
-    (CROW0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW0, 0:0:0);
-    $width (negedge CROW0, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_9_ ( output PADDI, input MAin9 );
-
-  mjiobuf0084 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
-
-  specify
-    (MAin9 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin9, 0:0:0);
-    $width (negedge MAin9, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_8_ ( output PADDI, input MAin8 );
-
-  mjiobuf0084 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
-
-  specify
-    (MAin8 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin8, 0:0:0);
-    $width (negedge MAin8, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_7_ ( output PADDI, input MAin7 );
-
-  mjiobuf0084 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
-
-  specify
-    (MAin7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin7, 0:0:0);
-    $width (negedge MAin7, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_6_ ( output PADDI, input MAin6 );
-
-  mjiobuf0084 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
-
-  specify
-    (MAin6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin6, 0:0:0);
-    $width (negedge MAin6, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_5_ ( output PADDI, input MAin5 );
-
-  mjiobuf0084 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
-
-  specify
-    (MAin5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin5, 0:0:0);
-    $width (negedge MAin5, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_4_ ( output PADDI, input MAin4 );
-
-  mjiobuf0084 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
-
-  specify
-    (MAin4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin4, 0:0:0);
-    $width (negedge MAin4, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_3_ ( output PADDI, input MAin3 );
-
-  mjiobuf0084 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
-
-  specify
-    (MAin3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin3, 0:0:0);
-    $width (negedge MAin3, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_2_ ( output PADDI, input MAin2 );
-
-  mjiobuf0084 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
-
-  specify
-    (MAin2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin2, 0:0:0);
-    $width (negedge MAin2, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_1_ ( output PADDI, input MAin1 );
-
-  mjiobuf0084 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
-
-  specify
-    (MAin1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin1, 0:0:0);
-    $width (negedge MAin1, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_0_ ( output PADDI, input MAin0 );
-
-  mjiobuf0084 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
-
-  specify
-    (MAin0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin0, 0:0:0);
-    $width (negedge MAin0, 0:0:0);
-  endspecify
-
-endmodule
+
+// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
+// Netlist created on Sat Aug 19 20:53:19 2023
+// Netlist written on Sat Aug 19 20:53:21 2023
+// Design is for device LCMXO256C
+// Design is for package TQFP100
+// Design is for performance grade 3
+
+`timescale 1 ns / 1 ps
+
+module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
+                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
+                UFMCLK, UFMSDI, UFMSDO );
+  input  PHI2;
+  input  [9:0] MAin;
+  input  [1:0] CROW;
+  input  [7:0] Din;
+  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
+  output [7:0] Dout;
+  output LED;
+  output [1:0] RBA;
+  output [11:0] RA;
+  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
+  inout  [7:0] RD;
+  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
+         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
+         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
+         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
+         \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, 
+         CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, 
+         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
+         \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , 
+         CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
+         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, 
+         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, 
+         CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
+         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
+         N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , 
+         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, 
+         UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, 
+         UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, 
+         un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, 
+         FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, 
+         RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, 
+         N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, 
+         UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, 
+         nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, 
+         nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , 
+         \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , 
+         \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , 
+         \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, 
+         N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, 
+         RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, 
+         CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, 
+         nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, 
+         CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , 
+         CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, 
+         un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , 
+         \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , 
+         UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , 
+         CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , 
+         g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, 
+         \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , 
+         \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, 
+         \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , 
+         \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
+         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
+
+  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
+    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
+  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
+  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
+  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
+  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
+  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
+    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
+  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
+    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
+  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
+    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
+  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
+    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
+  SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), 
+    .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), 
+    .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
+    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
+  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
+    .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), 
+    .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
+    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
+  SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
+    .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
+    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
+    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
+    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
+  SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), 
+    .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
+    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
+  SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
+    .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), 
+    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
+  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
+    .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), 
+    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
+    .F1(Cmdn8MEGEN_4_u_i_0));
+  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), 
+    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
+    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
+  SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
+    .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
+    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
+  SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), 
+    .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
+    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
+  SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), 
+    .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), 
+    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
+  SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), 
+    .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
+    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
+  SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), 
+    .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), 
+    .Q0(\RA_c[11] ), .F1(N_171));
+  SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), 
+    .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
+    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
+    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
+  SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), 
+    .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), 
+    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
+  SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), 
+    .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
+    .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
+    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
+  SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), 
+    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), 
+    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
+    .F1(Ready_0_sqmuxa), .Q1(RASr));
+  SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), 
+    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
+    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
+  SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), 
+    .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), 
+    .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), 
+    .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
+  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
+    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), 
+    .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
+    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
+  SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), 
+    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
+    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
+  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
+    .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
+    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
+  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), 
+    .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
+    .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
+  SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), 
+    .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
+    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
+  SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), 
+    .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), 
+    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
+  SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), 
+    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
+    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
+  SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), 
+    .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), 
+    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
+  SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), 
+    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), 
+    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
+    .F1(nRCAS_0_sqmuxa_1));
+  SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
+    .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), 
+    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
+    .F1(N_179));
+  SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), 
+    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
+    .F1(nUFMCS15));
+  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
+    .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), 
+    .M0(Ready), .OFX0(m18_0_a2_1));
+  SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), 
+    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
+    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
+    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
+  SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), 
+    .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), 
+    .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
+    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
+    .Q1(\RowA[5] ));
+  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
+    .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), 
+    .F1(un1_FS_14_i_a2_0_1));
+  SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
+    .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), 
+    .F1(un1_FS_13_i_a2_1));
+  SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), 
+    .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
+    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
+    .Q1(\Bank[1] ));
+  SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), 
+    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), 
+    .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
+    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
+  SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), 
+    .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
+    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
+    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
+  SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
+    .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
+    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
+    .F1(N_155), .Q1(CmdUFMCS));
+  SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), 
+    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
+    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
+  SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
+    .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), 
+    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
+  SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), 
+    .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), 
+    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
+    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
+  SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
+    .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
+    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
+  SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), 
+    .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), 
+    .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), 
+    .Q1(CBR_fast));
+  SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), 
+    .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
+    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
+  SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), 
+    .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
+    .Q1(\RowA[9] ));
+  SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), 
+    .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), 
+    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
+    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
+  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), 
+    .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), 
+    .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), 
+    .F1(N_132));
+  SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), 
+    .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
+    .Q1(\RBA_c[1] ));
+  SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), 
+    .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), 
+    .F1(UFMSDI_ens2_i_a2_4_2));
+  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), 
+    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), 
+    .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
+    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
+  SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
+    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
+  SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), 
+    .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), 
+    .F1(UFMSDI_r_xx_mm_1));
+  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), 
+    .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
+    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
+  SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
+    .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
+  SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), 
+    .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), 
+    .F1(un1_CMDWR));
+  SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
+    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
+    .F1(\RA_c[7] ));
+  SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
+    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
+    .F1(\RA_c[6] ));
+  SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
+    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
+    .F1(\RA_c[5] ));
+  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), 
+    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
+    .Q0(\RA_c[10] ), .F1(N_159_i));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
+    .RD0(RD[0]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
+  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
+  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
+  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
+  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
+  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
+  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
+  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
+  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
+  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
+  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
+  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
+  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
+    .RD7(RD[7]));
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
+    .RD6(RD[6]));
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
+    .RD5(RD[5]));
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
+    .RD4(RD[4]));
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
+    .RD3(RD[3]));
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
+    .RD2(RD[2]));
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
+    .RD1(RD[1]));
+  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
+  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
+  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
+  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
+  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
+  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
+  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
+  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
+  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
+  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
+  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
+  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
+  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
+  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
+  LED LED_I( .PADDO(LED_c), .LED(LED));
+  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
+  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
+  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
+  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
+  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
+  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
+  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
+  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
+  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
+  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
+  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
+  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
+  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
+  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
+  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
+  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
+  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
+  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
+  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
+  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
+  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
+  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
+  VHI VHI_INST( .Z(VCCI));
+  PUR PUR_INST( .PUR(VCCI));
+  GSR GSR_INST( .GSR(VCCI));
+  VLO VLO_INST( .Z(GNDI_TSALL));
+  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
+endmodule
+
+module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
+         A1_dly, CLK_dly, A0_dly;
+
+  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
+    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+  endspecify
+
+endmodule
+
+module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module vcc ( output PWR1 );
+
+  VHI INST1( .Z(PWR1));
+endmodule
+
+module gnd ( output PWR0 );
+
+  VLO INST1( .Z(PWR0));
+endmodule
+
+module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h300a;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
+  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
+    .CO1());
+
+  specify
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h5002;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
+
+  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40002 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module inverter ( input I, output Z );
+
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40004 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40005 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40006 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
+  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
+         CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(\SLICE_20/SLICE_20_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
+  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
+    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40009 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40010 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40011 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40012 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40013 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40014 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40020 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40025 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40032 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40033 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40034 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40035 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40036 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40037 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40038 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40039 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40040 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40041 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40042 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40045 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40046 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40047 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40048 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40049 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40050 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40051 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40053 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40054 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
+         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
+
+  lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
+  lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
+  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
+    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
+    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40055 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40056 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40058 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40061 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40062 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
+
+  lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40063 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40064 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
+
+  lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40065 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+
+  lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40066 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40067 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40068 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40070 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40071 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40072 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, M0_dly, CLK_dly;
+
+  lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40073 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40074 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40075 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40076 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40077 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40078 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40079 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40080 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
+
+  lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40081 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
+
+  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
+
+  specify
+    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD0) = (0:0:0,0:0:0);
+    (RD0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD0, 0:0:0);
+    $width (negedge RD0, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf ( input I, T, output Z, PAD, input PADI );
+
+  IB INST1( .I(PADI), .O(Z));
+  OBW INST2( .I(I), .T(T), .O(PAD));
+endmodule
+
+module Dout_0_ ( input PADDO, output Dout0 );
+
+  mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+
+  specify
+    (PADDO => Dout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0082 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module PHI2 ( output PADDI, input PHI2 );
+
+  mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+
+  specify
+    (PHI2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge PHI2, 0:0:0);
+    $width (negedge PHI2, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0083 ( output Z, input PAD );
+
+  IBPD INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDO ( output PADDI, input UFMSDO );
+
+  mjiobuf0084 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
+
+  specify
+    (UFMSDO => PADDI) = (0:0:0,0:0:0);
+    $width (posedge UFMSDO, 0:0:0);
+    $width (negedge UFMSDO, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0084 ( output Z, input PAD );
+
+  IB INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDI ( input PADDO, output UFMSDI );
+
+  mjiobuf0085 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
+
+  specify
+    (PADDO => UFMSDI) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0085 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module UFMCLK ( input PADDO, output UFMCLK );
+
+  mjiobuf0085 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
+
+  specify
+    (PADDO => UFMCLK) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nUFMCS ( input PADDO, output nUFMCS );
+
+  mjiobuf0085 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
+
+  specify
+    (PADDO => nUFMCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQML ( input PADDO, output RDQML );
+
+  mjiobuf0085 RDQML_pad( .I(PADDO), .PAD(RDQML));
+
+  specify
+    (PADDO => RDQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQMH ( input PADDO, output RDQMH );
+
+  mjiobuf0085 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+
+  specify
+    (PADDO => RDQMH) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRCAS ( input PADDO, output nRCAS );
+
+  mjiobuf0085 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
+
+  specify
+    (PADDO => nRCAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRRAS ( input PADDO, output nRRAS );
+
+  mjiobuf0085 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
+
+  specify
+    (PADDO => nRRAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRWE ( input PADDO, output nRWE );
+
+  mjiobuf0085 nRWE_pad( .I(PADDO), .PAD(nRWE));
+
+  specify
+    (PADDO => nRWE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCKE ( input PADDO, output RCKE );
+
+  mjiobuf0085 RCKE_pad( .I(PADDO), .PAD(RCKE));
+
+  specify
+    (PADDO => RCKE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCLK ( output PADDI, input RCLK );
+
+  mjiobuf0084 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+
+  specify
+    (RCLK => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RCLK, 0:0:0);
+    $width (negedge RCLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module nRCS ( input PADDO, output nRCS );
+
+  mjiobuf0085 nRCS_pad( .I(PADDO), .PAD(nRCS));
+
+  specify
+    (PADDO => nRCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
+
+  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
+
+  specify
+    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD7) = (0:0:0,0:0:0);
+    (RD7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD7, 0:0:0);
+    $width (negedge RD7, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
+
+  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
+
+  specify
+    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD6) = (0:0:0,0:0:0);
+    (RD6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD6, 0:0:0);
+    $width (negedge RD6, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
+
+  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
+
+  specify
+    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD5) = (0:0:0,0:0:0);
+    (RD5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD5, 0:0:0);
+    $width (negedge RD5, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
+
+  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
+
+  specify
+    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD4) = (0:0:0,0:0:0);
+    (RD4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD4, 0:0:0);
+    $width (negedge RD4, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
+
+  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
+
+  specify
+    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD3) = (0:0:0,0:0:0);
+    (RD3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD3, 0:0:0);
+    $width (negedge RD3, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
+
+  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
+
+  specify
+    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD2) = (0:0:0,0:0:0);
+    (RD2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD2, 0:0:0);
+    $width (negedge RD2, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
+
+  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
+
+  specify
+    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD1) = (0:0:0,0:0:0);
+    (RD1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD1, 0:0:0);
+    $width (negedge RD1, 0:0:0);
+  endspecify
+
+endmodule
+
+module RA_11_ ( input PADDO, output RA11 );
+
+  mjiobuf0085 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
+
+  specify
+    (PADDO => RA11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_10_ ( input PADDO, output RA10 );
+
+  mjiobuf0085 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
+
+  specify
+    (PADDO => RA10) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_9_ ( input PADDO, output RA9 );
+
+  mjiobuf0085 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+
+  specify
+    (PADDO => RA9) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_8_ ( input PADDO, output RA8 );
+
+  mjiobuf0085 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+
+  specify
+    (PADDO => RA8) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_7_ ( input PADDO, output RA7 );
+
+  mjiobuf0085 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+
+  specify
+    (PADDO => RA7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_6_ ( input PADDO, output RA6 );
+
+  mjiobuf0085 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+
+  specify
+    (PADDO => RA6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_5_ ( input PADDO, output RA5 );
+
+  mjiobuf0085 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+
+  specify
+    (PADDO => RA5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_4_ ( input PADDO, output RA4 );
+
+  mjiobuf0085 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+
+  specify
+    (PADDO => RA4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_3_ ( input PADDO, output RA3 );
+
+  mjiobuf0085 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+
+  specify
+    (PADDO => RA3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_2_ ( input PADDO, output RA2 );
+
+  mjiobuf0085 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+
+  specify
+    (PADDO => RA2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_1_ ( input PADDO, output RA1 );
+
+  mjiobuf0085 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+
+  specify
+    (PADDO => RA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_0_ ( input PADDO, output RA0 );
+
+  mjiobuf0085 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+
+  specify
+    (PADDO => RA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_1_ ( input PADDO, output RBA1 );
+
+  mjiobuf0085 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
+
+  specify
+    (PADDO => RBA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_0_ ( input PADDO, output RBA0 );
+
+  mjiobuf0085 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
+
+  specify
+    (PADDO => RBA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module LED ( input PADDO, output LED );
+
+  mjiobuf0086 LED_pad( .I(PADDO), .PAD(LED));
+
+  specify
+    (PADDO => LED) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0086 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module nFWE ( output PADDI, input nFWE );
+
+  mjiobuf0084 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+
+  specify
+    (nFWE => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nFWE, 0:0:0);
+    $width (negedge nFWE, 0:0:0);
+  endspecify
+
+endmodule
+
+module nCRAS ( output PADDI, input nCRAS );
+
+  mjiobuf0087 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+
+  specify
+    (nCRAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCRAS, 0:0:0);
+    $width (negedge nCRAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0087 ( output Z, input PAD );
+
+  IBPU INST1( .I(PAD), .O(Z));
+endmodule
+
+module nCCAS ( output PADDI, input nCCAS );
+
+  mjiobuf0087 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+
+  specify
+    (nCCAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCCAS, 0:0:0);
+    $width (negedge nCCAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_7_ ( input PADDO, output Dout7 );
+
+  mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+
+  specify
+    (PADDO => Dout7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_6_ ( input PADDO, output Dout6 );
+
+  mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+
+  specify
+    (PADDO => Dout6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_5_ ( input PADDO, output Dout5 );
+
+  mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+
+  specify
+    (PADDO => Dout5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_4_ ( input PADDO, output Dout4 );
+
+  mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+
+  specify
+    (PADDO => Dout4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_3_ ( input PADDO, output Dout3 );
+
+  mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+
+  specify
+    (PADDO => Dout3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_2_ ( input PADDO, output Dout2 );
+
+  mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+
+  specify
+    (PADDO => Dout2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_1_ ( input PADDO, output Dout1 );
+
+  mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+
+  specify
+    (PADDO => Dout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Din_7_ ( output PADDI, input Din7 );
+
+  mjiobuf0084 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+
+  specify
+    (Din7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din7, 0:0:0);
+    $width (negedge Din7, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_6_ ( output PADDI, input Din6 );
+
+  mjiobuf0084 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+
+  specify
+    (Din6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din6, 0:0:0);
+    $width (negedge Din6, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_5_ ( output PADDI, input Din5 );
+
+  mjiobuf0084 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+
+  specify
+    (Din5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din5, 0:0:0);
+    $width (negedge Din5, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_4_ ( output PADDI, input Din4 );
+
+  mjiobuf0084 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+
+  specify
+    (Din4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din4, 0:0:0);
+    $width (negedge Din4, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_3_ ( output PADDI, input Din3 );
+
+  mjiobuf0084 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+
+  specify
+    (Din3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din3, 0:0:0);
+    $width (negedge Din3, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_2_ ( output PADDI, input Din2 );
+
+  mjiobuf0084 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+
+  specify
+    (Din2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din2, 0:0:0);
+    $width (negedge Din2, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_1_ ( output PADDI, input Din1 );
+
+  mjiobuf0084 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+
+  specify
+    (Din1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din1, 0:0:0);
+    $width (negedge Din1, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_0_ ( output PADDI, input Din0 );
+
+  mjiobuf0084 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+
+  specify
+    (Din0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din0, 0:0:0);
+    $width (negedge Din0, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_1_ ( output PADDI, input CROW1 );
+
+  mjiobuf0084 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+
+  specify
+    (CROW1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW1, 0:0:0);
+    $width (negedge CROW1, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_0_ ( output PADDI, input CROW0 );
+
+  mjiobuf0084 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+
+  specify
+    (CROW0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW0, 0:0:0);
+    $width (negedge CROW0, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_9_ ( output PADDI, input MAin9 );
+
+  mjiobuf0084 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+
+  specify
+    (MAin9 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin9, 0:0:0);
+    $width (negedge MAin9, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_8_ ( output PADDI, input MAin8 );
+
+  mjiobuf0084 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+
+  specify
+    (MAin8 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin8, 0:0:0);
+    $width (negedge MAin8, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_7_ ( output PADDI, input MAin7 );
+
+  mjiobuf0084 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+
+  specify
+    (MAin7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin7, 0:0:0);
+    $width (negedge MAin7, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_6_ ( output PADDI, input MAin6 );
+
+  mjiobuf0084 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+
+  specify
+    (MAin6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin6, 0:0:0);
+    $width (negedge MAin6, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_5_ ( output PADDI, input MAin5 );
+
+  mjiobuf0084 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+
+  specify
+    (MAin5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin5, 0:0:0);
+    $width (negedge MAin5, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_4_ ( output PADDI, input MAin4 );
+
+  mjiobuf0084 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+
+  specify
+    (MAin4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin4, 0:0:0);
+    $width (negedge MAin4, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_3_ ( output PADDI, input MAin3 );
+
+  mjiobuf0084 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+
+  specify
+    (MAin3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin3, 0:0:0);
+    $width (negedge MAin3, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_2_ ( output PADDI, input MAin2 );
+
+  mjiobuf0084 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+
+  specify
+    (MAin2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin2, 0:0:0);
+    $width (negedge MAin2, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_1_ ( output PADDI, input MAin1 );
+
+  mjiobuf0084 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+
+  specify
+    (MAin1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin1, 0:0:0);
+    $width (negedge MAin1, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_0_ ( output PADDI, input MAin0 );
+
+  mjiobuf0084 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+
+  specify
+    (MAin0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin0, 0:0:0);
+    $width (negedge MAin0, 0:0:0);
+  endspecify
+
+endmodule
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
index 90f3ed2..63745f3 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
@@ -15,17 +15,15 @@
 
 Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial -ioreg
      b RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
-     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/
-     Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplif
-     y.lpf -lpf
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c
-     0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf
+     Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf
+     -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO.lpf -c 0 -gui -msgset
+     Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO256CTQFP100
 Target Performance:   3
 Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/16/23  04:50:39
+Mapped on:  08/19/23  20:53:19
 
 
 Design Summary
@@ -67,9 +65,9 @@ Mapped on:  08/16/23  04:50:39
      Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
      Net RASr2: 2 loads, 2 LSLICEs
      Net Ready_fast: 7 loads, 7 LSLICEs
-
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
+
      Net InitReady: 16 loads
      Net Ready: 16 loads
      Net S[1]: 13 loads
@@ -127,9 +125,9 @@ Mapped on:  08/16/23  04:50:39
 +---------------------+-----------+-----------+------------+------------+
 | nRWE                | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
-
 | RCKE                | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
+
 | RCLK                | INPUT     | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
 | nRCS                | OUTPUT    | LVCMOS33  |            |            |
@@ -184,9 +182,9 @@ Mapped on:  08/16/23  04:50:39
 +---------------------+-----------+-----------+------------+------------+
 | nCCAS               | INPUT     | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
-
 | Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
+
 | Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
 | Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
@@ -244,6 +242,8 @@ Mapped on:  08/16/23  04:50:39
 
 
 
+
+
 Removed logic
 
 Block GSR_INST undriven or does not drive anything - clipped.
@@ -285,7 +285,7 @@ Block VCC was optimized away.
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 29 MB
+   Peak Memory Usage: 50 MB
         
 
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_ngd.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_ngd.asd
index c265c78..8440a7e 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_ngd.asd
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_ngd.asd
@@ -1 +1 @@
-[ActiveSupport NGD]
+[ActiveSupport NGD]
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
index b7ff036..79408b2 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.19
 
-Wed Aug 16 04:50:47 2023
+Sat Aug 19 20:53:29 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+------+----------------------------------+
@@ -276,7 +276,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:47 2023
+Sat Aug 19 20:53:29 2023
 
 
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
index ccd443c..c0c129b 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
@@ -12,12 +12,12 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:41 2023
+Sat Aug 19 20:53:22 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
 RAM2GS_LCMXO256C_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
+Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
 
 
 Preference file: RAM2GS_LCMXO256C_impl1.prf.
@@ -26,22 +26,22 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            8.213        0            0.273        0            06           Completed
+5_1   *      0            8.213        0            0.273        0            08           Completed
 * : Design saved.
 
-Total (real) run time for 1-seed: 6 secs 
+Total (real) run time for 1-seed: 8 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Wed Aug 16 04:50:41 2023
+Sat Aug 19 20:53:22 2023
 
 
 Best Par Run
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
 Preference file: RAM2GS_LCMXO256C_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
@@ -90,12 +90,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 .................
 Placer score = 582801.
-Finished Placer Phase 1.  REAL time: 6 secs 
+Finished Placer Phase 1.  REAL time: 7 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  582334
-Finished Placer Phase 2.  REAL time: 6 secs 
+Finished Placer Phase 2.  REAL time: 7 secs 
 
 
 
@@ -130,7 +130,7 @@ I/O Bank Usage Summary:
 | 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 5 secs 
+Total placer CPU time: 7 secs 
 
 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
 
@@ -142,9 +142,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=8 clock_loads=4
 
-Completed router resource preassignment. Real time: 6 secs 
+Completed router resource preassignment. Real time: 8 secs 
 
-Start NBR router at 04:50:47 08/16/23
+Start NBR router at 20:53:30 08/19/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -159,41 +159,41 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 04:50:47 08/16/23
+Start NBR special constraint process at 20:53:30 08/19/23
 
-Start NBR section for initial routing at 04:50:47 08/16/23
+Start NBR section for initial routing at 20:53:30 08/19/23
 Level 1, iteration 1
 0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 8 secs 
 Level 2, iteration 1
 0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 8 secs 
 Level 3, iteration 1
 0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.405ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.405ns/0.000ns; real time: 8 secs 
 Level 4, iteration 1
 10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 8 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 04:50:47 08/16/23
+Start NBR section for normal routing at 20:53:30 08/19/23
 Level 4, iteration 1
 5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 8 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 8 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:47 08/16/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:53:30 08/19/23
 
-Start NBR section for re-routing at 04:50:47 08/16/23
+Start NBR section for re-routing at 20:53:30 08/19/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 8 secs 
 
-Start NBR section for post-routing at 04:50:47 08/16/23
+Start NBR section for post-routing at 20:53:30 08/19/23
 
 End NBR router with 0 unrouted connection
 
@@ -211,8 +211,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=8 clock_loads=4
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+Total CPU time 8 secs 
+Total REAL time: 8 secs 
 Completely routed.
 End of route.  633 routed (100.00%); 0 unrouted.
 
@@ -234,8 +234,8 @@ PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 8 secs 
+Total REAL time to completion: 8 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt
index 1ea018d..7cd5bf3 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt
@@ -1,59 +1,59 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-
-# Written on Wed Aug 16 04:50:33 2023
-
-##### FILES SYNTAX CHECKED ##############################################
-Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
-
-#Run constraint checker to find more issues with constraints.
-#########################################################################
-
-
-
-No issues found in constraint syntax.
-
-
-
-Clock Summary
-*************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-Clock Load Summary
-******************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+
+# Written on Sat Aug 19 20:53:13 2023
+
+##### FILES SYNTAX CHECKED ##############################################
+Constraint File(s):      "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
+
+#Run constraint checker to find more issues with constraints.
+#########################################################################
+
+
+
+No issues found in constraint syntax.
+
+
+
+Clock Summary
+*************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+Clock Load Summary
+******************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
index cb134d2..6269b4a 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
@@ -24,7 +24,7 @@
 
 
 Last Process:
-VHDL Simulation File
+IBIS Model
 State:
 Passed
 
@@ -48,7 +48,7 @@
 
 
 Logic preference file:
-RAM2GS_LCMXO256C.lpf
+RAM2GS-LCMXO.lpf
 
 
 Physical Preference file:
@@ -62,15 +62,15 @@
 
 
 Updated:
-2023/08/16 05:03:18
+2023/08/20 05:55:46
 
 
 Implementation Location:
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1
+Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1
 
 
 Project File:
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf
+Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf
 
 
 
    
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html
index 682b70c..860c5d7 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html
@@ -10,9 +10,9 @@
 #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
 #install: C:\lscc\diamond\3.12\synpbase
 #OS: Windows 8 6.2
-#Hostname: ZANEPC
+#Hostname: ZANEMACWIN11
 
-# Wed Aug 16 04:50:31 2023
+# Sat Aug 19 20:53:10 2023
 
 #Implementation: impl1
 
@@ -27,7 +27,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -45,7 +45,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -57,29 +57,27 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
+Options changed - recompiling
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
 
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:31 2023
+# Sat Aug 19 20:53:11 2023
 
 ###########################################################]
 ###########################################################[
@@ -94,34 +92,34 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:31 2023
+# Sat Aug 19 20:53:11 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
 
 @END
 
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:31 2023
+# Sat Aug 19 20:53:11 2023
 
 ###########################################################]
 ###########################################################[
@@ -136,7 +134,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -144,15 +142,17 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 @N|Running in 64-bit mode
 File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:32 2023
+# Sat Aug 19 20:53:12 2023
 
 ###########################################################]
-# Wed Aug 16 04:50:33 2023
+Premap Report
+
+# Sat Aug 19 20:53:12 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -165,34 +165,34 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
 
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
 
 @N: FX493 |Applying initial value "0" on instance InitReady.
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@@ -218,20 +218,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
 
@@ -298,23 +298,25 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
+# Sat Aug 19 20:53:14 2023
 
 ###########################################################]
-# Wed Aug 16 04:50:35 2023
+Map & Optimize Report
+
+# Sat Aug 19 20:53:14 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -327,70 +329,70 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
@@ -400,9 +402,9 @@ Pass		 CPU time		Worst Slack		Luts / Registers
    4		0h:00m:01s		    -3.23ns		 123 /        89
    5		0h:00m:01s		    -3.23ns		 124 /        89
    6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
 Timing driven replication report
 Added 3 Registers via timing driven replication
 Added 1 LUTs via timing driven replication
@@ -416,29 +418,29 @@ Added 1 LUTs via timing driven replication
   11		0h:00m:01s		    -3.19ns		 127 /        92
   12		0h:00m:01s		    -3.19ns		 127 /        92
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
 
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
@@ -447,7 +449,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
+# Timing report written on Sat Aug 19 20:53:17 2023
 #
 
 
@@ -455,7 +457,7 @@ Top view:               RAM2GS
 Requested Frequency:    2.9 MHz
 Wire load mode:         top
 Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
                        
 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
 
@@ -934,10 +936,10 @@ nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
 
 ---------------------------------------
 Resource Usage Report
@@ -967,10 +969,10 @@ VHI:            1
 VLO:            1
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 196MB)
 
 Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
+# Sat Aug 19 20:53:17 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf
index 2b0f89b..ca24d6c 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf
@@ -1,24 +1,24 @@
-#
-# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
-#
-
-# Period Constraints 
-FREQUENCY PORT "PHI2" 2.9 MHz;
-FREQUENCY PORT "nCCAS" 2.9 MHz;
-FREQUENCY PORT "nCRAS" 2.9 MHz;
-FREQUENCY PORT "RCLK" 62.5 MHz;
-
-
-# Output Constraints 
-
-# Input Constraints 
-
-# Point-to-point Delay Constraints 
-
-
-
-# Block Path Constraints 
-
-BLOCK ASYNCPATHS;
-
-# End of generated Logical Preferences.
+#
+# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
+#
+
+# Period Constraints 
+FREQUENCY PORT "PHI2" 2.9 MHz;
+FREQUENCY PORT "nCCAS" 2.9 MHz;
+FREQUENCY PORT "nCRAS" 2.9 MHz;
+FREQUENCY PORT "RCLK" 62.5 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.tcl b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.tcl
index 6c51127..017d401 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.tcl
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.tcl
@@ -1,65 +1,65 @@
-#-- Lattice Semiconductor Corporation Ltd.
-#-- Synplify OEM project file
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO256C
-set_option -package T100C
-set_option -speed_grade -3
-
-#compilation/mapping options
-set_option -symbolic_fsm_compiler true
-set_option -resource_sharing true
-
-#use verilog 2001 standard option
-set_option -vlog_std v2001
-
-#map options
-set_option -frequency 70
-set_option -maxfan 1000
-set_option -auto_constrain_io 0
-set_option -disable_io_insertion false
-set_option -retiming false; set_option -pipe false
-set_option -force_gsr auto
-set_option -compiler_compatible 0
-set_option -dup false
-
-add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc}
-set_option -default_enum_encoding default
-
-#simulation options
-
-
-#timing analysis options
-set_option -num_critical_paths 3
-
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#synplifyPro options
-set_option -fix_gated_and_generated_clocks 1
-set_option -update_models_cp 0
-set_option -resolve_multiple_driver 0
-
-
-set_option -seqshift_no_replicate 0
-
-#-- add_file options
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C}
-add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v}
-
-#-- top module name
-set_option -top_module RAM2GS
-
-#-- set result format/file last
-project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi}
-
-#-- error message log file
-project -log_file {RAM2GS_LCMXO256C_impl1.srf}
-
-#-- set any command lines input by customer
-
-
-#-- run Synplify with 'arrange HDL file'
-project -run -clean
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO256C
+set_option -package T100C
+set_option -speed_grade -3
+
+#compilation/mapping options
+set_option -symbolic_fsm_compiler true
+set_option -resource_sharing true
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 70
+set_option -maxfan 1000
+set_option -auto_constrain_io 0
+set_option -disable_io_insertion false
+set_option -retiming false; set_option -pipe false
+set_option -force_gsr auto
+set_option -compiler_compatible 0
+set_option -dup false
+
+add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
+set_option -default_enum_encoding default
+
+#simulation options
+
+
+#timing analysis options
+set_option -num_critical_paths 3
+
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#synplifyPro options
+set_option -fix_gated_and_generated_clocks 1
+set_option -update_models_cp 0
+set_option -resolve_multiple_driver 0
+
+
+set_option -seqshift_no_replicate 0
+
+#-- add_file options
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO256C}
+add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v}
+
+#-- top module name
+set_option -top_module RAM2GS
+
+#-- set result format/file last
+project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi}
+
+#-- error message log file
+project -log_file {RAM2GS_LCMXO256C_impl1.srf}
+
+#-- set any command lines input by customer
+
+
+#-- run Synplify with 'arrange HDL file'
+project -run -clean
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
index ae0b1f0..664bb71 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:40 2023
+Sat Aug 19 20:53:20 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
 Design file:     ram2gs_lcmxo256c_impl1_map.ncd
 Preference file: ram2gs_lcmxo256c_impl1.prf
 Device,speed:    LCMXO256C,3
@@ -253,7 +253,7 @@ Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:40 2023
+Sat Aug 19 20:53:20 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -263,7 +263,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
 Design file:     ram2gs_lcmxo256c_impl1_map.ncd
 Preference file: ram2gs_lcmxo256c_impl1.prf
 Device,speed:    LCMXO256C,M
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
index 9e01f86..e3d51c1 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:48 2023
+Sat Aug 19 20:53:31 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
 Design file:     ram2gs_lcmxo256c_impl1.ncd
 Preference file: ram2gs_lcmxo256c_impl1.prf
 Device,speed:    LCMXO256C,3
@@ -1223,7 +1223,7 @@ Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:48 2023
+Sat Aug 19 20:53:31 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1233,7 +1233,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
 Design file:     ram2gs_lcmxo256c_impl1.ncd
 Preference file: ram2gs_lcmxo256c_impl1.prf
 Device,speed:    LCMXO256C,m
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.sdf
index f861f76..86eb853 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.sdf
@@ -1,2927 +1,2927 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:50 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1_SLICE_65I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_B")
-    (INSTANCE RD_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_B")
-    (INSTANCE Dout_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2B")
-    (INSTANCE PHI2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2S) (1250:1250:1250))
-      (WIDTH (negedge PHI2S) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDOB")
-    (INSTANCE UFMSDOI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
-      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDIB")
-    (INSTANCE UFMSDII)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLKB")
-    (INSTANCE UFMCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCSB")
-    (INSTANCE nUFMCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMLB")
-    (INSTANCE RDQMLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMHB")
-    (INSTANCE RDQMHI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCASB")
-    (INSTANCE nRCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRASB")
-    (INSTANCE nRRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWEB")
-    (INSTANCE nRWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKEB")
-    (INSTANCE RCKEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLKB")
-    (INSTANCE RCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLKS) (1250:1250:1250))
-      (WIDTH (negedge RCLKS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCSB")
-    (INSTANCE nRCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_B")
-    (INSTANCE RD_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_B")
-    (INSTANCE RD_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_B")
-    (INSTANCE RD_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_B")
-    (INSTANCE RD_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_B")
-    (INSTANCE RD_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_B")
-    (INSTANCE RD_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_B")
-    (INSTANCE RD_1_I0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_B")
-    (INSTANCE RA_11_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_B")
-    (INSTANCE RA_10_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_B")
-    (INSTANCE RA_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_B")
-    (INSTANCE RA_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_B")
-    (INSTANCE RA_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_B")
-    (INSTANCE RA_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_B")
-    (INSTANCE RA_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_B")
-    (INSTANCE RA_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_B")
-    (INSTANCE RA_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_B")
-    (INSTANCE RA_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_B")
-    (INSTANCE RA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_B")
-    (INSTANCE RA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_B")
-    (INSTANCE RBA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_B")
-    (INSTANCE RBA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LEDB")
-    (INSTANCE LEDI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWEB")
-    (INSTANCE nFWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWES) (1250:1250:1250))
-      (WIDTH (negedge nFWES) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRASB")
-    (INSTANCE nCRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRASS) (1250:1250:1250))
-      (WIDTH (negedge nCRASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCASB")
-    (INSTANCE nCCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCASS) (1250:1250:1250))
-      (WIDTH (negedge nCCASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_B")
-    (INSTANCE Dout_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_B")
-    (INSTANCE Dout_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_B")
-    (INSTANCE Dout_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_B")
-    (INSTANCE Dout_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_B")
-    (INSTANCE Dout_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_B")
-    (INSTANCE Dout_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_B")
-    (INSTANCE Dout_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_B")
-    (INSTANCE Din_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_B")
-    (INSTANCE Din_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_B")
-    (INSTANCE Din_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_B")
-    (INSTANCE Din_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_B")
-    (INSTANCE Din_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_B")
-    (INSTANCE Din_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_B")
-    (INSTANCE Din_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_B")
-    (INSTANCE Din_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_B")
-    (INSTANCE CROW_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_B")
-    (INSTANCE CROW_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_B")
-    (INSTANCE MAin_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_B")
-    (INSTANCE MAin_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_B")
-    (INSTANCE MAin_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_B")
-    (INSTANCE MAin_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_B")
-    (INSTANCE MAin_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_B")
-    (INSTANCE MAin_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_B")
-    (INSTANCE MAin_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_B")
-    (INSTANCE MAin_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_B")
-    (INSTANCE MAin_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_B")
-    (INSTANCE MAin_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (1232:1375:1519)(1232:1375:1519))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/B0 (1203:1339:1475)(1203:1339:1475))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/D1 (588:652:716)(588:652:716))
-        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/A1 (1146:1276:1406)(1146:1276:1406))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C0 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/C1 (1151:1263:1376)(1151:1263:1376))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (908:1011:1114)(908:1011:1114))
-        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B0 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/A1 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/C1 (1118:1249:1380)(1118:1249:1380))
-        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/D1 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/D0 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (1663:1816:1970)(1663:1816:1970))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (1260:1384:1509)(1260:1384:1509))
-        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/D1 (1001:1094:1188)(1001:1094:1188))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/B0 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/B1 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/B1 (1316:1448:1580)(1316:1448:1580))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/B0 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (1245:1393:1541)(1245:1393:1541))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (1648:1825:2002)(1648:1825:2002))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (1131:1266:1402)(1131:1266:1402))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C0 (1131:1266:1402)(1131:1266:1402))
-        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (1652:1794:1936)(1652:1794:1936))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/C0 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/A1 (1663:1816:1970)(1663:1816:1970))
-        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (1844:2015:2186)(1844:2015:2186))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/D0 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/D1 (595:663:731)(595:663:731))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A0 (864:963:1063)(864:963:1063))
-        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/D0 (1497:1620:1743)(1497:1620:1743))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (603:667:731)(603:667:731))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/B1 (918:1020:1123)(918:1020:1123))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/D0 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (1232:1375:1519)(1232:1375:1519))
-        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (1675:1841:2008)(1675:1841:2008))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (1561:1715:1869)(1561:1715:1869))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/A1 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_78I/F0 SLICE_9I/D1 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_85I/F1 SLICE_9I/C1 (1087:1218:1349)(1087:1218:1349))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/B1 (1843:2032:2222)(1843:2032:2222))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (1203:1325:1448)(1203:1325:1448))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/C0 (1683:1853:2023)(1683:1853:2023))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (1528:1679:1830)(1528:1679:1830))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/D1 (2744:2982:3221)(2744:2982:3221))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/D0 (2744:2982:3221)(2744:2982:3221))
-        (INTERCONNECT SLICE_70I/F1 SLICE_9I/A1 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/A1 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/A0 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70I/F1 SLICE_67I/A0 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70I/F1 SLICE_70I/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_70I/F1 SLICE_90I/B1 (1317:1447:1578)(1317:1447:1578))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/D0 (517:575:634)(517:575:634))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/B1 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_9I/F1 SLICE_9I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_9I/F1 SLICE_20I/D0 (261:290:320)(261:290:320))
-        (INTERCONNECT SLICE_14I/F1 SLICE_9I/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_14I/F1 SLICE_14I/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (559:618:678)(559:618:678))
-        (INTERCONNECT SLICE_70I/F0 SLICE_9I/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (2182:2416:2650)(2182:2416:2650))
-        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT SLICE_77I/F0 SLICE_14I/D1 (564:632:700)(564:632:700))
-        (INTERCONNECT SLICE_76I/F0 SLICE_14I/C1 (1530:1676:1822)(1530:1676:1822))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (1225:1351:1478)(1225:1351:1478))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (1525:1685:1846)(1525:1685:1846))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/B0 (1540:1705:1870)(1540:1705:1870))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/A0 (1879:2062:2246)(1879:2062:2246))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/C0 (1373:1516:1660)(1373:1516:1660))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/D0 (1225:1351:1478)(1225:1351:1478))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/C1 (1784:1959:2134)(1784:1959:2134))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/B0 (1541:1706:1872)(1541:1706:1872))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/B0 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/B0 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/D1 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (2110:2331:2552)(2110:2331:2552))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/C1 (2657:2925:3193)(2657:2925:3193))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A0 (2482:2728:2974)(2482:2728:2974))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/C1 (2365:2598:2832)(2365:2598:2832))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (2110:2331:2552)(2110:2331:2552))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (2620:2864:3109)(2620:2864:3109))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/A1 (2054:2267:2480)(2054:2267:2480))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/D1 (1793:1977:2161)(1793:1977:2161))
-        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (2210:2424:2639)
-          (2210:2424:2639))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/B1 (895:1001:1108)(895:1001:1108))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C1 (763:846:930)(763:846:930))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C0 (763:846:930)(763:846:930))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/C1 (1581:1730:1879)(1581:1730:1879))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (1769:1942:2115)(1769:1942:2115))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C1 (2019:2202:2385)(2019:2202:2385))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C0 (2019:2202:2385)(2019:2202:2385))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/D0 (1454:1588:1723)(1454:1588:1723))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/C1 (757:844:932)(757:844:932))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/C0 (757:844:932)(757:844:932))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/C1 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/C0 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/C0 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (878:975:1072)(878:975:1072))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/B1 (938:1041:1144)(938:1041:1144))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C0 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/C1 (1181:1293:1406)(1181:1293:1406))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/A0 (892:988:1084)(892:988:1084))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (1362:1496:1631)
-          (1362:1496:1631))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (1362:1496:1631)
-          (1362:1496:1631))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/A1 (1316:1443:1571)(1316:1443:1571))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/D0 (1047:1143:1239)(1047:1143:1239))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/C0 (718:795:873)(718:795:873))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/A1 (1286:1409:1533)(1286:1409:1533))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A1 (825:914:1004)(825:914:1004))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/B1 (1424:1556:1689)(1424:1556:1689))
-        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F1 SLICE_43I/A0 (849:948:1048)(849:948:1048))
-        (INTERCONNECT SLICE_19I/F1 SLICE_44I/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A1 (810:899:989)(810:899:989))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/D0 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_90I/F1 SLICE_20I/C0 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/F1 SLICE_21I/D1 (321:350:380)(321:350:380))
-        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (640:708:776)(640:708:776))
-        (INTERCONNECT SLICE_75I/F1 SLICE_67I/D1 (1047:1139:1231)(1047:1139:1231))
-        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (476:524:573)(476:524:573))
-        (INTERCONNECT SLICE_75I/F1 SLICE_82I/C1 (476:524:573)(476:524:573))
-        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (901:997:1094)(901:997:1094))
-        (INTERCONNECT Din_5_I/PADDI SLICE_21I/B1 (1546:1711:1877)(1546:1711:1877))
-        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (2468:2685:2903)(2468:2685:2903))
-        (INTERCONNECT Din_5_I/PADDI SLICE_67I/B1 (1949:2143:2338)(1949:2143:2338))
-        (INTERCONNECT Din_5_I/PADDI SLICE_75I/B0 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din_5_I/PADDI SLICE_76I/B1 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (1962:2156:2351)(1962:2156:2351))
-        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din_5_I/PADDI SLICE_82I/A1 (1500:1658:1817)(1500:1658:1817))
-        (INTERCONNECT Din_5_I/PADDI SLICE_82I/A0 (1500:1658:1817)(1500:1658:1817))
-        (INTERCONNECT Din_5_I/PADDI SLICE_85I/D0 (1944:2137:2330)(1944:2137:2330))
-        (INTERCONNECT Din_3_I/PADDI SLICE_21I/A1 (1398:1552:1707)(1398:1552:1707))
-        (INTERCONNECT Din_3_I/PADDI SLICE_57I/A1 (988:1113:1238)(988:1113:1238))
-        (INTERCONNECT Din_3_I/PADDI SLICE_67I/C1 (1556:1731:1906)(1556:1731:1906))
-        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (712:804:897)(712:804:897))
-        (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (988:1113:1238)(988:1113:1238))
-        (INTERCONNECT Din_3_I/PADDI SLICE_78I/D1 (709:801:894)(709:801:894))
-        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D1 (1418:1575:1733)(1418:1575:1733))
-        (INTERCONNECT Din_3_I/PADDI SLICE_82I/C0 (1277:1418:1560)(1277:1418:1560))
-        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (712:804:897)(712:804:897))
-        (INTERCONNECT SLICE_75I/F0 SLICE_21I/D0 (245:274:304)(245:274:304))
-        (INTERCONNECT SLICE_21I/F1 SLICE_21I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_21I/F1 SLICE_26I/A0 (853:947:1042)(853:947:1042))
-        (INTERCONNECT SLICE_82I/F1 SLICE_21I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/A0 (1514:1694:1875)(1514:1694:1875))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (1674:1856:2038)(1674:1856:2038))
-        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (1285:1433:1581)(1285:1433:1581))
-        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (921:1020:1119)(921:1020:1119))
-        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (1696:1875:2055)(1696:1875:2055))
-        (INTERCONNECT SLICE_67I/F0 SLICE_67I/A1 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_67I/F0 SLICE_82I/D0 (986:1100:1215)(986:1100:1215))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/A0 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (1682:1846:2010)(1682:1846:2010))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/C1 (1201:1313:1426)(1201:1313:1426))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A1 (854:945:1036)(854:945:1036))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A0 (575:636:697)(575:636:697))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/C0 (1611:1753:1895)(1611:1753:1895))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D1 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D0 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/C1 (2035:2209:2383)(2035:2209:2383))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/B1 (1769:1941:2114)(1769:1941:2114))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/B1 (1771:1932:2094)(1771:1932:2094))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/C1 (740:818:897)(740:818:897))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/C0 (740:818:897)(740:818:897))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/C1 (784:866:948)(784:866:948))
-        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/A0 (1746:1903:2061)
-          (1746:1903:2061))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B1 (1777:1952:2127)(1777:1952:2127))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B0 (1777:1952:2127)(1777:1952:2127))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/D1 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/B1 (1302:1432:1563)(1302:1432:1563))
-        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/C1 (1103:1234:1365)(1103:1234:1365))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/A1 (1260:1384:1509)(1260:1384:1509))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (544:603:663)(544:603:663))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/D1 (991:1084:1177)(991:1084:1177))
-        (INTERCONNECT SLICE_82I/F0 SLICE_22I/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/F1 SLICE_68I/C0 (1133:1244:1356)(1133:1244:1356))
-        (INTERCONNECT SLICE_22I/F1 SLICE_69I/C0 (1133:1244:1356)(1133:1244:1356))
-        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_78I/F1 SLICE_78I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/B0 (899:1000:1102)(899:1000:1102))
-        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/C0 (1936:2106:2276)(1936:2106:2276))
-        (INTERCONNECT SLICE_26I/F1 SLICE_26I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/F1 SLICE_29I/D1 (584:647:710)(584:647:710))
-        (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/C1 (726:803:880)(726:803:880))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/D0 (571:629:687)(571:629:687))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D1 (643:708:773)(643:708:773))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D0 (643:708:773)(643:708:773))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/C0 (798:882:966)(798:882:966))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/D1 (1534:1657:1781)(1534:1657:1781))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/D0 (932:1031:1131)(932:1031:1131))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/B0 (2655:2875:3095)(2655:2875:3095))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (1300:1448:1596)(1300:1448:1596))
-        (INTERCONNECT SLICE_83I/F1 SLICE_29I/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_83I/F1 SLICE_59I/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_83I/F1 SLICE_61I/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_73I/F1 SLICE_29I/A1 (1297:1422:1547)(1297:1422:1547))
-        (INTERCONNECT SLICE_73I/F1 SLICE_29I/A0 (1297:1422:1547)(1297:1422:1547))
-        (INTERCONNECT SLICE_73I/F1 SLICE_59I/D1 (1109:1203:1297)(1109:1203:1297))
-        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (1062:1179:1297)(1062:1179:1297))
-        (INTERCONNECT SLICE_73I/F1 SLICE_73I/C0 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_73I/F1 SLICE_94I/B1 (871:967:1064)(871:967:1064))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (2198:2404:2610)(2198:2404:2610))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/C0 (733:810:888)(733:810:888))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/B1 (886:982:1079)(886:982:1079))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/C0 (733:810:888)(733:810:888))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/D1 (1490:1629:1769)(1490:1629:1769))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/B1 (2511:2758:3006)(2511:2758:3006))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/B1 (2087:2299:2511)(2087:2299:2511))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/B1 (2087:2299:2511)(2087:2299:2511))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/B1 (1805:1983:2161)(1805:1983:2161))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/B0 (1805:1983:2161)(1805:1983:2161))
-        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (948:1049:1150)(948:1049:1150))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/A0 (1199:1330:1461)(1199:1330:1461))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/A1 (894:993:1093)(894:993:1093))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A1 (907:1003:1099)(907:1003:1099))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A0 (907:1003:1099)(907:1003:1099))
-        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B1 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B1 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B0 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/A1 (1378:1503:1629)(1378:1503:1629))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/C1 (1179:1290:1402)(1179:1290:1402))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/C0 (1179:1290:1402)(1179:1290:1402))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/A1 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D1 (563:621:680)(563:621:680))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D0 (563:621:680)(563:621:680))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/B1 (1424:1556:1689)(1424:1556:1689))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/A1 (1293:1417:1541)(1293:1417:1541))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/A0 (1293:1417:1541)(1293:1417:1541))
-        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_73I/F0 SLICE_31I/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (575:639:703)(575:639:703))
-        (INTERCONNECT SLICE_56I/F0 SLICE_32I/D1 (1352:1480:1609)(1352:1480:1609))
-        (INTERCONNECT SLICE_72I/F1 SLICE_32I/C1 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_72I/F1 SLICE_58I/D1 (291:320:350)(291:320:350))
-        (INTERCONNECT SLICE_72I/F1 SLICE_64I/B1 (929:1030:1132)(929:1030:1132))
-        (INTERCONNECT SLICE_72I/F1 SLICE_72I/C0 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_84I/F1 SLICE_32I/B1 (879:985:1092)(879:985:1092))
-        (INTERCONNECT SLICE_74I/F0 SLICE_32I/B0 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32I/F1 SLICE_87I/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT nCRASI/PADDI SLICE_33I/D1 (2857:3462:4068)(2857:3462:4068))
-        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (3532:4217:4903)(3532:4217:4903))
-        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/D0 (1365:1507:1650)(1365:1507:1650))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/A0 (1681:1846:2012)(1681:1846:2012))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/A1 (1239:1386:1534)(1239:1386:1534))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/A0 (1239:1386:1534)(1239:1386:1534))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/D0 (702:793:885)(702:793:885))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/D0 (1105:1225:1346)(1105:1225:1346))
-        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (939:1052:1165)(939:1052:1165))
-        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_85I/F0 SLICE_39I/D1 (1514:1646:1779)(1514:1646:1779))
-        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A1 (2147:2339:2531)(2147:2339:2531))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A0 (2147:2339:2531)(2147:2339:2531))
-        (INTERCONNECT Din_6_I/PADDI SLICE_39I/D0 (2053:2245:2437)(2053:2245:2437))
-        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (3194:3483:3773)(3194:3483:3773))
-        (INTERCONNECT Din_6_I/PADDI SLICE_75I/B1 (1519:1680:1842)(1519:1680:1842))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/D0 (2081:2276:2472)(2081:2276:2472))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (2388:2619:2851)(2388:2619:2851))
-        (INTERCONNECT Din_6_I/PADDI SLICE_78I/B0 (2396:2630:2864)(2396:2630:2864))
-        (INTERCONNECT Din_6_I/PADDI SLICE_85I/B0 (2799:3062:3325)(2799:3062:3325))
-        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (1313:1442:1571)(1313:1442:1571))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (1850:2013:2177)(1850:2013:2177))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (559:618:678)(559:618:678))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (1842:2003:2164)(1842:2003:2164))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_39I/F1 SLICE_57I/A0 (1767:1931:2095)(1767:1931:2095))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/D1 (960:1076:1193)(960:1076:1193))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/B1 (1967:2185:2404)(1967:2185:2404))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/B1 (1275:1430:1585)(1275:1430:1585))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/D1 (1370:1516:1662)(1370:1516:1662))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (1780:1956:2132)(1780:1956:2132))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/A1 (2097:2301:2505)(2097:2301:2505))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/D1 (2924:3195:3466)(2924:3195:3466))
-        (INTERCONNECT SLICE_43I/F1 SLICE_41I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_41I/F1 SLICE_41I/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (1342:1484:1626)(1342:1484:1626))
-        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/D0 (1352:1480:1609)(1352:1480:1609))
-        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/B0 (1293:1424:1555)(1293:1424:1555))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (2091:2277:2464)(2091:2277:2464))
-        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/C1 (1543:1684:1825)(1543:1684:1825))
-        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/A1 (2060:2242:2425)
-          (2060:2242:2425))
-        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (1978:2217:2456)(1978:2217:2456))
-        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/D0 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_50I/F0 SLICE_43I/A1 (1270:1395:1520)(1270:1395:1520))
-        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (16:16:16)(16:16:16))
-        (INTERCONNECT SLICE_50I/F0 SLICE_61I/D1 (1001:1094:1188)(1001:1094:1188))
-        (INTERCONNECT SLICE_50I/F0 SLICE_62I/C1 (1156:1268:1381)(1156:1268:1381))
-        (INTERCONNECT SLICE_83I/F0 SLICE_43I/B0 (1255:1408:1561)(1255:1408:1561))
-        (INTERCONNECT SLICE_83I/F0 SLICE_44I/A1 (1612:1787:1962)(1612:1787:1962))
-        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/F1 SLICE_44I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/D1 (1375:1502:1629)(1375:1502:1629))
-        (INTERCONNECT SLICE_72I/F0 SLICE_51I/C1 (1126:1237:1348)(1126:1237:1348))
-        (INTERCONNECT SLICE_66I/F0 SLICE_51I/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (1548:1774:2000)(1548:1774:2000))
-        (INTERCONNECT SLICE_51I/F1 SLICE_51I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (1409:1541:1674)(1409:1541:1674))
-        (INTERCONNECT SLICE_64I/F1 SLICE_52I/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (1157:1286:1415)(1157:1286:1415))
-        (INTERCONNECT SLICE_52I/F1 SLICE_52I/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_52I/F1 SLICE_64I/D0 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/D0 (1207:1330:1453)(1207:1330:1453))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (1949:2146:2344)(1949:2146:2344))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/B1 (1914:2103:2292)(1914:2103:2292))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/B0 (1997:2204:2411)(1997:2204:2411))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/D1 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/D0 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D1 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D0 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/A0 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (2426:2645:2865)(2426:2645:2865))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (2426:2645:2865)(2426:2645:2865))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (1898:2093:2289)(1898:2093:2289))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (1898:2093:2289)(1898:2093:2289))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/A1 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B0 (2176:2385:2595)(2176:2385:2595))
-        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (2322:2541:2761)(2322:2541:2761))
-        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (1473:1628:1784)(1473:1628:1784))
-        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (1635:1791:1948)(1635:1791:1948))
-        (INTERCONNECT Din_4_I/PADDI SLICE_77I/D1 (1628:1783:1939)(1628:1783:1939))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (1628:1783:1939)(1628:1783:1939))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/C0 (2072:2281:2490)(2072:2281:2490))
-        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (2787:3031:3276)(2787:3031:3276))
-        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (2787:3031:3276)(2787:3031:3276))
-        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (2225:2440:2655)(2225:2440:2655))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (1818:2004:2190)(1818:2004:2190))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (1818:2004:2190)(1818:2004:2190))
-        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (2377:2592:2807)(2377:2592:2807))
-        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (1564:1720:1877)(1564:1720:1877))
-        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (1798:1981:2164)(1798:1981:2164))
-        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (2042:2305:2568)(2042:2305:2568))
-        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (2630:2955:3280)(2630:2955:3280))
-        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (1260:1386:1513)(1260:1386:1513))
-        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (1126:1237:1348)(1126:1237:1348))
-        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (1332:1457:1583)(1332:1457:1583))
-        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (2232:2447:2663)(2232:2447:2663))
-        (INTERCONNECT Din_7_I/PADDI SLICE_75I/D1 (1515:1665:1815)(1515:1665:1815))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/A1 (2604:2844:3085)(2604:2844:3085))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (2642:2887:3132)(2642:2887:3132))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/A1 (1381:1533:1686)(1381:1533:1686))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/A0 (1381:1533:1686)(1381:1533:1686))
-        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_56I/F1 SLICE_70I/B1 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT Din_0_I/PADDI SLICE_57I/C1 (1277:1418:1559)(1277:1418:1559))
-        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (1839:2026:2214)(1839:2026:2214))
-        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (2242:2458:2675)(2242:2458:2675))
-        (INTERCONNECT Din_0_I/PADDI SLICE_76I/D1 (1532:1683:1835)(1532:1683:1835))
-        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (3049:3329:3610)(3049:3329:3610))
-        (INTERCONNECT Din_0_I/PADDI SLICE_85I/C1 (1566:1741:1917)(1566:1741:1917))
-        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (1437:1597:1758)(1437:1597:1758))
-        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (1129:1252:1375)(1129:1252:1375))
-        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (1411:1566:1722)(1411:1566:1722))
-        (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (1384:1536:1689)(1384:1536:1689))
-        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (1673:1860:2047)(1673:1860:2047))
-        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (1429:1587:1745)(1429:1587:1745))
-        (INTERCONNECT Din_1_I/PADDI SLICE_57I/D0 (710:802:894)(710:802:894))
-        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (1420:1577:1734)(1420:1577:1734))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (1933:2113:2294)(1933:2113:2294))
-        (INTERCONNECT Din_1_I/PADDI SLICE_75I/D0 (1113:1234:1355)(1113:1234:1355))
-        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (1025:1155:1286)(1025:1155:1286))
-        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (2233:2448:2664)(2233:2448:2664))
-        (INTERCONNECT Din_1_I/PADDI SLICE_85I/B1 (1025:1155:1286)(1025:1155:1286))
-        (INTERCONNECT SLICE_57I/F1 SLICE_57I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (875:974:1073)(875:974:1073))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/B1 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_80I/F0 SLICE_59I/B0 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_62I/F1 SLICE_59I/A0 (1751:1905:2060)(1751:1905:2060))
-        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (1723:1947:2172)(1723:1947:2172))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/A1 (1751:1905:2060)(1751:1905:2060))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/C1 (748:831:915)(748:831:915))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/D1 (996:1089:1183)(996:1089:1183))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (908:1011:1114)(908:1011:1114))
-        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (1382:1514:1647)(1382:1514:1647))
-        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (1348:1473:1599)(1348:1473:1599))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/B0 (1797:1958:2120)(1797:1958:2120))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/D1 (588:652:716)(588:652:716))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/D0 (1395:1523:1651)(1395:1523:1651))
-        (INTERCONNECT SLICE_79I/F0 SLICE_62I/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_63I/F1 SLICE_63I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (1990:2225:2460)(1990:2225:2460))
-        (INTERCONNECT SLICE_66I/F1 SLICE_64I/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/D1 (1335:1476:1617)(1335:1476:1617))
-        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (261:290:320)(261:290:320))
-        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (2100:2300:2500)(2100:2300:2500))
-        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/D0 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (1219:1345:1472)(1219:1345:1472))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/A1 (1884:2070:2256)(1884:2070:2256))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/C1 (1794:1974:2155)(1794:1974:2155))
-        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (579:644:709)(579:644:709))
-        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (982:1076:1170)(982:1076:1170))
-        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT SLICE_87I/F0 SLICE_68I/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_87I/F0 SLICE_69I/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_68I/F1 SLICE_68I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_84I/F0 SLICE_68I/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/A1 (514:575:636)(514:575:636))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/D1 (1647:1811:1975)(1647:1811:1975))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (1876:2059:2243)(1876:2059:2243))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/C1 (1765:1936:2107)(1765:1936:2107))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (1917:2105:2293)(1917:2105:2293))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/D1 (2013:2194:2375)(2013:2194:2375))
-        (INTERCONNECT SLICE_88I/F1 SLICE_71I/D0 (564:632:700)(564:632:700))
-        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (879:985:1092)(879:985:1092))
-        (INTERCONNECT SLICE_71I/F1 SLICE_71I/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_81I/F1 SLICE_72I/D1 (564:632:700)(564:632:700))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (1611:1765:1919)(1611:1765:1919))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (1926:2118:2310)(1926:2118:2310))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/D0 (2417:2628:2840)(2417:2628:2840))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (1115:1236:1357)(1115:1236:1357))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/D1 (1921:2099:2278)(1921:2099:2278))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/D0 (2324:2531:2739)(2324:2531:2739))
-        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (1689:1848:2008)(1689:1848:2008))
-        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/A0 (1735:1889:2044)(1735:1889:2044))
-        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (833:932:1032)(833:932:1032))
-        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_77I/F1 SLICE_77I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_79I/F1 SLICE_79I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (1164:1346:1528)(1164:1346:1528))
-        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (1943:2141:2340)(1943:2141:2340))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (2322:2546:2771)(2322:2546:2771))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (2322:2546:2771)(2322:2546:2771))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/C1 (2208:2420:2632)(2208:2420:2632))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (1508:1668:1828)(1508:1668:1828))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/B0 (1919:2110:2302)(1919:2110:2302))
-        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/C0 (723:805:887)(723:805:887))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (1514:1673:1833)(1514:1673:1833))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (1514:1673:1833)(1514:1673:1833))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (1802:1985:2168)(1802:1985:2168))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C0 (1802:1985:2168)(1802:1985:2168))
-        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (1635:1796:1957)(1635:1796:1957))
-        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (1635:1796:1957)(1635:1796:1957))
-        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (2063:2303:2544)(2063:2303:2544))
-        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (1971:2209:2448)(1971:2209:2448))
-        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (1748:1996:2245)(1748:1996:2245))
-        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (3364:3728:4093)(3364:3728:4093))
-        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (3364:3728:4093)(3364:3728:4093))
-        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (1783:2025:2267)(1783:2025:2267))
-        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (3357:3721:4085)(3357:3721:4085))
-        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/D1 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/A1 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (1932:2190:2449)(1932:2190:2449))
-        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (2063:2303:2544)(2063:2303:2544))
-        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (2288:2578:2869)(2288:2578:2869))
-        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (1418:1631:1845)(1418:1631:1845))
-        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (1421:1631:1841)(1421:1631:1841))
-        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (2196:2460:2725)(2196:2460:2725))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:53:34 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1_SLICE_65I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_B")
+    (INSTANCE RD_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_B")
+    (INSTANCE Dout_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2B")
+    (INSTANCE PHI2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2S) (1250:1250:1250))
+      (WIDTH (negedge PHI2S) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDOB")
+    (INSTANCE UFMSDOI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
+      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDIB")
+    (INSTANCE UFMSDII)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLKB")
+    (INSTANCE UFMCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCSB")
+    (INSTANCE nUFMCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMLB")
+    (INSTANCE RDQMLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMHB")
+    (INSTANCE RDQMHI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCASB")
+    (INSTANCE nRCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRASB")
+    (INSTANCE nRRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWEB")
+    (INSTANCE nRWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKEB")
+    (INSTANCE RCKEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLKB")
+    (INSTANCE RCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLKS) (1250:1250:1250))
+      (WIDTH (negedge RCLKS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCSB")
+    (INSTANCE nRCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_B")
+    (INSTANCE RD_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_B")
+    (INSTANCE RD_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_B")
+    (INSTANCE RD_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_B")
+    (INSTANCE RD_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_B")
+    (INSTANCE RD_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_B")
+    (INSTANCE RD_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_B")
+    (INSTANCE RD_1_I0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_B")
+    (INSTANCE RA_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_B")
+    (INSTANCE RA_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_B")
+    (INSTANCE RA_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_B")
+    (INSTANCE RA_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_B")
+    (INSTANCE RA_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_B")
+    (INSTANCE RA_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_B")
+    (INSTANCE RA_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_B")
+    (INSTANCE RA_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_B")
+    (INSTANCE RA_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_B")
+    (INSTANCE RA_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_B")
+    (INSTANCE RA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_B")
+    (INSTANCE RA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_B")
+    (INSTANCE RBA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_B")
+    (INSTANCE RBA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LEDB")
+    (INSTANCE LEDI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWEB")
+    (INSTANCE nFWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWES) (1250:1250:1250))
+      (WIDTH (negedge nFWES) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRASB")
+    (INSTANCE nCRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRASS) (1250:1250:1250))
+      (WIDTH (negedge nCRASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCASB")
+    (INSTANCE nCCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCASS) (1250:1250:1250))
+      (WIDTH (negedge nCCASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_B")
+    (INSTANCE Dout_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_B")
+    (INSTANCE Dout_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_B")
+    (INSTANCE Dout_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_B")
+    (INSTANCE Dout_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_B")
+    (INSTANCE Dout_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_B")
+    (INSTANCE Dout_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_B")
+    (INSTANCE Dout_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_B")
+    (INSTANCE Din_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_B")
+    (INSTANCE Din_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_B")
+    (INSTANCE Din_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_B")
+    (INSTANCE Din_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_B")
+    (INSTANCE Din_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_B")
+    (INSTANCE Din_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_B")
+    (INSTANCE Din_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_B")
+    (INSTANCE Din_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_B")
+    (INSTANCE CROW_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_B")
+    (INSTANCE CROW_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_B")
+    (INSTANCE MAin_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_B")
+    (INSTANCE MAin_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_B")
+    (INSTANCE MAin_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_B")
+    (INSTANCE MAin_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_B")
+    (INSTANCE MAin_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_B")
+    (INSTANCE MAin_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_B")
+    (INSTANCE MAin_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_B")
+    (INSTANCE MAin_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_B")
+    (INSTANCE MAin_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_B")
+    (INSTANCE MAin_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (1232:1375:1519)(1232:1375:1519))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/B0 (1203:1339:1475)(1203:1339:1475))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/D1 (588:652:716)(588:652:716))
+        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/A1 (1146:1276:1406)(1146:1276:1406))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C0 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/C1 (1151:1263:1376)(1151:1263:1376))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (908:1011:1114)(908:1011:1114))
+        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B0 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/A1 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/C1 (1118:1249:1380)(1118:1249:1380))
+        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/D1 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/D0 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (1663:1816:1970)(1663:1816:1970))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (1260:1384:1509)(1260:1384:1509))
+        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/D1 (1001:1094:1188)(1001:1094:1188))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/B0 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/B1 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/B1 (1316:1448:1580)(1316:1448:1580))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/B0 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (1245:1393:1541)(1245:1393:1541))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (1648:1825:2002)(1648:1825:2002))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (1131:1266:1402)(1131:1266:1402))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C0 (1131:1266:1402)(1131:1266:1402))
+        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (1652:1794:1936)(1652:1794:1936))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/C0 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/A1 (1663:1816:1970)(1663:1816:1970))
+        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (1844:2015:2186)(1844:2015:2186))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/D0 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/D1 (595:663:731)(595:663:731))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A0 (864:963:1063)(864:963:1063))
+        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/D0 (1497:1620:1743)(1497:1620:1743))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (603:667:731)(603:667:731))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/B1 (918:1020:1123)(918:1020:1123))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/D0 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (1232:1375:1519)(1232:1375:1519))
+        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (1675:1841:2008)(1675:1841:2008))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (1561:1715:1869)(1561:1715:1869))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/A1 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_78I/F0 SLICE_9I/D1 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_85I/F1 SLICE_9I/C1 (1087:1218:1349)(1087:1218:1349))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/B1 (1843:2032:2222)(1843:2032:2222))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (1203:1325:1448)(1203:1325:1448))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/C0 (1683:1853:2023)(1683:1853:2023))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (1528:1679:1830)(1528:1679:1830))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/D1 (2744:2982:3221)(2744:2982:3221))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/D0 (2744:2982:3221)(2744:2982:3221))
+        (INTERCONNECT SLICE_70I/F1 SLICE_9I/A1 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/A1 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/A0 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70I/F1 SLICE_67I/A0 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70I/F1 SLICE_70I/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_70I/F1 SLICE_90I/B1 (1317:1447:1578)(1317:1447:1578))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/D0 (517:575:634)(517:575:634))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/B1 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_9I/F1 SLICE_9I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_9I/F1 SLICE_20I/D0 (261:290:320)(261:290:320))
+        (INTERCONNECT SLICE_14I/F1 SLICE_9I/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_14I/F1 SLICE_14I/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (559:618:678)(559:618:678))
+        (INTERCONNECT SLICE_70I/F0 SLICE_9I/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (2182:2416:2650)(2182:2416:2650))
+        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT SLICE_77I/F0 SLICE_14I/D1 (564:632:700)(564:632:700))
+        (INTERCONNECT SLICE_76I/F0 SLICE_14I/C1 (1530:1676:1822)(1530:1676:1822))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (1225:1351:1478)(1225:1351:1478))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (1525:1685:1846)(1525:1685:1846))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/B0 (1540:1705:1870)(1540:1705:1870))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/A0 (1879:2062:2246)(1879:2062:2246))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/C0 (1373:1516:1660)(1373:1516:1660))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/D0 (1225:1351:1478)(1225:1351:1478))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/C1 (1784:1959:2134)(1784:1959:2134))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/B0 (1541:1706:1872)(1541:1706:1872))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/B0 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/B0 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/D1 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (2110:2331:2552)(2110:2331:2552))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/C1 (2657:2925:3193)(2657:2925:3193))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A0 (2482:2728:2974)(2482:2728:2974))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/C1 (2365:2598:2832)(2365:2598:2832))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (2110:2331:2552)(2110:2331:2552))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (2620:2864:3109)(2620:2864:3109))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/A1 (2054:2267:2480)(2054:2267:2480))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/D1 (1793:1977:2161)(1793:1977:2161))
+        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (2210:2424:2639)
+          (2210:2424:2639))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/B1 (895:1001:1108)(895:1001:1108))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C1 (763:846:930)(763:846:930))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C0 (763:846:930)(763:846:930))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/C1 (1581:1730:1879)(1581:1730:1879))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (1769:1942:2115)(1769:1942:2115))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C1 (2019:2202:2385)(2019:2202:2385))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C0 (2019:2202:2385)(2019:2202:2385))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/D0 (1454:1588:1723)(1454:1588:1723))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/C1 (757:844:932)(757:844:932))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/C0 (757:844:932)(757:844:932))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/C1 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/C0 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/C0 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (878:975:1072)(878:975:1072))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/B1 (938:1041:1144)(938:1041:1144))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C0 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/C1 (1181:1293:1406)(1181:1293:1406))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/A0 (892:988:1084)(892:988:1084))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (1362:1496:1631)
+          (1362:1496:1631))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (1362:1496:1631)
+          (1362:1496:1631))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/A1 (1316:1443:1571)(1316:1443:1571))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/D0 (1047:1143:1239)(1047:1143:1239))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/C0 (718:795:873)(718:795:873))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/A1 (1286:1409:1533)(1286:1409:1533))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A1 (825:914:1004)(825:914:1004))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/B1 (1424:1556:1689)(1424:1556:1689))
+        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_43I/A0 (849:948:1048)(849:948:1048))
+        (INTERCONNECT SLICE_19I/F1 SLICE_44I/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A1 (810:899:989)(810:899:989))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/D0 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_90I/F1 SLICE_20I/C0 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_21I/D1 (321:350:380)(321:350:380))
+        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (640:708:776)(640:708:776))
+        (INTERCONNECT SLICE_75I/F1 SLICE_67I/D1 (1047:1139:1231)(1047:1139:1231))
+        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (476:524:573)(476:524:573))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/C1 (476:524:573)(476:524:573))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (901:997:1094)(901:997:1094))
+        (INTERCONNECT Din_5_I/PADDI SLICE_21I/B1 (1546:1711:1877)(1546:1711:1877))
+        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (2468:2685:2903)(2468:2685:2903))
+        (INTERCONNECT Din_5_I/PADDI SLICE_67I/B1 (1949:2143:2338)(1949:2143:2338))
+        (INTERCONNECT Din_5_I/PADDI SLICE_75I/B0 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/B1 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (1962:2156:2351)(1962:2156:2351))
+        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/A1 (1500:1658:1817)(1500:1658:1817))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/A0 (1500:1658:1817)(1500:1658:1817))
+        (INTERCONNECT Din_5_I/PADDI SLICE_85I/D0 (1944:2137:2330)(1944:2137:2330))
+        (INTERCONNECT Din_3_I/PADDI SLICE_21I/A1 (1398:1552:1707)(1398:1552:1707))
+        (INTERCONNECT Din_3_I/PADDI SLICE_57I/A1 (988:1113:1238)(988:1113:1238))
+        (INTERCONNECT Din_3_I/PADDI SLICE_67I/C1 (1556:1731:1906)(1556:1731:1906))
+        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (712:804:897)(712:804:897))
+        (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (988:1113:1238)(988:1113:1238))
+        (INTERCONNECT Din_3_I/PADDI SLICE_78I/D1 (709:801:894)(709:801:894))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D1 (1418:1575:1733)(1418:1575:1733))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/C0 (1277:1418:1560)(1277:1418:1560))
+        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (712:804:897)(712:804:897))
+        (INTERCONNECT SLICE_75I/F0 SLICE_21I/D0 (245:274:304)(245:274:304))
+        (INTERCONNECT SLICE_21I/F1 SLICE_21I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_21I/F1 SLICE_26I/A0 (853:947:1042)(853:947:1042))
+        (INTERCONNECT SLICE_82I/F1 SLICE_21I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/A0 (1514:1694:1875)(1514:1694:1875))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (1674:1856:2038)(1674:1856:2038))
+        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (1285:1433:1581)(1285:1433:1581))
+        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (921:1020:1119)(921:1020:1119))
+        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (1696:1875:2055)(1696:1875:2055))
+        (INTERCONNECT SLICE_67I/F0 SLICE_67I/A1 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_67I/F0 SLICE_82I/D0 (986:1100:1215)(986:1100:1215))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/A0 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (1682:1846:2010)(1682:1846:2010))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/C1 (1201:1313:1426)(1201:1313:1426))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A1 (854:945:1036)(854:945:1036))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A0 (575:636:697)(575:636:697))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/C0 (1611:1753:1895)(1611:1753:1895))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D1 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D0 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/C1 (2035:2209:2383)(2035:2209:2383))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/B1 (1769:1941:2114)(1769:1941:2114))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/B1 (1771:1932:2094)(1771:1932:2094))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/C1 (740:818:897)(740:818:897))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/C0 (740:818:897)(740:818:897))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/C1 (784:866:948)(784:866:948))
+        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/A0 (1746:1903:2061)
+          (1746:1903:2061))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B1 (1777:1952:2127)(1777:1952:2127))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B0 (1777:1952:2127)(1777:1952:2127))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/D1 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/B1 (1302:1432:1563)(1302:1432:1563))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/C1 (1103:1234:1365)(1103:1234:1365))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/A1 (1260:1384:1509)(1260:1384:1509))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (544:603:663)(544:603:663))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/D1 (991:1084:1177)(991:1084:1177))
+        (INTERCONNECT SLICE_82I/F0 SLICE_22I/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_68I/C0 (1133:1244:1356)(1133:1244:1356))
+        (INTERCONNECT SLICE_22I/F1 SLICE_69I/C0 (1133:1244:1356)(1133:1244:1356))
+        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_78I/F1 SLICE_78I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/B0 (899:1000:1102)(899:1000:1102))
+        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/C0 (1936:2106:2276)(1936:2106:2276))
+        (INTERCONNECT SLICE_26I/F1 SLICE_26I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F1 SLICE_29I/D1 (584:647:710)(584:647:710))
+        (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/C1 (726:803:880)(726:803:880))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/D0 (571:629:687)(571:629:687))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D1 (643:708:773)(643:708:773))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D0 (643:708:773)(643:708:773))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/C0 (798:882:966)(798:882:966))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/D1 (1534:1657:1781)(1534:1657:1781))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/D0 (932:1031:1131)(932:1031:1131))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/B0 (2655:2875:3095)(2655:2875:3095))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (1300:1448:1596)(1300:1448:1596))
+        (INTERCONNECT SLICE_83I/F1 SLICE_29I/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_83I/F1 SLICE_59I/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_83I/F1 SLICE_61I/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/A1 (1297:1422:1547)(1297:1422:1547))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/A0 (1297:1422:1547)(1297:1422:1547))
+        (INTERCONNECT SLICE_73I/F1 SLICE_59I/D1 (1109:1203:1297)(1109:1203:1297))
+        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (1062:1179:1297)(1062:1179:1297))
+        (INTERCONNECT SLICE_73I/F1 SLICE_73I/C0 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_73I/F1 SLICE_94I/B1 (871:967:1064)(871:967:1064))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (2198:2404:2610)(2198:2404:2610))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/C0 (733:810:888)(733:810:888))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/B1 (886:982:1079)(886:982:1079))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/C0 (733:810:888)(733:810:888))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/D1 (1490:1629:1769)(1490:1629:1769))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/B1 (2511:2758:3006)(2511:2758:3006))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/B1 (2087:2299:2511)(2087:2299:2511))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/B1 (2087:2299:2511)(2087:2299:2511))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/B1 (1805:1983:2161)(1805:1983:2161))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/B0 (1805:1983:2161)(1805:1983:2161))
+        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (948:1049:1150)(948:1049:1150))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/A0 (1199:1330:1461)(1199:1330:1461))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/A1 (894:993:1093)(894:993:1093))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A1 (907:1003:1099)(907:1003:1099))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A0 (907:1003:1099)(907:1003:1099))
+        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B1 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B1 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B0 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/A1 (1378:1503:1629)(1378:1503:1629))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/C1 (1179:1290:1402)(1179:1290:1402))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/C0 (1179:1290:1402)(1179:1290:1402))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/A1 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D1 (563:621:680)(563:621:680))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D0 (563:621:680)(563:621:680))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/B1 (1424:1556:1689)(1424:1556:1689))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/A1 (1293:1417:1541)(1293:1417:1541))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/A0 (1293:1417:1541)(1293:1417:1541))
+        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_73I/F0 SLICE_31I/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (575:639:703)(575:639:703))
+        (INTERCONNECT SLICE_56I/F0 SLICE_32I/D1 (1352:1480:1609)(1352:1480:1609))
+        (INTERCONNECT SLICE_72I/F1 SLICE_32I/C1 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_72I/F1 SLICE_58I/D1 (291:320:350)(291:320:350))
+        (INTERCONNECT SLICE_72I/F1 SLICE_64I/B1 (929:1030:1132)(929:1030:1132))
+        (INTERCONNECT SLICE_72I/F1 SLICE_72I/C0 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_84I/F1 SLICE_32I/B1 (879:985:1092)(879:985:1092))
+        (INTERCONNECT SLICE_74I/F0 SLICE_32I/B0 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F1 SLICE_87I/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT nCRASI/PADDI SLICE_33I/D1 (2857:3462:4068)(2857:3462:4068))
+        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (3532:4217:4903)(3532:4217:4903))
+        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/D0 (1365:1507:1650)(1365:1507:1650))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/A0 (1681:1846:2012)(1681:1846:2012))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/A1 (1239:1386:1534)(1239:1386:1534))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/A0 (1239:1386:1534)(1239:1386:1534))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/D0 (702:793:885)(702:793:885))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/D0 (1105:1225:1346)(1105:1225:1346))
+        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (939:1052:1165)(939:1052:1165))
+        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_85I/F0 SLICE_39I/D1 (1514:1646:1779)(1514:1646:1779))
+        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A1 (2147:2339:2531)(2147:2339:2531))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A0 (2147:2339:2531)(2147:2339:2531))
+        (INTERCONNECT Din_6_I/PADDI SLICE_39I/D0 (2053:2245:2437)(2053:2245:2437))
+        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (3194:3483:3773)(3194:3483:3773))
+        (INTERCONNECT Din_6_I/PADDI SLICE_75I/B1 (1519:1680:1842)(1519:1680:1842))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/D0 (2081:2276:2472)(2081:2276:2472))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (2388:2619:2851)(2388:2619:2851))
+        (INTERCONNECT Din_6_I/PADDI SLICE_78I/B0 (2396:2630:2864)(2396:2630:2864))
+        (INTERCONNECT Din_6_I/PADDI SLICE_85I/B0 (2799:3062:3325)(2799:3062:3325))
+        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (1313:1442:1571)(1313:1442:1571))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (1850:2013:2177)(1850:2013:2177))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (559:618:678)(559:618:678))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (1842:2003:2164)(1842:2003:2164))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_39I/F1 SLICE_57I/A0 (1767:1931:2095)(1767:1931:2095))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/D1 (960:1076:1193)(960:1076:1193))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/B1 (1967:2185:2404)(1967:2185:2404))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/B1 (1275:1430:1585)(1275:1430:1585))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/D1 (1370:1516:1662)(1370:1516:1662))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (1780:1956:2132)(1780:1956:2132))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/A1 (2097:2301:2505)(2097:2301:2505))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/D1 (2924:3195:3466)(2924:3195:3466))
+        (INTERCONNECT SLICE_43I/F1 SLICE_41I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_41I/F1 SLICE_41I/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (1342:1484:1626)(1342:1484:1626))
+        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/D0 (1352:1480:1609)(1352:1480:1609))
+        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/B0 (1293:1424:1555)(1293:1424:1555))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (2091:2277:2464)(2091:2277:2464))
+        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/C1 (1543:1684:1825)(1543:1684:1825))
+        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/A1 (2060:2242:2425)
+          (2060:2242:2425))
+        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (1978:2217:2456)(1978:2217:2456))
+        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/D0 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_50I/F0 SLICE_43I/A1 (1270:1395:1520)(1270:1395:1520))
+        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (16:16:16)(16:16:16))
+        (INTERCONNECT SLICE_50I/F0 SLICE_61I/D1 (1001:1094:1188)(1001:1094:1188))
+        (INTERCONNECT SLICE_50I/F0 SLICE_62I/C1 (1156:1268:1381)(1156:1268:1381))
+        (INTERCONNECT SLICE_83I/F0 SLICE_43I/B0 (1255:1408:1561)(1255:1408:1561))
+        (INTERCONNECT SLICE_83I/F0 SLICE_44I/A1 (1612:1787:1962)(1612:1787:1962))
+        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F1 SLICE_44I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/D1 (1375:1502:1629)(1375:1502:1629))
+        (INTERCONNECT SLICE_72I/F0 SLICE_51I/C1 (1126:1237:1348)(1126:1237:1348))
+        (INTERCONNECT SLICE_66I/F0 SLICE_51I/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (1548:1774:2000)(1548:1774:2000))
+        (INTERCONNECT SLICE_51I/F1 SLICE_51I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (1409:1541:1674)(1409:1541:1674))
+        (INTERCONNECT SLICE_64I/F1 SLICE_52I/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (1157:1286:1415)(1157:1286:1415))
+        (INTERCONNECT SLICE_52I/F1 SLICE_52I/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_52I/F1 SLICE_64I/D0 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/D0 (1207:1330:1453)(1207:1330:1453))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (1949:2146:2344)(1949:2146:2344))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/B1 (1914:2103:2292)(1914:2103:2292))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/B0 (1997:2204:2411)(1997:2204:2411))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/D1 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/D0 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D1 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D0 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/A0 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (2426:2645:2865)(2426:2645:2865))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (2426:2645:2865)(2426:2645:2865))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (1898:2093:2289)(1898:2093:2289))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (1898:2093:2289)(1898:2093:2289))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/A1 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B0 (2176:2385:2595)(2176:2385:2595))
+        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (2322:2541:2761)(2322:2541:2761))
+        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (1473:1628:1784)(1473:1628:1784))
+        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (1635:1791:1948)(1635:1791:1948))
+        (INTERCONNECT Din_4_I/PADDI SLICE_77I/D1 (1628:1783:1939)(1628:1783:1939))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (1628:1783:1939)(1628:1783:1939))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/C0 (2072:2281:2490)(2072:2281:2490))
+        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (2787:3031:3276)(2787:3031:3276))
+        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (2787:3031:3276)(2787:3031:3276))
+        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (2225:2440:2655)(2225:2440:2655))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (1818:2004:2190)(1818:2004:2190))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (1818:2004:2190)(1818:2004:2190))
+        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (2377:2592:2807)(2377:2592:2807))
+        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (1564:1720:1877)(1564:1720:1877))
+        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (1798:1981:2164)(1798:1981:2164))
+        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (2042:2305:2568)(2042:2305:2568))
+        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (2630:2955:3280)(2630:2955:3280))
+        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (1260:1386:1513)(1260:1386:1513))
+        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (1126:1237:1348)(1126:1237:1348))
+        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (1332:1457:1583)(1332:1457:1583))
+        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (2232:2447:2663)(2232:2447:2663))
+        (INTERCONNECT Din_7_I/PADDI SLICE_75I/D1 (1515:1665:1815)(1515:1665:1815))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/A1 (2604:2844:3085)(2604:2844:3085))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (2642:2887:3132)(2642:2887:3132))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/A1 (1381:1533:1686)(1381:1533:1686))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/A0 (1381:1533:1686)(1381:1533:1686))
+        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_56I/F1 SLICE_70I/B1 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT Din_0_I/PADDI SLICE_57I/C1 (1277:1418:1559)(1277:1418:1559))
+        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (1839:2026:2214)(1839:2026:2214))
+        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (2242:2458:2675)(2242:2458:2675))
+        (INTERCONNECT Din_0_I/PADDI SLICE_76I/D1 (1532:1683:1835)(1532:1683:1835))
+        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (3049:3329:3610)(3049:3329:3610))
+        (INTERCONNECT Din_0_I/PADDI SLICE_85I/C1 (1566:1741:1917)(1566:1741:1917))
+        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (1437:1597:1758)(1437:1597:1758))
+        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (1129:1252:1375)(1129:1252:1375))
+        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (1411:1566:1722)(1411:1566:1722))
+        (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (1384:1536:1689)(1384:1536:1689))
+        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (1673:1860:2047)(1673:1860:2047))
+        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (1429:1587:1745)(1429:1587:1745))
+        (INTERCONNECT Din_1_I/PADDI SLICE_57I/D0 (710:802:894)(710:802:894))
+        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (1420:1577:1734)(1420:1577:1734))
+        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (1933:2113:2294)(1933:2113:2294))
+        (INTERCONNECT Din_1_I/PADDI SLICE_75I/D0 (1113:1234:1355)(1113:1234:1355))
+        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (1025:1155:1286)(1025:1155:1286))
+        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (2233:2448:2664)(2233:2448:2664))
+        (INTERCONNECT Din_1_I/PADDI SLICE_85I/B1 (1025:1155:1286)(1025:1155:1286))
+        (INTERCONNECT SLICE_57I/F1 SLICE_57I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (875:974:1073)(875:974:1073))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/B1 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_80I/F0 SLICE_59I/B0 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_62I/F1 SLICE_59I/A0 (1751:1905:2060)(1751:1905:2060))
+        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (1723:1947:2172)(1723:1947:2172))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/A1 (1751:1905:2060)(1751:1905:2060))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/C1 (748:831:915)(748:831:915))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/D1 (996:1089:1183)(996:1089:1183))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (908:1011:1114)(908:1011:1114))
+        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (1382:1514:1647)(1382:1514:1647))
+        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (1348:1473:1599)(1348:1473:1599))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/B0 (1797:1958:2120)(1797:1958:2120))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/D1 (588:652:716)(588:652:716))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/D0 (1395:1523:1651)(1395:1523:1651))
+        (INTERCONNECT SLICE_79I/F0 SLICE_62I/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_63I/F1 SLICE_63I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (1990:2225:2460)(1990:2225:2460))
+        (INTERCONNECT SLICE_66I/F1 SLICE_64I/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/D1 (1335:1476:1617)(1335:1476:1617))
+        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (261:290:320)(261:290:320))
+        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (2100:2300:2500)(2100:2300:2500))
+        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/D0 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (1219:1345:1472)(1219:1345:1472))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/A1 (1884:2070:2256)(1884:2070:2256))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/C1 (1794:1974:2155)(1794:1974:2155))
+        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (579:644:709)(579:644:709))
+        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (982:1076:1170)(982:1076:1170))
+        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT SLICE_87I/F0 SLICE_68I/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_87I/F0 SLICE_69I/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_68I/F1 SLICE_68I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_84I/F0 SLICE_68I/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/A1 (514:575:636)(514:575:636))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/D1 (1647:1811:1975)(1647:1811:1975))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (1876:2059:2243)(1876:2059:2243))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/C1 (1765:1936:2107)(1765:1936:2107))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (1917:2105:2293)(1917:2105:2293))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/D1 (2013:2194:2375)(2013:2194:2375))
+        (INTERCONNECT SLICE_88I/F1 SLICE_71I/D0 (564:632:700)(564:632:700))
+        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (879:985:1092)(879:985:1092))
+        (INTERCONNECT SLICE_71I/F1 SLICE_71I/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_81I/F1 SLICE_72I/D1 (564:632:700)(564:632:700))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (1611:1765:1919)(1611:1765:1919))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (1926:2118:2310)(1926:2118:2310))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/D0 (2417:2628:2840)(2417:2628:2840))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (1115:1236:1357)(1115:1236:1357))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/D1 (1921:2099:2278)(1921:2099:2278))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/D0 (2324:2531:2739)(2324:2531:2739))
+        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (1689:1848:2008)(1689:1848:2008))
+        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/A0 (1735:1889:2044)(1735:1889:2044))
+        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (833:932:1032)(833:932:1032))
+        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_77I/F1 SLICE_77I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_79I/F1 SLICE_79I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (1164:1346:1528)(1164:1346:1528))
+        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (1943:2141:2340)(1943:2141:2340))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (2322:2546:2771)(2322:2546:2771))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (2322:2546:2771)(2322:2546:2771))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/C1 (2208:2420:2632)(2208:2420:2632))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (1508:1668:1828)(1508:1668:1828))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/B0 (1919:2110:2302)(1919:2110:2302))
+        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/C0 (723:805:887)(723:805:887))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (1514:1673:1833)(1514:1673:1833))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (1514:1673:1833)(1514:1673:1833))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (1802:1985:2168)(1802:1985:2168))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C0 (1802:1985:2168)(1802:1985:2168))
+        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (1635:1796:1957)(1635:1796:1957))
+        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (1635:1796:1957)(1635:1796:1957))
+        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (2063:2303:2544)(2063:2303:2544))
+        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (1971:2209:2448)(1971:2209:2448))
+        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (1748:1996:2245)(1748:1996:2245))
+        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (3364:3728:4093)(3364:3728:4093))
+        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (3364:3728:4093)(3364:3728:4093))
+        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (1783:2025:2267)(1783:2025:2267))
+        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (3357:3721:4085)(3357:3721:4085))
+        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/D1 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/A1 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (1932:2190:2449)(1932:2190:2449))
+        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (2063:2303:2544)(2063:2303:2544))
+        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (2288:2578:2869)(2288:2578:2869))
+        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (1418:1631:1845)(1418:1631:1845))
+        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (1421:1631:1841)(1421:1631:1841))
+        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (2196:2460:2725)(2196:2460:2725))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.vho b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.vho
index 5800c96..e5fc1b3 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.vho
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vho.vho
@@ -1,25810 +1,25810 @@
-
--- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
--- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_vho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd 
--- Netlist created on Wed Aug 16 04:50:39 2023
--- Netlist written on Wed Aug 16 04:50:50 2023
--- Design is for device LCMXO256C
--- Design is for package TQFP100
--- Design is for performance grade 3
-
--- entity vmuxregsre
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
-
-  end vmuxregsre;
-
-  architecture Structure of vmuxregsre is
-    component FL1P3DX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity vcc
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vcc is
-    port (PWR1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
-
-  end vcc;
-
-  architecture Structure of vcc is
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VHI
-      port map (Z=>PWR1);
-  end Structure;
-
--- entity gnd
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity gnd is
-    port (PWR0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
-
-  end gnd;
-
-  architecture Structure of gnd is
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VLO
-      port map (Z=>PWR0);
-  end Structure;
-
--- entity ccu2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu2B is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
-
-  end ccu2B;
-
-  architecture Structure of ccu2B is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_0
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_0 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_0";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
-
-  end SLICE_0;
-
-  architecture Structure of SLICE_0 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_0: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
-                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20001
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu20001 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
-
-  end ccu20001;
-
-  architecture Structure of ccu20001 is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_1
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_1 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_1";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
-
-  end SLICE_1;
-
-  architecture Structure of SLICE_1 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20001
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_17: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_16: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_16: ccu20001
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
-                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_2 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_2";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
-
-  end SLICE_2;
-
-  architecture Structure of SLICE_2 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_15: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_14: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_14: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
-                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_3
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_3 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_3";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
-
-  end SLICE_3;
-
-  architecture Structure of SLICE_3 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_13: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_12: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_12: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
-                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_4 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_4";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
-
-  end SLICE_4;
-
-  architecture Structure of SLICE_4 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_11: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_10: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_10: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
-                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_5
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_5 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_5";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
-
-  end SLICE_5;
-
-  architecture Structure of SLICE_5 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_9: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_8: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_8: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
-                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_6
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_6 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_6";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
-
-  end SLICE_6;
-
-  architecture Structure of SLICE_6 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_7: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_6: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_6: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
-                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_7
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_7 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_7";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
-
-  end SLICE_7;
-
-  architecture Structure of SLICE_7 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_5: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_4: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_4: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
-                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_8
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_8 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_8";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
-
-  end SLICE_8;
-
-  architecture Structure of SLICE_8 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_2: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
-                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut4 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
-
-  end lut4;
-
-  architecture Structure of lut4 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40002
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40002 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
-
-  end lut40002;
-
-  architecture Structure of lut40002 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3130")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity inverter
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity inverter is
-    port (I: in Std_logic; Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
-
-  end inverter;
-
-  architecture Structure of inverter is
-    component INV
-      port (A: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    INST1: INV
-      port map (A=>I, Z=>Z);
-  end Structure;
-
--- entity SLICE_9
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_9 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_9";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
-
-  end SLICE_9;
-
-  architecture Structure of SLICE_9 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40002
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    ADSubmitted_r: lut40002
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    ADSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40003
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40003 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
-
-  end lut40003;
-
-  architecture Structure of lut40003 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40004
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40004 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
-
-  end lut40004;
-
-  architecture Structure of lut40004 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF4FC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_14
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_14 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_14";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
-
-  end SLICE_14;
-
-  architecture Structure of SLICE_14 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40003
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2: lut40003
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1Submitted_RNO: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    C1Submitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40005
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40005 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
-
-  end lut40005;
-
-  architecture Structure of lut40005 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40006
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40006 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
-
-  end lut40006;
-
-  architecture Structure of lut40006 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF5F5")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0007
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0007 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
-
-  end vmuxregsre0007;
-
-  architecture Structure of vmuxregsre0007 is
-    component FL1P3IY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3IY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_19
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_19 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_19";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
-
-  end SLICE_19;
-
-  architecture Structure of SLICE_19 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNO_0: lut40006
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40008
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40008 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
-
-  end lut40008;
-
-  architecture Structure of lut40008 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40009
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40009 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
-
-  end lut40009;
-
-  architecture Structure of lut40009 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEA0A")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity selmux2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity selmux2 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
-
-  end selmux2;
-
-  architecture Structure of selmux2 is
-    component MUX21
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    INST1: MUX21
-      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
-  end Structure;
-
--- entity SLICE_20
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_20 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_20";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
-
-  end SLICE_20;
-
-  architecture Structure of SLICE_20 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
-    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40009
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_20_K1: lut40008
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
-                Z=>SLICE_20_SLICE_20_K1_H1);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable_s_GATE: lut40009
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>SLICE_20_CmdEnable_s_GATE_H0);
-    CmdEnable: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    SLICE_20_K0K1MUX: selmux2
-      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40010
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40010 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
-
-  end lut40010;
-
-  architecture Structure of lut40010 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0044")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40011
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40011 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
-
-  end lut40011;
-
-  architecture Structure of lut40011 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0023")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_21
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_21 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_21";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
-
-  end SLICE_21;
-
-  architecture Structure of SLICE_21 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40010
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40011
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_a2_2: lut40010
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_RNO: lut40011
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdLEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40012
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40012 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
-
-  end lut40012;
-
-  architecture Structure of lut40012 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40013
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40013 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
-
-  end lut40013;
-
-  architecture Structure of lut40013 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFAFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_22
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_22 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_22";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
-
-  end SLICE_22;
-
-  architecture Structure of SLICE_22 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2: lut40012
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_RNO: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40014
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40014 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
-
-  end lut40014;
-
-  architecture Structure of lut40014 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33AB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40015
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40015 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
-
-  end lut40015;
-
-  architecture Structure of lut40015 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0F05")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_26
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_26 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_26";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
-
-  end SLICE_26;
-
-  architecture Structure of SLICE_26 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40014
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_0: lut40014
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_RNO: lut40015
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Cmdn8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40016
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40016 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
-
-  end lut40016;
-
-  architecture Structure of lut40016 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF54")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40017
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40017 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
-
-  end lut40017;
-
-  architecture Structure of lut40017 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEE11")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_29
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_29 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_29";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
-
-  end SLICE_29;
-
-  architecture Structure of SLICE_29 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40017
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i: lut40016
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_0: lut40017
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40018
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40018 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
-
-  end lut40018;
-
-  architecture Structure of lut40018 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x66AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40019
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40019 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
-
-  end lut40019;
-
-  architecture Structure of lut40019 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x55AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_30
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_30 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_30";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
-
-  end SLICE_30;
-
-  architecture Structure of SLICE_30 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40018
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_2: lut40018
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_n1_0_x2: lut40019
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    IS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    IS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40020
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40020 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
-
-  end lut40020;
-
-  architecture Structure of lut40020 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40021
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40021 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
-
-  end lut40021;
-
-  architecture Structure of lut40021 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x6AAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_31
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_31 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_31";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
-
-  end SLICE_31;
-
-  architecture Structure of SLICE_31 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40020
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40021
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_RNO: lut40020
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_3: lut40021
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    IS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40022
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40022 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
-
-  end lut40022;
-
-  architecture Structure of lut40022 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5155")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40023
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40023 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
-
-  end lut40023;
-
-  architecture Structure of lut40023 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_32
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_32 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_32";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
-
-  end SLICE_32;
-
-  architecture Structure of SLICE_32 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40022
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a0: lut40022
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady_RNO: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40024
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40024 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
-
-  end lut40024;
-
-  architecture Structure of lut40024 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFAF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40025
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40025 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
-
-  end lut40025;
-
-  architecture Structure of lut40025 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA0AF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_33
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_33 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_33";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
-
-  end SLICE_33;
-
-  architecture Structure of SLICE_33 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40025
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LED_pad_RNO: lut40024
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    LEDEN_5_i_m2: lut40025
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    LEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40026
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40026 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
-
-  end lut40026;
-
-  architecture Structure of lut40026 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40027
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40027 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
-
-  end lut40027;
-
-  architecture Structure of lut40027 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA5AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_39
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_39 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_39";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
-
-  end SLICE_39;
-
-  architecture Structure of SLICE_39 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40026
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40027
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_0: lut40026
-      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RA11_2: lut40027
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RA11: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40028
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40028 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
-
-  end lut40028;
-
-  architecture Structure of lut40028 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2DAD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40029
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40029 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
-
-  end lut40029;
-
-  architecture Structure of lut40029 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCCEC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_41
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_41 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_41";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
-
-  end SLICE_41;
-
-  architecture Structure of SLICE_41 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40029
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_1_0: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u: lut40029
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40030
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40030 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
-
-  end lut40030;
-
-  architecture Structure of lut40030 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40031
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40031 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
-
-  end lut40031;
-
-  architecture Structure of lut40031 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFE50")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_42
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_42 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_42";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
-
-  end SLICE_42;
-
-  architecture Structure of SLICE_42 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40030
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40031
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_5: lut40030
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKE_2_0: lut40031
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKE: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40032
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40032 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
-
-  end lut40032;
-
-  architecture Structure of lut40032 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3704")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40033
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40033 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
-
-  end lut40033;
-
-  architecture Structure of lut40033 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF2F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_43
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_43 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_43";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
-
-  end SLICE_43;
-
-  architecture Structure of SLICE_43 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40033
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_RNO: lut40032
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_RNO: lut40033
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40034
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40034 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
-
-  end lut40034;
-
-  architecture Structure of lut40034 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0040")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_44
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_44 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_44";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
-
-  end SLICE_44;
-
-  architecture Structure of SLICE_44 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3: lut40034
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_fast_RNO: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RASr: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Ready_fast: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40035
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40035 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
-
-  end lut40035;
-
-  architecture Structure of lut40035 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0300")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_50
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_50 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_50";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
-
-  end SLICE_50;
-
-  architecture Structure of SLICE_50 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_RNO: lut40035
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0_i_o2_1: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    S_1: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, C0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40036
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40036 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
-
-  end lut40036;
-
-  architecture Structure of lut40036 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xABEF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40037
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40037 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
-
-  end lut40037;
-
-  architecture Structure of lut40037 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1302")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_51
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_51 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_51";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
-
-  end SLICE_51;
-
-  architecture Structure of SLICE_51 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40036
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_RNO_0: lut40036
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_RNO: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40038
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40038 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
-
-  end lut40038;
-
-  architecture Structure of lut40038 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33B3")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40039
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40039 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
-
-  end lut40039;
-
-  architecture Structure of lut40039 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5404")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_52
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_52 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_52";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
-
-  end SLICE_52;
-
-  architecture Structure of SLICE_52 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40039
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    PHI2r3_RNITCN41: lut40038
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_RNO: lut40039
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMSDI: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40040
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40040 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
-
-  end lut40040;
-
-  architecture Structure of lut40040 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEE22")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_55
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_55 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_55";
-
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
-
-  end SLICE_55;
-
-  architecture Structure of SLICE_55 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_4: lut40040
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
-      F0_out, Q0_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40041
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40041 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
-
-  end lut40041;
-
-  architecture Structure of lut40041 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40042
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40042 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
-
-  end lut40042;
-
-  architecture Structure of lut40042 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3C0C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_56
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_56 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_56";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
-
-  end SLICE_56;
-
-  architecture Structure of SLICE_56 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40042
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_11: lut40041
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_o2: lut40042
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40043
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40043 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
-
-  end lut40043;
-
-  architecture Structure of lut40043 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40044
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40044 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
-
-  end lut40044;
-
-  architecture Structure of lut40044 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBAFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_57
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_57 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_57";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
-
-  end SLICE_57;
-
-  architecture Structure of SLICE_57 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40043
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40044
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_2: lut40043
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG_3_u_0_a3_3: lut40044
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    XOR8MEG: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40045
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40045 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
-
-  end lut40045;
-
-  architecture Structure of lut40045 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0005")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40046
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40046 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
-
-  end lut40046;
-
-  architecture Structure of lut40046 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xC0CF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_58
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_58 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_58";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
-
-  end SLICE_58;
-
-  architecture Structure of SLICE_58 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40045
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40046
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_en_ss0_0_a2_0: lut40045
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    n8MEGEN_5_i_m2: lut40046
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    n8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40047
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40047 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
-
-  end lut40047;
-
-  architecture Structure of lut40047 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3F1D")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40048
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40048 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
-
-  end lut40048;
-
-  architecture Structure of lut40048 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5510")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0049
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0049 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0049 : ENTITY IS TRUE;
-
-  end vmuxregsre0049;
-
-  architecture Structure of vmuxregsre0049 is
-    component FL1P3BX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_59
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_59 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_59";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
-
-  end SLICE_59;
-
-  architecture Structure of SLICE_59 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40047
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40048
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0049
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_0: lut40047
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCAS_RNO: lut40048
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCAS: vmuxregsre0049
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40050
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40050 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
-
-  end lut40050;
-
-  architecture Structure of lut40050 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBFF0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40051
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40051 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
-
-  end lut40051;
-
-  architecture Structure of lut40051 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3233")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_60
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_60 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_60";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
-
-  end SLICE_60;
-
-  architecture Structure of SLICE_60 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0049
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40050
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40051
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_RNO_0: lut40050
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCS_RNO: lut40051
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCS: vmuxregsre0049
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40052
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40052 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
-
-  end lut40052;
-
-  architecture Structure of lut40052 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00C8")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40053
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40053 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
-
-  end lut40053;
-
-  architecture Structure of lut40053 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3031")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_61
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_61 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_61";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
-
-  end SLICE_61;
-
-  architecture Structure of SLICE_61 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0049
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i_0: lut40052
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRRAS_RNO: lut40053
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRRAS: vmuxregsre0049
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40054
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40054 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
-
-  end lut40054;
-
-  architecture Structure of lut40054 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40055
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40055 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
-
-  end lut40055;
-
-  architecture Structure of lut40055 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF2F7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_62
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_62 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_62";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
-
-  end SLICE_62;
-
-  architecture Structure of SLICE_62 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0049
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40054
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40055
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0_sqmuxa_1_0_a3: lut40054
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRWE_RNO: lut40055
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRWE: vmuxregsre0049
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40056
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40056 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
-
-  end lut40056;
-
-  architecture Structure of lut40056 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0400")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40057
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40057 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
-
-  end lut40057;
-
-  architecture Structure of lut40057 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF4F8")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_63
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_63 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_63";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
-
-  end SLICE_63;
-
-  architecture Structure of SLICE_63 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_0_0_a3_0: lut40056
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRowColSel_0_0: lut40057
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRowColSel: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40058
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40058 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
-
-  end lut40058;
-
-  architecture Structure of lut40058 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40059
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40059 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
-
-  end lut40059;
-
-  architecture Structure of lut40059 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDDFC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_64
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_64 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_64";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
-
-  end SLICE_64;
-
-  architecture Structure of SLICE_64 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0049
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40059
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS15_0_a2: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nUFMCS_s_0_N_5_i: lut40059
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nUFMCS: vmuxregsre0049
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40060
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40060 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
-
-  end lut40060;
-
-  architecture Structure of lut40060 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0002")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40061
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40061 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
-
-  end lut40061;
-
-  architecture Structure of lut40061 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity nRWE_RNO_1_SLICE_65
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWE_RNO_1_SLICE_65 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          OFX0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
-
-  end nRWE_RNO_1_SLICE_65;
-
-  architecture Structure of nRWE_RNO_1_SLICE_65 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_1_SLICE_65_K1: lut40060
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
-    nRWE_RNO_1_GATE: lut40061
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
-    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
-      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
-                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
-                Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     7 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     8 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40062
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40062 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
-
-  end lut40062;
-
-  architecture Structure of lut40062 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0F03")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40063
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40063 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
-
-  end lut40063;
-
-  architecture Structure of lut40063 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_66
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_66 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_66";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
-
-  end SLICE_66;
-
-  architecture Structure of SLICE_66 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS_s_0_N_5_i_N_2L1: lut40062
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_a2_2_2: lut40063
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40064
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40064 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
-
-  end lut40064;
-
-  architecture Structure of lut40064 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0008")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40065
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40065 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
-
-  end lut40065;
-
-  architecture Structure of lut40065 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0066
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0066 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0066 : ENTITY IS TRUE;
-
-  end vmuxregsre0066;
-
-  architecture Structure of vmuxregsre0066 is
-    component FL1P3JY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3JY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_67
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_67 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_67";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
-
-  end SLICE_67;
-
-  architecture Structure of SLICE_67 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40065
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0066
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK_1_sqmuxa_0_a2: lut40064
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG18_0_a2: lut40065
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_5: vmuxregsre0066
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_4: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
-      Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40067
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40067 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
-
-  end lut40067;
-
-  architecture Structure of lut40067 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40068
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40068 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
-
-  end lut40068;
-
-  architecture Structure of lut40068 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF8F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_68
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_68 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_68";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
-
-  end SLICE_68;
-
-  architecture Structure of SLICE_68 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40067
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40068
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0_1: lut40067
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_14_i_0: lut40068
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40069
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40069 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
-
-  end lut40069;
-
-  architecture Structure of lut40069 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0004")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40070
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40070 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
-
-  end lut40070;
-
-  architecture Structure of lut40070 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF8F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_69
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_69 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_69";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
-
-  end SLICE_69;
-
-  architecture Structure of SLICE_69 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40070
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_1: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_0: lut40070
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40071
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40071 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
-
-  end lut40071;
-
-  architecture Structure of lut40071 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40072
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40072 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
-
-  end lut40072;
-
-  architecture Structure of lut40072 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA0A0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_70
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_70 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_70";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
-
-  end SLICE_70;
-
-  architecture Structure of SLICE_70 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40071
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0: lut40071
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2: lut40072
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40073
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40073 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
-
-  end lut40073;
-
-  architecture Structure of lut40073 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40074
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40074 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
-
-  end lut40074;
-
-  architecture Structure of lut40074 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_71
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_71 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_71";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
-
-  end SLICE_71;
-
-  architecture Structure of SLICE_71 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40073
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40074
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_4: lut40073
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2_0_10: lut40074
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40075
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40075 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
-
-  end lut40075;
-
-  architecture Structure of lut40075 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40076
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40076 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
-
-  end lut40076;
-
-  architecture Structure of lut40076 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xACA0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_72
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_72 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_72";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
-
-  end SLICE_72;
-
-  architecture Structure of SLICE_72 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40075
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40076
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0: lut40075
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_m2: lut40076
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_3: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_2: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40077
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40077 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
-
-  end lut40077;
-
-  architecture Structure of lut40077 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFBFF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_73
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_73 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_73";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
-
-  end SLICE_73;
-
-  architecture Structure of SLICE_73 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_0_sqmuxa_0_o2: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdUFMCS: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CmdUFMCLK: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40078
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40078 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
-
-  end lut40078;
-
-  architecture Structure of lut40078 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8888")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40079
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40079 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
-
-  end lut40079;
-
-  architecture Structure of lut40079 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_74
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_74 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_74";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
-
-  end SLICE_74;
-
-  architecture Structure of SLICE_74 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40078
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40079
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    InitReady3_0_a2_3: lut40078
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady3_0_a2: lut40079
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdUFMSDI: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40080
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40080 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
-
-  end lut40080;
-
-  architecture Structure of lut40080 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFDD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40081
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40081 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
-
-  end lut40081;
-
-  architecture Structure of lut40081 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0003")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_75
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_75 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_75";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
-
-  end SLICE_75;
-
-  architecture Structure of SLICE_75 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40080
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40081
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_o2_0: lut40080
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_4_u_i_a2_0: lut40081
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CASr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40082
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40082 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
-
-  end lut40082;
-
-  architecture Structure of lut40082 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3300")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40083
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40083 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
-
-  end lut40083;
-
-  architecture Structure of lut40083 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_76
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_76 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_76";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
-
-  end SLICE_76;
-
-  architecture Structure of SLICE_76 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40082
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40083
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_4: lut40082
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_4_0: lut40083
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40084
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40084 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
-
-  end lut40084;
-
-  architecture Structure of lut40084 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40085
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40085 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
-
-  end lut40085;
-
-  architecture Structure of lut40085 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_77
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_77 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_77";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
-
-  end SLICE_77;
-
-  architecture Structure of SLICE_77 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40084
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40085
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_1: lut40084
-      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_5: lut40085
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40086
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40086 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
-
-  end lut40086;
-
-  architecture Structure of lut40086 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33FF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40087
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40087 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
-
-  end lut40087;
-
-  architecture Structure of lut40087 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_78
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_78 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_78";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
-
-  end SLICE_78;
-
-  architecture Structure of SLICE_78 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40086
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40087
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_o2: lut40086
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable17_0_a2_4: lut40087
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CBR_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CBR: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40088
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40088 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
-
-  end lut40088;
-
-  architecture Structure of lut40088 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0088")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40089
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40089 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
-
-  end lut40089;
-
-  architecture Structure of lut40089 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_79
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_79 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_79";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
-
-  end SLICE_79;
-
-  architecture Structure of SLICE_79 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40088
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40089
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_2: lut40088
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_RNO_0: lut40089
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40090
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40090 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
-
-  end lut40090;
-
-  architecture Structure of lut40090 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4005")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_80
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_80 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_80";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
-
-  end SLICE_80;
-
-  architecture Structure of SLICE_80 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vmuxregsre0066
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40082
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40090
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_RNO_1: lut40082
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRCAS_RNO_0: lut40090
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_9: vmuxregsre0066
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_8: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40091
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40091 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
-
-  end lut40091;
-
-  architecture Structure of lut40091 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40092
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40092 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
-
-  end lut40092;
-
-  architecture Structure of lut40092 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_81
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_81 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_81";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
-
-  end SLICE_81;
-
-  architecture Structure of SLICE_81 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40091
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40092
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0_3: lut40091
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_5: lut40092
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    FWEr_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    FWEr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40093
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40093 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
-
-  end lut40093;
-
-  architecture Structure of lut40093 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3230")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40094
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40094 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
-
-  end lut40094;
-
-  architecture Structure of lut40094 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1300")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_82
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_82 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_82";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
-
-  end SLICE_82;
-
-  architecture Structure of SLICE_82 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40093
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40094
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2: lut40093
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_1_sqmuxa_0_a2: lut40094
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr3: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40095
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40095 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
-
-  end lut40095;
-
-  architecture Structure of lut40095 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFEFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40096
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40096 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
-
-  end lut40096;
-
-  architecture Structure of lut40096 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7F7F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_83
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_83 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_83";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
-
-  end SLICE_83;
-
-  architecture Structure of SLICE_83 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40095
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40096
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_o2: lut40095
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_0_sqmuxa_0_o2: lut40096
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RBA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RBA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40097
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40097 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
-
-  end lut40097;
-
-  architecture Structure of lut40097 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0400")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40098
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40098 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
-
-  end lut40098;
-
-  architecture Structure of lut40098 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_84
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_84 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_84";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
-
-  end SLICE_84;
-
-  architecture Structure of SLICE_84 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40097
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40098
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a2_4_2: lut40097
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_a2_6: lut40098
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40099
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40099 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
-
-  end lut40099;
-
-  architecture Structure of lut40099 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40100
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40100 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
-
-  end lut40100;
-
-  architecture Structure of lut40100 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_85
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_85 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_85";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
-
-  end SLICE_85;
-
-  architecture Structure of SLICE_85 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40099
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40100
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2_3: lut40099
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_Din_4: lut40100
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40101
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40101 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
-
-  end lut40101;
-
-  architecture Structure of lut40101 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x55FF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40102
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40102 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
-
-  end lut40102;
-
-  architecture Structure of lut40102 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAAF0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_86
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_86 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_86";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
-
-  end SLICE_86;
-
-  architecture Structure of SLICE_86 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40101
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40102
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQML: lut40101
-      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_9: lut40102
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40103
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40103 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
-
-  end lut40103;
-
-  architecture Structure of lut40103 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00EE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40104
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40104 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
-
-  end lut40104;
-
-  architecture Structure of lut40104 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_87
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_87 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_87";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
-
-  end SLICE_87;
-
-  architecture Structure of SLICE_87 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40103
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40104
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_RNO_0: lut40103
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_a2_8: lut40104
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40105
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40105 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE;
-
-  end lut40105;
-
-  architecture Structure of lut40105 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0C00")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40106
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40106 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
-
-  end lut40106;
-
-  architecture Structure of lut40106 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFAFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_88
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_88 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_88";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
-
-  end SLICE_88;
-
-  architecture Structure of SLICE_88 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40105
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40106
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_3: lut40105
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nCCAS_pad_RNI01SJ: lut40106
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RowA_7: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_6: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, C0_ipd, A0_ipd, M1_dly, 
-      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40107
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40107 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
-
-  end lut40107;
-
-  architecture Structure of lut40107 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF0FF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40108
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40108 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
-
-  end lut40108;
-
-  architecture Structure of lut40108 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCCAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_89
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_89 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_89";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
-
-  end SLICE_89;
-
-  architecture Structure of SLICE_89 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40107
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40108
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQMH: lut40107
-      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_8: lut40108
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40109
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40109 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
-
-  end lut40109;
-
-  architecture Structure of lut40109 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCCC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40110
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40110 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE;
-
-  end lut40110;
-
-  architecture Structure of lut40110 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEE44")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_90
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_90 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_90";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
-
-  end SLICE_90;
-
-  architecture Structure of SLICE_90 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40109
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40110
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_CMDWR: lut40109
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_0: lut40110
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40111
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40111 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE;
-
-  end lut40111;
-
-  architecture Structure of lut40111 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFA0A")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40112
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40112 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE;
-
-  end lut40112;
-
-  architecture Structure of lut40112 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCFC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_91
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_91 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_91";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
-
-  end SLICE_91;
-
-  architecture Structure of SLICE_91 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40111
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40112
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_7: lut40111
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_1: lut40112
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40113
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40113 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE;
-
-  end lut40113;
-
-  architecture Structure of lut40113 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAFA0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40114
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40114 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE;
-
-  end lut40114;
-
-  architecture Structure of lut40114 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFC0C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_92
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_92 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_92";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
-
-  end SLICE_92;
-
-  architecture Structure of SLICE_92 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40113
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40114
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_6: lut40113
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_2: lut40114
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40115
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40115 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE;
-
-  end lut40115;
-
-  architecture Structure of lut40115 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xE4E4")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_93
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_93 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_93";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
-
-  end SLICE_93;
-
-  architecture Structure of SLICE_93 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40115
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_5: lut40115
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_3: lut40040
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40116
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40116 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE;
-
-  end lut40116;
-
-  architecture Structure of lut40116 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1111")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_94
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_94 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_94";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
-
-  end SLICE_94;
-
-  architecture Structure of SLICE_94 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0066
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40116
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40116
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN_8_u_0_a2_1_s: lut40072
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RA10: vmuxregsre0066
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, A0_ipd, M0_dly, LSR_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf is
-    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-          PAD: out Std_logic; PADI: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
-
-  end mjiobuf;
-
-  architecture Structure of mjiobuf is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-    component OBW
-      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PADI, O=>Z);
-    INST2: OBW
-      port map (I=>I, T=>T, O=>PAD);
-  end Structure;
-
--- entity RD_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD0 	: VitalDelayType := 0 ns;
-      tpw_RD0_posedge	: VitalDelayType := 0 ns;
-      tpw_RD0_negedge	: VitalDelayType := 0 ns;
-      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD0: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
-
-  end RD_0_B;
-
-  architecture Structure of RD_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD0_ipd 	: std_logic := 'X';
-    signal RD0_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_0: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
-                PADI=>RD0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD0_zd         	: std_logic := 'X';
-    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD0_RD0          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD0_ipd,
-        TestSignalName => "RD0",
-        Period => tperiod_RD0,
-        PulseWidthHigh => tpw_RD0_posedge,
-        PulseWidthLow => tpw_RD0_negedge,
-        PeriodData => periodcheckinfo_RD0,
-        Violation => tviol_RD0_RD0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD0_zd 	:= RD0_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
-                           PathDelay => tpd_RD0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD0,
-                           PathCondition => TRUE)),
-      GlitchData => RD0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0117
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0117 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0117 : ENTITY IS TRUE;
-
-  end mjiobuf0117;
-
-  architecture Structure of mjiobuf0117 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity Dout_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
-
-  end Dout_0_B;
-
-  architecture Structure of Dout_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout0_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_0: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
-    VARIABLE Dout0_zd         	: std_logic := 'X';
-    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout0_zd 	:= Dout0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout0,
-                           PathCondition => TRUE)),
-      GlitchData => Dout0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0118
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0118 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0118 : ENTITY IS TRUE;
-
-  end mjiobuf0118;
-
-  architecture Structure of mjiobuf0118 is
-    component IBPD
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPD
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity PHI2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity PHI2B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2B";
-
-      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_PHI2S 	: VitalDelayType := 0 ns;
-      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
-      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; PHI2S: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
-
-  end PHI2B;
-
-  architecture Structure of PHI2B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PHI2S_ipd 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    PHI2_pad: mjiobuf0118
-      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
-    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => PHI2S_ipd,
-        TestSignalName => "PHI2S",
-        Period => tperiod_PHI2S,
-        PulseWidthHigh => tpw_PHI2S_posedge,
-        PulseWidthLow => tpw_PHI2S_negedge,
-        PeriodData => periodcheckinfo_PHI2S,
-        Violation => tviol_PHI2S_PHI2S,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
-                           PathDelay => tpd_PHI2S_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0119
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0119 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0119 : ENTITY IS TRUE;
-
-  end mjiobuf0119;
-
-  architecture Structure of mjiobuf0119 is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity UFMSDOB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDOB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDOB";
-
-      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
-
-  end UFMSDOB;
-
-  architecture Structure of UFMSDOB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal UFMSDOS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    UFMSDO_pad: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
-    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => UFMSDOS_ipd,
-        TestSignalName => "UFMSDOS",
-        Period => tperiod_UFMSDOS,
-        PulseWidthHigh => tpw_UFMSDOS_posedge,
-        PulseWidthLow => tpw_UFMSDOS_negedge,
-        PeriodData => periodcheckinfo_UFMSDOS,
-        Violation => tviol_UFMSDOS_UFMSDOS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
-                           PathDelay => tpd_UFMSDOS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0120
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0120 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0120 : ENTITY IS TRUE;
-
-  end mjiobuf0120;
-
-  architecture Structure of mjiobuf0120 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity UFMSDIB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDIB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDIB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
-
-  end UFMSDIB;
-
-  architecture Structure of UFMSDIB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMSDIS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMSDI_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
-    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
-    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMSDIS_zd 	:= UFMSDIS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMSDIS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMSDIS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLKB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
-
-  end UFMCLKB;
-
-  architecture Structure of UFMCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMCLKS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMCLK_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
-    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
-    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMCLKS_zd 	:= UFMCLKS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMCLKS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMCLKS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nUFMCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nUFMCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
-
-  end nUFMCSB;
-
-  architecture Structure of nUFMCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nUFMCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nUFMCS_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
-    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
-    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nUFMCSS_zd 	:= nUFMCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nUFMCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nUFMCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMLB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMLB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMLB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
-
-  end RDQMLB;
-
-  architecture Structure of RDQMLB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMLS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQML_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
-    VARIABLE RDQMLS_zd         	: std_logic := 'X';
-    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMLS_zd 	:= RDQMLS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMLS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMLS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMHB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMHB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMHB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
-
-  end RDQMHB;
-
-  architecture Structure of RDQMHB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMHS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQMH_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
-    VARIABLE RDQMHS_zd         	: std_logic := 'X';
-    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMHS_zd 	:= RDQMHS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMHS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMHS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
-
-  end nRCASB;
-
-  architecture Structure of nRCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCASS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCAS_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
-    VARIABLE nRCASS_zd         	: std_logic := 'X';
-    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCASS_zd 	:= nRCASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRRASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
-
-  end nRRASB;
-
-  architecture Structure of nRRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRRASS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRRAS_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
-    VARIABLE nRRASS_zd         	: std_logic := 'X';
-    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRRASS_zd 	:= nRRASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRRASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRRASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRWES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
-
-  end nRWEB;
-
-  architecture Structure of nRWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRWES_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRWE_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>nRWES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
-    VARIABLE nRWES_zd         	: std_logic := 'X';
-    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRWES_zd 	:= nRWES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRWES,
-                           PathCondition => TRUE)),
-      GlitchData => nRWES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCKEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RCKES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
-
-  end RCKEB;
-
-  architecture Structure of RCKEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RCKES_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RCKE_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RCKES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
-    VARIABLE RCKES_zd         	: std_logic := 'X';
-    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RCKES_zd 	:= RCKES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RCKES,
-                           PathCondition => TRUE)),
-      GlitchData => RCKES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCLKB";
-
-      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RCLKS 	: VitalDelayType := 0 ns;
-      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
-      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; RCLKS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
-
-  end RCLKB;
-
-  architecture Structure of RCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal RCLKS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    RCLK_pad: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
-    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RCLKS_ipd,
-        TestSignalName => "RCLKS",
-        Period => tperiod_RCLKS,
-        PulseWidthHigh => tpw_RCLKS_posedge,
-        PulseWidthLow => tpw_RCLKS_negedge,
-        PeriodData => periodcheckinfo_RCLKS,
-        Violation => tviol_RCLKS_RCLKS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
-                           PathDelay => tpd_RCLKS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
-
-  end nRCSB;
-
-  architecture Structure of nRCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCS_pad: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
-    VARIABLE nRCSS_zd         	: std_logic := 'X';
-    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCSS_zd 	:= nRCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD7 	: VitalDelayType := 0 ns;
-      tpw_RD7_posedge	: VitalDelayType := 0 ns;
-      tpw_RD7_negedge	: VitalDelayType := 0 ns;
-      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD7: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
-
-  end RD_7_B;
-
-  architecture Structure of RD_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD7_ipd 	: std_logic := 'X';
-    signal RD7_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_7: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
-                PADI=>RD7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD7_zd         	: std_logic := 'X';
-    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD7_RD7          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD7_ipd,
-        TestSignalName => "RD7",
-        Period => tperiod_RD7,
-        PulseWidthHigh => tpw_RD7_posedge,
-        PulseWidthLow => tpw_RD7_negedge,
-        PeriodData => periodcheckinfo_RD7,
-        Violation => tviol_RD7_RD7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD7_zd 	:= RD7_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
-                           PathDelay => tpd_RD7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD7,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD7,
-                           PathCondition => TRUE)),
-      GlitchData => RD7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD6 	: VitalDelayType := 0 ns;
-      tpw_RD6_posedge	: VitalDelayType := 0 ns;
-      tpw_RD6_negedge	: VitalDelayType := 0 ns;
-      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD6: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
-
-  end RD_6_B;
-
-  architecture Structure of RD_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD6_ipd 	: std_logic := 'X';
-    signal RD6_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_6: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
-                PADI=>RD6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD6_zd         	: std_logic := 'X';
-    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD6_RD6          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD6_ipd,
-        TestSignalName => "RD6",
-        Period => tperiod_RD6,
-        PulseWidthHigh => tpw_RD6_posedge,
-        PulseWidthLow => tpw_RD6_negedge,
-        PeriodData => periodcheckinfo_RD6,
-        Violation => tviol_RD6_RD6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD6_zd 	:= RD6_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
-                           PathDelay => tpd_RD6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD6,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD6,
-                           PathCondition => TRUE)),
-      GlitchData => RD6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD5 	: VitalDelayType := 0 ns;
-      tpw_RD5_posedge	: VitalDelayType := 0 ns;
-      tpw_RD5_negedge	: VitalDelayType := 0 ns;
-      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD5: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
-
-  end RD_5_B;
-
-  architecture Structure of RD_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD5_ipd 	: std_logic := 'X';
-    signal RD5_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_5: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
-                PADI=>RD5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD5_zd         	: std_logic := 'X';
-    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD5_RD5          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD5_ipd,
-        TestSignalName => "RD5",
-        Period => tperiod_RD5,
-        PulseWidthHigh => tpw_RD5_posedge,
-        PulseWidthLow => tpw_RD5_negedge,
-        PeriodData => periodcheckinfo_RD5,
-        Violation => tviol_RD5_RD5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD5_zd 	:= RD5_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
-                           PathDelay => tpd_RD5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD5,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD5,
-                           PathCondition => TRUE)),
-      GlitchData => RD5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD4 	: VitalDelayType := 0 ns;
-      tpw_RD4_posedge	: VitalDelayType := 0 ns;
-      tpw_RD4_negedge	: VitalDelayType := 0 ns;
-      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD4: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
-
-  end RD_4_B;
-
-  architecture Structure of RD_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD4_ipd 	: std_logic := 'X';
-    signal RD4_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_4: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
-                PADI=>RD4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD4_zd         	: std_logic := 'X';
-    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD4_RD4          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD4_ipd,
-        TestSignalName => "RD4",
-        Period => tperiod_RD4,
-        PulseWidthHigh => tpw_RD4_posedge,
-        PulseWidthLow => tpw_RD4_negedge,
-        PeriodData => periodcheckinfo_RD4,
-        Violation => tviol_RD4_RD4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD4_zd 	:= RD4_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
-                           PathDelay => tpd_RD4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD4,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD4,
-                           PathCondition => TRUE)),
-      GlitchData => RD4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD3 	: VitalDelayType := 0 ns;
-      tpw_RD3_posedge	: VitalDelayType := 0 ns;
-      tpw_RD3_negedge	: VitalDelayType := 0 ns;
-      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD3: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
-
-  end RD_3_B;
-
-  architecture Structure of RD_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD3_ipd 	: std_logic := 'X';
-    signal RD3_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_3: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
-                PADI=>RD3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD3_zd         	: std_logic := 'X';
-    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD3_RD3          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD3_ipd,
-        TestSignalName => "RD3",
-        Period => tperiod_RD3,
-        PulseWidthHigh => tpw_RD3_posedge,
-        PulseWidthLow => tpw_RD3_negedge,
-        PeriodData => periodcheckinfo_RD3,
-        Violation => tviol_RD3_RD3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD3_zd 	:= RD3_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
-                           PathDelay => tpd_RD3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD3,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD3,
-                           PathCondition => TRUE)),
-      GlitchData => RD3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD2 	: VitalDelayType := 0 ns;
-      tpw_RD2_posedge	: VitalDelayType := 0 ns;
-      tpw_RD2_negedge	: VitalDelayType := 0 ns;
-      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD2: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
-
-  end RD_2_B;
-
-  architecture Structure of RD_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD2_ipd 	: std_logic := 'X';
-    signal RD2_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_2: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
-                PADI=>RD2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD2_zd         	: std_logic := 'X';
-    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD2_RD2          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD2_ipd,
-        TestSignalName => "RD2",
-        Period => tperiod_RD2,
-        PulseWidthHigh => tpw_RD2_posedge,
-        PulseWidthLow => tpw_RD2_negedge,
-        PeriodData => periodcheckinfo_RD2,
-        Violation => tviol_RD2_RD2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD2_zd 	:= RD2_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
-                           PathDelay => tpd_RD2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD2,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD2,
-                           PathCondition => TRUE)),
-      GlitchData => RD2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD1 	: VitalDelayType := 0 ns;
-      tpw_RD1_posedge	: VitalDelayType := 0 ns;
-      tpw_RD1_negedge	: VitalDelayType := 0 ns;
-      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD1: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
-
-  end RD_1_B;
-
-  architecture Structure of RD_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD1_ipd 	: std_logic := 'X';
-    signal RD1_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_1: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
-                PADI=>RD1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD1_zd         	: std_logic := 'X';
-    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD1_RD1          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD1_ipd,
-        TestSignalName => "RD1",
-        Period => tperiod_RD1,
-        PulseWidthHigh => tpw_RD1_posedge,
-        PulseWidthLow => tpw_RD1_negedge,
-        PeriodData => periodcheckinfo_RD1,
-        Violation => tviol_RD1_RD1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD1_zd 	:= RD1_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
-                           PathDelay => tpd_RD1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD1,
-                           PathCondition => TRUE)),
-      GlitchData => RD1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_11_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA11: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
-
-  end RA_11_B;
-
-  architecture Structure of RA_11_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA11_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_11: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA11_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
-    VARIABLE RA11_zd         	: std_logic := 'X';
-    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA11_zd 	:= RA11_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA11,
-                           PathCondition => TRUE)),
-      GlitchData => RA11_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_10_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_10_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA10: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
-
-  end RA_10_B;
-
-  architecture Structure of RA_10_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA10_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_10: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA10_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
-    VARIABLE RA10_zd         	: std_logic := 'X';
-    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA10_zd 	:= RA10_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA10,
-                           PathCondition => TRUE)),
-      GlitchData => RA10_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_9_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA9: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
-
-  end RA_9_B;
-
-  architecture Structure of RA_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA9_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_9: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA9_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
-    VARIABLE RA9_zd         	: std_logic := 'X';
-    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA9_zd 	:= RA9_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA9,
-                           PathCondition => TRUE)),
-      GlitchData => RA9_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_8_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA8: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
-
-  end RA_8_B;
-
-  architecture Structure of RA_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA8_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_8: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA8_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
-    VARIABLE RA8_zd         	: std_logic := 'X';
-    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA8_zd 	:= RA8_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA8,
-                           PathCondition => TRUE)),
-      GlitchData => RA8_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
-
-  end RA_7_B;
-
-  architecture Structure of RA_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA7_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_7: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
-    VARIABLE RA7_zd         	: std_logic := 'X';
-    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA7_zd 	:= RA7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA7,
-                           PathCondition => TRUE)),
-      GlitchData => RA7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
-
-  end RA_6_B;
-
-  architecture Structure of RA_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA6_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_6: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
-    VARIABLE RA6_zd         	: std_logic := 'X';
-    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA6_zd 	:= RA6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA6,
-                           PathCondition => TRUE)),
-      GlitchData => RA6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
-
-  end RA_5_B;
-
-  architecture Structure of RA_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA5_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_5: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
-    VARIABLE RA5_zd         	: std_logic := 'X';
-    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA5_zd 	:= RA5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA5,
-                           PathCondition => TRUE)),
-      GlitchData => RA5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
-
-  end RA_4_B;
-
-  architecture Structure of RA_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA4_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_4: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
-    VARIABLE RA4_zd         	: std_logic := 'X';
-    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA4_zd 	:= RA4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA4,
-                           PathCondition => TRUE)),
-      GlitchData => RA4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
-
-  end RA_3_B;
-
-  architecture Structure of RA_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA3_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_3: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
-    VARIABLE RA3_zd         	: std_logic := 'X';
-    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA3_zd 	:= RA3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA3,
-                           PathCondition => TRUE)),
-      GlitchData => RA3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
-
-  end RA_2_B;
-
-  architecture Structure of RA_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA2_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_2: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
-    VARIABLE RA2_zd         	: std_logic := 'X';
-    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA2_zd 	:= RA2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA2,
-                           PathCondition => TRUE)),
-      GlitchData => RA2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
-
-  end RA_1_B;
-
-  architecture Structure of RA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA1_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_1: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
-    VARIABLE RA1_zd         	: std_logic := 'X';
-    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA1_zd 	:= RA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA1,
-                           PathCondition => TRUE)),
-      GlitchData => RA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
-
-  end RA_0_B;
-
-  architecture Structure of RA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA0_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_0: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
-    VARIABLE RA0_zd         	: std_logic := 'X';
-    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA0_zd 	:= RA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA0,
-                           PathCondition => TRUE)),
-      GlitchData => RA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
-
-  end RBA_1_B;
-
-  architecture Structure of RBA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA1_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_1: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RBA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
-    VARIABLE RBA1_zd         	: std_logic := 'X';
-    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA1_zd 	:= RBA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA1,
-                           PathCondition => TRUE)),
-      GlitchData => RBA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
-
-  end RBA_0_B;
-
-  architecture Structure of RBA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA0_out 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_0: mjiobuf0120
-      port map (I=>PADDO_ipd, PAD=>RBA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
-    VARIABLE RBA0_zd         	: std_logic := 'X';
-    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA0_zd 	:= RBA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA0,
-                           PathCondition => TRUE)),
-      GlitchData => RBA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0121
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0121 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0121 : ENTITY IS TRUE;
-
-  end mjiobuf0121;
-
-  architecture Structure of mjiobuf0121 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity LEDB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity LEDB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "LEDB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; LEDS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
-
-  end LEDB;
-
-  architecture Structure of LEDB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal LEDS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    LED_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>LEDS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
-    VARIABLE LEDS_zd         	: std_logic := 'X';
-    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    LEDS_zd 	:= LEDS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_LEDS,
-                           PathCondition => TRUE)),
-      GlitchData => LEDS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nFWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nFWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nFWEB";
-
-      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nFWES 	: VitalDelayType := 0 ns;
-      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
-      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nFWES: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
-
-  end nFWEB;
-
-  architecture Structure of nFWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nFWES_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nFWE_pad: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
-    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nFWES_ipd,
-        TestSignalName => "nFWES",
-        Period => tperiod_nFWES,
-        PulseWidthHigh => tpw_nFWES_posedge,
-        PulseWidthLow => tpw_nFWES_negedge,
-        PeriodData => periodcheckinfo_nFWES,
-        Violation => tviol_nFWES_nFWES,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
-                           PathDelay => tpd_nFWES_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0122
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0122 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0122 : ENTITY IS TRUE;
-
-  end mjiobuf0122;
-
-  architecture Structure of mjiobuf0122 is
-    component IBPU
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPU
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity nCRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCRASB";
-
-      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCRASS 	: VitalDelayType := 0 ns;
-      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCRASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
-
-  end nCRASB;
-
-  architecture Structure of nCRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCRASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0122
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCRAS_pad: mjiobuf0122
-      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCRASS_ipd,
-        TestSignalName => "nCRASS",
-        Period => tperiod_nCRASS,
-        PulseWidthHigh => tpw_nCRASS_posedge,
-        PulseWidthLow => tpw_nCRASS_negedge,
-        PeriodData => periodcheckinfo_nCRASS,
-        Violation => tviol_nCRASS_nCRASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
-                           PathDelay => tpd_nCRASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCCASB";
-
-      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCCASS 	: VitalDelayType := 0 ns;
-      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCCASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
-
-  end nCCASB;
-
-  architecture Structure of nCCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCCASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0122
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCCAS_pad: mjiobuf0122
-      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCCASS_ipd,
-        TestSignalName => "nCCASS",
-        Period => tperiod_nCCASS,
-        PulseWidthHigh => tpw_nCCASS_posedge,
-        PulseWidthLow => tpw_nCCASS_negedge,
-        PeriodData => periodcheckinfo_nCCASS,
-        Violation => tviol_nCCASS_nCCASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
-                           PathDelay => tpd_nCCASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
-
-  end Dout_7_B;
-
-  architecture Structure of Dout_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout7_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_7: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
-    VARIABLE Dout7_zd         	: std_logic := 'X';
-    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout7_zd 	:= Dout7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout7,
-                           PathCondition => TRUE)),
-      GlitchData => Dout7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
-
-  end Dout_6_B;
-
-  architecture Structure of Dout_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout6_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_6: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
-    VARIABLE Dout6_zd         	: std_logic := 'X';
-    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout6_zd 	:= Dout6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout6,
-                           PathCondition => TRUE)),
-      GlitchData => Dout6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
-
-  end Dout_5_B;
-
-  architecture Structure of Dout_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout5_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_5: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
-    VARIABLE Dout5_zd         	: std_logic := 'X';
-    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout5_zd 	:= Dout5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout5,
-                           PathCondition => TRUE)),
-      GlitchData => Dout5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
-
-  end Dout_4_B;
-
-  architecture Structure of Dout_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout4_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_4: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
-    VARIABLE Dout4_zd         	: std_logic := 'X';
-    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout4_zd 	:= Dout4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout4,
-                           PathCondition => TRUE)),
-      GlitchData => Dout4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
-
-  end Dout_3_B;
-
-  architecture Structure of Dout_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout3_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_3: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
-    VARIABLE Dout3_zd         	: std_logic := 'X';
-    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout3_zd 	:= Dout3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout3,
-                           PathCondition => TRUE)),
-      GlitchData => Dout3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
-
-  end Dout_2_B;
-
-  architecture Structure of Dout_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout2_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_2: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
-    VARIABLE Dout2_zd         	: std_logic := 'X';
-    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout2_zd 	:= Dout2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout2,
-                           PathCondition => TRUE)),
-      GlitchData => Dout2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
-
-  end Dout_1_B;
-
-  architecture Structure of Dout_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout1_out 	: std_logic := 'X';
-
-    component mjiobuf0117
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_1: mjiobuf0117
-      port map (I=>PADDO_ipd, PAD=>Dout1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
-    VARIABLE Dout1_zd         	: std_logic := 'X';
-    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout1_zd 	:= Dout1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout1,
-                           PathCondition => TRUE)),
-      GlitchData => Dout1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_B";
-
-      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din7 	: VitalDelayType := 0 ns;
-      tpw_Din7_posedge	: VitalDelayType := 0 ns;
-      tpw_Din7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
-
-  end Din_7_B;
-
-  architecture Structure of Din_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_7: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din7_Din7          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din7_ipd,
-        TestSignalName => "Din7",
-        Period => tperiod_Din7,
-        PulseWidthHigh => tpw_Din7_posedge,
-        PulseWidthLow => tpw_Din7_negedge,
-        PeriodData => periodcheckinfo_Din7,
-        Violation => tviol_Din7_Din7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
-                           PathDelay => tpd_Din7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_B";
-
-      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din6 	: VitalDelayType := 0 ns;
-      tpw_Din6_posedge	: VitalDelayType := 0 ns;
-      tpw_Din6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
-
-  end Din_6_B;
-
-  architecture Structure of Din_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_6: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din6_Din6          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din6_ipd,
-        TestSignalName => "Din6",
-        Period => tperiod_Din6,
-        PulseWidthHigh => tpw_Din6_posedge,
-        PulseWidthLow => tpw_Din6_negedge,
-        PeriodData => periodcheckinfo_Din6,
-        Violation => tviol_Din6_Din6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
-                           PathDelay => tpd_Din6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_B";
-
-      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din5 	: VitalDelayType := 0 ns;
-      tpw_Din5_posedge	: VitalDelayType := 0 ns;
-      tpw_Din5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
-
-  end Din_5_B;
-
-  architecture Structure of Din_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_5: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din5_Din5          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din5_ipd,
-        TestSignalName => "Din5",
-        Period => tperiod_Din5,
-        PulseWidthHigh => tpw_Din5_posedge,
-        PulseWidthLow => tpw_Din5_negedge,
-        PeriodData => periodcheckinfo_Din5,
-        Violation => tviol_Din5_Din5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
-                           PathDelay => tpd_Din5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_B";
-
-      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din4 	: VitalDelayType := 0 ns;
-      tpw_Din4_posedge	: VitalDelayType := 0 ns;
-      tpw_Din4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
-
-  end Din_4_B;
-
-  architecture Structure of Din_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_4: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din4_Din4          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din4_ipd,
-        TestSignalName => "Din4",
-        Period => tperiod_Din4,
-        PulseWidthHigh => tpw_Din4_posedge,
-        PulseWidthLow => tpw_Din4_negedge,
-        PeriodData => periodcheckinfo_Din4,
-        Violation => tviol_Din4_Din4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
-                           PathDelay => tpd_Din4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_B";
-
-      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din3 	: VitalDelayType := 0 ns;
-      tpw_Din3_posedge	: VitalDelayType := 0 ns;
-      tpw_Din3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
-
-  end Din_3_B;
-
-  architecture Structure of Din_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_3: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din3_Din3          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din3_ipd,
-        TestSignalName => "Din3",
-        Period => tperiod_Din3,
-        PulseWidthHigh => tpw_Din3_posedge,
-        PulseWidthLow => tpw_Din3_negedge,
-        PeriodData => periodcheckinfo_Din3,
-        Violation => tviol_Din3_Din3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
-                           PathDelay => tpd_Din3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_B";
-
-      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din2 	: VitalDelayType := 0 ns;
-      tpw_Din2_posedge	: VitalDelayType := 0 ns;
-      tpw_Din2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
-
-  end Din_2_B;
-
-  architecture Structure of Din_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_2: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din2_Din2          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din2_ipd,
-        TestSignalName => "Din2",
-        Period => tperiod_Din2,
-        PulseWidthHigh => tpw_Din2_posedge,
-        PulseWidthLow => tpw_Din2_negedge,
-        PeriodData => periodcheckinfo_Din2,
-        Violation => tviol_Din2_Din2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
-                           PathDelay => tpd_Din2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_B";
-
-      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din1 	: VitalDelayType := 0 ns;
-      tpw_Din1_posedge	: VitalDelayType := 0 ns;
-      tpw_Din1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
-
-  end Din_1_B;
-
-  architecture Structure of Din_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_1: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din1_Din1          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din1_ipd,
-        TestSignalName => "Din1",
-        Period => tperiod_Din1,
-        PulseWidthHigh => tpw_Din1_posedge,
-        PulseWidthLow => tpw_Din1_negedge,
-        PeriodData => periodcheckinfo_Din1,
-        Violation => tviol_Din1_Din1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
-                           PathDelay => tpd_Din1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_B";
-
-      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din0 	: VitalDelayType := 0 ns;
-      tpw_Din0_posedge	: VitalDelayType := 0 ns;
-      tpw_Din0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
-
-  end Din_0_B;
-
-  architecture Structure of Din_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_0: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>Din0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din0_Din0          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din0_ipd,
-        TestSignalName => "Din0",
-        Period => tperiod_Din0,
-        PulseWidthHigh => tpw_Din0_posedge,
-        PulseWidthLow => tpw_Din0_negedge,
-        PeriodData => periodcheckinfo_Din0,
-        Violation => tviol_Din0_Din0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
-                           PathDelay => tpd_Din0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_1_B";
-
-      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW1 	: VitalDelayType := 0 ns;
-      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
-
-  end CROW_1_B;
-
-  architecture Structure of CROW_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_1: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW1_ipd,
-        TestSignalName => "CROW1",
-        Period => tperiod_CROW1,
-        PulseWidthHigh => tpw_CROW1_posedge,
-        PulseWidthLow => tpw_CROW1_negedge,
-        PeriodData => periodcheckinfo_CROW1,
-        Violation => tviol_CROW1_CROW1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
-                           PathDelay => tpd_CROW1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_0_B";
-
-      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW0 	: VitalDelayType := 0 ns;
-      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
-
-  end CROW_0_B;
-
-  architecture Structure of CROW_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_0: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW0_ipd,
-        TestSignalName => "CROW0",
-        Period => tperiod_CROW0,
-        PulseWidthHigh => tpw_CROW0_posedge,
-        PulseWidthLow => tpw_CROW0_negedge,
-        PeriodData => periodcheckinfo_CROW0,
-        Violation => tviol_CROW0_CROW0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
-                           PathDelay => tpd_CROW0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_9_B";
-
-      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin9 	: VitalDelayType := 0 ns;
-      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin9: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
-
-  end MAin_9_B;
-
-  architecture Structure of MAin_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin9_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_9: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin9_ipd,
-        TestSignalName => "MAin9",
-        Period => tperiod_MAin9,
-        PulseWidthHigh => tpw_MAin9_posedge,
-        PulseWidthLow => tpw_MAin9_negedge,
-        PeriodData => periodcheckinfo_MAin9,
-        Violation => tviol_MAin9_MAin9,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
-                           PathDelay => tpd_MAin9_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_8_B";
-
-      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin8 	: VitalDelayType := 0 ns;
-      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin8: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
-
-  end MAin_8_B;
-
-  architecture Structure of MAin_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin8_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_8: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin8_ipd,
-        TestSignalName => "MAin8",
-        Period => tperiod_MAin8,
-        PulseWidthHigh => tpw_MAin8_posedge,
-        PulseWidthLow => tpw_MAin8_negedge,
-        PeriodData => periodcheckinfo_MAin8,
-        Violation => tviol_MAin8_MAin8,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
-                           PathDelay => tpd_MAin8_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_7_B";
-
-      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin7 	: VitalDelayType := 0 ns;
-      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
-
-  end MAin_7_B;
-
-  architecture Structure of MAin_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_7: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin7_ipd,
-        TestSignalName => "MAin7",
-        Period => tperiod_MAin7,
-        PulseWidthHigh => tpw_MAin7_posedge,
-        PulseWidthLow => tpw_MAin7_negedge,
-        PeriodData => periodcheckinfo_MAin7,
-        Violation => tviol_MAin7_MAin7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
-                           PathDelay => tpd_MAin7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_6_B";
-
-      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin6 	: VitalDelayType := 0 ns;
-      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
-
-  end MAin_6_B;
-
-  architecture Structure of MAin_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_6: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin6_ipd,
-        TestSignalName => "MAin6",
-        Period => tperiod_MAin6,
-        PulseWidthHigh => tpw_MAin6_posedge,
-        PulseWidthLow => tpw_MAin6_negedge,
-        PeriodData => periodcheckinfo_MAin6,
-        Violation => tviol_MAin6_MAin6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
-                           PathDelay => tpd_MAin6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_5_B";
-
-      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin5 	: VitalDelayType := 0 ns;
-      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
-
-  end MAin_5_B;
-
-  architecture Structure of MAin_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_5: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin5_ipd,
-        TestSignalName => "MAin5",
-        Period => tperiod_MAin5,
-        PulseWidthHigh => tpw_MAin5_posedge,
-        PulseWidthLow => tpw_MAin5_negedge,
-        PeriodData => periodcheckinfo_MAin5,
-        Violation => tviol_MAin5_MAin5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
-                           PathDelay => tpd_MAin5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_4_B";
-
-      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin4 	: VitalDelayType := 0 ns;
-      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
-
-  end MAin_4_B;
-
-  architecture Structure of MAin_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_4: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin4_ipd,
-        TestSignalName => "MAin4",
-        Period => tperiod_MAin4,
-        PulseWidthHigh => tpw_MAin4_posedge,
-        PulseWidthLow => tpw_MAin4_negedge,
-        PeriodData => periodcheckinfo_MAin4,
-        Violation => tviol_MAin4_MAin4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
-                           PathDelay => tpd_MAin4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_3_B";
-
-      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin3 	: VitalDelayType := 0 ns;
-      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
-
-  end MAin_3_B;
-
-  architecture Structure of MAin_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_3: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin3_ipd,
-        TestSignalName => "MAin3",
-        Period => tperiod_MAin3,
-        PulseWidthHigh => tpw_MAin3_posedge,
-        PulseWidthLow => tpw_MAin3_negedge,
-        PeriodData => periodcheckinfo_MAin3,
-        Violation => tviol_MAin3_MAin3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
-                           PathDelay => tpd_MAin3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_2_B";
-
-      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin2 	: VitalDelayType := 0 ns;
-      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
-
-  end MAin_2_B;
-
-  architecture Structure of MAin_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_2: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin2_ipd,
-        TestSignalName => "MAin2",
-        Period => tperiod_MAin2,
-        PulseWidthHigh => tpw_MAin2_posedge,
-        PulseWidthLow => tpw_MAin2_negedge,
-        PeriodData => periodcheckinfo_MAin2,
-        Violation => tviol_MAin2_MAin2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
-                           PathDelay => tpd_MAin2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_1_B";
-
-      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin1 	: VitalDelayType := 0 ns;
-      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
-
-  end MAin_1_B;
-
-  architecture Structure of MAin_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_1: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin1_ipd,
-        TestSignalName => "MAin1",
-        Period => tperiod_MAin1,
-        PulseWidthHigh => tpw_MAin1_posedge,
-        PulseWidthLow => tpw_MAin1_negedge,
-        PeriodData => periodcheckinfo_MAin1,
-        Violation => tviol_MAin1_MAin1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
-                           PathDelay => tpd_MAin1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_0_B";
-
-      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin0 	: VitalDelayType := 0 ns;
-      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
-
-  end MAin_0_B;
-
-  architecture Structure of MAin_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_0: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin0_ipd,
-        TestSignalName => "MAin0",
-        Period => tperiod_MAin0,
-        PulseWidthHigh => tpw_MAin0_posedge,
-        PulseWidthLow => tpw_MAin0_negedge,
-        PeriodData => periodcheckinfo_MAin0,
-        Violation => tviol_MAin0_MAin0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
-                           PathDelay => tpd_MAin0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RAM2GS
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RAM2GS is
-    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
-          CROW: in Std_logic_vector (1 downto 0); 
-          Din: in Std_logic_vector (7 downto 0); 
-          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
-          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
-          RBA: out Std_logic_vector (1 downto 0); 
-          RA: out Std_logic_vector (11 downto 0); 
-          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
-          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
-          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
-          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
-          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
-
-
-
-  end RAM2GS;
-
-  architecture Structure of RAM2GS is
-    signal FS_1: Std_logic;
-    signal FS_0: Std_logic;
-    signal RCLK_c: Std_logic;
-    signal FS_cry_1: Std_logic;
-    signal FS_17: Std_logic;
-    signal FS_16: Std_logic;
-    signal FS_cry_15: Std_logic;
-    signal FS_15: Std_logic;
-    signal FS_14: Std_logic;
-    signal FS_cry_13: Std_logic;
-    signal FS_13: Std_logic;
-    signal FS_12: Std_logic;
-    signal FS_cry_11: Std_logic;
-    signal FS_11: Std_logic;
-    signal FS_10: Std_logic;
-    signal FS_cry_9: Std_logic;
-    signal FS_9: Std_logic;
-    signal FS_8: Std_logic;
-    signal FS_cry_7: Std_logic;
-    signal FS_7: Std_logic;
-    signal FS_6: Std_logic;
-    signal FS_cry_5: Std_logic;
-    signal FS_5: Std_logic;
-    signal FS_4: Std_logic;
-    signal FS_cry_3: Std_logic;
-    signal FS_3: Std_logic;
-    signal FS_2: Std_logic;
-    signal CmdEnable17_0_a2_4: Std_logic;
-    signal CmdEnable17_0_a2_3: Std_logic;
-    signal MAin_c_0: Std_logic;
-    signal N_147: Std_logic;
-    signal ADSubmitted: Std_logic;
-    signal CmdEnable17: Std_logic;
-    signal CmdEnable16: Std_logic;
-    signal C1WR_0_a2: Std_logic;
-    signal ADSubmitted_r: Std_logic;
-    signal PHI2_c: Std_logic;
-    signal CmdEnable16_0_a2_5: Std_logic;
-    signal CmdEnable16_0_a2_4: Std_logic;
-    signal MAin_c_1: Std_logic;
-    signal C1Submitted: Std_logic;
-    signal C1Submitted_RNO: Std_logic;
-    signal RASr2: Std_logic;
-    signal S_1: Std_logic;
-    signal CO0: Std_logic;
-    signal IS_3: Std_logic;
-    signal N_177_i: Std_logic;
-    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
-    signal CmdEnable: Std_logic;
-    signal un1_CMDWR: Std_logic;
-    signal CmdEnable_s: Std_logic;
-    signal N_128: Std_logic;
-    signal Din_c_5: Std_logic;
-    signal Din_c_3: Std_logic;
-    signal N_133: Std_logic;
-    signal N_152: Std_logic;
-    signal N_132: Std_logic;
-    signal LEDEN: Std_logic;
-    signal N_21_i: Std_logic;
-    signal XOR8MEG18: Std_logic;
-    signal CmdLEDEN: Std_logic;
-    signal CmdSubmitted: Std_logic;
-    signal InitReady: Std_logic;
-    signal PHI2r3: Std_logic;
-    signal PHI2r2: Std_logic;
-    signal CmdSubmitted_1_sqmuxa: Std_logic;
-    signal N_460_0: Std_logic;
-    signal N_136: Std_logic;
-    signal N_43: Std_logic;
-    signal Cmdn8MEGEN: Std_logic;
-    signal CmdEnable16_4: Std_logic;
-    signal n8MEGEN: Std_logic;
-    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
-    signal N_19_i: Std_logic;
-    signal nRRAS_5_u_i_0: Std_logic;
-    signal IS_0: Std_logic;
-    signal N_160: Std_logic;
-    signal N_155: Std_logic;
-    signal Ready: Std_logic;
-    signal N_64_i_i: Std_logic;
-    signal N_24: Std_logic;
-    signal IS_1: Std_logic;
-    signal IS_2: Std_logic;
-    signal N_60_i_i: Std_logic;
-    signal N_56_i: Std_logic;
-    signal N_159_i: Std_logic;
-    signal N_159: Std_logic;
-    signal N_61_i_i: Std_logic;
-    signal RA10s_i: Std_logic;
-    signal N_126: Std_logic;
-    signal N_51: Std_logic;
-    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
-    signal InitReady3: Std_logic;
-    signal N_461_0: Std_logic;
-    signal UFMSDI_ens2_i_a0: Std_logic;
-    signal nCRAS_c: Std_logic;
-    signal CBR: Std_logic;
-    signal UFMSDO_c: Std_logic;
-    signal N_70: Std_logic;
-    signal N_33: Std_logic;
-    signal LED_c: Std_logic;
-    signal un1_Din_4: Std_logic;
-    signal XOR8MEG: Std_logic;
-    signal Din_c_6: Std_logic;
-    signal RA11_2: Std_logic;
-    signal Ready_fast: Std_logic;
-    signal RA_c_11: Std_logic;
-    signal N_171: Std_logic;
-    signal CASr2: Std_logic;
-    signal FWEr_fast: Std_logic;
-    signal RCKEEN_8_u_0_0: Std_logic;
-    signal RCKEEN_8_u_1: Std_logic;
-    signal RCKEEN_8: Std_logic;
-    signal PHI2r: Std_logic;
-    signal RCKEEN: Std_logic;
-    signal RASr3: Std_logic;
-    signal RASr: Std_logic;
-    signal RCKE_2: Std_logic;
-    signal RCKE_c: Std_logic;
-    signal m18_0_a3_3: Std_logic;
-    signal S_0_i_o2_1: Std_logic;
-    signal N_165: Std_logic;
-    signal N_462_0: Std_logic;
-    signal Ready_0_sqmuxa: Std_logic;
-    signal N_463_0: Std_logic;
-    signal nRRAS_0_sqmuxa: Std_logic;
-    signal CmdUFMCLK: Std_logic;
-    signal N_129: Std_logic;
-    signal UFMCLK_r_i_a2_2_2: Std_logic;
-    signal UFMCLK_c: Std_logic;
-    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
-    signal nUFMCS15: Std_logic;
-    signal N_139_i: Std_logic;
-    signal UFMCLK_RNO: Std_logic;
-    signal UFMSDI_r_xx_mm_1: Std_logic;
-    signal UFMSDI_c: Std_logic;
-    signal UFMSDI_RNO: Std_logic;
-    signal MAin_c_4: Std_logic;
-    signal nRowColSel: Std_logic;
-    signal RowA_4: Std_logic;
-    signal Din_c_4: Std_logic;
-    signal nCCAS_c: Std_logic;
-    signal RA_c_4: Std_logic;
-    signal WRD_4: Std_logic;
-    signal WRD_5: Std_logic;
-    signal Bank_7: Std_logic;
-    signal Bank_6: Std_logic;
-    signal Bank_5: Std_logic;
-    signal Bank_2: Std_logic;
-    signal Din_c_7: Std_logic;
-    signal WRD_6: Std_logic;
-    signal C1WR_0_a2_0_11: Std_logic;
-    signal WRD_7: Std_logic;
-    signal Din_c_0: Std_logic;
-    signal Din_c_2: Std_logic;
-    signal Din_c_1: Std_logic;
-    signal XOR8MEG_3_u_0_a3_2: Std_logic;
-    signal XOR8MEG_3: Std_logic;
-    signal N_69: Std_logic;
-    signal N_31: Std_logic;
-    signal N_151: Std_logic;
-    signal N_41: Std_logic;
-    signal g0_1: Std_logic;
-    signal nRCAS_0_sqmuxa_1: Std_logic;
-    signal N_37_i: Std_logic;
-    signal nRCAS_c: Std_logic;
-    signal CASr3: Std_logic;
-    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
-    signal N_28_i_1: Std_logic;
-    signal N_28_i: Std_logic;
-    signal nRCS_c: Std_logic;
-    signal N_24_i: Std_logic;
-    signal nRRAS_c: Std_logic;
-    signal CBR_fast: Std_logic;
-    signal m18_0_a2_1: Std_logic;
-    signal FWEr: Std_logic;
-    signal G_17_1: Std_logic;
-    signal N_39_i: Std_logic;
-    signal nRWE_c: Std_logic;
-    signal N_179: Std_logic;
-    signal nRowColSel_0_0: Std_logic;
-    signal nUFMCS_c: Std_logic;
-    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
-    signal nUFMCS_s_0_N_5_i: Std_logic;
-    signal CmdUFMCS: Std_logic;
-    signal N_95_5: Std_logic;
-    signal N_95_3: Std_logic;
-    signal RowA_0: Std_logic;
-    signal RowA_1: Std_logic;
-    signal MAin_c_5: Std_logic;
-    signal CmdUFMCLK_1_sqmuxa: Std_logic;
-    signal RowA_5: Std_logic;
-    signal N_137_8: Std_logic;
-    signal un1_FS_14_i_a2_0_1: Std_logic;
-    signal N_137_6: Std_logic;
-    signal un1_FS_13_i_a2_1: Std_logic;
-    signal Bank_0: Std_logic;
-    signal C1WR_0_a2_0_10: Std_logic;
-    signal Bank_1: Std_logic;
-    signal MAin_c_6: Std_logic;
-    signal MAin_c_7: Std_logic;
-    signal C1WR_0_a2_0_3: Std_logic;
-    signal Bank_3: Std_logic;
-    signal Bank_4: Std_logic;
-    signal C1WR_0_a2_0_4: Std_logic;
-    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
-    signal MAin_c_3: Std_logic;
-    signal MAin_c_2: Std_logic;
-    signal RowA_2: Std_logic;
-    signal RowA_3: Std_logic;
-    signal CmdUFMSDI: Std_logic;
-    signal CASr: Std_logic;
-    signal CmdEnable16_1: Std_logic;
-    signal m6_0_a2_2: Std_logic;
-    signal WRD_0: Std_logic;
-    signal WRD_1: Std_logic;
-    signal g4_0_0_0: Std_logic;
-    signal MAin_c_9: Std_logic;
-    signal MAin_c_8: Std_logic;
-    signal RowA_8: Std_logic;
-    signal RowA_9: Std_logic;
-    signal nFWE_c: Std_logic;
-    signal CROW_c_1: Std_logic;
-    signal CROW_c_0: Std_logic;
-    signal RBA_c_0: Std_logic;
-    signal RBA_c_1: Std_logic;
-    signal WRD_2: Std_logic;
-    signal WRD_3: Std_logic;
-    signal RA_c_9: Std_logic;
-    signal RDQML_c: Std_logic;
-    signal RD_1_i: Std_logic;
-    signal RowA_6: Std_logic;
-    signal RowA_7: Std_logic;
-    signal RA_c_8: Std_logic;
-    signal RDQMH_c: Std_logic;
-    signal RA_c_0: Std_logic;
-    signal RA_c_1: Std_logic;
-    signal RA_c_7: Std_logic;
-    signal RA_c_2: Std_logic;
-    signal RA_c_6: Std_logic;
-    signal RA_c_3: Std_logic;
-    signal RA_c_5: Std_logic;
-    signal RA_c_10: Std_logic;
-    signal RD_in_0: Std_logic;
-    signal RD_in_7: Std_logic;
-    signal RD_in_6: Std_logic;
-    signal RD_in_5: Std_logic;
-    signal RD_in_4: Std_logic;
-    signal RD_in_3: Std_logic;
-    signal RD_in_2: Std_logic;
-    signal RD_in_1: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI_TSALL: Std_logic;
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-    component PUR
-      port (PUR: in Std_logic);
-    end component;
-    component GSR
-      port (GSR: in Std_logic);
-    end component;
-    component TSALL
-      port (TSALL: in Std_logic);
-    end component;
-    component SLICE_0
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_1
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_2
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_3
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_4
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_5
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_6
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_7
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_8
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_9
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_14
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_19
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_20
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_21
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_22
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_26
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_29
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_30
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_31
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_32
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_33
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_39
-      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_41
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_42
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_43
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_44
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_50
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_51
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_52
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_55
-      port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_56
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_57
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_58
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_59
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_60
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_61
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_62
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_63
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_64
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component nRWE_RNO_1_SLICE_65
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            OFX0: out Std_logic);
-    end component;
-    component SLICE_66
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_67
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_68
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_69
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_70
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_71
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_72
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_73
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_74
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_75
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_76
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_77
-      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_78
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_79
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_80
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_81
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_82
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_83
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_84
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_85
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_86
-      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_87
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_88
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_89
-      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_90
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_91
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_92
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_93
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_94
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component RD_0_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD0: inout Std_logic);
-    end component;
-    component Dout_0_B
-      port (PADDO: in Std_logic; Dout0: out Std_logic);
-    end component;
-    component PHI2B
-      port (PADDI: out Std_logic; PHI2S: in Std_logic);
-    end component;
-    component UFMSDOB
-      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-    end component;
-    component UFMSDIB
-      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-    end component;
-    component UFMCLKB
-      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-    end component;
-    component nUFMCSB
-      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-    end component;
-    component RDQMLB
-      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-    end component;
-    component RDQMHB
-      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-    end component;
-    component nRCASB
-      port (PADDO: in Std_logic; nRCASS: out Std_logic);
-    end component;
-    component nRRASB
-      port (PADDO: in Std_logic; nRRASS: out Std_logic);
-    end component;
-    component nRWEB
-      port (PADDO: in Std_logic; nRWES: out Std_logic);
-    end component;
-    component RCKEB
-      port (PADDO: in Std_logic; RCKES: out Std_logic);
-    end component;
-    component RCLKB
-      port (PADDI: out Std_logic; RCLKS: in Std_logic);
-    end component;
-    component nRCSB
-      port (PADDO: in Std_logic; nRCSS: out Std_logic);
-    end component;
-    component RD_7_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD7: inout Std_logic);
-    end component;
-    component RD_6_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD6: inout Std_logic);
-    end component;
-    component RD_5_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD5: inout Std_logic);
-    end component;
-    component RD_4_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD4: inout Std_logic);
-    end component;
-    component RD_3_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD3: inout Std_logic);
-    end component;
-    component RD_2_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD2: inout Std_logic);
-    end component;
-    component RD_1_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD1: inout Std_logic);
-    end component;
-    component RA_11_B
-      port (PADDO: in Std_logic; RA11: out Std_logic);
-    end component;
-    component RA_10_B
-      port (PADDO: in Std_logic; RA10: out Std_logic);
-    end component;
-    component RA_9_B
-      port (PADDO: in Std_logic; RA9: out Std_logic);
-    end component;
-    component RA_8_B
-      port (PADDO: in Std_logic; RA8: out Std_logic);
-    end component;
-    component RA_7_B
-      port (PADDO: in Std_logic; RA7: out Std_logic);
-    end component;
-    component RA_6_B
-      port (PADDO: in Std_logic; RA6: out Std_logic);
-    end component;
-    component RA_5_B
-      port (PADDO: in Std_logic; RA5: out Std_logic);
-    end component;
-    component RA_4_B
-      port (PADDO: in Std_logic; RA4: out Std_logic);
-    end component;
-    component RA_3_B
-      port (PADDO: in Std_logic; RA3: out Std_logic);
-    end component;
-    component RA_2_B
-      port (PADDO: in Std_logic; RA2: out Std_logic);
-    end component;
-    component RA_1_B
-      port (PADDO: in Std_logic; RA1: out Std_logic);
-    end component;
-    component RA_0_B
-      port (PADDO: in Std_logic; RA0: out Std_logic);
-    end component;
-    component RBA_1_B
-      port (PADDO: in Std_logic; RBA1: out Std_logic);
-    end component;
-    component RBA_0_B
-      port (PADDO: in Std_logic; RBA0: out Std_logic);
-    end component;
-    component LEDB
-      port (PADDO: in Std_logic; LEDS: out Std_logic);
-    end component;
-    component nFWEB
-      port (PADDI: out Std_logic; nFWES: in Std_logic);
-    end component;
-    component nCRASB
-      port (PADDI: out Std_logic; nCRASS: in Std_logic);
-    end component;
-    component nCCASB
-      port (PADDI: out Std_logic; nCCASS: in Std_logic);
-    end component;
-    component Dout_7_B
-      port (PADDO: in Std_logic; Dout7: out Std_logic);
-    end component;
-    component Dout_6_B
-      port (PADDO: in Std_logic; Dout6: out Std_logic);
-    end component;
-    component Dout_5_B
-      port (PADDO: in Std_logic; Dout5: out Std_logic);
-    end component;
-    component Dout_4_B
-      port (PADDO: in Std_logic; Dout4: out Std_logic);
-    end component;
-    component Dout_3_B
-      port (PADDO: in Std_logic; Dout3: out Std_logic);
-    end component;
-    component Dout_2_B
-      port (PADDO: in Std_logic; Dout2: out Std_logic);
-    end component;
-    component Dout_1_B
-      port (PADDO: in Std_logic; Dout1: out Std_logic);
-    end component;
-    component Din_7_B
-      port (PADDI: out Std_logic; Din7: in Std_logic);
-    end component;
-    component Din_6_B
-      port (PADDI: out Std_logic; Din6: in Std_logic);
-    end component;
-    component Din_5_B
-      port (PADDI: out Std_logic; Din5: in Std_logic);
-    end component;
-    component Din_4_B
-      port (PADDI: out Std_logic; Din4: in Std_logic);
-    end component;
-    component Din_3_B
-      port (PADDI: out Std_logic; Din3: in Std_logic);
-    end component;
-    component Din_2_B
-      port (PADDI: out Std_logic; Din2: in Std_logic);
-    end component;
-    component Din_1_B
-      port (PADDI: out Std_logic; Din1: in Std_logic);
-    end component;
-    component Din_0_B
-      port (PADDI: out Std_logic; Din0: in Std_logic);
-    end component;
-    component CROW_1_B
-      port (PADDI: out Std_logic; CROW1: in Std_logic);
-    end component;
-    component CROW_0_B
-      port (PADDI: out Std_logic; CROW0: in Std_logic);
-    end component;
-    component MAin_9_B
-      port (PADDI: out Std_logic; MAin9: in Std_logic);
-    end component;
-    component MAin_8_B
-      port (PADDI: out Std_logic; MAin8: in Std_logic);
-    end component;
-    component MAin_7_B
-      port (PADDI: out Std_logic; MAin7: in Std_logic);
-    end component;
-    component MAin_6_B
-      port (PADDI: out Std_logic; MAin6: in Std_logic);
-    end component;
-    component MAin_5_B
-      port (PADDI: out Std_logic; MAin5: in Std_logic);
-    end component;
-    component MAin_4_B
-      port (PADDI: out Std_logic; MAin4: in Std_logic);
-    end component;
-    component MAin_3_B
-      port (PADDI: out Std_logic; MAin3: in Std_logic);
-    end component;
-    component MAin_2_B
-      port (PADDI: out Std_logic; MAin2: in Std_logic);
-    end component;
-    component MAin_1_B
-      port (PADDI: out Std_logic; MAin1: in Std_logic);
-    end component;
-    component MAin_0_B
-      port (PADDI: out Std_logic; MAin0: in Std_logic);
-    end component;
-  begin
-    SLICE_0I: SLICE_0
-      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
-                FCO=>FS_cry_1);
-    SLICE_1I: SLICE_1
-      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
-                Q1=>FS_17);
-    SLICE_2I: SLICE_2
-      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
-                Q1=>FS_15, FCO=>FS_cry_15);
-    SLICE_3I: SLICE_3
-      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
-                Q1=>FS_13, FCO=>FS_cry_13);
-    SLICE_4I: SLICE_4
-      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
-                Q1=>FS_11, FCO=>FS_cry_11);
-    SLICE_5I: SLICE_5
-      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
-                Q1=>FS_9, FCO=>FS_cry_9);
-    SLICE_6I: SLICE_6
-      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
-                Q1=>FS_7, FCO=>FS_cry_7);
-    SLICE_7I: SLICE_7
-      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
-                Q1=>FS_5, FCO=>FS_cry_5);
-    SLICE_8I: SLICE_8
-      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
-                Q1=>FS_3, FCO=>FS_cry_3);
-    SLICE_9I: SLICE_9
-      port map (D1=>CmdEnable17_0_a2_4, C1=>CmdEnable17_0_a2_3, B1=>MAin_c_0, 
-                A1=>N_147, D0=>ADSubmitted, C0=>CmdEnable17, B0=>CmdEnable16, 
-                A0=>C1WR_0_a2, DI0=>ADSubmitted_r, CLK=>PHI2_c, 
-                F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
-    SLICE_14I: SLICE_14
-      port map (D1=>CmdEnable16_0_a2_5, C1=>CmdEnable16_0_a2_4, A1=>N_147, 
-                D0=>MAin_c_1, C0=>CmdEnable16, B0=>C1Submitted, A0=>N_147, 
-                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
-                Q0=>C1Submitted, F1=>CmdEnable16);
-    SLICE_19I: SLICE_19
-      port map (D1=>RASr2, C1=>S_1, B1=>CO0, A1=>IS_3, C0=>S_1, A0=>CO0, 
-                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
-                F1=>Ready_0_sqmuxa_0_a3_2);
-    SLICE_20I: SLICE_20
-      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>CmdEnable17, C0=>un1_CMDWR, 
-                B0=>C1Submitted, A0=>CmdEnable, DI0=>CmdEnable_s, 
-                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
-    SLICE_21I: SLICE_21
-      port map (D1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_133, C0=>N_152, 
-                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
-                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
-    SLICE_22I: SLICE_22
-      port map (D1=>CmdSubmitted, C1=>InitReady, B1=>PHI2r3, A1=>PHI2r2, 
-                C0=>CmdSubmitted_1_sqmuxa, A0=>CmdSubmitted, DI0=>N_460_0, 
-                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
-    SLICE_26I: SLICE_26
-      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
-                D0=>n8MEGEN, C0=>Cmdn8MEGEN_4_u_i_0, A0=>N_152, DI0=>N_19_i, 
-                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
-                F1=>Cmdn8MEGEN_4_u_i_0);
-    SLICE_29I: SLICE_29
-      port map (D1=>nRRAS_5_u_i_0, C1=>IS_0, B1=>N_160, A1=>N_155, D0=>IS_0, 
-                B0=>Ready, A0=>N_155, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
-                Q0=>IS_0, F1=>N_24);
-    SLICE_30I: SLICE_30
-      port map (D1=>IS_0, B1=>IS_1, A1=>IS_2, D0=>IS_0, A0=>IS_1, 
-                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
-    SLICE_31I: SLICE_31
-      port map (D1=>IS_2, C1=>N_159, B1=>IS_1, A1=>IS_3, D0=>IS_2, C0=>IS_0, 
-                B0=>IS_1, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
-    SLICE_32I: SLICE_32
-      port map (D1=>N_126, C1=>N_51, B1=>UFMSDI_ens2_i_a2_4_2, A1=>InitReady, 
-                B0=>InitReady3, A0=>InitReady, DI0=>N_461_0, CLK=>RCLK_c, 
-                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
-    SLICE_33I: SLICE_33
-      port map (D1=>nCRAS_c, C1=>LEDEN, A1=>CBR, D0=>UFMSDO_c, C0=>InitReady, 
-                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
-                Q0=>LEDEN, F1=>LED_c);
-    SLICE_39I: SLICE_39
-      port map (D1=>un1_Din_4, A1=>XOR8MEG, D0=>Din_c_6, C0=>n8MEGEN, 
-                A0=>XOR8MEG, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
-                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
-    SLICE_41I: SLICE_41
-      port map (D1=>CASr2, C1=>S_1, B1=>CO0, A1=>FWEr_fast, D0=>CBR, C0=>Ready, 
-                B0=>RCKEEN_8_u_0_0, A0=>RCKEEN_8_u_1, DI0=>RCKEEN_8, M1=>PHI2r, 
-                CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_1, 
-                Q1=>PHI2r2);
-    SLICE_42I: SLICE_42
-      port map (D1=>IS_0, C1=>RASr2, B1=>IS_2, A1=>IS_1, D0=>RCKEEN, C0=>RASr3, 
-                B0=>RASr, A0=>RASr2, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
-                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
-    SLICE_43I: SLICE_43
-      port map (D1=>InitReady, C1=>RASr2, B1=>Ready, A1=>S_0_i_o2_1, 
-                D0=>InitReady, C0=>Ready, B0=>N_165, A0=>Ready_0_sqmuxa_0_a3_2, 
-                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
-                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
-    SLICE_44I: SLICE_44
-      port map (D1=>Ready, C1=>InitReady, B1=>Ready_0_sqmuxa_0_a3_2, A1=>N_165, 
-                C0=>Ready_0_sqmuxa, A0=>Ready_fast, DI0=>N_463_0, M1=>nCRAS_c, 
-                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
-                Q1=>RASr);
-    SLICE_50I: SLICE_50
-      port map (D1=>Ready, C1=>CO0, B1=>S_1, C0=>CO0, A0=>S_1, DI0=>S_0_i_o2_1, 
-                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
-                F1=>nRRAS_0_sqmuxa);
-    SLICE_51I: SLICE_51
-      port map (D1=>CmdUFMCLK, C1=>N_129, B1=>InitReady, A1=>UFMCLK_r_i_a2_2_2, 
-                D0=>UFMCLK_c, C0=>UFMCLK_r_i_m4_xx_mm_1, B0=>nUFMCS15, 
-                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
-                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
-                Q1=>RASr2);
-    SLICE_52I: SLICE_52
-      port map (D1=>PHI2r2, C1=>PHI2r3, B1=>InitReady, A1=>CmdSubmitted, 
-                D0=>UFMSDI_r_xx_mm_1, C0=>N_139_i, B0=>UFMSDI_c, A0=>nUFMCS15, 
-                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
-                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
-    SLICE_55I: SLICE_55
-      port map (D0=>MAin_c_4, B0=>nRowColSel, A0=>RowA_4, M1=>Din_c_5, 
-                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
-    SLICE_56I: SLICE_56
-      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, D0=>FS_5, 
-                C0=>FS_9, B0=>FS_7, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
-                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
-    SLICE_57I: SLICE_57
-      port map (D1=>un1_Din_4, C1=>Din_c_0, B1=>Din_c_2, A1=>Din_c_3, 
-                D0=>Din_c_1, C0=>XOR8MEG_3_u_0_a3_2, B0=>LEDEN, A0=>N_171, 
-                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
-                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
-    SLICE_58I: SLICE_58
-      port map (D1=>N_51, C1=>InitReady, A1=>FS_8, D0=>UFMSDO_c, C0=>InitReady, 
-                B0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
-                Q0=>n8MEGEN, F1=>N_151);
-    SLICE_59I: SLICE_59
-      port map (D1=>N_155, C1=>S_1, B1=>Ready, A1=>N_160, D0=>N_41, C0=>S_1, 
-                B0=>g0_1, A0=>nRCAS_0_sqmuxa_1, DI0=>N_37_i, CLK=>RCLK_c, 
-                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
-    SLICE_60I: SLICE_60
-      port map (D1=>FWEr_fast, C1=>CO0, B1=>CASr2, A1=>CASr3, 
-                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
-                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
-    SLICE_61I: SLICE_61
-      port map (D1=>S_0_i_o2_1, C1=>RCKE_c, B1=>Ready, A1=>RASr2, D0=>IS_0, 
-                C0=>N_155, B0=>nRRAS_5_u_i_0, A0=>N_160, DI0=>N_24_i, 
-                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
-    SLICE_62I: SLICE_62
-      port map (D1=>RASr2, C1=>S_0_i_o2_1, B1=>Ready, A1=>CBR_fast, 
-                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>FWEr, A0=>G_17_1, 
-                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
-                F1=>nRCAS_0_sqmuxa_1);
-    SLICE_63I: SLICE_63
-      port map (D1=>FWEr, C1=>CASr3, B1=>Ready, A1=>CBR, D0=>S_1, C0=>N_179, 
-                B0=>Ready, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
-                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
-    SLICE_64I: SLICE_64
-      port map (D1=>FS_11, C1=>InitReady, B1=>N_51, A1=>FS_10, D0=>N_139_i, 
-                C0=>nUFMCS_c, B0=>nUFMCS15, A0=>nUFMCS_s_0_N_5_i_N_2L1, 
-                DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, F0=>nUFMCS_s_0_N_5_i, 
-                Q0=>nUFMCS_c, F1=>nUFMCS15);
-    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
-      port map (D1=>RASr2, C1=>S_1, B1=>CO0, A1=>RCKE_c, D0=>m18_0_a3_3, 
-                C0=>S_1, B0=>CO0, A0=>InitReady, M0=>Ready, OFX0=>m18_0_a2_1);
-    SLICE_66I: SLICE_66
-      port map (D1=>CmdUFMCS, C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, D0=>N_95_5, 
-                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
-                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
-                Q1=>RowA_1);
-    SLICE_67I: SLICE_67
-      port map (D1=>N_128, C1=>Din_c_3, B1=>Din_c_5, A1=>XOR8MEG18, 
-                D0=>CmdEnable, C0=>MAin_c_0, B0=>MAin_c_1, A0=>N_147, 
-                M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>XOR8MEG18, Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
-    SLICE_68I: SLICE_68
-      port map (D1=>FS_5, C1=>FS_2, B1=>FS_0, A1=>FS_3, D0=>N_137_8, C0=>N_136, 
-                B0=>un1_FS_14_i_a2_0_1, A0=>N_137_6, F0=>N_31, 
-                F1=>un1_FS_14_i_a2_0_1);
-    SLICE_69I: SLICE_69
-      port map (D1=>FS_0, C1=>FS_3, B1=>FS_5, A1=>FS_2, D0=>N_137_8, C0=>N_136, 
-                B0=>N_137_6, A0=>un1_FS_13_i_a2_1, F0=>N_33, 
-                F1=>un1_FS_13_i_a2_1);
-    SLICE_70I: SLICE_70
-      port map (D1=>Bank_0, C1=>C1WR_0_a2_0_10, B1=>C1WR_0_a2_0_11, A1=>Bank_1, 
-                C0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
-                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
-    SLICE_71I: SLICE_71
-      port map (D1=>MAin_c_6, C1=>MAin_c_7, B1=>MAin_c_4, A1=>MAin_c_5, 
-                D0=>C1WR_0_a2_0_3, C0=>Bank_3, B0=>Bank_4, A0=>C1WR_0_a2_0_4, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
-                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
-    SLICE_72I: SLICE_72
-      port map (D1=>UFMSDI_ens2_i_o2_0_3, C1=>FS_16, A1=>FS_12, D0=>FS_4, 
-                C0=>N_51, B0=>FS_11, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
-                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
-                Q1=>RowA_3);
-    SLICE_73I: SLICE_73
-      port map (D1=>InitReady, C1=>S_1, B1=>RASr2, A1=>CO0, C0=>N_155, 
-                A0=>Ready, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
-                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
-    SLICE_74I: SLICE_74
-      port map (B1=>FS_11, A1=>FS_14, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
-                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
-    SLICE_75I: SLICE_75
-      port map (D1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, D0=>Din_c_1, C0=>N_128, 
-                B0=>Din_c_5, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
-                Q0=>CASr, F1=>N_128, Q1=>CASr2);
-    SLICE_76I: SLICE_76
-      port map (D1=>Din_c_0, B1=>Din_c_5, D0=>MAin_c_0, C0=>CmdEnable16_4, 
-                B0=>Din_c_1, A0=>Din_c_3, M1=>Din_c_5, M0=>Din_c_4, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
-                F1=>CmdEnable16_4, Q1=>Bank_5);
-    SLICE_77I: SLICE_77
-      port map (D1=>Din_c_4, A1=>Din_c_7, D0=>Din_c_6, C0=>MAin_c_1, 
-                B0=>CmdEnable16_1, A0=>Din_c_2, M1=>Din_c_7, M0=>Din_c_6, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
-                F1=>CmdEnable16_1, Q1=>Bank_7);
-    SLICE_78I: SLICE_78
-      port map (D1=>Din_c_3, B1=>Din_c_5, D0=>MAin_c_1, C0=>N_43, B0=>Din_c_6, 
-                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
-                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
-    SLICE_79I: SLICE_79
-      port map (D1=>CASr3, B1=>CASr2, A1=>Ready, D0=>CO0, C0=>S_1, 
-                B0=>m6_0_a2_2, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
-                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
-    SLICE_80I: SLICE_80
-      port map (D1=>CASr2, B1=>CASr3, D0=>FWEr, C0=>CO0, B0=>g4_0_0_0, 
-                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
-    SLICE_81I: SLICE_81
-      port map (D1=>FS_13, C1=>FS_14, B1=>FS_15, A1=>FS_17, D0=>FS_13, 
-                C0=>FS_17, B0=>FS_15, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
-                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
-                Q1=>FWEr_fast);
-    SLICE_82I: SLICE_82
-      port map (D1=>Din_c_3, C1=>N_128, B1=>CmdLEDEN, A1=>Din_c_5, 
-                D0=>XOR8MEG18, C0=>Din_c_3, B0=>N_128, A0=>Din_c_5, M0=>CASr2, 
-                CLK=>RCLK_c, F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
-    SLICE_83I: SLICE_83
-      port map (C1=>IS_1, B1=>IS_3, A1=>IS_2, C0=>IS_1, B0=>IS_0, A0=>IS_2, 
-                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
-    SLICE_84I: SLICE_84
-      port map (D1=>FS_6, C1=>FS_10, B1=>FS_11, A1=>FS_8, D0=>FS_7, C0=>FS_10, 
-                B0=>FS_1, A0=>FS_6, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
-    SLICE_85I: SLICE_85
-      port map (D1=>Din_c_4, C1=>Din_c_0, B1=>Din_c_1, A1=>Din_c_7, 
-                D0=>Din_c_5, C0=>Din_c_4, B0=>Din_c_6, A0=>Din_c_7, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
-                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
-    SLICE_86I: SLICE_86
-      port map (D1=>nRowColSel, A1=>MAin_c_9, D0=>nRowColSel, C0=>RowA_9, 
-                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
-    SLICE_87I: SLICE_87
-      port map (D1=>UFMSDI_ens2_i_a0, B1=>N_151, A1=>CmdUFMSDI, D0=>N_151, 
-                C0=>FS_9, B0=>FS_11, A0=>FS_4, F0=>N_137_8, 
-                F1=>UFMSDI_r_xx_mm_1);
-    SLICE_88I: SLICE_88
-      port map (D1=>MAin_c_2, C1=>nFWE_c, B1=>MAin_c_3, C0=>nFWE_c, 
-                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
-                Q1=>RowA_7);
-    SLICE_89I: SLICE_89
-      port map (D1=>nRowColSel, C1=>MAin_c_9, D0=>nRowColSel, B0=>MAin_c_8, 
-                A0=>RowA_8, F0=>RA_c_8, F1=>RDQMH_c);
-    SLICE_90I: SLICE_90
-      port map (D1=>MAin_c_0, C1=>MAin_c_1, B1=>N_147, D0=>MAin_c_0, 
-                B0=>RowA_0, A0=>nRowColSel, F0=>RA_c_0, F1=>un1_CMDWR);
-    SLICE_91I: SLICE_91
-      port map (D1=>MAin_c_7, C1=>nRowColSel, A1=>RowA_7, D0=>RowA_1, 
-                C0=>nRowColSel, B0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
-    SLICE_92I: SLICE_92
-      port map (D1=>RowA_6, C1=>nRowColSel, A1=>MAin_c_6, D0=>MAin_c_2, 
-                C0=>nRowColSel, B0=>RowA_2, F0=>RA_c_2, F1=>RA_c_6);
-    SLICE_93I: SLICE_93
-      port map (C1=>MAin_c_5, B1=>RowA_5, A1=>nRowColSel, D0=>MAin_c_3, 
-                B0=>nRowColSel, A0=>RowA_3, F0=>RA_c_3, F1=>RA_c_5);
-    SLICE_94I: SLICE_94
-      port map (B1=>N_155, A1=>Ready, C0=>S_1, A0=>Ready, M0=>IS_0, 
-                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
-                Q0=>RA_c_10, F1=>N_159_i);
-    RD_0_I: RD_0_B
-      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
-    Dout_0_I: Dout_0_B
-      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
-    PHI2I: PHI2B
-      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
-    UFMSDOI: UFMSDOB
-      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
-    UFMSDII: UFMSDIB
-      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
-    UFMCLKI: UFMCLKB
-      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
-    nUFMCSI: nUFMCSB
-      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
-    RDQMLI: RDQMLB
-      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
-    RDQMHI: RDQMHB
-      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
-    nRCASI: nRCASB
-      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
-    nRRASI: nRRASB
-      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
-    nRWEI: nRWEB
-      port map (PADDO=>nRWE_c, nRWES=>nRWE);
-    RCKEI: RCKEB
-      port map (PADDO=>RCKE_c, RCKES=>RCKE);
-    RCLKI: RCLKB
-      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
-    nRCSI: nRCSB
-      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
-    RD_7_I: RD_7_B
-      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
-    RD_6_I: RD_6_B
-      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
-    RD_5_I: RD_5_B
-      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
-    RD_4_I: RD_4_B
-      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
-    RD_3_I: RD_3_B
-      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
-    RD_2_I: RD_2_B
-      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
-    RD_1_I0: RD_1_B
-      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
-    RA_11_I: RA_11_B
-      port map (PADDO=>RA_c_11, RA11=>RA(11));
-    RA_10_I: RA_10_B
-      port map (PADDO=>RA_c_10, RA10=>RA(10));
-    RA_9_I: RA_9_B
-      port map (PADDO=>RA_c_9, RA9=>RA(9));
-    RA_8_I: RA_8_B
-      port map (PADDO=>RA_c_8, RA8=>RA(8));
-    RA_7_I: RA_7_B
-      port map (PADDO=>RA_c_7, RA7=>RA(7));
-    RA_6_I: RA_6_B
-      port map (PADDO=>RA_c_6, RA6=>RA(6));
-    RA_5_I: RA_5_B
-      port map (PADDO=>RA_c_5, RA5=>RA(5));
-    RA_4_I: RA_4_B
-      port map (PADDO=>RA_c_4, RA4=>RA(4));
-    RA_3_I: RA_3_B
-      port map (PADDO=>RA_c_3, RA3=>RA(3));
-    RA_2_I: RA_2_B
-      port map (PADDO=>RA_c_2, RA2=>RA(2));
-    RA_1_I: RA_1_B
-      port map (PADDO=>RA_c_1, RA1=>RA(1));
-    RA_0_I: RA_0_B
-      port map (PADDO=>RA_c_0, RA0=>RA(0));
-    RBA_1_I: RBA_1_B
-      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
-    RBA_0_I: RBA_0_B
-      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
-    LEDI: LEDB
-      port map (PADDO=>LED_c, LEDS=>LED);
-    nFWEI: nFWEB
-      port map (PADDI=>nFWE_c, nFWES=>nFWE);
-    nCRASI: nCRASB
-      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
-    nCCASI: nCCASB
-      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
-    Dout_7_I: Dout_7_B
-      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
-    Dout_6_I: Dout_6_B
-      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
-    Dout_5_I: Dout_5_B
-      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
-    Dout_4_I: Dout_4_B
-      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
-    Dout_3_I: Dout_3_B
-      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
-    Dout_2_I: Dout_2_B
-      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
-    Dout_1_I: Dout_1_B
-      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
-    Din_7_I: Din_7_B
-      port map (PADDI=>Din_c_7, Din7=>Din(7));
-    Din_6_I: Din_6_B
-      port map (PADDI=>Din_c_6, Din6=>Din(6));
-    Din_5_I: Din_5_B
-      port map (PADDI=>Din_c_5, Din5=>Din(5));
-    Din_4_I: Din_4_B
-      port map (PADDI=>Din_c_4, Din4=>Din(4));
-    Din_3_I: Din_3_B
-      port map (PADDI=>Din_c_3, Din3=>Din(3));
-    Din_2_I: Din_2_B
-      port map (PADDI=>Din_c_2, Din2=>Din(2));
-    Din_1_I: Din_1_B
-      port map (PADDI=>Din_c_1, Din1=>Din(1));
-    Din_0_I: Din_0_B
-      port map (PADDI=>Din_c_0, Din0=>Din(0));
-    CROW_1_I: CROW_1_B
-      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
-    CROW_0_I: CROW_0_B
-      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
-    MAin_9_I: MAin_9_B
-      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
-    MAin_8_I: MAin_8_B
-      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
-    MAin_7_I: MAin_7_B
-      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
-    MAin_6_I: MAin_6_B
-      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
-    MAin_5_I: MAin_5_B
-      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
-    MAin_4_I: MAin_4_B
-      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
-    MAin_3_I: MAin_3_B
-      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
-    MAin_2_I: MAin_2_B
-      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
-    MAin_1_I: MAin_1_B
-      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
-    MAin_0_I: MAin_0_B
-      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
-    VHI_INST: VHI
-      port map (Z=>VCCI);
-    PUR_INST: PUR
-      port map (PUR=>VCCI);
-    GSR_INST: GSR
-      port map (GSR=>VCCI);
-    VLO_INST: VLO
-      port map (Z=>GNDI_TSALL);
-    TSALL_INST: TSALL
-      port map (TSALL=>GNDI_TSALL);
-  end Structure;
-
-
-
-  library IEEE, vital2000, MACHXO;
-  configuration Structure_CON of RAM2GS is
-    for Structure
-    end for;
-  end Structure_CON;
-
-
+
+-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+-- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_vho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd 
+-- Netlist created on Sat Aug 19 20:53:19 2023
+-- Netlist written on Sat Aug 19 20:53:34 2023
+-- Design is for device LCMXO256C
+-- Design is for package TQFP100
+-- Design is for performance grade 3
+
+-- entity vmuxregsre
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
+
+  end vmuxregsre;
+
+  architecture Structure of vmuxregsre is
+    component FL1P3DX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity vcc
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vcc is
+    port (PWR1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
+
+  end vcc;
+
+  architecture Structure of vcc is
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VHI
+      port map (Z=>PWR1);
+  end Structure;
+
+-- entity gnd
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity gnd is
+    port (PWR0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
+
+  end gnd;
+
+  architecture Structure of gnd is
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VLO
+      port map (Z=>PWR0);
+  end Structure;
+
+-- entity ccu2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu2B is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
+
+  end ccu2B;
+
+  architecture Structure of ccu2B is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_0
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_0";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
+
+  end SLICE_0;
+
+  architecture Structure of SLICE_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_0: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
+                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20001
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu20001 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
+
+  end ccu20001;
+
+  architecture Structure of ccu20001 is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_1
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_1";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
+
+  end SLICE_1;
+
+  architecture Structure of SLICE_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu20001
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_17: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_16: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_16: ccu20001
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
+                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_2 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_2";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
+
+  end SLICE_2;
+
+  architecture Structure of SLICE_2 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_15: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_14: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_14: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
+                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_3
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_3 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_3";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
+
+  end SLICE_3;
+
+  architecture Structure of SLICE_3 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_13: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_12: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_12: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
+                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_4 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_4";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
+
+  end SLICE_4;
+
+  architecture Structure of SLICE_4 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_11: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_10: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_10: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
+                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_5
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_5 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_5";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
+
+  end SLICE_5;
+
+  architecture Structure of SLICE_5 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_9: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_8: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_8: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
+                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_6
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_6 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_6";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
+
+  end SLICE_6;
+
+  architecture Structure of SLICE_6 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_7: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_6: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_6: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
+                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_7
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_7 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_7";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
+
+  end SLICE_7;
+
+  architecture Structure of SLICE_7 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_5: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_4: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_4: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
+                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_8
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_8 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_8";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
+
+  end SLICE_8;
+
+  architecture Structure of SLICE_8 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_2: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
+                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut4 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
+
+  end lut4;
+
+  architecture Structure of lut4 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40002
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40002 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
+
+  end lut40002;
+
+  architecture Structure of lut40002 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3130")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity inverter
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity inverter is
+    port (I: in Std_logic; Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
+
+  end inverter;
+
+  architecture Structure of inverter is
+    component INV
+      port (A: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    INST1: INV
+      port map (A=>I, Z=>Z);
+  end Structure;
+
+-- entity SLICE_9
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_9 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_9";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
+
+  end SLICE_9;
+
+  architecture Structure of SLICE_9 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40002
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    ADSubmitted_r: lut40002
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    ADSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40003
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40003 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
+
+  end lut40003;
+
+  architecture Structure of lut40003 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40004
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40004 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
+
+  end lut40004;
+
+  architecture Structure of lut40004 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF4FC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_14
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_14 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_14";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
+
+  end SLICE_14;
+
+  architecture Structure of SLICE_14 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40003
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40004
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2: lut40003
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    C1Submitted_RNO: lut40004
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    C1Submitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40005
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40005 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
+
+  end lut40005;
+
+  architecture Structure of lut40005 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0080")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40006
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40006 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
+
+  end lut40006;
+
+  architecture Structure of lut40006 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF5F5")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0007
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0007 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
+
+  end vmuxregsre0007;
+
+  architecture Structure of vmuxregsre0007 is
+    component FL1P3IY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3IY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_19
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_19 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_19";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
+
+  end SLICE_19;
+
+  architecture Structure of SLICE_19 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40006
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    S_RNO_0: lut40006
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40008
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40008 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
+
+  end lut40008;
+
+  architecture Structure of lut40008 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40009
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40009 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
+
+  end lut40009;
+
+  architecture Structure of lut40009 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEA0A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity selmux2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity selmux2 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
+
+  end selmux2;
+
+  architecture Structure of selmux2 is
+    component MUX21
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    INST1: MUX21
+      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
+  end Structure;
+
+-- entity SLICE_20
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_20 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_20";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
+
+  end SLICE_20;
+
+  architecture Structure of SLICE_20 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
+    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40008
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40009
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    SLICE_20_K1: lut40008
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
+                Z=>SLICE_20_SLICE_20_K1_H1);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable_s_GATE: lut40009
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>SLICE_20_CmdEnable_s_GATE_H0);
+    CmdEnable: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    SLICE_20_K0K1MUX: selmux2
+      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
+                SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40010
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40010 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
+
+  end lut40010;
+
+  architecture Structure of lut40010 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0044")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40011
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40011 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
+
+  end lut40011;
+
+  architecture Structure of lut40011 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0023")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_21
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_21 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_21";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
+
+  end SLICE_21;
+
+  architecture Structure of SLICE_21 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40010
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40011
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_a2_2: lut40010
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_RNO: lut40011
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdLEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40012
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40012 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
+
+  end lut40012;
+
+  architecture Structure of lut40012 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40013
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40013 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
+
+  end lut40013;
+
+  architecture Structure of lut40013 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFAFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_22
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_22 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_22";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
+
+  end SLICE_22;
+
+  architecture Structure of SLICE_22 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2: lut40012
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_RNO: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40014
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40014 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
+
+  end lut40014;
+
+  architecture Structure of lut40014 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33AB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40015
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40015 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
+
+  end lut40015;
+
+  architecture Structure of lut40015 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0F05")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_26
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_26 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_26";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
+
+  end SLICE_26;
+
+  architecture Structure of SLICE_26 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40014
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40015
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_0: lut40014
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Cmdn8MEGEN_RNO: lut40015
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Cmdn8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40016
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40016 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
+
+  end lut40016;
+
+  architecture Structure of lut40016 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF54")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40017
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40017 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
+
+  end lut40017;
+
+  architecture Structure of lut40017 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEE11")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_29
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_29 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_29";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
+
+  end SLICE_29;
+
+  architecture Structure of SLICE_29 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40016
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40017
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i: lut40016
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_0: lut40017
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40018
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40018 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
+
+  end lut40018;
+
+  architecture Structure of lut40018 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x66AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40019
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40019 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
+
+  end lut40019;
+
+  architecture Structure of lut40019 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x55AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_30
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_30 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_30";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
+
+  end SLICE_30;
+
+  architecture Structure of SLICE_30 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40018
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40019
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_RNO_2: lut40018
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_n1_0_x2: lut40019
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    IS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    IS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40020
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40020 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
+
+  end lut40020;
+
+  architecture Structure of lut40020 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40021
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40021 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
+
+  end lut40021;
+
+  architecture Structure of lut40021 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x6AAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_31
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_31 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_31";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
+
+  end SLICE_31;
+
+  architecture Structure of SLICE_31 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40020
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40021
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RA10_RNO: lut40020
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_3: lut40021
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    IS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40022
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40022 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
+
+  end lut40022;
+
+  architecture Structure of lut40022 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5155")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40023
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40023 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
+
+  end lut40023;
+
+  architecture Structure of lut40023 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_32
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_32 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_32";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
+
+  end SLICE_32;
+
+  architecture Structure of SLICE_32 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40022
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a0: lut40022
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady_RNO: lut40023
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40024
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40024 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
+
+  end lut40024;
+
+  architecture Structure of lut40024 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFAF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40025
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40025 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
+
+  end lut40025;
+
+  architecture Structure of lut40025 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA0AF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_33
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_33 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_33";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
+
+  end SLICE_33;
+
+  architecture Structure of SLICE_33 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40025
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    LED_pad_RNO: lut40024
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    LEDEN_5_i_m2: lut40025
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    LEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40026
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40026 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
+
+  end lut40026;
+
+  architecture Structure of lut40026 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40027
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40027 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
+
+  end lut40027;
+
+  architecture Structure of lut40027 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA5AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_39
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_39 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_39";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
+
+  end SLICE_39;
+
+  architecture Structure of SLICE_39 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40026
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40027
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_0: lut40026
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RA11_2: lut40027
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RA11: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40028
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40028 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
+
+  end lut40028;
+
+  architecture Structure of lut40028 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2DAD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40029
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40029 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
+
+  end lut40029;
+
+  architecture Structure of lut40029 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCCEC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_41
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_41 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_41";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
+
+  end SLICE_41;
+
+  architecture Structure of SLICE_41 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40029
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_1_0: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKEEN_8_u: lut40029
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40030
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40030 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
+
+  end lut40030;
+
+  architecture Structure of lut40030 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40031
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40031 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
+
+  end lut40031;
+
+  architecture Structure of lut40031 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFE50")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_42
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_42 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_42";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
+
+  end SLICE_42;
+
+  architecture Structure of SLICE_42 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40030
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40031
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_5: lut40030
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKE_2_0: lut40031
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKE: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40032
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40032 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
+
+  end lut40032;
+
+  architecture Structure of lut40032 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3704")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40033
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40033 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
+
+  end lut40033;
+
+  architecture Structure of lut40033 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF2F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_43
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_43 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_43";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
+
+  end SLICE_43;
+
+  architecture Structure of SLICE_43 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40032
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_RNO: lut40032
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_RNO: lut40033
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40034
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40034 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
+
+  end lut40034;
+
+  architecture Structure of lut40034 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0040")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_44
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_44 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_44";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
+
+  end SLICE_44;
+
+  architecture Structure of SLICE_44 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3: lut40034
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_fast_RNO: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RASr: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Ready_fast: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40035
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40035 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
+
+  end lut40035;
+
+  architecture Structure of lut40035 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_50
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_50 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_50";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
+
+  end SLICE_50;
+
+  architecture Structure of SLICE_50 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_RNO: lut40035
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0_i_o2_1: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    S_1: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, C0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40036
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40036 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
+
+  end lut40036;
+
+  architecture Structure of lut40036 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xABEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40037
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40037 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
+
+  end lut40037;
+
+  architecture Structure of lut40037 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1302")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_51
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_51 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_51";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
+
+  end SLICE_51;
+
+  architecture Structure of SLICE_51 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMCLK_RNO_0: lut40036
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMCLK_RNO: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40038
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40038 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
+
+  end lut40038;
+
+  architecture Structure of lut40038 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33B3")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40039
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40039 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
+
+  end lut40039;
+
+  architecture Structure of lut40039 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_52
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_52 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_52";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
+
+  end SLICE_52;
+
+  architecture Structure of SLICE_52 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40039
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    PHI2r3_RNITCN41: lut40038
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_RNO: lut40039
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMSDI: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40040
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40040 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
+
+  end lut40040;
+
+  architecture Structure of lut40040 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEE22")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_55
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_55 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_55";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
+
+  end SLICE_55;
+
+  architecture Structure of SLICE_55 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_4: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40041
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40041 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
+
+  end lut40041;
+
+  architecture Structure of lut40041 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40042
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40042 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
+
+  end lut40042;
+
+  architecture Structure of lut40042 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3C0C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_56
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_56 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_56";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
+
+  end SLICE_56;
+
+  architecture Structure of SLICE_56 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40042
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_11: lut40041
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_ens2_i_o2: lut40042
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40043
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40043 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
+
+  end lut40043;
+
+  architecture Structure of lut40043 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40044
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40044 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
+
+  end lut40044;
+
+  architecture Structure of lut40044 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBAFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_57
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_57 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_57";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
+
+  end SLICE_57;
+
+  architecture Structure of SLICE_57 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_2: lut40043
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG_3_u_0_a3_3: lut40044
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    XOR8MEG: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40045
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40045 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
+
+  end lut40045;
+
+  architecture Structure of lut40045 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0005")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40046
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40046 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
+
+  end lut40046;
+
+  architecture Structure of lut40046 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xC0CF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_58
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_58 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_58";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
+
+  end SLICE_58;
+
+  architecture Structure of SLICE_58 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_en_ss0_0_a2_0: lut40045
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    n8MEGEN_5_i_m2: lut40046
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    n8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40047
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40047 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
+
+  end lut40047;
+
+  architecture Structure of lut40047 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3F1D")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40048
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40048 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
+
+  end lut40048;
+
+  architecture Structure of lut40048 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5510")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0049
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0049 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0049 : ENTITY IS TRUE;
+
+  end vmuxregsre0049;
+
+  architecture Structure of vmuxregsre0049 is
+    component FL1P3BX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3BX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_59
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_59 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_59";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
+
+  end SLICE_59;
+
+  architecture Structure of SLICE_59 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40047
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0049
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_0: lut40047
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCAS_RNO: lut40048
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCAS: vmuxregsre0049
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40050
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40050 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
+
+  end lut40050;
+
+  architecture Structure of lut40050 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBFF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40051
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40051 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
+
+  end lut40051;
+
+  architecture Structure of lut40051 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3233")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_60
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_60 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_60";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
+
+  end SLICE_60;
+
+  architecture Structure of SLICE_60 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0049
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40050
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40051
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCS_RNO_0: lut40050
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCS_RNO: lut40051
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCS: vmuxregsre0049
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40052
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40052 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
+
+  end lut40052;
+
+  architecture Structure of lut40052 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00C8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40053
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40053 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
+
+  end lut40053;
+
+  architecture Structure of lut40053 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3031")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_61
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_61 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_61";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
+
+  end SLICE_61;
+
+  architecture Structure of SLICE_61 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0049
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40052
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i_0: lut40052
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRRAS_RNO: lut40053
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRRAS: vmuxregsre0049
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40054
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40054 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
+
+  end lut40054;
+
+  architecture Structure of lut40054 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40055
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40055 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
+
+  end lut40055;
+
+  architecture Structure of lut40055 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF2F7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_62
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_62 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_62";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
+
+  end SLICE_62;
+
+  architecture Structure of SLICE_62 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0049
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40054
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40055
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_0_sqmuxa_1_0_a3: lut40054
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRWE_RNO: lut40055
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRWE: vmuxregsre0049
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40056
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40056 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
+
+  end lut40056;
+
+  architecture Structure of lut40056 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0400")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40057
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40057 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
+
+  end lut40057;
+
+  architecture Structure of lut40057 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF4F8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_63
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_63 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_63";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
+
+  end SLICE_63;
+
+  architecture Structure of SLICE_63 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40056
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_0_0_a3_0: lut40056
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRowColSel_0_0: lut40057
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRowColSel: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40058
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40058 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
+
+  end lut40058;
+
+  architecture Structure of lut40058 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40059
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40059 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
+
+  end lut40059;
+
+  architecture Structure of lut40059 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDDFC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_64
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_64 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_64";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
+
+  end SLICE_64;
+
+  architecture Structure of SLICE_64 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0049
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS15_0_a2: lut40058
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nUFMCS_s_0_N_5_i: lut40059
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nUFMCS: vmuxregsre0049
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40060
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40060 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
+
+  end lut40060;
+
+  architecture Structure of lut40060 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0002")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40061
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40061 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
+
+  end lut40061;
+
+  architecture Structure of lut40061 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity nRWE_RNO_1_SLICE_65
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWE_RNO_1_SLICE_65 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
+
+  end nRWE_RNO_1_SLICE_65;
+
+  architecture Structure of nRWE_RNO_1_SLICE_65 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_1_SLICE_65_K1: lut40060
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
+    nRWE_RNO_1_GATE: lut40061
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
+    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
+      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
+                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
+                Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40062
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40062 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
+
+  end lut40062;
+
+  architecture Structure of lut40062 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0F03")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40063
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40063 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
+
+  end lut40063;
+
+  architecture Structure of lut40063 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_66
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_66 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_66";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
+
+  end SLICE_66;
+
+  architecture Structure of SLICE_66 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS_s_0_N_5_i_N_2L1: lut40062
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_a2_2_2: lut40063
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40064
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40064 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
+
+  end lut40064;
+
+  architecture Structure of lut40064 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0008")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40065
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40065 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
+
+  end lut40065;
+
+  architecture Structure of lut40065 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0066
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0066 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0066 : ENTITY IS TRUE;
+
+  end vmuxregsre0066;
+
+  architecture Structure of vmuxregsre0066 is
+    component FL1P3JY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3JY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_67
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_67 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_67";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
+
+  end SLICE_67;
+
+  architecture Structure of SLICE_67 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0066
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    CmdUFMCLK_1_sqmuxa_0_a2: lut40064
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG18_0_a2: lut40065
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_5: vmuxregsre0066
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_4: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40067
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40067 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
+
+  end lut40067;
+
+  architecture Structure of lut40067 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40068
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40068 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
+
+  end lut40068;
+
+  architecture Structure of lut40068 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF8F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_68
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_68 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_68";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
+
+  end SLICE_68;
+
+  architecture Structure of SLICE_68 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40067
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40068
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2_0_1: lut40067
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_14_i_0: lut40068
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40069
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40069 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
+
+  end lut40069;
+
+  architecture Structure of lut40069 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0004")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40070
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40070 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
+
+  end lut40070;
+
+  architecture Structure of lut40070 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF8F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_69
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_69 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_69";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
+
+  end SLICE_69;
+
+  architecture Structure of SLICE_69 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40070
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_13_i_a2_1: lut40069
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_0: lut40070
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40071
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40071 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
+
+  end lut40071;
+
+  architecture Structure of lut40071 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40072
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40072 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
+
+  end lut40072;
+
+  architecture Structure of lut40072 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA0A0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_70
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_70 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_70";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
+
+  end SLICE_70;
+
+  architecture Structure of SLICE_70 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40071
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0: lut40071
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2: lut40072
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40073
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40073 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
+
+  end lut40073;
+
+  architecture Structure of lut40073 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40074
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40074 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
+
+  end lut40074;
+
+  architecture Structure of lut40074 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_71
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_71 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_71";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
+
+  end SLICE_71;
+
+  architecture Structure of SLICE_71 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40073
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_4: lut40073
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2_0_10: lut40074
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40075
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40075 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
+
+  end lut40075;
+
+  architecture Structure of lut40075 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40076
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40076 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
+
+  end lut40076;
+
+  architecture Structure of lut40076 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xACA0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_72
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_72 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_72";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
+
+  end SLICE_72;
+
+  architecture Structure of SLICE_72 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40075
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40076
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0: lut40075
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_m2: lut40076
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_3: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_2: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40077
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40077 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
+
+  end lut40077;
+
+  architecture Structure of lut40077 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFBFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_73
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_73 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_73";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
+
+  end SLICE_73;
+
+  architecture Structure of SLICE_73 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40077
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0: lut40077
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_0_sqmuxa_0_o2: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdUFMCS: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CmdUFMCLK: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40078
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40078 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
+
+  end lut40078;
+
+  architecture Structure of lut40078 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8888")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40079
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40079 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
+
+  end lut40079;
+
+  architecture Structure of lut40079 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_74
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_74 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_74";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
+
+  end SLICE_74;
+
+  architecture Structure of SLICE_74 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40078
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40079
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    InitReady3_0_a2_3: lut40078
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady3_0_a2: lut40079
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdUFMSDI: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40080
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40080 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
+
+  end lut40080;
+
+  architecture Structure of lut40080 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFDD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40081
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40081 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
+
+  end lut40081;
+
+  architecture Structure of lut40081 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0003")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_75
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_75 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_75";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
+
+  end SLICE_75;
+
+  architecture Structure of SLICE_75 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40080
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_o2_0: lut40080
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_4_u_i_a2_0: lut40081
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CASr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40082
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40082 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
+
+  end lut40082;
+
+  architecture Structure of lut40082 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40083
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40083 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
+
+  end lut40083;
+
+  architecture Structure of lut40083 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_76
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_76 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_76";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
+
+  end SLICE_76;
+
+  architecture Structure of SLICE_76 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40082
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40083
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_4: lut40082
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_4_0: lut40083
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40084
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40084 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
+
+  end lut40084;
+
+  architecture Structure of lut40084 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40085
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40085 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
+
+  end lut40085;
+
+  architecture Structure of lut40085 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_77
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_77 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_77";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
+
+  end SLICE_77;
+
+  architecture Structure of SLICE_77 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40084
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40085
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_1: lut40084
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_5: lut40085
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40086
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40086 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
+
+  end lut40086;
+
+  architecture Structure of lut40086 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40087
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40087 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
+
+  end lut40087;
+
+  architecture Structure of lut40087 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_78
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_78 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_78";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
+
+  end SLICE_78;
+
+  architecture Structure of SLICE_78 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40086
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40087
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_o2: lut40086
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable17_0_a2_4: lut40087
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CBR_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CBR: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40088
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40088 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
+
+  end lut40088;
+
+  architecture Structure of lut40088 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0088")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40089
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40089 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
+
+  end lut40089;
+
+  architecture Structure of lut40089 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_79
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_79 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_79";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
+
+  end SLICE_79;
+
+  architecture Structure of SLICE_79 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40088
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40089
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_2: lut40088
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRWE_RNO_0: lut40089
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40090
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40090 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
+
+  end lut40090;
+
+  architecture Structure of lut40090 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4005")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_80
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_80 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_80";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
+
+  end SLICE_80;
+
+  architecture Structure of SLICE_80 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vmuxregsre0066
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40082
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40090
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_RNO_1: lut40082
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRCAS_RNO_0: lut40090
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_9: vmuxregsre0066
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_8: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40091
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40091 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
+
+  end lut40091;
+
+  architecture Structure of lut40091 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40092
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40092 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
+
+  end lut40092;
+
+  architecture Structure of lut40092 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_81
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_81 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_81";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
+
+  end SLICE_81;
+
+  architecture Structure of SLICE_81 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40091
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40092
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0_3: lut40091
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady3_0_a2_5: lut40092
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    FWEr_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    FWEr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40093
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40093 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
+
+  end lut40093;
+
+  architecture Structure of lut40093 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3230")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40094
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40094 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
+
+  end lut40094;
+
+  architecture Structure of lut40094 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_82
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_82 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_82";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
+
+  end SLICE_82;
+
+  architecture Structure of SLICE_82 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40094
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdLEDEN_4_u_i_a2: lut40093
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_1_sqmuxa_0_a2: lut40094
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr3: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40095
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40095 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
+
+  end lut40095;
+
+  architecture Structure of lut40095 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFEFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40096
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40096 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
+
+  end lut40096;
+
+  architecture Structure of lut40096 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7F7F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_83
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_83 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_83";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
+
+  end SLICE_83;
+
+  architecture Structure of SLICE_83 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40095
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40096
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_o2: lut40095
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready_0_sqmuxa_0_o2: lut40096
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RBA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RBA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40097
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40097 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
+
+  end lut40097;
+
+  architecture Structure of lut40097 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0400")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40098
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40098 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
+
+  end lut40098;
+
+  architecture Structure of lut40098 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_84
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_84 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_84";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
+
+  end SLICE_84;
+
+  architecture Structure of SLICE_84 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40097
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40098
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a2_4_2: lut40097
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_a2_6: lut40098
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40099
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40099 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
+
+  end lut40099;
+
+  architecture Structure of lut40099 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40100
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40100 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
+
+  end lut40100;
+
+  architecture Structure of lut40100 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_85
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_85 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_85";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
+
+  end SLICE_85;
+
+  architecture Structure of SLICE_85 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40099
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40100
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2_3: lut40099
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_Din_4: lut40100
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40101
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40101 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
+
+  end lut40101;
+
+  architecture Structure of lut40101 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x55FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40102
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40102 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
+
+  end lut40102;
+
+  architecture Structure of lut40102 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAAF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_86
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_86 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_86";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
+
+  end SLICE_86;
+
+  architecture Structure of SLICE_86 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40101
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40102
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQML: lut40101
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_9: lut40102
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40103
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40103 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
+
+  end lut40103;
+
+  architecture Structure of lut40103 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00EE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40104
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40104 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
+
+  end lut40104;
+
+  architecture Structure of lut40104 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_87
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_87 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_87";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
+
+  end SLICE_87;
+
+  architecture Structure of SLICE_87 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40103
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40104
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_RNO_0: lut40103
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un1_FS_13_i_a2_8: lut40104
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40105
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40105 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE;
+
+  end lut40105;
+
+  architecture Structure of lut40105 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0C00")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40106
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40106 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
+
+  end lut40106;
+
+  architecture Structure of lut40106 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFAFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_88
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_88 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_88";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
+
+  end SLICE_88;
+
+  architecture Structure of SLICE_88 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40105
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_3: lut40105
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nCCAS_pad_RNI01SJ: lut40106
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RowA_7: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_6: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, C0_ipd, A0_ipd, M1_dly, 
+      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40107
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40107 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
+
+  end lut40107;
+
+  architecture Structure of lut40107 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF0FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40108
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40108 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
+
+  end lut40108;
+
+  architecture Structure of lut40108 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCCAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_89
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_89 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_89";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
+
+  end SLICE_89;
+
+  architecture Structure of SLICE_89 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40107
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40108
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQMH: lut40107
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_8: lut40108
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40109
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40109 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
+
+  end lut40109;
+
+  architecture Structure of lut40109 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCCC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40110
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40110 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE;
+
+  end lut40110;
+
+  architecture Structure of lut40110 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEE44")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_90
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_90 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_90";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
+
+  end SLICE_90;
+
+  architecture Structure of SLICE_90 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40109
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40110
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_CMDWR: lut40109
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_0: lut40110
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40111
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40111 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE;
+
+  end lut40111;
+
+  architecture Structure of lut40111 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFA0A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40112
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40112 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE;
+
+  end lut40112;
+
+  architecture Structure of lut40112 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCFC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_91
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_91 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_91";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
+
+  end SLICE_91;
+
+  architecture Structure of SLICE_91 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40111
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40112
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_7: lut40111
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_1: lut40112
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40113
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40113 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE;
+
+  end lut40113;
+
+  architecture Structure of lut40113 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAFA0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40114
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40114 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE;
+
+  end lut40114;
+
+  architecture Structure of lut40114 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFC0C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_92
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_92 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_92";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
+
+  end SLICE_92;
+
+  architecture Structure of SLICE_92 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40113
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40114
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_6: lut40113
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_2: lut40114
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40115
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40115 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE;
+
+  end lut40115;
+
+  architecture Structure of lut40115 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xE4E4")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_93
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_93 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_93";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
+
+  end SLICE_93;
+
+  architecture Structure of SLICE_93 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40115
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_5: lut40115
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_3: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40116
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40116 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE;
+
+  end lut40116;
+
+  architecture Structure of lut40116 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1111")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_94
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_94 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_94";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
+
+  end SLICE_94;
+
+  architecture Structure of SLICE_94 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0066
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40116
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40116
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN_8_u_0_a2_1_s: lut40072
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RA10: vmuxregsre0066
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, A0_ipd, M0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf is
+    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+          PAD: out Std_logic; PADI: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
+
+  end mjiobuf;
+
+  architecture Structure of mjiobuf is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+    component OBW
+      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PADI, O=>Z);
+    INST2: OBW
+      port map (I=>I, T=>T, O=>PAD);
+  end Structure;
+
+-- entity RD_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_0_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD0 	: VitalDelayType := 0 ns;
+      tpw_RD0_posedge	: VitalDelayType := 0 ns;
+      tpw_RD0_negedge	: VitalDelayType := 0 ns;
+      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD0: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
+
+  end RD_0_B;
+
+  architecture Structure of RD_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD0_ipd 	: std_logic := 'X';
+    signal RD0_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_0: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
+                PADI=>RD0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD0_zd         	: std_logic := 'X';
+    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD0_RD0          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD0_ipd,
+        TestSignalName => "RD0",
+        Period => tperiod_RD0,
+        PulseWidthHigh => tpw_RD0_posedge,
+        PulseWidthLow => tpw_RD0_negedge,
+        PeriodData => periodcheckinfo_RD0,
+        Violation => tviol_RD0_RD0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD0_zd 	:= RD0_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
+                           PathDelay => tpd_RD0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD0,
+                           PathCondition => TRUE)),
+      GlitchData => RD0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0117
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0117 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0117 : ENTITY IS TRUE;
+
+  end mjiobuf0117;
+
+  architecture Structure of mjiobuf0117 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity Dout_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
+
+  end Dout_0_B;
+
+  architecture Structure of Dout_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout0_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_0: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
+    VARIABLE Dout0_zd         	: std_logic := 'X';
+    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout0_zd 	:= Dout0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout0,
+                           PathCondition => TRUE)),
+      GlitchData => Dout0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0118
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0118 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0118 : ENTITY IS TRUE;
+
+  end mjiobuf0118;
+
+  architecture Structure of mjiobuf0118 is
+    component IBPD
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPD
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity PHI2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity PHI2B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "PHI2B";
+
+      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_PHI2S 	: VitalDelayType := 0 ns;
+      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
+      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; PHI2S: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
+
+  end PHI2B;
+
+  architecture Structure of PHI2B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PHI2S_ipd 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    PHI2_pad: mjiobuf0118
+      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
+    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => PHI2S_ipd,
+        TestSignalName => "PHI2S",
+        Period => tperiod_PHI2S,
+        PulseWidthHigh => tpw_PHI2S_posedge,
+        PulseWidthLow => tpw_PHI2S_negedge,
+        PeriodData => periodcheckinfo_PHI2S,
+        Violation => tviol_PHI2S_PHI2S,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
+                           PathDelay => tpd_PHI2S_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0119
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0119 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0119 : ENTITY IS TRUE;
+
+  end mjiobuf0119;
+
+  architecture Structure of mjiobuf0119 is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity UFMSDOB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDOB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDOB";
+
+      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
+
+  end UFMSDOB;
+
+  architecture Structure of UFMSDOB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal UFMSDOS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    UFMSDO_pad: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
+    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => UFMSDOS_ipd,
+        TestSignalName => "UFMSDOS",
+        Period => tperiod_UFMSDOS,
+        PulseWidthHigh => tpw_UFMSDOS_posedge,
+        PulseWidthLow => tpw_UFMSDOS_negedge,
+        PeriodData => periodcheckinfo_UFMSDOS,
+        Violation => tviol_UFMSDOS_UFMSDOS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
+                           PathDelay => tpd_UFMSDOS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0120
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0120 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0120 : ENTITY IS TRUE;
+
+  end mjiobuf0120;
+
+  architecture Structure of mjiobuf0120 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity UFMSDIB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDIB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDIB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
+
+  end UFMSDIB;
+
+  architecture Structure of UFMSDIB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMSDIS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMSDI_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
+    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
+    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMSDIS_zd 	:= UFMSDIS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMSDIS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMSDIS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity UFMCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMCLKB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
+
+  end UFMCLKB;
+
+  architecture Structure of UFMCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMCLKS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMCLK_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
+    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
+    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMCLKS_zd 	:= UFMCLKS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMCLKS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMCLKS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nUFMCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nUFMCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nUFMCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
+
+  end nUFMCSB;
+
+  architecture Structure of nUFMCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nUFMCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nUFMCS_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
+    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
+    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nUFMCSS_zd 	:= nUFMCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nUFMCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nUFMCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMLB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMLB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMLB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
+
+  end RDQMLB;
+
+  architecture Structure of RDQMLB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMLS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQML_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
+    VARIABLE RDQMLS_zd         	: std_logic := 'X';
+    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMLS_zd 	:= RDQMLS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMLS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMLS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMHB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMHB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMHB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
+
+  end RDQMHB;
+
+  architecture Structure of RDQMHB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMHS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQMH_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
+    VARIABLE RDQMHS_zd         	: std_logic := 'X';
+    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMHS_zd 	:= RDQMHS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMHS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMHS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
+
+  end nRCASB;
+
+  architecture Structure of nRCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCASS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCAS_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
+    VARIABLE nRCASS_zd         	: std_logic := 'X';
+    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCASS_zd 	:= nRCASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRRASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRRASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
+
+  end nRRASB;
+
+  architecture Structure of nRRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRRASS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRRAS_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
+    VARIABLE nRRASS_zd         	: std_logic := 'X';
+    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRRASS_zd 	:= nRRASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRRASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRRASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRWES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
+
+  end nRWEB;
+
+  architecture Structure of nRWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRWES_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRWE_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>nRWES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
+    VARIABLE nRWES_zd         	: std_logic := 'X';
+    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRWES_zd 	:= nRWES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRWES,
+                           PathCondition => TRUE)),
+      GlitchData => nRWES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCKEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCKEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCKEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RCKES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
+
+  end RCKEB;
+
+  architecture Structure of RCKEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RCKES_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RCKE_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RCKES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
+    VARIABLE RCKES_zd         	: std_logic := 'X';
+    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RCKES_zd 	:= RCKES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RCKES,
+                           PathCondition => TRUE)),
+      GlitchData => RCKES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCLKB";
+
+      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RCLKS 	: VitalDelayType := 0 ns;
+      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
+      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; RCLKS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
+
+  end RCLKB;
+
+  architecture Structure of RCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal RCLKS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    RCLK_pad: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
+    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RCLKS_ipd,
+        TestSignalName => "RCLKS",
+        Period => tperiod_RCLKS,
+        PulseWidthHigh => tpw_RCLKS_posedge,
+        PulseWidthLow => tpw_RCLKS_negedge,
+        PeriodData => periodcheckinfo_RCLKS,
+        Violation => tviol_RCLKS_RCLKS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
+                           PathDelay => tpd_RCLKS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
+
+  end nRCSB;
+
+  architecture Structure of nRCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCS_pad: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
+    VARIABLE nRCSS_zd         	: std_logic := 'X';
+    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCSS_zd 	:= nRCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_7_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD7 	: VitalDelayType := 0 ns;
+      tpw_RD7_posedge	: VitalDelayType := 0 ns;
+      tpw_RD7_negedge	: VitalDelayType := 0 ns;
+      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD7: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
+
+  end RD_7_B;
+
+  architecture Structure of RD_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD7_ipd 	: std_logic := 'X';
+    signal RD7_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_7: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
+                PADI=>RD7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD7_zd         	: std_logic := 'X';
+    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD7_RD7          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD7_ipd,
+        TestSignalName => "RD7",
+        Period => tperiod_RD7,
+        PulseWidthHigh => tpw_RD7_posedge,
+        PulseWidthLow => tpw_RD7_negedge,
+        PeriodData => periodcheckinfo_RD7,
+        Violation => tviol_RD7_RD7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD7_zd 	:= RD7_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
+                           PathDelay => tpd_RD7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD7,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD7,
+                           PathCondition => TRUE)),
+      GlitchData => RD7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_6_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD6 	: VitalDelayType := 0 ns;
+      tpw_RD6_posedge	: VitalDelayType := 0 ns;
+      tpw_RD6_negedge	: VitalDelayType := 0 ns;
+      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD6: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
+
+  end RD_6_B;
+
+  architecture Structure of RD_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD6_ipd 	: std_logic := 'X';
+    signal RD6_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_6: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
+                PADI=>RD6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD6_zd         	: std_logic := 'X';
+    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD6_RD6          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD6_ipd,
+        TestSignalName => "RD6",
+        Period => tperiod_RD6,
+        PulseWidthHigh => tpw_RD6_posedge,
+        PulseWidthLow => tpw_RD6_negedge,
+        PeriodData => periodcheckinfo_RD6,
+        Violation => tviol_RD6_RD6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD6_zd 	:= RD6_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
+                           PathDelay => tpd_RD6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD6,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD6,
+                           PathCondition => TRUE)),
+      GlitchData => RD6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_5_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD5 	: VitalDelayType := 0 ns;
+      tpw_RD5_posedge	: VitalDelayType := 0 ns;
+      tpw_RD5_negedge	: VitalDelayType := 0 ns;
+      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD5: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
+
+  end RD_5_B;
+
+  architecture Structure of RD_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD5_ipd 	: std_logic := 'X';
+    signal RD5_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_5: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
+                PADI=>RD5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD5_zd         	: std_logic := 'X';
+    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD5_RD5          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD5_ipd,
+        TestSignalName => "RD5",
+        Period => tperiod_RD5,
+        PulseWidthHigh => tpw_RD5_posedge,
+        PulseWidthLow => tpw_RD5_negedge,
+        PeriodData => periodcheckinfo_RD5,
+        Violation => tviol_RD5_RD5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD5_zd 	:= RD5_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
+                           PathDelay => tpd_RD5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD5,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD5,
+                           PathCondition => TRUE)),
+      GlitchData => RD5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_4_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD4 	: VitalDelayType := 0 ns;
+      tpw_RD4_posedge	: VitalDelayType := 0 ns;
+      tpw_RD4_negedge	: VitalDelayType := 0 ns;
+      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD4: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
+
+  end RD_4_B;
+
+  architecture Structure of RD_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD4_ipd 	: std_logic := 'X';
+    signal RD4_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_4: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
+                PADI=>RD4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD4_zd         	: std_logic := 'X';
+    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD4_RD4          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD4_ipd,
+        TestSignalName => "RD4",
+        Period => tperiod_RD4,
+        PulseWidthHigh => tpw_RD4_posedge,
+        PulseWidthLow => tpw_RD4_negedge,
+        PeriodData => periodcheckinfo_RD4,
+        Violation => tviol_RD4_RD4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD4_zd 	:= RD4_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
+                           PathDelay => tpd_RD4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD4,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD4,
+                           PathCondition => TRUE)),
+      GlitchData => RD4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_3_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD3 	: VitalDelayType := 0 ns;
+      tpw_RD3_posedge	: VitalDelayType := 0 ns;
+      tpw_RD3_negedge	: VitalDelayType := 0 ns;
+      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD3: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
+
+  end RD_3_B;
+
+  architecture Structure of RD_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD3_ipd 	: std_logic := 'X';
+    signal RD3_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_3: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
+                PADI=>RD3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD3_zd         	: std_logic := 'X';
+    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD3_RD3          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD3_ipd,
+        TestSignalName => "RD3",
+        Period => tperiod_RD3,
+        PulseWidthHigh => tpw_RD3_posedge,
+        PulseWidthLow => tpw_RD3_negedge,
+        PeriodData => periodcheckinfo_RD3,
+        Violation => tviol_RD3_RD3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD3_zd 	:= RD3_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
+                           PathDelay => tpd_RD3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD3,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD3,
+                           PathCondition => TRUE)),
+      GlitchData => RD3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_2_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD2 	: VitalDelayType := 0 ns;
+      tpw_RD2_posedge	: VitalDelayType := 0 ns;
+      tpw_RD2_negedge	: VitalDelayType := 0 ns;
+      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD2: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
+
+  end RD_2_B;
+
+  architecture Structure of RD_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD2_ipd 	: std_logic := 'X';
+    signal RD2_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_2: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
+                PADI=>RD2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD2_zd         	: std_logic := 'X';
+    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD2_RD2          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD2_ipd,
+        TestSignalName => "RD2",
+        Period => tperiod_RD2,
+        PulseWidthHigh => tpw_RD2_posedge,
+        PulseWidthLow => tpw_RD2_negedge,
+        PeriodData => periodcheckinfo_RD2,
+        Violation => tviol_RD2_RD2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD2_zd 	:= RD2_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
+                           PathDelay => tpd_RD2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD2,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD2,
+                           PathCondition => TRUE)),
+      GlitchData => RD2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_1_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD1 	: VitalDelayType := 0 ns;
+      tpw_RD1_posedge	: VitalDelayType := 0 ns;
+      tpw_RD1_negedge	: VitalDelayType := 0 ns;
+      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD1: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
+
+  end RD_1_B;
+
+  architecture Structure of RD_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD1_ipd 	: std_logic := 'X';
+    signal RD1_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_1: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
+                PADI=>RD1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD1_zd         	: std_logic := 'X';
+    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD1_RD1          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD1_ipd,
+        TestSignalName => "RD1",
+        Period => tperiod_RD1,
+        PulseWidthHigh => tpw_RD1_posedge,
+        PulseWidthLow => tpw_RD1_negedge,
+        PeriodData => periodcheckinfo_RD1,
+        Violation => tviol_RD1_RD1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD1_zd 	:= RD1_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
+                           PathDelay => tpd_RD1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD1,
+                           PathCondition => TRUE)),
+      GlitchData => RD1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_11_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
+
+  end RA_11_B;
+
+  architecture Structure of RA_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA11_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_11: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
+    VARIABLE RA11_zd         	: std_logic := 'X';
+    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA11_zd 	:= RA11_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA11,
+                           PathCondition => TRUE)),
+      GlitchData => RA11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_10_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
+
+  end RA_10_B;
+
+  architecture Structure of RA_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA10_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_10: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
+    VARIABLE RA10_zd         	: std_logic := 'X';
+    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA10_zd 	:= RA10_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA10,
+                           PathCondition => TRUE)),
+      GlitchData => RA10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
+
+  end RA_9_B;
+
+  architecture Structure of RA_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA9_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_9: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
+    VARIABLE RA9_zd         	: std_logic := 'X';
+    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA9_zd 	:= RA9_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA9,
+                           PathCondition => TRUE)),
+      GlitchData => RA9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
+
+  end RA_8_B;
+
+  architecture Structure of RA_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA8_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_8: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
+    VARIABLE RA8_zd         	: std_logic := 'X';
+    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA8_zd 	:= RA8_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA8,
+                           PathCondition => TRUE)),
+      GlitchData => RA8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
+
+  end RA_7_B;
+
+  architecture Structure of RA_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA7_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_7: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
+    VARIABLE RA7_zd         	: std_logic := 'X';
+    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA7_zd 	:= RA7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA7,
+                           PathCondition => TRUE)),
+      GlitchData => RA7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
+
+  end RA_6_B;
+
+  architecture Structure of RA_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA6_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_6: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
+    VARIABLE RA6_zd         	: std_logic := 'X';
+    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA6_zd 	:= RA6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA6,
+                           PathCondition => TRUE)),
+      GlitchData => RA6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
+
+  end RA_5_B;
+
+  architecture Structure of RA_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA5_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_5: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
+    VARIABLE RA5_zd         	: std_logic := 'X';
+    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA5_zd 	:= RA5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA5,
+                           PathCondition => TRUE)),
+      GlitchData => RA5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
+
+  end RA_4_B;
+
+  architecture Structure of RA_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA4_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_4: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
+    VARIABLE RA4_zd         	: std_logic := 'X';
+    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA4_zd 	:= RA4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA4,
+                           PathCondition => TRUE)),
+      GlitchData => RA4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
+
+  end RA_3_B;
+
+  architecture Structure of RA_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA3_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_3: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
+    VARIABLE RA3_zd         	: std_logic := 'X';
+    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA3_zd 	:= RA3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA3,
+                           PathCondition => TRUE)),
+      GlitchData => RA3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
+
+  end RA_2_B;
+
+  architecture Structure of RA_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA2_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_2: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
+    VARIABLE RA2_zd         	: std_logic := 'X';
+    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA2_zd 	:= RA2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA2,
+                           PathCondition => TRUE)),
+      GlitchData => RA2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
+
+  end RA_1_B;
+
+  architecture Structure of RA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA1_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_1: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
+    VARIABLE RA1_zd         	: std_logic := 'X';
+    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA1_zd 	:= RA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA1,
+                           PathCondition => TRUE)),
+      GlitchData => RA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
+
+  end RA_0_B;
+
+  architecture Structure of RA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA0_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_0: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
+    VARIABLE RA0_zd         	: std_logic := 'X';
+    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA0_zd 	:= RA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA0,
+                           PathCondition => TRUE)),
+      GlitchData => RA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
+
+  end RBA_1_B;
+
+  architecture Structure of RBA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA1_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_1: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RBA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
+    VARIABLE RBA1_zd         	: std_logic := 'X';
+    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA1_zd 	:= RBA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA1,
+                           PathCondition => TRUE)),
+      GlitchData => RBA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
+
+  end RBA_0_B;
+
+  architecture Structure of RBA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA0_out 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_0: mjiobuf0120
+      port map (I=>PADDO_ipd, PAD=>RBA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
+    VARIABLE RBA0_zd         	: std_logic := 'X';
+    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA0_zd 	:= RBA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA0,
+                           PathCondition => TRUE)),
+      GlitchData => RBA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0121
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0121 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0121 : ENTITY IS TRUE;
+
+  end mjiobuf0121;
+
+  architecture Structure of mjiobuf0121 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity LEDB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity LEDB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LEDB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; LEDS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
+
+  end LEDB;
+
+  architecture Structure of LEDB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal LEDS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    LED_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>LEDS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
+    VARIABLE LEDS_zd         	: std_logic := 'X';
+    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    LEDS_zd 	:= LEDS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_LEDS,
+                           PathCondition => TRUE)),
+      GlitchData => LEDS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nFWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nFWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nFWEB";
+
+      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nFWES 	: VitalDelayType := 0 ns;
+      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
+      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nFWES: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
+
+  end nFWEB;
+
+  architecture Structure of nFWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nFWES_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nFWE_pad: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
+    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nFWES_ipd,
+        TestSignalName => "nFWES",
+        Period => tperiod_nFWES,
+        PulseWidthHigh => tpw_nFWES_posedge,
+        PulseWidthLow => tpw_nFWES_negedge,
+        PeriodData => periodcheckinfo_nFWES,
+        Violation => tviol_nFWES_nFWES,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
+                           PathDelay => tpd_nFWES_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0122
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0122 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0122 : ENTITY IS TRUE;
+
+  end mjiobuf0122;
+
+  architecture Structure of mjiobuf0122 is
+    component IBPU
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPU
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity nCRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCRASB";
+
+      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCRASS 	: VitalDelayType := 0 ns;
+      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCRASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
+
+  end nCRASB;
+
+  architecture Structure of nCRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCRASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0122
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCRAS_pad: mjiobuf0122
+      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCRASS_ipd,
+        TestSignalName => "nCRASS",
+        Period => tperiod_nCRASS,
+        PulseWidthHigh => tpw_nCRASS_posedge,
+        PulseWidthLow => tpw_nCRASS_negedge,
+        PeriodData => periodcheckinfo_nCRASS,
+        Violation => tviol_nCRASS_nCRASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
+                           PathDelay => tpd_nCRASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nCCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCCASB";
+
+      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCCASS 	: VitalDelayType := 0 ns;
+      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCCASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
+
+  end nCCASB;
+
+  architecture Structure of nCCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCCASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0122
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCCAS_pad: mjiobuf0122
+      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCCASS_ipd,
+        TestSignalName => "nCCASS",
+        Period => tperiod_nCCASS,
+        PulseWidthHigh => tpw_nCCASS_posedge,
+        PulseWidthLow => tpw_nCCASS_negedge,
+        PeriodData => periodcheckinfo_nCCASS,
+        Violation => tviol_nCCASS_nCCASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
+                           PathDelay => tpd_nCCASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
+
+  end Dout_7_B;
+
+  architecture Structure of Dout_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout7_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_7: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
+    VARIABLE Dout7_zd         	: std_logic := 'X';
+    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout7_zd 	:= Dout7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout7,
+                           PathCondition => TRUE)),
+      GlitchData => Dout7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
+
+  end Dout_6_B;
+
+  architecture Structure of Dout_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout6_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_6: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
+    VARIABLE Dout6_zd         	: std_logic := 'X';
+    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout6_zd 	:= Dout6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout6,
+                           PathCondition => TRUE)),
+      GlitchData => Dout6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
+
+  end Dout_5_B;
+
+  architecture Structure of Dout_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout5_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_5: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
+    VARIABLE Dout5_zd         	: std_logic := 'X';
+    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout5_zd 	:= Dout5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout5,
+                           PathCondition => TRUE)),
+      GlitchData => Dout5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
+
+  end Dout_4_B;
+
+  architecture Structure of Dout_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout4_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_4: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
+    VARIABLE Dout4_zd         	: std_logic := 'X';
+    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout4_zd 	:= Dout4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout4,
+                           PathCondition => TRUE)),
+      GlitchData => Dout4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
+
+  end Dout_3_B;
+
+  architecture Structure of Dout_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout3_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_3: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
+    VARIABLE Dout3_zd         	: std_logic := 'X';
+    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout3_zd 	:= Dout3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout3,
+                           PathCondition => TRUE)),
+      GlitchData => Dout3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
+
+  end Dout_2_B;
+
+  architecture Structure of Dout_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout2_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_2: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
+    VARIABLE Dout2_zd         	: std_logic := 'X';
+    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout2_zd 	:= Dout2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout2,
+                           PathCondition => TRUE)),
+      GlitchData => Dout2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
+
+  end Dout_1_B;
+
+  architecture Structure of Dout_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout1_out 	: std_logic := 'X';
+
+    component mjiobuf0117
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_1: mjiobuf0117
+      port map (I=>PADDO_ipd, PAD=>Dout1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
+    VARIABLE Dout1_zd         	: std_logic := 'X';
+    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout1_zd 	:= Dout1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout1,
+                           PathCondition => TRUE)),
+      GlitchData => Dout1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_7_B";
+
+      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din7 	: VitalDelayType := 0 ns;
+      tpw_Din7_posedge	: VitalDelayType := 0 ns;
+      tpw_Din7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
+
+  end Din_7_B;
+
+  architecture Structure of Din_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_7: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din7_Din7          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din7_ipd,
+        TestSignalName => "Din7",
+        Period => tperiod_Din7,
+        PulseWidthHigh => tpw_Din7_posedge,
+        PulseWidthLow => tpw_Din7_negedge,
+        PeriodData => periodcheckinfo_Din7,
+        Violation => tviol_Din7_Din7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
+                           PathDelay => tpd_Din7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_6_B";
+
+      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din6 	: VitalDelayType := 0 ns;
+      tpw_Din6_posedge	: VitalDelayType := 0 ns;
+      tpw_Din6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
+
+  end Din_6_B;
+
+  architecture Structure of Din_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_6: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din6_Din6          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din6_ipd,
+        TestSignalName => "Din6",
+        Period => tperiod_Din6,
+        PulseWidthHigh => tpw_Din6_posedge,
+        PulseWidthLow => tpw_Din6_negedge,
+        PeriodData => periodcheckinfo_Din6,
+        Violation => tviol_Din6_Din6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
+                           PathDelay => tpd_Din6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_5_B";
+
+      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din5 	: VitalDelayType := 0 ns;
+      tpw_Din5_posedge	: VitalDelayType := 0 ns;
+      tpw_Din5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
+
+  end Din_5_B;
+
+  architecture Structure of Din_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_5: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din5_Din5          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din5_ipd,
+        TestSignalName => "Din5",
+        Period => tperiod_Din5,
+        PulseWidthHigh => tpw_Din5_posedge,
+        PulseWidthLow => tpw_Din5_negedge,
+        PeriodData => periodcheckinfo_Din5,
+        Violation => tviol_Din5_Din5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
+                           PathDelay => tpd_Din5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_4_B";
+
+      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din4 	: VitalDelayType := 0 ns;
+      tpw_Din4_posedge	: VitalDelayType := 0 ns;
+      tpw_Din4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
+
+  end Din_4_B;
+
+  architecture Structure of Din_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_4: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din4_Din4          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din4_ipd,
+        TestSignalName => "Din4",
+        Period => tperiod_Din4,
+        PulseWidthHigh => tpw_Din4_posedge,
+        PulseWidthLow => tpw_Din4_negedge,
+        PeriodData => periodcheckinfo_Din4,
+        Violation => tviol_Din4_Din4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
+                           PathDelay => tpd_Din4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_3_B";
+
+      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din3 	: VitalDelayType := 0 ns;
+      tpw_Din3_posedge	: VitalDelayType := 0 ns;
+      tpw_Din3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
+
+  end Din_3_B;
+
+  architecture Structure of Din_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_3: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din3_Din3          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din3_ipd,
+        TestSignalName => "Din3",
+        Period => tperiod_Din3,
+        PulseWidthHigh => tpw_Din3_posedge,
+        PulseWidthLow => tpw_Din3_negedge,
+        PeriodData => periodcheckinfo_Din3,
+        Violation => tviol_Din3_Din3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
+                           PathDelay => tpd_Din3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_2_B";
+
+      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din2 	: VitalDelayType := 0 ns;
+      tpw_Din2_posedge	: VitalDelayType := 0 ns;
+      tpw_Din2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
+
+  end Din_2_B;
+
+  architecture Structure of Din_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_2: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din2_Din2          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din2_ipd,
+        TestSignalName => "Din2",
+        Period => tperiod_Din2,
+        PulseWidthHigh => tpw_Din2_posedge,
+        PulseWidthLow => tpw_Din2_negedge,
+        PeriodData => periodcheckinfo_Din2,
+        Violation => tviol_Din2_Din2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
+                           PathDelay => tpd_Din2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_1_B";
+
+      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din1 	: VitalDelayType := 0 ns;
+      tpw_Din1_posedge	: VitalDelayType := 0 ns;
+      tpw_Din1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
+
+  end Din_1_B;
+
+  architecture Structure of Din_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_1: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din1_Din1          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din1_ipd,
+        TestSignalName => "Din1",
+        Period => tperiod_Din1,
+        PulseWidthHigh => tpw_Din1_posedge,
+        PulseWidthLow => tpw_Din1_negedge,
+        PeriodData => periodcheckinfo_Din1,
+        Violation => tviol_Din1_Din1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
+                           PathDelay => tpd_Din1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_0_B";
+
+      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din0 	: VitalDelayType := 0 ns;
+      tpw_Din0_posedge	: VitalDelayType := 0 ns;
+      tpw_Din0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
+
+  end Din_0_B;
+
+  architecture Structure of Din_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_0: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>Din0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din0_Din0          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din0_ipd,
+        TestSignalName => "Din0",
+        Period => tperiod_Din0,
+        PulseWidthHigh => tpw_Din0_posedge,
+        PulseWidthLow => tpw_Din0_negedge,
+        PeriodData => periodcheckinfo_Din0,
+        Violation => tviol_Din0_Din0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
+                           PathDelay => tpd_Din0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_1_B";
+
+      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW1 	: VitalDelayType := 0 ns;
+      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
+
+  end CROW_1_B;
+
+  architecture Structure of CROW_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_1: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW1_ipd,
+        TestSignalName => "CROW1",
+        Period => tperiod_CROW1,
+        PulseWidthHigh => tpw_CROW1_posedge,
+        PulseWidthLow => tpw_CROW1_negedge,
+        PeriodData => periodcheckinfo_CROW1,
+        Violation => tviol_CROW1_CROW1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
+                           PathDelay => tpd_CROW1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_0_B";
+
+      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW0 	: VitalDelayType := 0 ns;
+      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
+
+  end CROW_0_B;
+
+  architecture Structure of CROW_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_0: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW0_ipd,
+        TestSignalName => "CROW0",
+        Period => tperiod_CROW0,
+        PulseWidthHigh => tpw_CROW0_posedge,
+        PulseWidthLow => tpw_CROW0_negedge,
+        PeriodData => periodcheckinfo_CROW0,
+        Violation => tviol_CROW0_CROW0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
+                           PathDelay => tpd_CROW0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_9_B";
+
+      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin9 	: VitalDelayType := 0 ns;
+      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin9: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
+
+  end MAin_9_B;
+
+  architecture Structure of MAin_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin9_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_9: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin9_ipd,
+        TestSignalName => "MAin9",
+        Period => tperiod_MAin9,
+        PulseWidthHigh => tpw_MAin9_posedge,
+        PulseWidthLow => tpw_MAin9_negedge,
+        PeriodData => periodcheckinfo_MAin9,
+        Violation => tviol_MAin9_MAin9,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
+                           PathDelay => tpd_MAin9_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_8_B";
+
+      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin8 	: VitalDelayType := 0 ns;
+      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin8: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
+
+  end MAin_8_B;
+
+  architecture Structure of MAin_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin8_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_8: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin8_ipd,
+        TestSignalName => "MAin8",
+        Period => tperiod_MAin8,
+        PulseWidthHigh => tpw_MAin8_posedge,
+        PulseWidthLow => tpw_MAin8_negedge,
+        PeriodData => periodcheckinfo_MAin8,
+        Violation => tviol_MAin8_MAin8,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
+                           PathDelay => tpd_MAin8_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_7_B";
+
+      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin7 	: VitalDelayType := 0 ns;
+      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
+
+  end MAin_7_B;
+
+  architecture Structure of MAin_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_7: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin7_ipd,
+        TestSignalName => "MAin7",
+        Period => tperiod_MAin7,
+        PulseWidthHigh => tpw_MAin7_posedge,
+        PulseWidthLow => tpw_MAin7_negedge,
+        PeriodData => periodcheckinfo_MAin7,
+        Violation => tviol_MAin7_MAin7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
+                           PathDelay => tpd_MAin7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_6_B";
+
+      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin6 	: VitalDelayType := 0 ns;
+      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
+
+  end MAin_6_B;
+
+  architecture Structure of MAin_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_6: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin6_ipd,
+        TestSignalName => "MAin6",
+        Period => tperiod_MAin6,
+        PulseWidthHigh => tpw_MAin6_posedge,
+        PulseWidthLow => tpw_MAin6_negedge,
+        PeriodData => periodcheckinfo_MAin6,
+        Violation => tviol_MAin6_MAin6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
+                           PathDelay => tpd_MAin6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_5_B";
+
+      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin5 	: VitalDelayType := 0 ns;
+      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
+
+  end MAin_5_B;
+
+  architecture Structure of MAin_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_5: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin5_ipd,
+        TestSignalName => "MAin5",
+        Period => tperiod_MAin5,
+        PulseWidthHigh => tpw_MAin5_posedge,
+        PulseWidthLow => tpw_MAin5_negedge,
+        PeriodData => periodcheckinfo_MAin5,
+        Violation => tviol_MAin5_MAin5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
+                           PathDelay => tpd_MAin5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_4_B";
+
+      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin4 	: VitalDelayType := 0 ns;
+      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
+
+  end MAin_4_B;
+
+  architecture Structure of MAin_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_4: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin4_ipd,
+        TestSignalName => "MAin4",
+        Period => tperiod_MAin4,
+        PulseWidthHigh => tpw_MAin4_posedge,
+        PulseWidthLow => tpw_MAin4_negedge,
+        PeriodData => periodcheckinfo_MAin4,
+        Violation => tviol_MAin4_MAin4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
+                           PathDelay => tpd_MAin4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_3_B";
+
+      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin3 	: VitalDelayType := 0 ns;
+      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
+
+  end MAin_3_B;
+
+  architecture Structure of MAin_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_3: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin3_ipd,
+        TestSignalName => "MAin3",
+        Period => tperiod_MAin3,
+        PulseWidthHigh => tpw_MAin3_posedge,
+        PulseWidthLow => tpw_MAin3_negedge,
+        PeriodData => periodcheckinfo_MAin3,
+        Violation => tviol_MAin3_MAin3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
+                           PathDelay => tpd_MAin3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_2_B";
+
+      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin2 	: VitalDelayType := 0 ns;
+      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
+
+  end MAin_2_B;
+
+  architecture Structure of MAin_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_2: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin2_ipd,
+        TestSignalName => "MAin2",
+        Period => tperiod_MAin2,
+        PulseWidthHigh => tpw_MAin2_posedge,
+        PulseWidthLow => tpw_MAin2_negedge,
+        PeriodData => periodcheckinfo_MAin2,
+        Violation => tviol_MAin2_MAin2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
+                           PathDelay => tpd_MAin2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_1_B";
+
+      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin1 	: VitalDelayType := 0 ns;
+      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
+
+  end MAin_1_B;
+
+  architecture Structure of MAin_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_1: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin1_ipd,
+        TestSignalName => "MAin1",
+        Period => tperiod_MAin1,
+        PulseWidthHigh => tpw_MAin1_posedge,
+        PulseWidthLow => tpw_MAin1_negedge,
+        PeriodData => periodcheckinfo_MAin1,
+        Violation => tviol_MAin1_MAin1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
+                           PathDelay => tpd_MAin1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_0_B";
+
+      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin0 	: VitalDelayType := 0 ns;
+      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
+
+  end MAin_0_B;
+
+  architecture Structure of MAin_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_0: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin0_ipd,
+        TestSignalName => "MAin0",
+        Period => tperiod_MAin0,
+        PulseWidthHigh => tpw_MAin0_posedge,
+        PulseWidthLow => tpw_MAin0_negedge,
+        PeriodData => periodcheckinfo_MAin0,
+        Violation => tviol_MAin0_MAin0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
+                           PathDelay => tpd_MAin0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RAM2GS
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RAM2GS is
+    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
+          CROW: in Std_logic_vector (1 downto 0); 
+          Din: in Std_logic_vector (7 downto 0); 
+          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
+          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
+          RBA: out Std_logic_vector (1 downto 0); 
+          RA: out Std_logic_vector (11 downto 0); 
+          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
+          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
+          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
+          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
+          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
+
+
+
+  end RAM2GS;
+
+  architecture Structure of RAM2GS is
+    signal FS_1: Std_logic;
+    signal FS_0: Std_logic;
+    signal RCLK_c: Std_logic;
+    signal FS_cry_1: Std_logic;
+    signal FS_17: Std_logic;
+    signal FS_16: Std_logic;
+    signal FS_cry_15: Std_logic;
+    signal FS_15: Std_logic;
+    signal FS_14: Std_logic;
+    signal FS_cry_13: Std_logic;
+    signal FS_13: Std_logic;
+    signal FS_12: Std_logic;
+    signal FS_cry_11: Std_logic;
+    signal FS_11: Std_logic;
+    signal FS_10: Std_logic;
+    signal FS_cry_9: Std_logic;
+    signal FS_9: Std_logic;
+    signal FS_8: Std_logic;
+    signal FS_cry_7: Std_logic;
+    signal FS_7: Std_logic;
+    signal FS_6: Std_logic;
+    signal FS_cry_5: Std_logic;
+    signal FS_5: Std_logic;
+    signal FS_4: Std_logic;
+    signal FS_cry_3: Std_logic;
+    signal FS_3: Std_logic;
+    signal FS_2: Std_logic;
+    signal CmdEnable17_0_a2_4: Std_logic;
+    signal CmdEnable17_0_a2_3: Std_logic;
+    signal MAin_c_0: Std_logic;
+    signal N_147: Std_logic;
+    signal ADSubmitted: Std_logic;
+    signal CmdEnable17: Std_logic;
+    signal CmdEnable16: Std_logic;
+    signal C1WR_0_a2: Std_logic;
+    signal ADSubmitted_r: Std_logic;
+    signal PHI2_c: Std_logic;
+    signal CmdEnable16_0_a2_5: Std_logic;
+    signal CmdEnable16_0_a2_4: Std_logic;
+    signal MAin_c_1: Std_logic;
+    signal C1Submitted: Std_logic;
+    signal C1Submitted_RNO: Std_logic;
+    signal RASr2: Std_logic;
+    signal S_1: Std_logic;
+    signal CO0: Std_logic;
+    signal IS_3: Std_logic;
+    signal N_177_i: Std_logic;
+    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
+    signal CmdEnable: Std_logic;
+    signal un1_CMDWR: Std_logic;
+    signal CmdEnable_s: Std_logic;
+    signal N_128: Std_logic;
+    signal Din_c_5: Std_logic;
+    signal Din_c_3: Std_logic;
+    signal N_133: Std_logic;
+    signal N_152: Std_logic;
+    signal N_132: Std_logic;
+    signal LEDEN: Std_logic;
+    signal N_21_i: Std_logic;
+    signal XOR8MEG18: Std_logic;
+    signal CmdLEDEN: Std_logic;
+    signal CmdSubmitted: Std_logic;
+    signal InitReady: Std_logic;
+    signal PHI2r3: Std_logic;
+    signal PHI2r2: Std_logic;
+    signal CmdSubmitted_1_sqmuxa: Std_logic;
+    signal N_460_0: Std_logic;
+    signal N_136: Std_logic;
+    signal N_43: Std_logic;
+    signal Cmdn8MEGEN: Std_logic;
+    signal CmdEnable16_4: Std_logic;
+    signal n8MEGEN: Std_logic;
+    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
+    signal N_19_i: Std_logic;
+    signal nRRAS_5_u_i_0: Std_logic;
+    signal IS_0: Std_logic;
+    signal N_160: Std_logic;
+    signal N_155: Std_logic;
+    signal Ready: Std_logic;
+    signal N_64_i_i: Std_logic;
+    signal N_24: Std_logic;
+    signal IS_1: Std_logic;
+    signal IS_2: Std_logic;
+    signal N_60_i_i: Std_logic;
+    signal N_56_i: Std_logic;
+    signal N_159_i: Std_logic;
+    signal N_159: Std_logic;
+    signal N_61_i_i: Std_logic;
+    signal RA10s_i: Std_logic;
+    signal N_126: Std_logic;
+    signal N_51: Std_logic;
+    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
+    signal InitReady3: Std_logic;
+    signal N_461_0: Std_logic;
+    signal UFMSDI_ens2_i_a0: Std_logic;
+    signal nCRAS_c: Std_logic;
+    signal CBR: Std_logic;
+    signal UFMSDO_c: Std_logic;
+    signal N_70: Std_logic;
+    signal N_33: Std_logic;
+    signal LED_c: Std_logic;
+    signal un1_Din_4: Std_logic;
+    signal XOR8MEG: Std_logic;
+    signal Din_c_6: Std_logic;
+    signal RA11_2: Std_logic;
+    signal Ready_fast: Std_logic;
+    signal RA_c_11: Std_logic;
+    signal N_171: Std_logic;
+    signal CASr2: Std_logic;
+    signal FWEr_fast: Std_logic;
+    signal RCKEEN_8_u_0_0: Std_logic;
+    signal RCKEEN_8_u_1: Std_logic;
+    signal RCKEEN_8: Std_logic;
+    signal PHI2r: Std_logic;
+    signal RCKEEN: Std_logic;
+    signal RASr3: Std_logic;
+    signal RASr: Std_logic;
+    signal RCKE_2: Std_logic;
+    signal RCKE_c: Std_logic;
+    signal m18_0_a3_3: Std_logic;
+    signal S_0_i_o2_1: Std_logic;
+    signal N_165: Std_logic;
+    signal N_462_0: Std_logic;
+    signal Ready_0_sqmuxa: Std_logic;
+    signal N_463_0: Std_logic;
+    signal nRRAS_0_sqmuxa: Std_logic;
+    signal CmdUFMCLK: Std_logic;
+    signal N_129: Std_logic;
+    signal UFMCLK_r_i_a2_2_2: Std_logic;
+    signal UFMCLK_c: Std_logic;
+    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
+    signal nUFMCS15: Std_logic;
+    signal N_139_i: Std_logic;
+    signal UFMCLK_RNO: Std_logic;
+    signal UFMSDI_r_xx_mm_1: Std_logic;
+    signal UFMSDI_c: Std_logic;
+    signal UFMSDI_RNO: Std_logic;
+    signal MAin_c_4: Std_logic;
+    signal nRowColSel: Std_logic;
+    signal RowA_4: Std_logic;
+    signal Din_c_4: Std_logic;
+    signal nCCAS_c: Std_logic;
+    signal RA_c_4: Std_logic;
+    signal WRD_4: Std_logic;
+    signal WRD_5: Std_logic;
+    signal Bank_7: Std_logic;
+    signal Bank_6: Std_logic;
+    signal Bank_5: Std_logic;
+    signal Bank_2: Std_logic;
+    signal Din_c_7: Std_logic;
+    signal WRD_6: Std_logic;
+    signal C1WR_0_a2_0_11: Std_logic;
+    signal WRD_7: Std_logic;
+    signal Din_c_0: Std_logic;
+    signal Din_c_2: Std_logic;
+    signal Din_c_1: Std_logic;
+    signal XOR8MEG_3_u_0_a3_2: Std_logic;
+    signal XOR8MEG_3: Std_logic;
+    signal N_69: Std_logic;
+    signal N_31: Std_logic;
+    signal N_151: Std_logic;
+    signal N_41: Std_logic;
+    signal g0_1: Std_logic;
+    signal nRCAS_0_sqmuxa_1: Std_logic;
+    signal N_37_i: Std_logic;
+    signal nRCAS_c: Std_logic;
+    signal CASr3: Std_logic;
+    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
+    signal N_28_i_1: Std_logic;
+    signal N_28_i: Std_logic;
+    signal nRCS_c: Std_logic;
+    signal N_24_i: Std_logic;
+    signal nRRAS_c: Std_logic;
+    signal CBR_fast: Std_logic;
+    signal m18_0_a2_1: Std_logic;
+    signal FWEr: Std_logic;
+    signal G_17_1: Std_logic;
+    signal N_39_i: Std_logic;
+    signal nRWE_c: Std_logic;
+    signal N_179: Std_logic;
+    signal nRowColSel_0_0: Std_logic;
+    signal nUFMCS_c: Std_logic;
+    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
+    signal nUFMCS_s_0_N_5_i: Std_logic;
+    signal CmdUFMCS: Std_logic;
+    signal N_95_5: Std_logic;
+    signal N_95_3: Std_logic;
+    signal RowA_0: Std_logic;
+    signal RowA_1: Std_logic;
+    signal MAin_c_5: Std_logic;
+    signal CmdUFMCLK_1_sqmuxa: Std_logic;
+    signal RowA_5: Std_logic;
+    signal N_137_8: Std_logic;
+    signal un1_FS_14_i_a2_0_1: Std_logic;
+    signal N_137_6: Std_logic;
+    signal un1_FS_13_i_a2_1: Std_logic;
+    signal Bank_0: Std_logic;
+    signal C1WR_0_a2_0_10: Std_logic;
+    signal Bank_1: Std_logic;
+    signal MAin_c_6: Std_logic;
+    signal MAin_c_7: Std_logic;
+    signal C1WR_0_a2_0_3: Std_logic;
+    signal Bank_3: Std_logic;
+    signal Bank_4: Std_logic;
+    signal C1WR_0_a2_0_4: Std_logic;
+    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
+    signal MAin_c_3: Std_logic;
+    signal MAin_c_2: Std_logic;
+    signal RowA_2: Std_logic;
+    signal RowA_3: Std_logic;
+    signal CmdUFMSDI: Std_logic;
+    signal CASr: Std_logic;
+    signal CmdEnable16_1: Std_logic;
+    signal m6_0_a2_2: Std_logic;
+    signal WRD_0: Std_logic;
+    signal WRD_1: Std_logic;
+    signal g4_0_0_0: Std_logic;
+    signal MAin_c_9: Std_logic;
+    signal MAin_c_8: Std_logic;
+    signal RowA_8: Std_logic;
+    signal RowA_9: Std_logic;
+    signal nFWE_c: Std_logic;
+    signal CROW_c_1: Std_logic;
+    signal CROW_c_0: Std_logic;
+    signal RBA_c_0: Std_logic;
+    signal RBA_c_1: Std_logic;
+    signal WRD_2: Std_logic;
+    signal WRD_3: Std_logic;
+    signal RA_c_9: Std_logic;
+    signal RDQML_c: Std_logic;
+    signal RD_1_i: Std_logic;
+    signal RowA_6: Std_logic;
+    signal RowA_7: Std_logic;
+    signal RA_c_8: Std_logic;
+    signal RDQMH_c: Std_logic;
+    signal RA_c_0: Std_logic;
+    signal RA_c_1: Std_logic;
+    signal RA_c_7: Std_logic;
+    signal RA_c_2: Std_logic;
+    signal RA_c_6: Std_logic;
+    signal RA_c_3: Std_logic;
+    signal RA_c_5: Std_logic;
+    signal RA_c_10: Std_logic;
+    signal RD_in_0: Std_logic;
+    signal RD_in_7: Std_logic;
+    signal RD_in_6: Std_logic;
+    signal RD_in_5: Std_logic;
+    signal RD_in_4: Std_logic;
+    signal RD_in_3: Std_logic;
+    signal RD_in_2: Std_logic;
+    signal RD_in_1: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI_TSALL: Std_logic;
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+    component PUR
+      port (PUR: in Std_logic);
+    end component;
+    component GSR
+      port (GSR: in Std_logic);
+    end component;
+    component TSALL
+      port (TSALL: in Std_logic);
+    end component;
+    component SLICE_0
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component SLICE_1
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_2
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_3
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_4
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_5
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_6
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_7
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_8
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_9
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_14
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_19
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_20
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component SLICE_21
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_22
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_26
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_29
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_30
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_31
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_32
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_33
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_39
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_41
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_42
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_43
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_44
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_50
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_51
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_52
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_55
+      port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_56
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_57
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_58
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_59
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_60
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_61
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_62
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_63
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_64
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component nRWE_RNO_1_SLICE_65
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component SLICE_66
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_67
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_68
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_69
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_70
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_71
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_72
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_73
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_74
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_75
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_76
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_77
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_78
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_79
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_80
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_81
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_82
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_83
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_84
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_85
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_86
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_87
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_88
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_89
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_90
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_91
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_92
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_93
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_94
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component RD_0_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD0: inout Std_logic);
+    end component;
+    component Dout_0_B
+      port (PADDO: in Std_logic; Dout0: out Std_logic);
+    end component;
+    component PHI2B
+      port (PADDI: out Std_logic; PHI2S: in Std_logic);
+    end component;
+    component UFMSDOB
+      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+    end component;
+    component UFMSDIB
+      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+    end component;
+    component UFMCLKB
+      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+    end component;
+    component nUFMCSB
+      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+    end component;
+    component RDQMLB
+      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+    end component;
+    component RDQMHB
+      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+    end component;
+    component nRCASB
+      port (PADDO: in Std_logic; nRCASS: out Std_logic);
+    end component;
+    component nRRASB
+      port (PADDO: in Std_logic; nRRASS: out Std_logic);
+    end component;
+    component nRWEB
+      port (PADDO: in Std_logic; nRWES: out Std_logic);
+    end component;
+    component RCKEB
+      port (PADDO: in Std_logic; RCKES: out Std_logic);
+    end component;
+    component RCLKB
+      port (PADDI: out Std_logic; RCLKS: in Std_logic);
+    end component;
+    component nRCSB
+      port (PADDO: in Std_logic; nRCSS: out Std_logic);
+    end component;
+    component RD_7_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD7: inout Std_logic);
+    end component;
+    component RD_6_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD6: inout Std_logic);
+    end component;
+    component RD_5_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD5: inout Std_logic);
+    end component;
+    component RD_4_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD4: inout Std_logic);
+    end component;
+    component RD_3_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD3: inout Std_logic);
+    end component;
+    component RD_2_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD2: inout Std_logic);
+    end component;
+    component RD_1_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD1: inout Std_logic);
+    end component;
+    component RA_11_B
+      port (PADDO: in Std_logic; RA11: out Std_logic);
+    end component;
+    component RA_10_B
+      port (PADDO: in Std_logic; RA10: out Std_logic);
+    end component;
+    component RA_9_B
+      port (PADDO: in Std_logic; RA9: out Std_logic);
+    end component;
+    component RA_8_B
+      port (PADDO: in Std_logic; RA8: out Std_logic);
+    end component;
+    component RA_7_B
+      port (PADDO: in Std_logic; RA7: out Std_logic);
+    end component;
+    component RA_6_B
+      port (PADDO: in Std_logic; RA6: out Std_logic);
+    end component;
+    component RA_5_B
+      port (PADDO: in Std_logic; RA5: out Std_logic);
+    end component;
+    component RA_4_B
+      port (PADDO: in Std_logic; RA4: out Std_logic);
+    end component;
+    component RA_3_B
+      port (PADDO: in Std_logic; RA3: out Std_logic);
+    end component;
+    component RA_2_B
+      port (PADDO: in Std_logic; RA2: out Std_logic);
+    end component;
+    component RA_1_B
+      port (PADDO: in Std_logic; RA1: out Std_logic);
+    end component;
+    component RA_0_B
+      port (PADDO: in Std_logic; RA0: out Std_logic);
+    end component;
+    component RBA_1_B
+      port (PADDO: in Std_logic; RBA1: out Std_logic);
+    end component;
+    component RBA_0_B
+      port (PADDO: in Std_logic; RBA0: out Std_logic);
+    end component;
+    component LEDB
+      port (PADDO: in Std_logic; LEDS: out Std_logic);
+    end component;
+    component nFWEB
+      port (PADDI: out Std_logic; nFWES: in Std_logic);
+    end component;
+    component nCRASB
+      port (PADDI: out Std_logic; nCRASS: in Std_logic);
+    end component;
+    component nCCASB
+      port (PADDI: out Std_logic; nCCASS: in Std_logic);
+    end component;
+    component Dout_7_B
+      port (PADDO: in Std_logic; Dout7: out Std_logic);
+    end component;
+    component Dout_6_B
+      port (PADDO: in Std_logic; Dout6: out Std_logic);
+    end component;
+    component Dout_5_B
+      port (PADDO: in Std_logic; Dout5: out Std_logic);
+    end component;
+    component Dout_4_B
+      port (PADDO: in Std_logic; Dout4: out Std_logic);
+    end component;
+    component Dout_3_B
+      port (PADDO: in Std_logic; Dout3: out Std_logic);
+    end component;
+    component Dout_2_B
+      port (PADDO: in Std_logic; Dout2: out Std_logic);
+    end component;
+    component Dout_1_B
+      port (PADDO: in Std_logic; Dout1: out Std_logic);
+    end component;
+    component Din_7_B
+      port (PADDI: out Std_logic; Din7: in Std_logic);
+    end component;
+    component Din_6_B
+      port (PADDI: out Std_logic; Din6: in Std_logic);
+    end component;
+    component Din_5_B
+      port (PADDI: out Std_logic; Din5: in Std_logic);
+    end component;
+    component Din_4_B
+      port (PADDI: out Std_logic; Din4: in Std_logic);
+    end component;
+    component Din_3_B
+      port (PADDI: out Std_logic; Din3: in Std_logic);
+    end component;
+    component Din_2_B
+      port (PADDI: out Std_logic; Din2: in Std_logic);
+    end component;
+    component Din_1_B
+      port (PADDI: out Std_logic; Din1: in Std_logic);
+    end component;
+    component Din_0_B
+      port (PADDI: out Std_logic; Din0: in Std_logic);
+    end component;
+    component CROW_1_B
+      port (PADDI: out Std_logic; CROW1: in Std_logic);
+    end component;
+    component CROW_0_B
+      port (PADDI: out Std_logic; CROW0: in Std_logic);
+    end component;
+    component MAin_9_B
+      port (PADDI: out Std_logic; MAin9: in Std_logic);
+    end component;
+    component MAin_8_B
+      port (PADDI: out Std_logic; MAin8: in Std_logic);
+    end component;
+    component MAin_7_B
+      port (PADDI: out Std_logic; MAin7: in Std_logic);
+    end component;
+    component MAin_6_B
+      port (PADDI: out Std_logic; MAin6: in Std_logic);
+    end component;
+    component MAin_5_B
+      port (PADDI: out Std_logic; MAin5: in Std_logic);
+    end component;
+    component MAin_4_B
+      port (PADDI: out Std_logic; MAin4: in Std_logic);
+    end component;
+    component MAin_3_B
+      port (PADDI: out Std_logic; MAin3: in Std_logic);
+    end component;
+    component MAin_2_B
+      port (PADDI: out Std_logic; MAin2: in Std_logic);
+    end component;
+    component MAin_1_B
+      port (PADDI: out Std_logic; MAin1: in Std_logic);
+    end component;
+    component MAin_0_B
+      port (PADDI: out Std_logic; MAin0: in Std_logic);
+    end component;
+  begin
+    SLICE_0I: SLICE_0
+      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
+                FCO=>FS_cry_1);
+    SLICE_1I: SLICE_1
+      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
+                Q1=>FS_17);
+    SLICE_2I: SLICE_2
+      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
+                Q1=>FS_15, FCO=>FS_cry_15);
+    SLICE_3I: SLICE_3
+      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
+                Q1=>FS_13, FCO=>FS_cry_13);
+    SLICE_4I: SLICE_4
+      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
+                Q1=>FS_11, FCO=>FS_cry_11);
+    SLICE_5I: SLICE_5
+      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
+                Q1=>FS_9, FCO=>FS_cry_9);
+    SLICE_6I: SLICE_6
+      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
+                Q1=>FS_7, FCO=>FS_cry_7);
+    SLICE_7I: SLICE_7
+      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
+                Q1=>FS_5, FCO=>FS_cry_5);
+    SLICE_8I: SLICE_8
+      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
+                Q1=>FS_3, FCO=>FS_cry_3);
+    SLICE_9I: SLICE_9
+      port map (D1=>CmdEnable17_0_a2_4, C1=>CmdEnable17_0_a2_3, B1=>MAin_c_0, 
+                A1=>N_147, D0=>ADSubmitted, C0=>CmdEnable17, B0=>CmdEnable16, 
+                A0=>C1WR_0_a2, DI0=>ADSubmitted_r, CLK=>PHI2_c, 
+                F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
+    SLICE_14I: SLICE_14
+      port map (D1=>CmdEnable16_0_a2_5, C1=>CmdEnable16_0_a2_4, A1=>N_147, 
+                D0=>MAin_c_1, C0=>CmdEnable16, B0=>C1Submitted, A0=>N_147, 
+                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
+                Q0=>C1Submitted, F1=>CmdEnable16);
+    SLICE_19I: SLICE_19
+      port map (D1=>RASr2, C1=>S_1, B1=>CO0, A1=>IS_3, C0=>S_1, A0=>CO0, 
+                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
+                F1=>Ready_0_sqmuxa_0_a3_2);
+    SLICE_20I: SLICE_20
+      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>CmdEnable17, C0=>un1_CMDWR, 
+                B0=>C1Submitted, A0=>CmdEnable, DI0=>CmdEnable_s, 
+                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
+    SLICE_21I: SLICE_21
+      port map (D1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_133, C0=>N_152, 
+                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
+                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
+    SLICE_22I: SLICE_22
+      port map (D1=>CmdSubmitted, C1=>InitReady, B1=>PHI2r3, A1=>PHI2r2, 
+                C0=>CmdSubmitted_1_sqmuxa, A0=>CmdSubmitted, DI0=>N_460_0, 
+                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
+    SLICE_26I: SLICE_26
+      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
+                D0=>n8MEGEN, C0=>Cmdn8MEGEN_4_u_i_0, A0=>N_152, DI0=>N_19_i, 
+                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
+                F1=>Cmdn8MEGEN_4_u_i_0);
+    SLICE_29I: SLICE_29
+      port map (D1=>nRRAS_5_u_i_0, C1=>IS_0, B1=>N_160, A1=>N_155, D0=>IS_0, 
+                B0=>Ready, A0=>N_155, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
+                Q0=>IS_0, F1=>N_24);
+    SLICE_30I: SLICE_30
+      port map (D1=>IS_0, B1=>IS_1, A1=>IS_2, D0=>IS_0, A0=>IS_1, 
+                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
+    SLICE_31I: SLICE_31
+      port map (D1=>IS_2, C1=>N_159, B1=>IS_1, A1=>IS_3, D0=>IS_2, C0=>IS_0, 
+                B0=>IS_1, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
+    SLICE_32I: SLICE_32
+      port map (D1=>N_126, C1=>N_51, B1=>UFMSDI_ens2_i_a2_4_2, A1=>InitReady, 
+                B0=>InitReady3, A0=>InitReady, DI0=>N_461_0, CLK=>RCLK_c, 
+                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
+    SLICE_33I: SLICE_33
+      port map (D1=>nCRAS_c, C1=>LEDEN, A1=>CBR, D0=>UFMSDO_c, C0=>InitReady, 
+                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
+                Q0=>LEDEN, F1=>LED_c);
+    SLICE_39I: SLICE_39
+      port map (D1=>un1_Din_4, A1=>XOR8MEG, D0=>Din_c_6, C0=>n8MEGEN, 
+                A0=>XOR8MEG, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
+                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
+    SLICE_41I: SLICE_41
+      port map (D1=>CASr2, C1=>S_1, B1=>CO0, A1=>FWEr_fast, D0=>CBR, C0=>Ready, 
+                B0=>RCKEEN_8_u_0_0, A0=>RCKEEN_8_u_1, DI0=>RCKEEN_8, M1=>PHI2r, 
+                CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_1, 
+                Q1=>PHI2r2);
+    SLICE_42I: SLICE_42
+      port map (D1=>IS_0, C1=>RASr2, B1=>IS_2, A1=>IS_1, D0=>RCKEEN, C0=>RASr3, 
+                B0=>RASr, A0=>RASr2, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
+                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
+    SLICE_43I: SLICE_43
+      port map (D1=>InitReady, C1=>RASr2, B1=>Ready, A1=>S_0_i_o2_1, 
+                D0=>InitReady, C0=>Ready, B0=>N_165, A0=>Ready_0_sqmuxa_0_a3_2, 
+                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
+                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
+    SLICE_44I: SLICE_44
+      port map (D1=>Ready, C1=>InitReady, B1=>Ready_0_sqmuxa_0_a3_2, A1=>N_165, 
+                C0=>Ready_0_sqmuxa, A0=>Ready_fast, DI0=>N_463_0, M1=>nCRAS_c, 
+                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
+                Q1=>RASr);
+    SLICE_50I: SLICE_50
+      port map (D1=>Ready, C1=>CO0, B1=>S_1, C0=>CO0, A0=>S_1, DI0=>S_0_i_o2_1, 
+                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
+                F1=>nRRAS_0_sqmuxa);
+    SLICE_51I: SLICE_51
+      port map (D1=>CmdUFMCLK, C1=>N_129, B1=>InitReady, A1=>UFMCLK_r_i_a2_2_2, 
+                D0=>UFMCLK_c, C0=>UFMCLK_r_i_m4_xx_mm_1, B0=>nUFMCS15, 
+                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
+                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
+                Q1=>RASr2);
+    SLICE_52I: SLICE_52
+      port map (D1=>PHI2r2, C1=>PHI2r3, B1=>InitReady, A1=>CmdSubmitted, 
+                D0=>UFMSDI_r_xx_mm_1, C0=>N_139_i, B0=>UFMSDI_c, A0=>nUFMCS15, 
+                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
+                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
+    SLICE_55I: SLICE_55
+      port map (D0=>MAin_c_4, B0=>nRowColSel, A0=>RowA_4, M1=>Din_c_5, 
+                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
+    SLICE_56I: SLICE_56
+      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, D0=>FS_5, 
+                C0=>FS_9, B0=>FS_7, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
+                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
+    SLICE_57I: SLICE_57
+      port map (D1=>un1_Din_4, C1=>Din_c_0, B1=>Din_c_2, A1=>Din_c_3, 
+                D0=>Din_c_1, C0=>XOR8MEG_3_u_0_a3_2, B0=>LEDEN, A0=>N_171, 
+                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
+                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
+    SLICE_58I: SLICE_58
+      port map (D1=>N_51, C1=>InitReady, A1=>FS_8, D0=>UFMSDO_c, C0=>InitReady, 
+                B0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
+                Q0=>n8MEGEN, F1=>N_151);
+    SLICE_59I: SLICE_59
+      port map (D1=>N_155, C1=>S_1, B1=>Ready, A1=>N_160, D0=>N_41, C0=>S_1, 
+                B0=>g0_1, A0=>nRCAS_0_sqmuxa_1, DI0=>N_37_i, CLK=>RCLK_c, 
+                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
+    SLICE_60I: SLICE_60
+      port map (D1=>FWEr_fast, C1=>CO0, B1=>CASr2, A1=>CASr3, 
+                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
+                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
+    SLICE_61I: SLICE_61
+      port map (D1=>S_0_i_o2_1, C1=>RCKE_c, B1=>Ready, A1=>RASr2, D0=>IS_0, 
+                C0=>N_155, B0=>nRRAS_5_u_i_0, A0=>N_160, DI0=>N_24_i, 
+                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
+    SLICE_62I: SLICE_62
+      port map (D1=>RASr2, C1=>S_0_i_o2_1, B1=>Ready, A1=>CBR_fast, 
+                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>FWEr, A0=>G_17_1, 
+                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
+                F1=>nRCAS_0_sqmuxa_1);
+    SLICE_63I: SLICE_63
+      port map (D1=>FWEr, C1=>CASr3, B1=>Ready, A1=>CBR, D0=>S_1, C0=>N_179, 
+                B0=>Ready, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
+                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
+    SLICE_64I: SLICE_64
+      port map (D1=>FS_11, C1=>InitReady, B1=>N_51, A1=>FS_10, D0=>N_139_i, 
+                C0=>nUFMCS_c, B0=>nUFMCS15, A0=>nUFMCS_s_0_N_5_i_N_2L1, 
+                DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, F0=>nUFMCS_s_0_N_5_i, 
+                Q0=>nUFMCS_c, F1=>nUFMCS15);
+    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
+      port map (D1=>RASr2, C1=>S_1, B1=>CO0, A1=>RCKE_c, D0=>m18_0_a3_3, 
+                C0=>S_1, B0=>CO0, A0=>InitReady, M0=>Ready, OFX0=>m18_0_a2_1);
+    SLICE_66I: SLICE_66
+      port map (D1=>CmdUFMCS, C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, D0=>N_95_5, 
+                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
+                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
+                Q1=>RowA_1);
+    SLICE_67I: SLICE_67
+      port map (D1=>N_128, C1=>Din_c_3, B1=>Din_c_5, A1=>XOR8MEG18, 
+                D0=>CmdEnable, C0=>MAin_c_0, B0=>MAin_c_1, A0=>N_147, 
+                M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>XOR8MEG18, Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
+    SLICE_68I: SLICE_68
+      port map (D1=>FS_5, C1=>FS_2, B1=>FS_0, A1=>FS_3, D0=>N_137_8, C0=>N_136, 
+                B0=>un1_FS_14_i_a2_0_1, A0=>N_137_6, F0=>N_31, 
+                F1=>un1_FS_14_i_a2_0_1);
+    SLICE_69I: SLICE_69
+      port map (D1=>FS_0, C1=>FS_3, B1=>FS_5, A1=>FS_2, D0=>N_137_8, C0=>N_136, 
+                B0=>N_137_6, A0=>un1_FS_13_i_a2_1, F0=>N_33, 
+                F1=>un1_FS_13_i_a2_1);
+    SLICE_70I: SLICE_70
+      port map (D1=>Bank_0, C1=>C1WR_0_a2_0_10, B1=>C1WR_0_a2_0_11, A1=>Bank_1, 
+                C0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
+                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
+    SLICE_71I: SLICE_71
+      port map (D1=>MAin_c_6, C1=>MAin_c_7, B1=>MAin_c_4, A1=>MAin_c_5, 
+                D0=>C1WR_0_a2_0_3, C0=>Bank_3, B0=>Bank_4, A0=>C1WR_0_a2_0_4, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
+                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
+    SLICE_72I: SLICE_72
+      port map (D1=>UFMSDI_ens2_i_o2_0_3, C1=>FS_16, A1=>FS_12, D0=>FS_4, 
+                C0=>N_51, B0=>FS_11, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
+                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
+                Q1=>RowA_3);
+    SLICE_73I: SLICE_73
+      port map (D1=>InitReady, C1=>S_1, B1=>RASr2, A1=>CO0, C0=>N_155, 
+                A0=>Ready, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
+                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
+    SLICE_74I: SLICE_74
+      port map (B1=>FS_11, A1=>FS_14, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
+                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
+                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
+    SLICE_75I: SLICE_75
+      port map (D1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, D0=>Din_c_1, C0=>N_128, 
+                B0=>Din_c_5, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
+                Q0=>CASr, F1=>N_128, Q1=>CASr2);
+    SLICE_76I: SLICE_76
+      port map (D1=>Din_c_0, B1=>Din_c_5, D0=>MAin_c_0, C0=>CmdEnable16_4, 
+                B0=>Din_c_1, A0=>Din_c_3, M1=>Din_c_5, M0=>Din_c_4, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
+                F1=>CmdEnable16_4, Q1=>Bank_5);
+    SLICE_77I: SLICE_77
+      port map (D1=>Din_c_4, A1=>Din_c_7, D0=>Din_c_6, C0=>MAin_c_1, 
+                B0=>CmdEnable16_1, A0=>Din_c_2, M1=>Din_c_7, M0=>Din_c_6, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
+                F1=>CmdEnable16_1, Q1=>Bank_7);
+    SLICE_78I: SLICE_78
+      port map (D1=>Din_c_3, B1=>Din_c_5, D0=>MAin_c_1, C0=>N_43, B0=>Din_c_6, 
+                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
+                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
+    SLICE_79I: SLICE_79
+      port map (D1=>CASr3, B1=>CASr2, A1=>Ready, D0=>CO0, C0=>S_1, 
+                B0=>m6_0_a2_2, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
+                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
+    SLICE_80I: SLICE_80
+      port map (D1=>CASr2, B1=>CASr3, D0=>FWEr, C0=>CO0, B0=>g4_0_0_0, 
+                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
+    SLICE_81I: SLICE_81
+      port map (D1=>FS_13, C1=>FS_14, B1=>FS_15, A1=>FS_17, D0=>FS_13, 
+                C0=>FS_17, B0=>FS_15, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
+                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
+                Q1=>FWEr_fast);
+    SLICE_82I: SLICE_82
+      port map (D1=>Din_c_3, C1=>N_128, B1=>CmdLEDEN, A1=>Din_c_5, 
+                D0=>XOR8MEG18, C0=>Din_c_3, B0=>N_128, A0=>Din_c_5, M0=>CASr2, 
+                CLK=>RCLK_c, F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
+    SLICE_83I: SLICE_83
+      port map (C1=>IS_1, B1=>IS_3, A1=>IS_2, C0=>IS_1, B0=>IS_0, A0=>IS_2, 
+                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
+    SLICE_84I: SLICE_84
+      port map (D1=>FS_6, C1=>FS_10, B1=>FS_11, A1=>FS_8, D0=>FS_7, C0=>FS_10, 
+                B0=>FS_1, A0=>FS_6, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
+    SLICE_85I: SLICE_85
+      port map (D1=>Din_c_4, C1=>Din_c_0, B1=>Din_c_1, A1=>Din_c_7, 
+                D0=>Din_c_5, C0=>Din_c_4, B0=>Din_c_6, A0=>Din_c_7, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
+                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
+    SLICE_86I: SLICE_86
+      port map (D1=>nRowColSel, A1=>MAin_c_9, D0=>nRowColSel, C0=>RowA_9, 
+                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
+    SLICE_87I: SLICE_87
+      port map (D1=>UFMSDI_ens2_i_a0, B1=>N_151, A1=>CmdUFMSDI, D0=>N_151, 
+                C0=>FS_9, B0=>FS_11, A0=>FS_4, F0=>N_137_8, 
+                F1=>UFMSDI_r_xx_mm_1);
+    SLICE_88I: SLICE_88
+      port map (D1=>MAin_c_2, C1=>nFWE_c, B1=>MAin_c_3, C0=>nFWE_c, 
+                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
+                Q1=>RowA_7);
+    SLICE_89I: SLICE_89
+      port map (D1=>nRowColSel, C1=>MAin_c_9, D0=>nRowColSel, B0=>MAin_c_8, 
+                A0=>RowA_8, F0=>RA_c_8, F1=>RDQMH_c);
+    SLICE_90I: SLICE_90
+      port map (D1=>MAin_c_0, C1=>MAin_c_1, B1=>N_147, D0=>MAin_c_0, 
+                B0=>RowA_0, A0=>nRowColSel, F0=>RA_c_0, F1=>un1_CMDWR);
+    SLICE_91I: SLICE_91
+      port map (D1=>MAin_c_7, C1=>nRowColSel, A1=>RowA_7, D0=>RowA_1, 
+                C0=>nRowColSel, B0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
+    SLICE_92I: SLICE_92
+      port map (D1=>RowA_6, C1=>nRowColSel, A1=>MAin_c_6, D0=>MAin_c_2, 
+                C0=>nRowColSel, B0=>RowA_2, F0=>RA_c_2, F1=>RA_c_6);
+    SLICE_93I: SLICE_93
+      port map (C1=>MAin_c_5, B1=>RowA_5, A1=>nRowColSel, D0=>MAin_c_3, 
+                B0=>nRowColSel, A0=>RowA_3, F0=>RA_c_3, F1=>RA_c_5);
+    SLICE_94I: SLICE_94
+      port map (B1=>N_155, A1=>Ready, C0=>S_1, A0=>Ready, M0=>IS_0, 
+                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
+                Q0=>RA_c_10, F1=>N_159_i);
+    RD_0_I: RD_0_B
+      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
+    Dout_0_I: Dout_0_B
+      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
+    PHI2I: PHI2B
+      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
+    UFMSDOI: UFMSDOB
+      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
+    UFMSDII: UFMSDIB
+      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
+    UFMCLKI: UFMCLKB
+      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
+    nUFMCSI: nUFMCSB
+      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
+    RDQMLI: RDQMLB
+      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
+    RDQMHI: RDQMHB
+      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
+    nRCASI: nRCASB
+      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
+    nRRASI: nRRASB
+      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
+    nRWEI: nRWEB
+      port map (PADDO=>nRWE_c, nRWES=>nRWE);
+    RCKEI: RCKEB
+      port map (PADDO=>RCKE_c, RCKES=>RCKE);
+    RCLKI: RCLKB
+      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
+    nRCSI: nRCSB
+      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
+    RD_7_I: RD_7_B
+      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
+    RD_6_I: RD_6_B
+      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
+    RD_5_I: RD_5_B
+      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
+    RD_4_I: RD_4_B
+      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
+    RD_3_I: RD_3_B
+      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
+    RD_2_I: RD_2_B
+      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
+    RD_1_I0: RD_1_B
+      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
+    RA_11_I: RA_11_B
+      port map (PADDO=>RA_c_11, RA11=>RA(11));
+    RA_10_I: RA_10_B
+      port map (PADDO=>RA_c_10, RA10=>RA(10));
+    RA_9_I: RA_9_B
+      port map (PADDO=>RA_c_9, RA9=>RA(9));
+    RA_8_I: RA_8_B
+      port map (PADDO=>RA_c_8, RA8=>RA(8));
+    RA_7_I: RA_7_B
+      port map (PADDO=>RA_c_7, RA7=>RA(7));
+    RA_6_I: RA_6_B
+      port map (PADDO=>RA_c_6, RA6=>RA(6));
+    RA_5_I: RA_5_B
+      port map (PADDO=>RA_c_5, RA5=>RA(5));
+    RA_4_I: RA_4_B
+      port map (PADDO=>RA_c_4, RA4=>RA(4));
+    RA_3_I: RA_3_B
+      port map (PADDO=>RA_c_3, RA3=>RA(3));
+    RA_2_I: RA_2_B
+      port map (PADDO=>RA_c_2, RA2=>RA(2));
+    RA_1_I: RA_1_B
+      port map (PADDO=>RA_c_1, RA1=>RA(1));
+    RA_0_I: RA_0_B
+      port map (PADDO=>RA_c_0, RA0=>RA(0));
+    RBA_1_I: RBA_1_B
+      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
+    RBA_0_I: RBA_0_B
+      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
+    LEDI: LEDB
+      port map (PADDO=>LED_c, LEDS=>LED);
+    nFWEI: nFWEB
+      port map (PADDI=>nFWE_c, nFWES=>nFWE);
+    nCRASI: nCRASB
+      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
+    nCCASI: nCCASB
+      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
+    Dout_7_I: Dout_7_B
+      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
+    Dout_6_I: Dout_6_B
+      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
+    Dout_5_I: Dout_5_B
+      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
+    Dout_4_I: Dout_4_B
+      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
+    Dout_3_I: Dout_3_B
+      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
+    Dout_2_I: Dout_2_B
+      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
+    Dout_1_I: Dout_1_B
+      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
+    Din_7_I: Din_7_B
+      port map (PADDI=>Din_c_7, Din7=>Din(7));
+    Din_6_I: Din_6_B
+      port map (PADDI=>Din_c_6, Din6=>Din(6));
+    Din_5_I: Din_5_B
+      port map (PADDI=>Din_c_5, Din5=>Din(5));
+    Din_4_I: Din_4_B
+      port map (PADDI=>Din_c_4, Din4=>Din(4));
+    Din_3_I: Din_3_B
+      port map (PADDI=>Din_c_3, Din3=>Din(3));
+    Din_2_I: Din_2_B
+      port map (PADDI=>Din_c_2, Din2=>Din(2));
+    Din_1_I: Din_1_B
+      port map (PADDI=>Din_c_1, Din1=>Din(1));
+    Din_0_I: Din_0_B
+      port map (PADDI=>Din_c_0, Din0=>Din(0));
+    CROW_1_I: CROW_1_B
+      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
+    CROW_0_I: CROW_0_B
+      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
+    MAin_9_I: MAin_9_B
+      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
+    MAin_8_I: MAin_8_B
+      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
+    MAin_7_I: MAin_7_B
+      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
+    MAin_6_I: MAin_6_B
+      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
+    MAin_5_I: MAin_5_B
+      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
+    MAin_4_I: MAin_4_B
+      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
+    MAin_3_I: MAin_3_B
+      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
+    MAin_2_I: MAin_2_B
+      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
+    MAin_1_I: MAin_1_B
+      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
+    MAin_0_I: MAin_0_B
+      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
+    VHI_INST: VHI
+      port map (Z=>VCCI);
+    PUR_INST: PUR
+      port map (PUR=>VCCI);
+    GSR_INST: GSR
+      port map (GSR=>VCCI);
+    VLO_INST: VLO
+      port map (Z=>GNDI_TSALL);
+    TSALL_INST: TSALL
+      port map (TSALL=>GNDI_TSALL);
+  end Structure;
+
+
+
+  library IEEE, vital2000, MACHXO;
+  configuration Structure_CON of RAM2GS is
+    for Structure
+    end for;
+  end Structure_CON;
+
+
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf
index 840a29c..6f63be3 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf
@@ -1,2922 +1,2922 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:49 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1\/SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_")
-    (INSTANCE RD\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_")
-    (INSTANCE Dout\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2")
-    (INSTANCE PHI2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2) (1250:1250:1250))
-      (WIDTH (negedge PHI2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDO")
-    (INSTANCE UFMSDO_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDO) (1250:1250:1250))
-      (WIDTH (negedge UFMSDO) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI")
-    (INSTANCE UFMSDI_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK")
-    (INSTANCE UFMCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCS")
-    (INSTANCE nUFMCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQML")
-    (INSTANCE RDQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMH")
-    (INSTANCE RDQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCAS")
-    (INSTANCE nRCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRAS")
-    (INSTANCE nRRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE")
-    (INSTANCE RCKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLK")
-    (INSTANCE RCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLK) (1250:1250:1250))
-      (WIDTH (negedge RCLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCS")
-    (INSTANCE nRCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_")
-    (INSTANCE RD\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_")
-    (INSTANCE RD\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_")
-    (INSTANCE RD\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_")
-    (INSTANCE RD\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_")
-    (INSTANCE RD\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_")
-    (INSTANCE RD\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_")
-    (INSTANCE RD\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_")
-    (INSTANCE RBA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_")
-    (INSTANCE RBA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LED")
-    (INSTANCE LED_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWE")
-    (INSTANCE nFWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWE) (1250:1250:1250))
-      (WIDTH (negedge nFWE) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRAS")
-    (INSTANCE nCRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRAS) (1250:1250:1250))
-      (WIDTH (negedge nCRAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCAS")
-    (INSTANCE nCCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCAS) (1250:1250:1250))
-      (WIDTH (negedge nCCAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_")
-    (INSTANCE Dout\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_")
-    (INSTANCE Dout\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_")
-    (INSTANCE Dout\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_")
-    (INSTANCE Dout\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_")
-    (INSTANCE Dout\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_")
-    (INSTANCE Dout\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_")
-    (INSTANCE Dout\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_")
-    (INSTANCE Din\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_")
-    (INSTANCE Din\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_")
-    (INSTANCE Din\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_")
-    (INSTANCE Din\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_")
-    (INSTANCE Din\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_")
-    (INSTANCE Din\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_")
-    (INSTANCE Din\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_")
-    (INSTANCE Din\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_")
-    (INSTANCE CROW\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_")
-    (INSTANCE CROW\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_")
-    (INSTANCE MAin\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_")
-    (INSTANCE MAin\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_")
-    (INSTANCE MAin\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_")
-    (INSTANCE MAin\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_")
-    (INSTANCE MAin\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_")
-    (INSTANCE MAin\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_")
-    (INSTANCE MAin\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_")
-    (INSTANCE MAin\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_")
-    (INSTANCE MAin\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_")
-    (INSTANCE MAin\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (1232:1375:1519)(1232:1375:1519))
-        (INTERCONNECT SLICE_0/Q1 SLICE_84/B0 (1203:1339:1475)(1203:1339:1475))
-        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_0/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_0/Q0 SLICE_69/D1 (588:652:716)(588:652:716))
-        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (730:1041:1353)(730:1041:1353))
-        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/A1 (1146:1276:1406)(1146:1276:1406))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (1151:1263:1376)(1151:1263:1376))
-        (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (908:1011:1114)(908:1011:1114))
-        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/A1 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_2/Q0 SLICE_81/C1 (1118:1249:1380)(1118:1249:1380))
-        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/D1 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/D0 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1663:1816:1970)(1663:1816:1970))
-        (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (1260:1384:1509)(1260:1384:1509))
-        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/D1 (1001:1094:1188)(1001:1094:1188))
-        (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (1316:1448:1580)(1316:1448:1580))
-        (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (1733:1895:2058)(1733:1895:2058))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (1245:1393:1541)(1245:1393:1541))
-        (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (1648:1825:2002)(1648:1825:2002))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1131:1266:1402)(1131:1266:1402))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/C0 (1131:1266:1402)(1131:1266:1402))
-        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (1652:1794:1936)(1652:1794:1936))
-        (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_5/Q0 SLICE_84/A1 (1663:1816:1970)(1663:1816:1970))
-        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (1844:2015:2186)(1844:2015:2186))
-        (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/D1 (595:663:731)(595:663:731))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (864:963:1063)(864:963:1063))
-        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1497:1620:1743)(1497:1620:1743))
-        (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (603:667:731)(603:667:731))
-        (INTERCONNECT SLICE_7/Q1 SLICE_69/B1 (918:1020:1123)(918:1020:1123))
-        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7/Q0 SLICE_72/D0 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1232:1375:1519)(1232:1375:1519))
-        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (1675:1841:2008)(1675:1841:2008))
-        (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (1561:1715:1869)(1561:1715:1869))
-        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8/Q0 SLICE_68/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_8/Q0 SLICE_69/A1 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_85/F1 SLICE_9/C1 (1087:1218:1349)(1087:1218:1349))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/B1 (1843:2032:2222)(1843:2032:2222))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1203:1325:1448)(1203:1325:1448))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (1683:1853:2023)(1683:1853:2023))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (1528:1679:1830)(1528:1679:1830))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D1 (2744:2982:3221)(2744:2982:3221))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D0 (2744:2982:3221)(2744:2982:3221))
-        (INTERCONNECT SLICE_70/F1 SLICE_9/A1 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/A1 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/A0 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (882:978:1075)(882:978:1075))
-        (INTERCONNECT SLICE_70/F1 SLICE_70/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_70/F1 SLICE_90/B1 (1317:1447:1578)(1317:1447:1578))
-        (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634))
-        (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (261:290:320)(261:290:320))
-        (INTERCONNECT SLICE_14/F1 SLICE_9/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_14/F1 SLICE_14/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (559:618:678)(559:618:678))
-        (INTERCONNECT SLICE_70/F0 SLICE_9/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2182:2416:2650)(2182:2416:2650))
-        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2731:3325:3919)(2731:3325:3919))
-        (INTERCONNECT SLICE_77/F0 SLICE_14/D1 (564:632:700)(564:632:700))
-        (INTERCONNECT SLICE_76/F0 SLICE_14/C1 (1530:1676:1822)(1530:1676:1822))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (1225:1351:1478)(1225:1351:1478))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1525:1685:1846)(1525:1685:1846))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/B0 (1540:1705:1870)(1540:1705:1870))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (1879:2062:2246)(1879:2062:2246))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/C0 (1373:1516:1660)(1373:1516:1660))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1225:1351:1478)(1225:1351:1478))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (1784:1959:2134)(1784:1959:2134))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (1541:1706:1872)(1541:1706:1872))
-        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_14/Q0 SLICE_20/B0 (832:929:1026)(832:929:1026))
-        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/D1 (956:1070:1185)(956:1070:1185))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (2110:2331:2552)(2110:2331:2552))
-        (INTERCONNECT SLICE_51/Q1 SLICE_42/C1 (2657:2925:3193)(2657:2925:3193))
-        (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (2482:2728:2974)(2482:2728:2974))
-        (INTERCONNECT SLICE_51/Q1 SLICE_43/C1 (2365:2598:2832)(2365:2598:2832))
-        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (2110:2331:2552)(2110:2331:2552))
-        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (2620:2864:3109)(2620:2864:3109))
-        (INTERCONNECT SLICE_51/Q1 SLICE_61/A1 (2054:2267:2480)(2054:2267:2480))
-        (INTERCONNECT SLICE_51/Q1 SLICE_62/D1 (1793:1977:2161)(1793:1977:2161))
-        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (2210:2424:2639)(2210:2424:2639))
-        (INTERCONNECT SLICE_51/Q1 SLICE_73/B1 (895:1001:1108)(895:1001:1108))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (763:846:930)(763:846:930))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (763:846:930)(763:846:930))
-        (INTERCONNECT SLICE_50/Q0 SLICE_41/C1 (1581:1730:1879)(1581:1730:1879))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (1769:1942:2115)(1769:1942:2115))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (2019:2202:2385)(2019:2202:2385))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (2019:2202:2385)(2019:2202:2385))
-        (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (1454:1588:1723)(1454:1588:1723))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C1 (757:844:932)(757:844:932))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C0 (757:844:932)(757:844:932))
-        (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2026:2210:2394)(2026:2210:2394))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (878:975:1072)(878:975:1072))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_19/Q0 SLICE_41/B1 (938:1041:1144)(938:1041:1144))
-        (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1181:1293:1406)(1181:1293:1406))
-        (INTERCONNECT SLICE_19/Q0 SLICE_63/A0 (892:988:1084)(892:988:1084))
-        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1362:1496:1631)(1362:1496:1631))
-        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1362:1496:1631)(1362:1496:1631))
-        (INTERCONNECT SLICE_19/Q0 SLICE_73/A1 (1316:1443:1571)(1316:1443:1571))
-        (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (1047:1143:1239)(1047:1143:1239))
-        (INTERCONNECT SLICE_19/Q0 SLICE_80/C0 (718:795:873)(718:795:873))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/A1 (1286:1409:1533)(1286:1409:1533))
-        (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (825:914:1004)(825:914:1004))
-        (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (1424:1556:1689)(1424:1556:1689))
-        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/F1 SLICE_43/A0 (849:948:1048)(849:948:1048))
-        (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_20/Q0 SLICE_20/A1 (810:899:989)(810:899:989))
-        (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_20/Q0 SLICE_67/D0 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_90/F1 SLICE_20/C0 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75/F1 SLICE_21/D1 (321:350:380)(321:350:380))
-        (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (640:708:776)(640:708:776))
-        (INTERCONNECT SLICE_75/F1 SLICE_67/D1 (1047:1139:1231)(1047:1139:1231))
-        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (476:524:573)(476:524:573))
-        (INTERCONNECT SLICE_75/F1 SLICE_82/C1 (476:524:573)(476:524:573))
-        (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (901:997:1094)(901:997:1094))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/B1 (1546:1711:1877)(1546:1711:1877))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2468:2685:2903)(2468:2685:2903))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/B1 (1949:2143:2338)(1949:2143:2338))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/B0 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B1 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1962:2156:2351)(1962:2156:2351))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2795:3059:3324)(2795:3059:3324))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A1 (1500:1658:1817)(1500:1658:1817))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A0 (1500:1658:1817)(1500:1658:1817))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/D0 (1944:2137:2330)(1944:2137:2330))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/A1 (1398:1552:1707)(1398:1552:1707))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/A1 (988:1113:1238)(988:1113:1238))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/C1 (1556:1731:1906)(1556:1731:1906))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (712:804:897)(712:804:897))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (988:1113:1238)(988:1113:1238))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/D1 (709:801:894)(709:801:894))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/D1 (1418:1575:1733)(1418:1575:1733))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/C0 (1277:1418:1560)(1277:1418:1560))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (712:804:897)(712:804:897))
-        (INTERCONNECT SLICE_75/F0 SLICE_21/D0 (245:274:304)(245:274:304))
-        (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (853:947:1042)(853:947:1042))
-        (INTERCONNECT SLICE_82/F1 SLICE_21/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_33/Q0 SLICE_21/A0 (1514:1694:1875)(1514:1694:1875))
-        (INTERCONNECT SLICE_33/Q0 SLICE_33/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (1674:1856:2038)(1674:1856:2038))
-        (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F0 SLICE_21/CE (1285:1433:1581)(1285:1433:1581))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (921:1020:1119)(921:1020:1119))
-        (INTERCONNECT SLICE_67/F0 SLICE_57/CE (1696:1875:2055)(1696:1875:2055))
-        (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_67/F0 SLICE_82/D0 (986:1100:1215)(986:1100:1215))
-        (INTERCONNECT SLICE_21/Q0 SLICE_33/A0 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_21/Q0 SLICE_82/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1682:1846:2010)(1682:1846:2010))
-        (INTERCONNECT SLICE_32/Q0 SLICE_22/C1 (1201:1313:1426)(1201:1313:1426))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/A1 (854:945:1036)(854:945:1036))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (575:636:697)(575:636:697))
-        (INTERCONNECT SLICE_32/Q0 SLICE_33/C0 (1611:1753:1895)(1611:1753:1895))
-        (INTERCONNECT SLICE_32/Q0 SLICE_43/D1 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_32/Q0 SLICE_43/D0 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_32/Q0 SLICE_44/C1 (2035:2209:2383)(2035:2209:2383))
-        (INTERCONNECT SLICE_32/Q0 SLICE_51/B1 (1769:1941:2114)(1769:1941:2114))
-        (INTERCONNECT SLICE_32/Q0 SLICE_52/B1 (1771:1932:2094)(1771:1932:2094))
-        (INTERCONNECT SLICE_32/Q0 SLICE_58/C1 (740:818:897)(740:818:897))
-        (INTERCONNECT SLICE_32/Q0 SLICE_58/C0 (740:818:897)(740:818:897))
-        (INTERCONNECT SLICE_32/Q0 SLICE_64/C1 (784:866:948)(784:866:948))
-        (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (1746:1903:2061)(1746:1903:2061))
-        (INTERCONNECT SLICE_32/Q0 SLICE_66/B1 (1777:1952:2127)(1777:1952:2127))
-        (INTERCONNECT SLICE_32/Q0 SLICE_66/B0 (1777:1952:2127)(1777:1952:2127))
-        (INTERCONNECT SLICE_32/Q0 SLICE_73/D1 (1477:1603:1729)(1477:1603:1729))
-        (INTERCONNECT SLICE_43/Q1 SLICE_22/B1 (1302:1432:1563)(1302:1432:1563))
-        (INTERCONNECT SLICE_43/Q1 SLICE_52/C1 (1103:1234:1365)(1103:1234:1365))
-        (INTERCONNECT SLICE_41/Q1 SLICE_22/A1 (1260:1384:1509)(1260:1384:1509))
-        (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (544:603:663)(544:603:663))
-        (INTERCONNECT SLICE_41/Q1 SLICE_52/D1 (991:1084:1177)(991:1084:1177))
-        (INTERCONNECT SLICE_82/F0 SLICE_22/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22/F1 SLICE_68/C0 (1133:1244:1356)(1133:1244:1356))
-        (INTERCONNECT SLICE_22/F1 SLICE_69/C0 (1133:1244:1356)(1133:1244:1356))
-        (INTERCONNECT SLICE_78/F1 SLICE_26/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_26/Q0 SLICE_58/B0 (899:1000:1102)(899:1000:1102))
-        (INTERCONNECT SLICE_76/F1 SLICE_26/A1 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_58/Q0 SLICE_39/C0 (1936:2106:2276)(1936:2106:2276))
-        (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/F1 SLICE_29/D1 (584:647:710)(584:647:710))
-        (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (726:803:880)(726:803:880))
-        (INTERCONNECT SLICE_29/Q0 SLICE_29/D0 (571:629:687)(571:629:687))
-        (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (643:708:773)(643:708:773))
-        (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (643:708:773)(643:708:773))
-        (INTERCONNECT SLICE_29/Q0 SLICE_31/C0 (798:882:966)(798:882:966))
-        (INTERCONNECT SLICE_29/Q0 SLICE_42/D1 (1534:1657:1781)(1534:1657:1781))
-        (INTERCONNECT SLICE_29/Q0 SLICE_61/D0 (932:1031:1131)(932:1031:1131))
-        (INTERCONNECT SLICE_29/Q0 SLICE_83/B0 (2655:2875:3095)(2655:2875:3095))
-        (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (1300:1448:1596)(1300:1448:1596))
-        (INTERCONNECT SLICE_83/F1 SLICE_29/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_83/F1 SLICE_61/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_73/F1 SLICE_29/A1 (1297:1422:1547)(1297:1422:1547))
-        (INTERCONNECT SLICE_73/F1 SLICE_29/A0 (1297:1422:1547)(1297:1422:1547))
-        (INTERCONNECT SLICE_73/F1 SLICE_59/D1 (1109:1203:1297)(1109:1203:1297))
-        (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1062:1179:1297)(1062:1179:1297))
-        (INTERCONNECT SLICE_73/F1 SLICE_73/C0 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_73/F1 SLICE_94/B1 (871:967:1064)(871:967:1064))
-        (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (2198:2404:2610)(2198:2404:2610))
-        (INTERCONNECT SLICE_43/Q0 SLICE_41/C0 (733:810:888)(733:810:888))
-        (INTERCONNECT SLICE_43/Q0 SLICE_43/B1 (886:982:1079)(886:982:1079))
-        (INTERCONNECT SLICE_43/Q0 SLICE_43/C0 (733:810:888)(733:810:888))
-        (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (1490:1629:1769)(1490:1629:1769))
-        (INTERCONNECT SLICE_43/Q0 SLICE_59/B1 (2511:2758:3006)(2511:2758:3006))
-        (INTERCONNECT SLICE_43/Q0 SLICE_61/B1 (2087:2299:2511)(2087:2299:2511))
-        (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2087:2299:2511)(2087:2299:2511))
-        (INTERCONNECT SLICE_43/Q0 SLICE_63/B1 (1805:1983:2161)(1805:1983:2161))
-        (INTERCONNECT SLICE_43/Q0 SLICE_63/B0 (1805:1983:2161)(1805:1983:2161))
-        (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (948:1049:1150)(948:1049:1150))
-        (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1199:1330:1461)(1199:1330:1461))
-        (INTERCONNECT SLICE_43/Q0 SLICE_79/A1 (894:993:1093)(894:993:1093))
-        (INTERCONNECT SLICE_43/Q0 SLICE_94/A1 (907:1003:1099)(907:1003:1099))
-        (INTERCONNECT SLICE_43/Q0 SLICE_94/A0 (907:1003:1099)(907:1003:1099))
-        (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_30/Q0 SLICE_30/B1 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (885:983:1081)(885:983:1081))
-        (INTERCONNECT SLICE_30/Q0 SLICE_42/A1 (1378:1503:1629)(1378:1503:1629))
-        (INTERCONNECT SLICE_30/Q0 SLICE_83/C1 (1179:1290:1402)(1179:1290:1402))
-        (INTERCONNECT SLICE_30/Q0 SLICE_83/C0 (1179:1290:1402)(1179:1290:1402))
-        (INTERCONNECT SLICE_30/Q1 SLICE_30/A1 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (563:621:680)(563:621:680))
-        (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (563:621:680)(563:621:680))
-        (INTERCONNECT SLICE_30/Q1 SLICE_42/B1 (1424:1556:1689)(1424:1556:1689))
-        (INTERCONNECT SLICE_30/Q1 SLICE_83/A1 (1293:1417:1541)(1293:1417:1541))
-        (INTERCONNECT SLICE_30/Q1 SLICE_83/A0 (1293:1417:1541)(1293:1417:1541))
-        (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94/F1 SLICE_30/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_94/F1 SLICE_31/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (575:639:703)(575:639:703))
-        (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1352:1480:1609)(1352:1480:1609))
-        (INTERCONNECT SLICE_72/F1 SLICE_32/C1 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (291:320:350)(291:320:350))
-        (INTERCONNECT SLICE_72/F1 SLICE_64/B1 (929:1030:1132)(929:1030:1132))
-        (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (446:494:543)(446:494:543))
-        (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (879:985:1092)(879:985:1092))
-        (INTERCONNECT SLICE_74/F0 SLICE_32/B0 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_33/D1 (2857:3462:4068)(2857:3462:4068))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (3532:4217:4903)(3532:4217:4903))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (2293:2830:3368)(2293:2830:3368))
-        (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1365:1507:1650)(1365:1507:1650))
-        (INTERCONNECT SLICE_78/Q0 SLICE_60/A0 (1681:1846:2012)(1681:1846:2012))
-        (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1239:1386:1534)(1239:1386:1534))
-        (INTERCONNECT SLICE_78/Q0 SLICE_79/A0 (1239:1386:1534)(1239:1386:1534))
-        (INTERCONNECT UFMSDO_I/PADDI SLICE_33/D0 (702:793:885)(702:793:885))
-        (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (1105:1225:1346)(1105:1225:1346))
-        (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69/F0 SLICE_33/CE (939:1052:1165)(939:1052:1165))
-        (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_85/F0 SLICE_39/D1 (1514:1646:1779)(1514:1646:1779))
-        (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_57/Q0 SLICE_39/A1 (2147:2339:2531)(2147:2339:2531))
-        (INTERCONNECT SLICE_57/Q0 SLICE_39/A0 (2147:2339:2531)(2147:2339:2531))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/D0 (2053:2245:2437)(2053:2245:2437))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (3194:3483:3773)(3194:3483:3773))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/B1 (1519:1680:1842)(1519:1680:1842))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/D0 (2081:2276:2472)(2081:2276:2472))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2388:2619:2851)(2388:2619:2851))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/B0 (2396:2630:2864)(2396:2630:2864))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/B0 (2799:3062:3325)(2799:3062:3325))
-        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1313:1442:1571)(1313:1442:1571))
-        (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1850:2013:2177)(1850:2013:2177))
-        (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (559:618:678)(559:618:678))
-        (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (1842:2003:2164)(1842:2003:2164))
-        (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1447:1581:1716)(1447:1581:1716))
-        (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (1767:1931:2095)(1767:1931:2095))
-        (INTERCONNECT SLICE_75/Q1 SLICE_41/D1 (960:1076:1193)(960:1076:1193))
-        (INTERCONNECT SLICE_75/Q1 SLICE_60/B1 (1967:2185:2404)(1967:2185:2404))
-        (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1275:1430:1585)(1275:1430:1585))
-        (INTERCONNECT SLICE_75/Q1 SLICE_80/D1 (1370:1516:1662)(1370:1516:1662))
-        (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (1780:1956:2132)(1780:1956:2132))
-        (INTERCONNECT SLICE_81/Q1 SLICE_41/A1 (2097:2301:2505)(2097:2301:2505))
-        (INTERCONNECT SLICE_81/Q1 SLICE_60/D1 (2924:3195:3466)(2924:3195:3466))
-        (INTERCONNECT SLICE_43/F1 SLICE_41/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_41/F1 SLICE_41/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1342:1484:1626)(1342:1484:1626))
-        (INTERCONNECT SLICE_41/Q0 SLICE_42/D0 (1352:1480:1609)(1352:1480:1609))
-        (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_44/Q1 SLICE_42/B0 (1293:1424:1555)(1293:1424:1555))
-        (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (2091:2277:2464)(2091:2277:2464))
-        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 SLICE_61/C1 (1543:1684:1825)(1543:1684:1825))
-        (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/A1 (2060:2242:2425)(2060:2242:2425))
-        (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (1978:2217:2456)(1978:2217:2456))
-        (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/D0 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_50/F0 SLICE_43/A1 (1270:1395:1520)(1270:1395:1520))
-        (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (16:16:16)(16:16:16))
-        (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (1001:1094:1188)(1001:1094:1188))
-        (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1156:1268:1381)(1156:1268:1381))
-        (INTERCONNECT SLICE_83/F0 SLICE_43/B0 (1255:1408:1561)(1255:1408:1561))
-        (INTERCONNECT SLICE_83/F0 SLICE_44/A1 (1612:1787:1962)(1612:1787:1962))
-        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/F1 SLICE_44/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1375:1502:1629)(1375:1502:1629))
-        (INTERCONNECT SLICE_72/F0 SLICE_51/C1 (1126:1237:1348)(1126:1237:1348))
-        (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_66/F0 SLICE_66/C1 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_51/Q0 SLICE_51/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1548:1774:2000)(1548:1774:2000))
-        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (1409:1541:1674)(1409:1541:1674))
-        (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_52/F1 SLICE_51/A0 (1157:1286:1415)(1157:1286:1415))
-        (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_52/F1 SLICE_64/D0 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/D0 (1207:1330:1453)(1207:1330:1453))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (1949:2146:2344)(1949:2146:2344))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/B1 (1914:2103:2292)(1914:2103:2292))
-        (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (1997:2204:2411)(1997:2204:2411))
-        (INTERCONNECT SLICE_63/Q0 SLICE_86/D1 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63/Q0 SLICE_86/D0 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (1451:1592:1734)(1451:1592:1734))
-        (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT SLICE_63/Q0 SLICE_91/C1 (2426:2645:2865)(2426:2645:2865))
-        (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (2426:2645:2865)(2426:2645:2865))
-        (INTERCONNECT SLICE_63/Q0 SLICE_92/C1 (1898:2093:2289)(1898:2093:2289))
-        (INTERCONNECT SLICE_63/Q0 SLICE_92/C0 (1898:2093:2289)(1898:2093:2289))
-        (INTERCONNECT SLICE_63/Q0 SLICE_93/A1 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2176:2385:2595)(2176:2385:2595))
-        (INTERCONNECT SLICE_67/Q0 SLICE_55/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2322:2541:2761)(2322:2541:2761))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/A1 (1473:1628:1784)(1473:1628:1784))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1635:1791:1948)(1635:1791:1948))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/D1 (1628:1783:1939)(1628:1783:1939))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/D1 (1628:1783:1939)(1628:1783:1939))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/C0 (2072:2281:2490)(2072:2281:2490))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (2787:3031:3276)(2787:3031:3276))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2787:3031:3276)(2787:3031:3276))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (2225:2440:2655)(2225:2440:2655))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (1818:2004:2190)(1818:2004:2190))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (1818:2004:2190)(1818:2004:2190))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (2377:2592:2807)(2377:2592:2807))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1564:1720:1877)(1564:1720:1877))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_88/A0 (1798:1981:2164)(1798:1981:2164))
-        (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (2042:2305:2568)(2042:2305:2568))
-        (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (2630:2955:3280)(2630:2955:3280))
-        (INTERCONNECT SLICE_77/Q1 SLICE_56/D1 (1260:1386:1513)(1260:1386:1513))
-        (INTERCONNECT SLICE_77/Q0 SLICE_56/C1 (1126:1237:1348)(1126:1237:1348))
-        (INTERCONNECT SLICE_76/Q1 SLICE_56/B1 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_71/Q0 SLICE_56/A1 (1332:1457:1583)(1332:1457:1583))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2232:2447:2663)(2232:2447:2663))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/D1 (1515:1665:1815)(1515:1665:1815))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/A1 (2604:2844:3085)(2604:2844:3085))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (2642:2887:3132)(2642:2887:3132))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A1 (1381:1533:1686)(1381:1533:1686))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A0 (1381:1533:1686)(1381:1533:1686))
-        (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/C1 (1277:1418:1559)(1277:1418:1559))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (1839:2026:2214)(1839:2026:2214))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (2242:2458:2675)(2242:2458:2675))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/D1 (1532:1683:1835)(1532:1683:1835))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (3049:3329:3610)(3049:3329:3610))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/C1 (1566:1741:1917)(1566:1741:1917))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1437:1597:1758)(1437:1597:1758))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1129:1252:1375)(1129:1252:1375))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1411:1566:1722)(1411:1566:1722))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1384:1536:1689)(1384:1536:1689))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1673:1860:2047)(1673:1860:2047))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (1429:1587:1745)(1429:1587:1745))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (710:802:894)(710:802:894))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (1420:1577:1734)(1420:1577:1734))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1933:2113:2294)(1933:2113:2294))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1113:1234:1355)(1113:1234:1355))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1025:1155:1286)(1025:1155:1286))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (2233:2448:2664)(2233:2448:2664))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/B1 (1025:1155:1286)(1025:1155:1286))
-        (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_80/F0 SLICE_59/B0 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_62/F1 SLICE_59/A0 (1751:1905:2060)(1751:1905:2060))
-        (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (1723:1947:2172)(1723:1947:2172))
-        (INTERCONNECT SLICE_82/Q0 SLICE_60/A1 (1751:1905:2060)(1751:1905:2060))
-        (INTERCONNECT SLICE_82/Q0 SLICE_63/C1 (748:831:915)(748:831:915))
-        (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (996:1089:1183)(996:1089:1183))
-        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (908:1011:1114)(908:1011:1114))
-        (INTERCONNECT SLICE_94/F0 SLICE_60/D0 (1382:1514:1647)(1382:1514:1647))
-        (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT SLICE_78/Q1 SLICE_62/A1 (1348:1473:1599)(1348:1473:1599))
-        (INTERCONNECT SLICE_78/Q1 SLICE_80/A0 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/D0 (568:631:694)(568:631:694))
-        (INTERCONNECT SLICE_81/Q0 SLICE_62/B0 (1797:1958:2120)(1797:1958:2120))
-        (INTERCONNECT SLICE_81/Q0 SLICE_63/D1 (588:652:716)(588:652:716))
-        (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1395:1523:1651)(1395:1523:1651))
-        (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/Q0 SLICE_64/C0 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1990:2225:2460)(1990:2225:2460))
-        (INTERCONNECT SLICE_66/F1 SLICE_64/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q1 SLICE_66/D1 (1335:1476:1617)(1335:1476:1617))
-        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_81/F0 SLICE_74/D0 (261:290:320)(261:290:320))
-        (INTERCONNECT SLICE_74/F1 SLICE_66/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_66/Q0 SLICE_90/B0 (2100:2300:2500)(2100:2300:2500))
-        (INTERCONNECT SLICE_66/Q1 SLICE_91/D0 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (1219:1345:1472)(1219:1345:1472))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/A1 (1884:2070:2256)(1884:2070:2256))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/C1 (1794:1974:2155)(1794:1974:2155))
-        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (579:644:709)(579:644:709))
-        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (982:1076:1170)(982:1076:1170))
-        (INTERCONNECT SLICE_67/Q1 SLICE_93/B1 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT SLICE_87/F0 SLICE_68/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_87/F0 SLICE_69/D0 (572:636:700)(572:636:700))
-        (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_84/F0 SLICE_68/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_84/F0 SLICE_69/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_70/Q0 SLICE_70/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_70/Q1 SLICE_70/A1 (514:575:636)(514:575:636))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/D1 (1647:1811:1975)(1647:1811:1975))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/A1 (1876:2059:2243)(1876:2059:2243))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/C1 (1765:1936:2107)(1765:1936:2107))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (1917:2105:2293)(1917:2105:2293))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/D1 (2013:2194:2375)(2013:2194:2375))
-        (INTERCONNECT SLICE_88/F1 SLICE_71/D0 (564:632:700)(564:632:700))
-        (INTERCONNECT SLICE_71/Q1 SLICE_71/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (879:985:1092)(879:985:1092))
-        (INTERCONNECT SLICE_71/F1 SLICE_71/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_81/F1 SLICE_72/D1 (564:632:700)(564:632:700))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (1611:1765:1919)(1611:1765:1919))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/B1 (1926:2118:2310)(1926:2118:2310))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/D0 (2417:2628:2840)(2417:2628:2840))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (1115:1236:1357)(1115:1236:1357))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/D1 (1921:2099:2278)(1921:2099:2278))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/D0 (2324:2531:2739)(2324:2531:2739))
-        (INTERCONNECT SLICE_72/Q0 SLICE_92/B0 (1689:1848:2008)(1689:1848:2008))
-        (INTERCONNECT SLICE_72/Q1 SLICE_93/A0 (1735:1889:2044)(1735:1889:2044))
-        (INTERCONNECT SLICE_74/Q0 SLICE_87/A1 (833:932:1032)(833:932:1032))
-        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_79/F1 SLICE_79/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (1164:1346:1528)(1164:1346:1528))
-        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (1943:2141:2340)(1943:2141:2340))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A1 (2322:2546:2771)(2322:2546:2771))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (2322:2546:2771)(2322:2546:2771))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2208:2420:2632)(2208:2420:2632))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/B0 (1919:2110:2302)(1919:2110:2302))
-        (INTERCONNECT SLICE_80/Q0 SLICE_89/A0 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_80/Q1 SLICE_86/C0 (723:805:887)(723:805:887))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1514:1673:1833)(1514:1673:1833))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1514:1673:1833)(1514:1673:1833))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (1802:1985:2168)(1802:1985:2168))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (1802:1985:2168)(1802:1985:2168))
-        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (1635:1796:1957)(1635:1796:1957))
-        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (1635:1796:1957)(1635:1796:1957))
-        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2063:2303:2544)(2063:2303:2544))
-        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (1971:2209:2448)(1971:2209:2448))
-        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1748:1996:2245)(1748:1996:2245))
-        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
-        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (3364:3728:4093)(3364:3728:4093))
-        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (3364:3728:4093)(3364:3728:4093))
-        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1783:2025:2267)(1783:2025:2267))
-        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (3357:3721:4085)(3357:3721:4085))
-        (INTERCONNECT SLICE_88/Q0 SLICE_92/D1 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT SLICE_88/Q1 SLICE_91/A1 (837:931:1026)(837:931:1026))
-        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1932:2190:2449)(1932:2190:2449))
-        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1974:2209:2444)(1974:2209:2444))
-        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (2063:2303:2544)(2063:2303:2544))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2288:2578:2869)(2288:2578:2869))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (1418:1631:1845)(1418:1631:1845))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (1421:1631:1841)(1421:1631:1841))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:53:33 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1\/SLICE_65)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_")
+    (INSTANCE RD\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_")
+    (INSTANCE Dout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2")
+    (INSTANCE PHI2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2) (1250:1250:1250))
+      (WIDTH (negedge PHI2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDO")
+    (INSTANCE UFMSDO_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDO) (1250:1250:1250))
+      (WIDTH (negedge UFMSDO) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDI")
+    (INSTANCE UFMSDI_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLK")
+    (INSTANCE UFMCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCS")
+    (INSTANCE nUFMCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQML")
+    (INSTANCE RDQML_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMH")
+    (INSTANCE RDQMH_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCAS")
+    (INSTANCE nRCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRAS")
+    (INSTANCE nRRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE")
+    (INSTANCE nRWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKE")
+    (INSTANCE RCKE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLK")
+    (INSTANCE RCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLK) (1250:1250:1250))
+      (WIDTH (negedge RCLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCS")
+    (INSTANCE nRCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_")
+    (INSTANCE RD\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_")
+    (INSTANCE RD\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_")
+    (INSTANCE RD\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_")
+    (INSTANCE RD\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_")
+    (INSTANCE RD\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_")
+    (INSTANCE RD\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_")
+    (INSTANCE RD\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_")
+    (INSTANCE RA\[11\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_")
+    (INSTANCE RA\[10\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_")
+    (INSTANCE RA\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_")
+    (INSTANCE RA\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_")
+    (INSTANCE RA\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_")
+    (INSTANCE RA\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_")
+    (INSTANCE RA\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_")
+    (INSTANCE RA\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_")
+    (INSTANCE RA\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_")
+    (INSTANCE RA\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_")
+    (INSTANCE RA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_")
+    (INSTANCE RA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_")
+    (INSTANCE RBA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_")
+    (INSTANCE RBA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LED")
+    (INSTANCE LED_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWE")
+    (INSTANCE nFWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWE) (1250:1250:1250))
+      (WIDTH (negedge nFWE) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRAS")
+    (INSTANCE nCRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRAS) (1250:1250:1250))
+      (WIDTH (negedge nCRAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCAS")
+    (INSTANCE nCCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCAS) (1250:1250:1250))
+      (WIDTH (negedge nCCAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_")
+    (INSTANCE Dout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_")
+    (INSTANCE Dout\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_")
+    (INSTANCE Dout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_")
+    (INSTANCE Dout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_")
+    (INSTANCE Dout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_")
+    (INSTANCE Dout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_")
+    (INSTANCE Dout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_")
+    (INSTANCE Din\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_")
+    (INSTANCE Din\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_")
+    (INSTANCE Din\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_")
+    (INSTANCE Din\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_")
+    (INSTANCE Din\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_")
+    (INSTANCE Din\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_")
+    (INSTANCE Din\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_")
+    (INSTANCE Din\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_")
+    (INSTANCE CROW\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_")
+    (INSTANCE CROW\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_")
+    (INSTANCE MAin\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_")
+    (INSTANCE MAin\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_")
+    (INSTANCE MAin\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_")
+    (INSTANCE MAin\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_")
+    (INSTANCE MAin\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_")
+    (INSTANCE MAin\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_")
+    (INSTANCE MAin\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_")
+    (INSTANCE MAin\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_")
+    (INSTANCE MAin\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_")
+    (INSTANCE MAin\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (1232:1375:1519)(1232:1375:1519))
+        (INTERCONNECT SLICE_0/Q1 SLICE_84/B0 (1203:1339:1475)(1203:1339:1475))
+        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_0/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_0/Q0 SLICE_69/D1 (588:652:716)(588:652:716))
+        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (730:1041:1353)(730:1041:1353))
+        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/A1 (1146:1276:1406)(1146:1276:1406))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (1151:1263:1376)(1151:1263:1376))
+        (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (908:1011:1114)(908:1011:1114))
+        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_2/Q0 SLICE_74/A1 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_2/Q0 SLICE_81/C1 (1118:1249:1380)(1118:1249:1380))
+        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/D1 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/D0 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1663:1816:1970)(1663:1816:1970))
+        (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (1260:1384:1509)(1260:1384:1509))
+        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4/Q1 SLICE_64/D1 (1001:1094:1188)(1001:1094:1188))
+        (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (1316:1448:1580)(1316:1448:1580))
+        (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (1733:1895:2058)(1733:1895:2058))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (1245:1393:1541)(1245:1393:1541))
+        (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (1648:1825:2002)(1648:1825:2002))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1131:1266:1402)(1131:1266:1402))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/C0 (1131:1266:1402)(1131:1266:1402))
+        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (1652:1794:1936)(1652:1794:1936))
+        (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_5/Q0 SLICE_84/A1 (1663:1816:1970)(1663:1816:1970))
+        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (1844:2015:2186)(1844:2015:2186))
+        (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/D1 (595:663:731)(595:663:731))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (864:963:1063)(864:963:1063))
+        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1497:1620:1743)(1497:1620:1743))
+        (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (603:667:731)(603:667:731))
+        (INTERCONNECT SLICE_7/Q1 SLICE_69/B1 (918:1020:1123)(918:1020:1123))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7/Q0 SLICE_72/D0 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1232:1375:1519)(1232:1375:1519))
+        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (1675:1841:2008)(1675:1841:2008))
+        (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (1561:1715:1869)(1561:1715:1869))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8/Q0 SLICE_68/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_8/Q0 SLICE_69/A1 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_85/F1 SLICE_9/C1 (1087:1218:1349)(1087:1218:1349))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/B1 (1843:2032:2222)(1843:2032:2222))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1203:1325:1448)(1203:1325:1448))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (1683:1853:2023)(1683:1853:2023))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (1528:1679:1830)(1528:1679:1830))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D1 (2744:2982:3221)(2744:2982:3221))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D0 (2744:2982:3221)(2744:2982:3221))
+        (INTERCONNECT SLICE_70/F1 SLICE_9/A1 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/A1 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/A0 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (882:978:1075)(882:978:1075))
+        (INTERCONNECT SLICE_70/F1 SLICE_70/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_70/F1 SLICE_90/B1 (1317:1447:1578)(1317:1447:1578))
+        (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634))
+        (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (261:290:320)(261:290:320))
+        (INTERCONNECT SLICE_14/F1 SLICE_9/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (559:618:678)(559:618:678))
+        (INTERCONNECT SLICE_70/F0 SLICE_9/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2182:2416:2650)(2182:2416:2650))
+        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2731:3325:3919)(2731:3325:3919))
+        (INTERCONNECT SLICE_77/F0 SLICE_14/D1 (564:632:700)(564:632:700))
+        (INTERCONNECT SLICE_76/F0 SLICE_14/C1 (1530:1676:1822)(1530:1676:1822))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (1225:1351:1478)(1225:1351:1478))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1525:1685:1846)(1525:1685:1846))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/B0 (1540:1705:1870)(1540:1705:1870))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (1879:2062:2246)(1879:2062:2246))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/C0 (1373:1516:1660)(1373:1516:1660))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1225:1351:1478)(1225:1351:1478))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (1784:1959:2134)(1784:1959:2134))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (1541:1706:1872)(1541:1706:1872))
+        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_14/Q0 SLICE_20/B0 (832:929:1026)(832:929:1026))
+        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/D1 (956:1070:1185)(956:1070:1185))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (2110:2331:2552)(2110:2331:2552))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/C1 (2657:2925:3193)(2657:2925:3193))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (2482:2728:2974)(2482:2728:2974))
+        (INTERCONNECT SLICE_51/Q1 SLICE_43/C1 (2365:2598:2832)(2365:2598:2832))
+        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (2110:2331:2552)(2110:2331:2552))
+        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (2620:2864:3109)(2620:2864:3109))
+        (INTERCONNECT SLICE_51/Q1 SLICE_61/A1 (2054:2267:2480)(2054:2267:2480))
+        (INTERCONNECT SLICE_51/Q1 SLICE_62/D1 (1793:1977:2161)(1793:1977:2161))
+        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (2210:2424:2639)(2210:2424:2639))
+        (INTERCONNECT SLICE_51/Q1 SLICE_73/B1 (895:1001:1108)(895:1001:1108))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (763:846:930)(763:846:930))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (763:846:930)(763:846:930))
+        (INTERCONNECT SLICE_50/Q0 SLICE_41/C1 (1581:1730:1879)(1581:1730:1879))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (1769:1942:2115)(1769:1942:2115))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (2019:2202:2385)(2019:2202:2385))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (2019:2202:2385)(2019:2202:2385))
+        (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (1454:1588:1723)(1454:1588:1723))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C1 (757:844:932)(757:844:932))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C0 (757:844:932)(757:844:932))
+        (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2026:2210:2394)(2026:2210:2394))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (878:975:1072)(878:975:1072))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_19/Q0 SLICE_41/B1 (938:1041:1144)(938:1041:1144))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1181:1293:1406)(1181:1293:1406))
+        (INTERCONNECT SLICE_19/Q0 SLICE_63/A0 (892:988:1084)(892:988:1084))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1362:1496:1631)(1362:1496:1631))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1362:1496:1631)(1362:1496:1631))
+        (INTERCONNECT SLICE_19/Q0 SLICE_73/A1 (1316:1443:1571)(1316:1443:1571))
+        (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (1047:1143:1239)(1047:1143:1239))
+        (INTERCONNECT SLICE_19/Q0 SLICE_80/C0 (718:795:873)(718:795:873))
+        (INTERCONNECT SLICE_31/Q0 SLICE_19/A1 (1286:1409:1533)(1286:1409:1533))
+        (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (825:914:1004)(825:914:1004))
+        (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (1424:1556:1689)(1424:1556:1689))
+        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/F1 SLICE_43/A0 (849:948:1048)(849:948:1048))
+        (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/A1 (810:899:989)(810:899:989))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_20/Q0 SLICE_67/D0 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_90/F1 SLICE_20/C0 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_21/D1 (321:350:380)(321:350:380))
+        (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (640:708:776)(640:708:776))
+        (INTERCONNECT SLICE_75/F1 SLICE_67/D1 (1047:1139:1231)(1047:1139:1231))
+        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (476:524:573)(476:524:573))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/C1 (476:524:573)(476:524:573))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (901:997:1094)(901:997:1094))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/B1 (1546:1711:1877)(1546:1711:1877))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2468:2685:2903)(2468:2685:2903))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/B1 (1949:2143:2338)(1949:2143:2338))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/B0 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B1 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1962:2156:2351)(1962:2156:2351))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2795:3059:3324)(2795:3059:3324))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A1 (1500:1658:1817)(1500:1658:1817))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A0 (1500:1658:1817)(1500:1658:1817))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/D0 (1944:2137:2330)(1944:2137:2330))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/A1 (1398:1552:1707)(1398:1552:1707))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/A1 (988:1113:1238)(988:1113:1238))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/C1 (1556:1731:1906)(1556:1731:1906))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (712:804:897)(712:804:897))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (988:1113:1238)(988:1113:1238))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/D1 (709:801:894)(709:801:894))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/D1 (1418:1575:1733)(1418:1575:1733))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/C0 (1277:1418:1560)(1277:1418:1560))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (712:804:897)(712:804:897))
+        (INTERCONNECT SLICE_75/F0 SLICE_21/D0 (245:274:304)(245:274:304))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (853:947:1042)(853:947:1042))
+        (INTERCONNECT SLICE_82/F1 SLICE_21/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_33/Q0 SLICE_21/A0 (1514:1694:1875)(1514:1694:1875))
+        (INTERCONNECT SLICE_33/Q0 SLICE_33/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (1674:1856:2038)(1674:1856:2038))
+        (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/F0 SLICE_21/CE (1285:1433:1581)(1285:1433:1581))
+        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (921:1020:1119)(921:1020:1119))
+        (INTERCONNECT SLICE_67/F0 SLICE_57/CE (1696:1875:2055)(1696:1875:2055))
+        (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_67/F0 SLICE_82/D0 (986:1100:1215)(986:1100:1215))
+        (INTERCONNECT SLICE_21/Q0 SLICE_33/A0 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_21/Q0 SLICE_82/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1682:1846:2010)(1682:1846:2010))
+        (INTERCONNECT SLICE_32/Q0 SLICE_22/C1 (1201:1313:1426)(1201:1313:1426))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/A1 (854:945:1036)(854:945:1036))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (575:636:697)(575:636:697))
+        (INTERCONNECT SLICE_32/Q0 SLICE_33/C0 (1611:1753:1895)(1611:1753:1895))
+        (INTERCONNECT SLICE_32/Q0 SLICE_43/D1 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_32/Q0 SLICE_43/D0 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_32/Q0 SLICE_44/C1 (2035:2209:2383)(2035:2209:2383))
+        (INTERCONNECT SLICE_32/Q0 SLICE_51/B1 (1769:1941:2114)(1769:1941:2114))
+        (INTERCONNECT SLICE_32/Q0 SLICE_52/B1 (1771:1932:2094)(1771:1932:2094))
+        (INTERCONNECT SLICE_32/Q0 SLICE_58/C1 (740:818:897)(740:818:897))
+        (INTERCONNECT SLICE_32/Q0 SLICE_58/C0 (740:818:897)(740:818:897))
+        (INTERCONNECT SLICE_32/Q0 SLICE_64/C1 (784:866:948)(784:866:948))
+        (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (1746:1903:2061)(1746:1903:2061))
+        (INTERCONNECT SLICE_32/Q0 SLICE_66/B1 (1777:1952:2127)(1777:1952:2127))
+        (INTERCONNECT SLICE_32/Q0 SLICE_66/B0 (1777:1952:2127)(1777:1952:2127))
+        (INTERCONNECT SLICE_32/Q0 SLICE_73/D1 (1477:1603:1729)(1477:1603:1729))
+        (INTERCONNECT SLICE_43/Q1 SLICE_22/B1 (1302:1432:1563)(1302:1432:1563))
+        (INTERCONNECT SLICE_43/Q1 SLICE_52/C1 (1103:1234:1365)(1103:1234:1365))
+        (INTERCONNECT SLICE_41/Q1 SLICE_22/A1 (1260:1384:1509)(1260:1384:1509))
+        (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (544:603:663)(544:603:663))
+        (INTERCONNECT SLICE_41/Q1 SLICE_52/D1 (991:1084:1177)(991:1084:1177))
+        (INTERCONNECT SLICE_82/F0 SLICE_22/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22/F1 SLICE_68/C0 (1133:1244:1356)(1133:1244:1356))
+        (INTERCONNECT SLICE_22/F1 SLICE_69/C0 (1133:1244:1356)(1133:1244:1356))
+        (INTERCONNECT SLICE_78/F1 SLICE_26/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_26/Q0 SLICE_58/B0 (899:1000:1102)(899:1000:1102))
+        (INTERCONNECT SLICE_76/F1 SLICE_26/A1 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_58/Q0 SLICE_39/C0 (1936:2106:2276)(1936:2106:2276))
+        (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61/F1 SLICE_29/D1 (584:647:710)(584:647:710))
+        (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (726:803:880)(726:803:880))
+        (INTERCONNECT SLICE_29/Q0 SLICE_29/D0 (571:629:687)(571:629:687))
+        (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (643:708:773)(643:708:773))
+        (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (643:708:773)(643:708:773))
+        (INTERCONNECT SLICE_29/Q0 SLICE_31/C0 (798:882:966)(798:882:966))
+        (INTERCONNECT SLICE_29/Q0 SLICE_42/D1 (1534:1657:1781)(1534:1657:1781))
+        (INTERCONNECT SLICE_29/Q0 SLICE_61/D0 (932:1031:1131)(932:1031:1131))
+        (INTERCONNECT SLICE_29/Q0 SLICE_83/B0 (2655:2875:3095)(2655:2875:3095))
+        (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (1300:1448:1596)(1300:1448:1596))
+        (INTERCONNECT SLICE_83/F1 SLICE_29/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_83/F1 SLICE_61/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_73/F1 SLICE_29/A1 (1297:1422:1547)(1297:1422:1547))
+        (INTERCONNECT SLICE_73/F1 SLICE_29/A0 (1297:1422:1547)(1297:1422:1547))
+        (INTERCONNECT SLICE_73/F1 SLICE_59/D1 (1109:1203:1297)(1109:1203:1297))
+        (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1062:1179:1297)(1062:1179:1297))
+        (INTERCONNECT SLICE_73/F1 SLICE_73/C0 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_73/F1 SLICE_94/B1 (871:967:1064)(871:967:1064))
+        (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (2198:2404:2610)(2198:2404:2610))
+        (INTERCONNECT SLICE_43/Q0 SLICE_41/C0 (733:810:888)(733:810:888))
+        (INTERCONNECT SLICE_43/Q0 SLICE_43/B1 (886:982:1079)(886:982:1079))
+        (INTERCONNECT SLICE_43/Q0 SLICE_43/C0 (733:810:888)(733:810:888))
+        (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (1490:1629:1769)(1490:1629:1769))
+        (INTERCONNECT SLICE_43/Q0 SLICE_59/B1 (2511:2758:3006)(2511:2758:3006))
+        (INTERCONNECT SLICE_43/Q0 SLICE_61/B1 (2087:2299:2511)(2087:2299:2511))
+        (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2087:2299:2511)(2087:2299:2511))
+        (INTERCONNECT SLICE_43/Q0 SLICE_63/B1 (1805:1983:2161)(1805:1983:2161))
+        (INTERCONNECT SLICE_43/Q0 SLICE_63/B0 (1805:1983:2161)(1805:1983:2161))
+        (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (948:1049:1150)(948:1049:1150))
+        (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1199:1330:1461)(1199:1330:1461))
+        (INTERCONNECT SLICE_43/Q0 SLICE_79/A1 (894:993:1093)(894:993:1093))
+        (INTERCONNECT SLICE_43/Q0 SLICE_94/A1 (907:1003:1099)(907:1003:1099))
+        (INTERCONNECT SLICE_43/Q0 SLICE_94/A0 (907:1003:1099)(907:1003:1099))
+        (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_30/Q0 SLICE_30/B1 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (885:983:1081)(885:983:1081))
+        (INTERCONNECT SLICE_30/Q0 SLICE_42/A1 (1378:1503:1629)(1378:1503:1629))
+        (INTERCONNECT SLICE_30/Q0 SLICE_83/C1 (1179:1290:1402)(1179:1290:1402))
+        (INTERCONNECT SLICE_30/Q0 SLICE_83/C0 (1179:1290:1402)(1179:1290:1402))
+        (INTERCONNECT SLICE_30/Q1 SLICE_30/A1 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (563:621:680)(563:621:680))
+        (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (563:621:680)(563:621:680))
+        (INTERCONNECT SLICE_30/Q1 SLICE_42/B1 (1424:1556:1689)(1424:1556:1689))
+        (INTERCONNECT SLICE_30/Q1 SLICE_83/A1 (1293:1417:1541)(1293:1417:1541))
+        (INTERCONNECT SLICE_30/Q1 SLICE_83/A0 (1293:1417:1541)(1293:1417:1541))
+        (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94/F1 SLICE_30/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_94/F1 SLICE_31/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (575:639:703)(575:639:703))
+        (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1352:1480:1609)(1352:1480:1609))
+        (INTERCONNECT SLICE_72/F1 SLICE_32/C1 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (291:320:350)(291:320:350))
+        (INTERCONNECT SLICE_72/F1 SLICE_64/B1 (929:1030:1132)(929:1030:1132))
+        (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (446:494:543)(446:494:543))
+        (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (879:985:1092)(879:985:1092))
+        (INTERCONNECT SLICE_74/F0 SLICE_32/B0 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_33/D1 (2857:3462:4068)(2857:3462:4068))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (3532:4217:4903)(3532:4217:4903))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (2293:2830:3368)(2293:2830:3368))
+        (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1365:1507:1650)(1365:1507:1650))
+        (INTERCONNECT SLICE_78/Q0 SLICE_60/A0 (1681:1846:2012)(1681:1846:2012))
+        (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1239:1386:1534)(1239:1386:1534))
+        (INTERCONNECT SLICE_78/Q0 SLICE_79/A0 (1239:1386:1534)(1239:1386:1534))
+        (INTERCONNECT UFMSDO_I/PADDI SLICE_33/D0 (702:793:885)(702:793:885))
+        (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (1105:1225:1346)(1105:1225:1346))
+        (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69/F0 SLICE_33/CE (939:1052:1165)(939:1052:1165))
+        (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_85/F0 SLICE_39/D1 (1514:1646:1779)(1514:1646:1779))
+        (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_57/Q0 SLICE_39/A1 (2147:2339:2531)(2147:2339:2531))
+        (INTERCONNECT SLICE_57/Q0 SLICE_39/A0 (2147:2339:2531)(2147:2339:2531))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/D0 (2053:2245:2437)(2053:2245:2437))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (3194:3483:3773)(3194:3483:3773))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/B1 (1519:1680:1842)(1519:1680:1842))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/D0 (2081:2276:2472)(2081:2276:2472))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2388:2619:2851)(2388:2619:2851))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/B0 (2396:2630:2864)(2396:2630:2864))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/B0 (2799:3062:3325)(2799:3062:3325))
+        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1313:1442:1571)(1313:1442:1571))
+        (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1850:2013:2177)(1850:2013:2177))
+        (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (559:618:678)(559:618:678))
+        (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (1842:2003:2164)(1842:2003:2164))
+        (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1447:1581:1716)(1447:1581:1716))
+        (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (1767:1931:2095)(1767:1931:2095))
+        (INTERCONNECT SLICE_75/Q1 SLICE_41/D1 (960:1076:1193)(960:1076:1193))
+        (INTERCONNECT SLICE_75/Q1 SLICE_60/B1 (1967:2185:2404)(1967:2185:2404))
+        (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1275:1430:1585)(1275:1430:1585))
+        (INTERCONNECT SLICE_75/Q1 SLICE_80/D1 (1370:1516:1662)(1370:1516:1662))
+        (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (1780:1956:2132)(1780:1956:2132))
+        (INTERCONNECT SLICE_81/Q1 SLICE_41/A1 (2097:2301:2505)(2097:2301:2505))
+        (INTERCONNECT SLICE_81/Q1 SLICE_60/D1 (2924:3195:3466)(2924:3195:3466))
+        (INTERCONNECT SLICE_43/F1 SLICE_41/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_41/F1 SLICE_41/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1342:1484:1626)(1342:1484:1626))
+        (INTERCONNECT SLICE_41/Q0 SLICE_42/D0 (1352:1480:1609)(1352:1480:1609))
+        (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_44/Q1 SLICE_42/B0 (1293:1424:1555)(1293:1424:1555))
+        (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (2091:2277:2464)(2091:2277:2464))
+        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42/Q0 SLICE_61/C1 (1543:1684:1825)(1543:1684:1825))
+        (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/A1 (2060:2242:2425)(2060:2242:2425))
+        (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (1978:2217:2456)(1978:2217:2456))
+        (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/D0 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_50/F0 SLICE_43/A1 (1270:1395:1520)(1270:1395:1520))
+        (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (16:16:16)(16:16:16))
+        (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (1001:1094:1188)(1001:1094:1188))
+        (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1156:1268:1381)(1156:1268:1381))
+        (INTERCONNECT SLICE_83/F0 SLICE_43/B0 (1255:1408:1561)(1255:1408:1561))
+        (INTERCONNECT SLICE_83/F0 SLICE_44/A1 (1612:1787:1962)(1612:1787:1962))
+        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44/F1 SLICE_44/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1375:1502:1629)(1375:1502:1629))
+        (INTERCONNECT SLICE_72/F0 SLICE_51/C1 (1126:1237:1348)(1126:1237:1348))
+        (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_66/F0 SLICE_66/C1 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_51/Q0 SLICE_51/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1548:1774:2000)(1548:1774:2000))
+        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (1409:1541:1674)(1409:1541:1674))
+        (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_52/F1 SLICE_51/A0 (1157:1286:1415)(1157:1286:1415))
+        (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_52/F1 SLICE_64/D0 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/D0 (1207:1330:1453)(1207:1330:1453))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (1949:2146:2344)(1949:2146:2344))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/B1 (1914:2103:2292)(1914:2103:2292))
+        (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (1997:2204:2411)(1997:2204:2411))
+        (INTERCONNECT SLICE_63/Q0 SLICE_86/D1 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63/Q0 SLICE_86/D0 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (1451:1592:1734)(1451:1592:1734))
+        (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT SLICE_63/Q0 SLICE_91/C1 (2426:2645:2865)(2426:2645:2865))
+        (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (2426:2645:2865)(2426:2645:2865))
+        (INTERCONNECT SLICE_63/Q0 SLICE_92/C1 (1898:2093:2289)(1898:2093:2289))
+        (INTERCONNECT SLICE_63/Q0 SLICE_92/C0 (1898:2093:2289)(1898:2093:2289))
+        (INTERCONNECT SLICE_63/Q0 SLICE_93/A1 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2176:2385:2595)(2176:2385:2595))
+        (INTERCONNECT SLICE_67/Q0 SLICE_55/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2322:2541:2761)(2322:2541:2761))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/A1 (1473:1628:1784)(1473:1628:1784))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1635:1791:1948)(1635:1791:1948))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/D1 (1628:1783:1939)(1628:1783:1939))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/D1 (1628:1783:1939)(1628:1783:1939))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/C0 (2072:2281:2490)(2072:2281:2490))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (2787:3031:3276)(2787:3031:3276))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2787:3031:3276)(2787:3031:3276))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (2225:2440:2655)(2225:2440:2655))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (1818:2004:2190)(1818:2004:2190))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (1818:2004:2190)(1818:2004:2190))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (2377:2592:2807)(2377:2592:2807))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1564:1720:1877)(1564:1720:1877))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_88/A0 (1798:1981:2164)(1798:1981:2164))
+        (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (2042:2305:2568)(2042:2305:2568))
+        (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (2630:2955:3280)(2630:2955:3280))
+        (INTERCONNECT SLICE_77/Q1 SLICE_56/D1 (1260:1386:1513)(1260:1386:1513))
+        (INTERCONNECT SLICE_77/Q0 SLICE_56/C1 (1126:1237:1348)(1126:1237:1348))
+        (INTERCONNECT SLICE_76/Q1 SLICE_56/B1 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_71/Q0 SLICE_56/A1 (1332:1457:1583)(1332:1457:1583))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2232:2447:2663)(2232:2447:2663))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/D1 (1515:1665:1815)(1515:1665:1815))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/A1 (2604:2844:3085)(2604:2844:3085))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (2642:2887:3132)(2642:2887:3132))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A1 (1381:1533:1686)(1381:1533:1686))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A0 (1381:1533:1686)(1381:1533:1686))
+        (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/C1 (1277:1418:1559)(1277:1418:1559))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (1839:2026:2214)(1839:2026:2214))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (2242:2458:2675)(2242:2458:2675))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/D1 (1532:1683:1835)(1532:1683:1835))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (3049:3329:3610)(3049:3329:3610))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/C1 (1566:1741:1917)(1566:1741:1917))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1437:1597:1758)(1437:1597:1758))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1129:1252:1375)(1129:1252:1375))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1411:1566:1722)(1411:1566:1722))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1384:1536:1689)(1384:1536:1689))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1673:1860:2047)(1673:1860:2047))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (1429:1587:1745)(1429:1587:1745))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (710:802:894)(710:802:894))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (1420:1577:1734)(1420:1577:1734))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1933:2113:2294)(1933:2113:2294))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1113:1234:1355)(1113:1234:1355))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1025:1155:1286)(1025:1155:1286))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (2233:2448:2664)(2233:2448:2664))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/B1 (1025:1155:1286)(1025:1155:1286))
+        (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_80/F0 SLICE_59/B0 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_62/F1 SLICE_59/A0 (1751:1905:2060)(1751:1905:2060))
+        (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (1723:1947:2172)(1723:1947:2172))
+        (INTERCONNECT SLICE_82/Q0 SLICE_60/A1 (1751:1905:2060)(1751:1905:2060))
+        (INTERCONNECT SLICE_82/Q0 SLICE_63/C1 (748:831:915)(748:831:915))
+        (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (996:1089:1183)(996:1089:1183))
+        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (908:1011:1114)(908:1011:1114))
+        (INTERCONNECT SLICE_94/F0 SLICE_60/D0 (1382:1514:1647)(1382:1514:1647))
+        (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT SLICE_78/Q1 SLICE_62/A1 (1348:1473:1599)(1348:1473:1599))
+        (INTERCONNECT SLICE_78/Q1 SLICE_80/A0 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/D0 (568:631:694)(568:631:694))
+        (INTERCONNECT SLICE_81/Q0 SLICE_62/B0 (1797:1958:2120)(1797:1958:2120))
+        (INTERCONNECT SLICE_81/Q0 SLICE_63/D1 (588:652:716)(588:652:716))
+        (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1395:1523:1651)(1395:1523:1651))
+        (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64/Q0 SLICE_64/C0 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1990:2225:2460)(1990:2225:2460))
+        (INTERCONNECT SLICE_66/F1 SLICE_64/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73/Q1 SLICE_66/D1 (1335:1476:1617)(1335:1476:1617))
+        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_81/F0 SLICE_74/D0 (261:290:320)(261:290:320))
+        (INTERCONNECT SLICE_74/F1 SLICE_66/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_66/Q0 SLICE_90/B0 (2100:2300:2500)(2100:2300:2500))
+        (INTERCONNECT SLICE_66/Q1 SLICE_91/D0 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (1219:1345:1472)(1219:1345:1472))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/A1 (1884:2070:2256)(1884:2070:2256))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/C1 (1794:1974:2155)(1794:1974:2155))
+        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (579:644:709)(579:644:709))
+        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (982:1076:1170)(982:1076:1170))
+        (INTERCONNECT SLICE_67/Q1 SLICE_93/B1 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT SLICE_87/F0 SLICE_68/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_87/F0 SLICE_69/D0 (572:636:700)(572:636:700))
+        (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_84/F0 SLICE_68/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_84/F0 SLICE_69/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_70/Q0 SLICE_70/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_70/Q1 SLICE_70/A1 (514:575:636)(514:575:636))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/D1 (1647:1811:1975)(1647:1811:1975))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/A1 (1876:2059:2243)(1876:2059:2243))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/C1 (1765:1936:2107)(1765:1936:2107))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (1917:2105:2293)(1917:2105:2293))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/D1 (2013:2194:2375)(2013:2194:2375))
+        (INTERCONNECT SLICE_88/F1 SLICE_71/D0 (564:632:700)(564:632:700))
+        (INTERCONNECT SLICE_71/Q1 SLICE_71/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (879:985:1092)(879:985:1092))
+        (INTERCONNECT SLICE_71/F1 SLICE_71/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_81/F1 SLICE_72/D1 (564:632:700)(564:632:700))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (1611:1765:1919)(1611:1765:1919))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/B1 (1926:2118:2310)(1926:2118:2310))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/D0 (2417:2628:2840)(2417:2628:2840))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (1115:1236:1357)(1115:1236:1357))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/D1 (1921:2099:2278)(1921:2099:2278))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/D0 (2324:2531:2739)(2324:2531:2739))
+        (INTERCONNECT SLICE_72/Q0 SLICE_92/B0 (1689:1848:2008)(1689:1848:2008))
+        (INTERCONNECT SLICE_72/Q1 SLICE_93/A0 (1735:1889:2044)(1735:1889:2044))
+        (INTERCONNECT SLICE_74/Q0 SLICE_87/A1 (833:932:1032)(833:932:1032))
+        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_79/F1 SLICE_79/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (1164:1346:1528)(1164:1346:1528))
+        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (1943:2141:2340)(1943:2141:2340))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A1 (2322:2546:2771)(2322:2546:2771))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (2322:2546:2771)(2322:2546:2771))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2208:2420:2632)(2208:2420:2632))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/B0 (1919:2110:2302)(1919:2110:2302))
+        (INTERCONNECT SLICE_80/Q0 SLICE_89/A0 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_80/Q1 SLICE_86/C0 (723:805:887)(723:805:887))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1514:1673:1833)(1514:1673:1833))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1514:1673:1833)(1514:1673:1833))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (1802:1985:2168)(1802:1985:2168))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (1802:1985:2168)(1802:1985:2168))
+        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (1635:1796:1957)(1635:1796:1957))
+        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (1635:1796:1957)(1635:1796:1957))
+        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2063:2303:2544)(2063:2303:2544))
+        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (1971:2209:2448)(1971:2209:2448))
+        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1748:1996:2245)(1748:1996:2245))
+        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2544:2849:3155)(2544:2849:3155))
+        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (3364:3728:4093)(3364:3728:4093))
+        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (3364:3728:4093)(3364:3728:4093))
+        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1783:2025:2267)(1783:2025:2267))
+        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (3357:3721:4085)(3357:3721:4085))
+        (INTERCONNECT SLICE_88/Q0 SLICE_92/D1 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT SLICE_88/Q1 SLICE_91/A1 (837:931:1026)(837:931:1026))
+        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1932:2190:2449)(1932:2190:2449))
+        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1974:2209:2444)(1974:2209:2444))
+        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (2063:2303:2544)(2063:2303:2544))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2288:2578:2869)(2288:2578:2869))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (1418:1631:1845)(1418:1631:1845))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (1421:1631:1841)(1421:1631:1841))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2196:2460:2725)(2196:2460:2725))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo
index 28dbed9..e9279a7 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo
@@ -1,3714 +1,3714 @@
-
-// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
-// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_vo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd 
-// Netlist created on Wed Aug 16 04:50:39 2023
-// Netlist written on Wed Aug 16 04:50:49 2023
-// Design is for device LCMXO256C
-// Design is for package TQFP100
-// Design is for performance grade 3
-
-`timescale 1 ns / 1 ps
-
-module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
-                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
-                UFMCLK, UFMSDI, UFMSDO );
-  input  PHI2;
-  input  [9:0] MAin;
-  input  [1:0] CROW;
-  input  [7:0] Din;
-  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
-  output [7:0] Dout;
-  output LED;
-  output [1:0] RBA;
-  output [11:0] RA;
-  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
-  inout  [7:0] RD;
-  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
-         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
-         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
-         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
-         \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, CmdEnable17_0_a2_3, 
-         \MAin_c[0] , N_147, ADSubmitted, CmdEnable17, CmdEnable16, C1WR_0_a2, 
-         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
-         \MAin_c[1] , C1Submitted, C1Submitted_RNO, RASr2, \S[1] , CO0, 
-         \IS[3] , N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
-         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_133, N_152, N_132, 
-         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, InitReady, PHI2r3, 
-         PHI2r2, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
-         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
-         \IS[0] , N_160, N_155, Ready, N_64_i_i, N_24, \IS[1] , \IS[2] , 
-         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, N_51, 
-         UFMSDI_ens2_i_a2_4_2, InitReady3, N_461_0, UFMSDI_ens2_i_a0, nCRAS_c, 
-         CBR, UFMSDO_c, N_70, N_33, LED_c, un1_Din_4, XOR8MEG, \Din_c[6] , 
-         RA11_2, Ready_fast, \RA_c[11] , N_171, CASr2, FWEr_fast, 
-         RCKEEN_8_u_0_0, RCKEEN_8_u_1, RCKEEN_8, PHI2r, RCKEEN, RASr3, RASr, 
-         RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, 
-         Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, 
-         UFMCLK_r_i_a2_2_2, UFMCLK_c, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, N_139_i, 
-         UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \MAin_c[4] , 
-         nRowColSel, \RowA[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , 
-         \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , \Din_c[7] , 
-         \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[0] , \Din_c[2] , 
-         \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, 
-         g0_1, nRCAS_0_sqmuxa_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, 
-         N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, m18_0_a2_1, FWEr, 
-         G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, 
-         nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, 
-         \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , 
-         N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , 
-         C1WR_0_a2_0_10, \Bank[1] , \MAin_c[6] , \MAin_c[7] , C1WR_0_a2_0_3, 
-         \Bank[3] , \Bank[4] , C1WR_0_a2_0_4, UFMSDI_ens2_i_o2_0_3, 
-         \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, 
-         CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , 
-         \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , 
-         \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, 
-         RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , 
-         \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , 
-         \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
-         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
-
-  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
-    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
-  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
-  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
-  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
-  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
-  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
-    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
-  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
-    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
-  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
-    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
-  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
-    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
-  SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(CmdEnable17_0_a2_3), 
-    .B1(\MAin_c[0] ), .A1(N_147), .D0(ADSubmitted), .C0(CmdEnable17), 
-    .B0(CmdEnable16), .A0(C1WR_0_a2), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
-    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
-  SLICE_14 SLICE_14( .D1(CmdEnable16_0_a2_5), .C1(CmdEnable16_0_a2_4), 
-    .A1(N_147), .D0(\MAin_c[1] ), .C0(CmdEnable16), .B0(C1Submitted), 
-    .A0(N_147), .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), 
-    .Q0(C1Submitted), .F1(CmdEnable16));
-  SLICE_19 SLICE_19( .D1(RASr2), .C1(\S[1] ), .B1(CO0), .A1(\IS[3] ), 
-    .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
-  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(CmdEnable17), 
-    .C0(un1_CMDWR), .B0(C1Submitted), .A0(CmdEnable), .DI0(CmdEnable_s), 
-    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
-  SLICE_21 SLICE_21( .D1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_133), 
-    .C0(N_152), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
-  SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(InitReady), .B1(PHI2r3), 
-    .A1(PHI2r2), .C0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), .DI0(N_460_0), 
-    .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
-  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
-    .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), 
-    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
-    .F1(Cmdn8MEGEN_4_u_i_0));
-  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(\IS[0] ), .B1(N_160), .A1(N_155), 
-    .D0(\IS[0] ), .B0(Ready), .A0(N_155), .DI0(N_64_i_i), .CLK(RCLK_c), 
-    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
-  SLICE_30 SLICE_30( .D1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .D0(\IS[0] ), 
-    .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
-    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
-  SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), 
-    .D0(\IS[2] ), .C0(\IS[0] ), .B0(\IS[1] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
-    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
-  SLICE_32 SLICE_32( .D1(N_126), .C1(N_51), .B1(UFMSDI_ens2_i_a2_4_2), 
-    .A1(InitReady), .B0(InitReady3), .A0(InitReady), .DI0(N_461_0), 
-    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
-  SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(LEDEN), .A1(CBR), .D0(UFMSDO_c), 
-    .C0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
-    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
-  SLICE_39 SLICE_39( .D1(un1_Din_4), .A1(XOR8MEG), .D0(\Din_c[6] ), 
-    .C0(n8MEGEN), .A0(XOR8MEG), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), 
-    .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171));
-  SLICE_41 SLICE_41( .D1(CASr2), .C1(\S[1] ), .B1(CO0), .A1(FWEr_fast), 
-    .D0(CBR), .C0(Ready), .B0(RCKEEN_8_u_0_0), .A0(RCKEEN_8_u_1), 
-    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
-    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
-  SLICE_42 SLICE_42( .D1(\IS[0] ), .C1(RASr2), .B1(\IS[2] ), .A1(\IS[1] ), 
-    .D0(RCKEEN), .C0(RASr3), .B0(RASr), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), 
-    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
-  SLICE_43 SLICE_43( .D1(InitReady), .C1(RASr2), .B1(Ready), 
-    .A1(\S_0_i_o2[1] ), .D0(InitReady), .C0(Ready), .B0(N_165), 
-    .A0(Ready_0_sqmuxa_0_a3_2), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), 
-    .F0(N_462_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
-  SLICE_44 SLICE_44( .D1(Ready), .C1(InitReady), .B1(Ready_0_sqmuxa_0_a3_2), 
-    .A1(N_165), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), 
-    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
-    .F1(Ready_0_sqmuxa), .Q1(RASr));
-  SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .B1(\S[1] ), .C0(CO0), .A0(\S[1] ), 
-    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
-    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
-  SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(N_129), .B1(InitReady), 
-    .A1(UFMCLK_r_i_a2_2_2), .D0(UFMCLK_c), .C0(UFMCLK_r_i_m4_xx_mm_1), 
-    .B0(nUFMCS15), .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), 
-    .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
-  SLICE_52 SLICE_52( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), 
-    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), 
-    .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
-    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
-  SLICE_55 SLICE_55( .D0(\MAin_c[4] ), .B0(nRowColSel), .A0(\RowA[4] ), 
-    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
-    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
-  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
-    .A1(\Bank[2] ), .D0(\FS[5] ), .C0(\FS[9] ), .B0(\FS[7] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
-    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
-  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[3] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), 
-    .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), 
-    .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
-  SLICE_58 SLICE_58( .D1(N_51), .C1(InitReady), .A1(\FS[8] ), .D0(UFMSDO_c), 
-    .C0(InitReady), .B0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
-    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
-  SLICE_59 SLICE_59( .D1(N_155), .C1(\S[1] ), .B1(Ready), .A1(N_160), 
-    .D0(N_41), .C0(\S[1] ), .B0(g0_1), .A0(nRCAS_0_sqmuxa_1), .DI0(N_37_i), 
-    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
-  SLICE_60 SLICE_60( .D1(FWEr_fast), .C1(CO0), .B1(CASr2), .A1(CASr3), 
-    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
-    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
-  SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(RCKE_c), .B1(Ready), .A1(RASr2), 
-    .D0(\IS[0] ), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(N_160), .DI0(N_24_i), 
-    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
-  SLICE_62 SLICE_62( .D1(RASr2), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(CBR_fast), 
-    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(FWEr), .A0(G_17_1), 
-    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
-    .F1(nRCAS_0_sqmuxa_1));
-  SLICE_63 SLICE_63( .D1(FWEr), .C1(CASr3), .B1(Ready), .A1(CBR), .D0(\S[1] ), 
-    .C0(N_179), .B0(Ready), .A0(CO0), .DI0(nRowColSel_0_0), 
-    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
-    .F1(N_179));
-  SLICE_64 SLICE_64( .D1(\FS[11] ), .C1(InitReady), .B1(N_51), .A1(\FS[10] ), 
-    .D0(N_139_i), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(nUFMCS_s_0_N_5_i_N_2L1), 
-    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
-    .F1(nUFMCS15));
-  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(\S[1] ), .B1(CO0), 
-    .A1(RCKE_c), .D0(m18_0_a3_3), .C0(\S[1] ), .B0(CO0), .A0(InitReady), 
-    .M0(Ready), .OFX0(m18_0_a2_1));
-  SLICE_66 SLICE_66( .D1(CmdUFMCS), .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), 
-    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
-    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
-    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
-  SLICE_67 SLICE_67( .D1(N_128), .C1(\Din_c[3] ), .B1(\Din_c[5] ), 
-    .A1(XOR8MEG18), .D0(CmdEnable), .C0(\MAin_c[0] ), .B0(\MAin_c[1] ), 
-    .A0(N_147), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
-    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
-    .Q1(\RowA[5] ));
-  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[2] ), .B1(\FS[0] ), .A1(\FS[3] ), 
-    .D0(N_137_8), .C0(N_136), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), 
-    .F1(un1_FS_14_i_a2_0_1));
-  SLICE_69 SLICE_69( .D1(\FS[0] ), .C1(\FS[3] ), .B1(\FS[5] ), .A1(\FS[2] ), 
-    .D0(N_137_8), .C0(N_136), .B0(N_137_6), .A0(un1_FS_13_i_a2_1), .F0(N_33), 
-    .F1(un1_FS_13_i_a2_1));
-  SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), 
-    .A1(\Bank[1] ), .C0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
-    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
-    .Q1(\Bank[1] ));
-  SLICE_71 SLICE_71( .D1(\MAin_c[6] ), .C1(\MAin_c[7] ), .B1(\MAin_c[4] ), 
-    .A1(\MAin_c[5] ), .D0(C1WR_0_a2_0_3), .C0(\Bank[3] ), .B0(\Bank[4] ), 
-    .A0(C1WR_0_a2_0_4), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
-    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
-  SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), 
-    .D0(\FS[4] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
-    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
-    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
-  SLICE_73 SLICE_73( .D1(InitReady), .C1(\S[1] ), .B1(RASr2), .A1(CO0), 
-    .C0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
-    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
-    .F1(N_155), .Q1(CmdUFMCS));
-  SLICE_74 SLICE_74( .B1(\FS[11] ), .A1(\FS[14] ), .D0(N_95_5), .C0(N_95_3), 
-    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
-  SLICE_75 SLICE_75( .D1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
-    .D0(\Din_c[1] ), .C0(N_128), .B0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), 
-    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
-  SLICE_76 SLICE_76( .D1(\Din_c[0] ), .B1(\Din_c[5] ), .D0(\MAin_c[0] ), 
-    .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), 
-    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
-    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
-  SLICE_77 SLICE_77( .D1(\Din_c[4] ), .A1(\Din_c[7] ), .D0(\Din_c[6] ), 
-    .C0(\MAin_c[1] ), .B0(CmdEnable16_1), .A0(\Din_c[2] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
-    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
-  SLICE_78 SLICE_78( .D1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), 
-    .C0(N_43), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), 
-    .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast));
-  SLICE_79 SLICE_79( .D1(CASr3), .B1(CASr2), .A1(Ready), .D0(CO0), .C0(\S[1] ), 
-    .B0(m6_0_a2_2), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(nCCAS_c), 
-    .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
-  SLICE_80 SLICE_80( .D1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CO0), 
-    .B0(g4_0_0_0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
-    .Q1(\RowA[9] ));
-  SLICE_81 SLICE_81( .D1(\FS[13] ), .C1(\FS[14] ), .B1(\FS[15] ), 
-    .A1(\FS[17] ), .D0(\FS[13] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[12] ), 
-    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
-    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
-  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(N_128), .B1(CmdLEDEN), 
-    .A1(\Din_c[5] ), .D0(XOR8MEG18), .C0(\Din_c[3] ), .B0(N_128), 
-    .A0(\Din_c[5] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), 
-    .Q0(CASr3), .F1(N_132));
-  SLICE_83 SLICE_83( .C1(\IS[1] ), .B1(\IS[3] ), .A1(\IS[2] ), .C0(\IS[1] ), 
-    .B0(\IS[0] ), .A0(\IS[2] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
-    .Q1(\RBA_c[1] ));
-  SLICE_84 SLICE_84( .D1(\FS[6] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[8] ), 
-    .D0(\FS[7] ), .C0(\FS[10] ), .B0(\FS[1] ), .A0(\FS[6] ), .F0(N_137_6), 
-    .F1(UFMSDI_ens2_i_a2_4_2));
-  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[0] ), .B1(\Din_c[1] ), 
-    .A1(\Din_c[7] ), .D0(\Din_c[5] ), .C0(\Din_c[4] ), .B0(\Din_c[6] ), 
-    .A0(\Din_c[7] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
-    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
-  SLICE_86 SLICE_86( .D1(nRowColSel), .A1(\MAin_c[9] ), .D0(nRowColSel), 
-    .C0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
-  SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .B1(N_151), .A1(CmdUFMSDI), 
-    .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), 
-    .F1(UFMSDI_r_xx_mm_1));
-  SLICE_88 SLICE_88( .D1(\MAin_c[2] ), .C1(nFWE_c), .B1(\MAin_c[3] ), 
-    .C0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
-    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
-  SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), 
-    .B0(\MAin_c[8] ), .A0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
-  SLICE_90 SLICE_90( .D1(\MAin_c[0] ), .C1(\MAin_c[1] ), .B1(N_147), 
-    .D0(\MAin_c[0] ), .B0(\RowA[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), 
-    .F1(un1_CMDWR));
-  SLICE_91 SLICE_91( .D1(\MAin_c[7] ), .C1(nRowColSel), .A1(\RowA[7] ), 
-    .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), 
-    .F1(\RA_c[7] ));
-  SLICE_92 SLICE_92( .D1(\RowA[6] ), .C1(nRowColSel), .A1(\MAin_c[6] ), 
-    .D0(\MAin_c[2] ), .C0(nRowColSel), .B0(\RowA[2] ), .F0(\RA_c[2] ), 
-    .F1(\RA_c[6] ));
-  SLICE_93 SLICE_93( .C1(\MAin_c[5] ), .B1(\RowA[5] ), .A1(nRowColSel), 
-    .D0(\MAin_c[3] ), .B0(nRowColSel), .A0(\RowA[3] ), .F0(\RA_c[3] ), 
-    .F1(\RA_c[5] ));
-  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .C0(\S[1] ), .A0(Ready), 
-    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
-    .Q0(\RA_c[10] ), .F1(N_159_i));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
-    .RD0(RD[0]));
-  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
-  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
-  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
-  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
-  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
-  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
-  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
-  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
-  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
-  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
-  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
-  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
-  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
-  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
-    .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
-    .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
-    .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
-    .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
-    .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
-    .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
-    .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
-  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
-  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
-  LED LED_I( .PADDO(LED_c), .LED(LED));
-  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
-  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
-  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
-  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
-  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
-  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
-  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
-  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
-  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
-  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
-  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
-  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
-  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
-  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
-  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
-  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
-  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
-  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
-  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
-  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
-  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
-  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
-  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
-  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
-  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
-  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
-  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
-  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
-  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
-  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
-  VHI VHI_INST( .Z(VCCI));
-  PUR PUR_INST( .PUR(VCCI));
-  GSR GSR_INST( .GSR(VCCI));
-  VLO VLO_INST( .Z(GNDI_TSALL));
-  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
-endmodule
-
-module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
-         A1_dly, CLK_dly, A0_dly;
-
-  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
-    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-  endspecify
-
-endmodule
-
-module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module vcc ( output PWR1 );
-
-  VHI INST1( .Z(PWR1));
-endmodule
-
-module gnd ( output PWR0 );
-
-  VLO INST1( .Z(PWR0));
-endmodule
-
-module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h300a;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
-  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
-    .CO1());
-
-  specify
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h5002;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
-
-  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut4 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40002 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
-module SLICE_14 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40003 CmdEnable16_0_a2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40003 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40004 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF4FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40005 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40006 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
-         CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(\SLICE_20/SLICE_20_K1_H1 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
-  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
-    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
-  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40012 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40014 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40017 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEE11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_30 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40018 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40023 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40022 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_33 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40024 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 LEDEN_5_i_m2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input D1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40026 XOR8MEG_3_u_0_a3_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40027 RA11_2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40026 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40027 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA5AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40029 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40028 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2DAD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40030 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40031 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFE50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40032 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3704) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, B1, A1, C0, A0, DI0, M1, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40034 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40013 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_50 ( input D1, C1, B1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40035 nRowColSel_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40013 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40036 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hABEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40038 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40039 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40040 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40040 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEE22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40041 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40042 UFMSDI_ens2_i_o2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40043 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40044 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40044 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40045 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40046 n8MEGEN_5_i_m2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hC0CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40048 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0049 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3F1D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0049 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40050 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40051 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0049 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40050 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40052 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0049 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40053 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40054 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40055 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0049 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40056 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40057 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40056 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF4F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40058 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40059 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0049 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40059 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
-    OFX0 );
-  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
-         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
-
-  lut40060 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
-  lut40061 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
-  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
-    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
-    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (C1 => OFX0) = (0:0:0,0:0:0);
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_66 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40062 nUFMCS_s_0_N_5_i_N_2L1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40063 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40064 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40065 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0066 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0066 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40067 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40068 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40069 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40070 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, C0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40071 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40072 C1WR_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40071 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40072 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
-
-  lut40073 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40074 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40073 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40074 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40075 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40076 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40075 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40076 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hACA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, C0, A0, M1, M0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
-
-  lut40077 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40013 IS_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
-
-  lut40078 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40079 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_75 ( input D1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40080 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40081 CmdLEDEN_4_u_i_a2_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40082 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40083 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40082 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40083 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40084 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40085 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40084 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40085 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40086 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40087 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40086 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40087 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40088 nRWE_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40089 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40088 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40089 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input D1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40082 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40090 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0066 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40090 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40091 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40092 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40091 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40092 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, M0_dly, CLK_dly;
-
-  lut40093 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40094 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40093 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3230) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40094 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40095 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40096 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40095 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40096 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40097 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40098 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40097 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40098 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40099 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40099 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40100 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_86 ( input D1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40101 RDQML( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40102 \un9_RA[9] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40101 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40102 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_87 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40103 UFMSDI_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40103 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40104 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input D1, C1, B1, C0, A0, M1, M0, LSR, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40105 C1WR_0_a2_0_3( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40106 nCCAS_pad_RNI01SJ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40105 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40106 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input D1, C1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40107 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40108 \un9_RA[8] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40107 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40108 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input D1, C1, B1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40109 un1_CMDWR( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40110 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40109 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCCC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40110 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40111 \un9_RA[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40112 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40111 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40112 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40113 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40114 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40113 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40114 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_93 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40115 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40040 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40115 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_94 ( input B1, A1, C0, A0, M0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
-
-  lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0066 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40116 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
-
-  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
-
-  specify
-    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD0) = (0:0:0,0:0:0);
-    (RD0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD0, 0:0:0);
-    $width (negedge RD0, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf ( input I, T, output Z, PAD, input PADI );
-
-  IB INST1( .I(PADI), .O(Z));
-  OBW INST2( .I(I), .T(T), .O(PAD));
-endmodule
-
-module Dout_0_ ( input PADDO, output Dout0 );
-
-  mjiobuf0117 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
-
-  specify
-    (PADDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0117 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module PHI2 ( output PADDI, input PHI2 );
-
-  mjiobuf0118 PHI2_pad( .Z(PADDI), .PAD(PHI2));
-
-  specify
-    (PHI2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge PHI2, 0:0:0);
-    $width (negedge PHI2, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0118 ( output Z, input PAD );
-
-  IBPD INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDO ( output PADDI, input UFMSDO );
-
-  mjiobuf0119 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
-
-  specify
-    (UFMSDO => PADDI) = (0:0:0,0:0:0);
-    $width (posedge UFMSDO, 0:0:0);
-    $width (negedge UFMSDO, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0119 ( output Z, input PAD );
-
-  IB INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDI ( input PADDO, output UFMSDI );
-
-  mjiobuf0120 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
-
-  specify
-    (PADDO => UFMSDI) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0120 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module UFMCLK ( input PADDO, output UFMCLK );
-
-  mjiobuf0120 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
-
-  specify
-    (PADDO => UFMCLK) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS ( input PADDO, output nUFMCS );
-
-  mjiobuf0120 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
-
-  specify
-    (PADDO => nUFMCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQML ( input PADDO, output RDQML );
-
-  mjiobuf0120 RDQML_pad( .I(PADDO), .PAD(RDQML));
-
-  specify
-    (PADDO => RDQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQMH ( input PADDO, output RDQMH );
-
-  mjiobuf0120 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
-
-  specify
-    (PADDO => RDQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS ( input PADDO, output nRCAS );
-
-  mjiobuf0120 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
-
-  specify
-    (PADDO => nRCAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS ( input PADDO, output nRRAS );
-
-  mjiobuf0120 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
-
-  specify
-    (PADDO => nRRAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE ( input PADDO, output nRWE );
-
-  mjiobuf0120 nRWE_pad( .I(PADDO), .PAD(nRWE));
-
-  specify
-    (PADDO => nRWE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE ( input PADDO, output RCKE );
-
-  mjiobuf0120 RCKE_pad( .I(PADDO), .PAD(RCKE));
-
-  specify
-    (PADDO => RCKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCLK ( output PADDI, input RCLK );
-
-  mjiobuf0119 RCLK_pad( .Z(PADDI), .PAD(RCLK));
-
-  specify
-    (RCLK => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RCLK, 0:0:0);
-    $width (negedge RCLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS ( input PADDO, output nRCS );
-
-  mjiobuf0120 nRCS_pad( .I(PADDO), .PAD(nRCS));
-
-  specify
-    (PADDO => nRCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
-
-  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
-
-  specify
-    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD7) = (0:0:0,0:0:0);
-    (RD7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD7, 0:0:0);
-    $width (negedge RD7, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
-
-  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
-
-  specify
-    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD6) = (0:0:0,0:0:0);
-    (RD6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD6, 0:0:0);
-    $width (negedge RD6, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
-
-  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
-
-  specify
-    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD5) = (0:0:0,0:0:0);
-    (RD5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD5, 0:0:0);
-    $width (negedge RD5, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
-
-  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
-
-  specify
-    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD4) = (0:0:0,0:0:0);
-    (RD4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD4, 0:0:0);
-    $width (negedge RD4, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
-
-  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
-
-  specify
-    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD3) = (0:0:0,0:0:0);
-    (RD3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD3, 0:0:0);
-    $width (negedge RD3, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
-
-  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
-
-  specify
-    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD2) = (0:0:0,0:0:0);
-    (RD2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD2, 0:0:0);
-    $width (negedge RD2, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
-
-  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
-
-  specify
-    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD1) = (0:0:0,0:0:0);
-    (RD1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD1, 0:0:0);
-    $width (negedge RD1, 0:0:0);
-  endspecify
-
-endmodule
-
-module RA_11_ ( input PADDO, output RA11 );
-
-  mjiobuf0120 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
-
-  specify
-    (PADDO => RA11) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10_ ( input PADDO, output RA10 );
-
-  mjiobuf0120 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
-
-  specify
-    (PADDO => RA10) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_9_ ( input PADDO, output RA9 );
-
-  mjiobuf0120 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
-
-  specify
-    (PADDO => RA9) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_8_ ( input PADDO, output RA8 );
-
-  mjiobuf0120 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
-
-  specify
-    (PADDO => RA8) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_7_ ( input PADDO, output RA7 );
-
-  mjiobuf0120 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
-
-  specify
-    (PADDO => RA7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_6_ ( input PADDO, output RA6 );
-
-  mjiobuf0120 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
-
-  specify
-    (PADDO => RA6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_5_ ( input PADDO, output RA5 );
-
-  mjiobuf0120 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
-
-  specify
-    (PADDO => RA5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_4_ ( input PADDO, output RA4 );
-
-  mjiobuf0120 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
-
-  specify
-    (PADDO => RA4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_3_ ( input PADDO, output RA3 );
-
-  mjiobuf0120 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
-
-  specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2_ ( input PADDO, output RA2 );
-
-  mjiobuf0120 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
-
-  specify
-    (PADDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_1_ ( input PADDO, output RA1 );
-
-  mjiobuf0120 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
-
-  specify
-    (PADDO => RA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_0_ ( input PADDO, output RA0 );
-
-  mjiobuf0120 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
-
-  specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1_ ( input PADDO, output RBA1 );
-
-  mjiobuf0120 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
-
-  specify
-    (PADDO => RBA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_0_ ( input PADDO, output RBA0 );
-
-  mjiobuf0120 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
-
-  specify
-    (PADDO => RBA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module LED ( input PADDO, output LED );
-
-  mjiobuf0121 LED_pad( .I(PADDO), .PAD(LED));
-
-  specify
-    (PADDO => LED) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0121 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module nFWE ( output PADDI, input nFWE );
-
-  mjiobuf0119 nFWE_pad( .Z(PADDI), .PAD(nFWE));
-
-  specify
-    (nFWE => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nFWE, 0:0:0);
-    $width (negedge nFWE, 0:0:0);
-  endspecify
-
-endmodule
-
-module nCRAS ( output PADDI, input nCRAS );
-
-  mjiobuf0122 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
-
-  specify
-    (nCRAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCRAS, 0:0:0);
-    $width (negedge nCRAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0122 ( output Z, input PAD );
-
-  IBPU INST1( .I(PAD), .O(Z));
-endmodule
-
-module nCCAS ( output PADDI, input nCCAS );
-
-  mjiobuf0122 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
-
-  specify
-    (nCCAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCCAS, 0:0:0);
-    $width (negedge nCCAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_7_ ( input PADDO, output Dout7 );
-
-  mjiobuf0117 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
-
-  specify
-    (PADDO => Dout7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_6_ ( input PADDO, output Dout6 );
-
-  mjiobuf0117 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
-
-  specify
-    (PADDO => Dout6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_5_ ( input PADDO, output Dout5 );
-
-  mjiobuf0117 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
-
-  specify
-    (PADDO => Dout5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_4_ ( input PADDO, output Dout4 );
-
-  mjiobuf0117 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
-
-  specify
-    (PADDO => Dout4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input PADDO, output Dout3 );
-
-  mjiobuf0117 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
-
-  specify
-    (PADDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input PADDO, output Dout2 );
-
-  mjiobuf0117 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
-
-  specify
-    (PADDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input PADDO, output Dout1 );
-
-  mjiobuf0117 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
-
-  specify
-    (PADDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7_ ( output PADDI, input Din7 );
-
-  mjiobuf0119 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
-
-  specify
-    (Din7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din7, 0:0:0);
-    $width (negedge Din7, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6_ ( output PADDI, input Din6 );
-
-  mjiobuf0119 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
-
-  specify
-    (Din6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din6, 0:0:0);
-    $width (negedge Din6, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5_ ( output PADDI, input Din5 );
-
-  mjiobuf0119 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
-
-  specify
-    (Din5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din5, 0:0:0);
-    $width (negedge Din5, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4_ ( output PADDI, input Din4 );
-
-  mjiobuf0119 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
-
-  specify
-    (Din4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din4, 0:0:0);
-    $width (negedge Din4, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3_ ( output PADDI, input Din3 );
-
-  mjiobuf0119 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
-
-  specify
-    (Din3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din3, 0:0:0);
-    $width (negedge Din3, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2_ ( output PADDI, input Din2 );
-
-  mjiobuf0119 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
-
-  specify
-    (Din2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din2, 0:0:0);
-    $width (negedge Din2, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_1_ ( output PADDI, input Din1 );
-
-  mjiobuf0119 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
-
-  specify
-    (Din1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din1, 0:0:0);
-    $width (negedge Din1, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_0_ ( output PADDI, input Din0 );
-
-  mjiobuf0119 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
-
-  specify
-    (Din0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din0, 0:0:0);
-    $width (negedge Din0, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_1_ ( output PADDI, input CROW1 );
-
-  mjiobuf0119 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
-
-  specify
-    (CROW1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW1, 0:0:0);
-    $width (negedge CROW1, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_0_ ( output PADDI, input CROW0 );
-
-  mjiobuf0119 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
-
-  specify
-    (CROW0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW0, 0:0:0);
-    $width (negedge CROW0, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_9_ ( output PADDI, input MAin9 );
-
-  mjiobuf0119 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
-
-  specify
-    (MAin9 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin9, 0:0:0);
-    $width (negedge MAin9, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_8_ ( output PADDI, input MAin8 );
-
-  mjiobuf0119 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
-
-  specify
-    (MAin8 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin8, 0:0:0);
-    $width (negedge MAin8, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_7_ ( output PADDI, input MAin7 );
-
-  mjiobuf0119 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
-
-  specify
-    (MAin7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin7, 0:0:0);
-    $width (negedge MAin7, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_6_ ( output PADDI, input MAin6 );
-
-  mjiobuf0119 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
-
-  specify
-    (MAin6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin6, 0:0:0);
-    $width (negedge MAin6, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_5_ ( output PADDI, input MAin5 );
-
-  mjiobuf0119 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
-
-  specify
-    (MAin5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin5, 0:0:0);
-    $width (negedge MAin5, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_4_ ( output PADDI, input MAin4 );
-
-  mjiobuf0119 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
-
-  specify
-    (MAin4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin4, 0:0:0);
-    $width (negedge MAin4, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_3_ ( output PADDI, input MAin3 );
-
-  mjiobuf0119 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
-
-  specify
-    (MAin3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin3, 0:0:0);
-    $width (negedge MAin3, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_2_ ( output PADDI, input MAin2 );
-
-  mjiobuf0119 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
-
-  specify
-    (MAin2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin2, 0:0:0);
-    $width (negedge MAin2, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_1_ ( output PADDI, input MAin1 );
-
-  mjiobuf0119 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
-
-  specify
-    (MAin1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin1, 0:0:0);
-    $width (negedge MAin1, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_0_ ( output PADDI, input MAin0 );
-
-  mjiobuf0119 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
-
-  specify
-    (MAin0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin0, 0:0:0);
-    $width (negedge MAin0, 0:0:0);
-  endspecify
-
-endmodule
+
+// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_vo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd 
+// Netlist created on Sat Aug 19 20:53:19 2023
+// Netlist written on Sat Aug 19 20:53:33 2023
+// Design is for device LCMXO256C
+// Design is for package TQFP100
+// Design is for performance grade 3
+
+`timescale 1 ns / 1 ps
+
+module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
+                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
+                UFMCLK, UFMSDI, UFMSDO );
+  input  PHI2;
+  input  [9:0] MAin;
+  input  [1:0] CROW;
+  input  [7:0] Din;
+  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
+  output [7:0] Dout;
+  output LED;
+  output [1:0] RBA;
+  output [11:0] RA;
+  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
+  inout  [7:0] RD;
+  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
+         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
+         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
+         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
+         \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, CmdEnable17_0_a2_3, 
+         \MAin_c[0] , N_147, ADSubmitted, CmdEnable17, CmdEnable16, C1WR_0_a2, 
+         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
+         \MAin_c[1] , C1Submitted, C1Submitted_RNO, RASr2, \S[1] , CO0, 
+         \IS[3] , N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
+         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_133, N_152, N_132, 
+         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, InitReady, PHI2r3, 
+         PHI2r2, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
+         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
+         \IS[0] , N_160, N_155, Ready, N_64_i_i, N_24, \IS[1] , \IS[2] , 
+         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, N_51, 
+         UFMSDI_ens2_i_a2_4_2, InitReady3, N_461_0, UFMSDI_ens2_i_a0, nCRAS_c, 
+         CBR, UFMSDO_c, N_70, N_33, LED_c, un1_Din_4, XOR8MEG, \Din_c[6] , 
+         RA11_2, Ready_fast, \RA_c[11] , N_171, CASr2, FWEr_fast, 
+         RCKEEN_8_u_0_0, RCKEEN_8_u_1, RCKEEN_8, PHI2r, RCKEEN, RASr3, RASr, 
+         RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, 
+         Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, 
+         UFMCLK_r_i_a2_2_2, UFMCLK_c, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, N_139_i, 
+         UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \MAin_c[4] , 
+         nRowColSel, \RowA[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , 
+         \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , \Din_c[7] , 
+         \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[0] , \Din_c[2] , 
+         \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, 
+         g0_1, nRCAS_0_sqmuxa_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, 
+         N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, m18_0_a2_1, FWEr, 
+         G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, 
+         nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, 
+         \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , 
+         N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , 
+         C1WR_0_a2_0_10, \Bank[1] , \MAin_c[6] , \MAin_c[7] , C1WR_0_a2_0_3, 
+         \Bank[3] , \Bank[4] , C1WR_0_a2_0_4, UFMSDI_ens2_i_o2_0_3, 
+         \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, 
+         CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , 
+         \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , 
+         \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, 
+         RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , 
+         \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , 
+         \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
+         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
+
+  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
+    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
+  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
+  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
+  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
+  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
+  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
+    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
+  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
+    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
+  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
+    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
+  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
+    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
+  SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(CmdEnable17_0_a2_3), 
+    .B1(\MAin_c[0] ), .A1(N_147), .D0(ADSubmitted), .C0(CmdEnable17), 
+    .B0(CmdEnable16), .A0(C1WR_0_a2), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
+    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
+  SLICE_14 SLICE_14( .D1(CmdEnable16_0_a2_5), .C1(CmdEnable16_0_a2_4), 
+    .A1(N_147), .D0(\MAin_c[1] ), .C0(CmdEnable16), .B0(C1Submitted), 
+    .A0(N_147), .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), 
+    .Q0(C1Submitted), .F1(CmdEnable16));
+  SLICE_19 SLICE_19( .D1(RASr2), .C1(\S[1] ), .B1(CO0), .A1(\IS[3] ), 
+    .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
+    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(CmdEnable17), 
+    .C0(un1_CMDWR), .B0(C1Submitted), .A0(CmdEnable), .DI0(CmdEnable_s), 
+    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
+  SLICE_21 SLICE_21( .D1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_133), 
+    .C0(N_152), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
+    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
+  SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(InitReady), .B1(PHI2r3), 
+    .A1(PHI2r2), .C0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), .DI0(N_460_0), 
+    .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
+  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
+    .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), 
+    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
+    .F1(Cmdn8MEGEN_4_u_i_0));
+  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(\IS[0] ), .B1(N_160), .A1(N_155), 
+    .D0(\IS[0] ), .B0(Ready), .A0(N_155), .DI0(N_64_i_i), .CLK(RCLK_c), 
+    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
+  SLICE_30 SLICE_30( .D1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .D0(\IS[0] ), 
+    .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
+    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
+  SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), 
+    .D0(\IS[2] ), .C0(\IS[0] ), .B0(\IS[1] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
+    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
+  SLICE_32 SLICE_32( .D1(N_126), .C1(N_51), .B1(UFMSDI_ens2_i_a2_4_2), 
+    .A1(InitReady), .B0(InitReady3), .A0(InitReady), .DI0(N_461_0), 
+    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
+  SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(LEDEN), .A1(CBR), .D0(UFMSDO_c), 
+    .C0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
+    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
+  SLICE_39 SLICE_39( .D1(un1_Din_4), .A1(XOR8MEG), .D0(\Din_c[6] ), 
+    .C0(n8MEGEN), .A0(XOR8MEG), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), 
+    .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171));
+  SLICE_41 SLICE_41( .D1(CASr2), .C1(\S[1] ), .B1(CO0), .A1(FWEr_fast), 
+    .D0(CBR), .C0(Ready), .B0(RCKEEN_8_u_0_0), .A0(RCKEEN_8_u_1), 
+    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
+    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
+  SLICE_42 SLICE_42( .D1(\IS[0] ), .C1(RASr2), .B1(\IS[2] ), .A1(\IS[1] ), 
+    .D0(RCKEEN), .C0(RASr3), .B0(RASr), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), 
+    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
+  SLICE_43 SLICE_43( .D1(InitReady), .C1(RASr2), .B1(Ready), 
+    .A1(\S_0_i_o2[1] ), .D0(InitReady), .C0(Ready), .B0(N_165), 
+    .A0(Ready_0_sqmuxa_0_a3_2), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), 
+    .F0(N_462_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
+  SLICE_44 SLICE_44( .D1(Ready), .C1(InitReady), .B1(Ready_0_sqmuxa_0_a3_2), 
+    .A1(N_165), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), 
+    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
+    .F1(Ready_0_sqmuxa), .Q1(RASr));
+  SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .B1(\S[1] ), .C0(CO0), .A0(\S[1] ), 
+    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
+    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
+  SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(N_129), .B1(InitReady), 
+    .A1(UFMCLK_r_i_a2_2_2), .D0(UFMCLK_c), .C0(UFMCLK_r_i_m4_xx_mm_1), 
+    .B0(nUFMCS15), .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), 
+    .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
+  SLICE_52 SLICE_52( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), 
+    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), 
+    .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
+    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
+  SLICE_55 SLICE_55( .D0(\MAin_c[4] ), .B0(nRowColSel), .A0(\RowA[4] ), 
+    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
+    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
+  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
+    .A1(\Bank[2] ), .D0(\FS[5] ), .C0(\FS[9] ), .B0(\FS[7] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
+    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
+  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[3] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), 
+    .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), 
+    .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
+  SLICE_58 SLICE_58( .D1(N_51), .C1(InitReady), .A1(\FS[8] ), .D0(UFMSDO_c), 
+    .C0(InitReady), .B0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
+    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
+  SLICE_59 SLICE_59( .D1(N_155), .C1(\S[1] ), .B1(Ready), .A1(N_160), 
+    .D0(N_41), .C0(\S[1] ), .B0(g0_1), .A0(nRCAS_0_sqmuxa_1), .DI0(N_37_i), 
+    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
+  SLICE_60 SLICE_60( .D1(FWEr_fast), .C1(CO0), .B1(CASr2), .A1(CASr3), 
+    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
+    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
+  SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(RCKE_c), .B1(Ready), .A1(RASr2), 
+    .D0(\IS[0] ), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(N_160), .DI0(N_24_i), 
+    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
+  SLICE_62 SLICE_62( .D1(RASr2), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(CBR_fast), 
+    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(FWEr), .A0(G_17_1), 
+    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
+    .F1(nRCAS_0_sqmuxa_1));
+  SLICE_63 SLICE_63( .D1(FWEr), .C1(CASr3), .B1(Ready), .A1(CBR), .D0(\S[1] ), 
+    .C0(N_179), .B0(Ready), .A0(CO0), .DI0(nRowColSel_0_0), 
+    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
+    .F1(N_179));
+  SLICE_64 SLICE_64( .D1(\FS[11] ), .C1(InitReady), .B1(N_51), .A1(\FS[10] ), 
+    .D0(N_139_i), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(nUFMCS_s_0_N_5_i_N_2L1), 
+    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
+    .F1(nUFMCS15));
+  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(\S[1] ), .B1(CO0), 
+    .A1(RCKE_c), .D0(m18_0_a3_3), .C0(\S[1] ), .B0(CO0), .A0(InitReady), 
+    .M0(Ready), .OFX0(m18_0_a2_1));
+  SLICE_66 SLICE_66( .D1(CmdUFMCS), .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), 
+    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
+    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
+    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
+  SLICE_67 SLICE_67( .D1(N_128), .C1(\Din_c[3] ), .B1(\Din_c[5] ), 
+    .A1(XOR8MEG18), .D0(CmdEnable), .C0(\MAin_c[0] ), .B0(\MAin_c[1] ), 
+    .A0(N_147), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
+    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
+    .Q1(\RowA[5] ));
+  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[2] ), .B1(\FS[0] ), .A1(\FS[3] ), 
+    .D0(N_137_8), .C0(N_136), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), 
+    .F1(un1_FS_14_i_a2_0_1));
+  SLICE_69 SLICE_69( .D1(\FS[0] ), .C1(\FS[3] ), .B1(\FS[5] ), .A1(\FS[2] ), 
+    .D0(N_137_8), .C0(N_136), .B0(N_137_6), .A0(un1_FS_13_i_a2_1), .F0(N_33), 
+    .F1(un1_FS_13_i_a2_1));
+  SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), 
+    .A1(\Bank[1] ), .C0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
+    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
+    .Q1(\Bank[1] ));
+  SLICE_71 SLICE_71( .D1(\MAin_c[6] ), .C1(\MAin_c[7] ), .B1(\MAin_c[4] ), 
+    .A1(\MAin_c[5] ), .D0(C1WR_0_a2_0_3), .C0(\Bank[3] ), .B0(\Bank[4] ), 
+    .A0(C1WR_0_a2_0_4), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
+    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
+  SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), 
+    .D0(\FS[4] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
+    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
+    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
+  SLICE_73 SLICE_73( .D1(InitReady), .C1(\S[1] ), .B1(RASr2), .A1(CO0), 
+    .C0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
+    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
+    .F1(N_155), .Q1(CmdUFMCS));
+  SLICE_74 SLICE_74( .B1(\FS[11] ), .A1(\FS[14] ), .D0(N_95_5), .C0(N_95_3), 
+    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
+    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
+  SLICE_75 SLICE_75( .D1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
+    .D0(\Din_c[1] ), .C0(N_128), .B0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), 
+    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
+  SLICE_76 SLICE_76( .D1(\Din_c[0] ), .B1(\Din_c[5] ), .D0(\MAin_c[0] ), 
+    .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), 
+    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
+    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
+  SLICE_77 SLICE_77( .D1(\Din_c[4] ), .A1(\Din_c[7] ), .D0(\Din_c[6] ), 
+    .C0(\MAin_c[1] ), .B0(CmdEnable16_1), .A0(\Din_c[2] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
+    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
+  SLICE_78 SLICE_78( .D1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), 
+    .C0(N_43), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), 
+    .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast));
+  SLICE_79 SLICE_79( .D1(CASr3), .B1(CASr2), .A1(Ready), .D0(CO0), .C0(\S[1] ), 
+    .B0(m6_0_a2_2), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(nCCAS_c), 
+    .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
+  SLICE_80 SLICE_80( .D1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CO0), 
+    .B0(g4_0_0_0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
+    .Q1(\RowA[9] ));
+  SLICE_81 SLICE_81( .D1(\FS[13] ), .C1(\FS[14] ), .B1(\FS[15] ), 
+    .A1(\FS[17] ), .D0(\FS[13] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[12] ), 
+    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
+    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
+  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(N_128), .B1(CmdLEDEN), 
+    .A1(\Din_c[5] ), .D0(XOR8MEG18), .C0(\Din_c[3] ), .B0(N_128), 
+    .A0(\Din_c[5] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), 
+    .Q0(CASr3), .F1(N_132));
+  SLICE_83 SLICE_83( .C1(\IS[1] ), .B1(\IS[3] ), .A1(\IS[2] ), .C0(\IS[1] ), 
+    .B0(\IS[0] ), .A0(\IS[2] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
+    .Q1(\RBA_c[1] ));
+  SLICE_84 SLICE_84( .D1(\FS[6] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[8] ), 
+    .D0(\FS[7] ), .C0(\FS[10] ), .B0(\FS[1] ), .A0(\FS[6] ), .F0(N_137_6), 
+    .F1(UFMSDI_ens2_i_a2_4_2));
+  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[0] ), .B1(\Din_c[1] ), 
+    .A1(\Din_c[7] ), .D0(\Din_c[5] ), .C0(\Din_c[4] ), .B0(\Din_c[6] ), 
+    .A0(\Din_c[7] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
+    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
+  SLICE_86 SLICE_86( .D1(nRowColSel), .A1(\MAin_c[9] ), .D0(nRowColSel), 
+    .C0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
+  SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .B1(N_151), .A1(CmdUFMSDI), 
+    .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), 
+    .F1(UFMSDI_r_xx_mm_1));
+  SLICE_88 SLICE_88( .D1(\MAin_c[2] ), .C1(nFWE_c), .B1(\MAin_c[3] ), 
+    .C0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
+    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
+  SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), 
+    .B0(\MAin_c[8] ), .A0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
+  SLICE_90 SLICE_90( .D1(\MAin_c[0] ), .C1(\MAin_c[1] ), .B1(N_147), 
+    .D0(\MAin_c[0] ), .B0(\RowA[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), 
+    .F1(un1_CMDWR));
+  SLICE_91 SLICE_91( .D1(\MAin_c[7] ), .C1(nRowColSel), .A1(\RowA[7] ), 
+    .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), 
+    .F1(\RA_c[7] ));
+  SLICE_92 SLICE_92( .D1(\RowA[6] ), .C1(nRowColSel), .A1(\MAin_c[6] ), 
+    .D0(\MAin_c[2] ), .C0(nRowColSel), .B0(\RowA[2] ), .F0(\RA_c[2] ), 
+    .F1(\RA_c[6] ));
+  SLICE_93 SLICE_93( .C1(\MAin_c[5] ), .B1(\RowA[5] ), .A1(nRowColSel), 
+    .D0(\MAin_c[3] ), .B0(nRowColSel), .A0(\RowA[3] ), .F0(\RA_c[3] ), 
+    .F1(\RA_c[5] ));
+  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .C0(\S[1] ), .A0(Ready), 
+    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
+    .Q0(\RA_c[10] ), .F1(N_159_i));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
+    .RD0(RD[0]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
+  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
+  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
+  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
+  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
+  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
+  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
+  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
+  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
+  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
+  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
+  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
+  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
+    .RD7(RD[7]));
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
+    .RD6(RD[6]));
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
+    .RD5(RD[5]));
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
+    .RD4(RD[4]));
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
+    .RD3(RD[3]));
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
+    .RD2(RD[2]));
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
+    .RD1(RD[1]));
+  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
+  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
+  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
+  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
+  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
+  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
+  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
+  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
+  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
+  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
+  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
+  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
+  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
+  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
+  LED LED_I( .PADDO(LED_c), .LED(LED));
+  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
+  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
+  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
+  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
+  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
+  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
+  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
+  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
+  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
+  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
+  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
+  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
+  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
+  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
+  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
+  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
+  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
+  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
+  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
+  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
+  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
+  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
+  VHI VHI_INST( .Z(VCCI));
+  PUR PUR_INST( .PUR(VCCI));
+  GSR GSR_INST( .GSR(VCCI));
+  VLO VLO_INST( .Z(GNDI_TSALL));
+  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
+endmodule
+
+module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
+         A1_dly, CLK_dly, A0_dly;
+
+  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
+    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+  endspecify
+
+endmodule
+
+module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module vcc ( output PWR1 );
+
+  VHI INST1( .Z(PWR1));
+endmodule
+
+module gnd ( output PWR0 );
+
+  VLO INST1( .Z(PWR0));
+endmodule
+
+module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h300a;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
+  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
+    .CO1());
+
+  specify
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h5002;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
+
+  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40002 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module inverter ( input I, output Z );
+
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module SLICE_14 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40003 CmdEnable16_0_a2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40004 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF4FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40005 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40006 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
+  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
+         CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(\SLICE_20/SLICE_20_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
+  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
+    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40009 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40010 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40011 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40012 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40013 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40014 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEE11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_30 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40018 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40020 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40023 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40024 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40025 LEDEN_5_i_m2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40025 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_39 ( input D1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40026 XOR8MEG_3_u_0_a3_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40027 RA11_2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA5AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40028 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40029 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2DAD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40030 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40031 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFE50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40032 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40032 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3704) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40033 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_44 ( input D1, C1, B1, A1, C0, A0, DI0, M1, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40034 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40034 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_50 ( input D1, C1, B1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40035 nRowColSel_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40013 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40035 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40036 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40037 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40036 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hABEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40037 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40038 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40039 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40038 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40039 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40040 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40040 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEE22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40041 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40042 UFMSDI_ens2_i_o2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40041 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40042 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40043 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40044 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40044 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_58 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40045 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40046 n8MEGEN_5_i_m2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40045 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40046 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hC0CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40048 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0049 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40047 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3F1D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40048 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0049 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40050 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40051 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0049 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40050 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40051 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40052 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40053 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0049 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40053 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40054 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40055 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0049 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40054 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40055 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40056 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40057 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40056 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF4F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40058 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40059 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0049 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40058 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40059 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
+         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
+
+  lut40060 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
+  lut40061 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
+  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
+    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
+    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40061 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_66 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40062 nUFMCS_s_0_N_5_i_N_2L1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40063 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40062 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40063 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40064 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40065 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0066 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40064 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40065 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0066 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40067 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40068 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40067 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40068 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40069 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40070 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40070 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_70 ( input D1, C1, B1, A1, C0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40071 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40072 C1WR_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40071 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40072 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
+
+  lut40073 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40074 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40073 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40074 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40075 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40076 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40075 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40076 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hACA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_73 ( input D1, C1, B1, A1, C0, A0, M1, M0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
+
+  lut40077 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 IS_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40077 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+
+  lut40078 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40079 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40078 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40079 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_75 ( input D1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40080 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40081 CmdLEDEN_4_u_i_a2_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40080 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40081 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40082 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40083 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40082 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40083 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_77 ( input D1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40084 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40085 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40084 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40085 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_78 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40086 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40087 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40086 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40087 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40088 nRWE_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40089 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40088 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40089 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input D1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40082 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40090 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0066 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40090 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40091 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40092 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40091 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40092 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, M0_dly, CLK_dly;
+
+  lut40093 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40094 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40093 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3230) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40094 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40095 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40096 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40095 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40096 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40097 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40098 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40097 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40098 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40099 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40100 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40099 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40100 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_86 ( input D1, A1, D0, C0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40101 RDQML( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40102 \un9_RA[9] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40101 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40102 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_87 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40103 UFMSDI_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40104 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40103 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40104 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_88 ( input D1, C1, B1, C0, A0, M1, M0, LSR, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40105 C1WR_0_a2_0_3( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40106 nCCAS_pad_RNI01SJ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40105 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40106 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_89 ( input D1, C1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40107 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40108 \un9_RA[8] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40107 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40108 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_90 ( input D1, C1, B1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40109 un1_CMDWR( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40110 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40109 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCCC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40110 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_91 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40111 \un9_RA[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40112 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40111 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40112 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40113 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40114 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40113 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40114 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_93 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40115 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40040 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40115 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_94 ( input B1, A1, C0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
+
+  lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40072 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0066 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40116 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
+
+  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
+
+  specify
+    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD0) = (0:0:0,0:0:0);
+    (RD0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD0, 0:0:0);
+    $width (negedge RD0, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf ( input I, T, output Z, PAD, input PADI );
+
+  IB INST1( .I(PADI), .O(Z));
+  OBW INST2( .I(I), .T(T), .O(PAD));
+endmodule
+
+module Dout_0_ ( input PADDO, output Dout0 );
+
+  mjiobuf0117 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+
+  specify
+    (PADDO => Dout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0117 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module PHI2 ( output PADDI, input PHI2 );
+
+  mjiobuf0118 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+
+  specify
+    (PHI2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge PHI2, 0:0:0);
+    $width (negedge PHI2, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0118 ( output Z, input PAD );
+
+  IBPD INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDO ( output PADDI, input UFMSDO );
+
+  mjiobuf0119 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
+
+  specify
+    (UFMSDO => PADDI) = (0:0:0,0:0:0);
+    $width (posedge UFMSDO, 0:0:0);
+    $width (negedge UFMSDO, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0119 ( output Z, input PAD );
+
+  IB INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDI ( input PADDO, output UFMSDI );
+
+  mjiobuf0120 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
+
+  specify
+    (PADDO => UFMSDI) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0120 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module UFMCLK ( input PADDO, output UFMCLK );
+
+  mjiobuf0120 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
+
+  specify
+    (PADDO => UFMCLK) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nUFMCS ( input PADDO, output nUFMCS );
+
+  mjiobuf0120 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
+
+  specify
+    (PADDO => nUFMCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQML ( input PADDO, output RDQML );
+
+  mjiobuf0120 RDQML_pad( .I(PADDO), .PAD(RDQML));
+
+  specify
+    (PADDO => RDQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQMH ( input PADDO, output RDQMH );
+
+  mjiobuf0120 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+
+  specify
+    (PADDO => RDQMH) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRCAS ( input PADDO, output nRCAS );
+
+  mjiobuf0120 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
+
+  specify
+    (PADDO => nRCAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRRAS ( input PADDO, output nRRAS );
+
+  mjiobuf0120 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
+
+  specify
+    (PADDO => nRRAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRWE ( input PADDO, output nRWE );
+
+  mjiobuf0120 nRWE_pad( .I(PADDO), .PAD(nRWE));
+
+  specify
+    (PADDO => nRWE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCKE ( input PADDO, output RCKE );
+
+  mjiobuf0120 RCKE_pad( .I(PADDO), .PAD(RCKE));
+
+  specify
+    (PADDO => RCKE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCLK ( output PADDI, input RCLK );
+
+  mjiobuf0119 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+
+  specify
+    (RCLK => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RCLK, 0:0:0);
+    $width (negedge RCLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module nRCS ( input PADDO, output nRCS );
+
+  mjiobuf0120 nRCS_pad( .I(PADDO), .PAD(nRCS));
+
+  specify
+    (PADDO => nRCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
+
+  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
+
+  specify
+    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD7) = (0:0:0,0:0:0);
+    (RD7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD7, 0:0:0);
+    $width (negedge RD7, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
+
+  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
+
+  specify
+    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD6) = (0:0:0,0:0:0);
+    (RD6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD6, 0:0:0);
+    $width (negedge RD6, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
+
+  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
+
+  specify
+    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD5) = (0:0:0,0:0:0);
+    (RD5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD5, 0:0:0);
+    $width (negedge RD5, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
+
+  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
+
+  specify
+    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD4) = (0:0:0,0:0:0);
+    (RD4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD4, 0:0:0);
+    $width (negedge RD4, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
+
+  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
+
+  specify
+    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD3) = (0:0:0,0:0:0);
+    (RD3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD3, 0:0:0);
+    $width (negedge RD3, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
+
+  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
+
+  specify
+    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD2) = (0:0:0,0:0:0);
+    (RD2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD2, 0:0:0);
+    $width (negedge RD2, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
+
+  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
+
+  specify
+    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD1) = (0:0:0,0:0:0);
+    (RD1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD1, 0:0:0);
+    $width (negedge RD1, 0:0:0);
+  endspecify
+
+endmodule
+
+module RA_11_ ( input PADDO, output RA11 );
+
+  mjiobuf0120 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
+
+  specify
+    (PADDO => RA11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_10_ ( input PADDO, output RA10 );
+
+  mjiobuf0120 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
+
+  specify
+    (PADDO => RA10) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_9_ ( input PADDO, output RA9 );
+
+  mjiobuf0120 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+
+  specify
+    (PADDO => RA9) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_8_ ( input PADDO, output RA8 );
+
+  mjiobuf0120 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+
+  specify
+    (PADDO => RA8) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_7_ ( input PADDO, output RA7 );
+
+  mjiobuf0120 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+
+  specify
+    (PADDO => RA7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_6_ ( input PADDO, output RA6 );
+
+  mjiobuf0120 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+
+  specify
+    (PADDO => RA6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_5_ ( input PADDO, output RA5 );
+
+  mjiobuf0120 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+
+  specify
+    (PADDO => RA5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_4_ ( input PADDO, output RA4 );
+
+  mjiobuf0120 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+
+  specify
+    (PADDO => RA4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_3_ ( input PADDO, output RA3 );
+
+  mjiobuf0120 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+
+  specify
+    (PADDO => RA3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_2_ ( input PADDO, output RA2 );
+
+  mjiobuf0120 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+
+  specify
+    (PADDO => RA2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_1_ ( input PADDO, output RA1 );
+
+  mjiobuf0120 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+
+  specify
+    (PADDO => RA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_0_ ( input PADDO, output RA0 );
+
+  mjiobuf0120 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+
+  specify
+    (PADDO => RA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_1_ ( input PADDO, output RBA1 );
+
+  mjiobuf0120 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
+
+  specify
+    (PADDO => RBA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_0_ ( input PADDO, output RBA0 );
+
+  mjiobuf0120 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
+
+  specify
+    (PADDO => RBA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module LED ( input PADDO, output LED );
+
+  mjiobuf0121 LED_pad( .I(PADDO), .PAD(LED));
+
+  specify
+    (PADDO => LED) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0121 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module nFWE ( output PADDI, input nFWE );
+
+  mjiobuf0119 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+
+  specify
+    (nFWE => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nFWE, 0:0:0);
+    $width (negedge nFWE, 0:0:0);
+  endspecify
+
+endmodule
+
+module nCRAS ( output PADDI, input nCRAS );
+
+  mjiobuf0122 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+
+  specify
+    (nCRAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCRAS, 0:0:0);
+    $width (negedge nCRAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0122 ( output Z, input PAD );
+
+  IBPU INST1( .I(PAD), .O(Z));
+endmodule
+
+module nCCAS ( output PADDI, input nCCAS );
+
+  mjiobuf0122 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+
+  specify
+    (nCCAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCCAS, 0:0:0);
+    $width (negedge nCCAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_7_ ( input PADDO, output Dout7 );
+
+  mjiobuf0117 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+
+  specify
+    (PADDO => Dout7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_6_ ( input PADDO, output Dout6 );
+
+  mjiobuf0117 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+
+  specify
+    (PADDO => Dout6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_5_ ( input PADDO, output Dout5 );
+
+  mjiobuf0117 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+
+  specify
+    (PADDO => Dout5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_4_ ( input PADDO, output Dout4 );
+
+  mjiobuf0117 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+
+  specify
+    (PADDO => Dout4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_3_ ( input PADDO, output Dout3 );
+
+  mjiobuf0117 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+
+  specify
+    (PADDO => Dout3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_2_ ( input PADDO, output Dout2 );
+
+  mjiobuf0117 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+
+  specify
+    (PADDO => Dout2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_1_ ( input PADDO, output Dout1 );
+
+  mjiobuf0117 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+
+  specify
+    (PADDO => Dout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Din_7_ ( output PADDI, input Din7 );
+
+  mjiobuf0119 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+
+  specify
+    (Din7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din7, 0:0:0);
+    $width (negedge Din7, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_6_ ( output PADDI, input Din6 );
+
+  mjiobuf0119 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+
+  specify
+    (Din6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din6, 0:0:0);
+    $width (negedge Din6, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_5_ ( output PADDI, input Din5 );
+
+  mjiobuf0119 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+
+  specify
+    (Din5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din5, 0:0:0);
+    $width (negedge Din5, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_4_ ( output PADDI, input Din4 );
+
+  mjiobuf0119 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+
+  specify
+    (Din4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din4, 0:0:0);
+    $width (negedge Din4, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_3_ ( output PADDI, input Din3 );
+
+  mjiobuf0119 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+
+  specify
+    (Din3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din3, 0:0:0);
+    $width (negedge Din3, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_2_ ( output PADDI, input Din2 );
+
+  mjiobuf0119 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+
+  specify
+    (Din2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din2, 0:0:0);
+    $width (negedge Din2, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_1_ ( output PADDI, input Din1 );
+
+  mjiobuf0119 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+
+  specify
+    (Din1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din1, 0:0:0);
+    $width (negedge Din1, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_0_ ( output PADDI, input Din0 );
+
+  mjiobuf0119 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+
+  specify
+    (Din0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din0, 0:0:0);
+    $width (negedge Din0, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_1_ ( output PADDI, input CROW1 );
+
+  mjiobuf0119 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+
+  specify
+    (CROW1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW1, 0:0:0);
+    $width (negedge CROW1, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_0_ ( output PADDI, input CROW0 );
+
+  mjiobuf0119 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+
+  specify
+    (CROW0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW0, 0:0:0);
+    $width (negedge CROW0, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_9_ ( output PADDI, input MAin9 );
+
+  mjiobuf0119 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+
+  specify
+    (MAin9 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin9, 0:0:0);
+    $width (negedge MAin9, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_8_ ( output PADDI, input MAin8 );
+
+  mjiobuf0119 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+
+  specify
+    (MAin8 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin8, 0:0:0);
+    $width (negedge MAin8, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_7_ ( output PADDI, input MAin7 );
+
+  mjiobuf0119 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+
+  specify
+    (MAin7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin7, 0:0:0);
+    $width (negedge MAin7, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_6_ ( output PADDI, input MAin6 );
+
+  mjiobuf0119 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+
+  specify
+    (MAin6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin6, 0:0:0);
+    $width (negedge MAin6, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_5_ ( output PADDI, input MAin5 );
+
+  mjiobuf0119 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+
+  specify
+    (MAin5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin5, 0:0:0);
+    $width (negedge MAin5, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_4_ ( output PADDI, input MAin4 );
+
+  mjiobuf0119 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+
+  specify
+    (MAin4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin4, 0:0:0);
+    $width (negedge MAin4, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_3_ ( output PADDI, input MAin3 );
+
+  mjiobuf0119 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+
+  specify
+    (MAin3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin3, 0:0:0);
+    $width (negedge MAin3, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_2_ ( output PADDI, input MAin2 );
+
+  mjiobuf0119 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+
+  specify
+    (MAin2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin2, 0:0:0);
+    $width (negedge MAin2, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_1_ ( output PADDI, input MAin1 );
+
+  mjiobuf0119 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+
+  specify
+    (MAin1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin1, 0:0:0);
+    $width (negedge MAin1, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_0_ ( output PADDI, input MAin0 );
+
+  mjiobuf0119 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+
+  specify
+    (MAin0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin0, 0:0:0);
+    $width (negedge MAin0, 0:0:0);
+  endspecify
+
+endmodule
diff --git a/CPLD/LCMXO256C/impl1/automake.log b/CPLD/LCMXO256C/impl1/automake.log
index 68dd2e3..86f7796 100644
--- a/CPLD/LCMXO256C/impl1/automake.log
+++ b/CPLD/LCMXO256C/impl1/automake.log
@@ -1,2244 +1,490 @@
 
-synpwrap -msg -prj "RAM2GS_LCMXO256C_impl1_synplify.tcl" -log "RAM2GS_LCMXO256C_impl1.srf"
-Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved.
-Lattice Diamond Version 3.12.1.454
-    
-
-==contents of RAM2GS_LCMXO256C_impl1.srf
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:31 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:32 2023
-
-###########################################################]
-# Wed Aug 16 04:50:33 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
-
-###########################################################]
-# Wed Aug 16 04:50:35 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:01s		    -2.99ns		 127 /        92
-   9		0h:00m:01s		    -3.09ns		 127 /        92
-  10		0h:00m:01s		    -3.19ns		 127 /        92
-  11		0h:00m:01s		    -3.19ns		 127 /        92
-  12		0h:00m:01s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-
-Synthesis exit by 0.
-
-edif2ngd  -l "MachXO" -d LCMXO256C -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1" -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C"   "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi" "RAM2GS_LCMXO256C_impl1.ngo"   
-edif2ngd:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Writing the design to RAM2GS_LCMXO256C_impl1.ngo...
-
-Total CPU Time: 0 secs  
-Total REAL Time: 0 secs  
-Peak Memory Usage: 11 MB
-
-
-ngdbuild  -a "MachXO" -d LCMXO256C  -p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data"  -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1" -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C"  "RAM2GS_LCMXO256C_impl1.ngo" "RAM2GS_LCMXO256C_impl1.ngd"  	
-ngdbuild:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Reading 'RAM2GS_LCMXO256C_impl1.ngo' ...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-
-Design Results:
-    300 blocks expanded
-Complete the first expansion.
-Writing 'RAM2GS_LCMXO256C_impl1.ngd' ...
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 18 MB
-
-
-map -a "MachXO" -p LCMXO256C -t TQFP100 -s 3 -oc Commercial  -ioreg b "RAM2GS_LCMXO256C_impl1.ngd" -o "RAM2GS_LCMXO256C_impl1_map.ncd" -pr "RAM2GS_LCMXO256C_impl1.prf" -mp "RAM2GS_LCMXO256C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf"  -c 0           
-map:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-   Process the file: RAM2GS_LCMXO256C_impl1.ngd
-   Picdevice="LCMXO256C"
-
-   Pictype="TQFP100"
-
-   Picspeed=3
-
-   Remove unused logic
-
-   Do not produce over sized NCDs.
-
-Part used: LCMXO256CTQFP100, Performance used: 3.
-
-Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Running general design DRC...
-
-Removing unused logic...
-
-Optimizing...
-
-
-
-
-Design Summary:
-   Number of PFU registers:    92 out of   256 (36%)
-   Number of SLICEs:        69 out of   128 (54%)
-      SLICEs as Logic/ROM:     69 out of   128 (54%)
-      SLICEs as RAM:            0 out of    64 (0%)
-      SLICEs as Carry:          9 out of   128 (7%)
-   Number of LUT4s:        137 out of   256 (54%)
-      Number used as logic LUTs:        119
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 78 (86%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  5
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net N_31: 1 loads, 1 LSLICEs
-     Net N_33: 1 loads, 1 LSLICEs
-     Net N_159_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
-   Number of LSRs:  4
-     Net RA10s_i: 1 loads, 1 LSLICEs
-     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
-     Net RASr2: 2 loads, 2 LSLICEs
-     Net Ready_fast: 7 loads, 7 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net InitReady: 16 loads
-     Net Ready: 16 loads
-     Net S[1]: 13 loads
-     Net CO0: 12 loads
-     Net nRowColSel: 12 loads
-     Net RASr2: 11 loads
-     Net Din_c[5]: 10 loads
-     Net Din_c[3]: 9 loads
-     Net IS[0]: 9 loads
-     Net MAin_c[1]: 8 loads
- 
-
-   Number of warnings:  0
-   Number of errors:    0
-
-
-
-Total CPU Time: 0 secs  
-Total REAL Time: 0 secs  
-Peak Memory Usage: 29 MB
-
-Dumping design to file RAM2GS_LCMXO256C_impl1_map.ncd.
-
-ncd2eqn "RAM2GS_LCMXO256C_impl1_map.ncd"
-ncd2eqn:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Start loading RAM2GS_LCMXO256C_impl1_map.ncd.
-
-Loading design for application ncd2eqn from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application ncd2eqn from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Finish loading RAM2GS_LCMXO256C_impl1_map.ncd.
-ncd2eqn runs successfully.
-
-trce -f "RAM2GS_LCMXO256C_impl1.mt" -o "RAM2GS_LCMXO256C_impl1.tw1" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.prf"
-trce:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:40 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1_map.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:40 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1_map.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 30 MB
-
-
-ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO256C_impl1_mapvo.vo" -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format.
-Writing Verilog netlist to file RAM2GS_LCMXO256C_impl1_mapvo.vo
-Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvo.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 29 MB
-
-ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO256C_impl1_mapvho.vho" -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format.
-Writing VHDL netlist to file RAM2GS_LCMXO256C_impl1_mapvho.vho
-Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvho.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 29 MB
-
-mpartrce -p "RAM2GS_LCMXO256C_impl1.p2t" -f "RAM2GS_LCMXO256C_impl1.p3t" -tf "RAM2GS_LCMXO256C_impl1.pt" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.ncd"
-
----- MParTrce Tool ----
-Removing old design directory at request of -rem command line option to this program.
-Running par. Please wait . . .
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Wed Aug 16 04:50:41 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
-Preference file: RAM2GS_LCMXO256C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)      67/79           84% used
-                     67/78           85% bonded
-   SLICE             69/128          53% used
-
-
-
-Number of Signals: 251
-Number of Connections: 633
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 32)
-    PHI2_c (driver: PHI2, clk load #: 14)
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-.................
-Placer score = 582801.
-Finished Placer Phase 1.  REAL time: 6 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  582334
-Finished Placer Phase 2.  REAL time: 6 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 1 out of 80 (1%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 32
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 14
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 4 (50%)
-  SECONDARY: 1 out of 4 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 out of 79 (84.8%) PIO sites used.
-   67 out of 78 (85.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
-| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 5 secs 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-0 connections routed; 633 unrouted.
-Starting router resource preassignment
-    
-    
-
-    
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 04:50:47 08/16/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 04:50:47 08/16/23
-
-Start NBR section for initial routing at 04:50:47 08/16/23
-Level 1, iteration 1
-0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.405ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:47 08/16/23
-Level 4, iteration 1
-5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:47 08/16/23
-
-Start NBR section for re-routing at 04:50:47 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 04:50:47 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 8.213ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-    
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 8.213
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Exiting par with exit code 0
-Exiting mpartrce with exit code 0
-
-trce -f "RAM2GS_LCMXO256C_impl1.pt" -o "RAM2GS_LCMXO256C_impl1.twr" "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf"
-trce:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:48 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:48 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 31 MB
-
-
-iotiming  "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf"
-I/O Timing Report:
-:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application iotiming from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 3
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 4
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 5
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: M
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-Done.
-
 ibisgen "RAM2GS_LCMXO256C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
-IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
-
-Wed Aug 16 04:50:48 2023
-
-Comp: CROW[0]
- Site: 32
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: CROW[1]
- Site: 34
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[0]
- Site: 21
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[1]
- Site: 15
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[2]
- Site: 14
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[3]
- Site: 16
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[4]
- Site: 18
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[5]
- Site: 17
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[6]
- Site: 20
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[7]
- Site: 19
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Dout[0]
- Site: 1
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[1]
- Site: 7
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[2]
- Site: 8
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[3]
- Site: 6
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[4]
- Site: 4
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[5]
- Site: 5
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[6]
- Site: 2
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[7]
- Site: 3
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: LED
- Site: 57
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=14mA 
- SLEW=SLOW 
------------------------
-Comp: MAin[0]
- Site: 23
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[1]
- Site: 38
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[2]
- Site: 37
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[3]
- Site: 47
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[4]
- Site: 46
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[5]
- Site: 45
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[6]
- Site: 49
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[7]
- Site: 44
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[8]
- Site: 50
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[9]
- Site: 51
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: PHI2
- Site: 39
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=DOWN 
------------------------
-Comp: RA[0]
- Site: 98
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[10]
- Site: 87
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[11]
- Site: 79
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[1]
- Site: 89
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[2]
- Site: 94
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[3]
- Site: 97
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[4]
- Site: 99
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[5]
- Site: 95
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[6]
- Site: 91
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[7]
- Site: 100
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[8]
- Site: 96
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[9]
- Site: 85
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[0]
- Site: 63
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[1]
- Site: 83
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCKE
- Site: 82
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCLK
- Site: 86
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: RDQMH
- Site: 76
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RDQML
- Site: 61
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RD[0]
- Site: 64
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[1]
- Site: 65
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[2]
- Site: 66
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[3]
- Site: 67
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[4]
- Site: 68
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[5]
- Site: 69
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[6]
- Site: 70
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[7]
- Site: 71
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: UFMCLK
- Site: 58
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDI
- Site: 56
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDO
- Site: 55
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nCCAS
- Site: 27
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=UP 
------------------------
-Comp: nCRAS
- Site: 43
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=UP 
------------------------
-Comp: nFWE
- Site: 22
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nRCAS
- Site: 78
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRCS
- Site: 77
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRRAS
- Site: 73
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRWE
- Site: 72
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nUFMCS
- Site: 53
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Created design models.
-
-
-Generating: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
-
-
-    
-
-ldbanno "RAM2GS_LCMXO256C_impl1.ncd" -n Verilog  -o "RAM2GS_LCMXO256C_impl1_vo.vo"         -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1 design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO256C_impl1.ncd into .ldb format.
-Loading preferences from ram2gs_lcmxo256c_impl1.prf.
-Writing Verilog netlist to file RAM2GS_LCMXO256C_impl1_vo.vo
-Writing SDF timing to file RAM2GS_LCMXO256C_impl1_vo.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 31 MB
-
-ldbanno "RAM2GS_LCMXO256C_impl1.ncd" -n VHDL -o "RAM2GS_LCMXO256C_impl1_vho.vho"         -w -neg 
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1 design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO256C_impl1.ncd into .ldb format.
-Loading preferences from ram2gs_lcmxo256c_impl1.prf.
-Writing VHDL netlist to file RAM2GS_LCMXO256C_impl1_vho.vho
-Writing SDF timing to file RAM2GS_LCMXO256C_impl1_vho.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 31 MB
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
+
+Sun Aug 20 05:55:46 2023
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=14mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=DOWN 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=UP 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=UP 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
+
+
+    
diff --git a/CPLD/LCMXO256C/impl1/dm/layer0.xdm b/CPLD/LCMXO256C/impl1/dm/layer0.xdm
index 80ddd36..36c7233 100644
--- a/CPLD/LCMXO256C/impl1/dm/layer0.xdm
+++ b/CPLD/LCMXO256C/impl1/dm/layer0.xdm
@@ -1,32 +1,32 @@
-%%% protect protected_file
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-SS1S
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-S"/
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-/S<1sFkO>C#
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-S7RCVMI="F3s	).qvtP13CDsHFRo"DP="CDsHF>o"
-SqS"/
-
-
-
-
-/S<7>CV
-]sC
-
-@ 
+%%% protect protected_file
+@EG
+-
+]17p0Osk0CksRsPC#MHF=3"4j
+">
+!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
+S
+SS1S
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+/S<1sFkO>C#
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+S7RCVMI="F3s	).qvtP13CDsHFRo"DP="CDsHF>o"
+SqS"/
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+@ 
diff --git a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html
index df264d3..aab1a0b 100644
--- a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html
@@ -1,9 +1,9 @@
-         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS'
 Done: design load finished with (0) errors, and (0) warnings
 
 
    
\ No newline at end of file
diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
index 0a4c98e..fb14fcb 100644
--- a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
+++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
@@ -1,138 +1,138 @@
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo256c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Wed Aug 16 04:50:48 2023
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F    -0.006      M       1.904     3
-CROW[1] nCRAS F    -0.006      M       1.904     3
-Din[0]  PHI2  F     4.101      3       2.207     3
-Din[0]  nCCAS F     1.552      3      -0.018     M
-Din[1]  PHI2  F     2.668      3       3.026     3
-Din[1]  nCCAS F     0.606      3       0.745     3
-Din[2]  PHI2  F     2.073      3       2.917     3
-Din[2]  nCCAS F     0.500      3       0.619     3
-Din[3]  PHI2  F     2.620      3       3.334     3
-Din[3]  nCCAS F    -0.089      M       1.336     3
-Din[4]  PHI2  F     5.116      3       2.411     3
-Din[4]  nCCAS F     0.293      3       1.125     3
-Din[5]  PHI2  F     5.590      3       2.084     3
-Din[5]  nCCAS F     0.435      3       0.979     3
-Din[6]  PHI2  F     5.951      3       1.726     3
-Din[6]  nCCAS F     1.305      3       0.253     3
-Din[7]  PHI2  F     4.412      3       1.404     3
-Din[7]  nCCAS F     0.195      3       1.215     3
-MAin[0] PHI2  F     3.306      3       1.176     3
-MAin[0] nCRAS F    -0.132      M       2.336     3
-MAin[1] PHI2  F     2.656      3       2.511     3
-MAin[1] nCRAS F    -0.034      M       2.014     3
-MAin[2] PHI2  F     6.839      3      -0.310     M
-MAin[2] nCRAS F    -0.154      M       2.424     3
-MAin[3] PHI2  F     6.871      3      -0.311     M
-MAin[3] nCRAS F    -0.015      M       1.928     3
-MAin[4] PHI2  F     7.111      3      -0.361     M
-MAin[4] nCRAS F     0.370      3       1.590     3
-MAin[5] PHI2  F     7.075      3      -0.353     M
-MAin[5] nCRAS F    -0.126      M       2.320     3
-MAin[6] PHI2  F     6.794      3      -0.295     M
-MAin[6] nCRAS F     0.010      3       1.885     3
-MAin[7] PHI2  F     6.926      3      -0.324     M
-MAin[7] nCRAS F     0.319      3       1.622     3
-MAin[8] nCRAS F    -0.038      M       2.031     3
-MAin[9] nCRAS F     0.366      3       1.596     3
-PHI2    RCLK  R     2.295      3      -0.174     M
-UFMSDO  RCLK  R     1.364      3       0.511     3
-nCCAS   RCLK  R     2.300      3      -0.185     M
-nCCAS   nCRAS F     0.216      3       1.721     3
-nCRAS   RCLK  R     4.548      3      -0.507     M
-nFWE    PHI2  F     6.729      3      -0.281     M
-nFWE    nCRAS F    -0.037      M       2.025     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R     7.842         3        1.620          M
-LED    nCRAS F    10.578         3        2.158          M
-RA[0]  RCLK  R     9.531         3        1.954          M
-RA[0]  nCRAS F    11.210         3        2.276          M
-RA[10] RCLK  R     7.998         3        1.636          M
-RA[11] PHI2  R     8.837         3        1.781          M
-RA[1]  RCLK  R    11.134         3        2.285          M
-RA[1]  nCRAS F    11.588         3        2.348          M
-RA[2]  RCLK  R     8.931         3        1.827          M
-RA[2]  nCRAS F    10.718         3        2.175          M
-RA[3]  RCLK  R     9.942         3        2.025          M
-RA[3]  nCRAS F    11.459         3        2.315          M
-RA[4]  RCLK  R    10.804         3        2.199          M
-RA[4]  nCRAS F    11.949         3        2.399          M
-RA[5]  RCLK  R     9.531         3        1.954          M
-RA[5]  nCRAS F    10.353         3        2.098          M
-RA[6]  RCLK  R     8.931         3        1.827          M
-RA[6]  nCRAS F     9.961         3        2.021          M
-RA[7]  RCLK  R    10.350         3        2.117          M
-RA[7]  nCRAS F    10.579         3        2.124          M
-RA[8]  RCLK  R    10.008         3        2.034          M
-RA[8]  nCRAS F    11.368         3        2.282          M
-RA[9]  RCLK  R     9.085         3        1.845          M
-RA[9]  nCRAS F    10.306         3        2.065          M
-RBA[0] nCRAS F     8.339         3        1.684          M
-RBA[1] nCRAS F    10.066         3        2.033          M
-RCKE   RCLK  R     7.910         3        1.616          M
-RDQMH  RCLK  R     9.081         3        1.846          M
-RDQML  RCLK  R    10.003         3        2.044          M
-RD[0]  nCCAS F     8.482         3        1.831          M
-RD[1]  nCCAS F     7.771         3        1.703          M
-RD[2]  nCCAS F     8.472         3        1.830          M
-RD[3]  nCCAS F     8.468         3        1.830          M
-RD[4]  nCCAS F     8.240         3        1.804          M
-RD[5]  nCCAS F    10.703         3        2.293          M
-RD[6]  nCCAS F     8.240         3        1.804          M
-RD[7]  nCCAS F     9.407         3        2.023          M
-UFMCLK RCLK  R     7.454         3        1.510          M
-UFMSDI RCLK  R     6.271         3        1.287          M
-nRCAS  RCLK  R     7.626         3        1.553          M
-nRCS   RCLK  R     6.271         3        1.287          M
-nRRAS  RCLK  R     7.438         3        1.506          M
-nRWE   RCLK  R     6.271         3        1.287          M
-nUFMCS RCLK  R     7.914         3        1.619          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Sat Aug 19 20:53:32 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.006      M       1.904     3
+CROW[1] nCRAS F    -0.006      M       1.904     3
+Din[0]  PHI2  F     4.101      3       2.207     3
+Din[0]  nCCAS F     1.552      3      -0.018     M
+Din[1]  PHI2  F     2.668      3       3.026     3
+Din[1]  nCCAS F     0.606      3       0.745     3
+Din[2]  PHI2  F     2.073      3       2.917     3
+Din[2]  nCCAS F     0.500      3       0.619     3
+Din[3]  PHI2  F     2.620      3       3.334     3
+Din[3]  nCCAS F    -0.089      M       1.336     3
+Din[4]  PHI2  F     5.116      3       2.411     3
+Din[4]  nCCAS F     0.293      3       1.125     3
+Din[5]  PHI2  F     5.590      3       2.084     3
+Din[5]  nCCAS F     0.435      3       0.979     3
+Din[6]  PHI2  F     5.951      3       1.726     3
+Din[6]  nCCAS F     1.305      3       0.253     3
+Din[7]  PHI2  F     4.412      3       1.404     3
+Din[7]  nCCAS F     0.195      3       1.215     3
+MAin[0] PHI2  F     3.306      3       1.176     3
+MAin[0] nCRAS F    -0.132      M       2.336     3
+MAin[1] PHI2  F     2.656      3       2.511     3
+MAin[1] nCRAS F    -0.034      M       2.014     3
+MAin[2] PHI2  F     6.839      3      -0.310     M
+MAin[2] nCRAS F    -0.154      M       2.424     3
+MAin[3] PHI2  F     6.871      3      -0.311     M
+MAin[3] nCRAS F    -0.015      M       1.928     3
+MAin[4] PHI2  F     7.111      3      -0.361     M
+MAin[4] nCRAS F     0.370      3       1.590     3
+MAin[5] PHI2  F     7.075      3      -0.353     M
+MAin[5] nCRAS F    -0.126      M       2.320     3
+MAin[6] PHI2  F     6.794      3      -0.295     M
+MAin[6] nCRAS F     0.010      3       1.885     3
+MAin[7] PHI2  F     6.926      3      -0.324     M
+MAin[7] nCRAS F     0.319      3       1.622     3
+MAin[8] nCRAS F    -0.038      M       2.031     3
+MAin[9] nCRAS F     0.366      3       1.596     3
+PHI2    RCLK  R     2.295      3      -0.174     M
+UFMSDO  RCLK  R     1.364      3       0.511     3
+nCCAS   RCLK  R     2.300      3      -0.185     M
+nCCAS   nCRAS F     0.216      3       1.721     3
+nCRAS   RCLK  R     4.548      3      -0.507     M
+nFWE    PHI2  F     6.729      3      -0.281     M
+nFWE    nCRAS F    -0.037      M       2.025     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.842         3        1.620          M
+LED    nCRAS F    10.578         3        2.158          M
+RA[0]  RCLK  R     9.531         3        1.954          M
+RA[0]  nCRAS F    11.210         3        2.276          M
+RA[10] RCLK  R     7.998         3        1.636          M
+RA[11] PHI2  R     8.837         3        1.781          M
+RA[1]  RCLK  R    11.134         3        2.285          M
+RA[1]  nCRAS F    11.588         3        2.348          M
+RA[2]  RCLK  R     8.931         3        1.827          M
+RA[2]  nCRAS F    10.718         3        2.175          M
+RA[3]  RCLK  R     9.942         3        2.025          M
+RA[3]  nCRAS F    11.459         3        2.315          M
+RA[4]  RCLK  R    10.804         3        2.199          M
+RA[4]  nCRAS F    11.949         3        2.399          M
+RA[5]  RCLK  R     9.531         3        1.954          M
+RA[5]  nCRAS F    10.353         3        2.098          M
+RA[6]  RCLK  R     8.931         3        1.827          M
+RA[6]  nCRAS F     9.961         3        2.021          M
+RA[7]  RCLK  R    10.350         3        2.117          M
+RA[7]  nCRAS F    10.579         3        2.124          M
+RA[8]  RCLK  R    10.008         3        2.034          M
+RA[8]  nCRAS F    11.368         3        2.282          M
+RA[9]  RCLK  R     9.085         3        1.845          M
+RA[9]  nCRAS F    10.306         3        2.065          M
+RBA[0] nCRAS F     8.339         3        1.684          M
+RBA[1] nCRAS F    10.066         3        2.033          M
+RCKE   RCLK  R     7.910         3        1.616          M
+RDQMH  RCLK  R     9.081         3        1.846          M
+RDQML  RCLK  R    10.003         3        2.044          M
+RD[0]  nCCAS F     8.482         3        1.831          M
+RD[1]  nCCAS F     7.771         3        1.703          M
+RD[2]  nCCAS F     8.472         3        1.830          M
+RD[3]  nCCAS F     8.468         3        1.830          M
+RD[4]  nCCAS F     8.240         3        1.804          M
+RD[5]  nCCAS F    10.703         3        2.293          M
+RD[6]  nCCAS F     8.240         3        1.804          M
+RD[7]  nCCAS F     9.407         3        2.023          M
+UFMCLK RCLK  R     7.454         3        1.510          M
+UFMSDI RCLK  R     6.271         3        1.287          M
+nRCAS  RCLK  R     7.626         3        1.553          M
+nRCS   RCLK  R     6.271         3        1.287          M
+nRRAS  RCLK  R     7.438         3        1.506          M
+nRWE   RCLK  R     6.271         3        1.287          M
+nUFMCS RCLK  R     7.914         3        1.619          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
index 17468bc..fe80827 100644
--- a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
+++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
@@ -1,17 +1,17 @@
-[ActiveSupport TRCE]
-; Setup Analysis
-Fmax_0 = 56.029 MHz (2.900 MHz);
-Fmax_1 = 400.000 MHz (2.900 MHz);
-Fmax_2 = 400.000 MHz (2.900 MHz);
-Fmax_3 = 128.419 MHz (62.500 MHz);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
-; Hold Analysis
-Fmax_0 = - (-);
-Fmax_1 = - (-);
-Fmax_2 = - (-);
-Fmax_3 = - (-);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
+[ActiveSupport TRCE]
+; Setup Analysis
+Fmax_0 = 56.029 MHz (2.900 MHz);
+Fmax_1 = 400.000 MHz (2.900 MHz);
+Fmax_2 = 400.000 MHz (2.900 MHz);
+Fmax_3 = 128.419 MHz (62.500 MHz);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Fmax_0 = - (-);
+Fmax_1 = - (-);
+Fmax_2 = - (-);
+Fmax_3 = - (-);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO256C/impl1/run_options.txt b/CPLD/LCMXO256C/impl1/run_options.txt
index 7771d20..a606210 100644
--- a/CPLD/LCMXO256C/impl1/run_options.txt
+++ b/CPLD/LCMXO256C/impl1/run_options.txt
@@ -1,81 +1,81 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\run_options.txt
-#--  Written on Wed Aug 16 04:50:30 2023
-
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-
-
-#implementation: "impl1"
-impl -add impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -num_critical_paths 3
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C}
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO256C
-set_option -package T100C
-set_option -speed_grade -3
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 70
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./RAM2GS_LCMXO256C_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\run_options.txt
+#--  Written on Sat Aug 19 20:53:10 2023
+
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v"
+
+
+#implementation: "impl1"
+impl -add impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO256C}
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO256C
+set_option -package T100C
+set_option -speed_grade -3
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 70
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./RAM2GS_LCMXO256C_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO256C/impl1/scratchproject.prs b/CPLD/LCMXO256C/impl1/scratchproject.prs
index cf77e03..2c0b97c 100644
--- a/CPLD/LCMXO256C/impl1/scratchproject.prs
+++ b/CPLD/LCMXO256C/impl1/scratchproject.prs
@@ -1,80 +1,80 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\scratchproject.prs
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-
-
-#implementation: "impl1"
-impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -num_critical_paths 3
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/}
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C}
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO256C
-set_option -package T100C
-set_option -speed_grade -3
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 70
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\scratchproject.prs
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v"
+
+
+#implementation: "impl1"
+impl -add Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/}
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO256C}
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO256C
+set_option -package T100C
+set_option -speed_grade -3
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 70
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO256C/impl1/stdout.log b/CPLD/LCMXO256C/impl1/stdout.log
index 17df285..e09c5a2 100644
--- a/CPLD/LCMXO256C/impl1/stdout.log
+++ b/CPLD/LCMXO256C/impl1/stdout.log
@@ -1,89 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 04:50:30 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 04:50:31 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 04:50:31 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 04:50:31 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
-
-compiler completed
-# Wed Aug 16 04:50:32 2023
-
-Return Code: 0
-Run Time:00h:00m:01s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 04:50:32 2023
-
-multi_srs_gen completed
-# Wed Aug 16 04:50:33 2023
-
-Return Code: 0
-Run Time:00h:00m:01s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
-Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 04:50:33 2023
-
-premap completed with warnings
-# Wed Aug 16 04:50:34 2023
-
-Return Code: 1
-Run Time:00h:00m:01s
-Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 04:50:34 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 04:50:34 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
-
-fpga_mapper completed with warnings
-# Wed Aug 16 04:50:38 2023
-
-Return Code: 1
-Run Time:00h:00m:04s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
-Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO256C_impl1_synplify.tcl"
-exit status=0
-exit status=0
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 20:53:10 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 20:53:10 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 20:53:10 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 20:53:10 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
+
+compiler completed
+# Sat Aug 19 20:53:12 2023
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 20:53:12 2023
+
+multi_srs_gen completed
+# Sat Aug 19 20:53:12 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 20:53:12 2023
+
+premap completed with warnings
+# Sat Aug 19 20:53:14 2023
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 20:53:14 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 20:53:14 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 20:53:17 2023
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "RAM2GS_LCMXO256C_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO256C/impl1/stdout.log.bak.2 b/CPLD/LCMXO256C/impl1/stdout.log.bak.2
index 7129265..71a1535 100644
--- a/CPLD/LCMXO256C/impl1/stdout.log.bak.2
+++ b/CPLD/LCMXO256C/impl1/stdout.log.bak.2
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 03:31:19 2023
+Date:        Wed Aug 16 04:22:23 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
@@ -28,26 +28,26 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 03:31:19 2023
+# Wed Aug 16 04:22:23 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 03:31:19 2023
+# Wed Aug 16 04:22:23 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 03:31:19 2023
+# Wed Aug 16 04:22:23 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 
 compiler completed
-# Wed Aug 16 03:31:21 2023
+# Wed Aug 16 04:22:25 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 03:31:21 2023
+# Wed Aug 16 04:22:25 2023
 
 multi_srs_gen completed
-# Wed Aug 16 03:31:22 2023
+# Wed Aug 16 04:22:26 2023
 
 Return Code: 0
 Run Time:00h:00m:01s
@@ -56,28 +56,28 @@ Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 03:31:22 2023
+# Wed Aug 16 04:22:26 2023
 
 premap completed with warnings
-# Wed Aug 16 03:31:24 2023
+# Wed Aug 16 04:22:27 2023
 
 Return Code: 1
-Run Time:00h:00m:02s
+Run Time:00h:00m:01s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 03:31:24 2023
+# Wed Aug 16 04:22:27 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 03:31:24 2023
+# Wed Aug 16 04:22:27 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 03:31:29 2023
+# Wed Aug 16 04:22:31 2023
 
 Return Code: 1
-Run Time:00h:00m:05s
+Run Time:00h:00m:04s
 Complete: Map on proj_1|impl1
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
diff --git a/CPLD/LCMXO256C/impl1/stdout.log.bak.3 b/CPLD/LCMXO256C/impl1/stdout.log.bak.3
index b943250..7129265 100644
--- a/CPLD/LCMXO256C/impl1/stdout.log.bak.3
+++ b/CPLD/LCMXO256C/impl1/stdout.log.bak.3
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:29:31 2023
+Date:        Wed Aug 16 03:31:19 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
@@ -28,56 +28,56 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:29:32 2023
+# Wed Aug 16 03:31:19 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:29:32 2023
+# Wed Aug 16 03:31:19 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:29:32 2023
+# Wed Aug 16 03:31:19 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:29:34 2023
+# Wed Aug 16 03:31:21 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:29:34 2023
+# Wed Aug 16 03:31:21 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:29:34 2023
+# Wed Aug 16 03:31:22 2023
 
 Return Code: 0
-Run Time:00h:00m:00s
+Run Time:00h:00m:01s
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:29:34 2023
+# Wed Aug 16 03:31:22 2023
 
 premap completed with warnings
-# Wed Aug 16 02:29:36 2023
+# Wed Aug 16 03:31:24 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:29:36 2023
+# Wed Aug 16 03:31:24 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:29:36 2023
+# Wed Aug 16 03:31:24 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:29:39 2023
+# Wed Aug 16 03:31:29 2023
 
 Return Code: 1
-Run Time:00h:00m:03s
+Run Time:00h:00m:05s
 Complete: Map on proj_1|impl1
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
diff --git a/CPLD/LCMXO256C/impl1/stdout.log.bak.4 b/CPLD/LCMXO256C/impl1/stdout.log.bak.4
index a269fa7..b943250 100644
--- a/CPLD/LCMXO256C/impl1/stdout.log.bak.4
+++ b/CPLD/LCMXO256C/impl1/stdout.log.bak.4
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:15:33 2023
+Date:        Wed Aug 16 02:29:31 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
@@ -28,26 +28,26 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:15:33 2023
+# Wed Aug 16 02:29:32 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:15:33 2023
+# Wed Aug 16 02:29:32 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:15:33 2023
+# Wed Aug 16 02:29:32 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:15:35 2023
+# Wed Aug 16 02:29:34 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:15:35 2023
+# Wed Aug 16 02:29:34 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:15:35 2023
+# Wed Aug 16 02:29:34 2023
 
 Return Code: 0
 Run Time:00h:00m:00s
@@ -56,25 +56,25 @@ Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:15:35 2023
+# Wed Aug 16 02:29:34 2023
 
 premap completed with warnings
-# Wed Aug 16 02:15:37 2023
+# Wed Aug 16 02:29:36 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:15:37 2023
+# Wed Aug 16 02:29:36 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:15:37 2023
+# Wed Aug 16 02:29:36 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:15:40 2023
+# Wed Aug 16 02:29:39 2023
 
 Return Code: 1
 Run Time:00h:00m:03s
diff --git a/CPLD/LCMXO256C/impl1/stdout.log.bak.5 b/CPLD/LCMXO256C/impl1/stdout.log.bak.5
index 8e0836e..a269fa7 100644
--- a/CPLD/LCMXO256C/impl1/stdout.log.bak.5
+++ b/CPLD/LCMXO256C/impl1/stdout.log.bak.5
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 22:37:08 2023
+Date:        Wed Aug 16 02:15:33 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO256C_impl1_synplify.tcl
@@ -28,49 +28,56 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 22:37:09 2023
+# Wed Aug 16 02:15:33 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 22:37:09 2023
+# Wed Aug 16 02:15:33 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 22:37:09 2023
+# Wed Aug 16 02:15:33 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 
 compiler completed
-# Tue Aug 15 22:37:09 2023
+# Wed Aug 16 02:15:35 2023
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Wed Aug 16 02:15:35 2023
+
+multi_srs_gen completed
+# Wed Aug 16 02:15:35 2023
 
 Return Code: 0
 Run Time:00h:00m:00s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 22:37:09 2023
-Up-To-Date: multi_srs_gen. No run necessary
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srs
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 22:37:09 2023
+# Wed Aug 16 02:15:35 2023
 
 premap completed with warnings
-# Tue Aug 15 22:37:11 2023
+# Wed Aug 16 02:15:37 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 22:37:11 2023
+# Wed Aug 16 02:15:37 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 22:37:11 2023
+# Wed Aug 16 02:15:37 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm
 
 fpga_mapper completed with warnings
-# Tue Aug 15 22:37:15 2023
+# Wed Aug 16 02:15:40 2023
 
 Return Code: 1
-Run Time:00h:00m:04s
+Run Time:00h:00m:03s
 Complete: Map on proj_1|impl1
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
diff --git a/CPLD/LCMXO256C/impl1/synlog.tcl b/CPLD/LCMXO256C/impl1/synlog.tcl
index eb5e3ae..fcd4be4 100644
--- a/CPLD/LCMXO256C/impl1/synlog.tcl
+++ b/CPLD/LCMXO256C/impl1/synlog.tcl
@@ -1 +1 @@
-run_tcl -fg RAM2GS_LCMXO256C_impl1_synplify.tcl
+run_tcl -fg RAM2GS_LCMXO256C_impl1_synplify.tcl
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_comp.rt.csv.rptmap b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_comp.rt.csv.rptmap
index a497c74..ebb0fe1 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_comp.rt.csv.rptmap
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_comp.rt.csv.rptmap
@@ -1 +1 @@
-./synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv,RAM2GS_LCMXO256C_impl1_comp.rt.csv,Module Runtime Summary
+./synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv,RAM2GS_LCMXO256C_impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr
index d5d24e2..0c84f40 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr
@@ -1,108 +1,106 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.db b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.db
index 2f1d32b6ad7e8fe4f289308801b4b2dcaa28c8ec..27bf74809b7c42e24e4b13f07911c5fc0981a067 100644
GIT binary patch
delta 50
zcmZp0XmHrTCcrY4fq&{|L4kb!i48JhnT%}W>B*u@&hEx$CQ6Z3F+r&X`Nfl0%Lg-g
GNdN#~Lk-pd

delta 68
zcmZp0XmHrTCcx6bz~8W0P@s%oyN;1vypcayl*!rM*vv%9#VW=>FV&?evn(~nB|o_|
XH#M)MIL1A*#G^E6@@n~DCe;c6kNp(D

diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.rptmap b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.rptmap
index cab4f09..db931a9 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.rptmap
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_compiler.srr.rptmap
@@ -1 +1 @@
-./synlog/RAM2GS_LCMXO256C_impl1_compiler.srr,RAM2GS_LCMXO256C_impl1_compiler.srr,Compile Log
+./synlog/RAM2GS_LCMXO256C_impl1_compiler.srr,RAM2GS_LCMXO256C_impl1_compiler.srr,Compile Log
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr
index 60b0c2c..b58ee69 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr
@@ -1,659 +1,659 @@
-# Wed Aug 16 04:50:35 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:01s		    -2.99ns		 127 /        92
-   9		0h:00m:01s		    -3.09ns		 127 /        92
-  10		0h:00m:01s		    -3.19ns		 127 /        92
-  11		0h:00m:01s		    -3.19ns		 127 /        92
-  12		0h:00m:01s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
+# Sat Aug 19 20:53:14 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:53:17 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo256c-3
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:53:17 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr.db b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.srr.db
index d26dbc4bb6130d57fed6015dc52c8c6668a55ab7..8ad77861ccf6cd3194c6d86a69c8646c2dc2e8c3 100644
GIT binary patch
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diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.szr b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_fpga_mapper.szr
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diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr
index b265010..aefeeca 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr
@@ -1,28 +1,28 @@
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:32 2023
-
-###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:12 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr
index f7d810f..26b36d2 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr
@@ -1,162 +1,162 @@
-# Wed Aug 16 04:50:33 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
-
-###########################################################]
+# Sat Aug 19 20:53:12 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:53:14 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr.db b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.srr.db
index 1bcdffcdbf439a8163ea78017c16d6a6b850185a..cd147c0ed7e1c01c497cd58d7e7350ef1b430d1a 100644
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diff --git a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.xck b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.xck
index 465056f..44fa3d9 100644
--- a/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.xck
+++ b/CPLD/LCMXO256C/impl1/synlog/RAM2GS_LCMXO256C_impl1_premap.xck
@@ -1,4 +1,4 @@
-ckid0_0:@|S:RCLK@|E:nRWE@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
-ckid0_1:@|S:PHI2@|E:RA11@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
-ckid0_2:@|S:nCCAS@|E:WRD[7:0]@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2
-ckid0_3:@|S:nCRAS@|E:RowA[9:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
+ckid0_0:@|S:RCLK@|E:nRWE@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
+ckid0_1:@|S:PHI2@|E:RA11@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
+ckid0_2:@|S:nCCAS@|E:WRD[7:0]@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2
+ckid0_3:@|S:nCRAS@|E:RowA[9:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
diff --git a/CPLD/LCMXO256C/impl1/synlog/incr_compile.rpt.rptmap b/CPLD/LCMXO256C/impl1/synlog/incr_compile.rpt.rptmap
index dbb7528..37531b6 100644
--- a/CPLD/LCMXO256C/impl1/synlog/incr_compile.rpt.rptmap
+++ b/CPLD/LCMXO256C/impl1/synlog/incr_compile.rpt.rptmap
@@ -1 +1 @@
-./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
+./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
diff --git a/CPLD/LCMXO256C/impl1/synlog/layer0.tlg.rptmap b/CPLD/LCMXO256C/impl1/synlog/layer0.tlg.rptmap
index 3910cac..2caf2f3 100644
--- a/CPLD/LCMXO256C/impl1/synlog/layer0.tlg.rptmap
+++ b/CPLD/LCMXO256C/impl1/synlog/layer0.tlg.rptmap
@@ -1 +1 @@
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_compiler_notes.txt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_compiler_notes.txt
index 434a18f..a9d0906 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_compiler_notes.txt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_compiler_notes.txt
@@ -1,5 +1,5 @@
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-@N|Running in 64-bit mode
-
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N|Running in 64-bit mode
+
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_notes.txt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_notes.txt
index 242ec38..6365806 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_notes.txt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_notes.txt
@@ -1,20 +1,20 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_resourceusage.rpt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_resourceusage.rpt
index 35a7999..8aa2c2e 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_resourceusage.rpt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_resourceusage.rpt
@@ -1,24 +1,24 @@
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
+Resource Usage Report
+Part: lcmxo256c-3
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_warnings.txt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_warnings.txt
index b7e853c..a0096d4 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_warnings.txt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_fpga_mapper_warnings.txt
@@ -1,6 +1,6 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_combined_clk.rpt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_combined_clk.rpt
index 7fbc557..88df5e3 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_combined_clk.rpt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_combined_clk.rpt
@@ -1,24 +1,24 @@
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_notes.txt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_notes.txt
index f26ba50..e5e690c 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_notes.txt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_notes.txt
@@ -1,27 +1,27 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_warnings.txt b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_warnings.txt
index 81e8ed8..860c24f 100644
--- a/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_warnings.txt
+++ b/CPLD/LCMXO256C/impl1/synlog/report/RAM2GS_LCMXO256C_impl1_premap_warnings.txt
@@ -1 +1 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
diff --git a/CPLD/LCMXO256C/impl1/synlog/report/metrics.db b/CPLD/LCMXO256C/impl1/synlog/report/metrics.db
index 2836e4c046ed0d53eb5bc7b9c14058eba6d1a291..4d364db33859c6eb05e1f4566f0150b596d99c16 100644
GIT binary patch
delta 471
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    -
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:31 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-Linked File:  layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-Linked File:  RAM2GS_LCMXO256C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:31 2023
-
-###########################################################]
-
-
    
-
    -
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:32 2023
-
-###########################################################]
-
-
    
-
    -
-# Wed Aug 16 04:50:33 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  RAM2GS_LCMXO256C_impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS  
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:34 2023
-
-###########################################################]
-
-
    
-
    -
-# Wed Aug 16 04:50:35 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N:FX271 : ram2gs-spi.v(105) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N:FX271 : ram2gs-spi.v(105) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:01s		    -2.99ns		 127 /        92
-   9		0h:00m:01s		    -3.09ns		 127 /        92
-  10		0h:00m:01s		    -3.19ns		 127 /        92
-  11		0h:00m:01s		    -3.19ns		 127 /        92
-  12		0h:00m:01s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:38 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo256c-3
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-
    
+
    +
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 20:53:10 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+Linked File:  layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+Linked File:  RAM2GS_LCMXO256C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:11 2023
+
+###########################################################]
+
+
    
+
    +
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:53:12 2023
+
+###########################################################]
+
+
    
+
    +
+Premap Report
+
+
+
    
+
    +
+# Sat Aug 19 20:53:12 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+Linked File:  RAM2GS_LCMXO256C_impl1_scck.rpt
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
+@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
+@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS  
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+ClockId_0_0       RCLK                port                   48         nRWE           
+ClockId_0_1       PHI2                port                   19         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:53:14 2023
+
+###########################################################]
+
+
    
+
    +
+Map & Optimize Report
+
+
+
    
+
    +
+# Sat Aug 19 20:53:14 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N:FX271 : ram2gs-spi.v(105) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N:FX271 : ram2gs-spi.v(105) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:53:17 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo256c-3
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:53:17 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO256C/impl1/syntmp/RAM2GS_LCMXO256C_impl1_toc.htm b/CPLD/LCMXO256C/impl1/syntmp/RAM2GS_LCMXO256C_impl1_toc.htm
index e8dadfb..7437861 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/RAM2GS_LCMXO256C_impl1_toc.htm
+++ b/CPLD/LCMXO256C/impl1/syntmp/RAM2GS_LCMXO256C_impl1_toc.htm
@@ -1,58 +1,58 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
  
\ No newline at end of file
diff --git a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_compiler.log b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_compiler.log
index 70ffc45..02179b4 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_compiler.log
+++ b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_compiler.log
@@ -1,10 +1,10 @@
-C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO256C -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
-rc:0 success:1 runtime:1
-file:..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs|io:o|time:1692175831|size:10550|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr|io:o|time:1692175831|size:4581|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\..\RAM2GS-SPI.v|io:i|time:1692174460|size:11765|exec:0|csum:DDFDD384E6E6239925365D2C41FC9773
-file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
+C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs  -top  RAM2GS  -hdllog  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I Y:\Repos\RAM2GS\CPLD\LCMXO256C  -I Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO256C -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
+rc:0 success:1 runtime:2
+file:..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs|io:o|time:1692492791|size:10493|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO256C_impl1_compiler.srr|io:o|time:1692492791|size:4494|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\..\RAM2GS-SPI.v|io:i|time:1692234355|size:14885|exec:0|csum:22AA32E3708F79533C7AD37D1C9B8166
+file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
diff --git a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_fpga_mapper.log b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_fpga_mapper.log
index 4997ccb..a0c79e8 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_fpga_mapper.log
+++ b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1   -part LCMXO256C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\report\RAM2GS_LCMXO256C_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\syntmp\RAM2GS_LCMXO256C_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO256C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO256C_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO256C_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO256C_impl1.plg -osyn ..\RAM2GS_LCMXO256C_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
-rc:1 success:1 runtime:4
-file:..\RAM2GS_LCMXO256C_impl1.edi|io:o|time:1692175837|size:125385|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:i|time:1692175834|size:15189|exec:0|csum:7FED0757093D1004AA4D110C5A40C760
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO256C_impl1.plg|io:o|time:1692175838|size:854|exec:0|csum:
-file:..\RAM2GS_LCMXO256C_impl1.srm|io:o|time:1692175837|size:29138|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr|io:o|time:1692175838|size:35917|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1   -part LCMXO256C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\report\RAM2GS_LCMXO256C_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi   -freq 70.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\syntmp\RAM2GS_LCMXO256C_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.srm  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO256C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO256C_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO256C_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO256C_impl1.plg -osyn ..\RAM2GS_LCMXO256C_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
+rc:1 success:1 runtime:3
+file:..\RAM2GS_LCMXO256C_impl1.edi|io:o|time:1692492797|size:125386|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:i|time:1692492793|size:16783|exec:0|csum:62DD21FEC921FA060970A12A8F713254
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:RAM2GS_LCMXO256C_impl1.plg|io:o|time:1692492797|size:854|exec:0|csum:
+file:..\RAM2GS_LCMXO256C_impl1.srm|io:o|time:1692492796|size:29196|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO256C_impl1_fpga_mapper.srr|io:o|time:1692492797|size:35763|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_multi_srs_gen.log b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_multi_srs_gen.log
index 1b897e6..078773e 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_multi_srs_gen.log
+++ b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -1,7 +1,7 @@
-C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr
-rc:0 success:1 runtime:1
-file:..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs|io:i|time:1692175831|size:10550|exec:0|csum:3E9A22EDAAEC35E9596A07EAB1D8F12D
-file:..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs|io:o|time:1692175832|size:10295|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr|io:o|time:1692175832|size:1157|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
+C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs  -log  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr
+rc:0 success:1 runtime:0
+file:..\synwork\RAM2GS_LCMXO256C_impl1_comp.srs|io:i|time:1692492791|size:10493|exec:0|csum:3DEB59A735D21796D5257278F4A13B73
+file:..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs|io:o|time:1692492792|size:10369|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO256C_impl1_multi_srs_gen.srr|io:o|time:1692492792|size:1163|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
diff --git a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_premap.log b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_premap.log
index 4db752c..648bdd2 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/cmdrec_premap.log
+++ b/CPLD/LCMXO256C/impl1/syntmp/cmdrec_premap.log
@@ -1,14 +1,14 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1   -part LCMXO256C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\report\RAM2GS_LCMXO256C_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_cck.rpt   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\syntmp\RAM2GS_LCMXO256C_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO256C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO256C_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO256C_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO256C_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO256C_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO256C_impl1_premap.srr -sn 2021.03 -jobname "premap"
-rc:1 success:1 runtime:1
-file:..\RAM2GS_LCMXO256C_impl1.edi|io:o|time:1692174576|size:125385|exec:0|csum:
-file:..\RAM2GS_LCMXO256C_impl1_cck.rpt|io:o|time:1692175834|size:4751|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs|io:i|time:1692175832|size:10295|exec:0|csum:3B66F8D0469AB260AA4EC9F5FAA00B75
-file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:o|time:1692175834|size:15189|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO256C_impl1.plg|io:o|time:1692175833|size:0|exec:0|csum:
-file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:o|time:1692175834|size:15189|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO256C_impl1_premap.srr|io:o|time:1692175834|size:8417|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1   -part LCMXO256C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\report\RAM2GS_LCMXO256C_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi  -conchk_prepass  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_cck.rpt   -freq 70.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\syntmp\RAM2GS_LCMXO256C_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_prem.srd  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synlog\RAM2GS_LCMXO256C_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO256C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO256C_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO256C_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO256C_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO256C_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO256C_impl1_premap.srr -sn 2021.03 -jobname "premap"
+rc:1 success:1 runtime:2
+file:..\RAM2GS_LCMXO256C_impl1.edi|io:o|time:1692234355|size:122599|exec:0|csum:
+file:..\RAM2GS_LCMXO256C_impl1_cck.rpt|io:o|time:1692492793|size:4637|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\RAM2GS_LCMXO256C_impl1_mult.srs|io:i|time:1692492792|size:10369|exec:0|csum:C61B4444F963CDC69E144A3481F5769D
+file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:o|time:1692492793|size:16783|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:RAM2GS_LCMXO256C_impl1.plg|io:o|time:1692492793|size:0|exec:0|csum:
+file:..\synwork\RAM2GS_LCMXO256C_impl1_prem.srd|io:o|time:1692492793|size:16783|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO256C_impl1_premap.srr|io:o|time:1692492794|size:8364|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO256C/impl1/syntmp/statusReport.html b/CPLD/LCMXO256C/impl1/syntmp/statusReport.html
index 18b9fef..13a320a 100644
--- a/CPLD/LCMXO256C/impl1/syntmp/statusReport.html
+++ b/CPLD/LCMXO256C/impl1/syntmp/statusReport.html
@@ -1,115 +1,115 @@
- 
- 			 			
-			Project Status Summary Page
-			
-			
-			
-
- 			
- 			
-
     
- 
- 
-
- 		  
-		 
-
-
-
- 
- 
-  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO : LCMXO256C 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  0  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
- 				   
-         
- 		
- 			
-			
- 			
- 			
- 			
- 			
- 			
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-         
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-  
- 
- 
-
-
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-
- 
-
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-  
-  
-     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete400-00m:00s-8/16/2023
    4:50:31 AM
     (premap)Complete27100m:01s0m:01s173MB8/16/2023
    4:50:34 AM
     (fpga_mapper)Complete20600m:03s0m:03s185MB8/16/2023
    4:50:38 AM
    Multi-srs GeneratorComplete00m:01s8/16/2023
    4:50:32 AM    		 		
    
- 
     
- 
- 				   
- 
-  
-  
-
-
-
- 
-
-
-
- 
-
- 
-
-    
    Area Summary
     
     
     
    Register bits 92I/O cells 67
    Block RAMs
-(v_ram) 0DSPs
-(dsp_used) 0
    ORCA LUTs
-(total_luts) 119

    
- 
- 				   
- 
-  
- 
-    
- 
- 
- 
- 
- 
- 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz0.6 MHz-3.705
     RCLK62.5 MHz13.3 MHz-2.312
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz0.6 MHz-3.609
    
-
    
- 
- 				   
-  
-
- 
-
-    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
-
     
-
     
+ 
+ 			 			
+			Project Status Summary Page
+			
+			
+			
+
+ 			
+ 			
+
     
+ 
+ 
+
+ 		  
+		 
+
+
+
+ 
+ 
+  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO : LCMXO256C 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  0  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
+ 				   
+         
+ 		
+ 			
+			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
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+ 
+
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+ 
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+  
+     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete400-00m:01s-8/19/2023
    8:53:11 PM
     (premap)Complete27100m:01s0m:01s184MB8/19/2023
    8:53:13 PM
     (fpga_mapper)Complete20600m:03s0m:03s196MB8/19/2023
    8:53:17 PM
    Multi-srs GeneratorComplete8/19/2023
    8:53:12 PM    		 		
    
+ 
     
+ 
+ 				   
+ 
+  
+  
+
+
+
+ 
+
+
+
+ 
+
+ 
+
+    
    Area Summary
     
     
     
    Register bits 92I/O cells 67
    Block RAMs
+(v_ram) 0DSPs
+(dsp_used) 0
    ORCA LUTs
+(total_luts) 119

    
+ 
+ 				   
+ 
+  
+ 
+    
+ 
+ 
+ 
+ 
+ 
+ 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz0.6 MHz-3.705
     RCLK62.5 MHz13.3 MHz-2.312
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz0.6 MHz-3.609
    
+
    
+ 
+ 				   
+  
+
+ 
+
+    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
+
     
+
     
  
\ No newline at end of file
diff --git a/CPLD/LCMXO256C/impl1/synwork/.cckTransfer b/CPLD/LCMXO256C/impl1/synwork/.cckTransfer
index f6339db7f319334e1dfc805b12bf0b0044a89d5e..bb39f4206380c69e0058986c2a1dc08efb1ac8d5 100644
GIT binary patch
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diff --git a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.fdep b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.fdep
index 6d772b2..643c06e 100644
--- a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.fdep
+++ b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.fdep
@@ -1,16 +1,16 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\synwork\\RAM2GS_LCMXO256C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692174460
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work RAM2GS 0
+#OPTIONS:"|-layerid|0|-orig_srs|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\synwork\\RAM2GS_LCMXO256C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692234355
+0			"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work RAM2GS 0
diff --git a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv
index 915b7cd..0b328e3 100644
--- a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv
+++ b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_comp.rt.csv
@@ -1 +1 @@
-Library, Design Unit, compile Time, Peak Mem Usage
+Library, Design Unit, compile Time, Peak Mem Usage
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diff --git a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_m_srm/1.srm b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_m_srm/1.srm
index 86bdc3dd626b4aa53171b9fb9487a9393585b625..d089a50f0bdc78ca7ff891074bf939fa17384319 100644
GIT binary patch
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diff --git a/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_m_srm/fileinfo.srm b/CPLD/LCMXO256C/impl1/synwork/RAM2GS_LCMXO256C_impl1_m_srm/fileinfo.srm
index adf68aabb3bc69f378c5744876d9590550701e2b..44488e09d7bcb1376e45cb6675f4bf52dcfb5e9d 100644
GIT binary patch
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diff --git a/CPLD/LCMXO256C/impl1/synwork/_mh_info b/CPLD/LCMXO256C/impl1/synwork/_mh_info
index 37bc105..4e98067 100644
--- a/CPLD/LCMXO256C/impl1/synwork/_mh_info
+++ b/CPLD/LCMXO256C/impl1/synwork/_mh_info
@@ -1 +1 @@
-|1|
+|1|
diff --git a/CPLD/LCMXO256C/impl1/synwork/incr_compile.rpt b/CPLD/LCMXO256C/impl1/synwork/incr_compile.rpt
index d534d8a..065043f 100644
--- a/CPLD/LCMXO256C/impl1/synwork/incr_compile.rpt
+++ b/CPLD/LCMXO256C/impl1/synwork/incr_compile.rpt
@@ -1,38 +1,40 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL compiler and linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-Modified Files: 0
-FID:  path (prevtimestamp, timestamp)
-
-*******************************************************************
-Modules that may have changed as a result of file changes: 0
-MID:  lib.cell.view
-
-*******************************************************************
-Unmodified files: 7
-FID:  path (timestamp)
-0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v (2021-08-10 09:11:08)
-1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
-2        C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v (2021-08-10 09:07:02)
-3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
-4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
-5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
-6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v (2023-08-16 04:27:40)
-
-*******************************************************************
-Unchanged modules: 1
-MID:  lib.cell.view
-0        work.RAM2GS.verilog
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL compiler and linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+Modified Files: 2
+FID:  path (prevtimestamp, timestamp)
+6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v (2023-08-16 04:27:40, N/A)
+7        Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v (N/A, 2023-08-16 21:05:55)
+
+*******************************************************************
+Modules that may have changed as a result of file changes: 1
+MID:  lib.cell.view
+0        work.RAM2GS.verilog may have changed because the following files changed:
+                        Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v (N/A, 2023-08-16 21:05:55) <-- (module definition)
+
+*******************************************************************
+Unmodified files: 6
+FID:  path (timestamp)
+0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v (2021-08-10 09:11:08)
+1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
+2        C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v (2021-08-10 09:07:02)
+3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
+4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
+5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
+
+*******************************************************************
+Unchanged modules: 0
+MID:  lib.cell.view
diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.fdep b/CPLD/LCMXO256C/impl1/synwork/layer0.fdep
index a4fa5c8..719630b 100644
--- a/CPLD/LCMXO256C/impl1/synwork/layer0.fdep
+++ b/CPLD/LCMXO256C/impl1/synwork/layer0.fdep
@@ -1,18 +1,18 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\synwork\\RAM2GS_LCMXO256C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692174460
-#numinternalfiles:6
-#defaultlanguage:verilog
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work RAM2GS 0
+#OPTIONS:"|-layerid|0|-orig_srs|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\synwork\\RAM2GS_LCMXO256C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO256C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692234355
+#numinternalfiles:6
+#defaultlanguage:verilog
+0			"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work RAM2GS 0
diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.fdepxmr b/CPLD/LCMXO256C/impl1/synwork/layer0.fdepxmr
index 37d628b..8bc2ba2 100644
--- a/CPLD/LCMXO256C/impl1/synwork/layer0.fdepxmr
+++ b/CPLD/LCMXO256C/impl1/synwork/layer0.fdepxmr
@@ -1 +1 @@
-#XMR Information
+#XMR Information
diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.rt.csv b/CPLD/LCMXO256C/impl1/synwork/layer0.rt.csv
index 915b7cd..0b328e3 100644
--- a/CPLD/LCMXO256C/impl1/synwork/layer0.rt.csv
+++ b/CPLD/LCMXO256C/impl1/synwork/layer0.rt.csv
@@ -1 +1 @@
-Library, Design Unit, compile Time, Peak Mem Usage
+Library, Design Unit, compile Time, Peak Mem Usage
diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.srs b/CPLD/LCMXO256C/impl1/synwork/layer0.srs
index 39a308da09be91ba4d3fe1cb054d7db5fac6ab5b..a63d4c8a1d874247c6a7636f7d1c51f5a94185d7 100644
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diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.tlg b/CPLD/LCMXO256C/impl1/synwork/layer0.tlg
index b28b287..d202e02 100644
--- a/CPLD/LCMXO256C/impl1/synwork/layer0.tlg
+++ b/CPLD/LCMXO256C/impl1/synwork/layer0.tlg
@@ -1,11 +1,11 @@
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
-
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\layer0.rt.csv
+
diff --git a/CPLD/LCMXO256C/impl1/synwork/layer0.tlg.db b/CPLD/LCMXO256C/impl1/synwork/layer0.tlg.db
index 2f1d32b6ad7e8fe4f289308801b4b2dcaa28c8ec..27bf74809b7c42e24e4b13f07911c5fc0981a067 100644
GIT binary patch
delta 50
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GNdN#~Lk-pd

delta 68
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XH#M)MIL1A*#G^E6@@n~DCe;c6kNp(D

diff --git a/CPLD/LCMXO256C/impl1/synwork/modulechange.db b/CPLD/LCMXO256C/impl1/synwork/modulechange.db
index 5a77fcbf6de329bdefcd04ef9f6a523892f3f44c..f2bbc8535764cb61f65b5768ecb4a1cfdc0aaa72 100644
GIT binary patch
delta 199
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delta 157
zcmZoTz}Rqrae}m<90LOb8xX@l_(UCJaXAJ(k%zoMAy(e=4E&S$R`P}Np66HHtSAu4
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BC6NFC

diff --git a/CPLD/LCMXO256C/impl1/version.log b/CPLD/LCMXO256C/impl1/version.log
index 9d5f37d..a8d67f6 100644
--- a/CPLD/LCMXO256C/impl1/version.log
+++ b/CPLD/LCMXO256C/impl1/version.log
@@ -1,2 +1,2 @@
-R-2021.03L-SP1
-Synplify Pro (R)
+R-2021.03L-SP1
+Synplify Pro (R)
diff --git a/CPLD/LCMXO640C/.run_manager.ini b/CPLD/LCMXO640C/.run_manager.ini
index 8c0aa7b..b5da7d8 100644
--- a/CPLD/LCMXO640C/.run_manager.ini
+++ b/CPLD/LCMXO640C/.run_manager.ini
@@ -1,9 +1,9 @@
-[Runmanager]
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-
-[impl1%3CStrategy1%3E]
-isChecked=false
-isHidden=false
-isExpanded=false
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
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+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
index a7bbcc2..541b3a9 100644
--- a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
@@ -9,7 +9,7 @@
         
             
         
-        
+        
             
         
         
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
index eea92d0..63d5597 100644
--- a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
@@ -15,6 +15,41 @@ prj_run Export -impl impl1
 
 
 
+pn230819063021
+#Start recording tcl command: 8/19/2023 06:30:19
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+#Stop recording: 8/19/2023 06:30:21
+
+
+
+pn230819063032
+#Start recording tcl command: 8/19/2023 06:30:26
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+#Stop recording: 8/19/2023 06:30:32
+
+
+
+pn230819215438
+#Start recording tcl command: 8/19/2023 20:57:00
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_project close
+#Stop recording: 8/19/2023 21:54:38
+
+
+
+pn230820055538
+#Start recording tcl command: 8/20/2023 05:55:34
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_project close
+#Stop recording: 8/20/2023 05:55:38
+
+
+
 
    
 
    
 
    
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063021.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063021.tcr
new file mode 100644
index 0000000..3ec4819
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063021.tcr
@@ -0,0 +1,4 @@
+#Start recording tcl command: 8/19/2023 06:30:19
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+#Stop recording: 8/19/2023 06:30:21
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063032.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063032.tcr
new file mode 100644
index 0000000..fee2179
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819063032.tcr
@@ -0,0 +1,4 @@
+#Start recording tcl command: 8/19/2023 06:30:26
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+#Stop recording: 8/19/2023 06:30:32
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819215438.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819215438.tcr
new file mode 100644
index 0000000..a127ddc
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230819215438.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/19/2023 20:57:00
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_project close
+#Stop recording: 8/19/2023 21:54:38
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055538.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055538.tcr
new file mode 100644
index 0000000..f27c288
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055538.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 8/20/2023 05:55:34
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_project close
+#Stop recording: 8/20/2023 05:55:38
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055558.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055558.tcr
new file mode 100644
index 0000000..9a32664
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230820055558.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/20/2023 05:55:51
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1 -task IBIS
+prj_project close
+#Stop recording: 8/20/2023 05:55:58
diff --git a/CPLD/LCMXO640C/impl1/.build_status b/CPLD/LCMXO640C/impl1/.build_status
index f001400..4e6a6a8 100644
--- a/CPLD/LCMXO640C/impl1/.build_status
+++ b/CPLD/LCMXO640C/impl1/.build_status
@@ -2,35 +2,35 @@
 
     
         
-            
-            
-            
-            
+            
+            
+            
+            
         
-        
-            
-            
-            
-            
-            
+        
+            
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
+        
+            
         
         
-            
+            
             
             
             
             
         
-        
-            
+        
+            
         
         
         
@@ -49,23 +49,23 @@
         
         
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
     
 
diff --git a/CPLD/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs b/CPLD/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs
index c45e35b..bffc7d3 100644
--- a/CPLD/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs
+++ b/CPLD/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs
@@ -1,3373 +1,3373 @@
-|************************************************************************
-| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
-| Generate date: Wed Aug 16 04:50:53 2023
-|************************************************************************
-| IBIS File machxo.ibs
-| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
-| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
-| North Carolina State University, ERL, 2006
-|************************************************************************
-[IBIS ver]       3.2
-[File Name]     RAM2GS_LCMXO640C_im~.ibs
-[File Rev]       2.2
-[Date]           Mon Sep 28 10:44:10 EDT 2009
-[Source]         Lattice Semiconductor EE12 Process
-[Notes]          "Preliminary Version"
-                 Lattice Semiconductor has worked hard to ensure the
-                 models below are accurate and complete.  However, the
-                 data below was generated using simulation of the
-                 input/output model files for the silicon.  Therefore,
-                 the data below is for reference and initial design
-                 purposes only.
-|
-                 The data below is correlated to Spice models.  
-                 For questions regarding this data please contact
-                 us at www.latticesemi.com.
-|
-                 Lattice Semiconductor grants permission to use this
-                 data for use in printed circuit design using this
-                 Lattice programmable logic device.  Other use of this
-                 code, including the selling or duplication of any
-                 portion is strictly prohibited.
-|
-|                NAMING CONVENTION
-|
-        The IBIS [Model] header is limited by the specification to a
-        total of characters.  With such a set of characters available
-        for naming models it becomes important to attempt to
-        meaningfully encode the IO standards so they fit within the
-        twenty character limit.  It would seem that twenty characters
-        would provide room enough for describing IO's.  However, the
-        PLD IO structure continues to grow more and more complex.  The
-        complexity is making the twenty characters insuffiently
-        descriptive.  In order to overcome this issue the naming
-        convention described below is implemented to resolve the issue.
-|
-The twenty character space is managed as follows:
-                 bbbvvvsdddprugtcoixx
-|
-                 b = standard
-                 v = voltage (x.xx V)
-                 s = slew code
-                 d = drive (xx.x ma)
-                 p = pullup code
-                 r = series resistance code
-                 u = terminate to vcc code
-                 g = terminate to gnd code
-                 t = terminate to vtt code
-                 c = common mode termination mode
-                 o = diff resistor code
-                 i = diff resistor current code
-                 x = reserved
-|
-|
-                 standard
-|
-                 LVCMOS                   lvc
-                 lvcmosd                  lvd
-                 LVDSE                    lve
-                 LVTTL                    lvt
-                 lvttld                   ltd
-                 PCI                      pci
-                 pcix                     pcx
-                 AGP1x                    ag1
-                 agp2x                    ag2
-                 sstl_I                   ss1
-                 sstl_II                  ss2
-                 sstld_I                  s1d
-                 sstld_II                 s2d
-                 CTT                      ctt
-                 hstl_i                   hs1
-                 hstl_ii                  hs2
-                 hstl_iii                 hs3
-                 hstl_iv                  hs4
-                 hstld_i                  h1d
-                 hstld_ii                 h2d
-                 gtl                      gtl
-                 gtlplus                  gtp
-                 lvds                     lvs
-                 blvds                    blv
-                 mlvds                    mlv
-                 lvpecl                   lvp
-                 cml                      cml
-                 hypt                     hyp
-                 rsds                     rsd
-                 vref1                    vr1
-                 vref2                    vr2
-                 ref_res                  rer
-|
-|
-                 slew
-                 na                       a
-                 fast                     f
-                 slow                     s
-|
-                 pullmode
-                 off                      a
-                 pullup                   b
-                 pulldown                 c
-                 bushold                  d
-                 pciclamp                 e
-                 up_pciclamp              f
-                 down_pciclamp            g
-                 keeper_pciclamp          h
-                 schmitt                  i
-                 up_schmitt               j
-                 down_schmitt             k
-                 keeper_schmitt           l
-                 up_pciclamp_schmitt      m
-                 down_pciclamp_schmitt    n
-                 keeper_pciclamp_schmitt  o
-                 pciclamp_schmitt         p
-|
-                 impedence
-                 off                      a
-                 25                       b
-                 33                       c
-                 50                       d
-                 100                      e
-|
-                 termVCC
-                 off                      a
-                 50                       b
-                 100                      c
-                 120                      d
-|
-                 termGND
-                 off                      a
-                 50                       b
-                 100                      c
-                 120                      d
-|
-                 termVTT
-                 off                      a
-                 60                       b
-                 75                       c
-                 120                      d
-                 150                      e
-                 210                      f
-|
-                 VCMT
-                 off                      a
-                 VCMT                     b
-                 VTT                      c
-                 DDR-2                    d
-|
-                 differential resistor
-                 off                      a
-                 120                      b
-                 150                      c
-                 220                      d
-                 420                      e
-|
-                 differential current
-                 NA                       a
-                 2                        b
-                 3.5                      c
-                 4                        d
-                 6                        e
-|
-                 Reserved                 IO type
-                 in                       input only
-                 ou                       output
-                 io                       I/O
-                 od                       Open drain
-                 on                       Inverting differential I/O
-                                          (signal name only)
-                 op                       Non-Inverting differential I/O
-                                          (signal name only)
-|
-   All the IO models are generated with pull mode set to UP.
-|
-                 Lattice Semiconductor Corporation
-                 5555 NE Moore Court
-                 Hillsboro, OR 97214
-                 U.S.A
-|
-                 TEL: 1-800-Lattice (USA and Canada)
-                      408-826-6000 (other locations)
-|
-                 web: http://www.latticesemi.com/
-                 email: techsupport@latticesemi.com
-|
-|
-|
-[Disclaimer]     This IBIS source code is intended as a design reference
-   which illustrates how the Lattice Semiconductor device operates.
-   It is the user's responsibility to verify their design for
-   consistency and functionality through the use of formal
-   verification methods.  Lattice Semiconductor provides no warranty
-   regarding the use or functionality of this data.
-|
-[Copyright]      Copyright 2009 by Lattice Semiconductor Corporation
-|
-|  
-|************************************************************************
-|                       Component XO
-|************************************************************************
-|  
-[Component]     MXO256_MXO640_MXO1K_MXO2K
-[Manufacturer]    Lattice Semiconductor Corp.
-[Package]
-|TQFP100
-| variable            typ              min              max
-R_pkg                 70.5m            54.0m            87.0m
-L_pkg                 4.57nH           4.27nH           4.87nH
-C_pkg                 .52pF            .47pF            .57pF
-|
-[Pin] signal_name           model_name           R_pin     L_pin     C_pin
-32            CROW[0]              lvc330fxxxaaaaaaaain
-34            CROW[1]              lvc330fxxxaaaaaaaain
-21            Din[0]               lvc330fxxxaaaaaaaain
-15            Din[1]               lvc330fxxxaaaaaaaain
-14            Din[2]               lvc330fxxxaaaaaaaain
-16            Din[3]               lvc330fxxxaaaaaaaain
-18            Din[4]               lvc330fxxxaaaaaaaain
-17            Din[5]               lvc330fxxxaaaaaaaain
-20            Din[6]               lvc330fxxxaaaaaaaain
-19            Din[7]               lvc330fxxxaaaaaaaain
-1             Dout[0]              lvc330f040aaaaaaaaio
-7             Dout[1]              lvc330f040aaaaaaaaio
-8             Dout[2]              lvc330f040aaaaaaaaio
-6             Dout[3]              lvc330f040aaaaaaaaio
-4             Dout[4]              lvc330f040aaaaaaaaio
-5             Dout[5]              lvc330f040aaaaaaaaio
-2             Dout[6]              lvc330f040aaaaaaaaio
-3             Dout[7]              lvc330f040aaaaaaaaio
-57            LED                  lvc330s140aaaaaaaaio
-23            MAin[0]              lvc330fxxxaaaaaaaain
-38            MAin[1]              lvc330fxxxaaaaaaaain
-37            MAin[2]              lvc330fxxxaaaaaaaain
-47            MAin[3]              lvc330fxxxaaaaaaaain
-46            MAin[4]              lvc330fxxxaaaaaaaain
-45            MAin[5]              lvc330fxxxaaaaaaaain
-49            MAin[6]              lvc330fxxxaaaaaaaain
-44            MAin[7]              lvc330fxxxaaaaaaaain
-50            MAin[8]              lvc330fxxxaaaaaaaain
-51            MAin[9]              lvc330fxxxaaaaaaaain
-39            PHI2                 lvc330fxxxcaaaaaaain
-98            RA[0]                lvc330s040aaaaaaaaio
-87            RA[10]               lvc330s040aaaaaaaaio
-79            RA[11]               lvc330s040aaaaaaaaio
-89            RA[1]                lvc330s040aaaaaaaaio
-94            RA[2]                lvc330s040aaaaaaaaio
-97            RA[3]                lvc330s040aaaaaaaaio
-99            RA[4]                lvc330s040aaaaaaaaio
-95            RA[5]                lvc330s040aaaaaaaaio
-91            RA[6]                lvc330s040aaaaaaaaio
-100           RA[7]                lvc330s040aaaaaaaaio
-96            RA[8]                lvc330s040aaaaaaaaio
-85            RA[9]                lvc330s040aaaaaaaaio
-63            RBA[0]               lvc330s040aaaaaaaaio
-83            RBA[1]               lvc330s040aaaaaaaaio
-82            RCKE                 lvc330s040aaaaaaaaio
-86            RCLK                 lvc330fxxxaaaaaaaain
-76            RDQMH                lvc330s040aaaaaaaaio
-61            RDQML                lvc330s040aaaaaaaaio
-64            RD[0]                lvc330s040aaaaaaaaio
-65            RD[1]                lvc330s040aaaaaaaaio
-66            RD[2]                lvc330s040aaaaaaaaio
-67            RD[3]                lvc330s040aaaaaaaaio
-68            RD[4]                lvc330s040aaaaaaaaio
-69            RD[5]                lvc330s040aaaaaaaaio
-70            RD[6]                lvc330s040aaaaaaaaio
-71            RD[7]                lvc330s040aaaaaaaaio
-58            UFMCLK               lvc330s040aaaaaaaaio
-56            UFMSDI               lvc330s040aaaaaaaaio
-55            UFMSDO               lvc330fxxxaaaaaaaain
-27            nCCAS                lvc330fxxxbaaaaaaain
-43            nCRAS                lvc330fxxxbaaaaaaain
-22            nFWE                 lvc330fxxxaaaaaaaain
-78            nRCAS                lvc330s040aaaaaaaaio
-77            nRCS                 lvc330s040aaaaaaaaio
-73            nRRAS                lvc330s040aaaaaaaaio
-72            nRWE                 lvc330s040aaaaaaaaio
-53            nUFMCS               lvc330s040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330f040aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
-  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
-  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
-  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
-  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
-  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
-  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
-  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
-  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
-  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
-  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
-  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
-  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
-  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
-  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
-  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
-  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
-  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
-  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
-  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
-  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
-  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
-  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
-  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
-  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
-  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
-  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
-  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
-  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
-  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
-  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
-  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
-  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
-  0.00    9.270000nA        8.640000nA           10.950000nA
-  0.10    2.215985mA        1.960397mA           2.507890mA
-  0.20    4.086375mA        3.683686mA           4.498680mA
-  0.30    5.594166mA        5.150675mA           5.952471mA
-  0.40    6.738256mA        6.352364mA           6.929962mA
-  0.50    7.557146mA        7.289853mA           7.572152mA
-  0.60    8.124436mA        7.983242mA           8.013343mA
-  0.70    8.511126mA        8.476831mA           8.337834mA
-  0.80    8.778316mA        8.826620mA           8.591424mA
-  0.90    8.972606mA        9.080609mA           8.798515mA
-  1.00    9.121395mA        9.272098mA           8.969206mA
-  1.10    9.240584mA        9.422087mA           9.101296mA
-  1.20    9.339574mA        9.543476mA           9.202186mA
-  1.30    9.424063mA        9.644765mA           9.285275mA
-  1.40    9.498053mA        9.731354mA           9.357665mA
-  1.50    9.564242mA        9.806743mA           9.423455mA
-  1.60    9.625232mA        9.873832mA           9.485944mA
-  1.70    9.684621mA        9.934821mA           9.548134mA
-  1.80    9.747011mA        9.992810mA           9.610224mA
-  1.90    9.814800mA        10.052999mA          9.670813mA
-  2.00    9.885689mA        10.122988mA          9.728603mA
-  2.10    9.955379mA        10.203977mA          9.783293mA
-  2.20    10.021968mA       10.292966mA          9.835282mA
-  2.30    10.083958mA       10.380954mA          9.884972mA
-  2.40    10.141947mA       10.464943mA          9.932861mA
-  2.50    10.196936mA       10.542932mA          9.979551mA
-  2.60    10.249926mA       10.614921mA          10.025941mA
-  2.70    10.300915mA       10.681910mA          10.071930mA
-  2.80    10.350904mA       10.744899mA          10.118920mA
-  2.90    10.400894mA       10.805888mA          10.167909mA
-  3.00    10.451883mA       10.863877mA          10.218899mA
-  3.10    10.504872mA       10.921864mA          10.273889mA
-  3.20    10.559862mA       10.978747mA          10.332878mA
-  3.30    10.618848mA       11.037379mA          10.397868mA
-  3.40    10.682725mA       11.085335mA          10.469857mA
-  3.50    10.751986mA       11.124616mA          10.550843mA
-  3.60    10.804292mA       11.163898mA          10.640599mA
-  3.70    10.840604mA       11.203179mA          10.738212mA
-  3.80    10.876916mA       11.242461mA          10.773505mA
-  3.90    10.913228mA       11.281743mA          10.808797mA
-  4.00    10.949540mA       11.321024mA          10.844090mA
-  4.10    10.985852mA       11.360306mA          10.879382mA
-  4.20    11.022164mA       11.399587mA          10.914675mA
-  4.30    11.058476mA       11.438869mA          10.949967mA
-  4.40    11.094788mA       11.478151mA          10.985259mA
-  4.50    11.131100mA       11.517432mA          11.020552mA
-  4.60    11.167412mA       11.556714mA          11.055844mA
-  4.70    11.203724mA       11.595995mA          11.091137mA
-  4.80    11.240036mA       11.635277mA          11.126429mA
-  4.90    11.276348mA       11.674559mA          11.161721mA
-  5.00    11.312660mA       11.713840mA          11.197014mA
-  5.10    11.348972mA       11.753122mA          11.232306mA
-  5.20    11.385284mA       11.792403mA          11.267599mA
-  5.30    11.421596mA       11.831685mA          11.302891mA
-  5.40    11.457908mA       11.870967mA          11.338183mA
-  5.50    11.494220mA       11.910248mA          11.373476mA
-  5.60    11.530532mA       11.949530mA          11.408768mA
-  5.70    11.566844mA       11.988811mA          11.444061mA
-  5.80    11.603156mA       12.028093mA          11.479353mA
-  5.90    11.639468mA       12.067375mA          11.514645mA
-  6.00    11.675780mA       12.106656mA          11.549938mA
-  6.10    11.712092mA       12.145938mA          11.585230mA
-  6.20    11.748404mA       12.185219mA          11.620523mA
-  6.30    11.784716mA       12.224501mA          11.655815mA
-  6.40    11.821028mA       12.263783mA          11.691107mA
-  6.50    11.857340mA       12.303064mA          11.726400mA
-  6.60    11.893652mA       12.342346mA          11.761692mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    6.260163mA        5.384933mA           7.315403mA
-  -3.20    6.239699mA        5.366401mA           7.291487mA
-  -3.10    6.219236mA        5.347870mA           7.267570mA
-  -3.00    6.198773mA        5.329339mA           7.243653mA
-  -2.90    6.178310mA        5.310808mA           7.219736mA
-  -2.80    6.157847mA        5.292277mA           7.195819mA
-  -2.70    6.137383mA        5.273745mA           7.171903mA
-  -2.60    6.116920mA        5.255214mA           7.147986mA
-  -2.50    6.096457mA        5.236683mA           7.124069mA
-  -2.40    6.075994mA        5.218152mA           7.100152mA
-  -2.30    6.055531mA        5.199621mA           7.076235mA
-  -2.20    6.035067mA        5.181089mA           7.052319mA
-  -2.10    6.014604mA        5.162558mA           7.028402mA
-  -2.00    5.994141mA        5.144027mA           7.004485mA
-  -1.90    5.973678mA        5.125496mA           6.980568mA
-  -1.80    5.953215mA        5.106965mA           6.956651mA
-  -1.70    5.932751mA        5.088433mA           6.932735mA
-  -1.60    5.912288mA        5.069902mA           6.908818mA
-  -1.50    5.891825mA        5.051371mA           6.884901mA
-  -1.40    5.871362mA        5.032840mA           6.860984mA
-  -1.30    5.850899mA        5.014309mA           6.837067mA
-  -1.20    5.830435mA        4.995777mA           6.813151mA
-  -1.10    5.809972mA        4.977246mA           6.789234mA
-  -1.00    5.789509mA        4.958715mA           6.765317mA
-  -0.90    5.769046mA        4.940184mA           6.741400mA
-  -0.80    5.748583mA        4.921653mA           6.717483mA
-  -0.70    5.728119mA        4.903121mA           6.693567mA
-  -0.60    5.707656mA        4.884590mA           6.669650mA
-  -0.50    5.687193mA        4.866059mA           6.645733mA
-  -0.40    5.666730mA        4.847528mA           6.621816mA
-  -0.30    5.646267mA        4.828997mA           6.597899mA
-  -0.20    4.435786mA        3.802115mA           5.174820mA
-  -0.10    2.131925mA        1.838548mA           2.475669mA
-  0.00    -6.170000nA       -5.460000nA          -7.060000nA
-  0.10    -1.893038mA       -1.673728mA          -2.145840mA
-  0.20    -3.512428mA       -3.164516mA          -3.900829mA
-  0.30    -4.854717mA       -4.471005mA          -5.257719mA
-  0.40    -5.916606mA       -5.591894mA          -6.209108mA
-  0.50    -6.694696mA       -6.525883mA          -6.765898mA
-  0.60    -7.186085mA       -7.271372mA          -7.127487mA
-  0.70    -7.501974mA       -7.827161mA          -7.398777mA
-  0.80    -7.747264mA       -8.192150mA          -7.614967mA
-  0.90    -7.946053mA       -8.442739mA          -7.794856mA
-  1.00    -8.112642mA       -8.647928mA          -7.949846mA
-  1.10    -8.255932mA       -8.820317mA          -8.086935mA
-  1.20    -8.381921mA       -8.968206mA          -8.210725mA
-  1.30    -8.494611mA       -9.097295mA          -8.324315mA
-  1.40    -8.596900mA       -9.211784mA          -8.430004mA
-  1.50    -8.691089mA       -9.314673mA          -8.529494mA
-  1.60    -8.778479mA       -9.407962mA          -8.623884mA
-  1.70    -8.860368mA       -9.493551mA          -8.714073mA
-  1.80    -8.937858mA       -9.572640mA          -8.800963mA
-  1.90    -9.011447mA       -9.646329mA          -8.884952mA
-  2.00    -9.081837mA       -9.715418mA          -8.966642mA
-  2.10    -9.149526mA       -9.780507mA          -9.046332mA
-  2.20    -9.214816mA       -9.842296mA          -9.124421mA
-  2.30    -9.278305mA       -9.901185mA          -9.201211mA
-  2.40    -9.340094mA       -9.957574mA          -9.277001mA
-  2.50    -9.400784mA       -10.011863mA         -9.352391mA
-  2.60    -9.460574mA       -10.063852mA         -9.427582mA
-  2.70    -9.519964mA       -10.115841mA         -9.503173mA
-  2.80    -9.579454mA       -10.165830mA         -9.579563mA
-  2.90    -9.639644mA       -10.215819mA         -9.657654mA
-  3.00    -9.701034mA       -10.264808mA         -9.737845mA
-  3.10    -9.764525mA       -10.315796mA         -9.821135mA
-  3.20    -9.830715mA       -10.367780mA         -9.908326mA
-  3.30    -9.900606mA       -10.421706mA         -10.000817mA
-  3.40    -9.975092mA       -10.478956mA         -10.098808mA
-  3.50    -10.055705mA      -10.535873mA         -10.202798mA
-  3.60    -10.141346mA      -10.578599mA         -10.316786mA
-  3.70    -10.228551mA      -10.620789mA         -10.438679mA
-  3.80    -10.281620mA      -10.662980mA         -10.570555mA
-  3.90    -10.322662mA      -10.705170mA         -10.682977mA
-  4.00    -10.363704mA      -10.747360mA         -10.725640mA
-  4.10    -10.404746mA      -10.789550mA         -10.768303mA
-  4.20    -10.445787mA      -10.831741mA         -10.810966mA
-  4.30    -10.486829mA      -10.873931mA         -10.853629mA
-  4.40    -10.527871mA      -10.916121mA         -10.896292mA
-  4.50    -10.568913mA      -10.958311mA         -10.938955mA
-  4.60    -10.609955mA      -11.000502mA         -10.981618mA
-  4.70    -10.650997mA      -11.042692mA         -11.024281mA
-  4.80    -10.692039mA      -11.084882mA         -11.066944mA
-  4.90    -10.733081mA      -11.127072mA         -11.109607mA
-  5.00    -10.774122mA      -11.169262mA         -11.152270mA
-  5.10    -10.815164mA      -11.211453mA         -11.194933mA
-  5.20    -10.856206mA      -11.253643mA         -11.237597mA
-  5.30    -10.897248mA      -11.295833mA         -11.280260mA
-  5.40    -10.938290mA      -11.338023mA         -11.322923mA
-  5.50    -10.979332mA      -11.380214mA         -11.365586mA
-  5.60    -11.020374mA      -11.422404mA         -11.408249mA
-  5.70    -11.061416mA      -11.464594mA         -11.450912mA
-  5.80    -11.102458mA      -11.506784mA         -11.493575mA
-  5.90    -11.143499mA      -11.548975mA         -11.536238mA
-  6.00    -11.184541mA      -11.591165mA         -11.578901mA
-  6.10    -11.225583mA      -11.633355mA         -11.621564mA
-  6.20    -11.266625mA      -11.675545mA         -11.664227mA
-  6.30    -11.307667mA      -11.717736mA         -11.706890mA
-  6.40    -11.348709mA      -11.759926mA         -11.749553mA
-  6.50    -11.389751mA      -11.802116mA         -11.792216mA
-  6.55    -11.410272mA      -11.823211mA         -11.813548mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.204000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270300uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  0.287529/0.242724n  0.301503/0.328867n  0.291718/0.195168n
-dV/dt_f  0.313320/0.253363n  0.309840/0.389332n  0.311820/0.168025n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.782900V         2.609000V            2.960100V
-0.2020ns          2.783000V         2.608900V            2.962600V
-0.4040ns          2.787900V         2.610900V            3.090500V
-0.6061ns          3.029800V         2.611800V            3.431300V
-0.8081ns          3.255100V         2.678900V            3.466400V
-1.0101ns          3.294700V         2.982700V            3.469200V
-1.2121ns          3.298300V         3.109600V            3.469600V
-1.4141ns          3.299300V         3.123400V            3.469800V
-1.6162ns          3.299600V         3.137700V            3.469900V
-1.8182ns          3.299700V         3.138900V            3.469900V
-2.0202ns          3.299800V         3.139300V            3.469900V
-2.2222ns          3.299900V         3.139600V            3.469900V
-2.4242ns          3.299900V         3.139700V            3.469200V
-2.6263ns          3.299900V         3.139700V            3.471700V
-2.8283ns          3.299900V         3.139800V            3.470600V
-3.0303ns          3.299900V         3.139800V            3.470200V
-3.2323ns          3.299900V         3.139900V            3.470100V
-3.4343ns          3.302400V         3.139900V            3.470000V
-3.6364ns          3.301400V         3.139900V            3.470000V
-3.8384ns          3.300600V         3.139900V            3.470000V
-4.0404ns          3.300200V         3.139900V            3.470000V
-4.2424ns          3.300000V         3.139900V            3.470000V
-4.4444ns          3.300000V         3.139900V            3.470000V
-4.6465ns          3.300000V         3.139900V            3.469900V
-4.8485ns          3.300000V         3.140000V            3.469900V
-5.0505ns          3.300000V         3.141300V            3.469900V
-5.2525ns          3.300000V         3.142100V            3.469900V
-5.4545ns          3.299900V         3.140900V            3.469900V
-5.6566ns          3.299900V         3.140500V            3.469900V
-5.8586ns          3.299900V         3.140200V            3.469900V
-6.0606ns          3.299900V         3.140100V            3.469900V
-6.2626ns          3.299900V         3.140000V            3.469900V
-6.4646ns          3.299900V         3.140000V            3.469900V
-6.6667ns          3.299900V         3.140000V            3.470000V
-6.8687ns          3.299900V         3.140000V            3.470000V
-7.0707ns          3.299900V         3.140000V            3.470000V
-7.2727ns          3.299900V         3.139900V            3.470000V
-7.4747ns          3.299900V         3.139900V            3.470000V
-7.6768ns          3.299900V         3.139900V            3.470000V
-7.8788ns          3.299900V         3.139900V            3.470000V
-8.0808ns          3.299900V         3.139900V            3.470000V
-8.2828ns          3.299900V         3.139900V            3.470000V
-8.4848ns          3.299900V         3.139800V            3.470000V
-8.6869ns          3.299900V         3.139800V            3.470000V
-8.8889ns          3.299900V         3.139900V            3.470000V
-9.0909ns          3.299900V         3.139900V            3.470000V
-9.2929ns          3.299900V         3.139900V            3.470000V
-9.4949ns          3.300000V         3.139900V            3.470000V
-9.6970ns          3.300000V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.139900V            3.470000V
-11.7172ns         3.300000V         3.139900V            3.470000V
-11.9192ns         3.300000V         3.139900V            3.470000V
-12.1212ns         3.300000V         3.139900V            3.470000V
-12.3232ns         3.300000V         3.139900V            3.470000V
-12.5253ns         3.300000V         3.139900V            3.470000V
-12.7273ns         3.300000V         3.139900V            3.470000V
-12.9293ns         3.300000V         3.139900V            3.470000V
-13.1313ns         3.300000V         3.140000V            3.470000V
-13.3333ns         3.300000V         3.140000V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              4.225900uV        4.920300uV           3.956100uV
-0.2020ns          -0.116150mV       2.502300uV           -0.231550mV
-0.4040ns          -1.969300mV       5.640900uV           0.966840mV
-0.6061ns          23.188000mV       -0.508470mV          0.314560V
-0.8081ns          0.256150V         -5.285700mV          0.577600V
-1.0101ns          0.498250V         54.786000mV          0.667290V
-1.2121ns          0.599860V         0.232770V            0.689990V
-1.4141ns          0.636760V         0.420560V            0.696020V
-1.6162ns          0.647730V         0.550470V            0.696970V
-1.8182ns          0.651730V         0.605400V            0.696980V
-2.0202ns          0.652900V         0.628190V            0.696540V
-2.2222ns          0.653040V         0.636320V            0.696120V
-2.4242ns          0.653000V         0.639440V            0.698020V
-2.6263ns          0.652920V         0.640980V            0.608850V
-2.8283ns          0.652830V         0.641740V            0.523850V
-3.0303ns          0.652750V         0.642070V            0.484440V
-3.2323ns          0.652670V         0.642220V            0.464640V
-3.4343ns          0.646540V         0.642370V            0.456500V
-3.6364ns          0.546150V         0.642430V            0.451090V
-3.8384ns          0.483220V         0.642470V            0.449010V
-4.0404ns          0.451320V         0.642490V            0.447190V
-4.2424ns          0.434720V         0.642510V            0.447190V
-4.4444ns          0.427460V         0.642520V            0.447460V
-4.6465ns          0.422730V         0.642530V            0.449720V
-4.8485ns          0.420080V         0.642410V            0.452230V
-5.0505ns          0.418790V         0.647910V            0.454820V
-5.2525ns          0.418520V         0.569370V            0.457130V
-5.4545ns          0.419000V         0.507240V            0.459260V
-5.6566ns          0.420340V         0.472210V            0.461230V
-5.8586ns          0.422900V         0.450470V            0.463090V
-6.0606ns          0.425610V         0.440570V            0.464890V
-6.2626ns          0.428790V         0.434240V            0.466650V
-6.4646ns          0.432030V         0.430580V            0.468260V
-6.6667ns          0.435070V         0.428580V            0.469780V
-6.8687ns          0.437890V         0.427410V            0.471150V
-7.0707ns          0.440590V         0.426660V            0.472420V
-7.2727ns          0.443180V         0.426510V            0.473570V
-7.4747ns          0.445620V         0.426790V            0.474650V
-7.6768ns          0.447910V         0.427810V            0.475620V
-7.8788ns          0.450050V         0.429350V            0.476520V
-8.0808ns          0.452040V         0.431730V            0.477340V
-8.2828ns          0.453900V         0.435000V            0.478100V
-8.4848ns          0.455630V         0.438710V            0.478780V
-8.6869ns          0.457250V         0.442390V            0.479420V
-8.8889ns          0.458760V         0.446040V            0.479990V
-9.0909ns          0.460180V         0.449510V            0.480530V
-9.2929ns          0.461490V         0.452860V            0.481010V
-9.4949ns          0.462720V         0.455990V            0.481460V
-9.6970ns          0.463870V         0.458960V            0.481860V
-9.8990ns          0.464940V         0.461730V            0.482240V
-10.1010ns         0.466405V         0.465580V            0.482735V
-10.3030ns         0.467740V         0.469110V            0.483180V
-10.5051ns         0.468550V         0.471260V            0.483440V
-10.7071ns         0.469310V         0.473300V            0.483680V
-10.9091ns         0.470010V         0.475190V            0.483900V
-11.1111ns         0.470670V         0.476990V            0.484100V
-11.3131ns         0.471280V         0.478660V            0.484280V
-11.5152ns         0.471860V         0.480240V            0.484450V
-11.7172ns         0.472390V         0.481710V            0.484610V
-11.9192ns         0.472890V         0.483100V            0.484740V
-12.1212ns         0.473350V         0.484400V            0.484870V
-12.3232ns         0.473780V         0.485630V            0.484990V
-12.5253ns         0.474180V         0.486770V            0.485100V
-12.7273ns         0.474560V         0.487850V            0.485200V
-12.9293ns         0.474910V         0.488850V            0.485290V
-13.1313ns         0.475230V         0.489800V            0.485370V
-13.3333ns         0.475530V         0.490690V            0.485440V
-13.5354ns         0.475810V         0.491530V            0.485510V
-13.7374ns         0.476080V         0.492300V            0.485570V
-13.9394ns         0.476320V         0.493040V            0.485630V
-14.1414ns         0.476550V         0.493730V            0.485680V
-14.3434ns         0.476760V         0.494380V            0.485730V
-14.5455ns         0.476960V         0.494980V            0.485780V
-14.7475ns         0.477140V         0.495550V            0.485810V
-14.9495ns         0.477310V         0.496080V            0.485850V
-15.1515ns         0.477470V         0.496580V            0.485880V
-15.3535ns         0.477620V         0.497050V            0.485920V
-15.5556ns         0.477760V         0.497490V            0.485940V
-15.7576ns         0.477880V         0.497900V            0.485970V
-15.9596ns         0.478000V         0.498290V            0.485990V
-16.1616ns         0.478110V         0.498650V            0.486010V
-16.3636ns         0.478220V         0.499000V            0.486030V
-16.5657ns         0.478310V         0.499300V            0.486050V
-16.7677ns         0.478400V         0.499590V            0.486070V
-16.9697ns         0.478480V         0.499870V            0.486080V
-17.1717ns         0.478560V         0.500150V            0.486100V
-17.3737ns         0.478630V         0.500410V            0.486110V
-17.5758ns         0.478700V         0.500640V            0.486120V
-17.7778ns         0.478760V         0.500850V            0.486130V
-17.9798ns         0.478820V         0.501040V            0.486140V
-18.1818ns         0.478870V         0.501230V            0.486150V
-18.3838ns         0.478920V         0.501420V            0.486160V
-18.5859ns         0.478970V         0.501600V            0.486160V
-18.7879ns         0.479010V         0.501750V            0.486170V
-18.9899ns         0.479050V         0.501890V            0.486170V
-19.1919ns         0.479090V         0.502030V            0.486180V
-19.3939ns         0.479130V         0.502160V            0.486190V
-19.5960ns         0.479160V         0.502290V            0.486190V
-19.7980ns         0.479190V         0.502400V            0.486190V
-20.0000ns         0.479220V         0.502510V            0.486200V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              0.479590V         0.504150V            0.486240V
-0.2020ns          0.479620V         0.504110V            0.490470V
-0.4040ns          0.474700V         0.515850V            0.339650V
-0.6061ns          0.247410V         0.518820V            26.921000mV
-0.8081ns          33.630000mV       0.443630V            3.148700mV
-1.0101ns          5.280400mV        0.238780V            1.060300mV
-1.2121ns          1.954600mV        78.283000mV          0.294910mV
-1.4141ns          1.002900mV        15.120000mV          0.121950mV
-1.6162ns          0.281790mV        5.205600mV           54.285000uV
-1.8182ns          0.158200mV        2.668100mV           18.736000uV
-2.0202ns          86.848000uV       1.413600mV           -3.438700uV
-2.2222ns          51.525000uV       0.962940mV           -2.338900uV
-2.4242ns          18.844000uV       0.395150mV           -0.402350mV
-2.6263ns          5.905300uV        0.211990mV           -8.792700uV
-2.8283ns          1.900600uV        0.117500mV           -65.770000uV
-3.0303ns          -0.928100uV       94.558000uV          -55.523000uV
-3.2323ns          1.519900uV        57.044000uV          -52.135000uV
-3.4343ns          91.150000uV       30.103000uV          -44.758000uV
-3.6364ns          -33.181000uV      19.965000uV          -45.346000uV
-3.8384ns          -61.875000uV      10.378000uV          -43.013000uV
-4.0404ns          -55.678000uV      5.470400uV           -40.659000uV
-4.2424ns          -56.185000uV      2.225700uV           -38.424000uV
-4.4444ns          -54.079000uV      0.339030uV           -36.424000uV
-4.6465ns          -49.722000uV      42.294000nV          -34.475000uV
-4.8485ns          -47.356000uV      -67.623000uV         -32.629000uV
-5.0505ns          -45.017000uV      0.334260mV           -30.892000uV
-5.2525ns          -42.772000uV      24.321000uV          -29.369000uV
-5.4545ns          -40.550000uV      -57.294000uV         -27.879000uV
-5.6566ns          -38.605000uV      -81.026000uV         -26.455000uV
-5.8586ns          -36.728000uV      -83.374000uV         -25.106000uV
-6.0606ns          -34.884000uV      -73.915000uV         -23.906000uV
-6.2626ns          -33.048000uV      -70.059000uV         -22.718000uV
-6.4646ns          -31.513000uV      -66.837000uV         -21.555000uV
-6.6667ns          -30.051000uV      -63.741000uV         -20.455000uV
-6.8687ns          -28.580000uV      -60.682000uV         -19.480000uV
-7.0707ns          -27.108000uV      -57.943000uV         -18.510000uV
-7.2727ns          -25.888000uV      -55.297000uV         -17.548000uV
-7.4747ns          -24.730000uV      -52.722000uV         -16.641000uV
-7.6768ns          -23.520000uV      -50.167000uV         -15.845000uV
-7.8788ns          -22.298000uV      -47.891000uV         -15.046000uV
-8.0808ns          -21.294000uV      -45.695000uV         -14.242000uV
-8.2828ns          -20.344000uV      -43.550000uV         -13.487000uV
-8.4848ns          -19.327000uV      -41.420000uV         -12.832000uV
-8.6869ns          -18.294000uV      -39.563000uV         -12.169000uV
-8.8889ns          -17.459000uV      -37.784000uV         -11.491000uV
-9.0909ns          -16.672000uV      -36.017000uV         -10.860000uV
-9.2929ns          -15.813000uV      -34.253000uV         -10.318000uV
-9.4949ns          -14.935000uV      -32.736000uV         -9.766400uV
-9.6970ns          -14.237000uV      -31.289000uV         -9.192700uV
-9.8990ns          -13.584000uV      -29.817000uV         -8.661200uV
-10.1010ns         -12.478000uV      -27.709000uV         -7.982350uV
-10.3030ns         -11.518000uV      -25.885000uV         -7.262900uV
-10.5051ns         -10.975000uV      -24.642000uV         -6.813500uV
-10.7071ns         -10.351000uV      -23.387000uV         -6.441800uV
-10.9091ns         -9.707800uV       -22.333000uV         -6.054500uV
-11.1111ns         -9.217800uV       -21.337000uV         -5.636200uV
-11.3131ns         -8.765200uV       -20.281000uV         -5.254700uV
-11.5152ns         -8.231600uV       -19.208000uV         -4.946000uV
-11.7172ns         -7.678200uV       -18.321000uV         -4.620100uV
-11.9192ns         -7.266900uV       -17.488000uV         -4.260300uV
-12.1212ns         -6.890500uV       -16.587000uV         -3.935200uV
-12.3232ns         -6.432500uV       -15.666000uV         -3.678600uV
-12.5253ns         -5.954600uV       -14.919000uV         -3.403800uV
-12.7273ns         -5.609300uV       -14.221000uV         -3.092900uV
-12.9293ns         -5.296400uV       -13.450000uV         -2.814900uV
-13.1313ns         -4.902200uV       -12.657000uV         -2.601600uV
-13.3333ns         -4.488100uV       -12.026000uV         -2.369400uV
-13.5354ns         -4.198200uV       -11.442000uV         -2.099800uV
-13.7374ns         -3.938700uV       -10.780000uV         -1.861200uV
-13.9394ns         -3.598400uV       -10.096000uV         -1.684200uV
-14.1414ns         -3.238300uV       -9.563600uV          -1.487800uV
-14.3434ns         -2.995000uV       -9.074900uV          -1.252900uV
-14.5455ns         -2.780300uV       -8.505800uV          -1.047700uV
-14.7475ns         -2.485800uV       -7.913400uV          -0.901200uV
-14.9495ns         -2.171700uV       -7.464100uV          -0.734910uV
-15.1515ns         -1.967700uV       -7.055800uV          -0.529500uV
-15.3535ns         -1.790700uV       -6.565500uV          -0.352370uV
-15.5556ns         -1.535100uV       -6.051500uV          -0.231220uV
-15.7576ns         -1.260300uV       -5.672300uV          -90.901000nV
-15.9596ns         -1.089700uV       -5.331900uV          87.337000nV
-16.1616ns         -0.944660uV       -4.908600uV          0.238960uV
-16.3636ns         -0.722200uV       -4.461500uV          0.337930uV
-16.5657ns         -0.480790uV       -4.141700uV          0.456510uV
-16.7677ns         -0.338220uV       -3.858700uV          0.613870uV
-16.9697ns         -0.219860uV       -3.492600uV          0.746520uV
-17.1717ns         -26.846000nV      -3.102500uV          0.830300uV
-17.3737ns         0.184450uV        -2.833200uV          0.932440uV
-17.5758ns         0.301760uV        -2.598700uV          1.070900uV
-17.7778ns         0.396050uV        -2.281300uV          1.185800uV
-17.9798ns         0.563350uV        -1.940200uV          1.253900uV
-18.1818ns         0.748530uV        -1.713800uV          1.340400uV
-18.3838ns         0.849240uV        -1.520500uV          1.463300uV
-18.5859ns         0.929260uV        -1.244900uV          1.563400uV
-18.7879ns         1.076500uV        -0.945630uV          1.618300uV
-18.9899ns         1.240200uV        -0.755480uV          1.685500uV
-19.1919ns         1.323300uV        -0.596720uV          1.777100uV
-19.3939ns         1.386600uV        -0.356900uV          1.868700uV
-19.5960ns         1.516000uV        -93.762000nV         1.960300uV
-19.7980ns         1.661600uV        58.234000nV          2.029300uV
-20.0000ns         1.679900uV        0.178250uV           2.053600uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468600V
-0.4040ns          3.300900V         3.139100V            3.481500V
-0.6061ns          3.273500V         3.140100V            3.087100V
-0.8081ns          2.996200V         3.146300V            2.839700V
-1.0101ns          2.788200V         3.080900V            2.749500V
-1.2121ns          2.688900V         2.938500V            2.718000V
-1.4141ns          2.644300V         2.755500V            2.708000V
-1.6162ns          2.624600V         2.644100V            2.704400V
-1.8182ns          2.616600V         2.580800V            2.704300V
-2.0202ns          2.613600V         2.541800V            2.704600V
-2.2222ns          2.612200V         2.522600V            2.705800V
-2.4242ns          2.612400V         2.511700V            2.715900V
-2.6263ns          2.613100V         2.506400V            2.750300V
-2.8283ns          2.613800V         2.503800V            2.759900V
-3.0303ns          2.614700V         2.502700V            2.769100V
-3.2323ns          2.615500V         2.502100V            2.777600V
-3.4343ns          2.621600V         2.502400V            2.785300V
-3.6364ns          2.628100V         2.502800V            2.792600V
-3.8384ns          2.632500V         2.503300V            2.799400V
-4.0404ns          2.639100V         2.503900V            2.806100V
-4.2424ns          2.645800V         2.504500V            2.812200V
-4.4444ns          2.652000V         2.505100V            2.818200V
-4.6465ns          2.658100V         2.505700V            2.823700V
-4.8485ns          2.663800V         2.508100V            2.829100V
-5.0505ns          2.669000V         2.489000V            2.834000V
-5.2525ns          2.674300V         2.476800V            2.838800V
-5.4545ns          2.679100V         2.477300V            2.843300V
-5.6566ns          2.683900V         2.482300V            2.847700V
-5.8586ns          2.688200V         2.488300V            2.851700V
-6.0606ns          2.692500V         2.494500V            2.855700V
-6.2626ns          2.696400V         2.500200V            2.859400V
-6.4646ns          2.700300V         2.505800V            2.863000V
-6.6667ns          2.703900V         2.511100V            2.866300V
-6.8687ns          2.707400V         2.516200V            2.869600V
-7.0707ns          2.710700V         2.521000V            2.872700V
-7.2727ns          2.713900V         2.525700V            2.875700V
-7.4747ns          2.716900V         2.530100V            2.878500V
-7.6768ns          2.719800V         2.534400V            2.881200V
-7.8788ns          2.722500V         2.538400V            2.883800V
-8.0808ns          2.725200V         2.542300V            2.886300V
-8.2828ns          2.727700V         2.545900V            2.888700V
-8.4848ns          2.730200V         2.549500V            2.891000V
-8.6869ns          2.732400V         2.552800V            2.893100V
-8.8889ns          2.734700V         2.556100V            2.895300V
-9.0909ns          2.736800V         2.559100V            2.897300V
-9.2929ns          2.738800V         2.562100V            2.899200V
-9.4949ns          2.740700V         2.564900V            2.901100V
-9.6970ns          2.742600V         2.567700V            2.903000V
-9.8990ns          2.744300V         2.570200V            2.904700V
-10.1010ns         2.746850V         2.573900V            2.907350V
-10.3030ns         2.749200V         2.577400V            2.909900V
-10.5051ns         2.750700V         2.579600V            2.911600V
-10.7071ns         2.752100V         2.581700V            2.913200V
-10.9091ns         2.753400V         2.583700V            2.914800V
-11.1111ns         2.754700V         2.585700V            2.916300V
-11.3131ns         2.756000V         2.587500V            2.917800V
-11.5152ns         2.757200V         2.589300V            2.919300V
-11.7172ns         2.758300V         2.591000V            2.920700V
-11.9192ns         2.759400V         2.592600V            2.922000V
-12.1212ns         2.760400V         2.594200V            2.923300V
-12.3232ns         2.761400V         2.595700V            2.924600V
-12.5253ns         2.762300V         2.597100V            2.925800V
-12.7273ns         2.763200V         2.598500V            2.927000V
-12.9293ns         2.764000V         2.599800V            2.928100V
-13.1313ns         2.764900V         2.601100V            2.929200V
-13.3333ns         2.765600V         2.602300V            2.930200V
-13.5354ns         2.766400V         2.603500V            2.931300V
-13.7374ns         2.767100V         2.604600V            2.932200V
-13.9394ns         2.767800V         2.605700V            2.933200V
-14.1414ns         2.768400V         2.606800V            2.934100V
-14.3434ns         2.769000V         2.607800V            2.935000V
-14.5455ns         2.769600V         2.608700V            2.935800V
-14.7475ns         2.770200V         2.609600V            2.936600V
-14.9495ns         2.770700V         2.610500V            2.937400V
-15.1515ns         2.771200V         2.611300V            2.938200V
-15.3535ns         2.771700V         2.612100V            2.938900V
-15.5556ns         2.772200V         2.612900V            2.939600V
-15.7576ns         2.772600V         2.613600V            2.940300V
-15.9596ns         2.773000V         2.614400V            2.941000V
-16.1616ns         2.773400V         2.615000V            2.941600V
-16.3636ns         2.773800V         2.615700V            2.942200V
-16.5657ns         2.774100V         2.616300V            2.942800V
-16.7677ns         2.774400V         2.616900V            2.943400V
-16.9697ns         2.774700V         2.617500V            2.943900V
-17.1717ns         2.775000V         2.618000V            2.944500V
-17.3737ns         2.775300V         2.618600V            2.945000V
-17.5758ns         2.775600V         2.619100V            2.945500V
-17.7778ns         2.775800V         2.619500V            2.945900V
-17.9798ns         2.776100V         2.620000V            2.946400V
-18.1818ns         2.776300V         2.620400V            2.946900V
-18.3838ns         2.776500V         2.620900V            2.947300V
-18.5859ns         2.776700V         2.621300V            2.947700V
-18.7879ns         2.776900V         2.621700V            2.948100V
-18.9899ns         2.777100V         2.622000V            2.948500V
-19.1919ns         2.777200V         2.622400V            2.948900V
-19.3939ns         2.777400V         2.622700V            2.949300V
-19.5960ns         2.777500V         2.623000V            2.949600V
-19.7980ns         2.777700V         2.623300V            2.950000V
-20.0000ns         2.777800V         2.623600V            2.950300V
-|  
-| End [Model] lvc330f040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330fxxxaaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.201000pA       1.415500nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-| End [Model] lvc330fxxxaaaaaaaain
-|************************************************************************
-[Model]           lvc330fxxxbaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201050A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133030A
-  -1.38    -0.116640A        -0.121710A           -0.116640A
-  -1.30    -0.101410A        -0.107420A           -0.100700A
-  -1.22    -86.417000mA      -93.409000mA         -84.978000mA
-  -1.14    -71.666000mA      -79.637000mA         -69.556000mA
-  -1.06    -57.221000mA      -66.146000mA         -54.661000mA
-  -0.98    -43.217000mA      -53.024000mA         -40.890000mA
-  -0.90    -29.927000mA      -40.408000mA         -29.654000mA
-  -0.82    -17.982000mA      -28.511000mA         -21.115000mA
-  -0.74    -8.854400mA       -17.682000mA         -13.653000mA
-  -0.66    -3.663100mA       -8.577600mA          -7.237700mA
-  -0.58    -1.172200mA       -2.564300mA          -2.648300mA
-  -0.50    -0.318120mA       -0.464400mA          -0.594790mA
-  -0.42    -0.137880mA       -0.131860mA          -0.170510mA
-  -0.34    -0.109480mA       -92.671000uA         -0.122000mA
-  -0.26    -0.105780mA       -87.760000uA         -0.117970mA
-  -0.18    -0.105360mA       -87.079000uA         -0.117690mA
-  -0.10    -0.105300mA       -86.972000uA         -0.117660mA
-  -0.02    -0.105290mA       -86.946000uA         -0.117640mA
-  0.06    -0.105270mA       -86.931000uA         -0.117630mA
-  0.14    -0.105260mA       -86.918000uA         -0.117610mA
-  0.22    -0.105240mA       -86.905000uA         -0.117600mA
-  0.30    -0.105230mA       -86.892000uA         -0.117580mA
-  0.38    -0.105220mA       -86.878000uA         -0.117560mA
-  0.46    -0.105200mA       -86.864000uA         -0.117540mA
-  0.54    -0.105180mA       -86.849000uA         -0.117530mA
-  0.62    -0.105170mA       -86.834000uA         -0.117500mA
-  0.70    -0.105150mA       -86.818000uA         -0.117480mA
-  0.78    -0.105130mA       -86.801000uA         -0.117460mA
-  0.86    -0.105110mA       -86.783000uA         -0.117420mA
-  0.94    -0.105060mA       -86.761000uA         -0.117350mA
-  1.02    -0.105000mA       -86.718000uA         -0.117250mA
-  1.10    -0.104900mA       -86.652000uA         -0.117140mA
-  1.18    -0.104790mA       -86.563000uA         -0.117010mA
-  1.26    -0.104660mA       -86.454000uA         -0.116870mA
-  1.34    -0.104520mA       -86.328000uA         -0.116710mA
-  1.42    -0.104360mA       -86.186000uA         -0.116550mA
-  1.50    -0.104190mA       -86.027000uA         -0.116380mA
-  1.58    -0.104010mA       -85.852000uA         -0.116200mA
-  1.66    -0.103810mA       -85.660000uA         -0.116010mA
-  1.74    -0.103600mA       -85.448000uA         -0.115810mA
-  1.82    -0.103380mA       -85.214000uA         -0.115600mA
-  1.90    -0.103130mA       -84.953000uA         -0.115380mA
-  1.98    -0.102860mA       -84.659000uA         -0.115140mA
-  2.06    -0.102560mA       -84.336000uA         -0.114880mA
-  2.14    -0.102230mA       -83.988000uA         -0.114600mA
-  2.22    -0.101860mA       -83.605000uA         -0.114300mA
-  2.30    -0.101430mA       -83.172000uA         -0.113960mA
-  2.38    -0.100960mA       -82.673000uA         -0.113590mA
-  2.46    -0.100430mA       -82.088000uA         -0.113170mA
-  2.54    -99.809000uA      -81.393000uA         -0.112690mA
-  2.62    -99.072000uA      -80.257000uA         -0.112130mA
-  2.70    -98.172000uA      -76.079000uA         -0.111480mA
-  2.78    -97.041000uA      -68.566000uA         -0.110710mA
-  2.86    -94.411000uA      -58.013000uA         -0.109770mA
-  2.94    -86.817000uA      -44.639000uA         -0.108560mA
-  3.02    -74.531000uA      -28.610000uA         -0.106940mA
-  3.10    -57.975000uA      -10.054000uA         -0.102590mA
-  3.18    -37.471000uA      11.025000uA          -91.172000uA
-  3.26    -13.273000uA      34.949000uA          -73.303000uA
-  3.30    0.149480uA        48.450000uA          -62.148000uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.925400uA        1.695300uA           2.182200uA
-  -3.26    1.907100uA        1.679500uA           2.161600uA
-  -3.22    1.889100uA        1.664000uA           2.141300uA
-  -3.18    1.871200uA        1.648600uA           2.121100uA
-  -3.14    1.853600uA        1.633400uA           2.101200uA
-  -3.10    1.836100uA        1.618400uA           2.081400uA
-  -3.06    1.818900uA        1.603500uA           2.061900uA
-  -3.02    1.801800uA        1.588800uA           2.042600uA
-  -2.98    1.785000uA        1.574200uA           2.023500uA
-  -2.94    1.768300uA        1.559800uA           2.004600uA
-  -2.90    1.751800uA        1.545600uA           1.985900uA
-  -2.86    1.735600uA        1.531500uA           1.967400uA
-  -2.82    1.719500uA        1.517600uA           1.949100uA
-  -2.78    1.703600uA        1.503800uA           1.931100uA
-  -2.74    1.687800uA        1.490200uA           1.913200uA
-  -2.70    1.672300uA        1.476700uA           1.895500uA
-  -2.66    1.657000uA        1.463400uA           1.878100uA
-  -2.62    1.641800uA        1.450200uA           1.860800uA
-  -2.58    1.626800uA        1.437200uA           1.843800uA
-  -2.54    1.612000uA        1.424300uA           1.827000uA
-  -2.50    1.597400uA        1.411500uA           1.810300uA
-  -2.46    1.582900uA        1.398900uA           1.793900uA
-  -2.42    1.568600uA        1.386500uA           1.777600uA
-  -2.38    1.554500uA        1.374100uA           1.761600uA
-  -2.34    1.540600uA        1.361900uA           1.745700uA
-  -2.30    1.526800uA        1.349900uA           1.730100uA
-  -2.26    1.513300uA        1.337900uA           1.714600uA
-  -2.22    1.499800uA        1.326100uA           1.699300uA
-  -2.18    1.486600uA        1.314500uA           1.684300uA
-  -2.14    1.473500uA        1.302900uA           1.669400uA
-  -2.10    1.460500uA        1.291500uA           1.654700uA
-  -2.06    1.447700uA        1.280200uA           1.640100uA
-  -2.02    1.435100uA        1.269000uA           1.625800uA
-  -1.98    1.422600uA        1.257900uA           1.611700uA
-  -1.94    1.410300uA        1.247000uA           1.597700uA
-  -1.90    1.398200uA        1.236200uA           1.583900uA
-  -1.86    1.386100uA        1.225500uA           1.570300uA
-  -1.82    1.374300uA        1.214800uA           1.556900uA
-  -1.78    1.362500uA        1.204400uA           1.543600uA
-  -1.74    1.351000uA        1.194000uA           1.530500uA
-  -1.70    1.339500uA        1.183700uA           1.517600uA
-  -1.66    1.328200uA        1.173500uA           1.504900uA
-  -1.62    1.317000uA        1.163400uA           1.492300uA
-  -1.58    1.306000uA        1.153500uA           1.479900uA
-  -1.54    1.295100uA        1.143600uA           1.467600uA
-  -1.50    1.284300uA        1.133800uA           1.455500uA
-  -1.46    1.273700uA        1.124100uA           1.443600uA
-  -1.42    1.263200uA        1.114500uA           1.431800uA
-  -1.38    1.252800uA        1.105000uA           1.420200uA
-  -1.34    1.242500uA        1.095600uA           1.408700uA
-  -1.30    1.232300uA        1.086200uA           1.397400uA
-  -1.26    1.222300uA        1.077000uA           1.386200uA
-  -1.22    1.212300uA        1.067800uA           1.375200uA
-  -1.18    1.202500uA        1.058700uA           1.364300uA
-  -1.14    1.192800uA        1.049700uA           1.353500uA
-  -1.10    1.183200uA        1.040800uA           1.342900uA
-  -1.06    1.173700uA        1.031900uA           1.332400uA
-  -1.02    1.164300uA        1.023100uA           1.322100uA
-  -0.98    1.154900uA        1.014400uA           1.311900uA
-  -0.94    1.145700uA        1.005700uA           1.301800uA
-  -0.90    1.136600uA        0.997110uA           1.291800uA
-  -0.86    1.127600uA        0.988570uA           1.281900uA
-  -0.82    1.118600uA        0.980090uA           1.272200uA
-  -0.78    1.109700uA        0.971680uA           1.262500uA
-  -0.74    1.100900uA        0.963320uA           1.253000uA
-  -0.70    1.092200uA        0.955010uA           1.243600uA
-  -0.66    1.083600uA        0.946770uA           1.234300uA
-  -0.62    1.075000uA        0.938590uA           1.225100uA
-  -0.58    1.066500uA        0.930470uA           1.215900uA
-  -0.54    1.058100uA        0.922430uA           1.206900uA
-  -0.50    1.049700uA        0.914500uA           1.198000uA
-  -0.46    1.041400uA        0.906750uA           1.189000uA
-  -0.42    1.033100uA        0.899340uA           1.180100uA
-  -0.38    1.024800uA        0.892740uA           1.171100uA
-  -0.34    1.020592uA        0.890363uA           1.166191uA
-  -0.30    1.020569uA        0.890343uA           1.166164uA
-  -0.26    1.020475uA        0.890261uA           1.166058uA
-  -0.22    1.020102uA        0.889935uA           1.165631uA
-  -0.18    1.018607uA        0.888631uA           1.163922uA
-  -0.14    1.012627uA        0.883414uA           1.157089uA
-  -0.10    0.988706uA        0.862546uA           1.129756uA
-  -0.06    0.893025uA        0.779074uA           1.020425uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-| End [Model] lvc330fxxxbaaaaaaain
-|************************************************************************
-[Model]           lvc330fxxxcaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447790A           -0.471180A
-  -2.18    -0.421140A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201050A           -0.209560A
-  -1.62    -0.174190A        -0.174390A           -0.177660A
-  -1.54    -0.150480A        -0.153310A           -0.151880A
-  -1.46    -0.132440A        -0.136600A           -0.133040A
-  -1.38    -0.116650A        -0.121720A           -0.116660A
-  -1.30    -0.101420A        -0.107430A           -0.100730A
-  -1.22    -86.431000mA      -93.414000mA         -85.016000mA
-  -1.14    -71.684000mA      -79.643000mA         -69.612000mA
-  -1.06    -57.245000mA      -66.154000mA         -54.753000mA
-  -0.98    -43.252000mA      -53.034000mA         -41.074000mA
-  -0.90    -29.984000mA      -40.420000mA         -30.037000mA
-  -0.82    -18.095000mA      -28.529000mA         -21.592000mA
-  -0.74    -9.103200mA       -17.711000mA         -14.139000mA
-  -0.66    -4.031300mA       -8.632500mA          -7.727000mA
-  -0.58    -1.542300mA       -2.680900mA          -3.137100mA
-  -0.50    -0.637910mA       -0.641580mA          -1.050200mA
-  -0.42    -0.382200mA       -0.283040mA          -0.537030mA
-  -0.34    -0.274320mA       -0.191220mA          -0.380580mA
-  -0.26    -0.195030mA       -0.134430mA          -0.271430mA
-  -0.18    -0.125260mA       -86.198000uA         -0.174070mA
-  -0.10    -63.603000uA      -43.916000uA         -87.706000uA
-  -0.02    -11.477000uA      -8.053000uA          -15.489000uA
-  0.06    29.171000uA       20.579000uA          38.171000uA
-  0.14    58.135000uA       42.109000uA          72.311000uA
-  0.22    76.454000uA       57.027000uA          90.391000uA
-  0.30    86.646000uA       66.282000uA          99.147000uA
-  0.38    91.915000uA       71.334000uA          0.103720mA
-  0.46    94.550000uA       73.863000uA          0.106370mA
-  0.54    95.817000uA       75.185000uA          0.107930mA
-  0.62    96.442000uA       75.976000uA          0.108770mA
-  0.70    96.793000uA       76.516000uA          0.109190mA
-  0.78    97.021000uA       76.923000uA          0.109410mA
-  0.86    97.187000uA       77.250000uA          0.109550mA
-  0.94    97.320000uA       77.526000uA          0.109650mA
-  1.02    97.431000uA       77.766000uA          0.109720mA
-  1.10    97.528000uA       77.982000uA          0.109790mA
-  1.18    97.616000uA       78.178000uA          0.109850mA
-  1.26    97.697000uA       78.360000uA          0.109900mA
-  1.34    97.773000uA       78.530000uA          0.109950mA
-  1.42    97.844000uA       78.691000uA          0.110000mA
-  1.50    97.912000uA       78.844000uA          0.110050mA
-  1.58    97.978000uA       78.991000uA          0.110090mA
-  1.66    98.042000uA       79.132000uA          0.110130mA
-  1.74    98.104000uA       79.268000uA          0.110170mA
-  1.82    98.164000uA       79.399000uA          0.110220mA
-  1.90    98.223000uA       79.526000uA          0.110260mA
-  1.98    98.280000uA       79.648000uA          0.110300mA
-  2.06    98.337000uA       79.768000uA          0.110330mA
-  2.14    98.393000uA       79.890000uA          0.110370mA
-  2.22    98.448000uA       80.015000uA          0.110410mA
-  2.30    98.503000uA       80.140000uA          0.110450mA
-  2.38    98.559000uA       80.265000uA          0.110490mA
-  2.46    98.617000uA       80.391000uA          0.110530mA
-  2.54    98.679000uA       80.518000uA          0.110570mA
-  2.62    98.744000uA       80.648000uA          0.110620mA
-  2.70    98.813000uA       80.782000uA          0.110670mA
-  2.78    98.889000uA       80.922000uA          0.110720mA
-  2.86    98.972000uA       81.070000uA          0.110780mA
-  2.94    99.065000uA       81.227000uA          0.110850mA
-  3.02    99.170000uA       81.396000uA          0.110930mA
-  3.10    99.290000uA       81.580000uA          0.111020mA
-  3.18    99.427000uA       81.843000uA          0.111120mA
-  3.26    99.584000uA       82.507000uA          0.111250mA
-  3.30    99.674000uA       83.566000uA          0.111320mA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    0.153710mA        0.132100mA           0.170160mA
-  -3.26    0.152730mA        0.131080mA           0.169210mA
-  -3.22    0.151750mA        0.130060mA           0.168250mA
-  -3.18    0.150760mA        0.129030mA           0.167280mA
-  -3.14    0.149760mA        0.128000mA           0.166290mA
-  -3.10    0.148750mA        0.126970mA           0.165290mA
-  -3.06    0.147740mA        0.125930mA           0.164280mA
-  -3.02    0.146720mA        0.124900mA           0.163270mA
-  -2.98    0.145700mA        0.123870mA           0.162240mA
-  -2.94    0.144670mA        0.122850mA           0.161210mA
-  -2.90    0.143640mA        0.121820mA           0.160170mA
-  -2.86    0.142610mA        0.120800mA           0.159120mA
-  -2.82    0.141580mA        0.119780mA           0.158070mA
-  -2.78    0.140550mA        0.118770mA           0.157010mA
-  -2.74    0.139520mA        0.117770mA           0.155950mA
-  -2.70    0.138490mA        0.116770mA           0.154890mA
-  -2.66    0.137460mA        0.115780mA           0.153830mA
-  -2.62    0.136440mA        0.114800mA           0.152760mA
-  -2.58    0.135420mA        0.113820mA           0.151700mA
-  -2.54    0.134410mA        0.112860mA           0.150630mA
-  -2.50    0.133400mA        0.111900mA           0.149570mA
-  -2.46    0.132400mA        0.110960mA           0.148510mA
-  -2.42    0.131410mA        0.110030mA           0.147460mA
-  -2.38    0.130420mA        0.109110mA           0.146410mA
-  -2.34    0.129450mA        0.108200mA           0.145370mA
-  -2.30    0.128490mA        0.107310mA           0.144330mA
-  -2.26    0.127530mA        0.106430mA           0.143310mA
-  -2.22    0.126590mA        0.105570mA           0.142290mA
-  -2.18    0.125660mA        0.104720mA           0.141280mA
-  -2.14    0.124750mA        0.103880mA           0.140280mA
-  -2.10    0.123850mA        0.103060mA           0.139300mA
-  -2.06    0.122960mA        0.102260mA           0.138330mA
-  -2.02    0.122090mA        0.101480mA           0.137370mA
-  -1.98    0.121230mA        0.100710mA           0.136420mA
-  -1.94    0.120390mA        99.955000uA          0.135490mA
-  -1.90    0.119560mA        99.221000uA          0.134580mA
-  -1.86    0.118760mA        98.504000uA          0.133680mA
-  -1.82    0.117970mA        97.804000uA          0.132800mA
-  -1.78    0.117200mA        97.123000uA          0.131940mA
-  -1.74    0.116440mA        96.459000uA          0.131090mA
-  -1.70    0.115710mA        95.814000uA          0.130260mA
-  -1.66    0.114990mA        95.186000uA          0.129460mA
-  -1.62    0.114300mA        94.577000uA          0.128670mA
-  -1.58    0.113620mA        93.985000uA          0.127900mA
-  -1.54    0.112960mA        93.412000uA          0.127150mA
-  -1.50    0.112320mA        92.857000uA          0.126420mA
-  -1.46    0.111700mA        92.319000uA          0.125710mA
-  -1.42    0.111100mA        91.799000uA          0.125030mA
-  -1.38    0.110520mA        91.297000uA          0.124360mA
-  -1.34    0.109960mA        90.812000uA          0.123710mA
-  -1.30    0.109420mA        90.344000uA          0.123090mA
-  -1.26    0.108900mA        89.893000uA          0.122490mA
-  -1.22    0.108400mA        89.459000uA          0.121900mA
-  -1.18    0.107910mA        89.041000uA          0.121340mA
-  -1.14    0.107450mA        88.639000uA          0.120800mA
-  -1.10    0.107000mA        88.253000uA          0.120280mA
-  -1.06    0.106570mA        87.883000uA          0.119780mA
-  -1.02    0.106160mA        87.527000uA          0.119300mA
-  -0.98    0.105760mA        87.187000uA          0.118840mA
-  -0.94    0.105390mA        86.861000uA          0.118400mA
-  -0.90    0.105030mA        86.548000uA          0.117980mA
-  -0.86    0.104690mA        86.250000uA          0.117580mA
-  -0.82    0.104360mA        85.965000uA          0.117190mA
-  -0.78    0.104050mA        85.693000uA          0.116830mA
-  -0.74    0.103750mA        85.433000uA          0.116480mA
-  -0.70    0.103470mA        85.185000uA          0.116150mA
-  -0.66    0.103200mA        84.949000uA          0.115830mA
-  -0.62    0.102950mA        84.724000uA          0.115540mA
-  -0.58    0.102710mA        84.509000uA          0.115260mA
-  -0.54    0.102490mA        84.306000uA          0.114990mA
-  -0.50    0.102270mA        84.112000uA          0.114740mA
-  -0.46    0.102070mA        83.927000uA          0.114500mA
-  -0.42    0.101880mA        83.752000uA          0.114280mA
-  -0.38    0.101700mA        83.587000uA          0.114070mA
-  -0.34    0.101620mA        83.508000uA          0.113960mA
-  -0.30    0.101620mA        83.508000uA          0.113960mA
-  -0.26    0.101620mA        83.508000uA          0.113960mA
-  -0.22    0.101620mA        83.508000uA          0.113960mA
-  -0.18    0.101620mA        83.508000uA          0.113750mA
-  -0.14    0.100460mA        82.918000uA          0.112450mA
-  -0.10    0.100030mA        82.241000uA          0.112040mA
-  -0.06    99.844000uA       81.938000uA          0.111870mA
-  -0.02    99.724000uA       81.761000uA          0.111750mA
-  0.00    99.674000uA       81.693000uA          0.111690mA
-|  
-| End [Model] lvc330fxxxcaaaaaaain
-|************************************************************************
-[Model]           lvc330s040aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
-  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
-  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
-  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
-  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
-  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
-  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
-  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
-  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
-  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
-  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
-  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
-  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
-  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
-  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
-  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
-  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
-  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
-  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
-  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
-  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
-  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
-  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
-  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
-  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
-  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
-  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
-  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
-  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
-  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
-  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
-  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
-  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
-  0.00    9.270000nA        8.640000nA           10.950000nA
-  0.10    2.215985mA        1.960397mA           2.507890mA
-  0.20    4.086375mA        3.683686mA           4.498680mA
-  0.30    5.594166mA        5.150675mA           5.952471mA
-  0.40    6.738256mA        6.352364mA           6.929962mA
-  0.50    7.557146mA        7.289853mA           7.572152mA
-  0.60    8.124436mA        7.983242mA           8.013343mA
-  0.70    8.511126mA        8.476831mA           8.337834mA
-  0.80    8.778316mA        8.826620mA           8.591424mA
-  0.90    8.972606mA        9.080609mA           8.798515mA
-  1.00    9.121395mA        9.272098mA           8.969206mA
-  1.10    9.240584mA        9.422087mA           9.101296mA
-  1.20    9.339574mA        9.543476mA           9.202186mA
-  1.30    9.424063mA        9.644765mA           9.285275mA
-  1.40    9.498053mA        9.731354mA           9.357665mA
-  1.50    9.564242mA        9.806743mA           9.423455mA
-  1.60    9.625232mA        9.873832mA           9.485944mA
-  1.70    9.684621mA        9.934821mA           9.548134mA
-  1.80    9.747011mA        9.992810mA           9.610224mA
-  1.90    9.814800mA        10.052999mA          9.670813mA
-  2.00    9.885689mA        10.122988mA          9.728603mA
-  2.10    9.955379mA        10.203977mA          9.783293mA
-  2.20    10.021968mA       10.292966mA          9.835282mA
-  2.30    10.083958mA       10.380954mA          9.884972mA
-  2.40    10.141947mA       10.464943mA          9.932861mA
-  2.50    10.196936mA       10.542932mA          9.979551mA
-  2.60    10.249926mA       10.614921mA          10.025941mA
-  2.70    10.300915mA       10.681910mA          10.071930mA
-  2.80    10.350904mA       10.744899mA          10.118920mA
-  2.90    10.400894mA       10.805888mA          10.167909mA
-  3.00    10.451883mA       10.863877mA          10.218899mA
-  3.10    10.504872mA       10.921864mA          10.273889mA
-  3.20    10.559862mA       10.978747mA          10.332878mA
-  3.30    10.618848mA       11.037379mA          10.397868mA
-  3.40    10.682725mA       11.085335mA          10.469857mA
-  3.50    10.751986mA       11.124616mA          10.550843mA
-  3.60    10.804292mA       11.163898mA          10.640599mA
-  3.70    10.840604mA       11.203179mA          10.738212mA
-  3.80    10.876916mA       11.242461mA          10.773505mA
-  3.90    10.913228mA       11.281743mA          10.808797mA
-  4.00    10.949540mA       11.321024mA          10.844090mA
-  4.10    10.985852mA       11.360306mA          10.879382mA
-  4.20    11.022164mA       11.399587mA          10.914675mA
-  4.30    11.058476mA       11.438869mA          10.949967mA
-  4.40    11.094788mA       11.478151mA          10.985259mA
-  4.50    11.131100mA       11.517432mA          11.020552mA
-  4.60    11.167412mA       11.556714mA          11.055844mA
-  4.70    11.203724mA       11.595995mA          11.091137mA
-  4.80    11.240036mA       11.635277mA          11.126429mA
-  4.90    11.276348mA       11.674559mA          11.161721mA
-  5.00    11.312660mA       11.713840mA          11.197014mA
-  5.10    11.348972mA       11.753122mA          11.232306mA
-  5.20    11.385284mA       11.792403mA          11.267599mA
-  5.30    11.421596mA       11.831685mA          11.302891mA
-  5.40    11.457908mA       11.870967mA          11.338183mA
-  5.50    11.494220mA       11.910248mA          11.373476mA
-  5.60    11.530532mA       11.949530mA          11.408768mA
-  5.70    11.566844mA       11.988811mA          11.444061mA
-  5.80    11.603156mA       12.028093mA          11.479353mA
-  5.90    11.639468mA       12.067375mA          11.514645mA
-  6.00    11.675780mA       12.106656mA          11.549938mA
-  6.10    11.712092mA       12.145938mA          11.585230mA
-  6.20    11.748404mA       12.185219mA          11.620523mA
-  6.30    11.784716mA       12.224501mA          11.655815mA
-  6.40    11.821028mA       12.263783mA          11.691107mA
-  6.50    11.857340mA       12.303064mA          11.726400mA
-  6.60    11.893652mA       12.342346mA          11.761692mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    6.260163mA        5.384933mA           7.315403mA
-  -3.20    6.239699mA        5.366401mA           7.291487mA
-  -3.10    6.219236mA        5.347870mA           7.267570mA
-  -3.00    6.198773mA        5.329339mA           7.243653mA
-  -2.90    6.178310mA        5.310808mA           7.219736mA
-  -2.80    6.157847mA        5.292277mA           7.195819mA
-  -2.70    6.137383mA        5.273745mA           7.171903mA
-  -2.60    6.116920mA        5.255214mA           7.147986mA
-  -2.50    6.096457mA        5.236683mA           7.124069mA
-  -2.40    6.075994mA        5.218152mA           7.100152mA
-  -2.30    6.055531mA        5.199621mA           7.076235mA
-  -2.20    6.035067mA        5.181089mA           7.052319mA
-  -2.10    6.014604mA        5.162558mA           7.028402mA
-  -2.00    5.994141mA        5.144027mA           7.004485mA
-  -1.90    5.973678mA        5.125496mA           6.980568mA
-  -1.80    5.953215mA        5.106965mA           6.956651mA
-  -1.70    5.932751mA        5.088433mA           6.932735mA
-  -1.60    5.912288mA        5.069902mA           6.908818mA
-  -1.50    5.891825mA        5.051371mA           6.884901mA
-  -1.40    5.871362mA        5.032840mA           6.860984mA
-  -1.30    5.850899mA        5.014309mA           6.837067mA
-  -1.20    5.830435mA        4.995777mA           6.813151mA
-  -1.10    5.809972mA        4.977246mA           6.789234mA
-  -1.00    5.789509mA        4.958715mA           6.765317mA
-  -0.90    5.769046mA        4.940184mA           6.741400mA
-  -0.80    5.748583mA        4.921653mA           6.717483mA
-  -0.70    5.728119mA        4.903121mA           6.693567mA
-  -0.60    5.707656mA        4.884590mA           6.669650mA
-  -0.50    5.687193mA        4.866059mA           6.645733mA
-  -0.40    5.666730mA        4.847528mA           6.621816mA
-  -0.30    5.646267mA        4.828997mA           6.597899mA
-  -0.20    4.435786mA        3.802115mA           5.174820mA
-  -0.10    2.131925mA        1.838548mA           2.475669mA
-  0.00    -6.170000nA       -5.460000nA          -7.060000nA
-  0.10    -1.893038mA       -1.673728mA          -2.145840mA
-  0.20    -3.512428mA       -3.164516mA          -3.900829mA
-  0.30    -4.854717mA       -4.471005mA          -5.257719mA
-  0.40    -5.916606mA       -5.591894mA          -6.209108mA
-  0.50    -6.694696mA       -6.525883mA          -6.765898mA
-  0.60    -7.186085mA       -7.271372mA          -7.127487mA
-  0.70    -7.501974mA       -7.827161mA          -7.398777mA
-  0.80    -7.747264mA       -8.192150mA          -7.614967mA
-  0.90    -7.946053mA       -8.442739mA          -7.794856mA
-  1.00    -8.112642mA       -8.647928mA          -7.949846mA
-  1.10    -8.255932mA       -8.820317mA          -8.086935mA
-  1.20    -8.381921mA       -8.968206mA          -8.210725mA
-  1.30    -8.494611mA       -9.097295mA          -8.324315mA
-  1.40    -8.596900mA       -9.211784mA          -8.430004mA
-  1.50    -8.691089mA       -9.314673mA          -8.529494mA
-  1.60    -8.778479mA       -9.407962mA          -8.623884mA
-  1.70    -8.860368mA       -9.493551mA          -8.714073mA
-  1.80    -8.937858mA       -9.572640mA          -8.800963mA
-  1.90    -9.011447mA       -9.646329mA          -8.884952mA
-  2.00    -9.081837mA       -9.715418mA          -8.966642mA
-  2.10    -9.149526mA       -9.780507mA          -9.046332mA
-  2.20    -9.214816mA       -9.842296mA          -9.124421mA
-  2.30    -9.278305mA       -9.901185mA          -9.201211mA
-  2.40    -9.340094mA       -9.957574mA          -9.277001mA
-  2.50    -9.400784mA       -10.011863mA         -9.352391mA
-  2.60    -9.460574mA       -10.063852mA         -9.427582mA
-  2.70    -9.519964mA       -10.115841mA         -9.503173mA
-  2.80    -9.579454mA       -10.165830mA         -9.579563mA
-  2.90    -9.639644mA       -10.215819mA         -9.657654mA
-  3.00    -9.701034mA       -10.264808mA         -9.737845mA
-  3.10    -9.764525mA       -10.315796mA         -9.821135mA
-  3.20    -9.830715mA       -10.367780mA         -9.908326mA
-  3.30    -9.900606mA       -10.421706mA         -10.000817mA
-  3.40    -9.975092mA       -10.478956mA         -10.098808mA
-  3.50    -10.055705mA      -10.535873mA         -10.202798mA
-  3.60    -10.141346mA      -10.578599mA         -10.316786mA
-  3.70    -10.228551mA      -10.620789mA         -10.438679mA
-  3.80    -10.281620mA      -10.662980mA         -10.570555mA
-  3.90    -10.322662mA      -10.705170mA         -10.682977mA
-  4.00    -10.363704mA      -10.747360mA         -10.725640mA
-  4.10    -10.404746mA      -10.789550mA         -10.768303mA
-  4.20    -10.445787mA      -10.831741mA         -10.810966mA
-  4.30    -10.486829mA      -10.873931mA         -10.853629mA
-  4.40    -10.527871mA      -10.916121mA         -10.896292mA
-  4.50    -10.568913mA      -10.958311mA         -10.938955mA
-  4.60    -10.609955mA      -11.000502mA         -10.981618mA
-  4.70    -10.650997mA      -11.042692mA         -11.024281mA
-  4.80    -10.692039mA      -11.084882mA         -11.066944mA
-  4.90    -10.733081mA      -11.127072mA         -11.109607mA
-  5.00    -10.774122mA      -11.169262mA         -11.152270mA
-  5.10    -10.815164mA      -11.211453mA         -11.194933mA
-  5.20    -10.856206mA      -11.253643mA         -11.237597mA
-  5.30    -10.897248mA      -11.295833mA         -11.280260mA
-  5.40    -10.938290mA      -11.338023mA         -11.322923mA
-  5.50    -10.979332mA      -11.380214mA         -11.365586mA
-  5.60    -11.020374mA      -11.422404mA         -11.408249mA
-  5.70    -11.061416mA      -11.464594mA         -11.450912mA
-  5.80    -11.102458mA      -11.506784mA         -11.493575mA
-  5.90    -11.143499mA      -11.548975mA         -11.536238mA
-  6.00    -11.184541mA      -11.591165mA         -11.578901mA
-  6.10    -11.225583mA      -11.633355mA         -11.621564mA
-  6.20    -11.266625mA      -11.675545mA         -11.664227mA
-  6.30    -11.307667mA      -11.717736mA         -11.706890mA
-  6.40    -11.348709mA      -11.759926mA         -11.749553mA
-  6.50    -11.389751mA      -11.802116mA         -11.792216mA
-  6.55    -11.410272mA      -11.823211mA         -11.813548mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.201000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  0.287457/0.467122n  0.301305/0.700268n  0.291706/0.349090n
-dV/dt_f  0.309900/0.449885n  0.304680/0.837003n  0.308100/0.266290n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.782900V         2.609000V            2.960100V
-0.2020ns          2.783000V         2.608900V            2.962600V
-0.4040ns          2.788300V         2.610900V            3.086900V
-0.6061ns          3.016200V         2.611900V            3.417200V
-0.8081ns          3.244000V         2.678900V            3.463300V
-1.0101ns          3.291900V         2.961800V            3.467200V
-1.2121ns          3.295700V         3.102900V            3.468900V
-1.4141ns          3.297500V         3.120100V            3.469600V
-1.6162ns          3.298700V         3.136000V            3.469800V
-1.8182ns          3.299500V         3.136600V            3.469900V
-2.0202ns          3.299700V         3.137000V            3.469900V
-2.2222ns          3.299800V         3.138000V            3.469900V
-2.4242ns          3.299900V         3.138900V            3.469200V
-2.6263ns          3.299900V         3.139400V            3.471100V
-2.8283ns          3.299900V         3.139700V            3.470500V
-3.0303ns          3.299900V         3.139800V            3.470100V
-3.2323ns          3.299900V         3.139800V            3.470000V
-3.4343ns          3.300600V         3.139900V            3.470000V
-3.6364ns          3.301100V         3.139900V            3.470000V
-3.8384ns          3.300500V         3.139900V            3.470000V
-4.0404ns          3.300200V         3.139900V            3.470000V
-4.2424ns          3.300000V         3.139900V            3.470000V
-4.4444ns          3.300000V         3.139900V            3.470000V
-4.6465ns          3.300000V         3.139900V            3.470000V
-4.8485ns          3.300000V         3.140000V            3.469900V
-5.0505ns          3.300000V         3.140800V            3.469900V
-5.2525ns          3.300000V         3.141300V            3.469900V
-5.4545ns          3.299900V         3.140700V            3.469900V
-5.6566ns          3.299900V         3.140400V            3.469900V
-5.8586ns          3.299900V         3.140200V            3.469900V
-6.0606ns          3.299900V         3.140000V            3.469900V
-6.2626ns          3.299900V         3.140000V            3.469900V
-6.4646ns          3.299900V         3.140000V            3.469900V
-6.6667ns          3.299900V         3.140000V            3.469900V
-6.8687ns          3.299900V         3.140000V            3.469900V
-7.0707ns          3.299900V         3.139900V            3.469900V
-7.2727ns          3.299900V         3.139900V            3.470000V
-7.4747ns          3.299900V         3.139900V            3.470000V
-7.6768ns          3.299900V         3.139900V            3.470000V
-7.8788ns          3.299900V         3.139900V            3.470000V
-8.0808ns          3.299900V         3.139900V            3.470000V
-8.2828ns          3.299900V         3.139900V            3.470000V
-8.4848ns          3.299900V         3.139900V            3.470000V
-8.6869ns          3.299900V         3.139900V            3.470000V
-8.8889ns          3.299900V         3.139800V            3.470000V
-9.0909ns          3.299900V         3.139800V            3.470000V
-9.2929ns          3.299900V         3.139900V            3.470000V
-9.4949ns          3.299900V         3.139900V            3.470000V
-9.6970ns          3.299900V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.139900V            3.470000V
-11.7172ns         3.300000V         3.139900V            3.470000V
-11.9192ns         3.300000V         3.139900V            3.470000V
-12.1212ns         3.300000V         3.139900V            3.470000V
-12.3232ns         3.300000V         3.139900V            3.470000V
-12.5253ns         3.300000V         3.139900V            3.470000V
-12.7273ns         3.300000V         3.139900V            3.470000V
-12.9293ns         3.300000V         3.139900V            3.470000V
-13.1313ns         3.300000V         3.139900V            3.470000V
-13.3333ns         3.300000V         3.139900V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              4.225900uV        4.920300uV           3.956100uV
-0.2020ns          -0.116230mV       2.501000uV           -0.231630mV
-0.4040ns          -1.733400mV       5.664000uV           -6.571900mV
-0.6061ns          1.816900mV        -0.405040mV          0.151930V
-0.8081ns          0.105890V         -6.434700mV          0.334290V
-1.0101ns          0.246820V         13.033000mV          0.470790V
-1.2121ns          0.360950V         89.173000mV          0.542490V
-1.4141ns          0.454430V         0.176030V            0.572640V
-1.6162ns          0.508590V         0.271450V            0.582550V
-1.8182ns          0.534420V         0.353570V            0.588040V
-2.0202ns          0.543170V         0.429910V            0.588930V
-2.2222ns          0.549780V         0.484400V            0.588840V
-2.4242ns          0.550820V         0.517300V            0.590870V
-2.6263ns          0.551300V         0.536250V            0.553540V
-2.8283ns          0.551520V         0.543010V            0.497470V
-3.0303ns          0.551620V         0.548720V            0.468060V
-3.2323ns          0.551660V         0.549820V            0.453000V
-3.4343ns          0.558640V         0.550520V            0.446500V
-3.6364ns          0.508640V         0.550950V            0.442330V
-3.8384ns          0.463860V         0.551240V            0.440380V
-4.0404ns          0.438900V         0.551370V            0.438930V
-4.2424ns          0.425590V         0.551450V            0.438730V
-4.4444ns          0.417880V         0.551520V            0.438850V
-4.6465ns          0.413990V         0.551560V            0.439830V
-4.8485ns          0.411950V         0.551690V            0.441070V
-5.0505ns          0.411060V         0.558950V            0.443300V
-5.2525ns          0.410360V         0.519020V            0.446000V
-5.4545ns          0.410640V         0.480460V            0.448850V
-5.6566ns          0.411100V         0.455460V            0.451660V
-5.8586ns          0.412570V         0.440580V            0.454380V
-6.0606ns          0.414210V         0.430510V            0.456880V
-6.2626ns          0.416980V         0.426080V            0.459280V
-6.4646ns          0.420210V         0.423650V            0.461440V
-6.6667ns          0.423660V         0.422350V            0.463510V
-6.8687ns          0.426990V         0.421790V            0.465350V
-7.0707ns          0.430100V         0.421350V            0.467110V
-7.2727ns          0.433090V         0.421520V            0.468670V
-7.4747ns          0.435900V         0.421800V            0.470160V
-7.6768ns          0.438640V         0.422560V            0.471470V
-7.8788ns          0.441270V         0.423400V            0.472730V
-8.0808ns          0.443800V         0.425080V            0.473840V
-8.2828ns          0.446130V         0.426920V            0.474900V
-8.4848ns          0.448370V         0.429830V            0.475830V
-8.6869ns          0.450420V         0.433230V            0.476730V
-8.8889ns          0.452380V         0.436930V            0.477510V
-9.0909ns          0.454180V         0.440610V            0.478270V
-9.2929ns          0.455900V         0.444280V            0.478930V
-9.4949ns          0.457470V         0.447610V            0.479560V
-9.6970ns          0.458970V         0.450880V            0.480120V
-9.8990ns          0.460340V         0.453950V            0.480650V
-10.1010ns         0.462260V         0.458380V            0.481335V
-10.3030ns         0.464000V         0.462500V            0.481950V
-10.5051ns         0.465050V         0.464970V            0.482320V
-10.7071ns         0.466050V         0.467390V            0.482650V
-10.9091ns         0.466960V         0.469580V            0.482960V
-11.1111ns         0.467830V         0.471720V            0.483240V
-11.3131ns         0.468630V         0.473660V            0.483500V
-11.5152ns         0.469380V         0.475550V            0.483730V
-11.7172ns         0.470080V         0.477260V            0.483950V
-11.9192ns         0.470740V         0.478940V            0.484140V
-12.1212ns         0.471340V         0.480450V            0.484330V
-12.3232ns         0.471910V         0.481930V            0.484490V
-12.5253ns         0.472440V         0.483270V            0.484640V
-12.7273ns         0.472930V         0.484580V            0.484780V
-12.9293ns         0.473390V         0.485750V            0.484900V
-13.1313ns         0.473820V         0.486910V            0.485020V
-13.3333ns         0.474220V         0.487950V            0.485120V
-13.5354ns         0.474590V         0.488970V            0.485220V
-13.7374ns         0.474940V         0.489880V            0.485310V
-13.9394ns         0.475260V         0.490780V            0.485390V
-14.1414ns         0.475560V         0.491590V            0.485460V
-14.3434ns         0.475840V         0.492380V            0.485530V
-14.5455ns         0.476100V         0.493090V            0.485590V
-14.7475ns         0.476340V         0.493790V            0.485640V
-14.9495ns         0.476570V         0.494420V            0.485700V
-15.1515ns         0.476780V         0.495030V            0.485740V
-15.3535ns         0.476970V         0.495580V            0.485790V
-15.5556ns         0.477160V         0.496120V            0.485820V
-15.7576ns         0.477330V         0.496610V            0.485860V
-15.9596ns         0.477490V         0.497090V            0.485890V
-16.1616ns         0.477630V         0.497510V            0.485920V
-16.3636ns         0.477770V         0.497930V            0.485950V
-16.5657ns         0.477890V         0.498290V            0.485980V
-16.7677ns         0.478010V         0.498640V            0.486000V
-16.9697ns         0.478120V         0.498990V            0.486020V
-17.1717ns         0.478230V         0.499340V            0.486040V
-17.3737ns         0.478320V         0.499630V            0.486060V
-17.5758ns         0.478410V         0.499920V            0.486070V
-17.7778ns         0.478490V         0.500160V            0.486090V
-17.9798ns         0.478570V         0.500400V            0.486100V
-18.1818ns         0.478640V         0.500630V            0.486110V
-18.3838ns         0.478710V         0.500870V            0.486120V
-18.5859ns         0.478770V         0.501070V            0.486130V
-18.7879ns         0.478830V         0.501260V            0.486140V
-18.9899ns         0.478880V         0.501430V            0.486150V
-19.1919ns         0.478930V         0.501590V            0.486160V
-19.3939ns         0.478980V         0.501750V            0.486170V
-19.5960ns         0.479020V         0.501910V            0.486170V
-19.7980ns         0.479060V         0.502040V            0.486180V
-20.0000ns         0.479100V         0.502180V            0.486180V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              0.479590V         0.504150V            0.486240V
-0.2020ns          0.479620V         0.504110V            0.490470V
-0.4040ns          0.474660V         0.515850V            0.338690V
-0.6061ns          0.260970V         0.518810V            49.227000mV
-0.8081ns          57.693000mV       0.442430V            5.358900mV
-1.0101ns          10.006000mV       0.270560V            1.610600mV
-1.2121ns          3.219300mV        0.116620V            0.420340mV
-1.4141ns          1.539600mV        28.455000mV          0.168590mV
-1.6162ns          0.544500mV        9.235500mV           63.243000uV
-1.8182ns          0.242750mV        4.555900mV           28.107000uV
-2.0202ns          0.152510mV        2.530000mV           3.232400uV
-2.2222ns          71.354000uV       1.674500mV           0.754660uV
-2.4242ns          30.528000uV       0.925740mV           -0.544570mV
-2.6263ns          17.219000uV       0.496800mV           -0.223670mV
-2.8283ns          7.642900uV        0.286310mV           -18.013000uV
-3.0303ns          2.754100uV        0.206810mV           -16.664000uV
-3.2323ns          3.719000uV        0.129010mV           -14.948000uV
-3.4343ns          -0.126320mV       73.076000uV          -9.356000uV
-3.6364ns          -0.242850mV       44.601000uV          -11.098000uV
-3.8384ns          -32.574000uV      27.309000uV          -9.946200uV
-4.0404ns          3.566200uV        14.959000uV          -9.483100uV
-4.2424ns          -5.306100uV       8.251900uV           -8.932600uV
-4.4444ns          -13.750000uV      4.915800uV           -8.381600uV
-4.6465ns          10.940000uV       2.652800uV           -7.820100uV
-4.8485ns          18.035000uV       -0.108180mV          -7.265300uV
-5.0505ns          2.807200uV        0.153640mV           -6.819000uV
-5.2525ns          2.502100uV        -0.230170mV          -6.373400uV
-5.4545ns          3.131600uV        -97.756000uV         -5.936700uV
-5.6566ns          2.983900uV        -12.193000uV         -5.505100uV
-5.8586ns          2.947300uV        25.147000uV          -5.155800uV
-6.0606ns          3.185500uV        13.918000uV          -4.806500uV
-6.2626ns          3.361600uV        13.732000uV          -4.457800uV
-6.4646ns          3.383800uV        15.275000uV          -4.112200uV
-6.6667ns          3.430500uV        14.174000uV          -3.816000uV
-6.8687ns          3.538200uV        13.495000uV          -3.520100uV
-7.0707ns          3.619900uV        13.582000uV          -3.230000uV
-7.2727ns          3.637500uV        13.501000uV          -2.942000uV
-7.4747ns          3.665100uV        13.116000uV          -2.688300uV
-7.6768ns          3.717300uV        12.820000uV          -2.435300uV
-7.8788ns          3.759700uV        12.684000uV          -2.191800uV
-8.0808ns          3.777800uV        12.528000uV          -1.949700uV
-8.2828ns          3.800700uV        12.338000uV          -1.731900uV
-8.4848ns          3.835100uV        12.144000uV          -1.514700uV
-8.6869ns          3.864700uV        11.942000uV          -1.308300uV
-8.8889ns          3.882800uV        11.757000uV          -1.103000uV
-9.0909ns          3.903100uV        11.601000uV          -0.916190uV
-9.2929ns          3.928900uV        11.419000uV          -0.730020uV
-9.4949ns          3.951900uV        11.189000uV          -0.554530uV
-9.6970ns          3.968200uV        10.989000uV          -0.379920uV
-9.8990ns          3.985700uV        10.842000uV          -0.219880uV
-10.1010ns         4.015950uV        10.553500uV          12.615000nV
-10.3030ns         4.039500uV        10.248000uV          0.231740uV
-10.5051ns         4.054400uV        10.116000uV          0.368100uV
-10.7071ns         4.071500uV        9.956800uV           0.504010uV
-10.9091ns         4.087100uV        9.748000uV           0.632480uV
-11.1111ns         4.098800uV        9.573200uV           0.760290uV
-11.3131ns         4.111100uV        9.460300uV           0.877400uV
-11.5152ns         4.125100uV        9.320800uV           0.994070uV
-11.7172ns         4.137800uV        9.133200uV           1.103600uV
-11.9192ns         4.147200uV        8.978700uV           1.212600uV
-12.1212ns         4.157100uV        8.884300uV           1.313000uV
-12.3232ns         4.168500uV        8.764100uV           1.413100uV
-12.5253ns         4.178700uV        8.597200uV           1.506700uV
-12.7273ns         4.186000uV        8.456400uV           1.599900uV
-12.9293ns         4.193900uV        8.362900uV           1.686000uV
-13.1313ns         4.203100uV        8.269500uV           1.771700uV
-13.3333ns         4.211200uV        8.176000uV           1.851800uV
-13.5354ns         4.216800uV        8.065600uV           1.931600uV
-13.7374ns         4.222900uV        7.924500uV           2.005300uV
-13.9394ns         4.230300uV        7.808100uV           2.078800uV
-14.1414ns         4.236700uV        7.736300uV           2.147500uV
-14.3434ns         4.240800uV        7.664500uV           2.215800uV
-14.5455ns         4.245400uV        7.592700uV           2.279000uV
-14.7475ns         4.251200uV        7.503700uV           2.342000uV
-14.9495ns         4.256200uV        7.383500uV           2.400800uV
-15.1515ns         4.259000uV        7.286500uV           2.459400uV
-15.3535ns         4.262400uV        7.231700uV           2.513600uV
-15.5556ns         4.267000uV        7.176900uV           2.567700uV
-15.7576ns         4.270800uV        7.122100uV           2.618100uV
-15.9596ns         4.272600uV        7.049900uV           2.668300uV
-16.1616ns         4.274900uV        6.946400uV           2.714800uV
-16.3636ns         4.278400uV        6.865000uV           2.761200uV
-16.5657ns         4.281200uV        6.823600uV           2.804400uV
-16.7677ns         4.282300uV        6.782200uV           2.847500uV
-16.9697ns         4.283800uV        6.740700uV           2.887400uV
-17.1717ns         4.286400uV        6.682100uV           2.927100uV
-17.3737ns         4.288400uV        6.592100uV           2.964200uV
-17.5758ns         4.288700uV        6.523200uV           3.001200uV
-17.7778ns         4.289500uV        6.492500uV           3.035400uV
-17.9798ns         4.291500uV        6.461700uV           3.069500uV
-18.1818ns         4.292800uV        6.430900uV           3.101400uV
-18.3838ns         4.292600uV        6.383000uV           3.133100uV
-18.5859ns         4.292900uV        6.304200uV           3.162500uV
-18.7879ns         4.294300uV        6.245400uV           3.191700uV
-18.9899ns         4.295100uV        6.223200uV           3.219100uV
-19.1919ns         4.294400uV        6.200900uV           3.246200uV
-19.3939ns         4.294300uV        6.178600uV           3.270600uV
-19.5960ns         4.295200uV        6.139500uV           3.294900uV
-19.7980ns         4.295400uV        6.069700uV           3.319200uV
-20.0000ns         4.294000uV        6.076600uV           3.343600uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468600V
-0.4040ns          3.300900V         3.139100V            3.483300V
-0.6061ns          3.304400V         3.140100V            3.272000V
-0.8081ns          3.179500V         3.145900V            3.030300V
-1.0101ns          3.015400V         3.136300V            2.907000V
-1.2121ns          2.895000V         3.095000V            2.856700V
-1.4141ns          2.821600V         2.995500V            2.837500V
-1.6162ns          2.781500V         2.910100V            2.829200V
-1.8182ns          2.760300V         2.834600V            2.826700V
-2.0202ns          2.751400V         2.769700V            2.825700V
-2.2222ns          2.745500V         2.722000V            2.826100V
-2.4242ns          2.743500V         2.688600V            2.830900V
-2.6263ns          2.743000V         2.667400V            2.878100V
-2.8283ns          2.742800V         2.654200V            2.895900V
-3.0303ns          2.742900V         2.645000V            2.900000V
-3.2323ns          2.743200V         2.639400V            2.902500V
-3.4343ns          2.756300V         2.636600V            2.904500V
-3.6364ns          2.776700V         2.635200V            2.906500V
-3.8384ns          2.790100V         2.634000V            2.908200V
-4.0404ns          2.792600V         2.633800V            2.909800V
-4.2424ns          2.793100V         2.633700V            2.911300V
-4.4444ns          2.793600V         2.633900V            2.912900V
-4.6465ns          2.793500V         2.634100V            2.914200V
-4.8485ns          2.793500V         2.636300V            2.915600V
-5.0505ns          2.793500V         2.635700V            2.916900V
-5.2525ns          2.793500V         2.642300V            2.918100V
-5.4545ns          2.793500V         2.652700V            2.919300V
-5.6566ns          2.793400V         2.656300V            2.920400V
-5.8586ns          2.793400V         2.655900V            2.921400V
-6.0606ns          2.793300V         2.655100V            2.922500V
-6.2626ns          2.793200V         2.654600V            2.923500V
-6.4646ns          2.793100V         2.654000V            2.924400V
-6.6667ns          2.793000V         2.653400V            2.925300V
-6.8687ns          2.792900V         2.652800V            2.926200V
-7.0707ns          2.792800V         2.652200V            2.927100V
-7.2727ns          2.792700V         2.651700V            2.928000V
-7.4747ns          2.792600V         2.651100V            2.928900V
-7.6768ns          2.792500V         2.650500V            2.929700V
-7.8788ns          2.792300V         2.650000V            2.930600V
-8.0808ns          2.792200V         2.649500V            2.931500V
-8.2828ns          2.792100V         2.648900V            2.932300V
-8.4848ns          2.791900V         2.648400V            2.933200V
-8.6869ns          2.791800V         2.647900V            2.934100V
-8.8889ns          2.791600V         2.647400V            2.935000V
-9.0909ns          2.791500V         2.647000V            2.935800V
-9.2929ns          2.791300V         2.646500V            2.936600V
-9.4949ns          2.791200V         2.646000V            2.937400V
-9.6970ns          2.791000V         2.645600V            2.938200V
-9.8990ns          2.790900V         2.645100V            2.939000V
-10.1010ns         2.790650V         2.644500V            2.940050V
-10.3030ns         2.790400V         2.643900V            2.941100V
-10.5051ns         2.790200V         2.643500V            2.941700V
-10.7071ns         2.790100V         2.643100V            2.942400V
-10.9091ns         2.789900V         2.642700V            2.943000V
-11.1111ns         2.789700V         2.642400V            2.943600V
-11.3131ns         2.789600V         2.642000V            2.944100V
-11.5152ns         2.789400V         2.641600V            2.944700V
-11.7172ns         2.789200V         2.641300V            2.945200V
-11.9192ns         2.789100V         2.641000V            2.945700V
-12.1212ns         2.788900V         2.640600V            2.946200V
-12.3232ns         2.788700V         2.640300V            2.946700V
-12.5253ns         2.788600V         2.640000V            2.947100V
-12.7273ns         2.788400V         2.639700V            2.947600V
-12.9293ns         2.788200V         2.639400V            2.948000V
-13.1313ns         2.788000V         2.639100V            2.948400V
-13.3333ns         2.787900V         2.638900V            2.948800V
-13.5354ns         2.787700V         2.638600V            2.949200V
-13.7374ns         2.787500V         2.638300V            2.949600V
-13.9394ns         2.787400V         2.638000V            2.949900V
-14.1414ns         2.787200V         2.637800V            2.950300V
-14.3434ns         2.787000V         2.637500V            2.950600V
-14.5455ns         2.786900V         2.637300V            2.950900V
-14.7475ns         2.786700V         2.637100V            2.951200V
-14.9495ns         2.786500V         2.636800V            2.951500V
-15.1515ns         2.786400V         2.636600V            2.951800V
-15.3535ns         2.786200V         2.636400V            2.952100V
-15.5556ns         2.786100V         2.636100V            2.952400V
-15.7576ns         2.785900V         2.635900V            2.952600V
-15.9596ns         2.785800V         2.635700V            2.952900V
-16.1616ns         2.785600V         2.635500V            2.953100V
-16.3636ns         2.785500V         2.635300V            2.953400V
-16.5657ns         2.785300V         2.635100V            2.953600V
-16.7677ns         2.785200V         2.634900V            2.953800V
-16.9697ns         2.785000V         2.634700V            2.954000V
-17.1717ns         2.784900V         2.634500V            2.954200V
-17.3737ns         2.784800V         2.634300V            2.954400V
-17.5758ns         2.784600V         2.634200V            2.954600V
-17.7778ns         2.784500V         2.634000V            2.954800V
-17.9798ns         2.784400V         2.633800V            2.955000V
-18.1818ns         2.784300V         2.633600V            2.955100V
-18.3838ns         2.784200V         2.633500V            2.955300V
-18.5859ns         2.784100V         2.633300V            2.955500V
-18.7879ns         2.784000V         2.633100V            2.955600V
-18.9899ns         2.783900V         2.633000V            2.955800V
-19.1919ns         2.783800V         2.632800V            2.955900V
-19.3939ns         2.783700V         2.632700V            2.956100V
-19.5960ns         2.783600V         2.632500V            2.956200V
-19.7980ns         2.783600V         2.632400V            2.956300V
-20.0000ns         2.783500V         2.632200V            2.956500V
-|  
-| End [Model] lvc330s040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330s140aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -50.584550mA      -43.999960mA         -54.623576mA
-  -3.20    -50.404450mA      -43.837800mA         -54.427552mA
-  -3.10    -50.224350mA      -43.675640mA         -54.231528mA
-  -3.00    -50.044250mA      -43.513480mA         -54.035504mA
-  -2.90    -49.864150mA      -43.351320mA         -53.839480mA
-  -2.80    -49.684050mA      -43.189160mA         -53.643456mA
-  -2.70    -49.503950mA      -43.027000mA         -53.447432mA
-  -2.60    -49.323850mA      -42.864840mA         -53.251408mA
-  -2.50    -49.143750mA      -42.702680mA         -53.055384mA
-  -2.40    -48.963650mA      -42.540520mA         -52.859360mA
-  -2.30    -48.783550mA      -42.378360mA         -52.663336mA
-  -2.20    -48.603450mA      -42.216200mA         -52.467312mA
-  -2.10    -48.423350mA      -42.054040mA         -52.271288mA
-  -2.00    -48.243250mA      -41.891880mA         -52.075264mA
-  -1.90    -48.063150mA      -41.729720mA         -51.879240mA
-  -1.80    -47.883050mA      -41.567560mA         -51.683216mA
-  -1.70    -47.702950mA      -41.405400mA         -51.487192mA
-  -1.60    -47.522850mA      -41.243240mA         -51.291168mA
-  -1.50    -47.342750mA      -41.081080mA         -51.095144mA
-  -1.40    -47.162650mA      -40.960000mA         -50.899120mA
-  -1.30    -46.982550mA      -40.310000mA         -50.703096mA
-  -1.20    -46.802450mA      -39.409000mA         -50.507072mA
-  -1.10    -46.622350mA      -38.410000mA         -50.311048mA
-  -1.00    -46.442250mA      -37.323000mA         -50.115024mA
-  -0.90    -46.262150mA      -36.180000mA         -49.919000mA
-  -0.80    -46.082050mA      -35.076000mA         -49.327000mA
-  -0.70    -45.748900mA      -34.427000mA         -47.994000mA
-  -0.60    -42.249200mA      -34.203200mA         -45.776900mA
-  -0.50    -36.169470mA      -30.752860mA         -40.603750mA
-  -0.40    -29.014551mA      -24.879886mA         -32.919898mA
-  -0.30    -21.670346mA      -18.677585mA         -24.687602mA
-  -0.20    -14.338705mA      -12.435585mA         -16.367748mA
-  -0.10    -7.093292mA       -6.195266mA          -8.095791mA
-  0.00    27.190000nA       25.680000nA          31.680000nA
-  0.10    6.587285mA        5.878497mA           7.387890mA
-  0.20    12.314175mA       11.156186mA          13.529180mA
-  0.30    17.106166mA       15.766175mA          18.285171mA
-  0.40    20.907156mA       19.661164mA          21.673162mA
-  0.50    23.747146mA       22.813153mA          23.968152mA
-  0.60    25.783136mA       25.234142mA          25.549143mA
-  0.70    27.212126mA       27.008131mA          26.699134mA
-  0.80    28.206116mA       28.280120mA          27.588124mA
-  0.90    28.917106mA       29.203109mA          28.308115mA
-  1.00    29.453095mA       29.892098mA          28.908106mA
-  1.10    29.875084mA       30.426087mA          29.398096mA
-  1.20    30.221074mA       30.854076mA          29.770086mA
-  1.30    30.513063mA       31.208065mA          30.064075mA
-  1.40    30.767053mA       31.507054mA          30.315065mA
-  1.50    30.993042mA       31.766043mA          30.542055mA
-  1.60    31.203032mA       31.995032mA          30.762044mA
-  1.70    31.414021mA       32.204021mA          30.983034mA
-  1.80    31.648011mA       32.407010mA          31.201024mA
-  1.90    31.903000mA       32.633999mA          31.408013mA
-  2.00    32.157989mA       32.912988mA          31.601003mA
-  2.10    32.398979mA       33.235977mA          31.780993mA
-  2.20    32.620968mA       33.562966mA          31.951982mA
-  2.30    32.826958mA       33.870954mA          32.113972mA
-  2.40    33.017947mA       34.153943mA          32.268961mA
-  2.50    33.197936mA       34.411932mA          32.419951mA
-  2.60    33.368926mA       34.647921mA          32.567941mA
-  2.70    33.532915mA       34.866910mA          32.714930mA
-  2.80    33.693904mA       35.070899mA          32.864920mA
-  2.90    33.851894mA       35.264888mA          33.017909mA
-  3.00    34.012883mA       35.450877mA          33.177899mA
-  3.10    34.176872mA       35.632864mA          33.347889mA
-  3.20    34.349862mA       35.813747mA          33.531878mA
-  3.30    34.531848mA       35.996379mA          33.730868mA
-  3.40    34.729725mA       36.157497mA          33.951857mA
-  3.50    34.942986mA       36.297102mA          34.196843mA
-  3.60    35.117958mA       36.436708mA          34.470599mA
-  3.70    35.251602mA       36.576313mA          34.772212mA
-  3.80    35.385246mA       36.715919mA          34.904053mA
-  3.90    35.518890mA       36.855525mA          35.035893mA
-  4.00    35.652534mA       36.995130mA          35.167734mA
-  4.10    35.786178mA       37.134736mA          35.299574mA
-  4.20    35.919822mA       37.274341mA          35.431414mA
-  4.30    36.053466mA       37.413947mA          35.563255mA
-  4.40    36.187110mA       37.553553mA          35.695095mA
-  4.50    36.320754mA       37.693158mA          35.826936mA
-  4.60    36.454398mA       37.832764mA          35.958776mA
-  4.70    36.588042mA       37.972369mA          36.090616mA
-  4.80    36.721686mA       38.111975mA          36.222457mA
-  4.90    36.855330mA       38.251581mA          36.354297mA
-  5.00    36.988974mA       38.391186mA          36.486138mA
-  5.10    37.122618mA       38.530792mA          36.617978mA
-  5.20    37.256262mA       38.670397mA          36.749818mA
-  5.30    37.389906mA       38.810003mA          36.881659mA
-  5.40    37.523550mA       38.949609mA          37.013499mA
-  5.50    37.657194mA       39.089214mA          37.145340mA
-  5.60    37.790838mA       39.228820mA          37.277180mA
-  5.70    37.924482mA       39.368425mA          37.409020mA
-  5.80    38.058126mA       39.508031mA          37.540861mA
-  5.90    38.191770mA       39.647637mA          37.672701mA
-  6.00    38.325414mA       39.787242mA          37.804542mA
-  6.10    38.459058mA       39.926848mA          37.936382mA
-  6.20    38.592702mA       40.066453mA          38.068222mA
-  6.30    38.726346mA       40.206059mA          38.200063mA
-  6.40    38.859990mA       40.345665mA          38.331903mA
-  6.50    38.993634mA       40.485270mA          38.463744mA
-  6.60    39.127278mA       40.624876mA          38.595584mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    66.669757mA       87.094613mA          92.797733mA
-  -3.20    66.440741mA       86.767866mA          92.515330mA
-  -3.10    66.211726mA       86.441119mA          92.232928mA
-  -3.00    65.982711mA       86.114372mA          91.950525mA
-  -2.90    65.753695mA       85.787625mA          91.668122mA
-  -2.80    65.524680mA       85.460878mA          91.385720mA
-  -2.70    65.295664mA       85.134131mA          91.103317mA
-  -2.60    65.066649mA       84.807384mA          90.820915mA
-  -2.50    64.837633mA       84.480636mA          90.538512mA
-  -2.40    64.608618mA       84.153889mA          90.256109mA
-  -2.30    64.379602mA       83.827142mA          89.973707mA
-  -2.20    64.150587mA       83.500395mA          89.691304mA
-  -2.10    63.921571mA       83.173648mA          89.408901mA
-  -2.00    63.692556mA       82.846901mA          89.126499mA
-  -1.90    63.463540mA       82.520154mA          88.844096mA
-  -1.80    63.234525mA       82.323794mA          88.561693mA
-  -1.70    63.005509mA       81.008819mA          88.279291mA
-  -1.60    62.776494mA       78.640845mA          87.996888mA
-  -1.50    62.547479mA       75.568869mA          87.714485mA
-  -1.40    62.318463mA       71.978893mA          87.432083mA
-  -1.30    62.089448mA       67.983917mA          87.149680mA
-  -1.20    61.860432mA       63.658940mA          86.867278mA
-  -1.10    61.631417mA       59.058962mA          86.584875mA
-  -1.00    61.402401mA       54.225984mA          80.067686mA
-  -0.90    61.173386mA       49.192006mA          71.275712mA
-  -0.80    54.621889mA       45.212027mA          61.996736mA
-  -0.70    47.050911mA       41.794048mA          52.900760mA
-  -0.60    39.442932mA       35.550069mA          44.185783mA
-  -0.50    32.215954mA       29.164089mA          36.006805mA
-  -0.40    25.419974mA       23.007107mA          28.393828mA
-  -0.30    17.101700mA       15.824500mA          19.002300mA
-  -0.20    12.464986mA       11.277815mA          13.918820mA
-  -0.10    6.164125mA        5.580948mA           6.877969mA
-  0.00    -18.490000nA      -17.070000nA         -20.440000nA
-  0.10    -5.904938mA       -5.394928mA          -6.530140mA
-  0.20    -11.454128mA      -10.553116mA         -12.558129mA
-  0.30    -16.640117mA      -15.473105mA         -18.069119mA
-  0.40    -21.457106mA      -20.150094mA         -23.046108mA
-  0.50    -25.896096mA      -24.583083mA         -27.475098mA
-  0.60    -29.949085mA      -28.768072mA         -31.336087mA
-  0.70    -33.609074mA      -32.702061mA         -34.612077mA
-  0.80    -36.868064mA      -36.383050mA         -37.284067mA
-  0.90    -39.717053mA      -39.806039mA         -39.346056mA
-  1.00    -42.147042mA      -42.970028mA         -40.889046mA
-  1.10    -44.149032mA      -45.870017mA         -42.089035mA
-  1.20    -45.748021mA      -48.504006mA         -43.060025mA
-  1.30    -47.028011mA      -50.866995mA         -43.869015mA
-  1.40    -48.080000mA      -52.957984mA         -44.561004mA
-  1.50    -48.964989mA      -54.770973mA         -45.164994mA
-  1.60    -49.722979mA      -56.304962mA         -45.700984mA
-  1.70    -50.383968mA      -57.595951mA         -46.184973mA
-  1.80    -50.967958mA      -58.692940mA         -46.625963mA
-  1.90    -51.489947mA      -59.638929mA         -47.033952mA
-  2.00    -51.962937mA      -60.463918mA         -47.412942mA
-  2.10    -52.394926mA      -61.192907mA         -47.768932mA
-  2.20    -52.791916mA      -61.842896mA         -48.104921mA
-  2.30    -53.159905mA      -62.426885mA         -48.424911mA
-  2.40    -53.504894mA      -62.956874mA         -48.730901mA
-  2.50    -53.827884mA      -63.439863mA         -49.025891mA
-  2.60    -54.132874mA      -63.884852mA         -49.310882mA
-  2.70    -54.422864mA      -64.295841mA         -49.587873mA
-  2.80    -54.700854mA      -64.676830mA         -49.859863mA
-  2.90    -54.966844mA      -65.033819mA         -50.128854mA
-  3.00    -55.224834mA      -65.367808mA         -50.397845mA
-  3.10    -55.477825mA      -65.682796mA         -50.669835mA
-  3.20    -55.727815mA      -65.980780mA         -50.947826mA
-  3.30    -55.978806mA      -66.265706mA         -51.235817mA
-  3.40    -56.233792mA      -66.536956mA         -51.539808mA
-  3.50    -56.497705mA      -66.792873mA         -51.862798mA
-  3.60    -56.774346mA      -66.928560mA         -52.210786mA
-  3.70    -57.054551mA      -67.195337mA         -52.589679mA
-  3.80    -57.194470mA      -67.462113mA         -53.001555mA
-  3.90    -57.422477mA      -67.728890mA         -53.392977mA
-  4.00    -57.650484mA      -67.995667mA         -53.537857mA
-  4.10    -57.878491mA      -68.262444mA         -53.750052mA
-  4.20    -58.106498mA      -68.529220mA         -53.962246mA
-  4.30    -58.334506mA      -68.795997mA         -54.174441mA
-  4.40    -58.562513mA      -69.062774mA         -54.386636mA
-  4.50    -58.790520mA      -69.329550mA         -54.598830mA
-  4.60    -59.018527mA      -69.596327mA         -54.811025mA
-  4.70    -59.246534mA      -69.863104mA         -55.023219mA
-  4.80    -59.474541mA      -70.129881mA         -55.235414mA
-  4.90    -59.702548mA      -70.396657mA         -55.447608mA
-  5.00    -59.930555mA      -70.663434mA         -55.659803mA
-  5.10    -60.158563mA      -70.930211mA         -55.871997mA
-  5.20    -60.386570mA      -71.196988mA         -56.084192mA
-  5.30    -60.614577mA      -71.463764mA         -56.296387mA
-  5.40    -60.842584mA      -71.730541mA         -56.508581mA
-  5.50    -61.070591mA      -71.997318mA         -56.720776mA
-  5.60    -61.298598mA      -72.264094mA         -56.932970mA
-  5.70    -61.526605mA      -72.530871mA         -57.145165mA
-  5.80    -61.754612mA      -72.797648mA         -57.357359mA
-  5.90    -61.982620mA      -73.064425mA         -57.569554mA
-  6.00    -62.210627mA      -73.331201mA         -57.781748mA
-  6.10    -62.438634mA      -73.597978mA         -57.993943mA
-  6.20    -62.666641mA      -73.864755mA         -58.206138mA
-  6.30    -62.894648mA      -74.131531mA         -58.418332mA
-  6.40    -63.122655mA      -74.398308mA         -58.630527mA
-  6.50    -63.350662mA      -74.665085mA         -58.842721mA
-  6.55    -63.464666mA      -74.798473mA         -58.948819mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.195000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.064900nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  1.322279/1.397370n  1.285979/1.830494n  1.312139/1.075717n
-dV/dt_f  0.909660/0.907875n  0.826020/1.758264n  1.011840/0.527820n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              1.726300V         1.546200V            1.899700V
-0.2020ns          1.726800V         1.546200V            1.904800V
-0.4040ns          1.737400V         1.550000V            2.017500V
-0.6061ns          1.942100V         1.551600V            2.912500V
-0.8081ns          2.634400V         1.596800V            3.407200V
-1.0101ns          3.187200V         1.875300V            3.460800V
-1.2121ns          3.279100V         2.359700V            3.465800V
-1.4141ns          3.292700V         2.847800V            3.467100V
-1.6162ns          3.295600V         3.089900V            3.467600V
-1.8182ns          3.296700V         3.123600V            3.467900V
-2.0202ns          3.297300V         3.130900V            3.468200V
-2.2222ns          3.297500V         3.134300V            3.468700V
-2.4242ns          3.297700V         3.135700V            3.468900V
-2.6263ns          3.297900V         3.136600V            3.470800V
-2.8283ns          3.298100V         3.137000V            3.470300V
-3.0303ns          3.298400V         3.137300V            3.470100V
-3.2323ns          3.299000V         3.137500V            3.470000V
-3.4343ns          3.300800V         3.137600V            3.470000V
-3.6364ns          3.300800V         3.137800V            3.470000V
-3.8384ns          3.300300V         3.137900V            3.469900V
-4.0404ns          3.300200V         3.138000V            3.469900V
-4.2424ns          3.300000V         3.138200V            3.469900V
-4.4444ns          3.300000V         3.138400V            3.469900V
-4.6465ns          3.300000V         3.138600V            3.469900V
-4.8485ns          3.300000V         3.138900V            3.469900V
-5.0505ns          3.300000V         3.139200V            3.469900V
-5.2525ns          3.300000V         3.140400V            3.469900V
-5.4545ns          3.299900V         3.140300V            3.469900V
-5.6566ns          3.299900V         3.140100V            3.469900V
-5.8586ns          3.299900V         3.140100V            3.470000V
-6.0606ns          3.299900V         3.140000V            3.470000V
-6.2626ns          3.299900V         3.140000V            3.470000V
-6.4646ns          3.299900V         3.140000V            3.470000V
-6.6667ns          3.299900V         3.140000V            3.470000V
-6.8687ns          3.299900V         3.140000V            3.470000V
-7.0707ns          3.299900V         3.140000V            3.470000V
-7.2727ns          3.299900V         3.140000V            3.470000V
-7.4747ns          3.299900V         3.140000V            3.470000V
-7.6768ns          3.299900V         3.140000V            3.470000V
-7.8788ns          3.300000V         3.140000V            3.470000V
-8.0808ns          3.300000V         3.140000V            3.470000V
-8.2828ns          3.300000V         3.140000V            3.470000V
-8.4848ns          3.300000V         3.140000V            3.470000V
-8.6869ns          3.300000V         3.139900V            3.470000V
-8.8889ns          3.300000V         3.139900V            3.470000V
-9.0909ns          3.300000V         3.139900V            3.470000V
-9.2929ns          3.300000V         3.139900V            3.470000V
-9.4949ns          3.300000V         3.139900V            3.470000V
-9.6970ns          3.300000V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.140000V            3.470000V
-11.7172ns         3.300000V         3.140000V            3.470000V
-11.9192ns         3.300000V         3.140000V            3.470000V
-12.1212ns         3.300000V         3.140000V            3.470000V
-12.3232ns         3.300000V         3.140000V            3.470000V
-12.5253ns         3.300000V         3.140000V            3.470000V
-12.7273ns         3.300000V         3.140000V            3.470000V
-12.9293ns         3.300000V         3.140000V            3.470000V
-13.1313ns         3.300000V         3.140000V            3.470000V
-13.3333ns         3.300000V         3.140000V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              1.860000uV        2.247100uV           1.679700uV
-0.2020ns          -0.129790mV       4.669400uV           -0.320790mV
-0.4040ns          -1.716600mV       0.272540uV           -4.681500mV
-0.6061ns          1.221000mV        -0.447820mV          0.186680V
-0.8081ns          0.107030V         -5.196400mV          0.507800V
-1.0101ns          0.361420V         7.872900mV           0.782610V
-1.2121ns          0.574160V         63.086000mV          1.032400V
-1.4141ns          0.778920V         0.229510V            1.269500V
-1.6162ns          0.975680V         0.410340V            1.497800V
-1.8182ns          1.166800V         0.562960V            1.717900V
-2.0202ns          1.353800V         0.714380V            1.916400V
-2.2222ns          1.533600V         0.865340V            2.085800V
-2.4242ns          1.705400V         1.012700V            2.201900V
-2.6263ns          1.865600V         1.157800V            2.206500V
-2.8283ns          2.002800V         1.297100V            2.148000V
-3.0303ns          2.119800V         1.433900V            2.116300V
-3.2323ns          2.194200V         1.564200V            2.100900V
-3.4343ns          2.242600V         1.684200V            2.095200V
-3.6364ns          2.206600V         1.795900V            2.092100V
-3.8384ns          2.175600V         1.885300V            2.093400V
-4.0404ns          2.158100V         1.961700V            2.097900V
-4.2424ns          2.149800V         2.017100V            2.104000V
-4.4444ns          2.145000V         2.058100V            2.111400V
-4.6465ns          2.142500V         2.090000V            2.119600V
-4.8485ns          2.141700V         2.113000V            2.127800V
-5.0505ns          2.141900V         2.137500V            2.135200V
-5.2525ns          2.142800V         2.134100V            2.141000V
-5.4545ns          2.144700V         2.126700V            2.146000V
-5.6566ns          2.148900V         2.121500V            2.150700V
-5.8586ns          2.153600V         2.118100V            2.154700V
-6.0606ns          2.158200V         2.116400V            2.158400V
-6.2626ns          2.162900V         2.115100V            2.161600V
-6.4646ns          2.167200V         2.114600V            2.164500V
-6.6667ns          2.171000V         2.114400V            2.167000V
-6.8687ns          2.174500V         2.114500V            2.169300V
-7.0707ns          2.177500V         2.114600V            2.171300V
-7.2727ns          2.180300V         2.114800V            2.173100V
-7.4747ns          2.182800V         2.115200V            2.174700V
-7.6768ns          2.185100V         2.115600V            2.176100V
-7.8788ns          2.187100V         2.116000V            2.177400V
-8.0808ns          2.188900V         2.116500V            2.178500V
-8.2828ns          2.190500V         2.117100V            2.179500V
-8.4848ns          2.191900V         2.117700V            2.180300V
-8.6869ns          2.193200V         2.118500V            2.181100V
-8.8889ns          2.194300V         2.119600V            2.181800V
-9.0909ns          2.195300V         2.121000V            2.182400V
-9.2929ns          2.196300V         2.122600V            2.182900V
-9.4949ns          2.197100V         2.124200V            2.183400V
-9.6970ns          2.197800V         2.125900V            2.183800V
-9.8990ns          2.198500V         2.127400V            2.184200V
-10.1010ns         2.199350V         2.129450V            2.184650V
-10.3030ns         2.200000V         2.131300V            2.185000V
-10.5051ns         2.200500V         2.132300V            2.185200V
-10.7071ns         2.200800V         2.133300V            2.185400V
-10.9091ns         2.201200V         2.134200V            2.185600V
-11.1111ns         2.201500V         2.135100V            2.185800V
-11.3131ns         2.201700V         2.135800V            2.185900V
-11.5152ns         2.202000V         2.136500V            2.186000V
-11.7172ns         2.202200V         2.137100V            2.186100V
-11.9192ns         2.202400V         2.137700V            2.186200V
-12.1212ns         2.202500V         2.138200V            2.186300V
-12.3232ns         2.202700V         2.138700V            2.186400V
-12.5253ns         2.202800V         2.139100V            2.186400V
-12.7273ns         2.202900V         2.139500V            2.186500V
-12.9293ns         2.203000V         2.139900V            2.186500V
-13.1313ns         2.203100V         2.140200V            2.186600V
-13.3333ns         2.203200V         2.140500V            2.186600V
-13.5354ns         2.203300V         2.140700V            2.186600V
-13.7374ns         2.203300V         2.141000V            2.186700V
-13.9394ns         2.203400V         2.141200V            2.186700V
-14.1414ns         2.203400V         2.141400V            2.186700V
-14.3434ns         2.203500V         2.141600V            2.186700V
-14.5455ns         2.203500V         2.141800V            2.186700V
-14.7475ns         2.203600V         2.141900V            2.186800V
-14.9495ns         2.203600V         2.142000V            2.186800V
-15.1515ns         2.203600V         2.142200V            2.186800V
-15.3535ns         2.203600V         2.142300V            2.186800V
-15.5556ns         2.203700V         2.142400V            2.186800V
-15.7576ns         2.203700V         2.142500V            2.186800V
-15.9596ns         2.203700V         2.142600V            2.186800V
-16.1616ns         2.203700V         2.142600V            2.186800V
-16.3636ns         2.203700V         2.142700V            2.186800V
-16.5657ns         2.203700V         2.142800V            2.186900V
-16.7677ns         2.203700V         2.142800V            2.186900V
-16.9697ns         2.203800V         2.142900V            2.186900V
-17.1717ns         2.203800V         2.142900V            2.186900V
-17.3737ns         2.203800V         2.143000V            2.186900V
-17.5758ns         2.203800V         2.143000V            2.186900V
-17.7778ns         2.203800V         2.143000V            2.186900V
-17.9798ns         2.203800V         2.143100V            2.186900V
-18.1818ns         2.203800V         2.143100V            2.186900V
-18.3838ns         2.203800V         2.143100V            2.186900V
-18.5859ns         2.203800V         2.143100V            2.186900V
-18.7879ns         2.203800V         2.143200V            2.186900V
-18.9899ns         2.203800V         2.143200V            2.186900V
-19.1919ns         2.203800V         2.143200V            2.186900V
-19.3939ns         2.203800V         2.143200V            2.186900V
-19.5960ns         2.203800V         2.143200V            2.186900V
-19.7980ns         2.203800V         2.143200V            2.186900V
-20.0000ns         2.203800V         2.143300V            2.186900V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.203900V         2.143400V            2.187000V
-0.2020ns          2.204000V         2.143400V            2.193500V
-0.4040ns          2.222800V         2.147700V            2.032600V
-0.6061ns          2.041300V         2.152800V            1.329800V
-0.8081ns          1.561500V         2.146100V            0.689440V
-1.0101ns          1.011100V         2.097000V            0.210050V
-1.2121ns          0.595520V         1.931200V            16.668000mV
-1.4141ns          0.291310V         1.573700V            3.287100mV
-1.6162ns          80.606000mV       1.160800V            1.540100mV
-1.8182ns          13.976000mV       0.816650V            0.795800mV
-2.0202ns          3.438200mV        0.556260V            0.249100mV
-2.2222ns          2.674800mV        0.354310V            0.141130mV
-2.4242ns          1.686600mV        0.200190V            -0.655480mV
-2.6263ns          0.612530mV        87.872000mV          -2.068600uV
-2.8283ns          0.572400mV        33.061000mV          -22.091000uV
-3.0303ns          0.375060mV        11.834000mV          -24.867000uV
-3.2323ns          0.241800mV        4.814600mV           -26.956000uV
-3.4343ns          -0.105830mV       3.354200mV           -15.925000uV
-3.6364ns          -75.323000uV      2.452700mV           -21.116000uV
-3.8384ns          4.162200uV        1.747000mV           -21.198000uV
-4.0404ns          -9.814400uV       1.397500mV           -20.735000uV
-4.2424ns          -8.341900uV       1.108100mV           -20.330000uV
-4.4444ns          -6.866100uV       0.872660mV           -19.920000uV
-4.6465ns          -5.387100uV       0.692450mV           -19.527000uV
-4.8485ns          -8.072400uV       0.289700mV           -19.137000uV
-5.0505ns          -7.958300uV       0.244360mV           -18.776000uV
-5.2525ns          -7.769600uV       -77.493000uV         -18.423000uV
-5.4545ns          -7.625700uV       -0.105340mV          -18.079000uV
-5.6566ns          -7.474800uV       -54.805000uV         -17.737000uV
-5.8586ns          -7.290100uV       10.015000uV          -17.420000uV
-6.0606ns          -7.095100uV       31.098000uV          -17.110000uV
-6.2626ns          -6.941900uV       27.849000uV          -16.798000uV
-6.4646ns          -6.801300uV       26.843000uV          -16.485000uV
-6.6667ns          -6.644700uV       25.837000uV          -16.193000uV
-6.8687ns          -6.483200uV       24.821000uV          -15.906000uV
-7.0707ns          -6.356800uV       23.930000uV          -15.617000uV
-7.2727ns          -6.241000uV       23.931000uV          -15.328000uV
-7.4747ns          -6.109700uV       23.867000uV          -15.057000uV
-7.6768ns          -5.973800uV       23.333000uV          -14.790000uV
-7.8788ns          -5.859500uV       22.861000uV          -14.523000uV
-8.0808ns          -5.751700uV       22.831000uV          -14.256000uV
-8.2828ns          -5.632300uV       22.765000uV          -14.004000uV
-8.4848ns          -5.509400uV       22.433000uV          -13.756000uV
-8.6869ns          -5.401200uV       22.127000uV          -13.508000uV
-8.8889ns          -5.297500uV       22.000000uV          -13.261000uV
-9.0909ns          -5.186800uV       21.856000uV          -13.026000uV
-9.2929ns          -5.073900uV       21.583000uV          -12.795000uV
-9.4949ns          -4.971400uV       21.321000uV          -12.566000uV
-9.6970ns          -4.872100uV       21.138000uV          -12.337000uV
-9.8990ns          -4.768700uV       20.948000uV          -12.119000uV
-10.1010ns         -4.615700uV       20.580000uV          -11.796500uV
-10.3030ns         -4.472500uV       20.255000uV          -11.478000uV
-10.5051ns         -4.375700uV       20.048000uV          -11.275000uV
-10.7071ns         -4.278400uV       19.819000uV          -11.074000uV
-10.9091ns         -4.186900uV       19.593000uV          -10.876000uV
-11.1111ns         -4.097100uV       19.385000uV          -10.679000uV
-11.3131ns         -4.006500uV       19.177000uV          -10.490000uV
-11.5152ns         -3.915700uV       18.963000uV          -10.303000uV
-11.7172ns         -3.829500uV       18.751000uV          -10.119000uV
-11.9192ns         -3.744700uV       18.550000uV          -9.935200uV
-12.1212ns         -3.659800uV       18.348000uV          -9.758900uV
-12.3232ns         -3.575000uV       18.147000uV          -9.584400uV
-12.5253ns         -3.493900uV       17.946000uV          -9.412900uV
-12.7273ns         -3.413900uV       17.750000uV          -9.242200uV
-12.9293ns         -3.334400uV       17.555000uV          -9.077700uV
-13.1313ns         -3.255000uV       17.367000uV          -8.914800uV
-13.3333ns         -3.178700uV       17.180000uV          -8.754900uV
-13.5354ns         -3.103400uV       16.992000uV          -8.595700uV
-13.7374ns         -3.028800uV       16.805000uV          -8.442200uV
-13.9394ns         -2.954500uV       16.625000uV          -8.290100uV
-14.1414ns         -2.882800uV       16.446000uV          -8.140800uV
-14.3434ns         -2.811900uV       16.271000uV          -7.992300uV
-14.5455ns         -2.741900uV       16.096000uV          -7.848800uV
-14.7475ns         -2.672100uV       15.921000uV          -7.706700uV
-14.9495ns         -2.604700uV       15.747000uV          -7.567200uV
-15.1515ns         -2.538000uV       15.582000uV          -7.428400uV
-15.3535ns         -2.472300uV       15.417000uV          -7.294300uV
-15.5556ns         -2.406900uV       15.254000uV          -7.161400uV
-15.7576ns         -2.343500uV       15.091000uV          -7.031000uV
-15.9596ns         -2.280700uV       14.928000uV          -6.901100uV
-16.1616ns         -2.219000uV       14.767000uV          -6.775700uV
-16.3636ns         -2.157500uV       14.614000uV          -6.651300uV
-16.5657ns         -2.097900uV       14.461000uV          -6.529200uV
-16.7677ns         -2.038900uV       14.310000uV          -6.407700uV
-16.9697ns         -1.980900uV       14.158000uV          -6.290200uV
-17.1717ns         -1.923100uV       14.007000uV          -6.173700uV
-17.3737ns         -1.867100uV       13.856000uV          -6.059300uV
-17.5758ns         -1.811500uV       13.715000uV          -5.945500uV
-17.7778ns         -1.756900uV       13.574000uV          -5.835400uV
-17.9798ns         -1.702700uV       13.433000uV          -5.726200uV
-18.1818ns         -1.649900uV       13.292000uV          -5.619000uV
-18.3838ns         -1.597600uV       13.151000uV          -5.512200uV
-18.5859ns         -1.546300uV       13.011000uV          -5.409000uV
-18.7879ns         -1.495300uV       12.881000uV          -5.306700uV
-18.9899ns         -1.445600uV       12.750000uV          -5.206100uV
-19.1919ns         -1.396400uV       12.619000uV          -5.105900uV
-19.3939ns         -1.348100uV       12.488000uV          -5.009100uV
-19.5960ns         -1.300200uV       12.357000uV          -4.913100uV
-19.7980ns         -1.253400uV       12.227000uV          -4.818400uV
-20.0000ns         -1.206900uV       12.109000uV          -4.724200uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468500V
-0.4040ns          3.300800V         3.139500V            3.480800V
-0.6061ns          3.307700V         3.140100V            3.421400V
-0.8081ns          3.288700V         3.143500V            3.119600V
-1.0101ns          3.205000V         3.143800V            2.661400V
-1.2121ns          3.025100V         3.145800V            2.287000V
-1.4141ns          2.763000V         3.126600V            2.008100V
-1.6162ns          2.525800V         3.091800V            1.804300V
-1.8182ns          2.335100V         3.031500V            1.669500V
-2.0202ns          2.176400V         2.950000V            1.556300V
-2.2222ns          2.038500V         2.833800V            1.492000V
-2.4242ns          1.931900V         2.695300V            1.454000V
-2.6263ns          1.842100V         2.569900V            1.511700V
-2.8283ns          1.775200V         2.465400V            1.518000V
-3.0303ns          1.725800V         2.375800V            1.523200V
-3.2323ns          1.686600V         2.288200V            1.528200V
-3.4343ns          1.685200V         2.209700V            1.533400V
-3.6364ns          1.704000V         2.138800V            1.538300V
-3.8384ns          1.711300V         2.070500V            1.543000V
-4.0404ns          1.712500V         2.009900V            1.547600V
-4.2424ns          1.714100V         1.956200V            1.552200V
-4.4444ns          1.715500V         1.910000V            1.556700V
-4.6465ns          1.717000V         1.869400V            1.561200V
-4.8485ns          1.718600V         1.839700V            1.565600V
-5.0505ns          1.719900V         1.823800V            1.569900V
-5.2525ns          1.721200V         1.826000V            1.574200V
-5.4545ns          1.722500V         1.835200V            1.578400V
-5.6566ns          1.723800V         1.841500V            1.582600V
-5.8586ns          1.725000V         1.842800V            1.586700V
-6.0606ns          1.726200V         1.841300V            1.590800V
-6.2626ns          1.727400V         1.839800V            1.594800V
-6.4646ns          1.728600V         1.838400V            1.598800V
-6.6667ns          1.729800V         1.837000V            1.602700V
-6.8687ns          1.730900V         1.835500V            1.606600V
-7.0707ns          1.732000V         1.834000V            1.610400V
-7.2727ns          1.733200V         1.832700V            1.614200V
-7.4747ns          1.734300V         1.831300V            1.618000V
-7.6768ns          1.735400V         1.829900V            1.621600V
-7.8788ns          1.736400V         1.828500V            1.625300V
-8.0808ns          1.737500V         1.827100V            1.628900V
-8.2828ns          1.738600V         1.825800V            1.632500V
-8.4848ns          1.739600V         1.824400V            1.636000V
-8.6869ns          1.740600V         1.823100V            1.639400V
-8.8889ns          1.741700V         1.821800V            1.642900V
-9.0909ns          1.742700V         1.820400V            1.646300V
-9.2929ns          1.743700V         1.819100V            1.649600V
-9.4949ns          1.744700V         1.817800V            1.652900V
-9.6970ns          1.745600V         1.816500V            1.656200V
-9.8990ns          1.746600V         1.815200V            1.659400V
-10.1010ns         1.748050V         1.813350V            1.664200V
-10.3030ns         1.749400V         1.811400V            1.668900V
-10.5051ns         1.750400V         1.810200V            1.672000V
-10.7071ns         1.751300V         1.809000V            1.675000V
-10.9091ns         1.752200V         1.807800V            1.678000V
-11.1111ns         1.753100V         1.806500V            1.681000V
-11.3131ns         1.753900V         1.805400V            1.684000V
-11.5152ns         1.754800V         1.804200V            1.686900V
-11.7172ns         1.755700V         1.803000V            1.689700V
-11.9192ns         1.756500V         1.801800V            1.692600V
-12.1212ns         1.757400V         1.800700V            1.695400V
-12.3232ns         1.758200V         1.799500V            1.698200V
-12.5253ns         1.759000V         1.798400V            1.700900V
-12.7273ns         1.759800V         1.797300V            1.703600V
-12.9293ns         1.760600V         1.796200V            1.706300V
-13.1313ns         1.761400V         1.795100V            1.709000V
-13.3333ns         1.762200V         1.794000V            1.711600V
-13.5354ns         1.763000V         1.792900V            1.714200V
-13.7374ns         1.763800V         1.791800V            1.716700V
-13.9394ns         1.764500V         1.790800V            1.719300V
-14.1414ns         1.765300V         1.789700V            1.721800V
-14.3434ns         1.766000V         1.788700V            1.724200V
-14.5455ns         1.766800V         1.787700V            1.726700V
-14.7475ns         1.767500V         1.786600V            1.729100V
-14.9495ns         1.768200V         1.785600V            1.731500V
-15.1515ns         1.768900V         1.784600V            1.733900V
-15.3535ns         1.769600V         1.783600V            1.736200V
-15.5556ns         1.770300V         1.782700V            1.738500V
-15.7576ns         1.771000V         1.781700V            1.740800V
-15.9596ns         1.771700V         1.780700V            1.743100V
-16.1616ns         1.772400V         1.779800V            1.745300V
-16.3636ns         1.773000V         1.778800V            1.747500V
-16.5657ns         1.773700V         1.777900V            1.749700V
-16.7677ns         1.774300V         1.777000V            1.751900V
-16.9697ns         1.775000V         1.776000V            1.754000V
-17.1717ns         1.775600V         1.775100V            1.756200V
-17.3737ns         1.776300V         1.774200V            1.758300V
-17.5758ns         1.776900V         1.773300V            1.760300V
-17.7778ns         1.777500V         1.772400V            1.762400V
-17.9798ns         1.778100V         1.771600V            1.764400V
-18.1818ns         1.778700V         1.770700V            1.766400V
-18.3838ns         1.779300V         1.769800V            1.768400V
-18.5859ns         1.779900V         1.769000V            1.770400V
-18.7879ns         1.780500V         1.768100V            1.772300V
-18.9899ns         1.781100V         1.767300V            1.774200V
-19.1919ns         1.781600V         1.766500V            1.776200V
-19.3939ns         1.782200V         1.765700V            1.778000V
-19.5960ns         1.782800V         1.764900V            1.779900V
-19.7980ns         1.783300V         1.764000V            1.781700V
-|20.0000ns         1.783900V         1.763300V            1.783600V
-40.0000ns         1.783900V         1.550000V            1.783600V
-|  
-| End [Model] lvc330s140aaaaaaaaio
-|************************************************************************
-| End [Component]
-[End]
+|************************************************************************
+| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
+| Generate date: Sun Aug 20 05:55:52 2023
+|************************************************************************
+| IBIS File machxo.ibs
+| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
+| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
+| North Carolina State University, ERL, 2006
+|************************************************************************
+[IBIS ver]       3.2
+[File Name]     RAM2GS_LCMXO640C_im~.ibs
+[File Rev]       2.2
+[Date]           Mon Sep 28 10:44:10 EDT 2009
+[Source]         Lattice Semiconductor EE12 Process
+[Notes]          "Preliminary Version"
+                 Lattice Semiconductor has worked hard to ensure the
+                 models below are accurate and complete.  However, the
+                 data below was generated using simulation of the
+                 input/output model files for the silicon.  Therefore,
+                 the data below is for reference and initial design
+                 purposes only.
+|
+                 The data below is correlated to Spice models.  
+                 For questions regarding this data please contact
+                 us at www.latticesemi.com.
+|
+                 Lattice Semiconductor grants permission to use this
+                 data for use in printed circuit design using this
+                 Lattice programmable logic device.  Other use of this
+                 code, including the selling or duplication of any
+                 portion is strictly prohibited.
+|
+|                NAMING CONVENTION
+|
+        The IBIS [Model] header is limited by the specification to a
+        total of characters.  With such a set of characters available
+        for naming models it becomes important to attempt to
+        meaningfully encode the IO standards so they fit within the
+        twenty character limit.  It would seem that twenty characters
+        would provide room enough for describing IO's.  However, the
+        PLD IO structure continues to grow more and more complex.  The
+        complexity is making the twenty characters insuffiently
+        descriptive.  In order to overcome this issue the naming
+        convention described below is implemented to resolve the issue.
+|
+The twenty character space is managed as follows:
+                 bbbvvvsdddprugtcoixx
+|
+                 b = standard
+                 v = voltage (x.xx V)
+                 s = slew code
+                 d = drive (xx.x ma)
+                 p = pullup code
+                 r = series resistance code
+                 u = terminate to vcc code
+                 g = terminate to gnd code
+                 t = terminate to vtt code
+                 c = common mode termination mode
+                 o = diff resistor code
+                 i = diff resistor current code
+                 x = reserved
+|
+|
+                 standard
+|
+                 LVCMOS                   lvc
+                 lvcmosd                  lvd
+                 LVDSE                    lve
+                 LVTTL                    lvt
+                 lvttld                   ltd
+                 PCI                      pci
+                 pcix                     pcx
+                 AGP1x                    ag1
+                 agp2x                    ag2
+                 sstl_I                   ss1
+                 sstl_II                  ss2
+                 sstld_I                  s1d
+                 sstld_II                 s2d
+                 CTT                      ctt
+                 hstl_i                   hs1
+                 hstl_ii                  hs2
+                 hstl_iii                 hs3
+                 hstl_iv                  hs4
+                 hstld_i                  h1d
+                 hstld_ii                 h2d
+                 gtl                      gtl
+                 gtlplus                  gtp
+                 lvds                     lvs
+                 blvds                    blv
+                 mlvds                    mlv
+                 lvpecl                   lvp
+                 cml                      cml
+                 hypt                     hyp
+                 rsds                     rsd
+                 vref1                    vr1
+                 vref2                    vr2
+                 ref_res                  rer
+|
+|
+                 slew
+                 na                       a
+                 fast                     f
+                 slow                     s
+|
+                 pullmode
+                 off                      a
+                 pullup                   b
+                 pulldown                 c
+                 bushold                  d
+                 pciclamp                 e
+                 up_pciclamp              f
+                 down_pciclamp            g
+                 keeper_pciclamp          h
+                 schmitt                  i
+                 up_schmitt               j
+                 down_schmitt             k
+                 keeper_schmitt           l
+                 up_pciclamp_schmitt      m
+                 down_pciclamp_schmitt    n
+                 keeper_pciclamp_schmitt  o
+                 pciclamp_schmitt         p
+|
+                 impedence
+                 off                      a
+                 25                       b
+                 33                       c
+                 50                       d
+                 100                      e
+|
+                 termVCC
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termGND
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termVTT
+                 off                      a
+                 60                       b
+                 75                       c
+                 120                      d
+                 150                      e
+                 210                      f
+|
+                 VCMT
+                 off                      a
+                 VCMT                     b
+                 VTT                      c
+                 DDR-2                    d
+|
+                 differential resistor
+                 off                      a
+                 120                      b
+                 150                      c
+                 220                      d
+                 420                      e
+|
+                 differential current
+                 NA                       a
+                 2                        b
+                 3.5                      c
+                 4                        d
+                 6                        e
+|
+                 Reserved                 IO type
+                 in                       input only
+                 ou                       output
+                 io                       I/O
+                 od                       Open drain
+                 on                       Inverting differential I/O
+                                          (signal name only)
+                 op                       Non-Inverting differential I/O
+                                          (signal name only)
+|
+   All the IO models are generated with pull mode set to UP.
+|
+                 Lattice Semiconductor Corporation
+                 5555 NE Moore Court
+                 Hillsboro, OR 97214
+                 U.S.A
+|
+                 TEL: 1-800-Lattice (USA and Canada)
+                      408-826-6000 (other locations)
+|
+                 web: http://www.latticesemi.com/
+                 email: techsupport@latticesemi.com
+|
+|
+|
+[Disclaimer]     This IBIS source code is intended as a design reference
+   which illustrates how the Lattice Semiconductor device operates.
+   It is the user's responsibility to verify their design for
+   consistency and functionality through the use of formal
+   verification methods.  Lattice Semiconductor provides no warranty
+   regarding the use or functionality of this data.
+|
+[Copyright]      Copyright 2009 by Lattice Semiconductor Corporation
+|
+|  
+|************************************************************************
+|                       Component XO
+|************************************************************************
+|  
+[Component]     MXO256_MXO640_MXO1K_MXO2K
+[Manufacturer]    Lattice Semiconductor Corp.
+[Package]
+|TQFP100
+| variable            typ              min              max
+R_pkg                 70.5m            54.0m            87.0m
+L_pkg                 4.57nH           4.27nH           4.87nH
+C_pkg                 .52pF            .47pF            .57pF
+|
+[Pin] signal_name           model_name           R_pin     L_pin     C_pin
+32            CROW[0]              lvc330fxxxaaaaaaaain
+34            CROW[1]              lvc330fxxxaaaaaaaain
+21            Din[0]               lvc330fxxxaaaaaaaain
+15            Din[1]               lvc330fxxxaaaaaaaain
+14            Din[2]               lvc330fxxxaaaaaaaain
+16            Din[3]               lvc330fxxxaaaaaaaain
+18            Din[4]               lvc330fxxxaaaaaaaain
+17            Din[5]               lvc330fxxxaaaaaaaain
+20            Din[6]               lvc330fxxxaaaaaaaain
+19            Din[7]               lvc330fxxxaaaaaaaain
+1             Dout[0]              lvc330f040aaaaaaaaio
+7             Dout[1]              lvc330f040aaaaaaaaio
+8             Dout[2]              lvc330f040aaaaaaaaio
+6             Dout[3]              lvc330f040aaaaaaaaio
+4             Dout[4]              lvc330f040aaaaaaaaio
+5             Dout[5]              lvc330f040aaaaaaaaio
+2             Dout[6]              lvc330f040aaaaaaaaio
+3             Dout[7]              lvc330f040aaaaaaaaio
+57            LED                  lvc330s140aaaaaaaaio
+23            MAin[0]              lvc330fxxxaaaaaaaain
+38            MAin[1]              lvc330fxxxaaaaaaaain
+37            MAin[2]              lvc330fxxxaaaaaaaain
+47            MAin[3]              lvc330fxxxaaaaaaaain
+46            MAin[4]              lvc330fxxxaaaaaaaain
+45            MAin[5]              lvc330fxxxaaaaaaaain
+49            MAin[6]              lvc330fxxxaaaaaaaain
+44            MAin[7]              lvc330fxxxaaaaaaaain
+50            MAin[8]              lvc330fxxxaaaaaaaain
+51            MAin[9]              lvc330fxxxaaaaaaaain
+39            PHI2                 lvc330fxxxcaaaaaaain
+98            RA[0]                lvc330s040aaaaaaaaio
+87            RA[10]               lvc330s040aaaaaaaaio
+79            RA[11]               lvc330s040aaaaaaaaio
+89            RA[1]                lvc330s040aaaaaaaaio
+94            RA[2]                lvc330s040aaaaaaaaio
+97            RA[3]                lvc330s040aaaaaaaaio
+99            RA[4]                lvc330s040aaaaaaaaio
+95            RA[5]                lvc330s040aaaaaaaaio
+91            RA[6]                lvc330s040aaaaaaaaio
+100           RA[7]                lvc330s040aaaaaaaaio
+96            RA[8]                lvc330s040aaaaaaaaio
+85            RA[9]                lvc330s040aaaaaaaaio
+63            RBA[0]               lvc330s040aaaaaaaaio
+83            RBA[1]               lvc330s040aaaaaaaaio
+82            RCKE                 lvc330s040aaaaaaaaio
+86            RCLK                 lvc330fxxxaaaaaaaain
+76            RDQMH                lvc330s040aaaaaaaaio
+61            RDQML                lvc330s040aaaaaaaaio
+64            RD[0]                lvc330s040aaaaaaaaio
+65            RD[1]                lvc330s040aaaaaaaaio
+66            RD[2]                lvc330s040aaaaaaaaio
+67            RD[3]                lvc330s040aaaaaaaaio
+68            RD[4]                lvc330s040aaaaaaaaio
+69            RD[5]                lvc330s040aaaaaaaaio
+70            RD[6]                lvc330s040aaaaaaaaio
+71            RD[7]                lvc330s040aaaaaaaaio
+58            UFMCLK               lvc330s040aaaaaaaaio
+56            UFMSDI               lvc330s040aaaaaaaaio
+55            UFMSDO               lvc330fxxxaaaaaaaain
+27            nCCAS                lvc330fxxxbaaaaaaain
+43            nCRAS                lvc330fxxxbaaaaaaain
+22            nFWE                 lvc330fxxxaaaaaaaain
+78            nRCAS                lvc330s040aaaaaaaaio
+77            nRCS                 lvc330s040aaaaaaaaio
+73            nRRAS                lvc330s040aaaaaaaaio
+72            nRWE                 lvc330s040aaaaaaaaio
+53            nUFMCS               lvc330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330f040aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
+  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
+  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
+  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
+  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
+  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
+  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
+  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
+  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
+  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
+  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
+  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
+  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
+  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
+  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
+  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
+  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
+  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
+  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
+  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
+  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
+  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
+  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
+  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
+  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
+  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
+  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
+  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
+  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
+  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
+  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
+  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
+  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
+  0.00    9.270000nA        8.640000nA           10.950000nA
+  0.10    2.215985mA        1.960397mA           2.507890mA
+  0.20    4.086375mA        3.683686mA           4.498680mA
+  0.30    5.594166mA        5.150675mA           5.952471mA
+  0.40    6.738256mA        6.352364mA           6.929962mA
+  0.50    7.557146mA        7.289853mA           7.572152mA
+  0.60    8.124436mA        7.983242mA           8.013343mA
+  0.70    8.511126mA        8.476831mA           8.337834mA
+  0.80    8.778316mA        8.826620mA           8.591424mA
+  0.90    8.972606mA        9.080609mA           8.798515mA
+  1.00    9.121395mA        9.272098mA           8.969206mA
+  1.10    9.240584mA        9.422087mA           9.101296mA
+  1.20    9.339574mA        9.543476mA           9.202186mA
+  1.30    9.424063mA        9.644765mA           9.285275mA
+  1.40    9.498053mA        9.731354mA           9.357665mA
+  1.50    9.564242mA        9.806743mA           9.423455mA
+  1.60    9.625232mA        9.873832mA           9.485944mA
+  1.70    9.684621mA        9.934821mA           9.548134mA
+  1.80    9.747011mA        9.992810mA           9.610224mA
+  1.90    9.814800mA        10.052999mA          9.670813mA
+  2.00    9.885689mA        10.122988mA          9.728603mA
+  2.10    9.955379mA        10.203977mA          9.783293mA
+  2.20    10.021968mA       10.292966mA          9.835282mA
+  2.30    10.083958mA       10.380954mA          9.884972mA
+  2.40    10.141947mA       10.464943mA          9.932861mA
+  2.50    10.196936mA       10.542932mA          9.979551mA
+  2.60    10.249926mA       10.614921mA          10.025941mA
+  2.70    10.300915mA       10.681910mA          10.071930mA
+  2.80    10.350904mA       10.744899mA          10.118920mA
+  2.90    10.400894mA       10.805888mA          10.167909mA
+  3.00    10.451883mA       10.863877mA          10.218899mA
+  3.10    10.504872mA       10.921864mA          10.273889mA
+  3.20    10.559862mA       10.978747mA          10.332878mA
+  3.30    10.618848mA       11.037379mA          10.397868mA
+  3.40    10.682725mA       11.085335mA          10.469857mA
+  3.50    10.751986mA       11.124616mA          10.550843mA
+  3.60    10.804292mA       11.163898mA          10.640599mA
+  3.70    10.840604mA       11.203179mA          10.738212mA
+  3.80    10.876916mA       11.242461mA          10.773505mA
+  3.90    10.913228mA       11.281743mA          10.808797mA
+  4.00    10.949540mA       11.321024mA          10.844090mA
+  4.10    10.985852mA       11.360306mA          10.879382mA
+  4.20    11.022164mA       11.399587mA          10.914675mA
+  4.30    11.058476mA       11.438869mA          10.949967mA
+  4.40    11.094788mA       11.478151mA          10.985259mA
+  4.50    11.131100mA       11.517432mA          11.020552mA
+  4.60    11.167412mA       11.556714mA          11.055844mA
+  4.70    11.203724mA       11.595995mA          11.091137mA
+  4.80    11.240036mA       11.635277mA          11.126429mA
+  4.90    11.276348mA       11.674559mA          11.161721mA
+  5.00    11.312660mA       11.713840mA          11.197014mA
+  5.10    11.348972mA       11.753122mA          11.232306mA
+  5.20    11.385284mA       11.792403mA          11.267599mA
+  5.30    11.421596mA       11.831685mA          11.302891mA
+  5.40    11.457908mA       11.870967mA          11.338183mA
+  5.50    11.494220mA       11.910248mA          11.373476mA
+  5.60    11.530532mA       11.949530mA          11.408768mA
+  5.70    11.566844mA       11.988811mA          11.444061mA
+  5.80    11.603156mA       12.028093mA          11.479353mA
+  5.90    11.639468mA       12.067375mA          11.514645mA
+  6.00    11.675780mA       12.106656mA          11.549938mA
+  6.10    11.712092mA       12.145938mA          11.585230mA
+  6.20    11.748404mA       12.185219mA          11.620523mA
+  6.30    11.784716mA       12.224501mA          11.655815mA
+  6.40    11.821028mA       12.263783mA          11.691107mA
+  6.50    11.857340mA       12.303064mA          11.726400mA
+  6.60    11.893652mA       12.342346mA          11.761692mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    6.260163mA        5.384933mA           7.315403mA
+  -3.20    6.239699mA        5.366401mA           7.291487mA
+  -3.10    6.219236mA        5.347870mA           7.267570mA
+  -3.00    6.198773mA        5.329339mA           7.243653mA
+  -2.90    6.178310mA        5.310808mA           7.219736mA
+  -2.80    6.157847mA        5.292277mA           7.195819mA
+  -2.70    6.137383mA        5.273745mA           7.171903mA
+  -2.60    6.116920mA        5.255214mA           7.147986mA
+  -2.50    6.096457mA        5.236683mA           7.124069mA
+  -2.40    6.075994mA        5.218152mA           7.100152mA
+  -2.30    6.055531mA        5.199621mA           7.076235mA
+  -2.20    6.035067mA        5.181089mA           7.052319mA
+  -2.10    6.014604mA        5.162558mA           7.028402mA
+  -2.00    5.994141mA        5.144027mA           7.004485mA
+  -1.90    5.973678mA        5.125496mA           6.980568mA
+  -1.80    5.953215mA        5.106965mA           6.956651mA
+  -1.70    5.932751mA        5.088433mA           6.932735mA
+  -1.60    5.912288mA        5.069902mA           6.908818mA
+  -1.50    5.891825mA        5.051371mA           6.884901mA
+  -1.40    5.871362mA        5.032840mA           6.860984mA
+  -1.30    5.850899mA        5.014309mA           6.837067mA
+  -1.20    5.830435mA        4.995777mA           6.813151mA
+  -1.10    5.809972mA        4.977246mA           6.789234mA
+  -1.00    5.789509mA        4.958715mA           6.765317mA
+  -0.90    5.769046mA        4.940184mA           6.741400mA
+  -0.80    5.748583mA        4.921653mA           6.717483mA
+  -0.70    5.728119mA        4.903121mA           6.693567mA
+  -0.60    5.707656mA        4.884590mA           6.669650mA
+  -0.50    5.687193mA        4.866059mA           6.645733mA
+  -0.40    5.666730mA        4.847528mA           6.621816mA
+  -0.30    5.646267mA        4.828997mA           6.597899mA
+  -0.20    4.435786mA        3.802115mA           5.174820mA
+  -0.10    2.131925mA        1.838548mA           2.475669mA
+  0.00    -6.170000nA       -5.460000nA          -7.060000nA
+  0.10    -1.893038mA       -1.673728mA          -2.145840mA
+  0.20    -3.512428mA       -3.164516mA          -3.900829mA
+  0.30    -4.854717mA       -4.471005mA          -5.257719mA
+  0.40    -5.916606mA       -5.591894mA          -6.209108mA
+  0.50    -6.694696mA       -6.525883mA          -6.765898mA
+  0.60    -7.186085mA       -7.271372mA          -7.127487mA
+  0.70    -7.501974mA       -7.827161mA          -7.398777mA
+  0.80    -7.747264mA       -8.192150mA          -7.614967mA
+  0.90    -7.946053mA       -8.442739mA          -7.794856mA
+  1.00    -8.112642mA       -8.647928mA          -7.949846mA
+  1.10    -8.255932mA       -8.820317mA          -8.086935mA
+  1.20    -8.381921mA       -8.968206mA          -8.210725mA
+  1.30    -8.494611mA       -9.097295mA          -8.324315mA
+  1.40    -8.596900mA       -9.211784mA          -8.430004mA
+  1.50    -8.691089mA       -9.314673mA          -8.529494mA
+  1.60    -8.778479mA       -9.407962mA          -8.623884mA
+  1.70    -8.860368mA       -9.493551mA          -8.714073mA
+  1.80    -8.937858mA       -9.572640mA          -8.800963mA
+  1.90    -9.011447mA       -9.646329mA          -8.884952mA
+  2.00    -9.081837mA       -9.715418mA          -8.966642mA
+  2.10    -9.149526mA       -9.780507mA          -9.046332mA
+  2.20    -9.214816mA       -9.842296mA          -9.124421mA
+  2.30    -9.278305mA       -9.901185mA          -9.201211mA
+  2.40    -9.340094mA       -9.957574mA          -9.277001mA
+  2.50    -9.400784mA       -10.011863mA         -9.352391mA
+  2.60    -9.460574mA       -10.063852mA         -9.427582mA
+  2.70    -9.519964mA       -10.115841mA         -9.503173mA
+  2.80    -9.579454mA       -10.165830mA         -9.579563mA
+  2.90    -9.639644mA       -10.215819mA         -9.657654mA
+  3.00    -9.701034mA       -10.264808mA         -9.737845mA
+  3.10    -9.764525mA       -10.315796mA         -9.821135mA
+  3.20    -9.830715mA       -10.367780mA         -9.908326mA
+  3.30    -9.900606mA       -10.421706mA         -10.000817mA
+  3.40    -9.975092mA       -10.478956mA         -10.098808mA
+  3.50    -10.055705mA      -10.535873mA         -10.202798mA
+  3.60    -10.141346mA      -10.578599mA         -10.316786mA
+  3.70    -10.228551mA      -10.620789mA         -10.438679mA
+  3.80    -10.281620mA      -10.662980mA         -10.570555mA
+  3.90    -10.322662mA      -10.705170mA         -10.682977mA
+  4.00    -10.363704mA      -10.747360mA         -10.725640mA
+  4.10    -10.404746mA      -10.789550mA         -10.768303mA
+  4.20    -10.445787mA      -10.831741mA         -10.810966mA
+  4.30    -10.486829mA      -10.873931mA         -10.853629mA
+  4.40    -10.527871mA      -10.916121mA         -10.896292mA
+  4.50    -10.568913mA      -10.958311mA         -10.938955mA
+  4.60    -10.609955mA      -11.000502mA         -10.981618mA
+  4.70    -10.650997mA      -11.042692mA         -11.024281mA
+  4.80    -10.692039mA      -11.084882mA         -11.066944mA
+  4.90    -10.733081mA      -11.127072mA         -11.109607mA
+  5.00    -10.774122mA      -11.169262mA         -11.152270mA
+  5.10    -10.815164mA      -11.211453mA         -11.194933mA
+  5.20    -10.856206mA      -11.253643mA         -11.237597mA
+  5.30    -10.897248mA      -11.295833mA         -11.280260mA
+  5.40    -10.938290mA      -11.338023mA         -11.322923mA
+  5.50    -10.979332mA      -11.380214mA         -11.365586mA
+  5.60    -11.020374mA      -11.422404mA         -11.408249mA
+  5.70    -11.061416mA      -11.464594mA         -11.450912mA
+  5.80    -11.102458mA      -11.506784mA         -11.493575mA
+  5.90    -11.143499mA      -11.548975mA         -11.536238mA
+  6.00    -11.184541mA      -11.591165mA         -11.578901mA
+  6.10    -11.225583mA      -11.633355mA         -11.621564mA
+  6.20    -11.266625mA      -11.675545mA         -11.664227mA
+  6.30    -11.307667mA      -11.717736mA         -11.706890mA
+  6.40    -11.348709mA      -11.759926mA         -11.749553mA
+  6.50    -11.389751mA      -11.802116mA         -11.792216mA
+  6.55    -11.410272mA      -11.823211mA         -11.813548mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.204000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270300uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.287529/0.242724n  0.301503/0.328867n  0.291718/0.195168n
+dV/dt_f  0.313320/0.253363n  0.309840/0.389332n  0.311820/0.168025n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.782900V         2.609000V            2.960100V
+0.2020ns          2.783000V         2.608900V            2.962600V
+0.4040ns          2.787900V         2.610900V            3.090500V
+0.6061ns          3.029800V         2.611800V            3.431300V
+0.8081ns          3.255100V         2.678900V            3.466400V
+1.0101ns          3.294700V         2.982700V            3.469200V
+1.2121ns          3.298300V         3.109600V            3.469600V
+1.4141ns          3.299300V         3.123400V            3.469800V
+1.6162ns          3.299600V         3.137700V            3.469900V
+1.8182ns          3.299700V         3.138900V            3.469900V
+2.0202ns          3.299800V         3.139300V            3.469900V
+2.2222ns          3.299900V         3.139600V            3.469900V
+2.4242ns          3.299900V         3.139700V            3.469200V
+2.6263ns          3.299900V         3.139700V            3.471700V
+2.8283ns          3.299900V         3.139800V            3.470600V
+3.0303ns          3.299900V         3.139800V            3.470200V
+3.2323ns          3.299900V         3.139900V            3.470100V
+3.4343ns          3.302400V         3.139900V            3.470000V
+3.6364ns          3.301400V         3.139900V            3.470000V
+3.8384ns          3.300600V         3.139900V            3.470000V
+4.0404ns          3.300200V         3.139900V            3.470000V
+4.2424ns          3.300000V         3.139900V            3.470000V
+4.4444ns          3.300000V         3.139900V            3.470000V
+4.6465ns          3.300000V         3.139900V            3.469900V
+4.8485ns          3.300000V         3.140000V            3.469900V
+5.0505ns          3.300000V         3.141300V            3.469900V
+5.2525ns          3.300000V         3.142100V            3.469900V
+5.4545ns          3.299900V         3.140900V            3.469900V
+5.6566ns          3.299900V         3.140500V            3.469900V
+5.8586ns          3.299900V         3.140200V            3.469900V
+6.0606ns          3.299900V         3.140100V            3.469900V
+6.2626ns          3.299900V         3.140000V            3.469900V
+6.4646ns          3.299900V         3.140000V            3.469900V
+6.6667ns          3.299900V         3.140000V            3.470000V
+6.8687ns          3.299900V         3.140000V            3.470000V
+7.0707ns          3.299900V         3.140000V            3.470000V
+7.2727ns          3.299900V         3.139900V            3.470000V
+7.4747ns          3.299900V         3.139900V            3.470000V
+7.6768ns          3.299900V         3.139900V            3.470000V
+7.8788ns          3.299900V         3.139900V            3.470000V
+8.0808ns          3.299900V         3.139900V            3.470000V
+8.2828ns          3.299900V         3.139900V            3.470000V
+8.4848ns          3.299900V         3.139800V            3.470000V
+8.6869ns          3.299900V         3.139800V            3.470000V
+8.8889ns          3.299900V         3.139900V            3.470000V
+9.0909ns          3.299900V         3.139900V            3.470000V
+9.2929ns          3.299900V         3.139900V            3.470000V
+9.4949ns          3.300000V         3.139900V            3.470000V
+9.6970ns          3.300000V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.139900V            3.470000V
+11.7172ns         3.300000V         3.139900V            3.470000V
+11.9192ns         3.300000V         3.139900V            3.470000V
+12.1212ns         3.300000V         3.139900V            3.470000V
+12.3232ns         3.300000V         3.139900V            3.470000V
+12.5253ns         3.300000V         3.139900V            3.470000V
+12.7273ns         3.300000V         3.139900V            3.470000V
+12.9293ns         3.300000V         3.139900V            3.470000V
+13.1313ns         3.300000V         3.140000V            3.470000V
+13.3333ns         3.300000V         3.140000V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              4.225900uV        4.920300uV           3.956100uV
+0.2020ns          -0.116150mV       2.502300uV           -0.231550mV
+0.4040ns          -1.969300mV       5.640900uV           0.966840mV
+0.6061ns          23.188000mV       -0.508470mV          0.314560V
+0.8081ns          0.256150V         -5.285700mV          0.577600V
+1.0101ns          0.498250V         54.786000mV          0.667290V
+1.2121ns          0.599860V         0.232770V            0.689990V
+1.4141ns          0.636760V         0.420560V            0.696020V
+1.6162ns          0.647730V         0.550470V            0.696970V
+1.8182ns          0.651730V         0.605400V            0.696980V
+2.0202ns          0.652900V         0.628190V            0.696540V
+2.2222ns          0.653040V         0.636320V            0.696120V
+2.4242ns          0.653000V         0.639440V            0.698020V
+2.6263ns          0.652920V         0.640980V            0.608850V
+2.8283ns          0.652830V         0.641740V            0.523850V
+3.0303ns          0.652750V         0.642070V            0.484440V
+3.2323ns          0.652670V         0.642220V            0.464640V
+3.4343ns          0.646540V         0.642370V            0.456500V
+3.6364ns          0.546150V         0.642430V            0.451090V
+3.8384ns          0.483220V         0.642470V            0.449010V
+4.0404ns          0.451320V         0.642490V            0.447190V
+4.2424ns          0.434720V         0.642510V            0.447190V
+4.4444ns          0.427460V         0.642520V            0.447460V
+4.6465ns          0.422730V         0.642530V            0.449720V
+4.8485ns          0.420080V         0.642410V            0.452230V
+5.0505ns          0.418790V         0.647910V            0.454820V
+5.2525ns          0.418520V         0.569370V            0.457130V
+5.4545ns          0.419000V         0.507240V            0.459260V
+5.6566ns          0.420340V         0.472210V            0.461230V
+5.8586ns          0.422900V         0.450470V            0.463090V
+6.0606ns          0.425610V         0.440570V            0.464890V
+6.2626ns          0.428790V         0.434240V            0.466650V
+6.4646ns          0.432030V         0.430580V            0.468260V
+6.6667ns          0.435070V         0.428580V            0.469780V
+6.8687ns          0.437890V         0.427410V            0.471150V
+7.0707ns          0.440590V         0.426660V            0.472420V
+7.2727ns          0.443180V         0.426510V            0.473570V
+7.4747ns          0.445620V         0.426790V            0.474650V
+7.6768ns          0.447910V         0.427810V            0.475620V
+7.8788ns          0.450050V         0.429350V            0.476520V
+8.0808ns          0.452040V         0.431730V            0.477340V
+8.2828ns          0.453900V         0.435000V            0.478100V
+8.4848ns          0.455630V         0.438710V            0.478780V
+8.6869ns          0.457250V         0.442390V            0.479420V
+8.8889ns          0.458760V         0.446040V            0.479990V
+9.0909ns          0.460180V         0.449510V            0.480530V
+9.2929ns          0.461490V         0.452860V            0.481010V
+9.4949ns          0.462720V         0.455990V            0.481460V
+9.6970ns          0.463870V         0.458960V            0.481860V
+9.8990ns          0.464940V         0.461730V            0.482240V
+10.1010ns         0.466405V         0.465580V            0.482735V
+10.3030ns         0.467740V         0.469110V            0.483180V
+10.5051ns         0.468550V         0.471260V            0.483440V
+10.7071ns         0.469310V         0.473300V            0.483680V
+10.9091ns         0.470010V         0.475190V            0.483900V
+11.1111ns         0.470670V         0.476990V            0.484100V
+11.3131ns         0.471280V         0.478660V            0.484280V
+11.5152ns         0.471860V         0.480240V            0.484450V
+11.7172ns         0.472390V         0.481710V            0.484610V
+11.9192ns         0.472890V         0.483100V            0.484740V
+12.1212ns         0.473350V         0.484400V            0.484870V
+12.3232ns         0.473780V         0.485630V            0.484990V
+12.5253ns         0.474180V         0.486770V            0.485100V
+12.7273ns         0.474560V         0.487850V            0.485200V
+12.9293ns         0.474910V         0.488850V            0.485290V
+13.1313ns         0.475230V         0.489800V            0.485370V
+13.3333ns         0.475530V         0.490690V            0.485440V
+13.5354ns         0.475810V         0.491530V            0.485510V
+13.7374ns         0.476080V         0.492300V            0.485570V
+13.9394ns         0.476320V         0.493040V            0.485630V
+14.1414ns         0.476550V         0.493730V            0.485680V
+14.3434ns         0.476760V         0.494380V            0.485730V
+14.5455ns         0.476960V         0.494980V            0.485780V
+14.7475ns         0.477140V         0.495550V            0.485810V
+14.9495ns         0.477310V         0.496080V            0.485850V
+15.1515ns         0.477470V         0.496580V            0.485880V
+15.3535ns         0.477620V         0.497050V            0.485920V
+15.5556ns         0.477760V         0.497490V            0.485940V
+15.7576ns         0.477880V         0.497900V            0.485970V
+15.9596ns         0.478000V         0.498290V            0.485990V
+16.1616ns         0.478110V         0.498650V            0.486010V
+16.3636ns         0.478220V         0.499000V            0.486030V
+16.5657ns         0.478310V         0.499300V            0.486050V
+16.7677ns         0.478400V         0.499590V            0.486070V
+16.9697ns         0.478480V         0.499870V            0.486080V
+17.1717ns         0.478560V         0.500150V            0.486100V
+17.3737ns         0.478630V         0.500410V            0.486110V
+17.5758ns         0.478700V         0.500640V            0.486120V
+17.7778ns         0.478760V         0.500850V            0.486130V
+17.9798ns         0.478820V         0.501040V            0.486140V
+18.1818ns         0.478870V         0.501230V            0.486150V
+18.3838ns         0.478920V         0.501420V            0.486160V
+18.5859ns         0.478970V         0.501600V            0.486160V
+18.7879ns         0.479010V         0.501750V            0.486170V
+18.9899ns         0.479050V         0.501890V            0.486170V
+19.1919ns         0.479090V         0.502030V            0.486180V
+19.3939ns         0.479130V         0.502160V            0.486190V
+19.5960ns         0.479160V         0.502290V            0.486190V
+19.7980ns         0.479190V         0.502400V            0.486190V
+20.0000ns         0.479220V         0.502510V            0.486200V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.479590V         0.504150V            0.486240V
+0.2020ns          0.479620V         0.504110V            0.490470V
+0.4040ns          0.474700V         0.515850V            0.339650V
+0.6061ns          0.247410V         0.518820V            26.921000mV
+0.8081ns          33.630000mV       0.443630V            3.148700mV
+1.0101ns          5.280400mV        0.238780V            1.060300mV
+1.2121ns          1.954600mV        78.283000mV          0.294910mV
+1.4141ns          1.002900mV        15.120000mV          0.121950mV
+1.6162ns          0.281790mV        5.205600mV           54.285000uV
+1.8182ns          0.158200mV        2.668100mV           18.736000uV
+2.0202ns          86.848000uV       1.413600mV           -3.438700uV
+2.2222ns          51.525000uV       0.962940mV           -2.338900uV
+2.4242ns          18.844000uV       0.395150mV           -0.402350mV
+2.6263ns          5.905300uV        0.211990mV           -8.792700uV
+2.8283ns          1.900600uV        0.117500mV           -65.770000uV
+3.0303ns          -0.928100uV       94.558000uV          -55.523000uV
+3.2323ns          1.519900uV        57.044000uV          -52.135000uV
+3.4343ns          91.150000uV       30.103000uV          -44.758000uV
+3.6364ns          -33.181000uV      19.965000uV          -45.346000uV
+3.8384ns          -61.875000uV      10.378000uV          -43.013000uV
+4.0404ns          -55.678000uV      5.470400uV           -40.659000uV
+4.2424ns          -56.185000uV      2.225700uV           -38.424000uV
+4.4444ns          -54.079000uV      0.339030uV           -36.424000uV
+4.6465ns          -49.722000uV      42.294000nV          -34.475000uV
+4.8485ns          -47.356000uV      -67.623000uV         -32.629000uV
+5.0505ns          -45.017000uV      0.334260mV           -30.892000uV
+5.2525ns          -42.772000uV      24.321000uV          -29.369000uV
+5.4545ns          -40.550000uV      -57.294000uV         -27.879000uV
+5.6566ns          -38.605000uV      -81.026000uV         -26.455000uV
+5.8586ns          -36.728000uV      -83.374000uV         -25.106000uV
+6.0606ns          -34.884000uV      -73.915000uV         -23.906000uV
+6.2626ns          -33.048000uV      -70.059000uV         -22.718000uV
+6.4646ns          -31.513000uV      -66.837000uV         -21.555000uV
+6.6667ns          -30.051000uV      -63.741000uV         -20.455000uV
+6.8687ns          -28.580000uV      -60.682000uV         -19.480000uV
+7.0707ns          -27.108000uV      -57.943000uV         -18.510000uV
+7.2727ns          -25.888000uV      -55.297000uV         -17.548000uV
+7.4747ns          -24.730000uV      -52.722000uV         -16.641000uV
+7.6768ns          -23.520000uV      -50.167000uV         -15.845000uV
+7.8788ns          -22.298000uV      -47.891000uV         -15.046000uV
+8.0808ns          -21.294000uV      -45.695000uV         -14.242000uV
+8.2828ns          -20.344000uV      -43.550000uV         -13.487000uV
+8.4848ns          -19.327000uV      -41.420000uV         -12.832000uV
+8.6869ns          -18.294000uV      -39.563000uV         -12.169000uV
+8.8889ns          -17.459000uV      -37.784000uV         -11.491000uV
+9.0909ns          -16.672000uV      -36.017000uV         -10.860000uV
+9.2929ns          -15.813000uV      -34.253000uV         -10.318000uV
+9.4949ns          -14.935000uV      -32.736000uV         -9.766400uV
+9.6970ns          -14.237000uV      -31.289000uV         -9.192700uV
+9.8990ns          -13.584000uV      -29.817000uV         -8.661200uV
+10.1010ns         -12.478000uV      -27.709000uV         -7.982350uV
+10.3030ns         -11.518000uV      -25.885000uV         -7.262900uV
+10.5051ns         -10.975000uV      -24.642000uV         -6.813500uV
+10.7071ns         -10.351000uV      -23.387000uV         -6.441800uV
+10.9091ns         -9.707800uV       -22.333000uV         -6.054500uV
+11.1111ns         -9.217800uV       -21.337000uV         -5.636200uV
+11.3131ns         -8.765200uV       -20.281000uV         -5.254700uV
+11.5152ns         -8.231600uV       -19.208000uV         -4.946000uV
+11.7172ns         -7.678200uV       -18.321000uV         -4.620100uV
+11.9192ns         -7.266900uV       -17.488000uV         -4.260300uV
+12.1212ns         -6.890500uV       -16.587000uV         -3.935200uV
+12.3232ns         -6.432500uV       -15.666000uV         -3.678600uV
+12.5253ns         -5.954600uV       -14.919000uV         -3.403800uV
+12.7273ns         -5.609300uV       -14.221000uV         -3.092900uV
+12.9293ns         -5.296400uV       -13.450000uV         -2.814900uV
+13.1313ns         -4.902200uV       -12.657000uV         -2.601600uV
+13.3333ns         -4.488100uV       -12.026000uV         -2.369400uV
+13.5354ns         -4.198200uV       -11.442000uV         -2.099800uV
+13.7374ns         -3.938700uV       -10.780000uV         -1.861200uV
+13.9394ns         -3.598400uV       -10.096000uV         -1.684200uV
+14.1414ns         -3.238300uV       -9.563600uV          -1.487800uV
+14.3434ns         -2.995000uV       -9.074900uV          -1.252900uV
+14.5455ns         -2.780300uV       -8.505800uV          -1.047700uV
+14.7475ns         -2.485800uV       -7.913400uV          -0.901200uV
+14.9495ns         -2.171700uV       -7.464100uV          -0.734910uV
+15.1515ns         -1.967700uV       -7.055800uV          -0.529500uV
+15.3535ns         -1.790700uV       -6.565500uV          -0.352370uV
+15.5556ns         -1.535100uV       -6.051500uV          -0.231220uV
+15.7576ns         -1.260300uV       -5.672300uV          -90.901000nV
+15.9596ns         -1.089700uV       -5.331900uV          87.337000nV
+16.1616ns         -0.944660uV       -4.908600uV          0.238960uV
+16.3636ns         -0.722200uV       -4.461500uV          0.337930uV
+16.5657ns         -0.480790uV       -4.141700uV          0.456510uV
+16.7677ns         -0.338220uV       -3.858700uV          0.613870uV
+16.9697ns         -0.219860uV       -3.492600uV          0.746520uV
+17.1717ns         -26.846000nV      -3.102500uV          0.830300uV
+17.3737ns         0.184450uV        -2.833200uV          0.932440uV
+17.5758ns         0.301760uV        -2.598700uV          1.070900uV
+17.7778ns         0.396050uV        -2.281300uV          1.185800uV
+17.9798ns         0.563350uV        -1.940200uV          1.253900uV
+18.1818ns         0.748530uV        -1.713800uV          1.340400uV
+18.3838ns         0.849240uV        -1.520500uV          1.463300uV
+18.5859ns         0.929260uV        -1.244900uV          1.563400uV
+18.7879ns         1.076500uV        -0.945630uV          1.618300uV
+18.9899ns         1.240200uV        -0.755480uV          1.685500uV
+19.1919ns         1.323300uV        -0.596720uV          1.777100uV
+19.3939ns         1.386600uV        -0.356900uV          1.868700uV
+19.5960ns         1.516000uV        -93.762000nV         1.960300uV
+19.7980ns         1.661600uV        58.234000nV          2.029300uV
+20.0000ns         1.679900uV        0.178250uV           2.053600uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468600V
+0.4040ns          3.300900V         3.139100V            3.481500V
+0.6061ns          3.273500V         3.140100V            3.087100V
+0.8081ns          2.996200V         3.146300V            2.839700V
+1.0101ns          2.788200V         3.080900V            2.749500V
+1.2121ns          2.688900V         2.938500V            2.718000V
+1.4141ns          2.644300V         2.755500V            2.708000V
+1.6162ns          2.624600V         2.644100V            2.704400V
+1.8182ns          2.616600V         2.580800V            2.704300V
+2.0202ns          2.613600V         2.541800V            2.704600V
+2.2222ns          2.612200V         2.522600V            2.705800V
+2.4242ns          2.612400V         2.511700V            2.715900V
+2.6263ns          2.613100V         2.506400V            2.750300V
+2.8283ns          2.613800V         2.503800V            2.759900V
+3.0303ns          2.614700V         2.502700V            2.769100V
+3.2323ns          2.615500V         2.502100V            2.777600V
+3.4343ns          2.621600V         2.502400V            2.785300V
+3.6364ns          2.628100V         2.502800V            2.792600V
+3.8384ns          2.632500V         2.503300V            2.799400V
+4.0404ns          2.639100V         2.503900V            2.806100V
+4.2424ns          2.645800V         2.504500V            2.812200V
+4.4444ns          2.652000V         2.505100V            2.818200V
+4.6465ns          2.658100V         2.505700V            2.823700V
+4.8485ns          2.663800V         2.508100V            2.829100V
+5.0505ns          2.669000V         2.489000V            2.834000V
+5.2525ns          2.674300V         2.476800V            2.838800V
+5.4545ns          2.679100V         2.477300V            2.843300V
+5.6566ns          2.683900V         2.482300V            2.847700V
+5.8586ns          2.688200V         2.488300V            2.851700V
+6.0606ns          2.692500V         2.494500V            2.855700V
+6.2626ns          2.696400V         2.500200V            2.859400V
+6.4646ns          2.700300V         2.505800V            2.863000V
+6.6667ns          2.703900V         2.511100V            2.866300V
+6.8687ns          2.707400V         2.516200V            2.869600V
+7.0707ns          2.710700V         2.521000V            2.872700V
+7.2727ns          2.713900V         2.525700V            2.875700V
+7.4747ns          2.716900V         2.530100V            2.878500V
+7.6768ns          2.719800V         2.534400V            2.881200V
+7.8788ns          2.722500V         2.538400V            2.883800V
+8.0808ns          2.725200V         2.542300V            2.886300V
+8.2828ns          2.727700V         2.545900V            2.888700V
+8.4848ns          2.730200V         2.549500V            2.891000V
+8.6869ns          2.732400V         2.552800V            2.893100V
+8.8889ns          2.734700V         2.556100V            2.895300V
+9.0909ns          2.736800V         2.559100V            2.897300V
+9.2929ns          2.738800V         2.562100V            2.899200V
+9.4949ns          2.740700V         2.564900V            2.901100V
+9.6970ns          2.742600V         2.567700V            2.903000V
+9.8990ns          2.744300V         2.570200V            2.904700V
+10.1010ns         2.746850V         2.573900V            2.907350V
+10.3030ns         2.749200V         2.577400V            2.909900V
+10.5051ns         2.750700V         2.579600V            2.911600V
+10.7071ns         2.752100V         2.581700V            2.913200V
+10.9091ns         2.753400V         2.583700V            2.914800V
+11.1111ns         2.754700V         2.585700V            2.916300V
+11.3131ns         2.756000V         2.587500V            2.917800V
+11.5152ns         2.757200V         2.589300V            2.919300V
+11.7172ns         2.758300V         2.591000V            2.920700V
+11.9192ns         2.759400V         2.592600V            2.922000V
+12.1212ns         2.760400V         2.594200V            2.923300V
+12.3232ns         2.761400V         2.595700V            2.924600V
+12.5253ns         2.762300V         2.597100V            2.925800V
+12.7273ns         2.763200V         2.598500V            2.927000V
+12.9293ns         2.764000V         2.599800V            2.928100V
+13.1313ns         2.764900V         2.601100V            2.929200V
+13.3333ns         2.765600V         2.602300V            2.930200V
+13.5354ns         2.766400V         2.603500V            2.931300V
+13.7374ns         2.767100V         2.604600V            2.932200V
+13.9394ns         2.767800V         2.605700V            2.933200V
+14.1414ns         2.768400V         2.606800V            2.934100V
+14.3434ns         2.769000V         2.607800V            2.935000V
+14.5455ns         2.769600V         2.608700V            2.935800V
+14.7475ns         2.770200V         2.609600V            2.936600V
+14.9495ns         2.770700V         2.610500V            2.937400V
+15.1515ns         2.771200V         2.611300V            2.938200V
+15.3535ns         2.771700V         2.612100V            2.938900V
+15.5556ns         2.772200V         2.612900V            2.939600V
+15.7576ns         2.772600V         2.613600V            2.940300V
+15.9596ns         2.773000V         2.614400V            2.941000V
+16.1616ns         2.773400V         2.615000V            2.941600V
+16.3636ns         2.773800V         2.615700V            2.942200V
+16.5657ns         2.774100V         2.616300V            2.942800V
+16.7677ns         2.774400V         2.616900V            2.943400V
+16.9697ns         2.774700V         2.617500V            2.943900V
+17.1717ns         2.775000V         2.618000V            2.944500V
+17.3737ns         2.775300V         2.618600V            2.945000V
+17.5758ns         2.775600V         2.619100V            2.945500V
+17.7778ns         2.775800V         2.619500V            2.945900V
+17.9798ns         2.776100V         2.620000V            2.946400V
+18.1818ns         2.776300V         2.620400V            2.946900V
+18.3838ns         2.776500V         2.620900V            2.947300V
+18.5859ns         2.776700V         2.621300V            2.947700V
+18.7879ns         2.776900V         2.621700V            2.948100V
+18.9899ns         2.777100V         2.622000V            2.948500V
+19.1919ns         2.777200V         2.622400V            2.948900V
+19.3939ns         2.777400V         2.622700V            2.949300V
+19.5960ns         2.777500V         2.623000V            2.949600V
+19.7980ns         2.777700V         2.623300V            2.950000V
+20.0000ns         2.777800V         2.623600V            2.950300V
+|  
+| End [Model] lvc330f040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330fxxxaaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415500nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+| End [Model] lvc330fxxxaaaaaaaain
+|************************************************************************
+[Model]           lvc330fxxxbaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201050A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133030A
+  -1.38    -0.116640A        -0.121710A           -0.116640A
+  -1.30    -0.101410A        -0.107420A           -0.100700A
+  -1.22    -86.417000mA      -93.409000mA         -84.978000mA
+  -1.14    -71.666000mA      -79.637000mA         -69.556000mA
+  -1.06    -57.221000mA      -66.146000mA         -54.661000mA
+  -0.98    -43.217000mA      -53.024000mA         -40.890000mA
+  -0.90    -29.927000mA      -40.408000mA         -29.654000mA
+  -0.82    -17.982000mA      -28.511000mA         -21.115000mA
+  -0.74    -8.854400mA       -17.682000mA         -13.653000mA
+  -0.66    -3.663100mA       -8.577600mA          -7.237700mA
+  -0.58    -1.172200mA       -2.564300mA          -2.648300mA
+  -0.50    -0.318120mA       -0.464400mA          -0.594790mA
+  -0.42    -0.137880mA       -0.131860mA          -0.170510mA
+  -0.34    -0.109480mA       -92.671000uA         -0.122000mA
+  -0.26    -0.105780mA       -87.760000uA         -0.117970mA
+  -0.18    -0.105360mA       -87.079000uA         -0.117690mA
+  -0.10    -0.105300mA       -86.972000uA         -0.117660mA
+  -0.02    -0.105290mA       -86.946000uA         -0.117640mA
+  0.06    -0.105270mA       -86.931000uA         -0.117630mA
+  0.14    -0.105260mA       -86.918000uA         -0.117610mA
+  0.22    -0.105240mA       -86.905000uA         -0.117600mA
+  0.30    -0.105230mA       -86.892000uA         -0.117580mA
+  0.38    -0.105220mA       -86.878000uA         -0.117560mA
+  0.46    -0.105200mA       -86.864000uA         -0.117540mA
+  0.54    -0.105180mA       -86.849000uA         -0.117530mA
+  0.62    -0.105170mA       -86.834000uA         -0.117500mA
+  0.70    -0.105150mA       -86.818000uA         -0.117480mA
+  0.78    -0.105130mA       -86.801000uA         -0.117460mA
+  0.86    -0.105110mA       -86.783000uA         -0.117420mA
+  0.94    -0.105060mA       -86.761000uA         -0.117350mA
+  1.02    -0.105000mA       -86.718000uA         -0.117250mA
+  1.10    -0.104900mA       -86.652000uA         -0.117140mA
+  1.18    -0.104790mA       -86.563000uA         -0.117010mA
+  1.26    -0.104660mA       -86.454000uA         -0.116870mA
+  1.34    -0.104520mA       -86.328000uA         -0.116710mA
+  1.42    -0.104360mA       -86.186000uA         -0.116550mA
+  1.50    -0.104190mA       -86.027000uA         -0.116380mA
+  1.58    -0.104010mA       -85.852000uA         -0.116200mA
+  1.66    -0.103810mA       -85.660000uA         -0.116010mA
+  1.74    -0.103600mA       -85.448000uA         -0.115810mA
+  1.82    -0.103380mA       -85.214000uA         -0.115600mA
+  1.90    -0.103130mA       -84.953000uA         -0.115380mA
+  1.98    -0.102860mA       -84.659000uA         -0.115140mA
+  2.06    -0.102560mA       -84.336000uA         -0.114880mA
+  2.14    -0.102230mA       -83.988000uA         -0.114600mA
+  2.22    -0.101860mA       -83.605000uA         -0.114300mA
+  2.30    -0.101430mA       -83.172000uA         -0.113960mA
+  2.38    -0.100960mA       -82.673000uA         -0.113590mA
+  2.46    -0.100430mA       -82.088000uA         -0.113170mA
+  2.54    -99.809000uA      -81.393000uA         -0.112690mA
+  2.62    -99.072000uA      -80.257000uA         -0.112130mA
+  2.70    -98.172000uA      -76.079000uA         -0.111480mA
+  2.78    -97.041000uA      -68.566000uA         -0.110710mA
+  2.86    -94.411000uA      -58.013000uA         -0.109770mA
+  2.94    -86.817000uA      -44.639000uA         -0.108560mA
+  3.02    -74.531000uA      -28.610000uA         -0.106940mA
+  3.10    -57.975000uA      -10.054000uA         -0.102590mA
+  3.18    -37.471000uA      11.025000uA          -91.172000uA
+  3.26    -13.273000uA      34.949000uA          -73.303000uA
+  3.30    0.149480uA        48.450000uA          -62.148000uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.925400uA        1.695300uA           2.182200uA
+  -3.26    1.907100uA        1.679500uA           2.161600uA
+  -3.22    1.889100uA        1.664000uA           2.141300uA
+  -3.18    1.871200uA        1.648600uA           2.121100uA
+  -3.14    1.853600uA        1.633400uA           2.101200uA
+  -3.10    1.836100uA        1.618400uA           2.081400uA
+  -3.06    1.818900uA        1.603500uA           2.061900uA
+  -3.02    1.801800uA        1.588800uA           2.042600uA
+  -2.98    1.785000uA        1.574200uA           2.023500uA
+  -2.94    1.768300uA        1.559800uA           2.004600uA
+  -2.90    1.751800uA        1.545600uA           1.985900uA
+  -2.86    1.735600uA        1.531500uA           1.967400uA
+  -2.82    1.719500uA        1.517600uA           1.949100uA
+  -2.78    1.703600uA        1.503800uA           1.931100uA
+  -2.74    1.687800uA        1.490200uA           1.913200uA
+  -2.70    1.672300uA        1.476700uA           1.895500uA
+  -2.66    1.657000uA        1.463400uA           1.878100uA
+  -2.62    1.641800uA        1.450200uA           1.860800uA
+  -2.58    1.626800uA        1.437200uA           1.843800uA
+  -2.54    1.612000uA        1.424300uA           1.827000uA
+  -2.50    1.597400uA        1.411500uA           1.810300uA
+  -2.46    1.582900uA        1.398900uA           1.793900uA
+  -2.42    1.568600uA        1.386500uA           1.777600uA
+  -2.38    1.554500uA        1.374100uA           1.761600uA
+  -2.34    1.540600uA        1.361900uA           1.745700uA
+  -2.30    1.526800uA        1.349900uA           1.730100uA
+  -2.26    1.513300uA        1.337900uA           1.714600uA
+  -2.22    1.499800uA        1.326100uA           1.699300uA
+  -2.18    1.486600uA        1.314500uA           1.684300uA
+  -2.14    1.473500uA        1.302900uA           1.669400uA
+  -2.10    1.460500uA        1.291500uA           1.654700uA
+  -2.06    1.447700uA        1.280200uA           1.640100uA
+  -2.02    1.435100uA        1.269000uA           1.625800uA
+  -1.98    1.422600uA        1.257900uA           1.611700uA
+  -1.94    1.410300uA        1.247000uA           1.597700uA
+  -1.90    1.398200uA        1.236200uA           1.583900uA
+  -1.86    1.386100uA        1.225500uA           1.570300uA
+  -1.82    1.374300uA        1.214800uA           1.556900uA
+  -1.78    1.362500uA        1.204400uA           1.543600uA
+  -1.74    1.351000uA        1.194000uA           1.530500uA
+  -1.70    1.339500uA        1.183700uA           1.517600uA
+  -1.66    1.328200uA        1.173500uA           1.504900uA
+  -1.62    1.317000uA        1.163400uA           1.492300uA
+  -1.58    1.306000uA        1.153500uA           1.479900uA
+  -1.54    1.295100uA        1.143600uA           1.467600uA
+  -1.50    1.284300uA        1.133800uA           1.455500uA
+  -1.46    1.273700uA        1.124100uA           1.443600uA
+  -1.42    1.263200uA        1.114500uA           1.431800uA
+  -1.38    1.252800uA        1.105000uA           1.420200uA
+  -1.34    1.242500uA        1.095600uA           1.408700uA
+  -1.30    1.232300uA        1.086200uA           1.397400uA
+  -1.26    1.222300uA        1.077000uA           1.386200uA
+  -1.22    1.212300uA        1.067800uA           1.375200uA
+  -1.18    1.202500uA        1.058700uA           1.364300uA
+  -1.14    1.192800uA        1.049700uA           1.353500uA
+  -1.10    1.183200uA        1.040800uA           1.342900uA
+  -1.06    1.173700uA        1.031900uA           1.332400uA
+  -1.02    1.164300uA        1.023100uA           1.322100uA
+  -0.98    1.154900uA        1.014400uA           1.311900uA
+  -0.94    1.145700uA        1.005700uA           1.301800uA
+  -0.90    1.136600uA        0.997110uA           1.291800uA
+  -0.86    1.127600uA        0.988570uA           1.281900uA
+  -0.82    1.118600uA        0.980090uA           1.272200uA
+  -0.78    1.109700uA        0.971680uA           1.262500uA
+  -0.74    1.100900uA        0.963320uA           1.253000uA
+  -0.70    1.092200uA        0.955010uA           1.243600uA
+  -0.66    1.083600uA        0.946770uA           1.234300uA
+  -0.62    1.075000uA        0.938590uA           1.225100uA
+  -0.58    1.066500uA        0.930470uA           1.215900uA
+  -0.54    1.058100uA        0.922430uA           1.206900uA
+  -0.50    1.049700uA        0.914500uA           1.198000uA
+  -0.46    1.041400uA        0.906750uA           1.189000uA
+  -0.42    1.033100uA        0.899340uA           1.180100uA
+  -0.38    1.024800uA        0.892740uA           1.171100uA
+  -0.34    1.020592uA        0.890363uA           1.166191uA
+  -0.30    1.020569uA        0.890343uA           1.166164uA
+  -0.26    1.020475uA        0.890261uA           1.166058uA
+  -0.22    1.020102uA        0.889935uA           1.165631uA
+  -0.18    1.018607uA        0.888631uA           1.163922uA
+  -0.14    1.012627uA        0.883414uA           1.157089uA
+  -0.10    0.988706uA        0.862546uA           1.129756uA
+  -0.06    0.893025uA        0.779074uA           1.020425uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+| End [Model] lvc330fxxxbaaaaaaain
+|************************************************************************
+[Model]           lvc330fxxxcaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447790A           -0.471180A
+  -2.18    -0.421140A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201050A           -0.209560A
+  -1.62    -0.174190A        -0.174390A           -0.177660A
+  -1.54    -0.150480A        -0.153310A           -0.151880A
+  -1.46    -0.132440A        -0.136600A           -0.133040A
+  -1.38    -0.116650A        -0.121720A           -0.116660A
+  -1.30    -0.101420A        -0.107430A           -0.100730A
+  -1.22    -86.431000mA      -93.414000mA         -85.016000mA
+  -1.14    -71.684000mA      -79.643000mA         -69.612000mA
+  -1.06    -57.245000mA      -66.154000mA         -54.753000mA
+  -0.98    -43.252000mA      -53.034000mA         -41.074000mA
+  -0.90    -29.984000mA      -40.420000mA         -30.037000mA
+  -0.82    -18.095000mA      -28.529000mA         -21.592000mA
+  -0.74    -9.103200mA       -17.711000mA         -14.139000mA
+  -0.66    -4.031300mA       -8.632500mA          -7.727000mA
+  -0.58    -1.542300mA       -2.680900mA          -3.137100mA
+  -0.50    -0.637910mA       -0.641580mA          -1.050200mA
+  -0.42    -0.382200mA       -0.283040mA          -0.537030mA
+  -0.34    -0.274320mA       -0.191220mA          -0.380580mA
+  -0.26    -0.195030mA       -0.134430mA          -0.271430mA
+  -0.18    -0.125260mA       -86.198000uA         -0.174070mA
+  -0.10    -63.603000uA      -43.916000uA         -87.706000uA
+  -0.02    -11.477000uA      -8.053000uA          -15.489000uA
+  0.06    29.171000uA       20.579000uA          38.171000uA
+  0.14    58.135000uA       42.109000uA          72.311000uA
+  0.22    76.454000uA       57.027000uA          90.391000uA
+  0.30    86.646000uA       66.282000uA          99.147000uA
+  0.38    91.915000uA       71.334000uA          0.103720mA
+  0.46    94.550000uA       73.863000uA          0.106370mA
+  0.54    95.817000uA       75.185000uA          0.107930mA
+  0.62    96.442000uA       75.976000uA          0.108770mA
+  0.70    96.793000uA       76.516000uA          0.109190mA
+  0.78    97.021000uA       76.923000uA          0.109410mA
+  0.86    97.187000uA       77.250000uA          0.109550mA
+  0.94    97.320000uA       77.526000uA          0.109650mA
+  1.02    97.431000uA       77.766000uA          0.109720mA
+  1.10    97.528000uA       77.982000uA          0.109790mA
+  1.18    97.616000uA       78.178000uA          0.109850mA
+  1.26    97.697000uA       78.360000uA          0.109900mA
+  1.34    97.773000uA       78.530000uA          0.109950mA
+  1.42    97.844000uA       78.691000uA          0.110000mA
+  1.50    97.912000uA       78.844000uA          0.110050mA
+  1.58    97.978000uA       78.991000uA          0.110090mA
+  1.66    98.042000uA       79.132000uA          0.110130mA
+  1.74    98.104000uA       79.268000uA          0.110170mA
+  1.82    98.164000uA       79.399000uA          0.110220mA
+  1.90    98.223000uA       79.526000uA          0.110260mA
+  1.98    98.280000uA       79.648000uA          0.110300mA
+  2.06    98.337000uA       79.768000uA          0.110330mA
+  2.14    98.393000uA       79.890000uA          0.110370mA
+  2.22    98.448000uA       80.015000uA          0.110410mA
+  2.30    98.503000uA       80.140000uA          0.110450mA
+  2.38    98.559000uA       80.265000uA          0.110490mA
+  2.46    98.617000uA       80.391000uA          0.110530mA
+  2.54    98.679000uA       80.518000uA          0.110570mA
+  2.62    98.744000uA       80.648000uA          0.110620mA
+  2.70    98.813000uA       80.782000uA          0.110670mA
+  2.78    98.889000uA       80.922000uA          0.110720mA
+  2.86    98.972000uA       81.070000uA          0.110780mA
+  2.94    99.065000uA       81.227000uA          0.110850mA
+  3.02    99.170000uA       81.396000uA          0.110930mA
+  3.10    99.290000uA       81.580000uA          0.111020mA
+  3.18    99.427000uA       81.843000uA          0.111120mA
+  3.26    99.584000uA       82.507000uA          0.111250mA
+  3.30    99.674000uA       83.566000uA          0.111320mA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    0.153710mA        0.132100mA           0.170160mA
+  -3.26    0.152730mA        0.131080mA           0.169210mA
+  -3.22    0.151750mA        0.130060mA           0.168250mA
+  -3.18    0.150760mA        0.129030mA           0.167280mA
+  -3.14    0.149760mA        0.128000mA           0.166290mA
+  -3.10    0.148750mA        0.126970mA           0.165290mA
+  -3.06    0.147740mA        0.125930mA           0.164280mA
+  -3.02    0.146720mA        0.124900mA           0.163270mA
+  -2.98    0.145700mA        0.123870mA           0.162240mA
+  -2.94    0.144670mA        0.122850mA           0.161210mA
+  -2.90    0.143640mA        0.121820mA           0.160170mA
+  -2.86    0.142610mA        0.120800mA           0.159120mA
+  -2.82    0.141580mA        0.119780mA           0.158070mA
+  -2.78    0.140550mA        0.118770mA           0.157010mA
+  -2.74    0.139520mA        0.117770mA           0.155950mA
+  -2.70    0.138490mA        0.116770mA           0.154890mA
+  -2.66    0.137460mA        0.115780mA           0.153830mA
+  -2.62    0.136440mA        0.114800mA           0.152760mA
+  -2.58    0.135420mA        0.113820mA           0.151700mA
+  -2.54    0.134410mA        0.112860mA           0.150630mA
+  -2.50    0.133400mA        0.111900mA           0.149570mA
+  -2.46    0.132400mA        0.110960mA           0.148510mA
+  -2.42    0.131410mA        0.110030mA           0.147460mA
+  -2.38    0.130420mA        0.109110mA           0.146410mA
+  -2.34    0.129450mA        0.108200mA           0.145370mA
+  -2.30    0.128490mA        0.107310mA           0.144330mA
+  -2.26    0.127530mA        0.106430mA           0.143310mA
+  -2.22    0.126590mA        0.105570mA           0.142290mA
+  -2.18    0.125660mA        0.104720mA           0.141280mA
+  -2.14    0.124750mA        0.103880mA           0.140280mA
+  -2.10    0.123850mA        0.103060mA           0.139300mA
+  -2.06    0.122960mA        0.102260mA           0.138330mA
+  -2.02    0.122090mA        0.101480mA           0.137370mA
+  -1.98    0.121230mA        0.100710mA           0.136420mA
+  -1.94    0.120390mA        99.955000uA          0.135490mA
+  -1.90    0.119560mA        99.221000uA          0.134580mA
+  -1.86    0.118760mA        98.504000uA          0.133680mA
+  -1.82    0.117970mA        97.804000uA          0.132800mA
+  -1.78    0.117200mA        97.123000uA          0.131940mA
+  -1.74    0.116440mA        96.459000uA          0.131090mA
+  -1.70    0.115710mA        95.814000uA          0.130260mA
+  -1.66    0.114990mA        95.186000uA          0.129460mA
+  -1.62    0.114300mA        94.577000uA          0.128670mA
+  -1.58    0.113620mA        93.985000uA          0.127900mA
+  -1.54    0.112960mA        93.412000uA          0.127150mA
+  -1.50    0.112320mA        92.857000uA          0.126420mA
+  -1.46    0.111700mA        92.319000uA          0.125710mA
+  -1.42    0.111100mA        91.799000uA          0.125030mA
+  -1.38    0.110520mA        91.297000uA          0.124360mA
+  -1.34    0.109960mA        90.812000uA          0.123710mA
+  -1.30    0.109420mA        90.344000uA          0.123090mA
+  -1.26    0.108900mA        89.893000uA          0.122490mA
+  -1.22    0.108400mA        89.459000uA          0.121900mA
+  -1.18    0.107910mA        89.041000uA          0.121340mA
+  -1.14    0.107450mA        88.639000uA          0.120800mA
+  -1.10    0.107000mA        88.253000uA          0.120280mA
+  -1.06    0.106570mA        87.883000uA          0.119780mA
+  -1.02    0.106160mA        87.527000uA          0.119300mA
+  -0.98    0.105760mA        87.187000uA          0.118840mA
+  -0.94    0.105390mA        86.861000uA          0.118400mA
+  -0.90    0.105030mA        86.548000uA          0.117980mA
+  -0.86    0.104690mA        86.250000uA          0.117580mA
+  -0.82    0.104360mA        85.965000uA          0.117190mA
+  -0.78    0.104050mA        85.693000uA          0.116830mA
+  -0.74    0.103750mA        85.433000uA          0.116480mA
+  -0.70    0.103470mA        85.185000uA          0.116150mA
+  -0.66    0.103200mA        84.949000uA          0.115830mA
+  -0.62    0.102950mA        84.724000uA          0.115540mA
+  -0.58    0.102710mA        84.509000uA          0.115260mA
+  -0.54    0.102490mA        84.306000uA          0.114990mA
+  -0.50    0.102270mA        84.112000uA          0.114740mA
+  -0.46    0.102070mA        83.927000uA          0.114500mA
+  -0.42    0.101880mA        83.752000uA          0.114280mA
+  -0.38    0.101700mA        83.587000uA          0.114070mA
+  -0.34    0.101620mA        83.508000uA          0.113960mA
+  -0.30    0.101620mA        83.508000uA          0.113960mA
+  -0.26    0.101620mA        83.508000uA          0.113960mA
+  -0.22    0.101620mA        83.508000uA          0.113960mA
+  -0.18    0.101620mA        83.508000uA          0.113750mA
+  -0.14    0.100460mA        82.918000uA          0.112450mA
+  -0.10    0.100030mA        82.241000uA          0.112040mA
+  -0.06    99.844000uA       81.938000uA          0.111870mA
+  -0.02    99.724000uA       81.761000uA          0.111750mA
+  0.00    99.674000uA       81.693000uA          0.111690mA
+|  
+| End [Model] lvc330fxxxcaaaaaaain
+|************************************************************************
+[Model]           lvc330s040aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
+  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
+  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
+  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
+  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
+  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
+  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
+  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
+  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
+  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
+  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
+  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
+  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
+  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
+  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
+  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
+  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
+  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
+  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
+  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
+  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
+  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
+  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
+  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
+  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
+  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
+  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
+  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
+  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
+  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
+  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
+  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
+  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
+  0.00    9.270000nA        8.640000nA           10.950000nA
+  0.10    2.215985mA        1.960397mA           2.507890mA
+  0.20    4.086375mA        3.683686mA           4.498680mA
+  0.30    5.594166mA        5.150675mA           5.952471mA
+  0.40    6.738256mA        6.352364mA           6.929962mA
+  0.50    7.557146mA        7.289853mA           7.572152mA
+  0.60    8.124436mA        7.983242mA           8.013343mA
+  0.70    8.511126mA        8.476831mA           8.337834mA
+  0.80    8.778316mA        8.826620mA           8.591424mA
+  0.90    8.972606mA        9.080609mA           8.798515mA
+  1.00    9.121395mA        9.272098mA           8.969206mA
+  1.10    9.240584mA        9.422087mA           9.101296mA
+  1.20    9.339574mA        9.543476mA           9.202186mA
+  1.30    9.424063mA        9.644765mA           9.285275mA
+  1.40    9.498053mA        9.731354mA           9.357665mA
+  1.50    9.564242mA        9.806743mA           9.423455mA
+  1.60    9.625232mA        9.873832mA           9.485944mA
+  1.70    9.684621mA        9.934821mA           9.548134mA
+  1.80    9.747011mA        9.992810mA           9.610224mA
+  1.90    9.814800mA        10.052999mA          9.670813mA
+  2.00    9.885689mA        10.122988mA          9.728603mA
+  2.10    9.955379mA        10.203977mA          9.783293mA
+  2.20    10.021968mA       10.292966mA          9.835282mA
+  2.30    10.083958mA       10.380954mA          9.884972mA
+  2.40    10.141947mA       10.464943mA          9.932861mA
+  2.50    10.196936mA       10.542932mA          9.979551mA
+  2.60    10.249926mA       10.614921mA          10.025941mA
+  2.70    10.300915mA       10.681910mA          10.071930mA
+  2.80    10.350904mA       10.744899mA          10.118920mA
+  2.90    10.400894mA       10.805888mA          10.167909mA
+  3.00    10.451883mA       10.863877mA          10.218899mA
+  3.10    10.504872mA       10.921864mA          10.273889mA
+  3.20    10.559862mA       10.978747mA          10.332878mA
+  3.30    10.618848mA       11.037379mA          10.397868mA
+  3.40    10.682725mA       11.085335mA          10.469857mA
+  3.50    10.751986mA       11.124616mA          10.550843mA
+  3.60    10.804292mA       11.163898mA          10.640599mA
+  3.70    10.840604mA       11.203179mA          10.738212mA
+  3.80    10.876916mA       11.242461mA          10.773505mA
+  3.90    10.913228mA       11.281743mA          10.808797mA
+  4.00    10.949540mA       11.321024mA          10.844090mA
+  4.10    10.985852mA       11.360306mA          10.879382mA
+  4.20    11.022164mA       11.399587mA          10.914675mA
+  4.30    11.058476mA       11.438869mA          10.949967mA
+  4.40    11.094788mA       11.478151mA          10.985259mA
+  4.50    11.131100mA       11.517432mA          11.020552mA
+  4.60    11.167412mA       11.556714mA          11.055844mA
+  4.70    11.203724mA       11.595995mA          11.091137mA
+  4.80    11.240036mA       11.635277mA          11.126429mA
+  4.90    11.276348mA       11.674559mA          11.161721mA
+  5.00    11.312660mA       11.713840mA          11.197014mA
+  5.10    11.348972mA       11.753122mA          11.232306mA
+  5.20    11.385284mA       11.792403mA          11.267599mA
+  5.30    11.421596mA       11.831685mA          11.302891mA
+  5.40    11.457908mA       11.870967mA          11.338183mA
+  5.50    11.494220mA       11.910248mA          11.373476mA
+  5.60    11.530532mA       11.949530mA          11.408768mA
+  5.70    11.566844mA       11.988811mA          11.444061mA
+  5.80    11.603156mA       12.028093mA          11.479353mA
+  5.90    11.639468mA       12.067375mA          11.514645mA
+  6.00    11.675780mA       12.106656mA          11.549938mA
+  6.10    11.712092mA       12.145938mA          11.585230mA
+  6.20    11.748404mA       12.185219mA          11.620523mA
+  6.30    11.784716mA       12.224501mA          11.655815mA
+  6.40    11.821028mA       12.263783mA          11.691107mA
+  6.50    11.857340mA       12.303064mA          11.726400mA
+  6.60    11.893652mA       12.342346mA          11.761692mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    6.260163mA        5.384933mA           7.315403mA
+  -3.20    6.239699mA        5.366401mA           7.291487mA
+  -3.10    6.219236mA        5.347870mA           7.267570mA
+  -3.00    6.198773mA        5.329339mA           7.243653mA
+  -2.90    6.178310mA        5.310808mA           7.219736mA
+  -2.80    6.157847mA        5.292277mA           7.195819mA
+  -2.70    6.137383mA        5.273745mA           7.171903mA
+  -2.60    6.116920mA        5.255214mA           7.147986mA
+  -2.50    6.096457mA        5.236683mA           7.124069mA
+  -2.40    6.075994mA        5.218152mA           7.100152mA
+  -2.30    6.055531mA        5.199621mA           7.076235mA
+  -2.20    6.035067mA        5.181089mA           7.052319mA
+  -2.10    6.014604mA        5.162558mA           7.028402mA
+  -2.00    5.994141mA        5.144027mA           7.004485mA
+  -1.90    5.973678mA        5.125496mA           6.980568mA
+  -1.80    5.953215mA        5.106965mA           6.956651mA
+  -1.70    5.932751mA        5.088433mA           6.932735mA
+  -1.60    5.912288mA        5.069902mA           6.908818mA
+  -1.50    5.891825mA        5.051371mA           6.884901mA
+  -1.40    5.871362mA        5.032840mA           6.860984mA
+  -1.30    5.850899mA        5.014309mA           6.837067mA
+  -1.20    5.830435mA        4.995777mA           6.813151mA
+  -1.10    5.809972mA        4.977246mA           6.789234mA
+  -1.00    5.789509mA        4.958715mA           6.765317mA
+  -0.90    5.769046mA        4.940184mA           6.741400mA
+  -0.80    5.748583mA        4.921653mA           6.717483mA
+  -0.70    5.728119mA        4.903121mA           6.693567mA
+  -0.60    5.707656mA        4.884590mA           6.669650mA
+  -0.50    5.687193mA        4.866059mA           6.645733mA
+  -0.40    5.666730mA        4.847528mA           6.621816mA
+  -0.30    5.646267mA        4.828997mA           6.597899mA
+  -0.20    4.435786mA        3.802115mA           5.174820mA
+  -0.10    2.131925mA        1.838548mA           2.475669mA
+  0.00    -6.170000nA       -5.460000nA          -7.060000nA
+  0.10    -1.893038mA       -1.673728mA          -2.145840mA
+  0.20    -3.512428mA       -3.164516mA          -3.900829mA
+  0.30    -4.854717mA       -4.471005mA          -5.257719mA
+  0.40    -5.916606mA       -5.591894mA          -6.209108mA
+  0.50    -6.694696mA       -6.525883mA          -6.765898mA
+  0.60    -7.186085mA       -7.271372mA          -7.127487mA
+  0.70    -7.501974mA       -7.827161mA          -7.398777mA
+  0.80    -7.747264mA       -8.192150mA          -7.614967mA
+  0.90    -7.946053mA       -8.442739mA          -7.794856mA
+  1.00    -8.112642mA       -8.647928mA          -7.949846mA
+  1.10    -8.255932mA       -8.820317mA          -8.086935mA
+  1.20    -8.381921mA       -8.968206mA          -8.210725mA
+  1.30    -8.494611mA       -9.097295mA          -8.324315mA
+  1.40    -8.596900mA       -9.211784mA          -8.430004mA
+  1.50    -8.691089mA       -9.314673mA          -8.529494mA
+  1.60    -8.778479mA       -9.407962mA          -8.623884mA
+  1.70    -8.860368mA       -9.493551mA          -8.714073mA
+  1.80    -8.937858mA       -9.572640mA          -8.800963mA
+  1.90    -9.011447mA       -9.646329mA          -8.884952mA
+  2.00    -9.081837mA       -9.715418mA          -8.966642mA
+  2.10    -9.149526mA       -9.780507mA          -9.046332mA
+  2.20    -9.214816mA       -9.842296mA          -9.124421mA
+  2.30    -9.278305mA       -9.901185mA          -9.201211mA
+  2.40    -9.340094mA       -9.957574mA          -9.277001mA
+  2.50    -9.400784mA       -10.011863mA         -9.352391mA
+  2.60    -9.460574mA       -10.063852mA         -9.427582mA
+  2.70    -9.519964mA       -10.115841mA         -9.503173mA
+  2.80    -9.579454mA       -10.165830mA         -9.579563mA
+  2.90    -9.639644mA       -10.215819mA         -9.657654mA
+  3.00    -9.701034mA       -10.264808mA         -9.737845mA
+  3.10    -9.764525mA       -10.315796mA         -9.821135mA
+  3.20    -9.830715mA       -10.367780mA         -9.908326mA
+  3.30    -9.900606mA       -10.421706mA         -10.000817mA
+  3.40    -9.975092mA       -10.478956mA         -10.098808mA
+  3.50    -10.055705mA      -10.535873mA         -10.202798mA
+  3.60    -10.141346mA      -10.578599mA         -10.316786mA
+  3.70    -10.228551mA      -10.620789mA         -10.438679mA
+  3.80    -10.281620mA      -10.662980mA         -10.570555mA
+  3.90    -10.322662mA      -10.705170mA         -10.682977mA
+  4.00    -10.363704mA      -10.747360mA         -10.725640mA
+  4.10    -10.404746mA      -10.789550mA         -10.768303mA
+  4.20    -10.445787mA      -10.831741mA         -10.810966mA
+  4.30    -10.486829mA      -10.873931mA         -10.853629mA
+  4.40    -10.527871mA      -10.916121mA         -10.896292mA
+  4.50    -10.568913mA      -10.958311mA         -10.938955mA
+  4.60    -10.609955mA      -11.000502mA         -10.981618mA
+  4.70    -10.650997mA      -11.042692mA         -11.024281mA
+  4.80    -10.692039mA      -11.084882mA         -11.066944mA
+  4.90    -10.733081mA      -11.127072mA         -11.109607mA
+  5.00    -10.774122mA      -11.169262mA         -11.152270mA
+  5.10    -10.815164mA      -11.211453mA         -11.194933mA
+  5.20    -10.856206mA      -11.253643mA         -11.237597mA
+  5.30    -10.897248mA      -11.295833mA         -11.280260mA
+  5.40    -10.938290mA      -11.338023mA         -11.322923mA
+  5.50    -10.979332mA      -11.380214mA         -11.365586mA
+  5.60    -11.020374mA      -11.422404mA         -11.408249mA
+  5.70    -11.061416mA      -11.464594mA         -11.450912mA
+  5.80    -11.102458mA      -11.506784mA         -11.493575mA
+  5.90    -11.143499mA      -11.548975mA         -11.536238mA
+  6.00    -11.184541mA      -11.591165mA         -11.578901mA
+  6.10    -11.225583mA      -11.633355mA         -11.621564mA
+  6.20    -11.266625mA      -11.675545mA         -11.664227mA
+  6.30    -11.307667mA      -11.717736mA         -11.706890mA
+  6.40    -11.348709mA      -11.759926mA         -11.749553mA
+  6.50    -11.389751mA      -11.802116mA         -11.792216mA
+  6.55    -11.410272mA      -11.823211mA         -11.813548mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.287457/0.467122n  0.301305/0.700268n  0.291706/0.349090n
+dV/dt_f  0.309900/0.449885n  0.304680/0.837003n  0.308100/0.266290n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.782900V         2.609000V            2.960100V
+0.2020ns          2.783000V         2.608900V            2.962600V
+0.4040ns          2.788300V         2.610900V            3.086900V
+0.6061ns          3.016200V         2.611900V            3.417200V
+0.8081ns          3.244000V         2.678900V            3.463300V
+1.0101ns          3.291900V         2.961800V            3.467200V
+1.2121ns          3.295700V         3.102900V            3.468900V
+1.4141ns          3.297500V         3.120100V            3.469600V
+1.6162ns          3.298700V         3.136000V            3.469800V
+1.8182ns          3.299500V         3.136600V            3.469900V
+2.0202ns          3.299700V         3.137000V            3.469900V
+2.2222ns          3.299800V         3.138000V            3.469900V
+2.4242ns          3.299900V         3.138900V            3.469200V
+2.6263ns          3.299900V         3.139400V            3.471100V
+2.8283ns          3.299900V         3.139700V            3.470500V
+3.0303ns          3.299900V         3.139800V            3.470100V
+3.2323ns          3.299900V         3.139800V            3.470000V
+3.4343ns          3.300600V         3.139900V            3.470000V
+3.6364ns          3.301100V         3.139900V            3.470000V
+3.8384ns          3.300500V         3.139900V            3.470000V
+4.0404ns          3.300200V         3.139900V            3.470000V
+4.2424ns          3.300000V         3.139900V            3.470000V
+4.4444ns          3.300000V         3.139900V            3.470000V
+4.6465ns          3.300000V         3.139900V            3.470000V
+4.8485ns          3.300000V         3.140000V            3.469900V
+5.0505ns          3.300000V         3.140800V            3.469900V
+5.2525ns          3.300000V         3.141300V            3.469900V
+5.4545ns          3.299900V         3.140700V            3.469900V
+5.6566ns          3.299900V         3.140400V            3.469900V
+5.8586ns          3.299900V         3.140200V            3.469900V
+6.0606ns          3.299900V         3.140000V            3.469900V
+6.2626ns          3.299900V         3.140000V            3.469900V
+6.4646ns          3.299900V         3.140000V            3.469900V
+6.6667ns          3.299900V         3.140000V            3.469900V
+6.8687ns          3.299900V         3.140000V            3.469900V
+7.0707ns          3.299900V         3.139900V            3.469900V
+7.2727ns          3.299900V         3.139900V            3.470000V
+7.4747ns          3.299900V         3.139900V            3.470000V
+7.6768ns          3.299900V         3.139900V            3.470000V
+7.8788ns          3.299900V         3.139900V            3.470000V
+8.0808ns          3.299900V         3.139900V            3.470000V
+8.2828ns          3.299900V         3.139900V            3.470000V
+8.4848ns          3.299900V         3.139900V            3.470000V
+8.6869ns          3.299900V         3.139900V            3.470000V
+8.8889ns          3.299900V         3.139800V            3.470000V
+9.0909ns          3.299900V         3.139800V            3.470000V
+9.2929ns          3.299900V         3.139900V            3.470000V
+9.4949ns          3.299900V         3.139900V            3.470000V
+9.6970ns          3.299900V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.139900V            3.470000V
+11.7172ns         3.300000V         3.139900V            3.470000V
+11.9192ns         3.300000V         3.139900V            3.470000V
+12.1212ns         3.300000V         3.139900V            3.470000V
+12.3232ns         3.300000V         3.139900V            3.470000V
+12.5253ns         3.300000V         3.139900V            3.470000V
+12.7273ns         3.300000V         3.139900V            3.470000V
+12.9293ns         3.300000V         3.139900V            3.470000V
+13.1313ns         3.300000V         3.139900V            3.470000V
+13.3333ns         3.300000V         3.139900V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              4.225900uV        4.920300uV           3.956100uV
+0.2020ns          -0.116230mV       2.501000uV           -0.231630mV
+0.4040ns          -1.733400mV       5.664000uV           -6.571900mV
+0.6061ns          1.816900mV        -0.405040mV          0.151930V
+0.8081ns          0.105890V         -6.434700mV          0.334290V
+1.0101ns          0.246820V         13.033000mV          0.470790V
+1.2121ns          0.360950V         89.173000mV          0.542490V
+1.4141ns          0.454430V         0.176030V            0.572640V
+1.6162ns          0.508590V         0.271450V            0.582550V
+1.8182ns          0.534420V         0.353570V            0.588040V
+2.0202ns          0.543170V         0.429910V            0.588930V
+2.2222ns          0.549780V         0.484400V            0.588840V
+2.4242ns          0.550820V         0.517300V            0.590870V
+2.6263ns          0.551300V         0.536250V            0.553540V
+2.8283ns          0.551520V         0.543010V            0.497470V
+3.0303ns          0.551620V         0.548720V            0.468060V
+3.2323ns          0.551660V         0.549820V            0.453000V
+3.4343ns          0.558640V         0.550520V            0.446500V
+3.6364ns          0.508640V         0.550950V            0.442330V
+3.8384ns          0.463860V         0.551240V            0.440380V
+4.0404ns          0.438900V         0.551370V            0.438930V
+4.2424ns          0.425590V         0.551450V            0.438730V
+4.4444ns          0.417880V         0.551520V            0.438850V
+4.6465ns          0.413990V         0.551560V            0.439830V
+4.8485ns          0.411950V         0.551690V            0.441070V
+5.0505ns          0.411060V         0.558950V            0.443300V
+5.2525ns          0.410360V         0.519020V            0.446000V
+5.4545ns          0.410640V         0.480460V            0.448850V
+5.6566ns          0.411100V         0.455460V            0.451660V
+5.8586ns          0.412570V         0.440580V            0.454380V
+6.0606ns          0.414210V         0.430510V            0.456880V
+6.2626ns          0.416980V         0.426080V            0.459280V
+6.4646ns          0.420210V         0.423650V            0.461440V
+6.6667ns          0.423660V         0.422350V            0.463510V
+6.8687ns          0.426990V         0.421790V            0.465350V
+7.0707ns          0.430100V         0.421350V            0.467110V
+7.2727ns          0.433090V         0.421520V            0.468670V
+7.4747ns          0.435900V         0.421800V            0.470160V
+7.6768ns          0.438640V         0.422560V            0.471470V
+7.8788ns          0.441270V         0.423400V            0.472730V
+8.0808ns          0.443800V         0.425080V            0.473840V
+8.2828ns          0.446130V         0.426920V            0.474900V
+8.4848ns          0.448370V         0.429830V            0.475830V
+8.6869ns          0.450420V         0.433230V            0.476730V
+8.8889ns          0.452380V         0.436930V            0.477510V
+9.0909ns          0.454180V         0.440610V            0.478270V
+9.2929ns          0.455900V         0.444280V            0.478930V
+9.4949ns          0.457470V         0.447610V            0.479560V
+9.6970ns          0.458970V         0.450880V            0.480120V
+9.8990ns          0.460340V         0.453950V            0.480650V
+10.1010ns         0.462260V         0.458380V            0.481335V
+10.3030ns         0.464000V         0.462500V            0.481950V
+10.5051ns         0.465050V         0.464970V            0.482320V
+10.7071ns         0.466050V         0.467390V            0.482650V
+10.9091ns         0.466960V         0.469580V            0.482960V
+11.1111ns         0.467830V         0.471720V            0.483240V
+11.3131ns         0.468630V         0.473660V            0.483500V
+11.5152ns         0.469380V         0.475550V            0.483730V
+11.7172ns         0.470080V         0.477260V            0.483950V
+11.9192ns         0.470740V         0.478940V            0.484140V
+12.1212ns         0.471340V         0.480450V            0.484330V
+12.3232ns         0.471910V         0.481930V            0.484490V
+12.5253ns         0.472440V         0.483270V            0.484640V
+12.7273ns         0.472930V         0.484580V            0.484780V
+12.9293ns         0.473390V         0.485750V            0.484900V
+13.1313ns         0.473820V         0.486910V            0.485020V
+13.3333ns         0.474220V         0.487950V            0.485120V
+13.5354ns         0.474590V         0.488970V            0.485220V
+13.7374ns         0.474940V         0.489880V            0.485310V
+13.9394ns         0.475260V         0.490780V            0.485390V
+14.1414ns         0.475560V         0.491590V            0.485460V
+14.3434ns         0.475840V         0.492380V            0.485530V
+14.5455ns         0.476100V         0.493090V            0.485590V
+14.7475ns         0.476340V         0.493790V            0.485640V
+14.9495ns         0.476570V         0.494420V            0.485700V
+15.1515ns         0.476780V         0.495030V            0.485740V
+15.3535ns         0.476970V         0.495580V            0.485790V
+15.5556ns         0.477160V         0.496120V            0.485820V
+15.7576ns         0.477330V         0.496610V            0.485860V
+15.9596ns         0.477490V         0.497090V            0.485890V
+16.1616ns         0.477630V         0.497510V            0.485920V
+16.3636ns         0.477770V         0.497930V            0.485950V
+16.5657ns         0.477890V         0.498290V            0.485980V
+16.7677ns         0.478010V         0.498640V            0.486000V
+16.9697ns         0.478120V         0.498990V            0.486020V
+17.1717ns         0.478230V         0.499340V            0.486040V
+17.3737ns         0.478320V         0.499630V            0.486060V
+17.5758ns         0.478410V         0.499920V            0.486070V
+17.7778ns         0.478490V         0.500160V            0.486090V
+17.9798ns         0.478570V         0.500400V            0.486100V
+18.1818ns         0.478640V         0.500630V            0.486110V
+18.3838ns         0.478710V         0.500870V            0.486120V
+18.5859ns         0.478770V         0.501070V            0.486130V
+18.7879ns         0.478830V         0.501260V            0.486140V
+18.9899ns         0.478880V         0.501430V            0.486150V
+19.1919ns         0.478930V         0.501590V            0.486160V
+19.3939ns         0.478980V         0.501750V            0.486170V
+19.5960ns         0.479020V         0.501910V            0.486170V
+19.7980ns         0.479060V         0.502040V            0.486180V
+20.0000ns         0.479100V         0.502180V            0.486180V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.479590V         0.504150V            0.486240V
+0.2020ns          0.479620V         0.504110V            0.490470V
+0.4040ns          0.474660V         0.515850V            0.338690V
+0.6061ns          0.260970V         0.518810V            49.227000mV
+0.8081ns          57.693000mV       0.442430V            5.358900mV
+1.0101ns          10.006000mV       0.270560V            1.610600mV
+1.2121ns          3.219300mV        0.116620V            0.420340mV
+1.4141ns          1.539600mV        28.455000mV          0.168590mV
+1.6162ns          0.544500mV        9.235500mV           63.243000uV
+1.8182ns          0.242750mV        4.555900mV           28.107000uV
+2.0202ns          0.152510mV        2.530000mV           3.232400uV
+2.2222ns          71.354000uV       1.674500mV           0.754660uV
+2.4242ns          30.528000uV       0.925740mV           -0.544570mV
+2.6263ns          17.219000uV       0.496800mV           -0.223670mV
+2.8283ns          7.642900uV        0.286310mV           -18.013000uV
+3.0303ns          2.754100uV        0.206810mV           -16.664000uV
+3.2323ns          3.719000uV        0.129010mV           -14.948000uV
+3.4343ns          -0.126320mV       73.076000uV          -9.356000uV
+3.6364ns          -0.242850mV       44.601000uV          -11.098000uV
+3.8384ns          -32.574000uV      27.309000uV          -9.946200uV
+4.0404ns          3.566200uV        14.959000uV          -9.483100uV
+4.2424ns          -5.306100uV       8.251900uV           -8.932600uV
+4.4444ns          -13.750000uV      4.915800uV           -8.381600uV
+4.6465ns          10.940000uV       2.652800uV           -7.820100uV
+4.8485ns          18.035000uV       -0.108180mV          -7.265300uV
+5.0505ns          2.807200uV        0.153640mV           -6.819000uV
+5.2525ns          2.502100uV        -0.230170mV          -6.373400uV
+5.4545ns          3.131600uV        -97.756000uV         -5.936700uV
+5.6566ns          2.983900uV        -12.193000uV         -5.505100uV
+5.8586ns          2.947300uV        25.147000uV          -5.155800uV
+6.0606ns          3.185500uV        13.918000uV          -4.806500uV
+6.2626ns          3.361600uV        13.732000uV          -4.457800uV
+6.4646ns          3.383800uV        15.275000uV          -4.112200uV
+6.6667ns          3.430500uV        14.174000uV          -3.816000uV
+6.8687ns          3.538200uV        13.495000uV          -3.520100uV
+7.0707ns          3.619900uV        13.582000uV          -3.230000uV
+7.2727ns          3.637500uV        13.501000uV          -2.942000uV
+7.4747ns          3.665100uV        13.116000uV          -2.688300uV
+7.6768ns          3.717300uV        12.820000uV          -2.435300uV
+7.8788ns          3.759700uV        12.684000uV          -2.191800uV
+8.0808ns          3.777800uV        12.528000uV          -1.949700uV
+8.2828ns          3.800700uV        12.338000uV          -1.731900uV
+8.4848ns          3.835100uV        12.144000uV          -1.514700uV
+8.6869ns          3.864700uV        11.942000uV          -1.308300uV
+8.8889ns          3.882800uV        11.757000uV          -1.103000uV
+9.0909ns          3.903100uV        11.601000uV          -0.916190uV
+9.2929ns          3.928900uV        11.419000uV          -0.730020uV
+9.4949ns          3.951900uV        11.189000uV          -0.554530uV
+9.6970ns          3.968200uV        10.989000uV          -0.379920uV
+9.8990ns          3.985700uV        10.842000uV          -0.219880uV
+10.1010ns         4.015950uV        10.553500uV          12.615000nV
+10.3030ns         4.039500uV        10.248000uV          0.231740uV
+10.5051ns         4.054400uV        10.116000uV          0.368100uV
+10.7071ns         4.071500uV        9.956800uV           0.504010uV
+10.9091ns         4.087100uV        9.748000uV           0.632480uV
+11.1111ns         4.098800uV        9.573200uV           0.760290uV
+11.3131ns         4.111100uV        9.460300uV           0.877400uV
+11.5152ns         4.125100uV        9.320800uV           0.994070uV
+11.7172ns         4.137800uV        9.133200uV           1.103600uV
+11.9192ns         4.147200uV        8.978700uV           1.212600uV
+12.1212ns         4.157100uV        8.884300uV           1.313000uV
+12.3232ns         4.168500uV        8.764100uV           1.413100uV
+12.5253ns         4.178700uV        8.597200uV           1.506700uV
+12.7273ns         4.186000uV        8.456400uV           1.599900uV
+12.9293ns         4.193900uV        8.362900uV           1.686000uV
+13.1313ns         4.203100uV        8.269500uV           1.771700uV
+13.3333ns         4.211200uV        8.176000uV           1.851800uV
+13.5354ns         4.216800uV        8.065600uV           1.931600uV
+13.7374ns         4.222900uV        7.924500uV           2.005300uV
+13.9394ns         4.230300uV        7.808100uV           2.078800uV
+14.1414ns         4.236700uV        7.736300uV           2.147500uV
+14.3434ns         4.240800uV        7.664500uV           2.215800uV
+14.5455ns         4.245400uV        7.592700uV           2.279000uV
+14.7475ns         4.251200uV        7.503700uV           2.342000uV
+14.9495ns         4.256200uV        7.383500uV           2.400800uV
+15.1515ns         4.259000uV        7.286500uV           2.459400uV
+15.3535ns         4.262400uV        7.231700uV           2.513600uV
+15.5556ns         4.267000uV        7.176900uV           2.567700uV
+15.7576ns         4.270800uV        7.122100uV           2.618100uV
+15.9596ns         4.272600uV        7.049900uV           2.668300uV
+16.1616ns         4.274900uV        6.946400uV           2.714800uV
+16.3636ns         4.278400uV        6.865000uV           2.761200uV
+16.5657ns         4.281200uV        6.823600uV           2.804400uV
+16.7677ns         4.282300uV        6.782200uV           2.847500uV
+16.9697ns         4.283800uV        6.740700uV           2.887400uV
+17.1717ns         4.286400uV        6.682100uV           2.927100uV
+17.3737ns         4.288400uV        6.592100uV           2.964200uV
+17.5758ns         4.288700uV        6.523200uV           3.001200uV
+17.7778ns         4.289500uV        6.492500uV           3.035400uV
+17.9798ns         4.291500uV        6.461700uV           3.069500uV
+18.1818ns         4.292800uV        6.430900uV           3.101400uV
+18.3838ns         4.292600uV        6.383000uV           3.133100uV
+18.5859ns         4.292900uV        6.304200uV           3.162500uV
+18.7879ns         4.294300uV        6.245400uV           3.191700uV
+18.9899ns         4.295100uV        6.223200uV           3.219100uV
+19.1919ns         4.294400uV        6.200900uV           3.246200uV
+19.3939ns         4.294300uV        6.178600uV           3.270600uV
+19.5960ns         4.295200uV        6.139500uV           3.294900uV
+19.7980ns         4.295400uV        6.069700uV           3.319200uV
+20.0000ns         4.294000uV        6.076600uV           3.343600uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468600V
+0.4040ns          3.300900V         3.139100V            3.483300V
+0.6061ns          3.304400V         3.140100V            3.272000V
+0.8081ns          3.179500V         3.145900V            3.030300V
+1.0101ns          3.015400V         3.136300V            2.907000V
+1.2121ns          2.895000V         3.095000V            2.856700V
+1.4141ns          2.821600V         2.995500V            2.837500V
+1.6162ns          2.781500V         2.910100V            2.829200V
+1.8182ns          2.760300V         2.834600V            2.826700V
+2.0202ns          2.751400V         2.769700V            2.825700V
+2.2222ns          2.745500V         2.722000V            2.826100V
+2.4242ns          2.743500V         2.688600V            2.830900V
+2.6263ns          2.743000V         2.667400V            2.878100V
+2.8283ns          2.742800V         2.654200V            2.895900V
+3.0303ns          2.742900V         2.645000V            2.900000V
+3.2323ns          2.743200V         2.639400V            2.902500V
+3.4343ns          2.756300V         2.636600V            2.904500V
+3.6364ns          2.776700V         2.635200V            2.906500V
+3.8384ns          2.790100V         2.634000V            2.908200V
+4.0404ns          2.792600V         2.633800V            2.909800V
+4.2424ns          2.793100V         2.633700V            2.911300V
+4.4444ns          2.793600V         2.633900V            2.912900V
+4.6465ns          2.793500V         2.634100V            2.914200V
+4.8485ns          2.793500V         2.636300V            2.915600V
+5.0505ns          2.793500V         2.635700V            2.916900V
+5.2525ns          2.793500V         2.642300V            2.918100V
+5.4545ns          2.793500V         2.652700V            2.919300V
+5.6566ns          2.793400V         2.656300V            2.920400V
+5.8586ns          2.793400V         2.655900V            2.921400V
+6.0606ns          2.793300V         2.655100V            2.922500V
+6.2626ns          2.793200V         2.654600V            2.923500V
+6.4646ns          2.793100V         2.654000V            2.924400V
+6.6667ns          2.793000V         2.653400V            2.925300V
+6.8687ns          2.792900V         2.652800V            2.926200V
+7.0707ns          2.792800V         2.652200V            2.927100V
+7.2727ns          2.792700V         2.651700V            2.928000V
+7.4747ns          2.792600V         2.651100V            2.928900V
+7.6768ns          2.792500V         2.650500V            2.929700V
+7.8788ns          2.792300V         2.650000V            2.930600V
+8.0808ns          2.792200V         2.649500V            2.931500V
+8.2828ns          2.792100V         2.648900V            2.932300V
+8.4848ns          2.791900V         2.648400V            2.933200V
+8.6869ns          2.791800V         2.647900V            2.934100V
+8.8889ns          2.791600V         2.647400V            2.935000V
+9.0909ns          2.791500V         2.647000V            2.935800V
+9.2929ns          2.791300V         2.646500V            2.936600V
+9.4949ns          2.791200V         2.646000V            2.937400V
+9.6970ns          2.791000V         2.645600V            2.938200V
+9.8990ns          2.790900V         2.645100V            2.939000V
+10.1010ns         2.790650V         2.644500V            2.940050V
+10.3030ns         2.790400V         2.643900V            2.941100V
+10.5051ns         2.790200V         2.643500V            2.941700V
+10.7071ns         2.790100V         2.643100V            2.942400V
+10.9091ns         2.789900V         2.642700V            2.943000V
+11.1111ns         2.789700V         2.642400V            2.943600V
+11.3131ns         2.789600V         2.642000V            2.944100V
+11.5152ns         2.789400V         2.641600V            2.944700V
+11.7172ns         2.789200V         2.641300V            2.945200V
+11.9192ns         2.789100V         2.641000V            2.945700V
+12.1212ns         2.788900V         2.640600V            2.946200V
+12.3232ns         2.788700V         2.640300V            2.946700V
+12.5253ns         2.788600V         2.640000V            2.947100V
+12.7273ns         2.788400V         2.639700V            2.947600V
+12.9293ns         2.788200V         2.639400V            2.948000V
+13.1313ns         2.788000V         2.639100V            2.948400V
+13.3333ns         2.787900V         2.638900V            2.948800V
+13.5354ns         2.787700V         2.638600V            2.949200V
+13.7374ns         2.787500V         2.638300V            2.949600V
+13.9394ns         2.787400V         2.638000V            2.949900V
+14.1414ns         2.787200V         2.637800V            2.950300V
+14.3434ns         2.787000V         2.637500V            2.950600V
+14.5455ns         2.786900V         2.637300V            2.950900V
+14.7475ns         2.786700V         2.637100V            2.951200V
+14.9495ns         2.786500V         2.636800V            2.951500V
+15.1515ns         2.786400V         2.636600V            2.951800V
+15.3535ns         2.786200V         2.636400V            2.952100V
+15.5556ns         2.786100V         2.636100V            2.952400V
+15.7576ns         2.785900V         2.635900V            2.952600V
+15.9596ns         2.785800V         2.635700V            2.952900V
+16.1616ns         2.785600V         2.635500V            2.953100V
+16.3636ns         2.785500V         2.635300V            2.953400V
+16.5657ns         2.785300V         2.635100V            2.953600V
+16.7677ns         2.785200V         2.634900V            2.953800V
+16.9697ns         2.785000V         2.634700V            2.954000V
+17.1717ns         2.784900V         2.634500V            2.954200V
+17.3737ns         2.784800V         2.634300V            2.954400V
+17.5758ns         2.784600V         2.634200V            2.954600V
+17.7778ns         2.784500V         2.634000V            2.954800V
+17.9798ns         2.784400V         2.633800V            2.955000V
+18.1818ns         2.784300V         2.633600V            2.955100V
+18.3838ns         2.784200V         2.633500V            2.955300V
+18.5859ns         2.784100V         2.633300V            2.955500V
+18.7879ns         2.784000V         2.633100V            2.955600V
+18.9899ns         2.783900V         2.633000V            2.955800V
+19.1919ns         2.783800V         2.632800V            2.955900V
+19.3939ns         2.783700V         2.632700V            2.956100V
+19.5960ns         2.783600V         2.632500V            2.956200V
+19.7980ns         2.783600V         2.632400V            2.956300V
+20.0000ns         2.783500V         2.632200V            2.956500V
+|  
+| End [Model] lvc330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330s140aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -50.584550mA      -43.999960mA         -54.623576mA
+  -3.20    -50.404450mA      -43.837800mA         -54.427552mA
+  -3.10    -50.224350mA      -43.675640mA         -54.231528mA
+  -3.00    -50.044250mA      -43.513480mA         -54.035504mA
+  -2.90    -49.864150mA      -43.351320mA         -53.839480mA
+  -2.80    -49.684050mA      -43.189160mA         -53.643456mA
+  -2.70    -49.503950mA      -43.027000mA         -53.447432mA
+  -2.60    -49.323850mA      -42.864840mA         -53.251408mA
+  -2.50    -49.143750mA      -42.702680mA         -53.055384mA
+  -2.40    -48.963650mA      -42.540520mA         -52.859360mA
+  -2.30    -48.783550mA      -42.378360mA         -52.663336mA
+  -2.20    -48.603450mA      -42.216200mA         -52.467312mA
+  -2.10    -48.423350mA      -42.054040mA         -52.271288mA
+  -2.00    -48.243250mA      -41.891880mA         -52.075264mA
+  -1.90    -48.063150mA      -41.729720mA         -51.879240mA
+  -1.80    -47.883050mA      -41.567560mA         -51.683216mA
+  -1.70    -47.702950mA      -41.405400mA         -51.487192mA
+  -1.60    -47.522850mA      -41.243240mA         -51.291168mA
+  -1.50    -47.342750mA      -41.081080mA         -51.095144mA
+  -1.40    -47.162650mA      -40.960000mA         -50.899120mA
+  -1.30    -46.982550mA      -40.310000mA         -50.703096mA
+  -1.20    -46.802450mA      -39.409000mA         -50.507072mA
+  -1.10    -46.622350mA      -38.410000mA         -50.311048mA
+  -1.00    -46.442250mA      -37.323000mA         -50.115024mA
+  -0.90    -46.262150mA      -36.180000mA         -49.919000mA
+  -0.80    -46.082050mA      -35.076000mA         -49.327000mA
+  -0.70    -45.748900mA      -34.427000mA         -47.994000mA
+  -0.60    -42.249200mA      -34.203200mA         -45.776900mA
+  -0.50    -36.169470mA      -30.752860mA         -40.603750mA
+  -0.40    -29.014551mA      -24.879886mA         -32.919898mA
+  -0.30    -21.670346mA      -18.677585mA         -24.687602mA
+  -0.20    -14.338705mA      -12.435585mA         -16.367748mA
+  -0.10    -7.093292mA       -6.195266mA          -8.095791mA
+  0.00    27.190000nA       25.680000nA          31.680000nA
+  0.10    6.587285mA        5.878497mA           7.387890mA
+  0.20    12.314175mA       11.156186mA          13.529180mA
+  0.30    17.106166mA       15.766175mA          18.285171mA
+  0.40    20.907156mA       19.661164mA          21.673162mA
+  0.50    23.747146mA       22.813153mA          23.968152mA
+  0.60    25.783136mA       25.234142mA          25.549143mA
+  0.70    27.212126mA       27.008131mA          26.699134mA
+  0.80    28.206116mA       28.280120mA          27.588124mA
+  0.90    28.917106mA       29.203109mA          28.308115mA
+  1.00    29.453095mA       29.892098mA          28.908106mA
+  1.10    29.875084mA       30.426087mA          29.398096mA
+  1.20    30.221074mA       30.854076mA          29.770086mA
+  1.30    30.513063mA       31.208065mA          30.064075mA
+  1.40    30.767053mA       31.507054mA          30.315065mA
+  1.50    30.993042mA       31.766043mA          30.542055mA
+  1.60    31.203032mA       31.995032mA          30.762044mA
+  1.70    31.414021mA       32.204021mA          30.983034mA
+  1.80    31.648011mA       32.407010mA          31.201024mA
+  1.90    31.903000mA       32.633999mA          31.408013mA
+  2.00    32.157989mA       32.912988mA          31.601003mA
+  2.10    32.398979mA       33.235977mA          31.780993mA
+  2.20    32.620968mA       33.562966mA          31.951982mA
+  2.30    32.826958mA       33.870954mA          32.113972mA
+  2.40    33.017947mA       34.153943mA          32.268961mA
+  2.50    33.197936mA       34.411932mA          32.419951mA
+  2.60    33.368926mA       34.647921mA          32.567941mA
+  2.70    33.532915mA       34.866910mA          32.714930mA
+  2.80    33.693904mA       35.070899mA          32.864920mA
+  2.90    33.851894mA       35.264888mA          33.017909mA
+  3.00    34.012883mA       35.450877mA          33.177899mA
+  3.10    34.176872mA       35.632864mA          33.347889mA
+  3.20    34.349862mA       35.813747mA          33.531878mA
+  3.30    34.531848mA       35.996379mA          33.730868mA
+  3.40    34.729725mA       36.157497mA          33.951857mA
+  3.50    34.942986mA       36.297102mA          34.196843mA
+  3.60    35.117958mA       36.436708mA          34.470599mA
+  3.70    35.251602mA       36.576313mA          34.772212mA
+  3.80    35.385246mA       36.715919mA          34.904053mA
+  3.90    35.518890mA       36.855525mA          35.035893mA
+  4.00    35.652534mA       36.995130mA          35.167734mA
+  4.10    35.786178mA       37.134736mA          35.299574mA
+  4.20    35.919822mA       37.274341mA          35.431414mA
+  4.30    36.053466mA       37.413947mA          35.563255mA
+  4.40    36.187110mA       37.553553mA          35.695095mA
+  4.50    36.320754mA       37.693158mA          35.826936mA
+  4.60    36.454398mA       37.832764mA          35.958776mA
+  4.70    36.588042mA       37.972369mA          36.090616mA
+  4.80    36.721686mA       38.111975mA          36.222457mA
+  4.90    36.855330mA       38.251581mA          36.354297mA
+  5.00    36.988974mA       38.391186mA          36.486138mA
+  5.10    37.122618mA       38.530792mA          36.617978mA
+  5.20    37.256262mA       38.670397mA          36.749818mA
+  5.30    37.389906mA       38.810003mA          36.881659mA
+  5.40    37.523550mA       38.949609mA          37.013499mA
+  5.50    37.657194mA       39.089214mA          37.145340mA
+  5.60    37.790838mA       39.228820mA          37.277180mA
+  5.70    37.924482mA       39.368425mA          37.409020mA
+  5.80    38.058126mA       39.508031mA          37.540861mA
+  5.90    38.191770mA       39.647637mA          37.672701mA
+  6.00    38.325414mA       39.787242mA          37.804542mA
+  6.10    38.459058mA       39.926848mA          37.936382mA
+  6.20    38.592702mA       40.066453mA          38.068222mA
+  6.30    38.726346mA       40.206059mA          38.200063mA
+  6.40    38.859990mA       40.345665mA          38.331903mA
+  6.50    38.993634mA       40.485270mA          38.463744mA
+  6.60    39.127278mA       40.624876mA          38.595584mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    66.669757mA       87.094613mA          92.797733mA
+  -3.20    66.440741mA       86.767866mA          92.515330mA
+  -3.10    66.211726mA       86.441119mA          92.232928mA
+  -3.00    65.982711mA       86.114372mA          91.950525mA
+  -2.90    65.753695mA       85.787625mA          91.668122mA
+  -2.80    65.524680mA       85.460878mA          91.385720mA
+  -2.70    65.295664mA       85.134131mA          91.103317mA
+  -2.60    65.066649mA       84.807384mA          90.820915mA
+  -2.50    64.837633mA       84.480636mA          90.538512mA
+  -2.40    64.608618mA       84.153889mA          90.256109mA
+  -2.30    64.379602mA       83.827142mA          89.973707mA
+  -2.20    64.150587mA       83.500395mA          89.691304mA
+  -2.10    63.921571mA       83.173648mA          89.408901mA
+  -2.00    63.692556mA       82.846901mA          89.126499mA
+  -1.90    63.463540mA       82.520154mA          88.844096mA
+  -1.80    63.234525mA       82.323794mA          88.561693mA
+  -1.70    63.005509mA       81.008819mA          88.279291mA
+  -1.60    62.776494mA       78.640845mA          87.996888mA
+  -1.50    62.547479mA       75.568869mA          87.714485mA
+  -1.40    62.318463mA       71.978893mA          87.432083mA
+  -1.30    62.089448mA       67.983917mA          87.149680mA
+  -1.20    61.860432mA       63.658940mA          86.867278mA
+  -1.10    61.631417mA       59.058962mA          86.584875mA
+  -1.00    61.402401mA       54.225984mA          80.067686mA
+  -0.90    61.173386mA       49.192006mA          71.275712mA
+  -0.80    54.621889mA       45.212027mA          61.996736mA
+  -0.70    47.050911mA       41.794048mA          52.900760mA
+  -0.60    39.442932mA       35.550069mA          44.185783mA
+  -0.50    32.215954mA       29.164089mA          36.006805mA
+  -0.40    25.419974mA       23.007107mA          28.393828mA
+  -0.30    17.101700mA       15.824500mA          19.002300mA
+  -0.20    12.464986mA       11.277815mA          13.918820mA
+  -0.10    6.164125mA        5.580948mA           6.877969mA
+  0.00    -18.490000nA      -17.070000nA         -20.440000nA
+  0.10    -5.904938mA       -5.394928mA          -6.530140mA
+  0.20    -11.454128mA      -10.553116mA         -12.558129mA
+  0.30    -16.640117mA      -15.473105mA         -18.069119mA
+  0.40    -21.457106mA      -20.150094mA         -23.046108mA
+  0.50    -25.896096mA      -24.583083mA         -27.475098mA
+  0.60    -29.949085mA      -28.768072mA         -31.336087mA
+  0.70    -33.609074mA      -32.702061mA         -34.612077mA
+  0.80    -36.868064mA      -36.383050mA         -37.284067mA
+  0.90    -39.717053mA      -39.806039mA         -39.346056mA
+  1.00    -42.147042mA      -42.970028mA         -40.889046mA
+  1.10    -44.149032mA      -45.870017mA         -42.089035mA
+  1.20    -45.748021mA      -48.504006mA         -43.060025mA
+  1.30    -47.028011mA      -50.866995mA         -43.869015mA
+  1.40    -48.080000mA      -52.957984mA         -44.561004mA
+  1.50    -48.964989mA      -54.770973mA         -45.164994mA
+  1.60    -49.722979mA      -56.304962mA         -45.700984mA
+  1.70    -50.383968mA      -57.595951mA         -46.184973mA
+  1.80    -50.967958mA      -58.692940mA         -46.625963mA
+  1.90    -51.489947mA      -59.638929mA         -47.033952mA
+  2.00    -51.962937mA      -60.463918mA         -47.412942mA
+  2.10    -52.394926mA      -61.192907mA         -47.768932mA
+  2.20    -52.791916mA      -61.842896mA         -48.104921mA
+  2.30    -53.159905mA      -62.426885mA         -48.424911mA
+  2.40    -53.504894mA      -62.956874mA         -48.730901mA
+  2.50    -53.827884mA      -63.439863mA         -49.025891mA
+  2.60    -54.132874mA      -63.884852mA         -49.310882mA
+  2.70    -54.422864mA      -64.295841mA         -49.587873mA
+  2.80    -54.700854mA      -64.676830mA         -49.859863mA
+  2.90    -54.966844mA      -65.033819mA         -50.128854mA
+  3.00    -55.224834mA      -65.367808mA         -50.397845mA
+  3.10    -55.477825mA      -65.682796mA         -50.669835mA
+  3.20    -55.727815mA      -65.980780mA         -50.947826mA
+  3.30    -55.978806mA      -66.265706mA         -51.235817mA
+  3.40    -56.233792mA      -66.536956mA         -51.539808mA
+  3.50    -56.497705mA      -66.792873mA         -51.862798mA
+  3.60    -56.774346mA      -66.928560mA         -52.210786mA
+  3.70    -57.054551mA      -67.195337mA         -52.589679mA
+  3.80    -57.194470mA      -67.462113mA         -53.001555mA
+  3.90    -57.422477mA      -67.728890mA         -53.392977mA
+  4.00    -57.650484mA      -67.995667mA         -53.537857mA
+  4.10    -57.878491mA      -68.262444mA         -53.750052mA
+  4.20    -58.106498mA      -68.529220mA         -53.962246mA
+  4.30    -58.334506mA      -68.795997mA         -54.174441mA
+  4.40    -58.562513mA      -69.062774mA         -54.386636mA
+  4.50    -58.790520mA      -69.329550mA         -54.598830mA
+  4.60    -59.018527mA      -69.596327mA         -54.811025mA
+  4.70    -59.246534mA      -69.863104mA         -55.023219mA
+  4.80    -59.474541mA      -70.129881mA         -55.235414mA
+  4.90    -59.702548mA      -70.396657mA         -55.447608mA
+  5.00    -59.930555mA      -70.663434mA         -55.659803mA
+  5.10    -60.158563mA      -70.930211mA         -55.871997mA
+  5.20    -60.386570mA      -71.196988mA         -56.084192mA
+  5.30    -60.614577mA      -71.463764mA         -56.296387mA
+  5.40    -60.842584mA      -71.730541mA         -56.508581mA
+  5.50    -61.070591mA      -71.997318mA         -56.720776mA
+  5.60    -61.298598mA      -72.264094mA         -56.932970mA
+  5.70    -61.526605mA      -72.530871mA         -57.145165mA
+  5.80    -61.754612mA      -72.797648mA         -57.357359mA
+  5.90    -61.982620mA      -73.064425mA         -57.569554mA
+  6.00    -62.210627mA      -73.331201mA         -57.781748mA
+  6.10    -62.438634mA      -73.597978mA         -57.993943mA
+  6.20    -62.666641mA      -73.864755mA         -58.206138mA
+  6.30    -62.894648mA      -74.131531mA         -58.418332mA
+  6.40    -63.122655mA      -74.398308mA         -58.630527mA
+  6.50    -63.350662mA      -74.665085mA         -58.842721mA
+  6.55    -63.464666mA      -74.798473mA         -58.948819mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.195000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.064900nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  1.322279/1.397370n  1.285979/1.830494n  1.312139/1.075717n
+dV/dt_f  0.909660/0.907875n  0.826020/1.758264n  1.011840/0.527820n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.726300V         1.546200V            1.899700V
+0.2020ns          1.726800V         1.546200V            1.904800V
+0.4040ns          1.737400V         1.550000V            2.017500V
+0.6061ns          1.942100V         1.551600V            2.912500V
+0.8081ns          2.634400V         1.596800V            3.407200V
+1.0101ns          3.187200V         1.875300V            3.460800V
+1.2121ns          3.279100V         2.359700V            3.465800V
+1.4141ns          3.292700V         2.847800V            3.467100V
+1.6162ns          3.295600V         3.089900V            3.467600V
+1.8182ns          3.296700V         3.123600V            3.467900V
+2.0202ns          3.297300V         3.130900V            3.468200V
+2.2222ns          3.297500V         3.134300V            3.468700V
+2.4242ns          3.297700V         3.135700V            3.468900V
+2.6263ns          3.297900V         3.136600V            3.470800V
+2.8283ns          3.298100V         3.137000V            3.470300V
+3.0303ns          3.298400V         3.137300V            3.470100V
+3.2323ns          3.299000V         3.137500V            3.470000V
+3.4343ns          3.300800V         3.137600V            3.470000V
+3.6364ns          3.300800V         3.137800V            3.470000V
+3.8384ns          3.300300V         3.137900V            3.469900V
+4.0404ns          3.300200V         3.138000V            3.469900V
+4.2424ns          3.300000V         3.138200V            3.469900V
+4.4444ns          3.300000V         3.138400V            3.469900V
+4.6465ns          3.300000V         3.138600V            3.469900V
+4.8485ns          3.300000V         3.138900V            3.469900V
+5.0505ns          3.300000V         3.139200V            3.469900V
+5.2525ns          3.300000V         3.140400V            3.469900V
+5.4545ns          3.299900V         3.140300V            3.469900V
+5.6566ns          3.299900V         3.140100V            3.469900V
+5.8586ns          3.299900V         3.140100V            3.470000V
+6.0606ns          3.299900V         3.140000V            3.470000V
+6.2626ns          3.299900V         3.140000V            3.470000V
+6.4646ns          3.299900V         3.140000V            3.470000V
+6.6667ns          3.299900V         3.140000V            3.470000V
+6.8687ns          3.299900V         3.140000V            3.470000V
+7.0707ns          3.299900V         3.140000V            3.470000V
+7.2727ns          3.299900V         3.140000V            3.470000V
+7.4747ns          3.299900V         3.140000V            3.470000V
+7.6768ns          3.299900V         3.140000V            3.470000V
+7.8788ns          3.300000V         3.140000V            3.470000V
+8.0808ns          3.300000V         3.140000V            3.470000V
+8.2828ns          3.300000V         3.140000V            3.470000V
+8.4848ns          3.300000V         3.140000V            3.470000V
+8.6869ns          3.300000V         3.139900V            3.470000V
+8.8889ns          3.300000V         3.139900V            3.470000V
+9.0909ns          3.300000V         3.139900V            3.470000V
+9.2929ns          3.300000V         3.139900V            3.470000V
+9.4949ns          3.300000V         3.139900V            3.470000V
+9.6970ns          3.300000V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.140000V            3.470000V
+11.7172ns         3.300000V         3.140000V            3.470000V
+11.9192ns         3.300000V         3.140000V            3.470000V
+12.1212ns         3.300000V         3.140000V            3.470000V
+12.3232ns         3.300000V         3.140000V            3.470000V
+12.5253ns         3.300000V         3.140000V            3.470000V
+12.7273ns         3.300000V         3.140000V            3.470000V
+12.9293ns         3.300000V         3.140000V            3.470000V
+13.1313ns         3.300000V         3.140000V            3.470000V
+13.3333ns         3.300000V         3.140000V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.860000uV        2.247100uV           1.679700uV
+0.2020ns          -0.129790mV       4.669400uV           -0.320790mV
+0.4040ns          -1.716600mV       0.272540uV           -4.681500mV
+0.6061ns          1.221000mV        -0.447820mV          0.186680V
+0.8081ns          0.107030V         -5.196400mV          0.507800V
+1.0101ns          0.361420V         7.872900mV           0.782610V
+1.2121ns          0.574160V         63.086000mV          1.032400V
+1.4141ns          0.778920V         0.229510V            1.269500V
+1.6162ns          0.975680V         0.410340V            1.497800V
+1.8182ns          1.166800V         0.562960V            1.717900V
+2.0202ns          1.353800V         0.714380V            1.916400V
+2.2222ns          1.533600V         0.865340V            2.085800V
+2.4242ns          1.705400V         1.012700V            2.201900V
+2.6263ns          1.865600V         1.157800V            2.206500V
+2.8283ns          2.002800V         1.297100V            2.148000V
+3.0303ns          2.119800V         1.433900V            2.116300V
+3.2323ns          2.194200V         1.564200V            2.100900V
+3.4343ns          2.242600V         1.684200V            2.095200V
+3.6364ns          2.206600V         1.795900V            2.092100V
+3.8384ns          2.175600V         1.885300V            2.093400V
+4.0404ns          2.158100V         1.961700V            2.097900V
+4.2424ns          2.149800V         2.017100V            2.104000V
+4.4444ns          2.145000V         2.058100V            2.111400V
+4.6465ns          2.142500V         2.090000V            2.119600V
+4.8485ns          2.141700V         2.113000V            2.127800V
+5.0505ns          2.141900V         2.137500V            2.135200V
+5.2525ns          2.142800V         2.134100V            2.141000V
+5.4545ns          2.144700V         2.126700V            2.146000V
+5.6566ns          2.148900V         2.121500V            2.150700V
+5.8586ns          2.153600V         2.118100V            2.154700V
+6.0606ns          2.158200V         2.116400V            2.158400V
+6.2626ns          2.162900V         2.115100V            2.161600V
+6.4646ns          2.167200V         2.114600V            2.164500V
+6.6667ns          2.171000V         2.114400V            2.167000V
+6.8687ns          2.174500V         2.114500V            2.169300V
+7.0707ns          2.177500V         2.114600V            2.171300V
+7.2727ns          2.180300V         2.114800V            2.173100V
+7.4747ns          2.182800V         2.115200V            2.174700V
+7.6768ns          2.185100V         2.115600V            2.176100V
+7.8788ns          2.187100V         2.116000V            2.177400V
+8.0808ns          2.188900V         2.116500V            2.178500V
+8.2828ns          2.190500V         2.117100V            2.179500V
+8.4848ns          2.191900V         2.117700V            2.180300V
+8.6869ns          2.193200V         2.118500V            2.181100V
+8.8889ns          2.194300V         2.119600V            2.181800V
+9.0909ns          2.195300V         2.121000V            2.182400V
+9.2929ns          2.196300V         2.122600V            2.182900V
+9.4949ns          2.197100V         2.124200V            2.183400V
+9.6970ns          2.197800V         2.125900V            2.183800V
+9.8990ns          2.198500V         2.127400V            2.184200V
+10.1010ns         2.199350V         2.129450V            2.184650V
+10.3030ns         2.200000V         2.131300V            2.185000V
+10.5051ns         2.200500V         2.132300V            2.185200V
+10.7071ns         2.200800V         2.133300V            2.185400V
+10.9091ns         2.201200V         2.134200V            2.185600V
+11.1111ns         2.201500V         2.135100V            2.185800V
+11.3131ns         2.201700V         2.135800V            2.185900V
+11.5152ns         2.202000V         2.136500V            2.186000V
+11.7172ns         2.202200V         2.137100V            2.186100V
+11.9192ns         2.202400V         2.137700V            2.186200V
+12.1212ns         2.202500V         2.138200V            2.186300V
+12.3232ns         2.202700V         2.138700V            2.186400V
+12.5253ns         2.202800V         2.139100V            2.186400V
+12.7273ns         2.202900V         2.139500V            2.186500V
+12.9293ns         2.203000V         2.139900V            2.186500V
+13.1313ns         2.203100V         2.140200V            2.186600V
+13.3333ns         2.203200V         2.140500V            2.186600V
+13.5354ns         2.203300V         2.140700V            2.186600V
+13.7374ns         2.203300V         2.141000V            2.186700V
+13.9394ns         2.203400V         2.141200V            2.186700V
+14.1414ns         2.203400V         2.141400V            2.186700V
+14.3434ns         2.203500V         2.141600V            2.186700V
+14.5455ns         2.203500V         2.141800V            2.186700V
+14.7475ns         2.203600V         2.141900V            2.186800V
+14.9495ns         2.203600V         2.142000V            2.186800V
+15.1515ns         2.203600V         2.142200V            2.186800V
+15.3535ns         2.203600V         2.142300V            2.186800V
+15.5556ns         2.203700V         2.142400V            2.186800V
+15.7576ns         2.203700V         2.142500V            2.186800V
+15.9596ns         2.203700V         2.142600V            2.186800V
+16.1616ns         2.203700V         2.142600V            2.186800V
+16.3636ns         2.203700V         2.142700V            2.186800V
+16.5657ns         2.203700V         2.142800V            2.186900V
+16.7677ns         2.203700V         2.142800V            2.186900V
+16.9697ns         2.203800V         2.142900V            2.186900V
+17.1717ns         2.203800V         2.142900V            2.186900V
+17.3737ns         2.203800V         2.143000V            2.186900V
+17.5758ns         2.203800V         2.143000V            2.186900V
+17.7778ns         2.203800V         2.143000V            2.186900V
+17.9798ns         2.203800V         2.143100V            2.186900V
+18.1818ns         2.203800V         2.143100V            2.186900V
+18.3838ns         2.203800V         2.143100V            2.186900V
+18.5859ns         2.203800V         2.143100V            2.186900V
+18.7879ns         2.203800V         2.143200V            2.186900V
+18.9899ns         2.203800V         2.143200V            2.186900V
+19.1919ns         2.203800V         2.143200V            2.186900V
+19.3939ns         2.203800V         2.143200V            2.186900V
+19.5960ns         2.203800V         2.143200V            2.186900V
+19.7980ns         2.203800V         2.143200V            2.186900V
+20.0000ns         2.203800V         2.143300V            2.186900V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.203900V         2.143400V            2.187000V
+0.2020ns          2.204000V         2.143400V            2.193500V
+0.4040ns          2.222800V         2.147700V            2.032600V
+0.6061ns          2.041300V         2.152800V            1.329800V
+0.8081ns          1.561500V         2.146100V            0.689440V
+1.0101ns          1.011100V         2.097000V            0.210050V
+1.2121ns          0.595520V         1.931200V            16.668000mV
+1.4141ns          0.291310V         1.573700V            3.287100mV
+1.6162ns          80.606000mV       1.160800V            1.540100mV
+1.8182ns          13.976000mV       0.816650V            0.795800mV
+2.0202ns          3.438200mV        0.556260V            0.249100mV
+2.2222ns          2.674800mV        0.354310V            0.141130mV
+2.4242ns          1.686600mV        0.200190V            -0.655480mV
+2.6263ns          0.612530mV        87.872000mV          -2.068600uV
+2.8283ns          0.572400mV        33.061000mV          -22.091000uV
+3.0303ns          0.375060mV        11.834000mV          -24.867000uV
+3.2323ns          0.241800mV        4.814600mV           -26.956000uV
+3.4343ns          -0.105830mV       3.354200mV           -15.925000uV
+3.6364ns          -75.323000uV      2.452700mV           -21.116000uV
+3.8384ns          4.162200uV        1.747000mV           -21.198000uV
+4.0404ns          -9.814400uV       1.397500mV           -20.735000uV
+4.2424ns          -8.341900uV       1.108100mV           -20.330000uV
+4.4444ns          -6.866100uV       0.872660mV           -19.920000uV
+4.6465ns          -5.387100uV       0.692450mV           -19.527000uV
+4.8485ns          -8.072400uV       0.289700mV           -19.137000uV
+5.0505ns          -7.958300uV       0.244360mV           -18.776000uV
+5.2525ns          -7.769600uV       -77.493000uV         -18.423000uV
+5.4545ns          -7.625700uV       -0.105340mV          -18.079000uV
+5.6566ns          -7.474800uV       -54.805000uV         -17.737000uV
+5.8586ns          -7.290100uV       10.015000uV          -17.420000uV
+6.0606ns          -7.095100uV       31.098000uV          -17.110000uV
+6.2626ns          -6.941900uV       27.849000uV          -16.798000uV
+6.4646ns          -6.801300uV       26.843000uV          -16.485000uV
+6.6667ns          -6.644700uV       25.837000uV          -16.193000uV
+6.8687ns          -6.483200uV       24.821000uV          -15.906000uV
+7.0707ns          -6.356800uV       23.930000uV          -15.617000uV
+7.2727ns          -6.241000uV       23.931000uV          -15.328000uV
+7.4747ns          -6.109700uV       23.867000uV          -15.057000uV
+7.6768ns          -5.973800uV       23.333000uV          -14.790000uV
+7.8788ns          -5.859500uV       22.861000uV          -14.523000uV
+8.0808ns          -5.751700uV       22.831000uV          -14.256000uV
+8.2828ns          -5.632300uV       22.765000uV          -14.004000uV
+8.4848ns          -5.509400uV       22.433000uV          -13.756000uV
+8.6869ns          -5.401200uV       22.127000uV          -13.508000uV
+8.8889ns          -5.297500uV       22.000000uV          -13.261000uV
+9.0909ns          -5.186800uV       21.856000uV          -13.026000uV
+9.2929ns          -5.073900uV       21.583000uV          -12.795000uV
+9.4949ns          -4.971400uV       21.321000uV          -12.566000uV
+9.6970ns          -4.872100uV       21.138000uV          -12.337000uV
+9.8990ns          -4.768700uV       20.948000uV          -12.119000uV
+10.1010ns         -4.615700uV       20.580000uV          -11.796500uV
+10.3030ns         -4.472500uV       20.255000uV          -11.478000uV
+10.5051ns         -4.375700uV       20.048000uV          -11.275000uV
+10.7071ns         -4.278400uV       19.819000uV          -11.074000uV
+10.9091ns         -4.186900uV       19.593000uV          -10.876000uV
+11.1111ns         -4.097100uV       19.385000uV          -10.679000uV
+11.3131ns         -4.006500uV       19.177000uV          -10.490000uV
+11.5152ns         -3.915700uV       18.963000uV          -10.303000uV
+11.7172ns         -3.829500uV       18.751000uV          -10.119000uV
+11.9192ns         -3.744700uV       18.550000uV          -9.935200uV
+12.1212ns         -3.659800uV       18.348000uV          -9.758900uV
+12.3232ns         -3.575000uV       18.147000uV          -9.584400uV
+12.5253ns         -3.493900uV       17.946000uV          -9.412900uV
+12.7273ns         -3.413900uV       17.750000uV          -9.242200uV
+12.9293ns         -3.334400uV       17.555000uV          -9.077700uV
+13.1313ns         -3.255000uV       17.367000uV          -8.914800uV
+13.3333ns         -3.178700uV       17.180000uV          -8.754900uV
+13.5354ns         -3.103400uV       16.992000uV          -8.595700uV
+13.7374ns         -3.028800uV       16.805000uV          -8.442200uV
+13.9394ns         -2.954500uV       16.625000uV          -8.290100uV
+14.1414ns         -2.882800uV       16.446000uV          -8.140800uV
+14.3434ns         -2.811900uV       16.271000uV          -7.992300uV
+14.5455ns         -2.741900uV       16.096000uV          -7.848800uV
+14.7475ns         -2.672100uV       15.921000uV          -7.706700uV
+14.9495ns         -2.604700uV       15.747000uV          -7.567200uV
+15.1515ns         -2.538000uV       15.582000uV          -7.428400uV
+15.3535ns         -2.472300uV       15.417000uV          -7.294300uV
+15.5556ns         -2.406900uV       15.254000uV          -7.161400uV
+15.7576ns         -2.343500uV       15.091000uV          -7.031000uV
+15.9596ns         -2.280700uV       14.928000uV          -6.901100uV
+16.1616ns         -2.219000uV       14.767000uV          -6.775700uV
+16.3636ns         -2.157500uV       14.614000uV          -6.651300uV
+16.5657ns         -2.097900uV       14.461000uV          -6.529200uV
+16.7677ns         -2.038900uV       14.310000uV          -6.407700uV
+16.9697ns         -1.980900uV       14.158000uV          -6.290200uV
+17.1717ns         -1.923100uV       14.007000uV          -6.173700uV
+17.3737ns         -1.867100uV       13.856000uV          -6.059300uV
+17.5758ns         -1.811500uV       13.715000uV          -5.945500uV
+17.7778ns         -1.756900uV       13.574000uV          -5.835400uV
+17.9798ns         -1.702700uV       13.433000uV          -5.726200uV
+18.1818ns         -1.649900uV       13.292000uV          -5.619000uV
+18.3838ns         -1.597600uV       13.151000uV          -5.512200uV
+18.5859ns         -1.546300uV       13.011000uV          -5.409000uV
+18.7879ns         -1.495300uV       12.881000uV          -5.306700uV
+18.9899ns         -1.445600uV       12.750000uV          -5.206100uV
+19.1919ns         -1.396400uV       12.619000uV          -5.105900uV
+19.3939ns         -1.348100uV       12.488000uV          -5.009100uV
+19.5960ns         -1.300200uV       12.357000uV          -4.913100uV
+19.7980ns         -1.253400uV       12.227000uV          -4.818400uV
+20.0000ns         -1.206900uV       12.109000uV          -4.724200uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468500V
+0.4040ns          3.300800V         3.139500V            3.480800V
+0.6061ns          3.307700V         3.140100V            3.421400V
+0.8081ns          3.288700V         3.143500V            3.119600V
+1.0101ns          3.205000V         3.143800V            2.661400V
+1.2121ns          3.025100V         3.145800V            2.287000V
+1.4141ns          2.763000V         3.126600V            2.008100V
+1.6162ns          2.525800V         3.091800V            1.804300V
+1.8182ns          2.335100V         3.031500V            1.669500V
+2.0202ns          2.176400V         2.950000V            1.556300V
+2.2222ns          2.038500V         2.833800V            1.492000V
+2.4242ns          1.931900V         2.695300V            1.454000V
+2.6263ns          1.842100V         2.569900V            1.511700V
+2.8283ns          1.775200V         2.465400V            1.518000V
+3.0303ns          1.725800V         2.375800V            1.523200V
+3.2323ns          1.686600V         2.288200V            1.528200V
+3.4343ns          1.685200V         2.209700V            1.533400V
+3.6364ns          1.704000V         2.138800V            1.538300V
+3.8384ns          1.711300V         2.070500V            1.543000V
+4.0404ns          1.712500V         2.009900V            1.547600V
+4.2424ns          1.714100V         1.956200V            1.552200V
+4.4444ns          1.715500V         1.910000V            1.556700V
+4.6465ns          1.717000V         1.869400V            1.561200V
+4.8485ns          1.718600V         1.839700V            1.565600V
+5.0505ns          1.719900V         1.823800V            1.569900V
+5.2525ns          1.721200V         1.826000V            1.574200V
+5.4545ns          1.722500V         1.835200V            1.578400V
+5.6566ns          1.723800V         1.841500V            1.582600V
+5.8586ns          1.725000V         1.842800V            1.586700V
+6.0606ns          1.726200V         1.841300V            1.590800V
+6.2626ns          1.727400V         1.839800V            1.594800V
+6.4646ns          1.728600V         1.838400V            1.598800V
+6.6667ns          1.729800V         1.837000V            1.602700V
+6.8687ns          1.730900V         1.835500V            1.606600V
+7.0707ns          1.732000V         1.834000V            1.610400V
+7.2727ns          1.733200V         1.832700V            1.614200V
+7.4747ns          1.734300V         1.831300V            1.618000V
+7.6768ns          1.735400V         1.829900V            1.621600V
+7.8788ns          1.736400V         1.828500V            1.625300V
+8.0808ns          1.737500V         1.827100V            1.628900V
+8.2828ns          1.738600V         1.825800V            1.632500V
+8.4848ns          1.739600V         1.824400V            1.636000V
+8.6869ns          1.740600V         1.823100V            1.639400V
+8.8889ns          1.741700V         1.821800V            1.642900V
+9.0909ns          1.742700V         1.820400V            1.646300V
+9.2929ns          1.743700V         1.819100V            1.649600V
+9.4949ns          1.744700V         1.817800V            1.652900V
+9.6970ns          1.745600V         1.816500V            1.656200V
+9.8990ns          1.746600V         1.815200V            1.659400V
+10.1010ns         1.748050V         1.813350V            1.664200V
+10.3030ns         1.749400V         1.811400V            1.668900V
+10.5051ns         1.750400V         1.810200V            1.672000V
+10.7071ns         1.751300V         1.809000V            1.675000V
+10.9091ns         1.752200V         1.807800V            1.678000V
+11.1111ns         1.753100V         1.806500V            1.681000V
+11.3131ns         1.753900V         1.805400V            1.684000V
+11.5152ns         1.754800V         1.804200V            1.686900V
+11.7172ns         1.755700V         1.803000V            1.689700V
+11.9192ns         1.756500V         1.801800V            1.692600V
+12.1212ns         1.757400V         1.800700V            1.695400V
+12.3232ns         1.758200V         1.799500V            1.698200V
+12.5253ns         1.759000V         1.798400V            1.700900V
+12.7273ns         1.759800V         1.797300V            1.703600V
+12.9293ns         1.760600V         1.796200V            1.706300V
+13.1313ns         1.761400V         1.795100V            1.709000V
+13.3333ns         1.762200V         1.794000V            1.711600V
+13.5354ns         1.763000V         1.792900V            1.714200V
+13.7374ns         1.763800V         1.791800V            1.716700V
+13.9394ns         1.764500V         1.790800V            1.719300V
+14.1414ns         1.765300V         1.789700V            1.721800V
+14.3434ns         1.766000V         1.788700V            1.724200V
+14.5455ns         1.766800V         1.787700V            1.726700V
+14.7475ns         1.767500V         1.786600V            1.729100V
+14.9495ns         1.768200V         1.785600V            1.731500V
+15.1515ns         1.768900V         1.784600V            1.733900V
+15.3535ns         1.769600V         1.783600V            1.736200V
+15.5556ns         1.770300V         1.782700V            1.738500V
+15.7576ns         1.771000V         1.781700V            1.740800V
+15.9596ns         1.771700V         1.780700V            1.743100V
+16.1616ns         1.772400V         1.779800V            1.745300V
+16.3636ns         1.773000V         1.778800V            1.747500V
+16.5657ns         1.773700V         1.777900V            1.749700V
+16.7677ns         1.774300V         1.777000V            1.751900V
+16.9697ns         1.775000V         1.776000V            1.754000V
+17.1717ns         1.775600V         1.775100V            1.756200V
+17.3737ns         1.776300V         1.774200V            1.758300V
+17.5758ns         1.776900V         1.773300V            1.760300V
+17.7778ns         1.777500V         1.772400V            1.762400V
+17.9798ns         1.778100V         1.771600V            1.764400V
+18.1818ns         1.778700V         1.770700V            1.766400V
+18.3838ns         1.779300V         1.769800V            1.768400V
+18.5859ns         1.779900V         1.769000V            1.770400V
+18.7879ns         1.780500V         1.768100V            1.772300V
+18.9899ns         1.781100V         1.767300V            1.774200V
+19.1919ns         1.781600V         1.766500V            1.776200V
+19.3939ns         1.782200V         1.765700V            1.778000V
+19.5960ns         1.782800V         1.764900V            1.779900V
+19.7980ns         1.783300V         1.764000V            1.781700V
+|20.0000ns         1.783900V         1.763300V            1.783600V
+40.0000ns         1.783900V         1.550000V            1.783600V
+|  
+| End [Model] lvc330s140aaaaaaaaio
+|************************************************************************
+| End [Component]
+[End]
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt
index 74e813c..ceaf9b4 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt
@@ -1,75 +1,75 @@
-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Wed Aug 16 04:50:55 2023 *
-NOTE DESIGN NAME: RAM2GS *
-NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
-NOTE PIN ASSIGNMENTS *
-NOTE PINS RD[0] : 64 : inout *
-NOTE PINS Dout[0] : 1 : out *
-NOTE PINS PHI2 : 39 : in *
-NOTE PINS UFMSDO : 55 : in *
-NOTE PINS UFMSDI : 56 : out *
-NOTE PINS UFMCLK : 58 : out *
-NOTE PINS nUFMCS : 53 : out *
-NOTE PINS RDQML : 61 : out *
-NOTE PINS RDQMH : 76 : out *
-NOTE PINS nRCAS : 78 : out *
-NOTE PINS nRRAS : 73 : out *
-NOTE PINS nRWE : 72 : out *
-NOTE PINS RCKE : 82 : out *
-NOTE PINS RCLK : 86 : in *
-NOTE PINS nRCS : 77 : out *
-NOTE PINS RD[7] : 71 : inout *
-NOTE PINS RD[6] : 70 : inout *
-NOTE PINS RD[5] : 69 : inout *
-NOTE PINS RD[4] : 68 : inout *
-NOTE PINS RD[3] : 67 : inout *
-NOTE PINS RD[2] : 66 : inout *
-NOTE PINS RD[1] : 65 : inout *
-NOTE PINS RA[11] : 79 : out *
-NOTE PINS RA[10] : 87 : out *
-NOTE PINS RA[9] : 85 : out *
-NOTE PINS RA[8] : 96 : out *
-NOTE PINS RA[7] : 100 : out *
-NOTE PINS RA[6] : 91 : out *
-NOTE PINS RA[5] : 95 : out *
-NOTE PINS RA[4] : 99 : out *
-NOTE PINS RA[3] : 97 : out *
-NOTE PINS RA[2] : 94 : out *
-NOTE PINS RA[1] : 89 : out *
-NOTE PINS RA[0] : 98 : out *
-NOTE PINS RBA[1] : 83 : out *
-NOTE PINS RBA[0] : 63 : out *
-NOTE PINS LED : 57 : out *
-NOTE PINS nFWE : 22 : in *
-NOTE PINS nCRAS : 43 : in *
-NOTE PINS nCCAS : 27 : in *
-NOTE PINS Dout[7] : 3 : out *
-NOTE PINS Dout[6] : 2 : out *
-NOTE PINS Dout[5] : 5 : out *
-NOTE PINS Dout[4] : 4 : out *
-NOTE PINS Dout[3] : 6 : out *
-NOTE PINS Dout[2] : 8 : out *
-NOTE PINS Dout[1] : 7 : out *
-NOTE PINS Din[7] : 19 : in *
-NOTE PINS Din[6] : 20 : in *
-NOTE PINS Din[5] : 17 : in *
-NOTE PINS Din[4] : 18 : in *
-NOTE PINS Din[3] : 16 : in *
-NOTE PINS Din[2] : 14 : in *
-NOTE PINS Din[1] : 15 : in *
-NOTE PINS Din[0] : 21 : in *
-NOTE PINS CROW[1] : 34 : in *
-NOTE PINS CROW[0] : 32 : in *
-NOTE PINS MAin[9] : 51 : in *
-NOTE PINS MAin[8] : 50 : in *
-NOTE PINS MAin[7] : 44 : in *
-NOTE PINS MAin[6] : 49 : in *
-NOTE PINS MAin[5] : 45 : in *
-NOTE PINS MAin[4] : 46 : in *
-NOTE PINS MAin[3] : 47 : in *
-NOTE PINS MAin[2] : 37 : in *
-NOTE PINS MAin[1] : 38 : in *
-NOTE PINS MAin[0] : 23 : in *
-NOTE CONFIGURATION MODE: NONE *
-NOTE COMPRESSION: off *
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Sat Aug 19 20:57:27 2023 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[0] : 64 : inout *
+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS PHI2 : 39 : in *
+NOTE PINS UFMSDO : 55 : in *
+NOTE PINS UFMSDI : 56 : out *
+NOTE PINS UFMCLK : 58 : out *
+NOTE PINS nUFMCS : 53 : out *
+NOTE PINS RDQML : 61 : out *
+NOTE PINS RDQMH : 76 : out *
+NOTE PINS nRCAS : 78 : out *
+NOTE PINS nRRAS : 73 : out *
+NOTE PINS nRWE : 72 : out *
+NOTE PINS RCKE : 82 : out *
+NOTE PINS RCLK : 86 : in *
+NOTE PINS nRCS : 77 : out *
+NOTE PINS RD[7] : 71 : inout *
+NOTE PINS RD[6] : 70 : inout *
+NOTE PINS RD[5] : 69 : inout *
+NOTE PINS RD[4] : 68 : inout *
+NOTE PINS RD[3] : 67 : inout *
+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
+NOTE PINS RA[9] : 85 : out *
+NOTE PINS RA[8] : 96 : out *
+NOTE PINS RA[7] : 100 : out *
+NOTE PINS RA[6] : 91 : out *
+NOTE PINS RA[5] : 95 : out *
+NOTE PINS RA[4] : 99 : out *
+NOTE PINS RA[3] : 97 : out *
+NOTE PINS RA[2] : 94 : out *
+NOTE PINS RA[1] : 89 : out *
+NOTE PINS RA[0] : 98 : out *
+NOTE PINS RBA[1] : 83 : out *
+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS LED : 57 : out *
+NOTE PINS nFWE : 22 : in *
+NOTE PINS nCRAS : 43 : in *
+NOTE PINS nCCAS : 27 : in *
+NOTE PINS Dout[7] : 3 : out *
+NOTE PINS Dout[6] : 2 : out *
+NOTE PINS Dout[5] : 5 : out *
+NOTE PINS Dout[4] : 4 : out *
+NOTE PINS Dout[3] : 6 : out *
+NOTE PINS Dout[2] : 8 : out *
+NOTE PINS Dout[1] : 7 : out *
+NOTE PINS Din[7] : 19 : in *
+NOTE PINS Din[6] : 20 : in *
+NOTE PINS Din[5] : 17 : in *
+NOTE PINS Din[4] : 18 : in *
+NOTE PINS Din[3] : 16 : in *
+NOTE PINS Din[2] : 14 : in *
+NOTE PINS Din[1] : 15 : in *
+NOTE PINS Din[0] : 21 : in *
+NOTE PINS CROW[1] : 34 : in *
+NOTE PINS CROW[0] : 32 : in *
+NOTE PINS MAin[9] : 51 : in *
+NOTE PINS MAin[8] : 50 : in *
+NOTE PINS MAin[7] : 44 : in *
+NOTE PINS MAin[6] : 49 : in *
+NOTE PINS MAin[5] : 45 : in *
+NOTE PINS MAin[4] : 46 : in *
+NOTE PINS MAin[3] : 47 : in *
+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr
index d75917f..0c38afe 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr
@@ -1,26 +1,26 @@
-----------------------------------------------------------------------
-Report for cell RAM2GS.verilog
-
-Register bits: 92 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-                                          Cell usage:
-                               cell       count    Res Usage(%)
-                                 BB        8       100.0
-                               CCU2        9       100.0
-                            FD1P3AX       11       100.0
-                            FD1S3AX       59       100.0
-                            FD1S3AY        5       100.0
-                            FD1S3IX       14       100.0
-                            FD1S3JX        3       100.0
-                                GSR        1       100.0
-                                 IB       26       100.0
-                                INV        8       100.0
-                                 OB       33       100.0
-                           ORCALUT4      119       100.0
-                              PFUMX        2       100.0
-                                PUR        1       100.0
-                                VHI        1       100.0
-                                VLO        1       100.0
-                            
-                         TOTAL           301           
+----------------------------------------------------------------------
+Report for cell RAM2GS.verilog
+
+Register bits: 92 of 640 (14%)
+PIC Latch:       0
+I/O cells:       67
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                 BB        8       100.0
+                               CCU2        9       100.0
+                            FD1P3AX       11       100.0
+                            FD1S3AX       59       100.0
+                            FD1S3AY        5       100.0
+                            FD1S3IX       14       100.0
+                            FD1S3JX        3       100.0
+                                GSR        1       100.0
+                                 IB       26       100.0
+                                INV        8       100.0
+                                 OB       33       100.0
+                           ORCALUT4      119       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL           301           
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn
index 5b6e508..26be261 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn
@@ -1,45 +1,45 @@
-BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:55 2023
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:57:26 2023
+
 
-
-Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
-
-Preference Summary:
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 46 MB
+Command: bitgen -w -g ES:No -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 67 MB
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit
index cb9573e44751ef7641cae8702526285a99b2a1b3..d1c799f44abe80ebd42f8120969c2469570e5060 100644
GIT binary patch
delta 33
pcmew|m+{M7#tGX+f)h&=92H8_6$~vEj0~(y&8>{gH=fq?0|3^a3rzq3

delta 33
pcmew|m+{M7#tGX+!c$We92H8_6%5T33{0#{4XjK}H=fq?0|3>v3qAk<

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd
index 37e2fc98df54ea11c33c83035af5fbdddab27f76..3448f965bb4d8f65bc25e76b275326e77843ac40 100644
GIT binary patch
delta 40
wcmcaUiSzm-&IuyS4^v)l6n`YaRv+!BrLRAkQPQE=Ub5X@l5xAeB$I>z06`TEGXMYp

delta 40
wcmcaUiSzm-&IuyScY2>~6n`YaR_OeIU0;7PqohN#y=1$+B;$5_NhS#c07~5rod5s;

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
index f0915dc..da08f0e 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
@@ -1,353 +1,353 @@
-PAD Specification File
-***************************
-
-PART TYPE:        LCMXO640C
-Performance Grade:      3
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.17
-
-Wed Aug 16 04:50:52 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+-------+----------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                       |
-+-----------+----------+---------------+-------+----------------------------------+
-| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:KEEPER            |
-| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:KEEPER            |
-| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:KEEPER            |
-| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:KEEPER            |
-| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:KEEPER            |
-| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:KEEPER            |
-| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:KEEPER            |
-| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:KEEPER            |
-| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:KEEPER            |
-| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:KEEPER            |
-| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:4mA SLEW:FAST              |
-| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:4mA SLEW:FAST              |
-| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:4mA SLEW:FAST              |
-| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:4mA SLEW:FAST              |
-| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:4mA SLEW:FAST              |
-| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:4mA SLEW:FAST              |
-| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:4mA SLEW:FAST              |
-| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:4mA SLEW:FAST              |
-| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:14mA SLEW:SLOW             |
-| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:KEEPER            |
-| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:KEEPER            |
-| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:KEEPER            |
-| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:KEEPER            |
-| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:KEEPER            |
-| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:KEEPER            |
-| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:KEEPER            |
-| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:KEEPER            |
-| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:KEEPER            |
-| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:KEEPER            |
-| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:DOWN              |
-| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
-| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
-| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
-| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
-| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
-| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
-| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
-| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
-| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
-| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
-| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
-| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
-| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
-| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:KEEPER            |
-| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
-| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
-| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
-| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
-| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
-| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP                |
-| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP                |
-| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:KEEPER            |
-| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
-| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
-| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
-| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
-| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
-+-----------+----------+---------------+-------+----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    |       |
-| 3    | 3.3V  |
-+------+-------+
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+---------------------+------------+---------------+-------+---------------+
-| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
-+----------+---------------------+------------+---------------+-------+---------------+
-| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
-| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
-| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
-| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
-| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
-| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
-| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
-| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
-| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
-| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
-| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
-| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
-| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
-| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
-| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
-| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
-| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
-| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
-| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
-| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
-| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
-| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
-| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
-| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
-| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
-| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
-| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
-| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
-| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
-| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
-| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
-| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
-| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
-| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
-| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
-| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
-| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
-| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
-| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
-| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
-| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
-| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
-| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
-| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
-| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
-| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
-| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
-| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
-| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
-| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
-| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
-| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
-| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
-| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
-| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
-| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
-| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
-| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
-| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
-| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
-| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
-| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
-| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
-| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
-| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
-| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
-| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
-| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
-| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
-| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
-| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
-| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
-| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
-| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
-| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
-| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
-| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
-| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
-| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
-| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
-| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
-| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
-| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
-| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
-| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
-| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
-| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
-| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
-| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
-| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
-| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
-| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
-| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
-| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
-| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
-| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
-| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
-| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
-| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
-| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
-| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
-| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
-| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
-| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
-| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
-| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
-| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
-| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
-| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
-| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
-| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
-| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
-| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
-| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
-| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
-| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
-| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
-| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
-| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
-| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
-| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
-| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
-| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
-| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
-| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
-| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
-| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
-| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
-| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
-| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
-| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
-| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
-| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
-| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
-| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
-| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
-| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
-| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
-| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
-| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
-| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
-| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
-| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
-| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
-| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
-| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
-| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
-| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
-| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
-| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
-| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
-| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
-| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
-| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
-| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
-| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
-| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
-| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
-| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
-| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
-| TCK/2    |                     |            |               | TCK   | TCK           |
-| TDI/2    |                     |            |               | TDI   | TDID0         |
-| TDO/2    |                     |            |               | TDO   | TDO           |
-| TMS/2    |                     |            |               | TMS   | TMS           |
-+----------+---------------------+------------+---------------+-------+---------------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "32";
-LOCATE  COMP  "CROW[1]"  SITE  "34";
-LOCATE  COMP  "Din[0]"  SITE  "21";
-LOCATE  COMP  "Din[1]"  SITE  "15";
-LOCATE  COMP  "Din[2]"  SITE  "14";
-LOCATE  COMP  "Din[3]"  SITE  "16";
-LOCATE  COMP  "Din[4]"  SITE  "18";
-LOCATE  COMP  "Din[5]"  SITE  "17";
-LOCATE  COMP  "Din[6]"  SITE  "20";
-LOCATE  COMP  "Din[7]"  SITE  "19";
-LOCATE  COMP  "Dout[0]"  SITE  "1";
-LOCATE  COMP  "Dout[1]"  SITE  "7";
-LOCATE  COMP  "Dout[2]"  SITE  "8";
-LOCATE  COMP  "Dout[3]"  SITE  "6";
-LOCATE  COMP  "Dout[4]"  SITE  "4";
-LOCATE  COMP  "Dout[5]"  SITE  "5";
-LOCATE  COMP  "Dout[6]"  SITE  "2";
-LOCATE  COMP  "Dout[7]"  SITE  "3";
-LOCATE  COMP  "LED"  SITE  "57";
-LOCATE  COMP  "MAin[0]"  SITE  "23";
-LOCATE  COMP  "MAin[1]"  SITE  "38";
-LOCATE  COMP  "MAin[2]"  SITE  "37";
-LOCATE  COMP  "MAin[3]"  SITE  "47";
-LOCATE  COMP  "MAin[4]"  SITE  "46";
-LOCATE  COMP  "MAin[5]"  SITE  "45";
-LOCATE  COMP  "MAin[6]"  SITE  "49";
-LOCATE  COMP  "MAin[7]"  SITE  "44";
-LOCATE  COMP  "MAin[8]"  SITE  "50";
-LOCATE  COMP  "MAin[9]"  SITE  "51";
-LOCATE  COMP  "PHI2"  SITE  "39";
-LOCATE  COMP  "RA[0]"  SITE  "98";
-LOCATE  COMP  "RA[10]"  SITE  "87";
-LOCATE  COMP  "RA[11]"  SITE  "79";
-LOCATE  COMP  "RA[1]"  SITE  "89";
-LOCATE  COMP  "RA[2]"  SITE  "94";
-LOCATE  COMP  "RA[3]"  SITE  "97";
-LOCATE  COMP  "RA[4]"  SITE  "99";
-LOCATE  COMP  "RA[5]"  SITE  "95";
-LOCATE  COMP  "RA[6]"  SITE  "91";
-LOCATE  COMP  "RA[7]"  SITE  "100";
-LOCATE  COMP  "RA[8]"  SITE  "96";
-LOCATE  COMP  "RA[9]"  SITE  "85";
-LOCATE  COMP  "RBA[0]"  SITE  "63";
-LOCATE  COMP  "RBA[1]"  SITE  "83";
-LOCATE  COMP  "RCKE"  SITE  "82";
-LOCATE  COMP  "RCLK"  SITE  "86";
-LOCATE  COMP  "RDQMH"  SITE  "76";
-LOCATE  COMP  "RDQML"  SITE  "61";
-LOCATE  COMP  "RD[0]"  SITE  "64";
-LOCATE  COMP  "RD[1]"  SITE  "65";
-LOCATE  COMP  "RD[2]"  SITE  "66";
-LOCATE  COMP  "RD[3]"  SITE  "67";
-LOCATE  COMP  "RD[4]"  SITE  "68";
-LOCATE  COMP  "RD[5]"  SITE  "69";
-LOCATE  COMP  "RD[6]"  SITE  "70";
-LOCATE  COMP  "RD[7]"  SITE  "71";
-LOCATE  COMP  "UFMCLK"  SITE  "58";
-LOCATE  COMP  "UFMSDI"  SITE  "56";
-LOCATE  COMP  "UFMSDO"  SITE  "55";
-LOCATE  COMP  "nCCAS"  SITE  "27";
-LOCATE  COMP  "nCRAS"  SITE  "43";
-LOCATE  COMP  "nFWE"  SITE  "22";
-LOCATE  COMP  "nRCAS"  SITE  "78";
-LOCATE  COMP  "nRCS"  SITE  "77";
-LOCATE  COMP  "nRRAS"  SITE  "73";
-LOCATE  COMP  "nRWE"  SITE  "72";
-LOCATE  COMP  "nUFMCS"  SITE  "53";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:52 2023
-
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Sat Aug 19 20:57:21 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                       |
++-----------+----------+---------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:KEEPER            |
+| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:KEEPER            |
+| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:KEEPER            |
+| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:KEEPER            |
+| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:KEEPER            |
+| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:KEEPER            |
+| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:KEEPER            |
+| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:KEEPER            |
+| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:KEEPER            |
+| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:KEEPER            |
+| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:4mA SLEW:FAST              |
+| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:4mA SLEW:FAST              |
+| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:4mA SLEW:FAST              |
+| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:4mA SLEW:FAST              |
+| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:4mA SLEW:FAST              |
+| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:4mA SLEW:FAST              |
+| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:4mA SLEW:FAST              |
+| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:4mA SLEW:FAST              |
+| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:14mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:KEEPER            |
+| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:KEEPER            |
+| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:KEEPER            |
+| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:KEEPER            |
+| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:KEEPER            |
+| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:KEEPER            |
+| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:KEEPER            |
+| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:KEEPER            |
+| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:KEEPER            |
+| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:KEEPER            |
+| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:DOWN              |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:KEEPER            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP                |
+| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP                |
+| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:KEEPER            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+---------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
++----------+---------------------+------------+---------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
+| TCK/2    |                     |            |               | TCK   | TCK           |
+| TDI/2    |                     |            |               | TDI   | TDID0         |
+| TDO/2    |                     |            |               | TDO   | TDO           |
+| TMS/2    |                     |            |               | TMS   | TMS           |
++----------+---------------------+------------+---------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:57:21 2023
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
index 7e25e48..eb9cfbf 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
@@ -1,213 +1,213 @@
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Wed Aug 16 04:50:48 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)      67/159          42% used
-                     67/74           90% bonded
-   SLICE             69/320          21% used
-
-
-
-Number of Signals: 251
-Number of Connections: 633
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 32)
-    PHI2_c (driver: PHI2, clk load #: 14)
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-.........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-.............
-Placer score = 956294.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  953137
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 1 out of 160 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 4 (50%)
-  SECONDARY: 1 out of 4 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 out of 159 (42.1%) PIO sites used.
-   67 out of 74 (90.5%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
-| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-| 2        | 13 / 14 ( 92%) | -          | -          | -          |
-| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-0 connections routed; 633 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Completed router resource preassignment. Real time: 4 secs 
-
-Start NBR router at 04:50:52 08/16/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 04:50:52 08/16/23
-
-Start NBR section for initial routing at 04:50:52 08/16/23
-Level 1, iteration 1
-1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.325ns/0.000ns; real time: 4 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.532ns/0.000ns; real time: 4 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.449ns/0.000ns; real time: 4 secs 
-Level 4, iteration 1
-8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:52 08/16/23
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 2
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:52 08/16/23
-
-Start NBR section for re-routing at 04:50:52 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for post-routing at 04:50:52 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 7.336ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 7.336
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Sat Aug 19 20:57:16 2023
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             69/320          21% used
+
+
+
+Number of Signals: 251
+Number of Connections: 633
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 32)
+    PHI2_c (driver: PHI2, clk load #: 14)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.............
+Placer score = 956294.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  953137
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 160 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 633 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Completed router resource preassignment. Real time: 6 secs 
+
+Start NBR router at 20:57:22 08/19/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 20:57:22 08/19/23
+
+Start NBR section for initial routing at 20:57:22 08/19/23
+Level 1, iteration 1
+1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.325ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.532ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.449ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 20:57:22 08/19/23
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:57:22 08/19/23
+
+Start NBR section for re-routing at 20:57:22 08/19/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 20:57:22 08/19/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 7.336ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  633 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 7.336
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.273
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
index f8365c2..86b1287 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
@@ -1,42 +1,42 @@
-[ActiveSupport PAR]
-; Global primary clocks
-GLOBAL_PRIMARY_USED = 2;
-; Global primary clock #0
-GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
-GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
-GLOBAL_PRIMARY_0_LOADNUM = 32;
-; Global primary clock #1
-GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
-GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_1_LOADNUM = 14;
-; # of global secondary clocks
-GLOBAL_SECONDARY_USED = 1;
-; Global secondary clock #0
-GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
-GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
-GLOBAL_SECONDARY_0_LOADNUM = 10;
-GLOBAL_SECONDARY_0_SIGTYPE = CLK;
-; I/O Bank 0 Usage
-BANK_0_USED = 18;
-BANK_0_AVAIL = 18;
-BANK_0_VCCIO = 3.3V;
-BANK_0_VREF1 = NA;
-BANK_0_VREF2 = NA;
-; I/O Bank 1 Usage
-BANK_1_USED = 18;
-BANK_1_AVAIL = 21;
-BANK_1_VCCIO = 3.3V;
-BANK_1_VREF1 = NA;
-BANK_1_VREF2 = NA;
-; I/O Bank 2 Usage
-BANK_2_USED = 13;
-BANK_2_AVAIL = 14;
-BANK_2_VCCIO = NA;
-BANK_2_VREF1 = NA;
-BANK_2_VREF2 = NA;
-; I/O Bank 3 Usage
-BANK_3_USED = 18;
-BANK_3_AVAIL = 21;
-BANK_3_VCCIO = 3.3V;
-BANK_3_VREF1 = NA;
-BANK_3_VREF2 = NA;
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 2;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 32;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 14;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 1;
+; Global secondary clock #0
+GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
+GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
+GLOBAL_SECONDARY_0_LOADNUM = 10;
+GLOBAL_SECONDARY_0_SIGTYPE = CLK;
+; I/O Bank 0 Usage
+BANK_0_USED = 18;
+BANK_0_AVAIL = 18;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+BANK_0_VREF2 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 18;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+BANK_1_VREF2 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 13;
+BANK_2_AVAIL = 14;
+BANK_2_VCCIO = NA;
+BANK_2_VREF1 = NA;
+BANK_2_VREF2 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 18;
+BANK_3_AVAIL = 21;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
+BANK_3_VREF2 = NA;
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
index 82b5aa6..f5af0d4 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
@@ -1,28 +1,28 @@
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:48 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
-RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
-RAM2GS_LCMXO640C_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            7.336        0            0.273        0            04           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 4 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:57:16 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            7.336        0            0.273        0            06           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
index ec074a2..8417bb5 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
@@ -1 +1 @@
-DRC detected 0 errors and 0 warnings.
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi
index d9bba43..2a22cd0 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi
@@ -1,2786 +1,2786 @@
-(edif RAM2GS
-  (edifVersion 2 0 0)
-  (edifLevel 0)
-  (keywordMap (keywordLevel 0))
-  (status
-    (written
-      (timeStamp 2023 8 16 4 50 45)
-      (author "Synopsys, Inc.")
-      (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
-     )
-   )
-  (library LUCENT
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell CCU2 (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A0 (direction INPUT))
-           (port B0 (direction INPUT))
-           (port C0 (direction INPUT))
-           (port D0 (direction INPUT))
-           (port A1 (direction INPUT))
-           (port B1 (direction INPUT))
-           (port C1 (direction INPUT))
-           (port D1 (direction INPUT))
-           (port CIN (direction INPUT))
-           (port COUT0 (direction OUTPUT))
-           (port COUT1 (direction OUTPUT))
-           (port S0 (direction OUTPUT))
-           (port S1 (direction OUTPUT))
-         )
-        (property INJECT1_1 (string "NO"))
-        (property INJECT1_0 (string "NO"))
-        (property INIT1 (string "0000"))
-        (property INIT0 (string "0000"))
-       )
-    )
-    (cell BB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port B (direction INOUT))
-           (port I (direction INPUT))
-           (port T (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell OB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell IB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3JX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port PD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3IX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port CD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AY (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1P3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell ORCALUT4 (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port B (direction INPUT))
-           (port C (direction INPUT))
-           (port D (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell PFUMX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port ALUT (direction INPUT))
-           (port BLUT (direction INPUT))
-           (port C0 (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell GSR (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port GSR (direction INPUT))
-         )
-       )
-    )
-    (cell INV (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VHI (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VLO (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-  )
-  (library work
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell RAM2GS (cellType GENERIC)
-       (view verilog (viewType NETLIST)
-         (interface
-           (port PHI2 (direction INPUT))
-           (port (array (rename main "MAin[9:0]") 10) (direction INPUT))
-           (port (array (rename crow "CROW[1:0]") 2) (direction INPUT))
-           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
-           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
-           (port nCCAS (direction INPUT))
-           (port nCRAS (direction INPUT))
-           (port nFWE (direction INPUT))
-           (port LED (direction OUTPUT))
-           (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT))
-           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
-           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
-           (port nRCS (direction OUTPUT))
-           (port RCLK (direction INPUT))
-           (port RCKE (direction OUTPUT))
-           (port nRWE (direction OUTPUT))
-           (port nRRAS (direction OUTPUT))
-           (port nRCAS (direction OUTPUT))
-           (port RDQMH (direction OUTPUT))
-           (port RDQML (direction OUTPUT))
-           (port nUFMCS (direction OUTPUT))
-           (port UFMCLK (direction OUTPUT))
-           (port UFMSDI (direction OUTPUT))
-           (port UFMSDO (direction INPUT))
-         )
-         (contents
-          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
-          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
-          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
-          )
-          (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))"))
-          )
-          (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))"))
-          )
-          (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
-          )
-          (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
-          )
-          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
-          )
-          (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))"))
-          )
-          (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance nRWE_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_0 "WRD[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_1 "WRD[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_2 "WRD[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_3 "WRD[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_4 "WRD[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_5 "WRD[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_6 "WRD[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_7 "WRD[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMCLK (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RBA_0 "RBA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RBA_1 "RBA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RA11 (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance RA10 (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0 "Bank[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_1 "Bank[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_2 "Bank[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_3 "Bank[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_4 "Bank[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_5 "Bank[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_6 "Bank[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_7 "Bank[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
-          )
-          (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B)+D (!C (!B A)))"))
-          )
-          (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C+(B+A)))"))
-          )
-          (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(!B+!A)))"))
-          )
-          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !A+D (!C !A+C (B !A)))"))
-          )
-          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C (!B A)+C !B))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
-          )
-          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)"))
-          )
-          (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D A)"))
-          )
-          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
-          )
-          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)+C !A))"))
-          )
-          (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+!A))"))
-          )
-          (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B A)))"))
-          )
-          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(!B+A))"))
-          )
-          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A))"))
-          )
-          (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
-          )
-          (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+!A)"))
-          )
-          (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(!B+!A))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+!A))"))
-          )
-          (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A+B !A)+C B)"))
-          )
-          (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
-          (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A+B !A)"))
-          )
-          (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B !A)"))
-          )
-          (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
-          )
-          (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
-          )
-          (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !B+D (!C (!B A)+C !B))"))
-          )
-          (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))"))
-          )
-          (instance nRWE_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance nRWE_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance nRWE_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))"))
-          )
-          (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))"))
-          )
-          (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A)+C !B)"))
-          )
-          (instance UFMSDI_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
-          )
-          (instance UFMCLK_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C !B)+D (C (!B !A)))"))
-          )
-          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(B+A))+D (!C B+C (B+!A)))"))
-          )
-          (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A))"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)))"))
-          )
-          (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
-          )
-          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A+B A)+C A)"))
-          )
-          (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))"))
-          )
-          (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x5002"))
-          )
-          (instance (rename FS_cry_0_14 "FS_cry_0[14]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_12 "FS_cry_0[12]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_10 "FS_cry_0[10]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_8 "FS_cry_0[8]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_6 "FS_cry_0[6]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_4 "FS_cry_0[4]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_2 "FS_cry_0[2]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (net C1WR_0_a2 (joined
-           (portRef Z (instanceRef C1WR_0_a2))
-           (portRef B (instanceRef ADSubmitted_r))
-          ))
-          (net CBR (joined
-           (portRef Q (instanceRef CBR))
-           (portRef A (instanceRef nRWE_RNO_0))
-           (portRef A (instanceRef nRCS_RNO))
-           (portRef A (instanceRef RCKEEN_8_u))
-           (portRef B (instanceRef nRowColSel_0_0_a3_0))
-           (portRef A (instanceRef LED_pad_RNO))
-          ))
-          (net C1Submitted (joined
-           (portRef Q (instanceRef C1Submitted))
-           (portRef D (instanceRef CmdEnable_s_am))
-           (portRef B (instanceRef C1Submitted_RNO))
-          ))
-          (net (rename Bank_2 "Bank[2]") (joined
-           (portRef Q (instanceRef Bank_2))
-           (portRef A (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net Ready (joined
-           (portRef Q (instanceRef Ready))
-           (portRef B (instanceRef IS_RNO_0))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRWE_RNO_2))
-           (portRef D (instanceRef RCKEEN_8_u))
-           (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef D (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C0 (instanceRef nRWE_RNO_1))
-           (portRef A (instanceRef Ready_RNO))
-           (portRef A (instanceRef RCKEEN_8_u_RNO))
-           (portRef A (instanceRef nRowColSel_RNO))
-          ))
-          (net n8MEGEN (joined
-           (portRef Q (instanceRef n8MEGEN))
-           (portRef C (instanceRef RA11_2))
-           (portRef C (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net CO0 (joined
-           (portRef Q (instanceRef S_0))
-           (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef nRCAS_RNO_0))
-           (portRef B (instanceRef nRWE_RNO_0))
-           (portRef B (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef A (instanceRef S_RNO_0))
-           (portRef A (instanceRef nRowColSel_0_0))
-           (portRef B (instanceRef nRWE_RNO_4))
-           (portRef B (instanceRef nRWE_RNO_3))
-           (portRef C (instanceRef nRowColSel_RNO))
-           (portRef B (instanceRef nRCS_RNO_0))
-          ))
-          (net (rename S_1 "S[1]") (joined
-           (portRef Q (instanceRef S_1))
-           (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRCAS_RNO))
-           (portRef C (instanceRef nRWE_RNO_0))
-           (portRef D (instanceRef RCKEEN_8_u_1_0))
-           (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef B (instanceRef S_0_i_o2_1))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef S_RNO_0))
-           (portRef D (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef A (instanceRef nRWE_RNO_4))
-           (portRef A (instanceRef nRWE_RNO_3))
-           (portRef B (instanceRef nRowColSel_RNO))
-          ))
-          (net RASr2 (joined
-           (portRef Q (instanceRef RASr2))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef D (instanceRef nRWE_RNO_5))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef RCKE_2_0))
-           (portRef B (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef D (instanceRef RASr3))
-           (portRef D (instanceRef nRWE_RNO_3))
-           (portRef B (instanceRef RCKEEN_8_u_RNO))
-           (portRef A (instanceRef RASr2_RNIAFR1))
-          ))
-          (net InitReady (joined
-           (portRef Q (instanceRef InitReady))
-           (portRef A (instanceRef UFMCLK_RNO_0))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-           (portRef B (instanceRef LEDEN_5_i_m2))
-           (portRef B (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef B (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef PHI2r3_RNITCN41))
-           (portRef C (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef A (instanceRef UFMSDI_ens2_i_a0))
-           (portRef B (instanceRef InitReady_RNO))
-           (portRef D (instanceRef nRWE_RNO_4))
-           (portRef D (instanceRef Ready_RNO))
-           (portRef C (instanceRef RCKEEN_8_u_RNO))
-          ))
-          (net FWEr (joined
-           (portRef Q (instanceRef FWEr))
-           (portRef C (instanceRef nRCAS_RNO_0))
-           (portRef A (instanceRef nRWE_RNO))
-           (portRef C (instanceRef nRowColSel_0_0_a3_0))
-          ))
-          (net CASr3 (joined
-           (portRef Q (instanceRef CASr3))
-           (portRef B (instanceRef nRCAS_RNO_1))
-           (portRef B (instanceRef nRWE_RNO_2))
-           (portRef A (instanceRef nRowColSel_0_0_a3_0))
-           (portRef C (instanceRef nRCS_RNO_0))
-          ))
-          (net (rename IS_0 "IS[0]") (joined
-           (portRef Q (instanceRef IS_0))
-           (portRef A (instanceRef IS_RNO_0))
-           (portRef D (instanceRef nRRAS_RNO))
-           (portRef A (instanceRef nRWE_RNO_5))
-           (portRef A (instanceRef IS_n1_0_x2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef A (instanceRef IS_RNO_2))
-           (portRef A (instanceRef nRRAS_5_u_i))
-           (portRef D (instanceRef IS_RNO_3))
-           (portRef A (instanceRef IS_i_0))
-          ))
-          (net (rename IS_3 "IS[3]") (joined
-           (portRef Q (instanceRef IS_3))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef RA10_RNO))
-           (portRef A (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_1 "IS[1]") (joined
-           (portRef Q (instanceRef IS_1))
-           (portRef B (instanceRef nRWE_RNO_5))
-           (portRef B (instanceRef IS_n1_0_x2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef IS_RNO_2))
-           (portRef A (instanceRef RA10_RNO))
-           (portRef C (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_2 "IS[2]") (joined
-           (portRef Q (instanceRef IS_2))
-           (portRef C (instanceRef nRWE_RNO_5))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef C (instanceRef IS_RNO_2))
-           (portRef B (instanceRef RA10_RNO))
-           (portRef B (instanceRef IS_RNO_3))
-          ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A1 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_13_i_a2_1))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A0 (instanceRef FS_cry_0_6))
-           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef B (instanceRef un1_FS_13_i_a2_6))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A1 (instanceRef FS_cry_0_6))
-           (portRef C (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A0 (instanceRef FS_cry_0_8))
-           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A1 (instanceRef FS_cry_0_8))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_0 "FS[0]") (joined
-           (portRef Q (instanceRef FS_0))
-           (portRef A0 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_1 "FS[1]") (joined
-           (portRef Q (instanceRef FS_1))
-           (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef UFMCLK_r_i_m2))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A0 (instanceRef FS_cry_0_2))
-           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef B (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_3 "FS[3]") (joined
-           (portRef Q (instanceRef FS_3))
-           (portRef A1 (instanceRef FS_cry_0_2))
-           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_10 "FS[10]") (joined
-           (portRef Q (instanceRef FS_10))
-           (portRef A0 (instanceRef FS_cry_0_10))
-           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef nUFMCS15_0_a2))
-          ))
-          (net (rename FS_11 "FS[11]") (joined
-           (portRef Q (instanceRef FS_11))
-           (portRef A1 (instanceRef FS_cry_0_10))
-           (portRef A (instanceRef InitReady3_0_a2_3))
-           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef C (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_12 "FS[12]") (joined
-           (portRef Q (instanceRef FS_12))
-           (portRef A0 (instanceRef FS_cry_0_12))
-           (portRef A (instanceRef InitReady3_0_a2_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net (rename FS_13 "FS[13]") (joined
-           (portRef Q (instanceRef FS_13))
-           (portRef A1 (instanceRef FS_cry_0_12))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef B (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_14 "FS[14]") (joined
-           (portRef Q (instanceRef FS_14))
-           (portRef A0 (instanceRef FS_cry_0_14))
-           (portRef B (instanceRef InitReady3_0_a2_3))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
-          ))
-          (net (rename FS_15 "FS[15]") (joined
-           (portRef Q (instanceRef FS_15))
-           (portRef A1 (instanceRef FS_cry_0_14))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_16 "FS[16]") (joined
-           (portRef Q (instanceRef FS_16))
-           (portRef A0 (instanceRef FS_cry_0_16))
-           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef B (instanceRef InitReady3_0_a2))
-          ))
-          (net (rename FS_17 "FS[17]") (joined
-           (portRef Q (instanceRef FS_17))
-           (portRef A1 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef D (instanceRef InitReady3_0_a2_5))
-          ))
-          (net PHI2r2 (joined
-           (portRef Q (instanceRef PHI2r2))
-           (portRef C (instanceRef un1_FS_14_i_a2))
-           (portRef C (instanceRef PHI2r3_RNITCN41))
-           (portRef D (instanceRef PHI2r3))
-          ))
-          (net CmdUFMCS (joined
-           (portRef Q (instanceRef CmdUFMCS))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-          ))
-          (net CASr2 (joined
-           (portRef Q (instanceRef CASr2))
-           (portRef A (instanceRef nRCAS_RNO_1))
-           (portRef A (instanceRef nRWE_RNO_2))
-           (portRef A (instanceRef RCKEEN_8_u_1_0))
-           (portRef D (instanceRef CASr3))
-           (portRef D (instanceRef nRCS_RNO_0))
-          ))
-          (net CASr (joined
-           (portRef Q (instanceRef CASr))
-           (portRef D (instanceRef CASr2))
-          ))
-          (net PHI2r (joined
-           (portRef Q (instanceRef PHI2r))
-           (portRef D (instanceRef PHI2r2))
-          ))
-          (net RASr (joined
-           (portRef Q (instanceRef RASr))
-           (portRef A (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RASr2))
-          ))
-          (net (rename Bank_0 "Bank[0]") (joined
-           (portRef Q (instanceRef Bank_0))
-           (portRef A (instanceRef C1WR_0_a2_0))
-          ))
-          (net (rename Bank_1 "Bank[1]") (joined
-           (portRef Q (instanceRef Bank_1))
-           (portRef B (instanceRef C1WR_0_a2_0))
-          ))
-          (net (rename Bank_3 "Bank[3]") (joined
-           (portRef Q (instanceRef Bank_3))
-           (portRef A (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net (rename Bank_4 "Bank[4]") (joined
-           (portRef Q (instanceRef Bank_4))
-           (portRef B (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net (rename Bank_5 "Bank[5]") (joined
-           (portRef Q (instanceRef Bank_5))
-           (portRef B (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename Bank_6 "Bank[6]") (joined
-           (portRef Q (instanceRef Bank_6))
-           (portRef C (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename Bank_7 "Bank[7]") (joined
-           (portRef Q (instanceRef Bank_7))
-           (portRef D (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename RowA_0 "RowA[0]") (joined
-           (portRef Q (instanceRef RowA_0))
-           (portRef B (instanceRef un9_RA_0))
-          ))
-          (net (rename RowA_1 "RowA[1]") (joined
-           (portRef Q (instanceRef RowA_1))
-           (portRef B (instanceRef un9_RA_1))
-          ))
-          (net (rename RowA_2 "RowA[2]") (joined
-           (portRef Q (instanceRef RowA_2))
-           (portRef B (instanceRef un9_RA_2))
-          ))
-          (net (rename RowA_3 "RowA[3]") (joined
-           (portRef Q (instanceRef RowA_3))
-           (portRef B (instanceRef un9_RA_3))
-          ))
-          (net (rename RowA_4 "RowA[4]") (joined
-           (portRef Q (instanceRef RowA_4))
-           (portRef B (instanceRef un9_RA_4))
-          ))
-          (net (rename RowA_5 "RowA[5]") (joined
-           (portRef Q (instanceRef RowA_5))
-           (portRef B (instanceRef un9_RA_5))
-          ))
-          (net (rename RowA_6 "RowA[6]") (joined
-           (portRef Q (instanceRef RowA_6))
-           (portRef B (instanceRef un9_RA_6))
-          ))
-          (net (rename RowA_7 "RowA[7]") (joined
-           (portRef Q (instanceRef RowA_7))
-           (portRef B (instanceRef un9_RA_7))
-          ))
-          (net (rename RowA_8 "RowA[8]") (joined
-           (portRef Q (instanceRef RowA_8))
-           (portRef B (instanceRef un9_RA_8))
-          ))
-          (net (rename RowA_9 "RowA[9]") (joined
-           (portRef Q (instanceRef RowA_9))
-           (portRef B (instanceRef un9_RA_9))
-          ))
-          (net (rename WRD_0 "WRD[0]") (joined
-           (portRef Q (instanceRef WRD_0))
-           (portRef I (instanceRef RD_pad_0))
-          ))
-          (net (rename WRD_1 "WRD[1]") (joined
-           (portRef Q (instanceRef WRD_1))
-           (portRef I (instanceRef RD_pad_1))
-          ))
-          (net (rename WRD_2 "WRD[2]") (joined
-           (portRef Q (instanceRef WRD_2))
-           (portRef I (instanceRef RD_pad_2))
-          ))
-          (net (rename WRD_3 "WRD[3]") (joined
-           (portRef Q (instanceRef WRD_3))
-           (portRef I (instanceRef RD_pad_3))
-          ))
-          (net (rename WRD_4 "WRD[4]") (joined
-           (portRef Q (instanceRef WRD_4))
-           (portRef I (instanceRef RD_pad_4))
-          ))
-          (net (rename WRD_5 "WRD[5]") (joined
-           (portRef Q (instanceRef WRD_5))
-           (portRef I (instanceRef RD_pad_5))
-          ))
-          (net (rename WRD_6 "WRD[6]") (joined
-           (portRef Q (instanceRef WRD_6))
-           (portRef I (instanceRef RD_pad_6))
-          ))
-          (net (rename WRD_7 "WRD[7]") (joined
-           (portRef Q (instanceRef WRD_7))
-           (portRef I (instanceRef RD_pad_7))
-          ))
-          (net nRowColSel (joined
-           (portRef Q (instanceRef nRowColSel))
-           (portRef B (instanceRef RDQML))
-           (portRef B (instanceRef RDQMH))
-           (portRef C (instanceRef un9_RA_9))
-           (portRef C (instanceRef un9_RA_7))
-           (portRef C (instanceRef un9_RA_6))
-           (portRef C (instanceRef un9_RA_5))
-           (portRef C (instanceRef un9_RA_4))
-           (portRef C (instanceRef un9_RA_3))
-           (portRef C (instanceRef un9_RA_2))
-           (portRef C (instanceRef un9_RA_1))
-           (portRef C (instanceRef un9_RA_0))
-           (portRef C (instanceRef un9_RA_8))
-          ))
-          (net RASr3 (joined
-           (portRef Q (instanceRef RASr3))
-           (portRef C (instanceRef RCKE_2_0))
-          ))
-          (net LEDEN (joined
-           (portRef Q (instanceRef LEDEN))
-           (portRef B (instanceRef LED_pad_RNO))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef A (instanceRef CmdLEDEN_RNO))
-          ))
-          (net CmdLEDEN (joined
-           (portRef Q (instanceRef CmdLEDEN))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef A (instanceRef LEDEN_5_i_m2))
-          ))
-          (net Cmdn8MEGEN (joined
-           (portRef Q (instanceRef Cmdn8MEGEN))
-           (portRef A (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net PHI2r3 (joined
-           (portRef Q (instanceRef PHI2r3))
-           (portRef D (instanceRef un1_FS_14_i_a2))
-           (portRef D (instanceRef PHI2r3_RNITCN41))
-          ))
-          (net CmdSubmitted (joined
-           (portRef Q (instanceRef CmdSubmitted))
-           (portRef A (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef PHI2r3_RNITCN41))
-           (portRef B (instanceRef CmdSubmitted_RNO))
-          ))
-          (net (rename FS_4 "FS[4]") (joined
-           (portRef Q (instanceRef FS_4))
-           (portRef A0 (instanceRef FS_cry_0_4))
-           (portRef B (instanceRef UFMCLK_r_i_m2))
-           (portRef A (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net InitReady3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef InitReady_RNO))
-          ))
-          (net RCKEEN (joined
-           (portRef Q (instanceRef RCKEEN))
-           (portRef D (instanceRef RCKE_2_0))
-          ))
-          (net RA11_2 (joined
-           (portRef Z (instanceRef RA11_2))
-           (portRef D (instanceRef RA11))
-          ))
-          (net XOR8MEG (joined
-           (portRef Q (instanceRef XOR8MEG))
-           (portRef B (instanceRef RA11_2))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_0))
-          ))
-          (net nRRAS_0_sqmuxa (joined
-           (portRef Z (instanceRef nRowColSel_RNO))
-           (portRef CD (instanceRef nRowColSel))
-          ))
-          (net nUFMCS15 (joined
-           (portRef Z (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef B (instanceRef UFMCLK_RNO))
-           (portRef B (instanceRef UFMSDI_RNO))
-          ))
-          (net Ready_0_sqmuxa (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef A (instanceRef Ready_fast_RNO))
-          ))
-          (net RCKE_2 (joined
-           (portRef Z (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RCKE))
-          ))
-          (net nRCAS_0_sqmuxa_1 (joined
-           (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef nRCAS_RNO))
-           (portRef C (instanceRef nRWE_RNO))
-          ))
-          (net XOR8MEG18 (joined
-           (portRef Z (instanceRef XOR8MEG18_0_a2))
-           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdLEDEN))
-           (portRef SP (instanceRef Cmdn8MEGEN))
-           (portRef SP (instanceRef XOR8MEG))
-          ))
-          (net CmdEnable (joined
-           (portRef Q (instanceRef CmdEnable))
-           (portRef A (instanceRef XOR8MEG18_0_a2))
-           (portRef B (instanceRef CmdEnable_s_am))
-           (portRef A (instanceRef CmdEnable_s_bm))
-          ))
-          (net CmdEnable16 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef ADSubmitted_r))
-           (portRef C0 (instanceRef CmdEnable_s))
-           (portRef A (instanceRef C1Submitted_RNO))
-          ))
-          (net CmdEnable17 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef ADSubmitted_r))
-           (portRef A (instanceRef CmdEnable_s_am))
-          ))
-          (net CmdSubmitted_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdSubmitted_RNO))
-          ))
-          (net CmdUFMCLK_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdUFMCLK))
-           (portRef SP (instanceRef CmdUFMCS))
-           (portRef SP (instanceRef CmdUFMSDI))
-          ))
-          (net CmdUFMCLK (joined
-           (portRef Q (instanceRef CmdUFMCLK))
-           (portRef B (instanceRef UFMCLK_RNO_0))
-          ))
-          (net CmdUFMSDI (joined
-           (portRef Q (instanceRef CmdUFMSDI))
-           (portRef A (instanceRef UFMSDI_RNO_0))
-          ))
-          (net ADSubmitted (joined
-           (portRef Q (instanceRef ADSubmitted))
-           (portRef A (instanceRef ADSubmitted_r))
-           (portRef B (instanceRef CmdEnable_s_bm))
-          ))
-          (net C1Submitted_RNO (joined
-           (portRef Z (instanceRef C1Submitted_RNO))
-           (portRef D (instanceRef C1Submitted))
-          ))
-          (net ADSubmitted_r (joined
-           (portRef Z (instanceRef ADSubmitted_r))
-           (portRef D (instanceRef ADSubmitted))
-          ))
-          (net UFMSDI_RNO (joined
-           (portRef Z (instanceRef UFMSDI_RNO))
-           (portRef D (instanceRef UFMSDI))
-          ))
-          (net CmdEnable_s (joined
-           (portRef Z (instanceRef CmdEnable_s))
-           (portRef D (instanceRef CmdEnable))
-          ))
-          (net nRowColSel_0_0 (joined
-           (portRef Z (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRowColSel))
-          ))
-          (net RCKEEN_8 (joined
-           (portRef Z (instanceRef RCKEEN_8_u))
-           (portRef D (instanceRef RCKEEN))
-          ))
-          (net N_31 (joined
-           (portRef Z (instanceRef un1_FS_14_i_0))
-           (portRef SP (instanceRef n8MEGEN))
-          ))
-          (net N_33 (joined
-           (portRef Z (instanceRef un1_FS_13_i_0))
-           (portRef SP (instanceRef LEDEN))
-          ))
-          (net N_24 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i))
-           (portRef B (instanceRef nRCS_RNO))
-          ))
-          (net N_41 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef A (instanceRef nRCAS_RNO))
-          ))
-          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
-           (portRef Z (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef nRRAS_5_u_i_0))
-           (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef D (instanceRef S_1))
-           (portRef D (instanceRef RCKEEN_8_u_RNO))
-          ))
-          (net N_159 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef D (instanceRef RA10_RNO))
-          ))
-          (net N_165 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef Ready_RNO))
-          ))
-          (net N_95_5 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_5))
-           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef D (instanceRef InitReady3_0_a2))
-          ))
-          (net N_95_3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef C (instanceRef InitReady3_0_a2))
-          ))
-          (net N_51 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef D (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef B (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_126 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
-           (portRef C (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_151 (joined
-           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef C (instanceRef UFMSDI_RNO_0))
-           (portRef D (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net N_137_8 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_8))
-           (portRef C (instanceRef un1_FS_13_i_0))
-           (portRef C (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_129 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef UFMCLK_RNO_0))
-          ))
-          (net N_155 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef IS_RNO_0))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRRAS_RNO))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_56_i (joined
-           (portRef Z (instanceRef IS_n1_0_x2))
-           (portRef D (instanceRef IS_1))
-          ))
-          (net N_160 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef nRRAS_RNO))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_136 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef un1_FS_13_i_0))
-           (portRef A (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_69 (joined
-           (portRef Z (instanceRef n8MEGEN_5_i_m2))
-           (portRef D (instanceRef n8MEGEN))
-          ))
-          (net N_70 (joined
-           (portRef Z (instanceRef LEDEN_5_i_m2))
-           (portRef D (instanceRef LEDEN))
-          ))
-          (net N_137_6 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef un1_FS_13_i_0))
-           (portRef B (instanceRef un1_FS_14_i_0))
-          ))
-          (net XOR8MEG_3 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef D (instanceRef XOR8MEG))
-          ))
-          (net CmdEnable16_1 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_1))
-           (portRef A (instanceRef CmdEnable16_0_a2_5))
-          ))
-          (net N_43 (joined
-           (portRef Z (instanceRef CmdEnable17_0_o2))
-           (portRef D (instanceRef CmdEnable17_0_a2_4))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_147 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0))
-           (portRef A (instanceRef un1_CMDWR))
-           (portRef C (instanceRef CmdEnable16_0_a2))
-           (portRef B (instanceRef C1WR_0_a2))
-           (portRef D (instanceRef XOR8MEG18_0_a2))
-           (portRef D (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef C1Submitted_RNO))
-          ))
-          (net CmdEnable16_4 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_4))
-           (portRef A (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net un1_Din_4 (joined
-           (portRef Z (instanceRef un1_Din_4))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_0))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a3_2))
-          ))
-          (net N_171 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a3_3))
-          ))
-          (net N_128 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_152 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef CmdLEDEN_RNO))
-           (portRef B (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net N_132 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef B (instanceRef CmdLEDEN_RNO))
-          ))
-          (net N_133 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef C (instanceRef CmdLEDEN_RNO))
-          ))
-          (net un1_CMDWR (joined
-           (portRef Z (instanceRef un1_CMDWR))
-           (portRef C (instanceRef CmdEnable_s_am))
-          ))
-          (net N_179 (joined
-           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
-           (portRef B (instanceRef nRowColSel_0_0))
-          ))
-          (net XOR8MEG_3_u_0_a3_2 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a3_3))
-          ))
-          (net UFMCLK_r_i_a2_2_2 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef C (instanceRef UFMCLK_RNO_0))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-          ))
-          (net UFMCLK_RNO (joined
-           (portRef Z (instanceRef UFMCLK_RNO))
-           (portRef D (instanceRef UFMCLK))
-          ))
-          (net UFMSDI_ens2_i_a0 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
-           (portRef B (instanceRef UFMSDI_RNO_0))
-          ))
-          (net RCKEEN_8_u_0_0 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_RNO))
-           (portRef B (instanceRef RCKEEN_8_u))
-          ))
-          (net RCKEEN_8_u_0_a2_1_out (joined
-           (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef D (instanceRef nRCS_RNO))
-          ))
-          (net nCRAS_c_i (joined
-           (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef CK (instanceRef CBR))
-           (portRef CK (instanceRef CBR_fast))
-           (portRef CK (instanceRef FWEr))
-           (portRef CK (instanceRef FWEr_fast))
-           (portRef CK (instanceRef RBA_1))
-           (portRef CK (instanceRef RBA_0))
-           (portRef CK (instanceRef RowA_9))
-           (portRef CK (instanceRef RowA_8))
-           (portRef CK (instanceRef RowA_7))
-           (portRef CK (instanceRef RowA_6))
-           (portRef CK (instanceRef RowA_5))
-           (portRef CK (instanceRef RowA_4))
-           (portRef CK (instanceRef RowA_3))
-           (portRef CK (instanceRef RowA_2))
-           (portRef CK (instanceRef RowA_1))
-           (portRef CK (instanceRef RowA_0))
-          ))
-          (net N_159_i (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef SP (instanceRef IS_3))
-           (portRef SP (instanceRef IS_2))
-           (portRef SP (instanceRef IS_1))
-          ))
-          (net RD_1_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef T (instanceRef RD_pad_0))
-           (portRef T (instanceRef RD_pad_1))
-           (portRef T (instanceRef RD_pad_2))
-           (portRef T (instanceRef RD_pad_3))
-           (portRef T (instanceRef RD_pad_4))
-           (portRef T (instanceRef RD_pad_5))
-           (portRef T (instanceRef RD_pad_6))
-           (portRef T (instanceRef RD_pad_7))
-          ))
-          (net N_28_i (joined
-           (portRef Z (instanceRef nRCS_RNO))
-           (portRef D (instanceRef nRCS))
-          ))
-          (net N_37_i (joined
-           (portRef Z (instanceRef nRCAS_RNO))
-           (portRef D (instanceRef nRCAS))
-          ))
-          (net N_24_i (joined
-           (portRef Z (instanceRef nRRAS_RNO))
-           (portRef D (instanceRef nRRAS))
-          ))
-          (net nUFMCS_s_0_N_5_i (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef D (instanceRef nUFMCS))
-          ))
-          (net N_39_i (joined
-           (portRef Z (instanceRef nRWE_RNO))
-           (portRef D (instanceRef nRWE))
-          ))
-          (net N_64_i_i (joined
-           (portRef Z (instanceRef IS_RNO_0))
-           (portRef D (instanceRef IS_0))
-          ))
-          (net N_61_i_i (joined
-           (portRef Z (instanceRef IS_RNO_3))
-           (portRef D (instanceRef IS_3))
-          ))
-          (net N_60_i_i (joined
-           (portRef Z (instanceRef IS_RNO_2))
-           (portRef D (instanceRef IS_2))
-          ))
-          (net N_177_i (joined
-           (portRef Z (instanceRef S_RNO_0))
-           (portRef D (instanceRef S_0))
-          ))
-          (net N_21_i (joined
-           (portRef Z (instanceRef CmdLEDEN_RNO))
-           (portRef D (instanceRef CmdLEDEN))
-          ))
-          (net N_19_i (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_RNO))
-           (portRef D (instanceRef Cmdn8MEGEN))
-          ))
-          (net N_139_i (joined
-           (portRef Z (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef A (instanceRef UFMCLK_RNO))
-           (portRef A (instanceRef UFMSDI_RNO))
-          ))
-          (net (rename FS_cry_0 "FS_cry[0]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_0))
-          ))
-          (net (rename FS_s_0 "FS_s[0]") (joined
-           (portRef S0 (instanceRef FS_cry_0_0))
-           (portRef D (instanceRef FS_0))
-          ))
-          (net (rename FS_cry_1 "FS_cry[1]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_0))
-           (portRef CIN (instanceRef FS_cry_0_2))
-          ))
-          (net (rename FS_s_1 "FS_s[1]") (joined
-           (portRef S1 (instanceRef FS_cry_0_0))
-           (portRef D (instanceRef FS_1))
-          ))
-          (net (rename FS_cry_2 "FS_cry[2]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_2))
-          ))
-          (net (rename FS_s_2 "FS_s[2]") (joined
-           (portRef S0 (instanceRef FS_cry_0_2))
-           (portRef D (instanceRef FS_2))
-          ))
-          (net (rename FS_cry_3 "FS_cry[3]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_2))
-           (portRef CIN (instanceRef FS_cry_0_4))
-          ))
-          (net (rename FS_s_3 "FS_s[3]") (joined
-           (portRef S1 (instanceRef FS_cry_0_2))
-           (portRef D (instanceRef FS_3))
-          ))
-          (net (rename FS_cry_4 "FS_cry[4]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_4))
-          ))
-          (net (rename FS_s_4 "FS_s[4]") (joined
-           (portRef S0 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef FS_4))
-          ))
-          (net (rename FS_cry_5 "FS_cry[5]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_4))
-           (portRef CIN (instanceRef FS_cry_0_6))
-          ))
-          (net (rename FS_s_5 "FS_s[5]") (joined
-           (portRef S1 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef FS_5))
-          ))
-          (net (rename FS_cry_6 "FS_cry[6]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_6))
-          ))
-          (net (rename FS_s_6 "FS_s[6]") (joined
-           (portRef S0 (instanceRef FS_cry_0_6))
-           (portRef D (instanceRef FS_6))
-          ))
-          (net (rename FS_cry_7 "FS_cry[7]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_6))
-           (portRef CIN (instanceRef FS_cry_0_8))
-          ))
-          (net (rename FS_s_7 "FS_s[7]") (joined
-           (portRef S1 (instanceRef FS_cry_0_6))
-           (portRef D (instanceRef FS_7))
-          ))
-          (net (rename FS_cry_8 "FS_cry[8]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_8))
-          ))
-          (net (rename FS_s_8 "FS_s[8]") (joined
-           (portRef S0 (instanceRef FS_cry_0_8))
-           (portRef D (instanceRef FS_8))
-          ))
-          (net (rename FS_cry_9 "FS_cry[9]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_8))
-           (portRef CIN (instanceRef FS_cry_0_10))
-          ))
-          (net (rename FS_s_9 "FS_s[9]") (joined
-           (portRef S1 (instanceRef FS_cry_0_8))
-           (portRef D (instanceRef FS_9))
-          ))
-          (net (rename FS_cry_10 "FS_cry[10]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_10))
-          ))
-          (net (rename FS_s_10 "FS_s[10]") (joined
-           (portRef S0 (instanceRef FS_cry_0_10))
-           (portRef D (instanceRef FS_10))
-          ))
-          (net (rename FS_cry_11 "FS_cry[11]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_10))
-           (portRef CIN (instanceRef FS_cry_0_12))
-          ))
-          (net (rename FS_s_11 "FS_s[11]") (joined
-           (portRef S1 (instanceRef FS_cry_0_10))
-           (portRef D (instanceRef FS_11))
-          ))
-          (net (rename FS_cry_12 "FS_cry[12]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_12))
-          ))
-          (net (rename FS_s_12 "FS_s[12]") (joined
-           (portRef S0 (instanceRef FS_cry_0_12))
-           (portRef D (instanceRef FS_12))
-          ))
-          (net (rename FS_cry_13 "FS_cry[13]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_12))
-           (portRef CIN (instanceRef FS_cry_0_14))
-          ))
-          (net (rename FS_s_13 "FS_s[13]") (joined
-           (portRef S1 (instanceRef FS_cry_0_12))
-           (portRef D (instanceRef FS_13))
-          ))
-          (net (rename FS_cry_14 "FS_cry[14]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_14))
-          ))
-          (net (rename FS_s_14 "FS_s[14]") (joined
-           (portRef S0 (instanceRef FS_cry_0_14))
-           (portRef D (instanceRef FS_14))
-          ))
-          (net (rename FS_cry_15 "FS_cry[15]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_14))
-           (portRef CIN (instanceRef FS_cry_0_16))
-          ))
-          (net (rename FS_s_15 "FS_s[15]") (joined
-           (portRef S1 (instanceRef FS_cry_0_14))
-           (portRef D (instanceRef FS_15))
-          ))
-          (net (rename FS_cry_16 "FS_cry[16]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_16))
-          ))
-          (net (rename FS_s_16 "FS_s[16]") (joined
-           (portRef S0 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef FS_16))
-          ))
-          (net (rename FS_s_17 "FS_s[17]") (joined
-           (portRef S1 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef FS_17))
-          ))
-          (net RA10s_i (joined
-           (portRef Z (instanceRef RA10_RNO))
-           (portRef PD (instanceRef RA10))
-          ))
-          (net Cmdn8MEGEN_4_u_i_0 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
-           (portRef A (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net UFMSDI_ens2_i_o2_0_3 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net C1WR_0_a2_0_3 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_3))
-           (portRef C (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net C1WR_0_a2_0_4 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net C1WR_0_a2_0_10 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_10))
-           (portRef C (instanceRef C1WR_0_a2_0))
-          ))
-          (net C1WR_0_a2_0_11 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_11))
-           (portRef D (instanceRef C1WR_0_a2_0))
-          ))
-          (net Ready_0_sqmuxa_0_a3_2 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef Ready_RNO))
-          ))
-          (net UFMSDI_ens2_i_a2_4_2 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net CmdEnable16_0_a2_4 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef CmdEnable16_0_a2))
-          ))
-          (net CmdEnable16_0_a2_5 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_5))
-           (portRef B (instanceRef CmdEnable16_0_a2))
-          ))
-          (net nRRAS_5_u_i_0 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0))
-           (portRef A (instanceRef nRRAS_RNO))
-           (portRef D (instanceRef nRRAS_5_u_i))
-          ))
-          (net CmdEnable17_0_a2_3 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable17_0_a2))
-          ))
-          (net CmdEnable17_0_a2_4 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_4))
-           (portRef B (instanceRef CmdEnable17_0_a2))
-          ))
-          (net un1_FS_13_i_a2_1 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_1))
-           (portRef D (instanceRef un1_FS_13_i_0))
-          ))
-          (net un1_FS_14_i_a2_0_1 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_14_i_0))
-          ))
-          (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_16))
-          ))
-          (net RCKEEN_8_u_1 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_1_0))
-           (portRef C (instanceRef RCKEEN_8_u))
-          ))
-          (net N_28_i_1 (joined
-           (portRef Z (instanceRef nRCS_RNO_0))
-           (portRef C (instanceRef nRCS_RNO))
-          ))
-          (net m18_0_a3_3 (joined
-           (portRef Z (instanceRef nRWE_RNO_5))
-           (portRef C (instanceRef nRWE_RNO_4))
-          ))
-          (net m18_0_a2_1 (joined
-           (portRef Z (instanceRef nRWE_RNO_1))
-           (portRef D (instanceRef nRWE_RNO))
-          ))
-          (net m6_0_a2_2 (joined
-           (portRef Z (instanceRef nRWE_RNO_2))
-           (portRef D (instanceRef nRWE_RNO_0))
-          ))
-          (net G_17_1 (joined
-           (portRef Z (instanceRef nRWE_RNO_0))
-           (portRef B (instanceRef nRWE_RNO))
-          ))
-          (net g0_1 (joined
-           (portRef Z (instanceRef nRCAS_RNO_0))
-           (portRef D (instanceRef nRCAS_RNO))
-          ))
-          (net g4_0_0_0 (joined
-           (portRef Z (instanceRef nRCAS_RNO_1))
-           (portRef D (instanceRef nRCAS_RNO_0))
-          ))
-          (net CBR_fast (joined
-           (portRef Q (instanceRef CBR_fast))
-           (portRef A (instanceRef nRCAS_RNO_0))
-           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-          ))
-          (net FWEr_fast (joined
-           (portRef Q (instanceRef FWEr_fast))
-           (portRef C (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef nRCS_RNO_0))
-          ))
-          (net Ready_fast (joined
-           (portRef Q (instanceRef Ready_fast))
-           (portRef B (instanceRef Ready_fast_RNO))
-           (portRef A (instanceRef Ready_fast_RNI29NA))
-          ))
-          (net UFMSDI_r_xx_mm_1 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_0))
-           (portRef D (instanceRef UFMSDI_RNO))
-          ))
-          (net UFMCLK_r_i_m4_xx_mm_1 (joined
-           (portRef Z (instanceRef UFMCLK_RNO_0))
-           (portRef D (instanceRef UFMCLK_RNO))
-          ))
-          (net nUFMCS_s_0_N_5_i_N_2L1 (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
-          ))
-          (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
-           (portRef Z (instanceRef XOR8MEG_CN))
-           (portRef CK (instanceRef ADSubmitted))
-           (portRef CK (instanceRef C1Submitted))
-           (portRef CK (instanceRef CmdEnable))
-           (portRef CK (instanceRef CmdLEDEN))
-           (portRef CK (instanceRef CmdSubmitted))
-           (portRef CK (instanceRef CmdUFMCLK))
-           (portRef CK (instanceRef CmdUFMCS))
-           (portRef CK (instanceRef CmdUFMSDI))
-           (portRef CK (instanceRef Cmdn8MEGEN))
-           (portRef CK (instanceRef XOR8MEG))
-          ))
-          (net VCC (joined
-           (portRef Z (instanceRef VCC))
-           (portRef CIN (instanceRef FS_cry_0_0))
-           (portRef GSR (instanceRef GSR_INST))
-          ))
-          (net GND (joined
-           (portRef Z (instanceRef GND))
-           (portRef D1 (instanceRef FS_cry_0_0))
-           (portRef C1 (instanceRef FS_cry_0_0))
-           (portRef B1 (instanceRef FS_cry_0_0))
-           (portRef D0 (instanceRef FS_cry_0_0))
-           (portRef C0 (instanceRef FS_cry_0_0))
-           (portRef B0 (instanceRef FS_cry_0_0))
-           (portRef D1 (instanceRef FS_cry_0_2))
-           (portRef C1 (instanceRef FS_cry_0_2))
-           (portRef B1 (instanceRef FS_cry_0_2))
-           (portRef D0 (instanceRef FS_cry_0_2))
-           (portRef C0 (instanceRef FS_cry_0_2))
-           (portRef B0 (instanceRef FS_cry_0_2))
-           (portRef D1 (instanceRef FS_cry_0_4))
-           (portRef C1 (instanceRef FS_cry_0_4))
-           (portRef B1 (instanceRef FS_cry_0_4))
-           (portRef D0 (instanceRef FS_cry_0_4))
-           (portRef C0 (instanceRef FS_cry_0_4))
-           (portRef B0 (instanceRef FS_cry_0_4))
-           (portRef D1 (instanceRef FS_cry_0_6))
-           (portRef C1 (instanceRef FS_cry_0_6))
-           (portRef B1 (instanceRef FS_cry_0_6))
-           (portRef D0 (instanceRef FS_cry_0_6))
-           (portRef C0 (instanceRef FS_cry_0_6))
-           (portRef B0 (instanceRef FS_cry_0_6))
-           (portRef D1 (instanceRef FS_cry_0_8))
-           (portRef C1 (instanceRef FS_cry_0_8))
-           (portRef B1 (instanceRef FS_cry_0_8))
-           (portRef D0 (instanceRef FS_cry_0_8))
-           (portRef C0 (instanceRef FS_cry_0_8))
-           (portRef B0 (instanceRef FS_cry_0_8))
-           (portRef D1 (instanceRef FS_cry_0_10))
-           (portRef C1 (instanceRef FS_cry_0_10))
-           (portRef B1 (instanceRef FS_cry_0_10))
-           (portRef D0 (instanceRef FS_cry_0_10))
-           (portRef C0 (instanceRef FS_cry_0_10))
-           (portRef B0 (instanceRef FS_cry_0_10))
-           (portRef D1 (instanceRef FS_cry_0_12))
-           (portRef C1 (instanceRef FS_cry_0_12))
-           (portRef B1 (instanceRef FS_cry_0_12))
-           (portRef D0 (instanceRef FS_cry_0_12))
-           (portRef C0 (instanceRef FS_cry_0_12))
-           (portRef B0 (instanceRef FS_cry_0_12))
-           (portRef D1 (instanceRef FS_cry_0_14))
-           (portRef C1 (instanceRef FS_cry_0_14))
-           (portRef B1 (instanceRef FS_cry_0_14))
-           (portRef D0 (instanceRef FS_cry_0_14))
-           (portRef C0 (instanceRef FS_cry_0_14))
-           (portRef B0 (instanceRef FS_cry_0_14))
-           (portRef D1 (instanceRef FS_cry_0_16))
-           (portRef C1 (instanceRef FS_cry_0_16))
-           (portRef B1 (instanceRef FS_cry_0_16))
-           (portRef D0 (instanceRef FS_cry_0_16))
-           (portRef C0 (instanceRef FS_cry_0_16))
-           (portRef B0 (instanceRef FS_cry_0_16))
-          ))
-          (net PHI2_c (joined
-           (portRef O (instanceRef PHI2_pad))
-           (portRef CK (instanceRef Bank_7))
-           (portRef CK (instanceRef Bank_6))
-           (portRef CK (instanceRef Bank_5))
-           (portRef CK (instanceRef Bank_4))
-           (portRef CK (instanceRef Bank_3))
-           (portRef CK (instanceRef Bank_2))
-           (portRef CK (instanceRef Bank_1))
-           (portRef CK (instanceRef Bank_0))
-           (portRef D (instanceRef PHI2r))
-           (portRef CK (instanceRef RA11))
-           (portRef A (instanceRef XOR8MEG_CN))
-          ))
-          (net PHI2 (joined
-           (portRef PHI2)
-           (portRef I (instanceRef PHI2_pad))
-          ))
-          (net (rename MAin_c_0 "MAin_c[0]") (joined
-           (portRef O (instanceRef MAin_pad_0))
-           (portRef B (instanceRef un1_CMDWR))
-           (portRef A (instanceRef un9_RA_0))
-           (portRef D (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef B (instanceRef XOR8MEG18_0_a2))
-           (portRef C (instanceRef CmdEnable17_0_a2))
-           (portRef D (instanceRef RowA_0))
-          ))
-          (net (rename MAin_0 "MAin[0]") (joined
-           (portRef (member main 9))
-           (portRef I (instanceRef MAin_pad_0))
-          ))
-          (net (rename MAin_c_1 "MAin_c[1]") (joined
-           (portRef O (instanceRef MAin_pad_1))
-           (portRef C (instanceRef un1_CMDWR))
-           (portRef A (instanceRef un9_RA_1))
-           (portRef C (instanceRef CmdEnable17_0_a2_4))
-           (portRef D (instanceRef CmdEnable16_0_a2_5))
-           (portRef A (instanceRef C1WR_0_a2))
-           (portRef C (instanceRef XOR8MEG18_0_a2))
-           (portRef D (instanceRef RowA_1))
-           (portRef D (instanceRef C1Submitted_RNO))
-          ))
-          (net (rename MAin_1 "MAin[1]") (joined
-           (portRef (member main 8))
-           (portRef I (instanceRef MAin_pad_1))
-          ))
-          (net (rename MAin_c_2 "MAin_c[2]") (joined
-           (portRef O (instanceRef MAin_pad_2))
-           (portRef A (instanceRef un9_RA_2))
-           (portRef A (instanceRef C1WR_0_a2_0_3))
-           (portRef D (instanceRef RowA_2))
-          ))
-          (net (rename MAin_2 "MAin[2]") (joined
-           (portRef (member main 7))
-           (portRef I (instanceRef MAin_pad_2))
-          ))
-          (net (rename MAin_c_3 "MAin_c[3]") (joined
-           (portRef O (instanceRef MAin_pad_3))
-           (portRef A (instanceRef un9_RA_3))
-           (portRef B (instanceRef C1WR_0_a2_0_3))
-           (portRef D (instanceRef RowA_3))
-          ))
-          (net (rename MAin_3 "MAin[3]") (joined
-           (portRef (member main 6))
-           (portRef I (instanceRef MAin_pad_3))
-          ))
-          (net (rename MAin_c_4 "MAin_c[4]") (joined
-           (portRef O (instanceRef MAin_pad_4))
-           (portRef A (instanceRef un9_RA_4))
-           (portRef A (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_4))
-          ))
-          (net (rename MAin_4 "MAin[4]") (joined
-           (portRef (member main 5))
-           (portRef I (instanceRef MAin_pad_4))
-          ))
-          (net (rename MAin_c_5 "MAin_c[5]") (joined
-           (portRef O (instanceRef MAin_pad_5))
-           (portRef A (instanceRef un9_RA_5))
-           (portRef B (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_5))
-          ))
-          (net (rename MAin_5 "MAin[5]") (joined
-           (portRef (member main 4))
-           (portRef I (instanceRef MAin_pad_5))
-          ))
-          (net (rename MAin_c_6 "MAin_c[6]") (joined
-           (portRef O (instanceRef MAin_pad_6))
-           (portRef A (instanceRef un9_RA_6))
-           (portRef C (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_6))
-          ))
-          (net (rename MAin_6 "MAin[6]") (joined
-           (portRef (member main 3))
-           (portRef I (instanceRef MAin_pad_6))
-          ))
-          (net (rename MAin_c_7 "MAin_c[7]") (joined
-           (portRef O (instanceRef MAin_pad_7))
-           (portRef A (instanceRef un9_RA_7))
-           (portRef D (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_7))
-          ))
-          (net (rename MAin_7 "MAin[7]") (joined
-           (portRef (member main 2))
-           (portRef I (instanceRef MAin_pad_7))
-          ))
-          (net (rename MAin_c_8 "MAin_c[8]") (joined
-           (portRef O (instanceRef MAin_pad_8))
-           (portRef A (instanceRef un9_RA_8))
-           (portRef D (instanceRef RowA_8))
-          ))
-          (net (rename MAin_8 "MAin[8]") (joined
-           (portRef (member main 1))
-           (portRef I (instanceRef MAin_pad_8))
-          ))
-          (net (rename MAin_c_9 "MAin_c[9]") (joined
-           (portRef O (instanceRef MAin_pad_9))
-           (portRef A (instanceRef RDQML))
-           (portRef A (instanceRef RDQMH))
-           (portRef A (instanceRef un9_RA_9))
-           (portRef D (instanceRef RowA_9))
-          ))
-          (net (rename MAin_9 "MAin[9]") (joined
-           (portRef (member main 0))
-           (portRef I (instanceRef MAin_pad_9))
-          ))
-          (net (rename CROW_c_0 "CROW_c[0]") (joined
-           (portRef O (instanceRef CROW_pad_0))
-           (portRef D (instanceRef RBA_0))
-          ))
-          (net (rename CROW_0 "CROW[0]") (joined
-           (portRef (member crow 1))
-           (portRef I (instanceRef CROW_pad_0))
-          ))
-          (net (rename CROW_c_1 "CROW_c[1]") (joined
-           (portRef O (instanceRef CROW_pad_1))
-           (portRef D (instanceRef RBA_1))
-          ))
-          (net (rename CROW_1 "CROW[1]") (joined
-           (portRef (member crow 0))
-           (portRef I (instanceRef CROW_pad_1))
-          ))
-          (net (rename Din_c_0 "Din_c[0]") (joined
-           (portRef O (instanceRef Din_pad_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable16_0_a2_4))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_0))
-           (portRef D (instanceRef CmdUFMSDI))
-           (portRef D (instanceRef WRD_0))
-          ))
-          (net (rename Din_0 "Din[0]") (joined
-           (portRef (member din 7))
-           (portRef I (instanceRef Din_pad_0))
-          ))
-          (net (rename Din_c_1 "Din_c[1]") (joined
-           (portRef O (instanceRef Din_pad_1))
-           (portRef A (instanceRef CmdEnable17_0_a2_3))
-           (portRef B (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef D (instanceRef Bank_1))
-           (portRef D (instanceRef CmdUFMCLK))
-           (portRef D (instanceRef WRD_1))
-          ))
-          (net (rename Din_1 "Din[1]") (joined
-           (portRef (member din 6))
-           (portRef I (instanceRef Din_pad_1))
-          ))
-          (net (rename Din_c_2 "Din_c[2]") (joined
-           (portRef O (instanceRef Din_pad_2))
-           (portRef A (instanceRef CmdEnable17_0_a2_4))
-           (portRef B (instanceRef CmdEnable16_0_a2_5))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_2))
-           (portRef D (instanceRef CmdUFMCS))
-           (portRef D (instanceRef WRD_2))
-          ))
-          (net (rename Din_2 "Din[2]") (joined
-           (portRef (member din 5))
-           (portRef I (instanceRef Din_pad_2))
-          ))
-          (net (rename Din_c_3 "Din_c[3]") (joined
-           (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdEnable17_0_o2))
-           (portRef C (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_3))
-           (portRef D (instanceRef WRD_3))
-          ))
-          (net (rename Din_3 "Din[3]") (joined
-           (portRef (member din 4))
-           (portRef I (instanceRef Din_pad_3))
-          ))
-          (net (rename Din_c_4 "Din_c[4]") (joined
-           (portRef O (instanceRef Din_pad_4))
-           (portRef D (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable16_0_a2_1))
-           (portRef A (instanceRef un1_Din_4))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef Bank_4))
-           (portRef D (instanceRef WRD_4))
-          ))
-          (net (rename Din_4 "Din[4]") (joined
-           (portRef (member din 3))
-           (portRef I (instanceRef Din_pad_4))
-          ))
-          (net (rename Din_c_5 "Din_c[5]") (joined
-           (portRef O (instanceRef Din_pad_5))
-           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdEnable17_0_o2))
-           (portRef B (instanceRef CmdEnable16_0_a2_4))
-           (portRef B (instanceRef un1_Din_4))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef Bank_5))
-           (portRef D (instanceRef WRD_5))
-          ))
-          (net (rename Din_5 "Din[5]") (joined
-           (portRef (member din 2))
-           (portRef I (instanceRef Din_pad_5))
-          ))
-          (net (rename Din_c_6 "Din_c[6]") (joined
-           (portRef O (instanceRef Din_pad_6))
-           (portRef C (instanceRef un1_Din_4))
-           (portRef A (instanceRef RA11_2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_4))
-           (portRef C (instanceRef CmdEnable16_0_a2_5))
-           (portRef D (instanceRef Bank_6))
-           (portRef D (instanceRef WRD_6))
-          ))
-          (net (rename Din_6 "Din[6]") (joined
-           (portRef (member din 1))
-           (portRef I (instanceRef Din_pad_6))
-          ))
-          (net (rename Din_c_7 "Din_c[7]") (joined
-           (portRef O (instanceRef Din_pad_7))
-           (portRef C (instanceRef CmdEnable17_0_a2_3))
-           (portRef B (instanceRef CmdEnable16_0_a2_1))
-           (portRef D (instanceRef un1_Din_4))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef Bank_7))
-           (portRef D (instanceRef WRD_7))
-          ))
-          (net (rename Din_7 "Din[7]") (joined
-           (portRef (member din 0))
-           (portRef I (instanceRef Din_pad_7))
-          ))
-          (net (rename Dout_0 "Dout[0]") (joined
-           (portRef O (instanceRef Dout_pad_0))
-           (portRef (member dout 7))
-          ))
-          (net (rename Dout_1 "Dout[1]") (joined
-           (portRef O (instanceRef Dout_pad_1))
-           (portRef (member dout 6))
-          ))
-          (net (rename Dout_2 "Dout[2]") (joined
-           (portRef O (instanceRef Dout_pad_2))
-           (portRef (member dout 5))
-          ))
-          (net (rename Dout_3 "Dout[3]") (joined
-           (portRef O (instanceRef Dout_pad_3))
-           (portRef (member dout 4))
-          ))
-          (net (rename Dout_4 "Dout[4]") (joined
-           (portRef O (instanceRef Dout_pad_4))
-           (portRef (member dout 3))
-          ))
-          (net (rename Dout_5 "Dout[5]") (joined
-           (portRef O (instanceRef Dout_pad_5))
-           (portRef (member dout 2))
-          ))
-          (net (rename Dout_6 "Dout[6]") (joined
-           (portRef O (instanceRef Dout_pad_6))
-           (portRef (member dout 1))
-          ))
-          (net (rename Dout_7 "Dout[7]") (joined
-           (portRef O (instanceRef Dout_pad_7))
-           (portRef (member dout 0))
-          ))
-          (net nCCAS_c (joined
-           (portRef O (instanceRef nCCAS_pad))
-           (portRef A (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef nCCAS_pad_RNISUR8))
-          ))
-          (net nCCAS (joined
-           (portRef nCCAS)
-           (portRef I (instanceRef nCCAS_pad))
-          ))
-          (net nCRAS_c (joined
-           (portRef O (instanceRef nCRAS_pad))
-           (portRef C (instanceRef LED_pad_RNO))
-           (portRef A (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef A (instanceRef RASr_RNO))
-          ))
-          (net nCRAS (joined
-           (portRef nCRAS)
-           (portRef I (instanceRef nCRAS_pad))
-          ))
-          (net nFWE_c (joined
-           (portRef O (instanceRef nFWE_pad))
-           (portRef C (instanceRef C1WR_0_a2_0_3))
-           (portRef B (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef nFWE_pad_RNI420B))
-          ))
-          (net nFWE (joined
-           (portRef nFWE)
-           (portRef I (instanceRef nFWE_pad))
-          ))
-          (net LED_c (joined
-           (portRef Z (instanceRef LED_pad_RNO))
-           (portRef I (instanceRef LED_pad))
-          ))
-          (net LED (joined
-           (portRef O (instanceRef LED_pad))
-           (portRef LED)
-          ))
-          (net (rename RBA_c_0 "RBA_c[0]") (joined
-           (portRef Q (instanceRef RBA_0))
-           (portRef I (instanceRef RBA_pad_0))
-          ))
-          (net (rename RBA_0 "RBA[0]") (joined
-           (portRef O (instanceRef RBA_pad_0))
-           (portRef (member rba 1))
-          ))
-          (net (rename RBA_c_1 "RBA_c[1]") (joined
-           (portRef Q (instanceRef RBA_1))
-           (portRef I (instanceRef RBA_pad_1))
-          ))
-          (net (rename RBA_1 "RBA[1]") (joined
-           (portRef O (instanceRef RBA_pad_1))
-           (portRef (member rba 0))
-          ))
-          (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Z (instanceRef un9_RA_0))
-           (portRef I (instanceRef RA_pad_0))
-          ))
-          (net (rename RA_0 "RA[0]") (joined
-           (portRef O (instanceRef RA_pad_0))
-           (portRef (member ra 11))
-          ))
-          (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Z (instanceRef un9_RA_1))
-           (portRef I (instanceRef RA_pad_1))
-          ))
-          (net (rename RA_1 "RA[1]") (joined
-           (portRef O (instanceRef RA_pad_1))
-           (portRef (member ra 10))
-          ))
-          (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Z (instanceRef un9_RA_2))
-           (portRef I (instanceRef RA_pad_2))
-          ))
-          (net (rename RA_2 "RA[2]") (joined
-           (portRef O (instanceRef RA_pad_2))
-           (portRef (member ra 9))
-          ))
-          (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Z (instanceRef un9_RA_3))
-           (portRef I (instanceRef RA_pad_3))
-          ))
-          (net (rename RA_3 "RA[3]") (joined
-           (portRef O (instanceRef RA_pad_3))
-           (portRef (member ra 8))
-          ))
-          (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Z (instanceRef un9_RA_4))
-           (portRef I (instanceRef RA_pad_4))
-          ))
-          (net (rename RA_4 "RA[4]") (joined
-           (portRef O (instanceRef RA_pad_4))
-           (portRef (member ra 7))
-          ))
-          (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Z (instanceRef un9_RA_5))
-           (portRef I (instanceRef RA_pad_5))
-          ))
-          (net (rename RA_5 "RA[5]") (joined
-           (portRef O (instanceRef RA_pad_5))
-           (portRef (member ra 6))
-          ))
-          (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Z (instanceRef un9_RA_6))
-           (portRef I (instanceRef RA_pad_6))
-          ))
-          (net (rename RA_6 "RA[6]") (joined
-           (portRef O (instanceRef RA_pad_6))
-           (portRef (member ra 5))
-          ))
-          (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Z (instanceRef un9_RA_7))
-           (portRef I (instanceRef RA_pad_7))
-          ))
-          (net (rename RA_7 "RA[7]") (joined
-           (portRef O (instanceRef RA_pad_7))
-           (portRef (member ra 4))
-          ))
-          (net (rename RA_c_8 "RA_c[8]") (joined
-           (portRef Z (instanceRef un9_RA_8))
-           (portRef I (instanceRef RA_pad_8))
-          ))
-          (net (rename RA_8 "RA[8]") (joined
-           (portRef O (instanceRef RA_pad_8))
-           (portRef (member ra 3))
-          ))
-          (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Z (instanceRef un9_RA_9))
-           (portRef I (instanceRef RA_pad_9))
-          ))
-          (net (rename RA_9 "RA[9]") (joined
-           (portRef O (instanceRef RA_pad_9))
-           (portRef (member ra 2))
-          ))
-          (net (rename RA_c_10 "RA_c[10]") (joined
-           (portRef Q (instanceRef RA10))
-           (portRef I (instanceRef RA_pad_10))
-          ))
-          (net (rename RA_10 "RA[10]") (joined
-           (portRef O (instanceRef RA_pad_10))
-           (portRef (member ra 1))
-          ))
-          (net (rename RA_c_11 "RA_c[11]") (joined
-           (portRef Q (instanceRef RA11))
-           (portRef I (instanceRef RA_pad_11))
-          ))
-          (net (rename RA_11 "RA[11]") (joined
-           (portRef O (instanceRef RA_pad_11))
-           (portRef (member ra 0))
-          ))
-          (net (rename RD_in_0 "RD_in[0]") (joined
-           (portRef O (instanceRef RD_pad_0))
-           (portRef I (instanceRef Dout_pad_0))
-          ))
-          (net (rename RD_0 "RD[0]") (joined
-           (portRef B (instanceRef RD_pad_0))
-           (portRef (member rd 7))
-          ))
-          (net (rename RD_in_1 "RD_in[1]") (joined
-           (portRef O (instanceRef RD_pad_1))
-           (portRef I (instanceRef Dout_pad_1))
-          ))
-          (net (rename RD_1 "RD[1]") (joined
-           (portRef B (instanceRef RD_pad_1))
-           (portRef (member rd 6))
-          ))
-          (net (rename RD_in_2 "RD_in[2]") (joined
-           (portRef O (instanceRef RD_pad_2))
-           (portRef I (instanceRef Dout_pad_2))
-          ))
-          (net (rename RD_2 "RD[2]") (joined
-           (portRef B (instanceRef RD_pad_2))
-           (portRef (member rd 5))
-          ))
-          (net (rename RD_in_3 "RD_in[3]") (joined
-           (portRef O (instanceRef RD_pad_3))
-           (portRef I (instanceRef Dout_pad_3))
-          ))
-          (net (rename RD_3 "RD[3]") (joined
-           (portRef B (instanceRef RD_pad_3))
-           (portRef (member rd 4))
-          ))
-          (net (rename RD_in_4 "RD_in[4]") (joined
-           (portRef O (instanceRef RD_pad_4))
-           (portRef I (instanceRef Dout_pad_4))
-          ))
-          (net (rename RD_4 "RD[4]") (joined
-           (portRef B (instanceRef RD_pad_4))
-           (portRef (member rd 3))
-          ))
-          (net (rename RD_in_5 "RD_in[5]") (joined
-           (portRef O (instanceRef RD_pad_5))
-           (portRef I (instanceRef Dout_pad_5))
-          ))
-          (net (rename RD_5 "RD[5]") (joined
-           (portRef B (instanceRef RD_pad_5))
-           (portRef (member rd 2))
-          ))
-          (net (rename RD_in_6 "RD_in[6]") (joined
-           (portRef O (instanceRef RD_pad_6))
-           (portRef I (instanceRef Dout_pad_6))
-          ))
-          (net (rename RD_6 "RD[6]") (joined
-           (portRef B (instanceRef RD_pad_6))
-           (portRef (member rd 1))
-          ))
-          (net (rename RD_in_7 "RD_in[7]") (joined
-           (portRef O (instanceRef RD_pad_7))
-           (portRef I (instanceRef Dout_pad_7))
-          ))
-          (net (rename RD_7 "RD[7]") (joined
-           (portRef B (instanceRef RD_pad_7))
-           (portRef (member rd 0))
-          ))
-          (net nRCS_c (joined
-           (portRef Q (instanceRef nRCS))
-           (portRef I (instanceRef nRCS_pad))
-          ))
-          (net nRCS (joined
-           (portRef O (instanceRef nRCS_pad))
-           (portRef nRCS)
-          ))
-          (net RCLK_c (joined
-           (portRef O (instanceRef RCLK_pad))
-           (portRef CK (instanceRef CASr))
-           (portRef CK (instanceRef CASr2))
-           (portRef CK (instanceRef CASr3))
-           (portRef CK (instanceRef FS_17))
-           (portRef CK (instanceRef FS_16))
-           (portRef CK (instanceRef FS_15))
-           (portRef CK (instanceRef FS_14))
-           (portRef CK (instanceRef FS_13))
-           (portRef CK (instanceRef FS_12))
-           (portRef CK (instanceRef FS_11))
-           (portRef CK (instanceRef FS_10))
-           (portRef CK (instanceRef FS_9))
-           (portRef CK (instanceRef FS_8))
-           (portRef CK (instanceRef FS_7))
-           (portRef CK (instanceRef FS_6))
-           (portRef CK (instanceRef FS_5))
-           (portRef CK (instanceRef FS_4))
-           (portRef CK (instanceRef FS_3))
-           (portRef CK (instanceRef FS_2))
-           (portRef CK (instanceRef FS_1))
-           (portRef CK (instanceRef FS_0))
-           (portRef CK (instanceRef IS_3))
-           (portRef CK (instanceRef IS_2))
-           (portRef CK (instanceRef IS_1))
-           (portRef CK (instanceRef IS_0))
-           (portRef CK (instanceRef InitReady))
-           (portRef CK (instanceRef LEDEN))
-           (portRef CK (instanceRef PHI2r))
-           (portRef CK (instanceRef PHI2r2))
-           (portRef CK (instanceRef PHI2r3))
-           (portRef CK (instanceRef RA10))
-           (portRef CK (instanceRef RASr))
-           (portRef CK (instanceRef RASr2))
-           (portRef CK (instanceRef RASr3))
-           (portRef CK (instanceRef RCKE))
-           (portRef CK (instanceRef RCKEEN))
-           (portRef CK (instanceRef Ready))
-           (portRef CK (instanceRef Ready_fast))
-           (portRef CK (instanceRef S_1))
-           (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef UFMCLK))
-           (portRef CK (instanceRef UFMSDI))
-           (portRef CK (instanceRef n8MEGEN))
-           (portRef CK (instanceRef nRCAS))
-           (portRef CK (instanceRef nRCS))
-           (portRef CK (instanceRef nRRAS))
-           (portRef CK (instanceRef nRWE))
-           (portRef CK (instanceRef nRowColSel))
-           (portRef CK (instanceRef nUFMCS))
-          ))
-          (net RCLK (joined
-           (portRef RCLK)
-           (portRef I (instanceRef RCLK_pad))
-          ))
-          (net RCKE_c (joined
-           (portRef Q (instanceRef RCKE))
-           (portRef C (instanceRef nRRAS_5_u_i_0))
-           (portRef I (instanceRef RCKE_pad))
-           (portRef C (instanceRef nRWE_RNO_3))
-          ))
-          (net RCKE (joined
-           (portRef O (instanceRef RCKE_pad))
-           (portRef RCKE)
-          ))
-          (net nRWE_c (joined
-           (portRef Q (instanceRef nRWE))
-           (portRef I (instanceRef nRWE_pad))
-          ))
-          (net nRWE (joined
-           (portRef O (instanceRef nRWE_pad))
-           (portRef nRWE)
-          ))
-          (net nRRAS_c (joined
-           (portRef Q (instanceRef nRRAS))
-           (portRef I (instanceRef nRRAS_pad))
-          ))
-          (net nRRAS (joined
-           (portRef O (instanceRef nRRAS_pad))
-           (portRef nRRAS)
-          ))
-          (net nRCAS_c (joined
-           (portRef Q (instanceRef nRCAS))
-           (portRef I (instanceRef nRCAS_pad))
-          ))
-          (net nRCAS (joined
-           (portRef O (instanceRef nRCAS_pad))
-           (portRef nRCAS)
-          ))
-          (net RDQMH_c (joined
-           (portRef Z (instanceRef RDQMH))
-           (portRef I (instanceRef RDQMH_pad))
-          ))
-          (net RDQMH (joined
-           (portRef O (instanceRef RDQMH_pad))
-           (portRef RDQMH)
-          ))
-          (net RDQML_c (joined
-           (portRef Z (instanceRef RDQML))
-           (portRef I (instanceRef RDQML_pad))
-          ))
-          (net RDQML (joined
-           (portRef O (instanceRef RDQML_pad))
-           (portRef RDQML)
-          ))
-          (net nUFMCS_c (joined
-           (portRef Q (instanceRef nUFMCS))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef I (instanceRef nUFMCS_pad))
-          ))
-          (net nUFMCS (joined
-           (portRef O (instanceRef nUFMCS_pad))
-           (portRef nUFMCS)
-          ))
-          (net UFMCLK_c (joined
-           (portRef Q (instanceRef UFMCLK))
-           (portRef C (instanceRef UFMCLK_RNO))
-           (portRef I (instanceRef UFMCLK_pad))
-          ))
-          (net UFMCLK (joined
-           (portRef O (instanceRef UFMCLK_pad))
-           (portRef UFMCLK)
-          ))
-          (net UFMSDI_c (joined
-           (portRef Q (instanceRef UFMSDI))
-           (portRef C (instanceRef UFMSDI_RNO))
-           (portRef I (instanceRef UFMSDI_pad))
-          ))
-          (net UFMSDI (joined
-           (portRef O (instanceRef UFMSDI_pad))
-           (portRef UFMSDI)
-          ))
-          (net UFMSDO_c (joined
-           (portRef O (instanceRef UFMSDO_pad))
-           (portRef C (instanceRef LEDEN_5_i_m2))
-           (portRef C (instanceRef n8MEGEN_5_i_m2))
-          ))
-          (net UFMSDO (joined
-           (portRef UFMSDO)
-           (portRef I (instanceRef UFMSDO_pad))
-          ))
-          (net N_460_0 (joined
-           (portRef Z (instanceRef CmdSubmitted_RNO))
-           (portRef D (instanceRef CmdSubmitted))
-          ))
-          (net N_461_0 (joined
-           (portRef Z (instanceRef InitReady_RNO))
-           (portRef D (instanceRef InitReady))
-          ))
-          (net N_462_0 (joined
-           (portRef Z (instanceRef Ready_RNO))
-           (portRef D (instanceRef Ready))
-          ))
-          (net N_463_0 (joined
-           (portRef Z (instanceRef Ready_fast_RNO))
-           (portRef D (instanceRef Ready_fast))
-          ))
-          (net nFWE_c_i (joined
-           (portRef Z (instanceRef nFWE_pad_RNI420B))
-           (portRef D (instanceRef FWEr))
-           (portRef D (instanceRef FWEr_fast))
-          ))
-          (net nCRAS_c_i_0 (joined
-           (portRef Z (instanceRef RASr_RNO))
-           (portRef D (instanceRef RASr))
-          ))
-          (net nCCAS_c_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNISUR8))
-           (portRef D (instanceRef CASr))
-           (portRef D (instanceRef CBR))
-           (portRef D (instanceRef CBR_fast))
-           (portRef CK (instanceRef WRD_7))
-           (portRef CK (instanceRef WRD_6))
-           (portRef CK (instanceRef WRD_5))
-           (portRef CK (instanceRef WRD_4))
-           (portRef CK (instanceRef WRD_3))
-           (portRef CK (instanceRef WRD_2))
-           (portRef CK (instanceRef WRD_1))
-           (portRef CK (instanceRef WRD_0))
-          ))
-          (net Ready_fast_i (joined
-           (portRef Z (instanceRef Ready_fast_RNI29NA))
-           (portRef CD (instanceRef RA11))
-           (portRef CD (instanceRef RBA_1))
-           (portRef CD (instanceRef RBA_0))
-           (portRef PD (instanceRef RowA_9))
-           (portRef CD (instanceRef RowA_8))
-           (portRef CD (instanceRef RowA_7))
-           (portRef CD (instanceRef RowA_6))
-           (portRef PD (instanceRef RowA_5))
-           (portRef CD (instanceRef RowA_4))
-           (portRef CD (instanceRef RowA_3))
-           (portRef CD (instanceRef RowA_2))
-           (portRef CD (instanceRef RowA_1))
-           (portRef CD (instanceRef RowA_0))
-          ))
-          (net (rename IS_i_0 "IS_i[0]") (joined
-           (portRef Z (instanceRef IS_i_0))
-           (portRef D (instanceRef RA10))
-          ))
-          (net RASr2_i (joined
-           (portRef Z (instanceRef RASr2_RNIAFR1))
-           (portRef CD (instanceRef S_1))
-           (portRef CD (instanceRef S_0))
-          ))
-          (net nRWE_RNO_4 (joined
-           (portRef Z (instanceRef nRWE_RNO_4))
-           (portRef BLUT (instanceRef nRWE_RNO_1))
-          ))
-          (net nRWE_RNO_3 (joined
-           (portRef Z (instanceRef nRWE_RNO_3))
-           (portRef ALUT (instanceRef nRWE_RNO_1))
-          ))
-          (net CmdEnable_s_am (joined
-           (portRef Z (instanceRef CmdEnable_s_am))
-           (portRef BLUT (instanceRef CmdEnable_s))
-          ))
-          (net CmdEnable_s_bm (joined
-           (portRef Z (instanceRef CmdEnable_s_bm))
-           (portRef ALUT (instanceRef CmdEnable_s))
-          ))
-         )
-        (property orig_inst_of (string "RAM2GS"))
-       )
-    )
-  )
-  (design RAM2GS (cellRef RAM2GS (libraryRef work))
-	(property PART (string "lcmxo640c-3") ))
-)
+(edif RAM2GS
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timeStamp 2023 8 19 20 57 11)
+      (author "Synopsys, Inc.")
+      (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
+     )
+   )
+  (library LUCENT
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell CCU2 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A0 (direction INPUT))
+           (port B0 (direction INPUT))
+           (port C0 (direction INPUT))
+           (port D0 (direction INPUT))
+           (port A1 (direction INPUT))
+           (port B1 (direction INPUT))
+           (port C1 (direction INPUT))
+           (port D1 (direction INPUT))
+           (port CIN (direction INPUT))
+           (port COUT0 (direction OUTPUT))
+           (port COUT1 (direction OUTPUT))
+           (port S0 (direction OUTPUT))
+           (port S1 (direction OUTPUT))
+         )
+        (property INJECT1_1 (string "NO"))
+        (property INJECT1_0 (string "NO"))
+        (property INIT1 (string "0000"))
+        (property INIT0 (string "0000"))
+       )
+    )
+    (cell BB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port B (direction INOUT))
+           (port I (direction INPUT))
+           (port T (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell OB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell IB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3JX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port PD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3AY (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell ORCALUT4 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port C (direction INPUT))
+           (port D (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell PFUMX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port ALUT (direction INPUT))
+           (port BLUT (direction INPUT))
+           (port C0 (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell GSR (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port GSR (direction INPUT))
+         )
+       )
+    )
+    (cell INV (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VHI (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VLO (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+  )
+  (library work
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell RAM2GS (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port PHI2 (direction INPUT))
+           (port (array (rename main "MAin[9:0]") 10) (direction INPUT))
+           (port (array (rename crow "CROW[1:0]") 2) (direction INPUT))
+           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
+           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
+           (port nCCAS (direction INPUT))
+           (port nCRAS (direction INPUT))
+           (port nFWE (direction INPUT))
+           (port LED (direction OUTPUT))
+           (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT))
+           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
+           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
+           (port nRCS (direction OUTPUT))
+           (port RCLK (direction INPUT))
+           (port RCKE (direction OUTPUT))
+           (port nRWE (direction OUTPUT))
+           (port nRRAS (direction OUTPUT))
+           (port nRCAS (direction OUTPUT))
+           (port RDQMH (direction OUTPUT))
+           (port RDQML (direction OUTPUT))
+           (port nUFMCS (direction OUTPUT))
+           (port UFMCLK (direction OUTPUT))
+           (port UFMSDI (direction OUTPUT))
+           (port UFMSDO (direction INPUT))
+         )
+         (contents
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))"))
+          )
+          (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))"))
+          )
+          (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
+          )
+          (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
+          )
+          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
+          )
+          (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))"))
+          )
+          (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A)))"))
+          )
+          (instance nRWE_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_0 "WRD[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_1 "WRD[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_2 "WRD[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_3 "WRD[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_4 "WRD[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_5 "WRD[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_6 "WRD[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_7 "WRD[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMCLK (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RBA_0 "RBA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RBA_1 "RBA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RA11 (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance RA10 (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance PHI2r (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_0 "Bank[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_1 "Bank[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_2 "Bank[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_3 "Bank[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_4 "Bank[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_5 "Bank[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_6 "Bank[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_7 "Bank[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
+          )
+          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
+          )
+          (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C !A)"))
+          )
+          (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !B)+D (!C (!B A)))"))
+          )
+          (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(B+A)))"))
+          )
+          (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(!B+!A)))"))
+          )
+          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !A+D (!C !A+C (B !A)))"))
+          )
+          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (!B A)+C !B))"))
+          )
+          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
+          )
+          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)"))
+          )
+          (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D A)"))
+          )
+          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
+          )
+          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
+          )
+          (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C !A))"))
+          )
+          (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+!A))"))
+          )
+          (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (!B A))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A)))"))
+          )
+          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+A))"))
+          )
+          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
+          )
+          (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+!A))"))
+          )
+          (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A)+C B)"))
+          )
+          (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A+B !A)"))
+          )
+          (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
+          )
+          (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
+          )
+          (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !B+D (!C (!B A)+C !B))"))
+          )
+          (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))"))
+          )
+          (instance nRWE_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance nRWE_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance nRWE_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))"))
+          )
+          (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))"))
+          )
+          (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C !B)"))
+          )
+          (instance UFMSDI_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
+          )
+          (instance UFMCLK_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B)+D (C (!B !A)))"))
+          )
+          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C B+C (B+!A)))"))
+          )
+          (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A))"))
+          )
+          (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+!A)))"))
+          )
+          (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A)))"))
+          )
+          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (!C (!B A)))"))
+          )
+          (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
+          )
+          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
+          )
+          (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A+B A)+C A)"))
+          )
+          (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C A)"))
+          )
+          (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))"))
+          )
+          (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x5002"))
+          )
+          (instance (rename FS_cry_0_14 "FS_cry_0[14]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_12 "FS_cry_0[12]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_10 "FS_cry_0[10]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_8 "FS_cry_0[8]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_6 "FS_cry_0[6]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_4 "FS_cry_0[4]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_2 "FS_cry_0[2]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (net C1WR_0_a2 (joined
+           (portRef Z (instanceRef C1WR_0_a2))
+           (portRef B (instanceRef ADSubmitted_r))
+          ))
+          (net CBR (joined
+           (portRef Q (instanceRef CBR))
+           (portRef A (instanceRef nRWE_RNO_0))
+           (portRef A (instanceRef nRCS_RNO))
+           (portRef A (instanceRef RCKEEN_8_u))
+           (portRef B (instanceRef nRowColSel_0_0_a3_0))
+           (portRef A (instanceRef LED_pad_RNO))
+          ))
+          (net C1Submitted (joined
+           (portRef Q (instanceRef C1Submitted))
+           (portRef D (instanceRef CmdEnable_s_am))
+           (portRef B (instanceRef C1Submitted_RNO))
+          ))
+          (net (rename Bank_2 "Bank[2]") (joined
+           (portRef Q (instanceRef Bank_2))
+           (portRef A (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net Ready (joined
+           (portRef Q (instanceRef Ready))
+           (portRef B (instanceRef IS_RNO_0))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef C (instanceRef nRWE_RNO_2))
+           (portRef D (instanceRef RCKEEN_8_u))
+           (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef D (instanceRef nRowColSel_0_0_a3_0))
+           (portRef D (instanceRef nRRAS_5_u_i_0))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef C (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef C0 (instanceRef nRWE_RNO_1))
+           (portRef A (instanceRef Ready_RNO))
+           (portRef A (instanceRef RCKEEN_8_u_RNO))
+           (portRef A (instanceRef nRowColSel_RNO))
+          ))
+          (net n8MEGEN (joined
+           (portRef Q (instanceRef n8MEGEN))
+           (portRef C (instanceRef RA11_2))
+           (portRef C (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net CO0 (joined
+           (portRef Q (instanceRef S_0))
+           (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef B (instanceRef nRCAS_RNO_0))
+           (portRef B (instanceRef nRWE_RNO_0))
+           (portRef B (instanceRef RCKEEN_8_u_1_0))
+           (portRef A (instanceRef S_0_i_o2_1))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef A (instanceRef S_RNO_0))
+           (portRef A (instanceRef nRowColSel_0_0))
+           (portRef B (instanceRef nRWE_RNO_4))
+           (portRef B (instanceRef nRWE_RNO_3))
+           (portRef C (instanceRef nRowColSel_RNO))
+           (portRef B (instanceRef nRCS_RNO_0))
+          ))
+          (net (rename S_1 "S[1]") (joined
+           (portRef Q (instanceRef S_1))
+           (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef C (instanceRef nRCAS_RNO))
+           (portRef C (instanceRef nRWE_RNO_0))
+           (portRef D (instanceRef RCKEEN_8_u_1_0))
+           (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef B (instanceRef S_0_i_o2_1))
+           (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef B (instanceRef S_RNO_0))
+           (portRef D (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef A (instanceRef nRWE_RNO_4))
+           (portRef A (instanceRef nRWE_RNO_3))
+           (portRef B (instanceRef nRowColSel_RNO))
+          ))
+          (net RASr2 (joined
+           (portRef Q (instanceRef RASr2))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef D (instanceRef nRWE_RNO_5))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef B (instanceRef RCKE_2_0))
+           (portRef B (instanceRef nRRAS_5_u_i_0))
+           (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef D (instanceRef RASr3))
+           (portRef D (instanceRef nRWE_RNO_3))
+           (portRef B (instanceRef RCKEEN_8_u_RNO))
+           (portRef A (instanceRef RASr2_RNIAFR1))
+          ))
+          (net InitReady (joined
+           (portRef Q (instanceRef InitReady))
+           (portRef A (instanceRef UFMCLK_RNO_0))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+           (portRef B (instanceRef LEDEN_5_i_m2))
+           (portRef B (instanceRef n8MEGEN_5_i_m2))
+           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef B (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef PHI2r3_RNITCN41))
+           (portRef C (instanceRef nUFMCS15_0_a2))
+           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef A (instanceRef UFMSDI_ens2_i_a0))
+           (portRef B (instanceRef InitReady_RNO))
+           (portRef D (instanceRef nRWE_RNO_4))
+           (portRef D (instanceRef Ready_RNO))
+           (portRef C (instanceRef RCKEEN_8_u_RNO))
+          ))
+          (net FWEr (joined
+           (portRef Q (instanceRef FWEr))
+           (portRef C (instanceRef nRCAS_RNO_0))
+           (portRef A (instanceRef nRWE_RNO))
+           (portRef C (instanceRef nRowColSel_0_0_a3_0))
+          ))
+          (net CASr3 (joined
+           (portRef Q (instanceRef CASr3))
+           (portRef B (instanceRef nRCAS_RNO_1))
+           (portRef B (instanceRef nRWE_RNO_2))
+           (portRef A (instanceRef nRowColSel_0_0_a3_0))
+           (portRef C (instanceRef nRCS_RNO_0))
+          ))
+          (net (rename IS_0 "IS[0]") (joined
+           (portRef Q (instanceRef IS_0))
+           (portRef A (instanceRef IS_RNO_0))
+           (portRef D (instanceRef nRRAS_RNO))
+           (portRef A (instanceRef nRWE_RNO_5))
+           (portRef A (instanceRef IS_n1_0_x2))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef A (instanceRef IS_RNO_2))
+           (portRef A (instanceRef nRRAS_5_u_i))
+           (portRef D (instanceRef IS_RNO_3))
+           (portRef A (instanceRef IS_i_0))
+          ))
+          (net (rename IS_3 "IS[3]") (joined
+           (portRef Q (instanceRef IS_3))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef RA10_RNO))
+           (portRef A (instanceRef IS_RNO_3))
+          ))
+          (net (rename IS_1 "IS[1]") (joined
+           (portRef Q (instanceRef IS_1))
+           (portRef B (instanceRef nRWE_RNO_5))
+           (portRef B (instanceRef IS_n1_0_x2))
+           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef B (instanceRef IS_RNO_2))
+           (portRef A (instanceRef RA10_RNO))
+           (portRef C (instanceRef IS_RNO_3))
+          ))
+          (net (rename IS_2 "IS[2]") (joined
+           (portRef Q (instanceRef IS_2))
+           (portRef C (instanceRef nRWE_RNO_5))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef C (instanceRef IS_RNO_2))
+           (portRef B (instanceRef RA10_RNO))
+           (portRef B (instanceRef IS_RNO_3))
+          ))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef Q (instanceRef FS_5))
+           (portRef A1 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef D (instanceRef un1_FS_13_i_a2_1))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2))
+          ))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef Q (instanceRef FS_6))
+           (portRef A0 (instanceRef FS_cry_0_6))
+           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef B (instanceRef un1_FS_13_i_a2_6))
+          ))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef Q (instanceRef FS_7))
+           (portRef A1 (instanceRef FS_cry_0_6))
+           (portRef C (instanceRef un1_FS_13_i_a2_6))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2))
+          ))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef Q (instanceRef FS_8))
+           (portRef A0 (instanceRef FS_cry_0_8))
+           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
+          ))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef Q (instanceRef FS_9))
+           (portRef A1 (instanceRef FS_cry_0_8))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2))
+           (portRef B (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net (rename FS_0 "FS[0]") (joined
+           (portRef Q (instanceRef FS_0))
+           (portRef A0 (instanceRef FS_cry_0_0))
+           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef A (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_1 "FS[1]") (joined
+           (portRef Q (instanceRef FS_1))
+           (portRef A1 (instanceRef FS_cry_0_0))
+           (portRef A (instanceRef un1_FS_13_i_a2_6))
+           (portRef A (instanceRef UFMCLK_r_i_m2))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef Q (instanceRef FS_2))
+           (portRef A0 (instanceRef FS_cry_0_2))
+           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef B (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_3 "FS[3]") (joined
+           (portRef Q (instanceRef FS_3))
+           (portRef A1 (instanceRef FS_cry_0_2))
+           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef C (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef Q (instanceRef FS_10))
+           (portRef A0 (instanceRef FS_cry_0_10))
+           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef D (instanceRef un1_FS_13_i_a2_6))
+           (portRef A (instanceRef InitReady3_0_a2))
+           (portRef A (instanceRef nUFMCS15_0_a2))
+          ))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef Q (instanceRef FS_11))
+           (portRef A1 (instanceRef FS_cry_0_10))
+           (portRef A (instanceRef InitReady3_0_a2_3))
+           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef C (instanceRef UFMCLK_r_i_m2))
+           (portRef B (instanceRef nUFMCS15_0_a2))
+           (portRef C (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef Q (instanceRef FS_12))
+           (portRef A0 (instanceRef FS_cry_0_12))
+           (portRef A (instanceRef InitReady3_0_a2_5))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef Q (instanceRef FS_13))
+           (portRef A1 (instanceRef FS_cry_0_12))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef B (instanceRef InitReady3_0_a2_5))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef Q (instanceRef FS_14))
+           (portRef A0 (instanceRef FS_cry_0_14))
+           (portRef B (instanceRef InitReady3_0_a2_3))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef Q (instanceRef FS_15))
+           (portRef A1 (instanceRef FS_cry_0_14))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef C (instanceRef InitReady3_0_a2_5))
+          ))
+          (net (rename FS_16 "FS[16]") (joined
+           (portRef Q (instanceRef FS_16))
+           (portRef A0 (instanceRef FS_cry_0_16))
+           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
+           (portRef B (instanceRef InitReady3_0_a2))
+          ))
+          (net (rename FS_17 "FS[17]") (joined
+           (portRef Q (instanceRef FS_17))
+           (portRef A1 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef D (instanceRef InitReady3_0_a2_5))
+          ))
+          (net PHI2r2 (joined
+           (portRef Q (instanceRef PHI2r2))
+           (portRef C (instanceRef un1_FS_14_i_a2))
+           (portRef C (instanceRef PHI2r3_RNITCN41))
+           (portRef D (instanceRef PHI2r3))
+          ))
+          (net CmdUFMCS (joined
+           (portRef Q (instanceRef CmdUFMCS))
+           (portRef A (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+          ))
+          (net CASr2 (joined
+           (portRef Q (instanceRef CASr2))
+           (portRef A (instanceRef nRCAS_RNO_1))
+           (portRef A (instanceRef nRWE_RNO_2))
+           (portRef A (instanceRef RCKEEN_8_u_1_0))
+           (portRef D (instanceRef CASr3))
+           (portRef D (instanceRef nRCS_RNO_0))
+          ))
+          (net CASr (joined
+           (portRef Q (instanceRef CASr))
+           (portRef D (instanceRef CASr2))
+          ))
+          (net PHI2r (joined
+           (portRef Q (instanceRef PHI2r))
+           (portRef D (instanceRef PHI2r2))
+          ))
+          (net RASr (joined
+           (portRef Q (instanceRef RASr))
+           (portRef A (instanceRef RCKE_2_0))
+           (portRef D (instanceRef RASr2))
+          ))
+          (net (rename Bank_0 "Bank[0]") (joined
+           (portRef Q (instanceRef Bank_0))
+           (portRef A (instanceRef C1WR_0_a2_0))
+          ))
+          (net (rename Bank_1 "Bank[1]") (joined
+           (portRef Q (instanceRef Bank_1))
+           (portRef B (instanceRef C1WR_0_a2_0))
+          ))
+          (net (rename Bank_3 "Bank[3]") (joined
+           (portRef Q (instanceRef Bank_3))
+           (portRef A (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net (rename Bank_4 "Bank[4]") (joined
+           (portRef Q (instanceRef Bank_4))
+           (portRef B (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net (rename Bank_5 "Bank[5]") (joined
+           (portRef Q (instanceRef Bank_5))
+           (portRef B (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename Bank_6 "Bank[6]") (joined
+           (portRef Q (instanceRef Bank_6))
+           (portRef C (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename Bank_7 "Bank[7]") (joined
+           (portRef Q (instanceRef Bank_7))
+           (portRef D (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename RowA_0 "RowA[0]") (joined
+           (portRef Q (instanceRef RowA_0))
+           (portRef B (instanceRef un9_RA_0))
+          ))
+          (net (rename RowA_1 "RowA[1]") (joined
+           (portRef Q (instanceRef RowA_1))
+           (portRef B (instanceRef un9_RA_1))
+          ))
+          (net (rename RowA_2 "RowA[2]") (joined
+           (portRef Q (instanceRef RowA_2))
+           (portRef B (instanceRef un9_RA_2))
+          ))
+          (net (rename RowA_3 "RowA[3]") (joined
+           (portRef Q (instanceRef RowA_3))
+           (portRef B (instanceRef un9_RA_3))
+          ))
+          (net (rename RowA_4 "RowA[4]") (joined
+           (portRef Q (instanceRef RowA_4))
+           (portRef B (instanceRef un9_RA_4))
+          ))
+          (net (rename RowA_5 "RowA[5]") (joined
+           (portRef Q (instanceRef RowA_5))
+           (portRef B (instanceRef un9_RA_5))
+          ))
+          (net (rename RowA_6 "RowA[6]") (joined
+           (portRef Q (instanceRef RowA_6))
+           (portRef B (instanceRef un9_RA_6))
+          ))
+          (net (rename RowA_7 "RowA[7]") (joined
+           (portRef Q (instanceRef RowA_7))
+           (portRef B (instanceRef un9_RA_7))
+          ))
+          (net (rename RowA_8 "RowA[8]") (joined
+           (portRef Q (instanceRef RowA_8))
+           (portRef B (instanceRef un9_RA_8))
+          ))
+          (net (rename RowA_9 "RowA[9]") (joined
+           (portRef Q (instanceRef RowA_9))
+           (portRef B (instanceRef un9_RA_9))
+          ))
+          (net (rename WRD_0 "WRD[0]") (joined
+           (portRef Q (instanceRef WRD_0))
+           (portRef I (instanceRef RD_pad_0))
+          ))
+          (net (rename WRD_1 "WRD[1]") (joined
+           (portRef Q (instanceRef WRD_1))
+           (portRef I (instanceRef RD_pad_1))
+          ))
+          (net (rename WRD_2 "WRD[2]") (joined
+           (portRef Q (instanceRef WRD_2))
+           (portRef I (instanceRef RD_pad_2))
+          ))
+          (net (rename WRD_3 "WRD[3]") (joined
+           (portRef Q (instanceRef WRD_3))
+           (portRef I (instanceRef RD_pad_3))
+          ))
+          (net (rename WRD_4 "WRD[4]") (joined
+           (portRef Q (instanceRef WRD_4))
+           (portRef I (instanceRef RD_pad_4))
+          ))
+          (net (rename WRD_5 "WRD[5]") (joined
+           (portRef Q (instanceRef WRD_5))
+           (portRef I (instanceRef RD_pad_5))
+          ))
+          (net (rename WRD_6 "WRD[6]") (joined
+           (portRef Q (instanceRef WRD_6))
+           (portRef I (instanceRef RD_pad_6))
+          ))
+          (net (rename WRD_7 "WRD[7]") (joined
+           (portRef Q (instanceRef WRD_7))
+           (portRef I (instanceRef RD_pad_7))
+          ))
+          (net nRowColSel (joined
+           (portRef Q (instanceRef nRowColSel))
+           (portRef B (instanceRef RDQML))
+           (portRef B (instanceRef RDQMH))
+           (portRef C (instanceRef un9_RA_9))
+           (portRef C (instanceRef un9_RA_7))
+           (portRef C (instanceRef un9_RA_6))
+           (portRef C (instanceRef un9_RA_5))
+           (portRef C (instanceRef un9_RA_4))
+           (portRef C (instanceRef un9_RA_3))
+           (portRef C (instanceRef un9_RA_2))
+           (portRef C (instanceRef un9_RA_1))
+           (portRef C (instanceRef un9_RA_0))
+           (portRef C (instanceRef un9_RA_8))
+          ))
+          (net RASr3 (joined
+           (portRef Q (instanceRef RASr3))
+           (portRef C (instanceRef RCKE_2_0))
+          ))
+          (net LEDEN (joined
+           (portRef Q (instanceRef LEDEN))
+           (portRef B (instanceRef LED_pad_RNO))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef A (instanceRef CmdLEDEN_RNO))
+          ))
+          (net CmdLEDEN (joined
+           (portRef Q (instanceRef CmdLEDEN))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef A (instanceRef LEDEN_5_i_m2))
+          ))
+          (net Cmdn8MEGEN (joined
+           (portRef Q (instanceRef Cmdn8MEGEN))
+           (portRef A (instanceRef n8MEGEN_5_i_m2))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net PHI2r3 (joined
+           (portRef Q (instanceRef PHI2r3))
+           (portRef D (instanceRef un1_FS_14_i_a2))
+           (portRef D (instanceRef PHI2r3_RNITCN41))
+          ))
+          (net CmdSubmitted (joined
+           (portRef Q (instanceRef CmdSubmitted))
+           (portRef A (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef PHI2r3_RNITCN41))
+           (portRef B (instanceRef CmdSubmitted_RNO))
+          ))
+          (net (rename FS_4 "FS[4]") (joined
+           (portRef Q (instanceRef FS_4))
+           (portRef A0 (instanceRef FS_cry_0_4))
+           (portRef B (instanceRef UFMCLK_r_i_m2))
+           (portRef A (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net InitReady3 (joined
+           (portRef Z (instanceRef InitReady3_0_a2))
+           (portRef A (instanceRef InitReady_RNO))
+          ))
+          (net RCKEEN (joined
+           (portRef Q (instanceRef RCKEEN))
+           (portRef D (instanceRef RCKE_2_0))
+          ))
+          (net RA11_2 (joined
+           (portRef Z (instanceRef RA11_2))
+           (portRef D (instanceRef RA11))
+          ))
+          (net XOR8MEG (joined
+           (portRef Q (instanceRef XOR8MEG))
+           (portRef B (instanceRef RA11_2))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_0))
+          ))
+          (net nRRAS_0_sqmuxa (joined
+           (portRef Z (instanceRef nRowColSel_RNO))
+           (portRef CD (instanceRef nRowColSel))
+          ))
+          (net nUFMCS15 (joined
+           (portRef Z (instanceRef nUFMCS15_0_a2))
+           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef B (instanceRef UFMCLK_RNO))
+           (portRef B (instanceRef UFMSDI_RNO))
+          ))
+          (net Ready_0_sqmuxa (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef A (instanceRef Ready_fast_RNO))
+          ))
+          (net RCKE_2 (joined
+           (portRef Z (instanceRef RCKE_2_0))
+           (portRef D (instanceRef RCKE))
+          ))
+          (net nRCAS_0_sqmuxa_1 (joined
+           (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef B (instanceRef nRCAS_RNO))
+           (portRef C (instanceRef nRWE_RNO))
+          ))
+          (net XOR8MEG18 (joined
+           (portRef Z (instanceRef XOR8MEG18_0_a2))
+           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef SP (instanceRef CmdLEDEN))
+           (portRef SP (instanceRef Cmdn8MEGEN))
+           (portRef SP (instanceRef XOR8MEG))
+          ))
+          (net CmdEnable (joined
+           (portRef Q (instanceRef CmdEnable))
+           (portRef A (instanceRef XOR8MEG18_0_a2))
+           (portRef B (instanceRef CmdEnable_s_am))
+           (portRef A (instanceRef CmdEnable_s_bm))
+          ))
+          (net CmdEnable16 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2))
+           (portRef D (instanceRef ADSubmitted_r))
+           (portRef C0 (instanceRef CmdEnable_s))
+           (portRef A (instanceRef C1Submitted_RNO))
+          ))
+          (net CmdEnable17 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2))
+           (portRef C (instanceRef ADSubmitted_r))
+           (portRef A (instanceRef CmdEnable_s_am))
+          ))
+          (net CmdSubmitted_1_sqmuxa (joined
+           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdSubmitted_RNO))
+          ))
+          (net CmdUFMCLK_1_sqmuxa (joined
+           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef SP (instanceRef CmdUFMCLK))
+           (portRef SP (instanceRef CmdUFMCS))
+           (portRef SP (instanceRef CmdUFMSDI))
+          ))
+          (net CmdUFMCLK (joined
+           (portRef Q (instanceRef CmdUFMCLK))
+           (portRef B (instanceRef UFMCLK_RNO_0))
+          ))
+          (net CmdUFMSDI (joined
+           (portRef Q (instanceRef CmdUFMSDI))
+           (portRef A (instanceRef UFMSDI_RNO_0))
+          ))
+          (net ADSubmitted (joined
+           (portRef Q (instanceRef ADSubmitted))
+           (portRef A (instanceRef ADSubmitted_r))
+           (portRef B (instanceRef CmdEnable_s_bm))
+          ))
+          (net C1Submitted_RNO (joined
+           (portRef Z (instanceRef C1Submitted_RNO))
+           (portRef D (instanceRef C1Submitted))
+          ))
+          (net ADSubmitted_r (joined
+           (portRef Z (instanceRef ADSubmitted_r))
+           (portRef D (instanceRef ADSubmitted))
+          ))
+          (net UFMSDI_RNO (joined
+           (portRef Z (instanceRef UFMSDI_RNO))
+           (portRef D (instanceRef UFMSDI))
+          ))
+          (net CmdEnable_s (joined
+           (portRef Z (instanceRef CmdEnable_s))
+           (portRef D (instanceRef CmdEnable))
+          ))
+          (net nRowColSel_0_0 (joined
+           (portRef Z (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef nRowColSel))
+          ))
+          (net RCKEEN_8 (joined
+           (portRef Z (instanceRef RCKEEN_8_u))
+           (portRef D (instanceRef RCKEEN))
+          ))
+          (net N_31 (joined
+           (portRef Z (instanceRef un1_FS_14_i_0))
+           (portRef SP (instanceRef n8MEGEN))
+          ))
+          (net N_33 (joined
+           (portRef Z (instanceRef un1_FS_13_i_0))
+           (portRef SP (instanceRef LEDEN))
+          ))
+          (net N_24 (joined
+           (portRef Z (instanceRef nRRAS_5_u_i))
+           (portRef B (instanceRef nRCS_RNO))
+          ))
+          (net N_41 (joined
+           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef A (instanceRef nRCAS_RNO))
+          ))
+          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
+           (portRef Z (instanceRef S_0_i_o2_1))
+           (portRef A (instanceRef nRRAS_5_u_i_0))
+           (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef D (instanceRef S_1))
+           (portRef D (instanceRef RCKEEN_8_u_RNO))
+          ))
+          (net N_159 (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef D (instanceRef RA10_RNO))
+          ))
+          (net N_165 (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef C (instanceRef Ready_RNO))
+          ))
+          (net N_95_5 (joined
+           (portRef Z (instanceRef InitReady3_0_a2_5))
+           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef D (instanceRef InitReady3_0_a2))
+          ))
+          (net N_95_3 (joined
+           (portRef Z (instanceRef InitReady3_0_a2_3))
+           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef C (instanceRef InitReady3_0_a2))
+          ))
+          (net N_51 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
+           (portRef D (instanceRef UFMCLK_r_i_m2))
+           (portRef D (instanceRef nUFMCS15_0_a2))
+           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef B (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net N_126 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
+           (portRef C (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net N_151 (joined
+           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef C (instanceRef UFMSDI_RNO_0))
+           (portRef D (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net N_137_8 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_8))
+           (portRef C (instanceRef un1_FS_13_i_0))
+           (portRef C (instanceRef un1_FS_14_i_0))
+          ))
+          (net N_129 (joined
+           (portRef Z (instanceRef UFMCLK_r_i_m2))
+           (portRef D (instanceRef UFMCLK_RNO_0))
+          ))
+          (net N_155 (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef C (instanceRef IS_RNO_0))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef C (instanceRef nRRAS_RNO))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef B (instanceRef nRRAS_5_u_i))
+          ))
+          (net N_56_i (joined
+           (portRef Z (instanceRef IS_n1_0_x2))
+           (portRef D (instanceRef IS_1))
+          ))
+          (net N_160 (joined
+           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef B (instanceRef nRRAS_RNO))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef C (instanceRef nRRAS_5_u_i))
+          ))
+          (net N_136 (joined
+           (portRef Z (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef un1_FS_13_i_0))
+           (portRef A (instanceRef un1_FS_14_i_0))
+          ))
+          (net N_69 (joined
+           (portRef Z (instanceRef n8MEGEN_5_i_m2))
+           (portRef D (instanceRef n8MEGEN))
+          ))
+          (net N_70 (joined
+           (portRef Z (instanceRef LEDEN_5_i_m2))
+           (portRef D (instanceRef LEDEN))
+          ))
+          (net N_137_6 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_6))
+           (portRef B (instanceRef un1_FS_13_i_0))
+           (portRef B (instanceRef un1_FS_14_i_0))
+          ))
+          (net XOR8MEG_3 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef D (instanceRef XOR8MEG))
+          ))
+          (net CmdEnable16_1 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_1))
+           (portRef A (instanceRef CmdEnable16_0_a2_5))
+          ))
+          (net N_43 (joined
+           (portRef Z (instanceRef CmdEnable17_0_o2))
+           (portRef D (instanceRef CmdEnable17_0_a2_4))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net N_147 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0))
+           (portRef A (instanceRef un1_CMDWR))
+           (portRef C (instanceRef CmdEnable16_0_a2))
+           (portRef B (instanceRef C1WR_0_a2))
+           (portRef D (instanceRef XOR8MEG18_0_a2))
+           (portRef D (instanceRef CmdEnable17_0_a2))
+           (portRef C (instanceRef C1Submitted_RNO))
+          ))
+          (net CmdEnable16_4 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_4))
+           (portRef A (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net un1_Din_4 (joined
+           (portRef Z (instanceRef un1_Din_4))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_0))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a3_2))
+          ))
+          (net N_171 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a3_3))
+          ))
+          (net N_128 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net N_152 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef CmdLEDEN_RNO))
+           (portRef B (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net N_132 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef B (instanceRef CmdLEDEN_RNO))
+          ))
+          (net N_133 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef C (instanceRef CmdLEDEN_RNO))
+          ))
+          (net un1_CMDWR (joined
+           (portRef Z (instanceRef un1_CMDWR))
+           (portRef C (instanceRef CmdEnable_s_am))
+          ))
+          (net N_179 (joined
+           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
+           (portRef B (instanceRef nRowColSel_0_0))
+          ))
+          (net XOR8MEG_3_u_0_a3_2 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a3_3))
+          ))
+          (net UFMCLK_r_i_a2_2_2 (joined
+           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef C (instanceRef UFMCLK_RNO_0))
+           (portRef C (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+          ))
+          (net UFMCLK_RNO (joined
+           (portRef Z (instanceRef UFMCLK_RNO))
+           (portRef D (instanceRef UFMCLK))
+          ))
+          (net UFMSDI_ens2_i_a0 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
+           (portRef B (instanceRef UFMSDI_RNO_0))
+          ))
+          (net RCKEEN_8_u_0_0 (joined
+           (portRef Z (instanceRef RCKEEN_8_u_RNO))
+           (portRef B (instanceRef RCKEEN_8_u))
+          ))
+          (net RCKEEN_8_u_0_a2_1_out (joined
+           (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef D (instanceRef nRCS_RNO))
+          ))
+          (net nCRAS_c_i (joined
+           (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
+           (portRef CK (instanceRef CBR))
+           (portRef CK (instanceRef CBR_fast))
+           (portRef CK (instanceRef FWEr))
+           (portRef CK (instanceRef FWEr_fast))
+           (portRef CK (instanceRef RBA_1))
+           (portRef CK (instanceRef RBA_0))
+           (portRef CK (instanceRef RowA_9))
+           (portRef CK (instanceRef RowA_8))
+           (portRef CK (instanceRef RowA_7))
+           (portRef CK (instanceRef RowA_6))
+           (portRef CK (instanceRef RowA_5))
+           (portRef CK (instanceRef RowA_4))
+           (portRef CK (instanceRef RowA_3))
+           (portRef CK (instanceRef RowA_2))
+           (portRef CK (instanceRef RowA_1))
+           (portRef CK (instanceRef RowA_0))
+          ))
+          (net N_159_i (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef SP (instanceRef IS_3))
+           (portRef SP (instanceRef IS_2))
+           (portRef SP (instanceRef IS_1))
+          ))
+          (net RD_1_i (joined
+           (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef T (instanceRef RD_pad_0))
+           (portRef T (instanceRef RD_pad_1))
+           (portRef T (instanceRef RD_pad_2))
+           (portRef T (instanceRef RD_pad_3))
+           (portRef T (instanceRef RD_pad_4))
+           (portRef T (instanceRef RD_pad_5))
+           (portRef T (instanceRef RD_pad_6))
+           (portRef T (instanceRef RD_pad_7))
+          ))
+          (net N_28_i (joined
+           (portRef Z (instanceRef nRCS_RNO))
+           (portRef D (instanceRef nRCS))
+          ))
+          (net N_37_i (joined
+           (portRef Z (instanceRef nRCAS_RNO))
+           (portRef D (instanceRef nRCAS))
+          ))
+          (net N_24_i (joined
+           (portRef Z (instanceRef nRRAS_RNO))
+           (portRef D (instanceRef nRRAS))
+          ))
+          (net nUFMCS_s_0_N_5_i (joined
+           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef D (instanceRef nUFMCS))
+          ))
+          (net N_39_i (joined
+           (portRef Z (instanceRef nRWE_RNO))
+           (portRef D (instanceRef nRWE))
+          ))
+          (net N_64_i_i (joined
+           (portRef Z (instanceRef IS_RNO_0))
+           (portRef D (instanceRef IS_0))
+          ))
+          (net N_61_i_i (joined
+           (portRef Z (instanceRef IS_RNO_3))
+           (portRef D (instanceRef IS_3))
+          ))
+          (net N_60_i_i (joined
+           (portRef Z (instanceRef IS_RNO_2))
+           (portRef D (instanceRef IS_2))
+          ))
+          (net N_177_i (joined
+           (portRef Z (instanceRef S_RNO_0))
+           (portRef D (instanceRef S_0))
+          ))
+          (net N_21_i (joined
+           (portRef Z (instanceRef CmdLEDEN_RNO))
+           (portRef D (instanceRef CmdLEDEN))
+          ))
+          (net N_19_i (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_RNO))
+           (portRef D (instanceRef Cmdn8MEGEN))
+          ))
+          (net N_139_i (joined
+           (portRef Z (instanceRef PHI2r3_RNITCN41))
+           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef A (instanceRef UFMCLK_RNO))
+           (portRef A (instanceRef UFMSDI_RNO))
+          ))
+          (net (rename FS_cry_0 "FS_cry[0]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_0))
+          ))
+          (net (rename FS_s_0 "FS_s[0]") (joined
+           (portRef S0 (instanceRef FS_cry_0_0))
+           (portRef D (instanceRef FS_0))
+          ))
+          (net (rename FS_cry_1 "FS_cry[1]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_0))
+           (portRef CIN (instanceRef FS_cry_0_2))
+          ))
+          (net (rename FS_s_1 "FS_s[1]") (joined
+           (portRef S1 (instanceRef FS_cry_0_0))
+           (portRef D (instanceRef FS_1))
+          ))
+          (net (rename FS_cry_2 "FS_cry[2]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_2))
+          ))
+          (net (rename FS_s_2 "FS_s[2]") (joined
+           (portRef S0 (instanceRef FS_cry_0_2))
+           (portRef D (instanceRef FS_2))
+          ))
+          (net (rename FS_cry_3 "FS_cry[3]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_2))
+           (portRef CIN (instanceRef FS_cry_0_4))
+          ))
+          (net (rename FS_s_3 "FS_s[3]") (joined
+           (portRef S1 (instanceRef FS_cry_0_2))
+           (portRef D (instanceRef FS_3))
+          ))
+          (net (rename FS_cry_4 "FS_cry[4]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_4))
+          ))
+          (net (rename FS_s_4 "FS_s[4]") (joined
+           (portRef S0 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef FS_4))
+          ))
+          (net (rename FS_cry_5 "FS_cry[5]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_4))
+           (portRef CIN (instanceRef FS_cry_0_6))
+          ))
+          (net (rename FS_s_5 "FS_s[5]") (joined
+           (portRef S1 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef FS_5))
+          ))
+          (net (rename FS_cry_6 "FS_cry[6]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_6))
+          ))
+          (net (rename FS_s_6 "FS_s[6]") (joined
+           (portRef S0 (instanceRef FS_cry_0_6))
+           (portRef D (instanceRef FS_6))
+          ))
+          (net (rename FS_cry_7 "FS_cry[7]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_6))
+           (portRef CIN (instanceRef FS_cry_0_8))
+          ))
+          (net (rename FS_s_7 "FS_s[7]") (joined
+           (portRef S1 (instanceRef FS_cry_0_6))
+           (portRef D (instanceRef FS_7))
+          ))
+          (net (rename FS_cry_8 "FS_cry[8]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_8))
+          ))
+          (net (rename FS_s_8 "FS_s[8]") (joined
+           (portRef S0 (instanceRef FS_cry_0_8))
+           (portRef D (instanceRef FS_8))
+          ))
+          (net (rename FS_cry_9 "FS_cry[9]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_8))
+           (portRef CIN (instanceRef FS_cry_0_10))
+          ))
+          (net (rename FS_s_9 "FS_s[9]") (joined
+           (portRef S1 (instanceRef FS_cry_0_8))
+           (portRef D (instanceRef FS_9))
+          ))
+          (net (rename FS_cry_10 "FS_cry[10]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_10))
+          ))
+          (net (rename FS_s_10 "FS_s[10]") (joined
+           (portRef S0 (instanceRef FS_cry_0_10))
+           (portRef D (instanceRef FS_10))
+          ))
+          (net (rename FS_cry_11 "FS_cry[11]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_10))
+           (portRef CIN (instanceRef FS_cry_0_12))
+          ))
+          (net (rename FS_s_11 "FS_s[11]") (joined
+           (portRef S1 (instanceRef FS_cry_0_10))
+           (portRef D (instanceRef FS_11))
+          ))
+          (net (rename FS_cry_12 "FS_cry[12]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_12))
+          ))
+          (net (rename FS_s_12 "FS_s[12]") (joined
+           (portRef S0 (instanceRef FS_cry_0_12))
+           (portRef D (instanceRef FS_12))
+          ))
+          (net (rename FS_cry_13 "FS_cry[13]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_12))
+           (portRef CIN (instanceRef FS_cry_0_14))
+          ))
+          (net (rename FS_s_13 "FS_s[13]") (joined
+           (portRef S1 (instanceRef FS_cry_0_12))
+           (portRef D (instanceRef FS_13))
+          ))
+          (net (rename FS_cry_14 "FS_cry[14]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_14))
+          ))
+          (net (rename FS_s_14 "FS_s[14]") (joined
+           (portRef S0 (instanceRef FS_cry_0_14))
+           (portRef D (instanceRef FS_14))
+          ))
+          (net (rename FS_cry_15 "FS_cry[15]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_14))
+           (portRef CIN (instanceRef FS_cry_0_16))
+          ))
+          (net (rename FS_s_15 "FS_s[15]") (joined
+           (portRef S1 (instanceRef FS_cry_0_14))
+           (portRef D (instanceRef FS_15))
+          ))
+          (net (rename FS_cry_16 "FS_cry[16]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_16))
+          ))
+          (net (rename FS_s_16 "FS_s[16]") (joined
+           (portRef S0 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef FS_16))
+          ))
+          (net (rename FS_s_17 "FS_s[17]") (joined
+           (portRef S1 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef FS_17))
+          ))
+          (net RA10s_i (joined
+           (portRef Z (instanceRef RA10_RNO))
+           (portRef PD (instanceRef RA10))
+          ))
+          (net Cmdn8MEGEN_4_u_i_0 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
+           (portRef A (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net UFMSDI_ens2_i_o2_0_3 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
+          ))
+          (net C1WR_0_a2_0_3 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_3))
+           (portRef C (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net C1WR_0_a2_0_4 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net C1WR_0_a2_0_10 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_10))
+           (portRef C (instanceRef C1WR_0_a2_0))
+          ))
+          (net C1WR_0_a2_0_11 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_11))
+           (portRef D (instanceRef C1WR_0_a2_0))
+          ))
+          (net Ready_0_sqmuxa_0_a3_2 (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef Ready_RNO))
+          ))
+          (net UFMSDI_ens2_i_a2_4_2 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef D (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net CmdEnable16_0_a2_4 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef CmdEnable16_0_a2))
+          ))
+          (net CmdEnable16_0_a2_5 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_5))
+           (portRef B (instanceRef CmdEnable16_0_a2))
+          ))
+          (net nRRAS_5_u_i_0 (joined
+           (portRef Z (instanceRef nRRAS_5_u_i_0))
+           (portRef A (instanceRef nRRAS_RNO))
+           (portRef D (instanceRef nRRAS_5_u_i))
+          ))
+          (net CmdEnable17_0_a2_3 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable17_0_a2))
+          ))
+          (net CmdEnable17_0_a2_4 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2_4))
+           (portRef B (instanceRef CmdEnable17_0_a2))
+          ))
+          (net un1_FS_13_i_a2_1 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_1))
+           (portRef D (instanceRef un1_FS_13_i_0))
+          ))
+          (net un1_FS_14_i_a2_0_1 (joined
+           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef D (instanceRef un1_FS_14_i_0))
+          ))
+          (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_16))
+          ))
+          (net RCKEEN_8_u_1 (joined
+           (portRef Z (instanceRef RCKEEN_8_u_1_0))
+           (portRef C (instanceRef RCKEEN_8_u))
+          ))
+          (net N_28_i_1 (joined
+           (portRef Z (instanceRef nRCS_RNO_0))
+           (portRef C (instanceRef nRCS_RNO))
+          ))
+          (net m18_0_a3_3 (joined
+           (portRef Z (instanceRef nRWE_RNO_5))
+           (portRef C (instanceRef nRWE_RNO_4))
+          ))
+          (net m18_0_a2_1 (joined
+           (portRef Z (instanceRef nRWE_RNO_1))
+           (portRef D (instanceRef nRWE_RNO))
+          ))
+          (net m6_0_a2_2 (joined
+           (portRef Z (instanceRef nRWE_RNO_2))
+           (portRef D (instanceRef nRWE_RNO_0))
+          ))
+          (net G_17_1 (joined
+           (portRef Z (instanceRef nRWE_RNO_0))
+           (portRef B (instanceRef nRWE_RNO))
+          ))
+          (net g0_1 (joined
+           (portRef Z (instanceRef nRCAS_RNO_0))
+           (portRef D (instanceRef nRCAS_RNO))
+          ))
+          (net g4_0_0_0 (joined
+           (portRef Z (instanceRef nRCAS_RNO_1))
+           (portRef D (instanceRef nRCAS_RNO_0))
+          ))
+          (net CBR_fast (joined
+           (portRef Q (instanceRef CBR_fast))
+           (portRef A (instanceRef nRCAS_RNO_0))
+           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+          ))
+          (net FWEr_fast (joined
+           (portRef Q (instanceRef FWEr_fast))
+           (portRef C (instanceRef RCKEEN_8_u_1_0))
+           (portRef A (instanceRef nRCS_RNO_0))
+          ))
+          (net Ready_fast (joined
+           (portRef Q (instanceRef Ready_fast))
+           (portRef B (instanceRef Ready_fast_RNO))
+           (portRef A (instanceRef Ready_fast_RNI29NA))
+          ))
+          (net UFMSDI_r_xx_mm_1 (joined
+           (portRef Z (instanceRef UFMSDI_RNO_0))
+           (portRef D (instanceRef UFMSDI_RNO))
+          ))
+          (net UFMCLK_r_i_m4_xx_mm_1 (joined
+           (portRef Z (instanceRef UFMCLK_RNO_0))
+           (portRef D (instanceRef UFMCLK_RNO))
+          ))
+          (net nUFMCS_s_0_N_5_i_N_2L1 (joined
+           (portRef Z (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
+          ))
+          (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
+           (portRef Z (instanceRef XOR8MEG_CN))
+           (portRef CK (instanceRef ADSubmitted))
+           (portRef CK (instanceRef C1Submitted))
+           (portRef CK (instanceRef CmdEnable))
+           (portRef CK (instanceRef CmdLEDEN))
+           (portRef CK (instanceRef CmdSubmitted))
+           (portRef CK (instanceRef CmdUFMCLK))
+           (portRef CK (instanceRef CmdUFMCS))
+           (portRef CK (instanceRef CmdUFMSDI))
+           (portRef CK (instanceRef Cmdn8MEGEN))
+           (portRef CK (instanceRef XOR8MEG))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef CIN (instanceRef FS_cry_0_0))
+           (portRef GSR (instanceRef GSR_INST))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef D1 (instanceRef FS_cry_0_0))
+           (portRef C1 (instanceRef FS_cry_0_0))
+           (portRef B1 (instanceRef FS_cry_0_0))
+           (portRef D0 (instanceRef FS_cry_0_0))
+           (portRef C0 (instanceRef FS_cry_0_0))
+           (portRef B0 (instanceRef FS_cry_0_0))
+           (portRef D1 (instanceRef FS_cry_0_2))
+           (portRef C1 (instanceRef FS_cry_0_2))
+           (portRef B1 (instanceRef FS_cry_0_2))
+           (portRef D0 (instanceRef FS_cry_0_2))
+           (portRef C0 (instanceRef FS_cry_0_2))
+           (portRef B0 (instanceRef FS_cry_0_2))
+           (portRef D1 (instanceRef FS_cry_0_4))
+           (portRef C1 (instanceRef FS_cry_0_4))
+           (portRef B1 (instanceRef FS_cry_0_4))
+           (portRef D0 (instanceRef FS_cry_0_4))
+           (portRef C0 (instanceRef FS_cry_0_4))
+           (portRef B0 (instanceRef FS_cry_0_4))
+           (portRef D1 (instanceRef FS_cry_0_6))
+           (portRef C1 (instanceRef FS_cry_0_6))
+           (portRef B1 (instanceRef FS_cry_0_6))
+           (portRef D0 (instanceRef FS_cry_0_6))
+           (portRef C0 (instanceRef FS_cry_0_6))
+           (portRef B0 (instanceRef FS_cry_0_6))
+           (portRef D1 (instanceRef FS_cry_0_8))
+           (portRef C1 (instanceRef FS_cry_0_8))
+           (portRef B1 (instanceRef FS_cry_0_8))
+           (portRef D0 (instanceRef FS_cry_0_8))
+           (portRef C0 (instanceRef FS_cry_0_8))
+           (portRef B0 (instanceRef FS_cry_0_8))
+           (portRef D1 (instanceRef FS_cry_0_10))
+           (portRef C1 (instanceRef FS_cry_0_10))
+           (portRef B1 (instanceRef FS_cry_0_10))
+           (portRef D0 (instanceRef FS_cry_0_10))
+           (portRef C0 (instanceRef FS_cry_0_10))
+           (portRef B0 (instanceRef FS_cry_0_10))
+           (portRef D1 (instanceRef FS_cry_0_12))
+           (portRef C1 (instanceRef FS_cry_0_12))
+           (portRef B1 (instanceRef FS_cry_0_12))
+           (portRef D0 (instanceRef FS_cry_0_12))
+           (portRef C0 (instanceRef FS_cry_0_12))
+           (portRef B0 (instanceRef FS_cry_0_12))
+           (portRef D1 (instanceRef FS_cry_0_14))
+           (portRef C1 (instanceRef FS_cry_0_14))
+           (portRef B1 (instanceRef FS_cry_0_14))
+           (portRef D0 (instanceRef FS_cry_0_14))
+           (portRef C0 (instanceRef FS_cry_0_14))
+           (portRef B0 (instanceRef FS_cry_0_14))
+           (portRef D1 (instanceRef FS_cry_0_16))
+           (portRef C1 (instanceRef FS_cry_0_16))
+           (portRef B1 (instanceRef FS_cry_0_16))
+           (portRef D0 (instanceRef FS_cry_0_16))
+           (portRef C0 (instanceRef FS_cry_0_16))
+           (portRef B0 (instanceRef FS_cry_0_16))
+          ))
+          (net PHI2_c (joined
+           (portRef O (instanceRef PHI2_pad))
+           (portRef CK (instanceRef Bank_7))
+           (portRef CK (instanceRef Bank_6))
+           (portRef CK (instanceRef Bank_5))
+           (portRef CK (instanceRef Bank_4))
+           (portRef CK (instanceRef Bank_3))
+           (portRef CK (instanceRef Bank_2))
+           (portRef CK (instanceRef Bank_1))
+           (portRef CK (instanceRef Bank_0))
+           (portRef D (instanceRef PHI2r))
+           (portRef CK (instanceRef RA11))
+           (portRef A (instanceRef XOR8MEG_CN))
+          ))
+          (net PHI2 (joined
+           (portRef PHI2)
+           (portRef I (instanceRef PHI2_pad))
+          ))
+          (net (rename MAin_c_0 "MAin_c[0]") (joined
+           (portRef O (instanceRef MAin_pad_0))
+           (portRef B (instanceRef un1_CMDWR))
+           (portRef A (instanceRef un9_RA_0))
+           (portRef D (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef B (instanceRef XOR8MEG18_0_a2))
+           (portRef C (instanceRef CmdEnable17_0_a2))
+           (portRef D (instanceRef RowA_0))
+          ))
+          (net (rename MAin_0 "MAin[0]") (joined
+           (portRef (member main 9))
+           (portRef I (instanceRef MAin_pad_0))
+          ))
+          (net (rename MAin_c_1 "MAin_c[1]") (joined
+           (portRef O (instanceRef MAin_pad_1))
+           (portRef C (instanceRef un1_CMDWR))
+           (portRef A (instanceRef un9_RA_1))
+           (portRef C (instanceRef CmdEnable17_0_a2_4))
+           (portRef D (instanceRef CmdEnable16_0_a2_5))
+           (portRef A (instanceRef C1WR_0_a2))
+           (portRef C (instanceRef XOR8MEG18_0_a2))
+           (portRef D (instanceRef RowA_1))
+           (portRef D (instanceRef C1Submitted_RNO))
+          ))
+          (net (rename MAin_1 "MAin[1]") (joined
+           (portRef (member main 8))
+           (portRef I (instanceRef MAin_pad_1))
+          ))
+          (net (rename MAin_c_2 "MAin_c[2]") (joined
+           (portRef O (instanceRef MAin_pad_2))
+           (portRef A (instanceRef un9_RA_2))
+           (portRef A (instanceRef C1WR_0_a2_0_3))
+           (portRef D (instanceRef RowA_2))
+          ))
+          (net (rename MAin_2 "MAin[2]") (joined
+           (portRef (member main 7))
+           (portRef I (instanceRef MAin_pad_2))
+          ))
+          (net (rename MAin_c_3 "MAin_c[3]") (joined
+           (portRef O (instanceRef MAin_pad_3))
+           (portRef A (instanceRef un9_RA_3))
+           (portRef B (instanceRef C1WR_0_a2_0_3))
+           (portRef D (instanceRef RowA_3))
+          ))
+          (net (rename MAin_3 "MAin[3]") (joined
+           (portRef (member main 6))
+           (portRef I (instanceRef MAin_pad_3))
+          ))
+          (net (rename MAin_c_4 "MAin_c[4]") (joined
+           (portRef O (instanceRef MAin_pad_4))
+           (portRef A (instanceRef un9_RA_4))
+           (portRef A (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_4))
+          ))
+          (net (rename MAin_4 "MAin[4]") (joined
+           (portRef (member main 5))
+           (portRef I (instanceRef MAin_pad_4))
+          ))
+          (net (rename MAin_c_5 "MAin_c[5]") (joined
+           (portRef O (instanceRef MAin_pad_5))
+           (portRef A (instanceRef un9_RA_5))
+           (portRef B (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_5))
+          ))
+          (net (rename MAin_5 "MAin[5]") (joined
+           (portRef (member main 4))
+           (portRef I (instanceRef MAin_pad_5))
+          ))
+          (net (rename MAin_c_6 "MAin_c[6]") (joined
+           (portRef O (instanceRef MAin_pad_6))
+           (portRef A (instanceRef un9_RA_6))
+           (portRef C (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_6))
+          ))
+          (net (rename MAin_6 "MAin[6]") (joined
+           (portRef (member main 3))
+           (portRef I (instanceRef MAin_pad_6))
+          ))
+          (net (rename MAin_c_7 "MAin_c[7]") (joined
+           (portRef O (instanceRef MAin_pad_7))
+           (portRef A (instanceRef un9_RA_7))
+           (portRef D (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_7))
+          ))
+          (net (rename MAin_7 "MAin[7]") (joined
+           (portRef (member main 2))
+           (portRef I (instanceRef MAin_pad_7))
+          ))
+          (net (rename MAin_c_8 "MAin_c[8]") (joined
+           (portRef O (instanceRef MAin_pad_8))
+           (portRef A (instanceRef un9_RA_8))
+           (portRef D (instanceRef RowA_8))
+          ))
+          (net (rename MAin_8 "MAin[8]") (joined
+           (portRef (member main 1))
+           (portRef I (instanceRef MAin_pad_8))
+          ))
+          (net (rename MAin_c_9 "MAin_c[9]") (joined
+           (portRef O (instanceRef MAin_pad_9))
+           (portRef A (instanceRef RDQML))
+           (portRef A (instanceRef RDQMH))
+           (portRef A (instanceRef un9_RA_9))
+           (portRef D (instanceRef RowA_9))
+          ))
+          (net (rename MAin_9 "MAin[9]") (joined
+           (portRef (member main 0))
+           (portRef I (instanceRef MAin_pad_9))
+          ))
+          (net (rename CROW_c_0 "CROW_c[0]") (joined
+           (portRef O (instanceRef CROW_pad_0))
+           (portRef D (instanceRef RBA_0))
+          ))
+          (net (rename CROW_0 "CROW[0]") (joined
+           (portRef (member crow 1))
+           (portRef I (instanceRef CROW_pad_0))
+          ))
+          (net (rename CROW_c_1 "CROW_c[1]") (joined
+           (portRef O (instanceRef CROW_pad_1))
+           (portRef D (instanceRef RBA_1))
+          ))
+          (net (rename CROW_1 "CROW[1]") (joined
+           (portRef (member crow 0))
+           (portRef I (instanceRef CROW_pad_1))
+          ))
+          (net (rename Din_c_0 "Din_c[0]") (joined
+           (portRef O (instanceRef Din_pad_0))
+           (portRef B (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable16_0_a2_4))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_0))
+           (portRef D (instanceRef CmdUFMSDI))
+           (portRef D (instanceRef WRD_0))
+          ))
+          (net (rename Din_0 "Din[0]") (joined
+           (portRef (member din 7))
+           (portRef I (instanceRef Din_pad_0))
+          ))
+          (net (rename Din_c_1 "Din_c[1]") (joined
+           (portRef O (instanceRef Din_pad_1))
+           (portRef A (instanceRef CmdEnable17_0_a2_3))
+           (portRef B (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef D (instanceRef Bank_1))
+           (portRef D (instanceRef CmdUFMCLK))
+           (portRef D (instanceRef WRD_1))
+          ))
+          (net (rename Din_1 "Din[1]") (joined
+           (portRef (member din 6))
+           (portRef I (instanceRef Din_pad_1))
+          ))
+          (net (rename Din_c_2 "Din_c[2]") (joined
+           (portRef O (instanceRef Din_pad_2))
+           (portRef A (instanceRef CmdEnable17_0_a2_4))
+           (portRef B (instanceRef CmdEnable16_0_a2_5))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_2))
+           (portRef D (instanceRef CmdUFMCS))
+           (portRef D (instanceRef WRD_2))
+          ))
+          (net (rename Din_2 "Din[2]") (joined
+           (portRef (member din 5))
+           (portRef I (instanceRef Din_pad_2))
+          ))
+          (net (rename Din_c_3 "Din_c[3]") (joined
+           (portRef O (instanceRef Din_pad_3))
+           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef D (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdEnable17_0_o2))
+           (portRef C (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_3))
+           (portRef D (instanceRef WRD_3))
+          ))
+          (net (rename Din_3 "Din[3]") (joined
+           (portRef (member din 4))
+           (portRef I (instanceRef Din_pad_3))
+          ))
+          (net (rename Din_c_4 "Din_c[4]") (joined
+           (portRef O (instanceRef Din_pad_4))
+           (portRef D (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable16_0_a2_1))
+           (portRef A (instanceRef un1_Din_4))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef D (instanceRef Bank_4))
+           (portRef D (instanceRef WRD_4))
+          ))
+          (net (rename Din_4 "Din[4]") (joined
+           (portRef (member din 3))
+           (portRef I (instanceRef Din_pad_4))
+          ))
+          (net (rename Din_c_5 "Din_c[5]") (joined
+           (portRef O (instanceRef Din_pad_5))
+           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef B (instanceRef CmdEnable17_0_o2))
+           (portRef B (instanceRef CmdEnable16_0_a2_4))
+           (portRef B (instanceRef un1_Din_4))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef Bank_5))
+           (portRef D (instanceRef WRD_5))
+          ))
+          (net (rename Din_5 "Din[5]") (joined
+           (portRef (member din 2))
+           (portRef I (instanceRef Din_pad_5))
+          ))
+          (net (rename Din_c_6 "Din_c[6]") (joined
+           (portRef O (instanceRef Din_pad_6))
+           (portRef C (instanceRef un1_Din_4))
+           (portRef A (instanceRef RA11_2))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef B (instanceRef CmdEnable17_0_a2_4))
+           (portRef C (instanceRef CmdEnable16_0_a2_5))
+           (portRef D (instanceRef Bank_6))
+           (portRef D (instanceRef WRD_6))
+          ))
+          (net (rename Din_6 "Din[6]") (joined
+           (portRef (member din 1))
+           (portRef I (instanceRef Din_pad_6))
+          ))
+          (net (rename Din_c_7 "Din_c[7]") (joined
+           (portRef O (instanceRef Din_pad_7))
+           (portRef C (instanceRef CmdEnable17_0_a2_3))
+           (portRef B (instanceRef CmdEnable16_0_a2_1))
+           (portRef D (instanceRef un1_Din_4))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef D (instanceRef Bank_7))
+           (portRef D (instanceRef WRD_7))
+          ))
+          (net (rename Din_7 "Din[7]") (joined
+           (portRef (member din 0))
+           (portRef I (instanceRef Din_pad_7))
+          ))
+          (net (rename Dout_0 "Dout[0]") (joined
+           (portRef O (instanceRef Dout_pad_0))
+           (portRef (member dout 7))
+          ))
+          (net (rename Dout_1 "Dout[1]") (joined
+           (portRef O (instanceRef Dout_pad_1))
+           (portRef (member dout 6))
+          ))
+          (net (rename Dout_2 "Dout[2]") (joined
+           (portRef O (instanceRef Dout_pad_2))
+           (portRef (member dout 5))
+          ))
+          (net (rename Dout_3 "Dout[3]") (joined
+           (portRef O (instanceRef Dout_pad_3))
+           (portRef (member dout 4))
+          ))
+          (net (rename Dout_4 "Dout[4]") (joined
+           (portRef O (instanceRef Dout_pad_4))
+           (portRef (member dout 3))
+          ))
+          (net (rename Dout_5 "Dout[5]") (joined
+           (portRef O (instanceRef Dout_pad_5))
+           (portRef (member dout 2))
+          ))
+          (net (rename Dout_6 "Dout[6]") (joined
+           (portRef O (instanceRef Dout_pad_6))
+           (portRef (member dout 1))
+          ))
+          (net (rename Dout_7 "Dout[7]") (joined
+           (portRef O (instanceRef Dout_pad_7))
+           (portRef (member dout 0))
+          ))
+          (net nCCAS_c (joined
+           (portRef O (instanceRef nCCAS_pad))
+           (portRef A (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef A (instanceRef nCCAS_pad_RNISUR8))
+          ))
+          (net nCCAS (joined
+           (portRef nCCAS)
+           (portRef I (instanceRef nCCAS_pad))
+          ))
+          (net nCRAS_c (joined
+           (portRef O (instanceRef nCRAS_pad))
+           (portRef C (instanceRef LED_pad_RNO))
+           (portRef A (instanceRef nCRAS_pad_RNIBPVB))
+           (portRef A (instanceRef RASr_RNO))
+          ))
+          (net nCRAS (joined
+           (portRef nCRAS)
+           (portRef I (instanceRef nCRAS_pad))
+          ))
+          (net nFWE_c (joined
+           (portRef O (instanceRef nFWE_pad))
+           (portRef C (instanceRef C1WR_0_a2_0_3))
+           (portRef B (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef A (instanceRef nFWE_pad_RNI420B))
+          ))
+          (net nFWE (joined
+           (portRef nFWE)
+           (portRef I (instanceRef nFWE_pad))
+          ))
+          (net LED_c (joined
+           (portRef Z (instanceRef LED_pad_RNO))
+           (portRef I (instanceRef LED_pad))
+          ))
+          (net LED (joined
+           (portRef O (instanceRef LED_pad))
+           (portRef LED)
+          ))
+          (net (rename RBA_c_0 "RBA_c[0]") (joined
+           (portRef Q (instanceRef RBA_0))
+           (portRef I (instanceRef RBA_pad_0))
+          ))
+          (net (rename RBA_0 "RBA[0]") (joined
+           (portRef O (instanceRef RBA_pad_0))
+           (portRef (member rba 1))
+          ))
+          (net (rename RBA_c_1 "RBA_c[1]") (joined
+           (portRef Q (instanceRef RBA_1))
+           (portRef I (instanceRef RBA_pad_1))
+          ))
+          (net (rename RBA_1 "RBA[1]") (joined
+           (portRef O (instanceRef RBA_pad_1))
+           (portRef (member rba 0))
+          ))
+          (net (rename RA_c_0 "RA_c[0]") (joined
+           (portRef Z (instanceRef un9_RA_0))
+           (portRef I (instanceRef RA_pad_0))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef O (instanceRef RA_pad_0))
+           (portRef (member ra 11))
+          ))
+          (net (rename RA_c_1 "RA_c[1]") (joined
+           (portRef Z (instanceRef un9_RA_1))
+           (portRef I (instanceRef RA_pad_1))
+          ))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef O (instanceRef RA_pad_1))
+           (portRef (member ra 10))
+          ))
+          (net (rename RA_c_2 "RA_c[2]") (joined
+           (portRef Z (instanceRef un9_RA_2))
+           (portRef I (instanceRef RA_pad_2))
+          ))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef O (instanceRef RA_pad_2))
+           (portRef (member ra 9))
+          ))
+          (net (rename RA_c_3 "RA_c[3]") (joined
+           (portRef Z (instanceRef un9_RA_3))
+           (portRef I (instanceRef RA_pad_3))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef O (instanceRef RA_pad_3))
+           (portRef (member ra 8))
+          ))
+          (net (rename RA_c_4 "RA_c[4]") (joined
+           (portRef Z (instanceRef un9_RA_4))
+           (portRef I (instanceRef RA_pad_4))
+          ))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef O (instanceRef RA_pad_4))
+           (portRef (member ra 7))
+          ))
+          (net (rename RA_c_5 "RA_c[5]") (joined
+           (portRef Z (instanceRef un9_RA_5))
+           (portRef I (instanceRef RA_pad_5))
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef O (instanceRef RA_pad_5))
+           (portRef (member ra 6))
+          ))
+          (net (rename RA_c_6 "RA_c[6]") (joined
+           (portRef Z (instanceRef un9_RA_6))
+           (portRef I (instanceRef RA_pad_6))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef O (instanceRef RA_pad_6))
+           (portRef (member ra 5))
+          ))
+          (net (rename RA_c_7 "RA_c[7]") (joined
+           (portRef Z (instanceRef un9_RA_7))
+           (portRef I (instanceRef RA_pad_7))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef O (instanceRef RA_pad_7))
+           (portRef (member ra 4))
+          ))
+          (net (rename RA_c_8 "RA_c[8]") (joined
+           (portRef Z (instanceRef un9_RA_8))
+           (portRef I (instanceRef RA_pad_8))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef O (instanceRef RA_pad_8))
+           (portRef (member ra 3))
+          ))
+          (net (rename RA_c_9 "RA_c[9]") (joined
+           (portRef Z (instanceRef un9_RA_9))
+           (portRef I (instanceRef RA_pad_9))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef O (instanceRef RA_pad_9))
+           (portRef (member ra 2))
+          ))
+          (net (rename RA_c_10 "RA_c[10]") (joined
+           (portRef Q (instanceRef RA10))
+           (portRef I (instanceRef RA_pad_10))
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef O (instanceRef RA_pad_10))
+           (portRef (member ra 1))
+          ))
+          (net (rename RA_c_11 "RA_c[11]") (joined
+           (portRef Q (instanceRef RA11))
+           (portRef I (instanceRef RA_pad_11))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef O (instanceRef RA_pad_11))
+           (portRef (member ra 0))
+          ))
+          (net (rename RD_in_0 "RD_in[0]") (joined
+           (portRef O (instanceRef RD_pad_0))
+           (portRef I (instanceRef Dout_pad_0))
+          ))
+          (net (rename RD_0 "RD[0]") (joined
+           (portRef B (instanceRef RD_pad_0))
+           (portRef (member rd 7))
+          ))
+          (net (rename RD_in_1 "RD_in[1]") (joined
+           (portRef O (instanceRef RD_pad_1))
+           (portRef I (instanceRef Dout_pad_1))
+          ))
+          (net (rename RD_1 "RD[1]") (joined
+           (portRef B (instanceRef RD_pad_1))
+           (portRef (member rd 6))
+          ))
+          (net (rename RD_in_2 "RD_in[2]") (joined
+           (portRef O (instanceRef RD_pad_2))
+           (portRef I (instanceRef Dout_pad_2))
+          ))
+          (net (rename RD_2 "RD[2]") (joined
+           (portRef B (instanceRef RD_pad_2))
+           (portRef (member rd 5))
+          ))
+          (net (rename RD_in_3 "RD_in[3]") (joined
+           (portRef O (instanceRef RD_pad_3))
+           (portRef I (instanceRef Dout_pad_3))
+          ))
+          (net (rename RD_3 "RD[3]") (joined
+           (portRef B (instanceRef RD_pad_3))
+           (portRef (member rd 4))
+          ))
+          (net (rename RD_in_4 "RD_in[4]") (joined
+           (portRef O (instanceRef RD_pad_4))
+           (portRef I (instanceRef Dout_pad_4))
+          ))
+          (net (rename RD_4 "RD[4]") (joined
+           (portRef B (instanceRef RD_pad_4))
+           (portRef (member rd 3))
+          ))
+          (net (rename RD_in_5 "RD_in[5]") (joined
+           (portRef O (instanceRef RD_pad_5))
+           (portRef I (instanceRef Dout_pad_5))
+          ))
+          (net (rename RD_5 "RD[5]") (joined
+           (portRef B (instanceRef RD_pad_5))
+           (portRef (member rd 2))
+          ))
+          (net (rename RD_in_6 "RD_in[6]") (joined
+           (portRef O (instanceRef RD_pad_6))
+           (portRef I (instanceRef Dout_pad_6))
+          ))
+          (net (rename RD_6 "RD[6]") (joined
+           (portRef B (instanceRef RD_pad_6))
+           (portRef (member rd 1))
+          ))
+          (net (rename RD_in_7 "RD_in[7]") (joined
+           (portRef O (instanceRef RD_pad_7))
+           (portRef I (instanceRef Dout_pad_7))
+          ))
+          (net (rename RD_7 "RD[7]") (joined
+           (portRef B (instanceRef RD_pad_7))
+           (portRef (member rd 0))
+          ))
+          (net nRCS_c (joined
+           (portRef Q (instanceRef nRCS))
+           (portRef I (instanceRef nRCS_pad))
+          ))
+          (net nRCS (joined
+           (portRef O (instanceRef nRCS_pad))
+           (portRef nRCS)
+          ))
+          (net RCLK_c (joined
+           (portRef O (instanceRef RCLK_pad))
+           (portRef CK (instanceRef CASr))
+           (portRef CK (instanceRef CASr2))
+           (portRef CK (instanceRef CASr3))
+           (portRef CK (instanceRef FS_17))
+           (portRef CK (instanceRef FS_16))
+           (portRef CK (instanceRef FS_15))
+           (portRef CK (instanceRef FS_14))
+           (portRef CK (instanceRef FS_13))
+           (portRef CK (instanceRef FS_12))
+           (portRef CK (instanceRef FS_11))
+           (portRef CK (instanceRef FS_10))
+           (portRef CK (instanceRef FS_9))
+           (portRef CK (instanceRef FS_8))
+           (portRef CK (instanceRef FS_7))
+           (portRef CK (instanceRef FS_6))
+           (portRef CK (instanceRef FS_5))
+           (portRef CK (instanceRef FS_4))
+           (portRef CK (instanceRef FS_3))
+           (portRef CK (instanceRef FS_2))
+           (portRef CK (instanceRef FS_1))
+           (portRef CK (instanceRef FS_0))
+           (portRef CK (instanceRef IS_3))
+           (portRef CK (instanceRef IS_2))
+           (portRef CK (instanceRef IS_1))
+           (portRef CK (instanceRef IS_0))
+           (portRef CK (instanceRef InitReady))
+           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef PHI2r))
+           (portRef CK (instanceRef PHI2r2))
+           (portRef CK (instanceRef PHI2r3))
+           (portRef CK (instanceRef RA10))
+           (portRef CK (instanceRef RASr))
+           (portRef CK (instanceRef RASr2))
+           (portRef CK (instanceRef RASr3))
+           (portRef CK (instanceRef RCKE))
+           (portRef CK (instanceRef RCKEEN))
+           (portRef CK (instanceRef Ready))
+           (portRef CK (instanceRef Ready_fast))
+           (portRef CK (instanceRef S_1))
+           (portRef CK (instanceRef S_0))
+           (portRef CK (instanceRef UFMCLK))
+           (portRef CK (instanceRef UFMSDI))
+           (portRef CK (instanceRef n8MEGEN))
+           (portRef CK (instanceRef nRCAS))
+           (portRef CK (instanceRef nRCS))
+           (portRef CK (instanceRef nRRAS))
+           (portRef CK (instanceRef nRWE))
+           (portRef CK (instanceRef nRowColSel))
+           (portRef CK (instanceRef nUFMCS))
+          ))
+          (net RCLK (joined
+           (portRef RCLK)
+           (portRef I (instanceRef RCLK_pad))
+          ))
+          (net RCKE_c (joined
+           (portRef Q (instanceRef RCKE))
+           (portRef C (instanceRef nRRAS_5_u_i_0))
+           (portRef I (instanceRef RCKE_pad))
+           (portRef C (instanceRef nRWE_RNO_3))
+          ))
+          (net RCKE (joined
+           (portRef O (instanceRef RCKE_pad))
+           (portRef RCKE)
+          ))
+          (net nRWE_c (joined
+           (portRef Q (instanceRef nRWE))
+           (portRef I (instanceRef nRWE_pad))
+          ))
+          (net nRWE (joined
+           (portRef O (instanceRef nRWE_pad))
+           (portRef nRWE)
+          ))
+          (net nRRAS_c (joined
+           (portRef Q (instanceRef nRRAS))
+           (portRef I (instanceRef nRRAS_pad))
+          ))
+          (net nRRAS (joined
+           (portRef O (instanceRef nRRAS_pad))
+           (portRef nRRAS)
+          ))
+          (net nRCAS_c (joined
+           (portRef Q (instanceRef nRCAS))
+           (portRef I (instanceRef nRCAS_pad))
+          ))
+          (net nRCAS (joined
+           (portRef O (instanceRef nRCAS_pad))
+           (portRef nRCAS)
+          ))
+          (net RDQMH_c (joined
+           (portRef Z (instanceRef RDQMH))
+           (portRef I (instanceRef RDQMH_pad))
+          ))
+          (net RDQMH (joined
+           (portRef O (instanceRef RDQMH_pad))
+           (portRef RDQMH)
+          ))
+          (net RDQML_c (joined
+           (portRef Z (instanceRef RDQML))
+           (portRef I (instanceRef RDQML_pad))
+          ))
+          (net RDQML (joined
+           (portRef O (instanceRef RDQML_pad))
+           (portRef RDQML)
+          ))
+          (net nUFMCS_c (joined
+           (portRef Q (instanceRef nUFMCS))
+           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef I (instanceRef nUFMCS_pad))
+          ))
+          (net nUFMCS (joined
+           (portRef O (instanceRef nUFMCS_pad))
+           (portRef nUFMCS)
+          ))
+          (net UFMCLK_c (joined
+           (portRef Q (instanceRef UFMCLK))
+           (portRef C (instanceRef UFMCLK_RNO))
+           (portRef I (instanceRef UFMCLK_pad))
+          ))
+          (net UFMCLK (joined
+           (portRef O (instanceRef UFMCLK_pad))
+           (portRef UFMCLK)
+          ))
+          (net UFMSDI_c (joined
+           (portRef Q (instanceRef UFMSDI))
+           (portRef C (instanceRef UFMSDI_RNO))
+           (portRef I (instanceRef UFMSDI_pad))
+          ))
+          (net UFMSDI (joined
+           (portRef O (instanceRef UFMSDI_pad))
+           (portRef UFMSDI)
+          ))
+          (net UFMSDO_c (joined
+           (portRef O (instanceRef UFMSDO_pad))
+           (portRef C (instanceRef LEDEN_5_i_m2))
+           (portRef C (instanceRef n8MEGEN_5_i_m2))
+          ))
+          (net UFMSDO (joined
+           (portRef UFMSDO)
+           (portRef I (instanceRef UFMSDO_pad))
+          ))
+          (net N_460_0 (joined
+           (portRef Z (instanceRef CmdSubmitted_RNO))
+           (portRef D (instanceRef CmdSubmitted))
+          ))
+          (net N_461_0 (joined
+           (portRef Z (instanceRef InitReady_RNO))
+           (portRef D (instanceRef InitReady))
+          ))
+          (net N_462_0 (joined
+           (portRef Z (instanceRef Ready_RNO))
+           (portRef D (instanceRef Ready))
+          ))
+          (net N_463_0 (joined
+           (portRef Z (instanceRef Ready_fast_RNO))
+           (portRef D (instanceRef Ready_fast))
+          ))
+          (net nFWE_c_i (joined
+           (portRef Z (instanceRef nFWE_pad_RNI420B))
+           (portRef D (instanceRef FWEr))
+           (portRef D (instanceRef FWEr_fast))
+          ))
+          (net nCRAS_c_i_0 (joined
+           (portRef Z (instanceRef RASr_RNO))
+           (portRef D (instanceRef RASr))
+          ))
+          (net nCCAS_c_i (joined
+           (portRef Z (instanceRef nCCAS_pad_RNISUR8))
+           (portRef D (instanceRef CASr))
+           (portRef D (instanceRef CBR))
+           (portRef D (instanceRef CBR_fast))
+           (portRef CK (instanceRef WRD_7))
+           (portRef CK (instanceRef WRD_6))
+           (portRef CK (instanceRef WRD_5))
+           (portRef CK (instanceRef WRD_4))
+           (portRef CK (instanceRef WRD_3))
+           (portRef CK (instanceRef WRD_2))
+           (portRef CK (instanceRef WRD_1))
+           (portRef CK (instanceRef WRD_0))
+          ))
+          (net Ready_fast_i (joined
+           (portRef Z (instanceRef Ready_fast_RNI29NA))
+           (portRef CD (instanceRef RA11))
+           (portRef CD (instanceRef RBA_1))
+           (portRef CD (instanceRef RBA_0))
+           (portRef PD (instanceRef RowA_9))
+           (portRef CD (instanceRef RowA_8))
+           (portRef CD (instanceRef RowA_7))
+           (portRef CD (instanceRef RowA_6))
+           (portRef PD (instanceRef RowA_5))
+           (portRef CD (instanceRef RowA_4))
+           (portRef CD (instanceRef RowA_3))
+           (portRef CD (instanceRef RowA_2))
+           (portRef CD (instanceRef RowA_1))
+           (portRef CD (instanceRef RowA_0))
+          ))
+          (net (rename IS_i_0 "IS_i[0]") (joined
+           (portRef Z (instanceRef IS_i_0))
+           (portRef D (instanceRef RA10))
+          ))
+          (net RASr2_i (joined
+           (portRef Z (instanceRef RASr2_RNIAFR1))
+           (portRef CD (instanceRef S_1))
+           (portRef CD (instanceRef S_0))
+          ))
+          (net nRWE_RNO_4 (joined
+           (portRef Z (instanceRef nRWE_RNO_4))
+           (portRef BLUT (instanceRef nRWE_RNO_1))
+          ))
+          (net nRWE_RNO_3 (joined
+           (portRef Z (instanceRef nRWE_RNO_3))
+           (portRef ALUT (instanceRef nRWE_RNO_1))
+          ))
+          (net CmdEnable_s_am (joined
+           (portRef Z (instanceRef CmdEnable_s_am))
+           (portRef BLUT (instanceRef CmdEnable_s))
+          ))
+          (net CmdEnable_s_bm (joined
+           (portRef Z (instanceRef CmdEnable_s_bm))
+           (portRef ALUT (instanceRef CmdEnable_s))
+          ))
+         )
+        (property orig_inst_of (string "RAM2GS"))
+       )
+    )
+  )
+  (design RAM2GS (cellRef RAM2GS (libraryRef work))
+	(property PART (string "lcmxo640c-3") ))
+)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.htm b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.htm
index 7f902d7..2007929 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.htm
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.htm
@@ -1,9 +1,9 @@
-
- 
- syntmp/RAM2GS_LCMXO640C_impl1_srr.htm log file
- 
- 
- 
- 				 
-
- 
+
+ 
+ syntmp/RAM2GS_LCMXO640C_impl1_srr.htm log file
+ 
+ 
+ 
+ 				 
+
+ 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
index 521e6fd..219cf39 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
@@ -1,1745 +1,1745 @@
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-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Wed Aug 16 04:50:55 2023 *
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-NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
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+NOTE DATE CREATED: Sat Aug 19 20:57:27 2023 *
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diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
index d0353b8..9ce5b3b 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
@@ -1,4 +1,4 @@
----- MParTrce Tool Log File ----
-
-==== Par Standard Out ====
-==== End of Par Standard Out ====
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
index fb266c4..cbdd36d 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
@@ -1,336 +1,336 @@
-
-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-Design Information
-------------------
-
-Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial -ioreg
-     b RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
-     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/
-     Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplif
-     y.lpf -lpf
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c
-     0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO640CTQFP100
-Target Performance:   3
-Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/16/23  04:50:46
-
-Design Summary
---------------
-
-   Number of PFU registers:    92 out of   640 (14%)
-   Number of SLICEs:        69 out of   320 (22%)
-      SLICEs as Logic/ROM:     69 out of   320 (22%)
-      SLICEs as RAM:            0 out of   192 (0%)
-      SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        137 out of   640 (21%)
-      Number used as logic LUTs:        119
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 74 (91%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  5
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net N_31: 1 loads, 1 LSLICEs
-     Net N_33: 1 loads, 1 LSLICEs
-     Net N_159_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
-   Number of LSRs:  4
-     Net RA10s_i: 1 loads, 1 LSLICEs
-     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
-     Net RASr2: 2 loads, 2 LSLICEs
-     Net Ready_fast: 7 loads, 7 LSLICEs
-
-                                    Page 1
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:46
-
-Design Summary (cont)
----------------------
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net InitReady: 16 loads
-     Net Ready: 16 loads
-     Net S[1]: 13 loads
-     Net CO0: 12 loads
-     Net nRowColSel: 12 loads
-     Net RASr2: 11 loads
-     Net Din_c[5]: 10 loads
-     Net Din_c[3]: 9 loads
-     Net IS[0]: 9 loads
-     Net MAin_c[1]: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-Design Errors/Warnings
-----------------------
-
-   No errors or warnings present.
-
-IO (PIO) Attributes
--------------------
-
-+---------------------+-----------+-----------+------------+------------+
-| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
-|                     |           |  IO_TYPE  | Register   |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[0]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| PHI2                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDO              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQML               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 2
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:46
-
-IO (PIO) Attributes (cont)
---------------------------
-| RCKE                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCLK                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCS                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[7]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[6]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[5]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[4]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[3]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[2]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[1]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| LED                 | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nFWE                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCRAS               | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCCAS               | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 3
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:46
-
-IO (PIO) Attributes (cont)
---------------------------
-| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[7]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[6]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[5]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[4]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[3]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[2]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[1]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[0]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[1]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[0]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[9]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[8]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[7]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[6]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[5]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[4]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[3]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[2]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[1]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[0]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-
-
-                                    Page 4
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:46
-
-Removed logic
--------------
-
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal nCRAS_c_i was merged into signal nCRAS_c
-Signal nFWE_c_i was merged into signal nFWE_c
-Signal nCRAS_c_i_0 was merged into signal nCRAS_c
-Signal nCCAS_c_i was merged into signal nCCAS_c
-Signal Ready_fast_i was merged into signal Ready_fast
-Signal IS_i[0] was merged into signal IS[0]
-Signal RASr2_i was merged into signal RASr2
-Signal XOR8MEG.CN was merged into signal PHI2_c
-Signal GND undriven or does not drive anything - clipped.
-Signal VCC undriven or does not drive anything - clipped.
-Signal FS_cry[2] undriven or does not drive anything - clipped.
-Signal FS_cry[4] undriven or does not drive anything - clipped.
-Signal FS_cry[6] undriven or does not drive anything - clipped.
-Signal FS_cry[8] undriven or does not drive anything - clipped.
-Signal FS_cry[10] undriven or does not drive anything - clipped.
-Signal FS_cry[12] undriven or does not drive anything - clipped.
-Signal FS_cry[14] undriven or does not drive anything - clipped.
-Signal FS_cry_0_COUT1[16] undriven or does not drive anything - clipped.
-Signal FS_cry[16] undriven or does not drive anything - clipped.
-Signal FS_cry[0] undriven or does not drive anything - clipped.
-Block nCRAS_pad_RNIBPVB was optimized away.
-Block nFWE_pad_RNI420B was optimized away.
-Block RASr_RNO was optimized away.
-Block nCCAS_pad_RNISUR8 was optimized away.
-Block Ready_fast_RNI29NA was optimized away.
-Block IS_i[0] was optimized away.
-Block RASr2_RNIAFR1 was optimized away.
-Block XOR8MEG.CN was optimized away.
-Block GND was optimized away.
-Block VCC was optimized away.
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 30 MB
-        
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-                                    Page 5
-
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial -ioreg
+     b RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf
+     Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf
+     -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO.lpf -c 0 -gui -msgset
+     Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/19/23  20:57:13
+
+Design Summary
+--------------
+
+   Number of PFU registers:    92 out of   640 (14%)
+   Number of SLICEs:        69 out of   320 (22%)
+      SLICEs as Logic/ROM:     69 out of   320 (22%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        137 out of   640 (21%)
+      Number used as logic LUTs:        119
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
+     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
+     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  5
+     Net XOR8MEG18: 3 loads, 3 LSLICEs
+     Net N_31: 1 loads, 1 LSLICEs
+     Net N_33: 1 loads, 1 LSLICEs
+     Net N_159_i: 2 loads, 2 LSLICEs
+     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
+   Number of LSRs:  4
+     Net RA10s_i: 1 loads, 1 LSLICEs
+     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
+     Net RASr2: 2 loads, 2 LSLICEs
+     Net Ready_fast: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:57:13
+
+Design Summary (cont)
+---------------------
+     Net InitReady: 16 loads
+     Net Ready: 16 loads
+     Net S[1]: 13 loads
+     Net CO0: 12 loads
+     Net nRowColSel: 12 loads
+     Net RASr2: 11 loads
+     Net Din_c[5]: 10 loads
+     Net Din_c[3]: 9 loads
+     Net IS[0]: 9 loads
+     Net MAin_c[1]: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:57:13
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:57:13
+
+IO (PIO) Attributes (cont)
+--------------------------
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:57:13
+
+Removed logic
+-------------
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_c_i was merged into signal nCRAS_c
+Signal nFWE_c_i was merged into signal nFWE_c
+Signal nCRAS_c_i_0 was merged into signal nCRAS_c
+Signal nCCAS_c_i was merged into signal nCCAS_c
+Signal Ready_fast_i was merged into signal Ready_fast
+Signal IS_i[0] was merged into signal IS[0]
+Signal RASr2_i was merged into signal RASr2
+Signal XOR8MEG.CN was merged into signal PHI2_c
+Signal GND undriven or does not drive anything - clipped.
+Signal VCC undriven or does not drive anything - clipped.
+Signal FS_cry[2] undriven or does not drive anything - clipped.
+Signal FS_cry[4] undriven or does not drive anything - clipped.
+Signal FS_cry[6] undriven or does not drive anything - clipped.
+Signal FS_cry[8] undriven or does not drive anything - clipped.
+Signal FS_cry[10] undriven or does not drive anything - clipped.
+Signal FS_cry[12] undriven or does not drive anything - clipped.
+Signal FS_cry[14] undriven or does not drive anything - clipped.
+Signal FS_cry_0_COUT1[16] undriven or does not drive anything - clipped.
+Signal FS_cry[16] undriven or does not drive anything - clipped.
+Signal FS_cry[0] undriven or does not drive anything - clipped.
+Block nCRAS_pad_RNIBPVB was optimized away.
+Block nFWE_pad_RNI420B was optimized away.
+Block RASr_RNO was optimized away.
+Block nCCAS_pad_RNISUR8 was optimized away.
+Block Ready_fast_RNI29NA was optimized away.
+Block IS_i[0] was optimized away.
+Block RASr2_RNIAFR1 was optimized away.
+Block XOR8MEG.CN was optimized away.
+Block GND was optimized away.
+Block VCC was optimized away.
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 51 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 5
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
index dc1115c..fb895f8 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
@@ -1,551 +1,551 @@
-
-comp 0: SLICE_0 (FSLICE)
-
-comp 1: SLICE_1 (FSLICE)
-
-comp 2: SLICE_2 (FSLICE)
-
-comp 3: SLICE_3 (FSLICE)
-
-comp 4: SLICE_4 (FSLICE)
-
-comp 5: SLICE_5 (FSLICE)
-
-comp 6: SLICE_6 (FSLICE)
-
-comp 7: SLICE_7 (FSLICE)
-
-comp 8: SLICE_8 (FSLICE)
-
-comp 9: SLICE_9 (FSLICE)
-ADSubmitted_r = (~CmdEnable16*((~C1WR_0_a2*ADSubmitted)+CmdEnable17))
-ADSubmitted.D = ADSubmitted_r
-ADSubmitted.CLK = ~PHI2_c
-ADSubmitted.SP = VCC
-ADSubmitted.LSR = GND
-CmdEnable17 = (N_147*(MAin_c[0]*(CmdEnable17_0_a2_4*CmdEnable17_0_a2_3)))
-
-comp 10: SLICE_14 (FSLICE)
-C1Submitted_RNO = (~MAin_c[1]*(CmdEnable16+C1Submitted)+MAin_c[1]*(~N_147*(CmdEnable16+C1Submitted)+N_147*CmdEnable16))
-C1Submitted.D = C1Submitted_RNO
-C1Submitted.CLK = ~PHI2_c
-C1Submitted.SP = VCC
-C1Submitted.LSR = GND
-CmdEnable16 = (N_147*(CmdEnable16_0_a2_5*CmdEnable16_0_a2_4))
-
-comp 11: SLICE_19 (FSLICE)
-N_177_i = (~CO0+S[1])
-CO0.D = N_177_i
-CO0.CLK = RCLK_c
-CO0.SP = VCC
-CO0.LSR = ~RASr2
-Ready_0_sqmuxa_0_a3_2 = (S[1]*(~RASr2*(IS[3]*CO0)))
-
-comp 12: SLICE_20 (FSLICE)
-CmdEnable_s = ((CmdEnable+ADSubmitted)*CmdEnable16)+(((C1Submitted*un1_CMDWR*CmdEnable17)+(CmdEnable*CmdEnable17)+(~un1_CMDWR*CmdEnable))*~CmdEnable16)
-CmdEnable.D = CmdEnable_s
-CmdEnable.CLK = ~PHI2_c
-CmdEnable.SP = VCC
-CmdEnable.LSR = GND
-
-comp 13: SLICE_21 (FSLICE)
-N_21_i = (~N_152*(~N_133*~N_132)+N_152*(~N_133*(~N_132*LEDEN)))
-CmdLEDEN.D = N_21_i
-CmdLEDEN.CLK = ~PHI2_c
-CmdLEDEN.SP = XOR8MEG18
-CmdLEDEN.LSR = GND
-N_152 = (~N_128*(Din_c[5]*~Din_c[3]))
-
-comp 14: SLICE_22 (FSLICE)
-N_460_0 = (CmdSubmitted_1_sqmuxa+CmdSubmitted)
-CmdSubmitted.D = N_460_0
-CmdSubmitted.CLK = ~PHI2_c
-CmdSubmitted.SP = VCC
-CmdSubmitted.LSR = GND
-N_136 = (PHI2r3*(~PHI2r2*(InitReady*CmdSubmitted)))
-
-comp 15: SLICE_26 (FSLICE)
-N_19_i = (~n8MEGEN*(~N_152*~Cmdn8MEGEN_4_u_i_0)+n8MEGEN*~Cmdn8MEGEN_4_u_i_0)
-Cmdn8MEGEN.D = N_19_i
-Cmdn8MEGEN.CLK = ~PHI2_c
-Cmdn8MEGEN.SP = XOR8MEG18
-Cmdn8MEGEN.LSR = GND
-Cmdn8MEGEN_4_u_i_0 = (~N_128*(~N_43*(~Cmdn8MEGEN+CmdEnable16_4)+N_43*CmdEnable16_4)+N_128*~Cmdn8MEGEN)
-
-comp 16: SLICE_29 (FSLICE)
-N_64_i_i = (~N_155*(Ready@~IS[0])+N_155*IS[0])
-IS[0].D = N_64_i_i
-IS[0].CLK = RCLK_c
-IS[0].SP = VCC
-IS[0].LSR = GND
-N_24 = ((~N_160*(~N_155*IS[0])+N_160*~N_155)+nRRAS_5_u_i_0)
-
-comp 17: SLICE_30 (FSLICE)
-N_56_i = (IS[1]@IS[0])
-IS[1].D = N_56_i
-IS[1].CLK = RCLK_c
-IS[1].SP = N_159_i
-IS[1].LSR = GND
-N_60_i_i = (IS[2]@(IS[1]*IS[0]))
-IS[2].D = N_60_i_i
-IS[2].CLK = RCLK_c
-IS[2].SP = N_159_i
-IS[2].LSR = GND
-
-comp 18: SLICE_31 (FSLICE)
-N_61_i_i = (~IS[0]*IS[3]+IS[0]*(~IS[1]*IS[3]+IS[1]*(IS[2]@IS[3])))
-IS[3].D = N_61_i_i
-IS[3].CLK = RCLK_c
-IS[3].SP = N_159_i
-IS[3].LSR = GND
-RA10s_i = ((~IS[3]+(IS[1]+IS[2]))+N_159)
-
-comp 19: SLICE_32 (FSLICE)
-N_461_0 = (InitReady3+InitReady)
-InitReady.D = N_461_0
-InitReady.CLK = RCLK_c
-InitReady.SP = VCC
-InitReady.LSR = GND
-UFMSDI_ens2_i_a0 = (~UFMSDI_ens2_i_a2_4_2*~InitReady+UFMSDI_ens2_i_a2_4_2*(~N_126*~InitReady+N_126*(N_51*~InitReady)))
-
-comp 20: SLICE_33 (FSLICE)
-N_70 = (~UFMSDO_c*(~InitReady+CmdLEDEN)+UFMSDO_c*(InitReady*CmdLEDEN))
-LEDEN.D = N_70
-LEDEN.CLK = RCLK_c
-LEDEN.SP = N_33
-LEDEN.LSR = GND
-LED_c = ((~LEDEN+CBR)+nCRAS_c)
-
-comp 21: SLICE_39 (FSLICE)
-RA11_2 = (~n8MEGEN*(XOR8MEG@Din_c[6])+n8MEGEN*XOR8MEG)
-RA_c[11].D = RA11_2
-RA_c[11].CLK = PHI2_c
-RA_c[11].SP = VCC
-RA_c[11].LSR = ~Ready_fast
-N_171 = (~un1_Din_4*XOR8MEG)
-
-comp 22: SLICE_41 (FSLICE)
-RCKEEN_8 = (~Ready*RCKEEN_8_u_0_0+Ready*(~RCKEEN_8_u_1*RCKEEN_8_u_0_0+RCKEEN_8_u_1*(~CBR+RCKEEN_8_u_0_0)))
-RCKEEN.D = RCKEEN_8
-RCKEEN.CLK = RCLK_c
-RCKEEN.SP = VCC
-RCKEEN.LSR = GND
-RCKEEN_8_u_1 = (~S[1]*(~FWEr_fast+CO0)+S[1]*(FWEr_fast*(~CO0+~CASr2)))
-PHI2r2.D = PHI2r
-PHI2r2.CLK = RCLK_c
-PHI2r2.SP = VCC
-PHI2r2.LSR = GND
-
-comp 23: SLICE_42 (FSLICE)
-RCKE_2 = (~RCKEEN*(RASr3*~RASr2)+RCKEEN*((RASr+RASr2)+RASr3))
-RCKE_c.D = RCKE_2
-RCKE_c.CLK = RCLK_c
-RCKE_c.SP = VCC
-RCKE_c.LSR = GND
-m18_0_a3_3 = (RASr2*(~IS[2]*(~IS[1]*IS[0])))
-PHI2r.D = PHI2_c
-PHI2r.CLK = RCLK_c
-PHI2r.SP = VCC
-PHI2r.LSR = GND
-
-comp 24: SLICE_43 (FSLICE)
-N_462_0 = (~InitReady*Ready+InitReady*(~N_165*(Ready+Ready_0_sqmuxa_0_a3_2)+N_165*Ready))
-Ready.D = N_462_0
-Ready.CLK = RCLK_c
-Ready.SP = VCC
-Ready.LSR = GND
-RCKEEN_8_u_0_0 = (~S_0_i_o2[1]*(~InitReady*(~RASr2*Ready)+InitReady*(~RASr2+~Ready))+S_0_i_o2[1]*(InitReady*~Ready))
-PHI2r3.D = PHI2r2
-PHI2r3.CLK = RCLK_c
-PHI2r3.SP = VCC
-PHI2r3.LSR = GND
-
-comp 25: SLICE_44 (FSLICE)
-N_463_0 = (Ready_0_sqmuxa+Ready_fast)
-Ready_fast.D = N_463_0
-Ready_fast.CLK = RCLK_c
-Ready_fast.SP = VCC
-Ready_fast.LSR = GND
-Ready_0_sqmuxa = (Ready_0_sqmuxa_0_a3_2*(~Ready*(~N_165*InitReady)))
-RASr.D = ~nCRAS_c
-RASr.CLK = RCLK_c
-RASr.SP = VCC
-RASr.LSR = GND
-
-comp 26: SLICE_50 (FSLICE)
-S_0_i_o2[1] = (CO0+S[1])
-S[1].D = S_0_i_o2[1]
-S[1].CLK = RCLK_c
-S[1].SP = VCC
-S[1].LSR = ~RASr2
-nRRAS_0_sqmuxa = (~CO0*(~S[1]*Ready))
-
-comp 27: SLICE_51 (FSLICE)
-UFMCLK_RNO = (~UFMCLK_r_i_m4_xx_mm_1*(~UFMCLK_c*(~nUFMCS15*N_139_i)+UFMCLK_c*~nUFMCS15)+UFMCLK_r_i_m4_xx_mm_1*(UFMCLK_c*(~nUFMCS15*~N_139_i)))
-UFMCLK_c.D = UFMCLK_RNO
-UFMCLK_c.CLK = RCLK_c
-UFMCLK_c.SP = VCC
-UFMCLK_c.LSR = GND
-UFMCLK_r_i_m4_xx_mm_1 = (~N_129*((~CmdUFMCLK+~InitReady)+UFMCLK_r_i_a2_2_2)+N_129*((~CmdUFMCLK*InitReady)+UFMCLK_r_i_a2_2_2))
-RASr2.D = RASr
-RASr2.CLK = RCLK_c
-RASr2.SP = VCC
-RASr2.LSR = GND
-
-comp 28: SLICE_52 (FSLICE)
-UFMSDI_RNO = (~UFMSDI_r_xx_mm_1*(UFMSDI_c*(~nUFMCS15*~N_139_i))+UFMSDI_r_xx_mm_1*(~UFMSDI_c*(~nUFMCS15*N_139_i)+UFMSDI_c*~nUFMCS15))
-UFMSDI_c.D = UFMSDI_RNO
-UFMSDI_c.CLK = RCLK_c
-UFMSDI_c.SP = VCC
-UFMSDI_c.LSR = GND
-N_139_i = (~PHI2r3*~InitReady+PHI2r3*(~PHI2r2*(~InitReady+CmdSubmitted)+PHI2r2*~InitReady))
-RASr3.D = RASr2
-RASr3.CLK = RCLK_c
-RASr3.SP = VCC
-RASr3.LSR = GND
-
-comp 29: SLICE_55 (FSLICE)
-RA_c[4] = (~nRowColSel*RowA[4]+nRowColSel*MAin_c[4])
-WRD[4].D = Din_c[4]
-WRD[4].CLK = ~nCCAS_c
-WRD[4].SP = VCC
-WRD[4].LSR = GND
-WRD[5].D = Din_c[5]
-WRD[5].CLK = ~nCCAS_c
-WRD[5].SP = VCC
-WRD[5].LSR = GND
-
-comp 30: SLICE_56 (FSLICE)
-N_126 = (~FS[9]*FS[7]+FS[9]*(~FS[7]*FS[5]))
-WRD[6].D = Din_c[6]
-WRD[6].CLK = ~nCCAS_c
-WRD[6].SP = VCC
-WRD[6].LSR = GND
-C1WR_0_a2_0_11 = (Bank[7]*(Bank[6]*(Bank[5]*~Bank[2])))
-WRD[7].D = Din_c[7]
-WRD[7].CLK = ~nCCAS_c
-WRD[7].SP = VCC
-WRD[7].LSR = GND
-
-comp 31: SLICE_57 (FSLICE)
-XOR8MEG_3 = (~XOR8MEG_3_u_0_a3_2*N_171+XOR8MEG_3_u_0_a3_2*((~LEDEN+~Din_c[1])+N_171))
-XOR8MEG.D = XOR8MEG_3
-XOR8MEG.CLK = ~PHI2_c
-XOR8MEG.SP = XOR8MEG18
-XOR8MEG.LSR = GND
-XOR8MEG_3_u_0_a3_2 = (un1_Din_4*(~Din_c[3]*(Din_c[2]*Din_c[0])))
-
-comp 32: SLICE_58 (FSLICE)
-N_69 = (~UFMSDO_c*(~InitReady+Cmdn8MEGEN)+UFMSDO_c*(InitReady*Cmdn8MEGEN))
-n8MEGEN.D = N_69
-n8MEGEN.CLK = RCLK_c
-n8MEGEN.SP = N_31
-n8MEGEN.LSR = GND
-N_151 = (~N_51*(~InitReady*~FS[8]))
-
-comp 33: SLICE_59 (FSLICE)
-N_37_i = (~g0_1*(~S[1]*(~nRCAS_0_sqmuxa_1*N_41)+S[1]*~nRCAS_0_sqmuxa_1)+g0_1*(~nRCAS_0_sqmuxa_1*N_41))
-nRCAS_c.D = N_37_i
-nRCAS_c.CLK = RCLK_c
-nRCAS_c.SP = VCC
-nRCAS_c.LSR = GND
-N_41 = (~S[1]*((~N_160+N_155)+Ready)+S[1]*(~Ready*(~N_160+N_155)))
-
-comp 34: SLICE_60 (FSLICE)
-N_28_i = (~RCKEEN_8_u_0_a2_1_out*~N_24+RCKEEN_8_u_0_a2_1_out*(~N_28_i_1*(~N_24*CBR)+N_28_i_1*~N_24))
-nRCS_c.D = N_28_i
-nRCS_c.CLK = RCLK_c
-nRCS_c.SP = VCC
-nRCS_c.LSR = GND
-N_28_i_1 = (~CASr2*(FWEr_fast+CO0)+CASr2*(~CASr3*(CO0@FWEr_fast)+CASr3*(FWEr_fast+CO0)))
-
-comp 35: SLICE_61 (FSLICE)
-N_24_i = (~IS[0]*(~N_155*(~N_160*~nRRAS_5_u_i_0)+N_155*~nRRAS_5_u_i_0)+IS[0]*(N_155*~nRRAS_5_u_i_0))
-nRRAS_c.D = N_24_i
-nRRAS_c.CLK = RCLK_c
-nRRAS_c.SP = VCC
-nRRAS_c.LSR = GND
-nRRAS_5_u_i_0 = (Ready*(~RCKE_c*(RASr2*~S_0_i_o2[1])+RCKE_c*~S_0_i_o2[1]))
-
-comp 36: SLICE_62 (FSLICE)
-N_39_i = (~m18_0_a2_1*((~G_17_1+~FWEr)+nRCAS_0_sqmuxa_1)+m18_0_a2_1*((G_17_1*~FWEr)+nRCAS_0_sqmuxa_1))
-nRWE_c.D = N_39_i
-nRWE_c.CLK = RCLK_c
-nRWE_c.SP = VCC
-nRWE_c.LSR = GND
-nRCAS_0_sqmuxa_1 = (Ready*(RASr2*(~S_0_i_o2[1]*CBR_fast)))
-
-comp 37: SLICE_63 (FSLICE)
-nRowColSel_0_0 = (~S[1]*(~Ready*N_179+Ready*(CO0+N_179))+S[1]*(~Ready*N_179+Ready*(~CO0+N_179)))
-nRowColSel.D = nRowColSel_0_0
-nRowColSel.CLK = RCLK_c
-nRowColSel.SP = VCC
-nRowColSel.LSR = nRRAS_0_sqmuxa
-N_179 = (Ready*(FWEr*(~CBR*~CASr3)))
-
-comp 38: SLICE_64 (FSLICE)
-nUFMCS_s_0_N_5_i = (~nUFMCS_s_0_N_5_i_N_2L1*((N_139_i+nUFMCS15)+nUFMCS_c)+nUFMCS_s_0_N_5_i_N_2L1*(~nUFMCS_c*nUFMCS15+nUFMCS_c*(~N_139_i+nUFMCS15)))
-nUFMCS_c.D = nUFMCS_s_0_N_5_i
-nUFMCS_c.CLK = RCLK_c
-nUFMCS_c.SP = VCC
-nUFMCS_c.LSR = GND
-nUFMCS15 = (~N_51*(~InitReady*(~FS[11]*~FS[10])))
-
-comp 39: nRWE_RNO_1/SLICE_65 (FSLICE)
-m18_0_a2_1 = ((~RASr2*RCKE_c*~CO0*~S[1])*Ready)+((InitReady*m18_0_a3_3*~CO0*~S[1])*~Ready)
-
-comp 40: SLICE_66 (FSLICE)
-UFMCLK_r_i_a2_2_2 = (N_95_5*(N_95_3*(~InitReady*FS[16])))
-RowA[0].D = MAin_c[0]
-RowA[0].CLK = ~nCRAS_c
-RowA[0].SP = VCC
-RowA[0].LSR = ~Ready_fast
-nUFMCS_s_0_N_5_i_N_2L1 = (~UFMCLK_r_i_a2_2_2*(~InitReady+CmdUFMCS))
-RowA[1].D = MAin_c[1]
-RowA[1].CLK = ~nCRAS_c
-RowA[1].SP = VCC
-RowA[1].LSR = ~Ready_fast
-
-comp 41: SLICE_67 (FSLICE)
-XOR8MEG18 = (N_147*(~MAin_c[1]*(MAin_c[0]*CmdEnable)))
-RowA[4].D = MAin_c[4]
-RowA[4].CLK = ~nCRAS_c
-RowA[4].SP = VCC
-RowA[4].LSR = ~Ready_fast
-CmdUFMCLK_1_sqmuxa = (~Din_c[3]*(Din_c[5]*(~N_128*XOR8MEG18)))
-RowA[5].D = MAin_c[5]
-RowA[5].CLK = ~nCRAS_c
-RowA[5].SP = VCC
-RowA[5].LSR = ~Ready_fast
-
-comp 42: SLICE_68 (FSLICE)
-N_31 = (~un1_FS_14_i_a2_0_1*N_136+un1_FS_14_i_a2_0_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
-un1_FS_14_i_a2_0_1 = (~FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
-
-comp 43: SLICE_69 (FSLICE)
-N_33 = (~un1_FS_13_i_a2_1*N_136+un1_FS_13_i_a2_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
-un1_FS_13_i_a2_1 = (FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
-
-comp 44: SLICE_70 (FSLICE)
-C1WR_0_a2 = (N_147*MAin_c[1])
-Bank[0].D = Din_c[0]
-Bank[0].CLK = PHI2_c
-Bank[0].SP = VCC
-Bank[0].LSR = GND
-N_147 = (C1WR_0_a2_0_11*(C1WR_0_a2_0_10*(Bank[1]*Bank[0])))
-Bank[1].D = Din_c[1]
-Bank[1].CLK = PHI2_c
-Bank[1].SP = VCC
-Bank[1].LSR = GND
-
-comp 45: SLICE_71 (FSLICE)
-C1WR_0_a2_0_10 = (C1WR_0_a2_0_4*(C1WR_0_a2_0_3*(Bank[4]*Bank[3])))
-Bank[2].D = Din_c[2]
-Bank[2].CLK = PHI2_c
-Bank[2].SP = VCC
-Bank[2].LSR = GND
-C1WR_0_a2_0_4 = (MAin_c[7]*(MAin_c[6]*(MAin_c[5]*MAin_c[4])))
-Bank[3].D = Din_c[3]
-Bank[3].CLK = PHI2_c
-Bank[3].SP = VCC
-Bank[3].LSR = GND
-
-comp 46: SLICE_72 (FSLICE)
-N_129 = (~N_51*(FS[11]*FS[4])+N_51*FS[1])
-RowA[2].D = MAin_c[2]
-RowA[2].CLK = ~nCRAS_c
-RowA[2].SP = VCC
-RowA[2].LSR = ~Ready_fast
-N_51 = ((FS[12]+FS[16])+UFMSDI_ens2_i_o2_0_3)
-RowA[3].D = MAin_c[3]
-RowA[3].CLK = ~nCRAS_c
-RowA[3].SP = VCC
-RowA[3].LSR = ~Ready_fast
-
-comp 47: SLICE_73 (FSLICE)
-N_159 = (N_155+Ready)
-CmdUFMCLK.D = Din_c[1]
-CmdUFMCLK.CLK = ~PHI2_c
-CmdUFMCLK.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMCLK.LSR = GND
-N_155 = (((~InitReady+~RASr2)+S[1])+CO0)
-CmdUFMCS.D = Din_c[2]
-CmdUFMCS.CLK = ~PHI2_c
-CmdUFMCS.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMCS.LSR = GND
-
-comp 48: SLICE_74 (FSLICE)
-InitReady3 = (N_95_5*(N_95_3*(FS[16]*FS[10])))
-CmdUFMSDI.D = Din_c[0]
-CmdUFMSDI.CLK = ~PHI2_c
-CmdUFMSDI.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMSDI.LSR = GND
-N_95_3 = (FS[14]*FS[11])
-
-comp 49: SLICE_75 (FSLICE)
-N_133 = (~N_128*(~Din_c[5]*~Din_c[1]))
-CASr.D = ~nCCAS_c
-CASr.CLK = RCLK_c
-CASr.SP = VCC
-CASr.LSR = GND
-N_128 = ((~Din_c[4]+Din_c[6])+Din_c[7])
-CASr2.D = CASr
-CASr2.CLK = RCLK_c
-CASr2.SP = VCC
-CASr2.LSR = GND
-
-comp 50: SLICE_76 (FSLICE)
-CmdEnable16_0_a2_4 = (~MAin_c[0]*(~Din_c[3]*(~Din_c[1]*CmdEnable16_4)))
-Bank[4].D = Din_c[4]
-Bank[4].CLK = PHI2_c
-Bank[4].SP = VCC
-Bank[4].LSR = GND
-CmdEnable16_4 = (~Din_c[5]*Din_c[0])
-Bank[5].D = Din_c[5]
-Bank[5].CLK = PHI2_c
-Bank[5].SP = VCC
-Bank[5].LSR = GND
-
-comp 51: SLICE_77 (FSLICE)
-CmdEnable16_0_a2_5 = (MAin_c[1]*(Din_c[6]*(~Din_c[2]*CmdEnable16_1)))
-Bank[6].D = Din_c[6]
-Bank[6].CLK = PHI2_c
-Bank[6].SP = VCC
-Bank[6].LSR = GND
-CmdEnable16_1 = (Din_c[7]*~Din_c[4])
-Bank[7].D = Din_c[7]
-Bank[7].CLK = PHI2_c
-Bank[7].SP = VCC
-Bank[7].LSR = GND
-
-comp 52: SLICE_78 (FSLICE)
-CmdEnable17_0_a2_4 = (~N_43*(MAin_c[1]*(~Din_c[6]*Din_c[2])))
-CBR.D = ~nCCAS_c
-CBR.CLK = ~nCRAS_c
-CBR.SP = VCC
-CBR.LSR = GND
-N_43 = (~Din_c[5]+~Din_c[3])
-CBR_fast.D = ~nCCAS_c
-CBR_fast.CLK = ~nCRAS_c
-CBR_fast.SP = VCC
-CBR_fast.LSR = GND
-
-comp 53: SLICE_79 (FSLICE)
-G_17_1 = (m6_0_a2_2*(S[1]*(CO0*~CBR)))
-WRD[0].D = Din_c[0]
-WRD[0].CLK = ~nCCAS_c
-WRD[0].SP = VCC
-WRD[0].LSR = GND
-m6_0_a2_2 = (Ready*(~CASr3*CASr2))
-WRD[1].D = Din_c[1]
-WRD[1].CLK = ~nCCAS_c
-WRD[1].SP = VCC
-WRD[1].LSR = GND
-
-comp 54: SLICE_80 (FSLICE)
-g0_1 = (~g4_0_0_0*(~FWEr*(~CO0*~CBR_fast))+g4_0_0_0*(~FWEr*(~CO0*~CBR_fast)+FWEr*(CO0*~CBR_fast)))
-RowA[8].D = MAin_c[8]
-RowA[8].CLK = ~nCRAS_c
-RowA[8].SP = VCC
-RowA[8].LSR = ~Ready_fast
-g4_0_0_0 = (~CASr3*CASr2)
-RowA[9].D = MAin_c[9]
-RowA[9].CLK = ~nCRAS_c
-RowA[9].SP = VCC
-RowA[9].LSR = ~Ready_fast
-
-comp 55: SLICE_81 (FSLICE)
-N_95_5 = (FS[17]*(FS[15]*(FS[13]*FS[12])))
-FWEr.D = ~nFWE_c
-FWEr.CLK = ~nCRAS_c
-FWEr.SP = VCC
-FWEr.LSR = GND
-UFMSDI_ens2_i_o2_0_3 = (((FS[13]+FS[14])+FS[15])+FS[17])
-FWEr_fast.D = ~nFWE_c
-FWEr_fast.CLK = ~nCRAS_c
-FWEr_fast.SP = VCC
-FWEr_fast.LSR = GND
-
-comp 56: SLICE_82 (FSLICE)
-CmdSubmitted_1_sqmuxa = (~Din_c[3]*(~N_128*XOR8MEG18)+Din_c[3]*(~Din_c[5]*(~N_128*XOR8MEG18)))
-CASr3.D = CASr2
-CASr3.CLK = RCLK_c
-CASr3.SP = VCC
-CASr3.LSR = GND
-N_132 = (~Din_c[3]*(~CmdLEDEN*N_128)+Din_c[3]*(~Din_c[5]*(~CmdLEDEN*N_128)+Din_c[5]*~CmdLEDEN))
-
-comp 57: SLICE_83 (FSLICE)
-N_165 = (~IS[2]+(~IS[1]+~IS[0]))
-RBA_c[0].D = CROW_c[0]
-RBA_c[0].CLK = ~nCRAS_c
-RBA_c[0].SP = VCC
-RBA_c[0].LSR = ~Ready_fast
-N_160 = ((IS[1]+IS[2])+IS[3])
-RBA_c[1].D = CROW_c[1]
-RBA_c[1].CLK = ~nCRAS_c
-RBA_c[1].SP = VCC
-RBA_c[1].LSR = ~Ready_fast
-
-comp 58: SLICE_84 (FSLICE)
-N_137_6 = (FS[10]*(~FS[7]*(~FS[6]*~FS[1])))
-UFMSDI_ens2_i_a2_4_2 = (FS[11]*(~FS[10]*(~FS[8]*FS[6])))
-
-comp 59: SLICE_85 (FSLICE)
-un1_Din_4 = (~Din_c[7]*(~Din_c[6]*(~Din_c[5]*~Din_c[4])))
-WRD[2].D = Din_c[2]
-WRD[2].CLK = ~nCCAS_c
-WRD[2].SP = VCC
-WRD[2].LSR = GND
-CmdEnable17_0_a2_3 = (~Din_c[4]*(Din_c[7]*(Din_c[0]*~Din_c[1])))
-WRD[3].D = Din_c[3]
-WRD[3].CLK = ~nCCAS_c
-WRD[3].SP = VCC
-WRD[3].LSR = GND
-
-comp 60: SLICE_86 (FSLICE)
-RA_c[9] = (~nRowColSel*RowA[9]+nRowColSel*MAin_c[9])
-RDQML_c = (~nRowColSel+~MAin_c[9])
-
-comp 61: SLICE_87 (FSLICE)
-N_137_8 = (N_151*(FS[11]*(~FS[9]*FS[4])))
-UFMSDI_r_xx_mm_1 = (~N_151*(~UFMSDI_ens2_i_a0*CmdUFMSDI)+N_151*~UFMSDI_ens2_i_a0)
-
-comp 62: SLICE_88 (FSLICE)
-RD_1_i = (nCCAS_c+nFWE_c)
-RowA[6].D = MAin_c[6]
-RowA[6].CLK = ~nCRAS_c
-RowA[6].SP = VCC
-RowA[6].LSR = ~Ready_fast
-C1WR_0_a2_0_3 = (~nFWE_c*(MAin_c[3]*MAin_c[2]))
-RowA[7].D = MAin_c[7]
-RowA[7].CLK = ~nCRAS_c
-RowA[7].SP = VCC
-RowA[7].LSR = ~Ready_fast
-
-comp 63: SLICE_89 (FSLICE)
-RA_c[8] = (~nRowColSel*RowA[8]+nRowColSel*MAin_c[8])
-RDQMH_c = (~nRowColSel+MAin_c[9])
-
-comp 64: SLICE_90 (FSLICE)
-RA_c[0] = (~nRowColSel*RowA[0]+nRowColSel*MAin_c[0])
-un1_CMDWR = (~MAin_c[1]*(MAin_c[0]*N_147)+MAin_c[1]*N_147)
-
-comp 65: SLICE_91 (FSLICE)
-RA_c[1] = (~nRowColSel*RowA[1]+nRowColSel*MAin_c[1])
-RA_c[7] = (~nRowColSel*RowA[7]+nRowColSel*MAin_c[7])
-
-comp 66: SLICE_92 (FSLICE)
-RA_c[2] = (~nRowColSel*RowA[2]+nRowColSel*MAin_c[2])
-RA_c[6] = (~nRowColSel*RowA[6]+nRowColSel*MAin_c[6])
-
-comp 67: SLICE_93 (FSLICE)
-RA_c[3] = (~nRowColSel*RowA[3]+nRowColSel*MAin_c[3])
-RA_c[5] = (~nRowColSel*RowA[5]+nRowColSel*MAin_c[5])
-
-comp 68: SLICE_94 (FSLICE)
-RCKEEN_8_u_0_a2_1_out = (S[1]*Ready)
-RA_c[10].D = ~IS[0]
-RA_c[10].CLK = RCLK_c
-RA_c[10].SP = VCC
-RA_c[10].LSR = RA10s_i
-N_159_i = (~N_155*~Ready)
+
+comp 0: SLICE_0 (FSLICE)
+
+comp 1: SLICE_1 (FSLICE)
+
+comp 2: SLICE_2 (FSLICE)
+
+comp 3: SLICE_3 (FSLICE)
+
+comp 4: SLICE_4 (FSLICE)
+
+comp 5: SLICE_5 (FSLICE)
+
+comp 6: SLICE_6 (FSLICE)
+
+comp 7: SLICE_7 (FSLICE)
+
+comp 8: SLICE_8 (FSLICE)
+
+comp 9: SLICE_9 (FSLICE)
+ADSubmitted_r = (~CmdEnable16*((~C1WR_0_a2*ADSubmitted)+CmdEnable17))
+ADSubmitted.D = ADSubmitted_r
+ADSubmitted.CLK = ~PHI2_c
+ADSubmitted.SP = VCC
+ADSubmitted.LSR = GND
+CmdEnable17 = (N_147*(MAin_c[0]*(CmdEnable17_0_a2_4*CmdEnable17_0_a2_3)))
+
+comp 10: SLICE_14 (FSLICE)
+C1Submitted_RNO = (~MAin_c[1]*(CmdEnable16+C1Submitted)+MAin_c[1]*(~N_147*(CmdEnable16+C1Submitted)+N_147*CmdEnable16))
+C1Submitted.D = C1Submitted_RNO
+C1Submitted.CLK = ~PHI2_c
+C1Submitted.SP = VCC
+C1Submitted.LSR = GND
+CmdEnable16 = (N_147*(CmdEnable16_0_a2_5*CmdEnable16_0_a2_4))
+
+comp 11: SLICE_19 (FSLICE)
+N_177_i = (~CO0+S[1])
+CO0.D = N_177_i
+CO0.CLK = RCLK_c
+CO0.SP = VCC
+CO0.LSR = ~RASr2
+Ready_0_sqmuxa_0_a3_2 = (S[1]*(~RASr2*(IS[3]*CO0)))
+
+comp 12: SLICE_20 (FSLICE)
+CmdEnable_s = ((CmdEnable+ADSubmitted)*CmdEnable16)+(((C1Submitted*un1_CMDWR*CmdEnable17)+(CmdEnable*CmdEnable17)+(~un1_CMDWR*CmdEnable))*~CmdEnable16)
+CmdEnable.D = CmdEnable_s
+CmdEnable.CLK = ~PHI2_c
+CmdEnable.SP = VCC
+CmdEnable.LSR = GND
+
+comp 13: SLICE_21 (FSLICE)
+N_21_i = (~N_152*(~N_133*~N_132)+N_152*(~N_133*(~N_132*LEDEN)))
+CmdLEDEN.D = N_21_i
+CmdLEDEN.CLK = ~PHI2_c
+CmdLEDEN.SP = XOR8MEG18
+CmdLEDEN.LSR = GND
+N_152 = (~N_128*(Din_c[5]*~Din_c[3]))
+
+comp 14: SLICE_22 (FSLICE)
+N_460_0 = (CmdSubmitted_1_sqmuxa+CmdSubmitted)
+CmdSubmitted.D = N_460_0
+CmdSubmitted.CLK = ~PHI2_c
+CmdSubmitted.SP = VCC
+CmdSubmitted.LSR = GND
+N_136 = (PHI2r3*(~PHI2r2*(InitReady*CmdSubmitted)))
+
+comp 15: SLICE_26 (FSLICE)
+N_19_i = (~n8MEGEN*(~N_152*~Cmdn8MEGEN_4_u_i_0)+n8MEGEN*~Cmdn8MEGEN_4_u_i_0)
+Cmdn8MEGEN.D = N_19_i
+Cmdn8MEGEN.CLK = ~PHI2_c
+Cmdn8MEGEN.SP = XOR8MEG18
+Cmdn8MEGEN.LSR = GND
+Cmdn8MEGEN_4_u_i_0 = (~N_128*(~N_43*(~Cmdn8MEGEN+CmdEnable16_4)+N_43*CmdEnable16_4)+N_128*~Cmdn8MEGEN)
+
+comp 16: SLICE_29 (FSLICE)
+N_64_i_i = (~N_155*(Ready@~IS[0])+N_155*IS[0])
+IS[0].D = N_64_i_i
+IS[0].CLK = RCLK_c
+IS[0].SP = VCC
+IS[0].LSR = GND
+N_24 = ((~N_160*(~N_155*IS[0])+N_160*~N_155)+nRRAS_5_u_i_0)
+
+comp 17: SLICE_30 (FSLICE)
+N_56_i = (IS[1]@IS[0])
+IS[1].D = N_56_i
+IS[1].CLK = RCLK_c
+IS[1].SP = N_159_i
+IS[1].LSR = GND
+N_60_i_i = (IS[2]@(IS[1]*IS[0]))
+IS[2].D = N_60_i_i
+IS[2].CLK = RCLK_c
+IS[2].SP = N_159_i
+IS[2].LSR = GND
+
+comp 18: SLICE_31 (FSLICE)
+N_61_i_i = (~IS[0]*IS[3]+IS[0]*(~IS[1]*IS[3]+IS[1]*(IS[2]@IS[3])))
+IS[3].D = N_61_i_i
+IS[3].CLK = RCLK_c
+IS[3].SP = N_159_i
+IS[3].LSR = GND
+RA10s_i = ((~IS[3]+(IS[1]+IS[2]))+N_159)
+
+comp 19: SLICE_32 (FSLICE)
+N_461_0 = (InitReady3+InitReady)
+InitReady.D = N_461_0
+InitReady.CLK = RCLK_c
+InitReady.SP = VCC
+InitReady.LSR = GND
+UFMSDI_ens2_i_a0 = (~UFMSDI_ens2_i_a2_4_2*~InitReady+UFMSDI_ens2_i_a2_4_2*(~N_126*~InitReady+N_126*(N_51*~InitReady)))
+
+comp 20: SLICE_33 (FSLICE)
+N_70 = (~UFMSDO_c*(~InitReady+CmdLEDEN)+UFMSDO_c*(InitReady*CmdLEDEN))
+LEDEN.D = N_70
+LEDEN.CLK = RCLK_c
+LEDEN.SP = N_33
+LEDEN.LSR = GND
+LED_c = ((~LEDEN+CBR)+nCRAS_c)
+
+comp 21: SLICE_39 (FSLICE)
+RA11_2 = (~n8MEGEN*(XOR8MEG@Din_c[6])+n8MEGEN*XOR8MEG)
+RA_c[11].D = RA11_2
+RA_c[11].CLK = PHI2_c
+RA_c[11].SP = VCC
+RA_c[11].LSR = ~Ready_fast
+N_171 = (~un1_Din_4*XOR8MEG)
+
+comp 22: SLICE_41 (FSLICE)
+RCKEEN_8 = (~Ready*RCKEEN_8_u_0_0+Ready*(~RCKEEN_8_u_1*RCKEEN_8_u_0_0+RCKEEN_8_u_1*(~CBR+RCKEEN_8_u_0_0)))
+RCKEEN.D = RCKEEN_8
+RCKEEN.CLK = RCLK_c
+RCKEEN.SP = VCC
+RCKEEN.LSR = GND
+RCKEEN_8_u_1 = (~S[1]*(~FWEr_fast+CO0)+S[1]*(FWEr_fast*(~CO0+~CASr2)))
+PHI2r2.D = PHI2r
+PHI2r2.CLK = RCLK_c
+PHI2r2.SP = VCC
+PHI2r2.LSR = GND
+
+comp 23: SLICE_42 (FSLICE)
+RCKE_2 = (~RCKEEN*(RASr3*~RASr2)+RCKEEN*((RASr+RASr2)+RASr3))
+RCKE_c.D = RCKE_2
+RCKE_c.CLK = RCLK_c
+RCKE_c.SP = VCC
+RCKE_c.LSR = GND
+m18_0_a3_3 = (RASr2*(~IS[2]*(~IS[1]*IS[0])))
+PHI2r.D = PHI2_c
+PHI2r.CLK = RCLK_c
+PHI2r.SP = VCC
+PHI2r.LSR = GND
+
+comp 24: SLICE_43 (FSLICE)
+N_462_0 = (~InitReady*Ready+InitReady*(~N_165*(Ready+Ready_0_sqmuxa_0_a3_2)+N_165*Ready))
+Ready.D = N_462_0
+Ready.CLK = RCLK_c
+Ready.SP = VCC
+Ready.LSR = GND
+RCKEEN_8_u_0_0 = (~S_0_i_o2[1]*(~InitReady*(~RASr2*Ready)+InitReady*(~RASr2+~Ready))+S_0_i_o2[1]*(InitReady*~Ready))
+PHI2r3.D = PHI2r2
+PHI2r3.CLK = RCLK_c
+PHI2r3.SP = VCC
+PHI2r3.LSR = GND
+
+comp 25: SLICE_44 (FSLICE)
+N_463_0 = (Ready_0_sqmuxa+Ready_fast)
+Ready_fast.D = N_463_0
+Ready_fast.CLK = RCLK_c
+Ready_fast.SP = VCC
+Ready_fast.LSR = GND
+Ready_0_sqmuxa = (Ready_0_sqmuxa_0_a3_2*(~Ready*(~N_165*InitReady)))
+RASr.D = ~nCRAS_c
+RASr.CLK = RCLK_c
+RASr.SP = VCC
+RASr.LSR = GND
+
+comp 26: SLICE_50 (FSLICE)
+S_0_i_o2[1] = (CO0+S[1])
+S[1].D = S_0_i_o2[1]
+S[1].CLK = RCLK_c
+S[1].SP = VCC
+S[1].LSR = ~RASr2
+nRRAS_0_sqmuxa = (~CO0*(~S[1]*Ready))
+
+comp 27: SLICE_51 (FSLICE)
+UFMCLK_RNO = (~UFMCLK_r_i_m4_xx_mm_1*(~UFMCLK_c*(~nUFMCS15*N_139_i)+UFMCLK_c*~nUFMCS15)+UFMCLK_r_i_m4_xx_mm_1*(UFMCLK_c*(~nUFMCS15*~N_139_i)))
+UFMCLK_c.D = UFMCLK_RNO
+UFMCLK_c.CLK = RCLK_c
+UFMCLK_c.SP = VCC
+UFMCLK_c.LSR = GND
+UFMCLK_r_i_m4_xx_mm_1 = (~N_129*((~CmdUFMCLK+~InitReady)+UFMCLK_r_i_a2_2_2)+N_129*((~CmdUFMCLK*InitReady)+UFMCLK_r_i_a2_2_2))
+RASr2.D = RASr
+RASr2.CLK = RCLK_c
+RASr2.SP = VCC
+RASr2.LSR = GND
+
+comp 28: SLICE_52 (FSLICE)
+UFMSDI_RNO = (~UFMSDI_r_xx_mm_1*(UFMSDI_c*(~nUFMCS15*~N_139_i))+UFMSDI_r_xx_mm_1*(~UFMSDI_c*(~nUFMCS15*N_139_i)+UFMSDI_c*~nUFMCS15))
+UFMSDI_c.D = UFMSDI_RNO
+UFMSDI_c.CLK = RCLK_c
+UFMSDI_c.SP = VCC
+UFMSDI_c.LSR = GND
+N_139_i = (~PHI2r3*~InitReady+PHI2r3*(~PHI2r2*(~InitReady+CmdSubmitted)+PHI2r2*~InitReady))
+RASr3.D = RASr2
+RASr3.CLK = RCLK_c
+RASr3.SP = VCC
+RASr3.LSR = GND
+
+comp 29: SLICE_55 (FSLICE)
+RA_c[4] = (~nRowColSel*RowA[4]+nRowColSel*MAin_c[4])
+WRD[4].D = Din_c[4]
+WRD[4].CLK = ~nCCAS_c
+WRD[4].SP = VCC
+WRD[4].LSR = GND
+WRD[5].D = Din_c[5]
+WRD[5].CLK = ~nCCAS_c
+WRD[5].SP = VCC
+WRD[5].LSR = GND
+
+comp 30: SLICE_56 (FSLICE)
+N_126 = (~FS[9]*FS[7]+FS[9]*(~FS[7]*FS[5]))
+WRD[6].D = Din_c[6]
+WRD[6].CLK = ~nCCAS_c
+WRD[6].SP = VCC
+WRD[6].LSR = GND
+C1WR_0_a2_0_11 = (Bank[7]*(Bank[6]*(Bank[5]*~Bank[2])))
+WRD[7].D = Din_c[7]
+WRD[7].CLK = ~nCCAS_c
+WRD[7].SP = VCC
+WRD[7].LSR = GND
+
+comp 31: SLICE_57 (FSLICE)
+XOR8MEG_3 = (~XOR8MEG_3_u_0_a3_2*N_171+XOR8MEG_3_u_0_a3_2*((~LEDEN+~Din_c[1])+N_171))
+XOR8MEG.D = XOR8MEG_3
+XOR8MEG.CLK = ~PHI2_c
+XOR8MEG.SP = XOR8MEG18
+XOR8MEG.LSR = GND
+XOR8MEG_3_u_0_a3_2 = (un1_Din_4*(~Din_c[3]*(Din_c[2]*Din_c[0])))
+
+comp 32: SLICE_58 (FSLICE)
+N_69 = (~UFMSDO_c*(~InitReady+Cmdn8MEGEN)+UFMSDO_c*(InitReady*Cmdn8MEGEN))
+n8MEGEN.D = N_69
+n8MEGEN.CLK = RCLK_c
+n8MEGEN.SP = N_31
+n8MEGEN.LSR = GND
+N_151 = (~N_51*(~InitReady*~FS[8]))
+
+comp 33: SLICE_59 (FSLICE)
+N_37_i = (~g0_1*(~S[1]*(~nRCAS_0_sqmuxa_1*N_41)+S[1]*~nRCAS_0_sqmuxa_1)+g0_1*(~nRCAS_0_sqmuxa_1*N_41))
+nRCAS_c.D = N_37_i
+nRCAS_c.CLK = RCLK_c
+nRCAS_c.SP = VCC
+nRCAS_c.LSR = GND
+N_41 = (~S[1]*((~N_160+N_155)+Ready)+S[1]*(~Ready*(~N_160+N_155)))
+
+comp 34: SLICE_60 (FSLICE)
+N_28_i = (~RCKEEN_8_u_0_a2_1_out*~N_24+RCKEEN_8_u_0_a2_1_out*(~N_28_i_1*(~N_24*CBR)+N_28_i_1*~N_24))
+nRCS_c.D = N_28_i
+nRCS_c.CLK = RCLK_c
+nRCS_c.SP = VCC
+nRCS_c.LSR = GND
+N_28_i_1 = (~CASr2*(FWEr_fast+CO0)+CASr2*(~CASr3*(CO0@FWEr_fast)+CASr3*(FWEr_fast+CO0)))
+
+comp 35: SLICE_61 (FSLICE)
+N_24_i = (~IS[0]*(~N_155*(~N_160*~nRRAS_5_u_i_0)+N_155*~nRRAS_5_u_i_0)+IS[0]*(N_155*~nRRAS_5_u_i_0))
+nRRAS_c.D = N_24_i
+nRRAS_c.CLK = RCLK_c
+nRRAS_c.SP = VCC
+nRRAS_c.LSR = GND
+nRRAS_5_u_i_0 = (Ready*(~RCKE_c*(RASr2*~S_0_i_o2[1])+RCKE_c*~S_0_i_o2[1]))
+
+comp 36: SLICE_62 (FSLICE)
+N_39_i = (~m18_0_a2_1*((~G_17_1+~FWEr)+nRCAS_0_sqmuxa_1)+m18_0_a2_1*((G_17_1*~FWEr)+nRCAS_0_sqmuxa_1))
+nRWE_c.D = N_39_i
+nRWE_c.CLK = RCLK_c
+nRWE_c.SP = VCC
+nRWE_c.LSR = GND
+nRCAS_0_sqmuxa_1 = (Ready*(RASr2*(~S_0_i_o2[1]*CBR_fast)))
+
+comp 37: SLICE_63 (FSLICE)
+nRowColSel_0_0 = (~S[1]*(~Ready*N_179+Ready*(CO0+N_179))+S[1]*(~Ready*N_179+Ready*(~CO0+N_179)))
+nRowColSel.D = nRowColSel_0_0
+nRowColSel.CLK = RCLK_c
+nRowColSel.SP = VCC
+nRowColSel.LSR = nRRAS_0_sqmuxa
+N_179 = (Ready*(FWEr*(~CBR*~CASr3)))
+
+comp 38: SLICE_64 (FSLICE)
+nUFMCS_s_0_N_5_i = (~nUFMCS_s_0_N_5_i_N_2L1*((N_139_i+nUFMCS15)+nUFMCS_c)+nUFMCS_s_0_N_5_i_N_2L1*(~nUFMCS_c*nUFMCS15+nUFMCS_c*(~N_139_i+nUFMCS15)))
+nUFMCS_c.D = nUFMCS_s_0_N_5_i
+nUFMCS_c.CLK = RCLK_c
+nUFMCS_c.SP = VCC
+nUFMCS_c.LSR = GND
+nUFMCS15 = (~N_51*(~InitReady*(~FS[11]*~FS[10])))
+
+comp 39: nRWE_RNO_1/SLICE_65 (FSLICE)
+m18_0_a2_1 = ((~RASr2*RCKE_c*~CO0*~S[1])*Ready)+((InitReady*m18_0_a3_3*~CO0*~S[1])*~Ready)
+
+comp 40: SLICE_66 (FSLICE)
+UFMCLK_r_i_a2_2_2 = (N_95_5*(N_95_3*(~InitReady*FS[16])))
+RowA[0].D = MAin_c[0]
+RowA[0].CLK = ~nCRAS_c
+RowA[0].SP = VCC
+RowA[0].LSR = ~Ready_fast
+nUFMCS_s_0_N_5_i_N_2L1 = (~UFMCLK_r_i_a2_2_2*(~InitReady+CmdUFMCS))
+RowA[1].D = MAin_c[1]
+RowA[1].CLK = ~nCRAS_c
+RowA[1].SP = VCC
+RowA[1].LSR = ~Ready_fast
+
+comp 41: SLICE_67 (FSLICE)
+XOR8MEG18 = (N_147*(~MAin_c[1]*(MAin_c[0]*CmdEnable)))
+RowA[4].D = MAin_c[4]
+RowA[4].CLK = ~nCRAS_c
+RowA[4].SP = VCC
+RowA[4].LSR = ~Ready_fast
+CmdUFMCLK_1_sqmuxa = (~Din_c[3]*(Din_c[5]*(~N_128*XOR8MEG18)))
+RowA[5].D = MAin_c[5]
+RowA[5].CLK = ~nCRAS_c
+RowA[5].SP = VCC
+RowA[5].LSR = ~Ready_fast
+
+comp 42: SLICE_68 (FSLICE)
+N_31 = (~un1_FS_14_i_a2_0_1*N_136+un1_FS_14_i_a2_0_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
+un1_FS_14_i_a2_0_1 = (~FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
+
+comp 43: SLICE_69 (FSLICE)
+N_33 = (~un1_FS_13_i_a2_1*N_136+un1_FS_13_i_a2_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
+un1_FS_13_i_a2_1 = (FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
+
+comp 44: SLICE_70 (FSLICE)
+C1WR_0_a2 = (N_147*MAin_c[1])
+Bank[0].D = Din_c[0]
+Bank[0].CLK = PHI2_c
+Bank[0].SP = VCC
+Bank[0].LSR = GND
+N_147 = (C1WR_0_a2_0_11*(C1WR_0_a2_0_10*(Bank[1]*Bank[0])))
+Bank[1].D = Din_c[1]
+Bank[1].CLK = PHI2_c
+Bank[1].SP = VCC
+Bank[1].LSR = GND
+
+comp 45: SLICE_71 (FSLICE)
+C1WR_0_a2_0_10 = (C1WR_0_a2_0_4*(C1WR_0_a2_0_3*(Bank[4]*Bank[3])))
+Bank[2].D = Din_c[2]
+Bank[2].CLK = PHI2_c
+Bank[2].SP = VCC
+Bank[2].LSR = GND
+C1WR_0_a2_0_4 = (MAin_c[7]*(MAin_c[6]*(MAin_c[5]*MAin_c[4])))
+Bank[3].D = Din_c[3]
+Bank[3].CLK = PHI2_c
+Bank[3].SP = VCC
+Bank[3].LSR = GND
+
+comp 46: SLICE_72 (FSLICE)
+N_129 = (~N_51*(FS[11]*FS[4])+N_51*FS[1])
+RowA[2].D = MAin_c[2]
+RowA[2].CLK = ~nCRAS_c
+RowA[2].SP = VCC
+RowA[2].LSR = ~Ready_fast
+N_51 = ((FS[12]+FS[16])+UFMSDI_ens2_i_o2_0_3)
+RowA[3].D = MAin_c[3]
+RowA[3].CLK = ~nCRAS_c
+RowA[3].SP = VCC
+RowA[3].LSR = ~Ready_fast
+
+comp 47: SLICE_73 (FSLICE)
+N_159 = (N_155+Ready)
+CmdUFMCLK.D = Din_c[1]
+CmdUFMCLK.CLK = ~PHI2_c
+CmdUFMCLK.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMCLK.LSR = GND
+N_155 = (((~InitReady+~RASr2)+S[1])+CO0)
+CmdUFMCS.D = Din_c[2]
+CmdUFMCS.CLK = ~PHI2_c
+CmdUFMCS.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMCS.LSR = GND
+
+comp 48: SLICE_74 (FSLICE)
+InitReady3 = (N_95_5*(N_95_3*(FS[16]*FS[10])))
+CmdUFMSDI.D = Din_c[0]
+CmdUFMSDI.CLK = ~PHI2_c
+CmdUFMSDI.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMSDI.LSR = GND
+N_95_3 = (FS[14]*FS[11])
+
+comp 49: SLICE_75 (FSLICE)
+N_133 = (~N_128*(~Din_c[5]*~Din_c[1]))
+CASr.D = ~nCCAS_c
+CASr.CLK = RCLK_c
+CASr.SP = VCC
+CASr.LSR = GND
+N_128 = ((~Din_c[4]+Din_c[6])+Din_c[7])
+CASr2.D = CASr
+CASr2.CLK = RCLK_c
+CASr2.SP = VCC
+CASr2.LSR = GND
+
+comp 50: SLICE_76 (FSLICE)
+CmdEnable16_0_a2_4 = (~MAin_c[0]*(~Din_c[3]*(~Din_c[1]*CmdEnable16_4)))
+Bank[4].D = Din_c[4]
+Bank[4].CLK = PHI2_c
+Bank[4].SP = VCC
+Bank[4].LSR = GND
+CmdEnable16_4 = (~Din_c[5]*Din_c[0])
+Bank[5].D = Din_c[5]
+Bank[5].CLK = PHI2_c
+Bank[5].SP = VCC
+Bank[5].LSR = GND
+
+comp 51: SLICE_77 (FSLICE)
+CmdEnable16_0_a2_5 = (MAin_c[1]*(Din_c[6]*(~Din_c[2]*CmdEnable16_1)))
+Bank[6].D = Din_c[6]
+Bank[6].CLK = PHI2_c
+Bank[6].SP = VCC
+Bank[6].LSR = GND
+CmdEnable16_1 = (Din_c[7]*~Din_c[4])
+Bank[7].D = Din_c[7]
+Bank[7].CLK = PHI2_c
+Bank[7].SP = VCC
+Bank[7].LSR = GND
+
+comp 52: SLICE_78 (FSLICE)
+CmdEnable17_0_a2_4 = (~N_43*(MAin_c[1]*(~Din_c[6]*Din_c[2])))
+CBR.D = ~nCCAS_c
+CBR.CLK = ~nCRAS_c
+CBR.SP = VCC
+CBR.LSR = GND
+N_43 = (~Din_c[5]+~Din_c[3])
+CBR_fast.D = ~nCCAS_c
+CBR_fast.CLK = ~nCRAS_c
+CBR_fast.SP = VCC
+CBR_fast.LSR = GND
+
+comp 53: SLICE_79 (FSLICE)
+G_17_1 = (m6_0_a2_2*(S[1]*(CO0*~CBR)))
+WRD[0].D = Din_c[0]
+WRD[0].CLK = ~nCCAS_c
+WRD[0].SP = VCC
+WRD[0].LSR = GND
+m6_0_a2_2 = (Ready*(~CASr3*CASr2))
+WRD[1].D = Din_c[1]
+WRD[1].CLK = ~nCCAS_c
+WRD[1].SP = VCC
+WRD[1].LSR = GND
+
+comp 54: SLICE_80 (FSLICE)
+g0_1 = (~g4_0_0_0*(~FWEr*(~CO0*~CBR_fast))+g4_0_0_0*(~FWEr*(~CO0*~CBR_fast)+FWEr*(CO0*~CBR_fast)))
+RowA[8].D = MAin_c[8]
+RowA[8].CLK = ~nCRAS_c
+RowA[8].SP = VCC
+RowA[8].LSR = ~Ready_fast
+g4_0_0_0 = (~CASr3*CASr2)
+RowA[9].D = MAin_c[9]
+RowA[9].CLK = ~nCRAS_c
+RowA[9].SP = VCC
+RowA[9].LSR = ~Ready_fast
+
+comp 55: SLICE_81 (FSLICE)
+N_95_5 = (FS[17]*(FS[15]*(FS[13]*FS[12])))
+FWEr.D = ~nFWE_c
+FWEr.CLK = ~nCRAS_c
+FWEr.SP = VCC
+FWEr.LSR = GND
+UFMSDI_ens2_i_o2_0_3 = (((FS[13]+FS[14])+FS[15])+FS[17])
+FWEr_fast.D = ~nFWE_c
+FWEr_fast.CLK = ~nCRAS_c
+FWEr_fast.SP = VCC
+FWEr_fast.LSR = GND
+
+comp 56: SLICE_82 (FSLICE)
+CmdSubmitted_1_sqmuxa = (~Din_c[3]*(~N_128*XOR8MEG18)+Din_c[3]*(~Din_c[5]*(~N_128*XOR8MEG18)))
+CASr3.D = CASr2
+CASr3.CLK = RCLK_c
+CASr3.SP = VCC
+CASr3.LSR = GND
+N_132 = (~Din_c[3]*(~CmdLEDEN*N_128)+Din_c[3]*(~Din_c[5]*(~CmdLEDEN*N_128)+Din_c[5]*~CmdLEDEN))
+
+comp 57: SLICE_83 (FSLICE)
+N_165 = (~IS[2]+(~IS[1]+~IS[0]))
+RBA_c[0].D = CROW_c[0]
+RBA_c[0].CLK = ~nCRAS_c
+RBA_c[0].SP = VCC
+RBA_c[0].LSR = ~Ready_fast
+N_160 = ((IS[1]+IS[2])+IS[3])
+RBA_c[1].D = CROW_c[1]
+RBA_c[1].CLK = ~nCRAS_c
+RBA_c[1].SP = VCC
+RBA_c[1].LSR = ~Ready_fast
+
+comp 58: SLICE_84 (FSLICE)
+N_137_6 = (FS[10]*(~FS[7]*(~FS[6]*~FS[1])))
+UFMSDI_ens2_i_a2_4_2 = (FS[11]*(~FS[10]*(~FS[8]*FS[6])))
+
+comp 59: SLICE_85 (FSLICE)
+un1_Din_4 = (~Din_c[7]*(~Din_c[6]*(~Din_c[5]*~Din_c[4])))
+WRD[2].D = Din_c[2]
+WRD[2].CLK = ~nCCAS_c
+WRD[2].SP = VCC
+WRD[2].LSR = GND
+CmdEnable17_0_a2_3 = (~Din_c[4]*(Din_c[7]*(Din_c[0]*~Din_c[1])))
+WRD[3].D = Din_c[3]
+WRD[3].CLK = ~nCCAS_c
+WRD[3].SP = VCC
+WRD[3].LSR = GND
+
+comp 60: SLICE_86 (FSLICE)
+RA_c[9] = (~nRowColSel*RowA[9]+nRowColSel*MAin_c[9])
+RDQML_c = (~nRowColSel+~MAin_c[9])
+
+comp 61: SLICE_87 (FSLICE)
+N_137_8 = (N_151*(FS[11]*(~FS[9]*FS[4])))
+UFMSDI_r_xx_mm_1 = (~N_151*(~UFMSDI_ens2_i_a0*CmdUFMSDI)+N_151*~UFMSDI_ens2_i_a0)
+
+comp 62: SLICE_88 (FSLICE)
+RD_1_i = (nCCAS_c+nFWE_c)
+RowA[6].D = MAin_c[6]
+RowA[6].CLK = ~nCRAS_c
+RowA[6].SP = VCC
+RowA[6].LSR = ~Ready_fast
+C1WR_0_a2_0_3 = (~nFWE_c*(MAin_c[3]*MAin_c[2]))
+RowA[7].D = MAin_c[7]
+RowA[7].CLK = ~nCRAS_c
+RowA[7].SP = VCC
+RowA[7].LSR = ~Ready_fast
+
+comp 63: SLICE_89 (FSLICE)
+RA_c[8] = (~nRowColSel*RowA[8]+nRowColSel*MAin_c[8])
+RDQMH_c = (~nRowColSel+MAin_c[9])
+
+comp 64: SLICE_90 (FSLICE)
+RA_c[0] = (~nRowColSel*RowA[0]+nRowColSel*MAin_c[0])
+un1_CMDWR = (~MAin_c[1]*(MAin_c[0]*N_147)+MAin_c[1]*N_147)
+
+comp 65: SLICE_91 (FSLICE)
+RA_c[1] = (~nRowColSel*RowA[1]+nRowColSel*MAin_c[1])
+RA_c[7] = (~nRowColSel*RowA[7]+nRowColSel*MAin_c[7])
+
+comp 66: SLICE_92 (FSLICE)
+RA_c[2] = (~nRowColSel*RowA[2]+nRowColSel*MAin_c[2])
+RA_c[6] = (~nRowColSel*RowA[6]+nRowColSel*MAin_c[6])
+
+comp 67: SLICE_93 (FSLICE)
+RA_c[3] = (~nRowColSel*RowA[3]+nRowColSel*MAin_c[3])
+RA_c[5] = (~nRowColSel*RowA[5]+nRowColSel*MAin_c[5])
+
+comp 68: SLICE_94 (FSLICE)
+RCKEEN_8_u_0_a2_1_out = (S[1]*Ready)
+RA_c[10].D = ~IS[0]
+RA_c[10].CLK = RCLK_c
+RA_c[10].SP = VCC
+RA_c[10].LSR = RA10s_i
+N_159_i = (~N_155*~Ready)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd
index 37e2fc98df54ea11c33c83035af5fbdddab27f76..3448f965bb4d8f65bc25e76b275326e77843ac40 100644
GIT binary patch
delta 40
wcmcaUiSzm-&IuyS4^v)l6n`YaRv+!BrLRAkQPQE=Ub5X@l5xAeB$I>z06`TEGXMYp

delta 40
wcmcaUiSzm-&IuyScY2>~6n`YaR_OeIU0;7PqohN#y=1$+B;$5_NhS#c07~5rod5s;

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd
index 2e14e5f1e23090931395f355efceb9ebaff8295e..22385bb173f6cfb4a0301acfa8e6ab2b0693ef51 100644
GIT binary patch
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diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t
index 16daf53..1df1245 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t
@@ -1,9 +1,9 @@
--w
--l 5
--i 6
--n 1
--t 1
--s 1
--c 0
--e 0
--exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
index f0915dc..da08f0e 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
@@ -1,353 +1,353 @@
-PAD Specification File
-***************************
-
-PART TYPE:        LCMXO640C
-Performance Grade:      3
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.17
-
-Wed Aug 16 04:50:52 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+-------+----------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                       |
-+-----------+----------+---------------+-------+----------------------------------+
-| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:KEEPER            |
-| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:KEEPER            |
-| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:KEEPER            |
-| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:KEEPER            |
-| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:KEEPER            |
-| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:KEEPER            |
-| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:KEEPER            |
-| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:KEEPER            |
-| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:KEEPER            |
-| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:KEEPER            |
-| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:4mA SLEW:FAST              |
-| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:4mA SLEW:FAST              |
-| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:4mA SLEW:FAST              |
-| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:4mA SLEW:FAST              |
-| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:4mA SLEW:FAST              |
-| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:4mA SLEW:FAST              |
-| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:4mA SLEW:FAST              |
-| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:4mA SLEW:FAST              |
-| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:14mA SLEW:SLOW             |
-| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:KEEPER            |
-| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:KEEPER            |
-| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:KEEPER            |
-| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:KEEPER            |
-| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:KEEPER            |
-| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:KEEPER            |
-| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:KEEPER            |
-| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:KEEPER            |
-| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:KEEPER            |
-| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:KEEPER            |
-| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:DOWN              |
-| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
-| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
-| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
-| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
-| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
-| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
-| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
-| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
-| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
-| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
-| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
-| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
-| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
-| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:KEEPER            |
-| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
-| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
-| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
-| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
-| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
-| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP                |
-| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP                |
-| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:KEEPER            |
-| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
-| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
-| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
-| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
-| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
-+-----------+----------+---------------+-------+----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    |       |
-| 3    | 3.3V  |
-+------+-------+
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+---------------------+------------+---------------+-------+---------------+
-| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
-+----------+---------------------+------------+---------------+-------+---------------+
-| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
-| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
-| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
-| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
-| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
-| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
-| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
-| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
-| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
-| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
-| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
-| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
-| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
-| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
-| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
-| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
-| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
-| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
-| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
-| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
-| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
-| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
-| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
-| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
-| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
-| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
-| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
-| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
-| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
-| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
-| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
-| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
-| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
-| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
-| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
-| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
-| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
-| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
-| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
-| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
-| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
-| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
-| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
-| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
-| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
-| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
-| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
-| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
-| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
-| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
-| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
-| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
-| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
-| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
-| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
-| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
-| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
-| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
-| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
-| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
-| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
-| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
-| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
-| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
-| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
-| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
-| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
-| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
-| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
-| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
-| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
-| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
-| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
-| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
-| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
-| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
-| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
-| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
-| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
-| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
-| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
-| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
-| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
-| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
-| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
-| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
-| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
-| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
-| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
-| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
-| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
-| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
-| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
-| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
-| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
-| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
-| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
-| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
-| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
-| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
-| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
-| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
-| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
-| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
-| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
-| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
-| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
-| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
-| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
-| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
-| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
-| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
-| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
-| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
-| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
-| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
-| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
-| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
-| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
-| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
-| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
-| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
-| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
-| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
-| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
-| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
-| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
-| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
-| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
-| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
-| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
-| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
-| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
-| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
-| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
-| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
-| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
-| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
-| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
-| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
-| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
-| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
-| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
-| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
-| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
-| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
-| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
-| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
-| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
-| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
-| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
-| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
-| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
-| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
-| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
-| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
-| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
-| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
-| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
-| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
-| TCK/2    |                     |            |               | TCK   | TCK           |
-| TDI/2    |                     |            |               | TDI   | TDID0         |
-| TDO/2    |                     |            |               | TDO   | TDO           |
-| TMS/2    |                     |            |               | TMS   | TMS           |
-+----------+---------------------+------------+---------------+-------+---------------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "32";
-LOCATE  COMP  "CROW[1]"  SITE  "34";
-LOCATE  COMP  "Din[0]"  SITE  "21";
-LOCATE  COMP  "Din[1]"  SITE  "15";
-LOCATE  COMP  "Din[2]"  SITE  "14";
-LOCATE  COMP  "Din[3]"  SITE  "16";
-LOCATE  COMP  "Din[4]"  SITE  "18";
-LOCATE  COMP  "Din[5]"  SITE  "17";
-LOCATE  COMP  "Din[6]"  SITE  "20";
-LOCATE  COMP  "Din[7]"  SITE  "19";
-LOCATE  COMP  "Dout[0]"  SITE  "1";
-LOCATE  COMP  "Dout[1]"  SITE  "7";
-LOCATE  COMP  "Dout[2]"  SITE  "8";
-LOCATE  COMP  "Dout[3]"  SITE  "6";
-LOCATE  COMP  "Dout[4]"  SITE  "4";
-LOCATE  COMP  "Dout[5]"  SITE  "5";
-LOCATE  COMP  "Dout[6]"  SITE  "2";
-LOCATE  COMP  "Dout[7]"  SITE  "3";
-LOCATE  COMP  "LED"  SITE  "57";
-LOCATE  COMP  "MAin[0]"  SITE  "23";
-LOCATE  COMP  "MAin[1]"  SITE  "38";
-LOCATE  COMP  "MAin[2]"  SITE  "37";
-LOCATE  COMP  "MAin[3]"  SITE  "47";
-LOCATE  COMP  "MAin[4]"  SITE  "46";
-LOCATE  COMP  "MAin[5]"  SITE  "45";
-LOCATE  COMP  "MAin[6]"  SITE  "49";
-LOCATE  COMP  "MAin[7]"  SITE  "44";
-LOCATE  COMP  "MAin[8]"  SITE  "50";
-LOCATE  COMP  "MAin[9]"  SITE  "51";
-LOCATE  COMP  "PHI2"  SITE  "39";
-LOCATE  COMP  "RA[0]"  SITE  "98";
-LOCATE  COMP  "RA[10]"  SITE  "87";
-LOCATE  COMP  "RA[11]"  SITE  "79";
-LOCATE  COMP  "RA[1]"  SITE  "89";
-LOCATE  COMP  "RA[2]"  SITE  "94";
-LOCATE  COMP  "RA[3]"  SITE  "97";
-LOCATE  COMP  "RA[4]"  SITE  "99";
-LOCATE  COMP  "RA[5]"  SITE  "95";
-LOCATE  COMP  "RA[6]"  SITE  "91";
-LOCATE  COMP  "RA[7]"  SITE  "100";
-LOCATE  COMP  "RA[8]"  SITE  "96";
-LOCATE  COMP  "RA[9]"  SITE  "85";
-LOCATE  COMP  "RBA[0]"  SITE  "63";
-LOCATE  COMP  "RBA[1]"  SITE  "83";
-LOCATE  COMP  "RCKE"  SITE  "82";
-LOCATE  COMP  "RCLK"  SITE  "86";
-LOCATE  COMP  "RDQMH"  SITE  "76";
-LOCATE  COMP  "RDQML"  SITE  "61";
-LOCATE  COMP  "RD[0]"  SITE  "64";
-LOCATE  COMP  "RD[1]"  SITE  "65";
-LOCATE  COMP  "RD[2]"  SITE  "66";
-LOCATE  COMP  "RD[3]"  SITE  "67";
-LOCATE  COMP  "RD[4]"  SITE  "68";
-LOCATE  COMP  "RD[5]"  SITE  "69";
-LOCATE  COMP  "RD[6]"  SITE  "70";
-LOCATE  COMP  "RD[7]"  SITE  "71";
-LOCATE  COMP  "UFMCLK"  SITE  "58";
-LOCATE  COMP  "UFMSDI"  SITE  "56";
-LOCATE  COMP  "UFMSDO"  SITE  "55";
-LOCATE  COMP  "nCCAS"  SITE  "27";
-LOCATE  COMP  "nCRAS"  SITE  "43";
-LOCATE  COMP  "nFWE"  SITE  "22";
-LOCATE  COMP  "nRCAS"  SITE  "78";
-LOCATE  COMP  "nRCS"  SITE  "77";
-LOCATE  COMP  "nRRAS"  SITE  "73";
-LOCATE  COMP  "nRWE"  SITE  "72";
-LOCATE  COMP  "nUFMCS"  SITE  "53";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:52 2023
-
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Sat Aug 19 20:57:21 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                       |
++-----------+----------+---------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:KEEPER            |
+| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:KEEPER            |
+| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:KEEPER            |
+| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:KEEPER            |
+| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:KEEPER            |
+| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:KEEPER            |
+| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:KEEPER            |
+| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:KEEPER            |
+| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:KEEPER            |
+| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:KEEPER            |
+| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:4mA SLEW:FAST              |
+| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:4mA SLEW:FAST              |
+| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:4mA SLEW:FAST              |
+| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:4mA SLEW:FAST              |
+| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:4mA SLEW:FAST              |
+| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:4mA SLEW:FAST              |
+| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:4mA SLEW:FAST              |
+| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:4mA SLEW:FAST              |
+| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:14mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:KEEPER            |
+| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:KEEPER            |
+| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:KEEPER            |
+| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:KEEPER            |
+| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:KEEPER            |
+| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:KEEPER            |
+| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:KEEPER            |
+| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:KEEPER            |
+| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:KEEPER            |
+| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:KEEPER            |
+| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:DOWN              |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:KEEPER            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP                |
+| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP                |
+| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:KEEPER            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+---------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
++----------+---------------------+------------+---------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
+| TCK/2    |                     |            |               | TCK   | TCK           |
+| TDI/2    |                     |            |               | TDI   | TDID0         |
+| TDO/2    |                     |            |               | TDO   | TDO           |
+| TMS/2    |                     |            |               | TMS   | TMS           |
++----------+---------------------+------------+---------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:57:21 2023
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
index 2b7c7ac..dd2c27b 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
@@ -1,241 +1,241 @@
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:48 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
-RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
-RAM2GS_LCMXO640C_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            7.336        0            0.273        0            04           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 4 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Wed Aug 16 04:50:48 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)      67/159          42% used
-                     67/74           90% bonded
-   SLICE             69/320          21% used
-
-
-
-Number of Signals: 251
-Number of Connections: 633
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 32)
-    PHI2_c (driver: PHI2, clk load #: 14)
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-.........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-.............
-Placer score = 956294.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  953137
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 1 out of 160 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 4 (50%)
-  SECONDARY: 1 out of 4 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 out of 159 (42.1%) PIO sites used.
-   67 out of 74 (90.5%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
-| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-| 2        | 13 / 14 ( 92%) | -          | -          | -          |
-| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-0 connections routed; 633 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Completed router resource preassignment. Real time: 4 secs 
-
-Start NBR router at 04:50:52 08/16/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 04:50:52 08/16/23
-
-Start NBR section for initial routing at 04:50:52 08/16/23
-Level 1, iteration 1
-1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.325ns/0.000ns; real time: 4 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.532ns/0.000ns; real time: 4 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.449ns/0.000ns; real time: 4 secs 
-Level 4, iteration 1
-8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:52 08/16/23
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 2
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:52 08/16/23
-
-Start NBR section for re-routing at 04:50:52 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for post-routing at 04:50:52 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 7.336ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 7.336
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:57:16 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            7.336        0            0.273        0            06           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Sat Aug 19 20:57:16 2023
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             69/320          21% used
+
+
+
+Number of Signals: 251
+Number of Connections: 633
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 32)
+    PHI2_c (driver: PHI2, clk load #: 14)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.............
+Placer score = 956294.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  953137
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 160 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 633 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Completed router resource preassignment. Real time: 6 secs 
+
+Start NBR router at 20:57:22 08/19/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 20:57:22 08/19/23
+
+Start NBR section for initial routing at 20:57:22 08/19/23
+Level 1, iteration 1
+1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.325ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.532ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.449ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 20:57:22 08/19/23
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:57:22 08/19/23
+
+Start NBR section for re-routing at 20:57:22 08/19/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 20:57:22 08/19/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 7.336ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  633 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 7.336
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.273
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
index ab940d3..181b2ca 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
@@ -1,79 +1,79 @@
-SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 04:50:46 2023
-
-SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "RD[7]" SITE "71" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-FREQUENCY PORT "PHI2" 2.900000 MHz ;
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-FREQUENCY PORT "RCLK" 62.500000 MHz ;
-SCHEMATIC END ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-COMMERCIAL ;
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 20:57:14 2023
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+FREQUENCY PORT "PHI2" 2.900000 MHz ;
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+FREQUENCY PORT "RCLK" 62.500000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srd
index 6d23493b35d178a92c4cddd2c4d81a993875ac86..7cc0fa03803065ab09751908d1b0c54998cada29 100644
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diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr
index cabd4ec..4f25284 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr
@@ -1,966 +1,968 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:37 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:39 2023
-
-###########################################################]
-# Wed Aug 16 04:50:39 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:41 2023
-
-###########################################################]
-# Wed Aug 16 04:50:41 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:02s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:02s		    -2.99ns		 127 /        92
-   9		0h:00m:02s		    -3.09ns		 127 /        92
-  10		0h:00m:02s		    -3.19ns		 127 /        92
-  11		0h:00m:02s		    -3.19ns		 127 /        92
-  12		0h:00m:02s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:45 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo640c-3
-
-Register bits: 92 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Wed Aug 16 04:50:45 2023
-
-###########################################################]
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 20:57:05 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:06 2023
+
+###########################################################]
+Premap Report
+
+# Sat Aug 19 20:57:07 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:57:08 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Sat Aug 19 20:57:08 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:57:11 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo640c-3
+
+Register bits: 92 of 640 (14%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:57:12 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr.db b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr.db
index 1f2d69f618bce437a777bacb9d96d0abb3a9cb5b..1e4545ad9e7d38619b9a2f06ae6b6032f37d682b 100644
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diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
index 7499213..4ca5dd2 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
@@ -1,413 +1,413 @@
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            129 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[2]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:               9.621ns  (25.1% logic, 74.9% route), 6 logic levels.
-
- Constraint Details:
-
-      9.621ns physical path delay SLICE_71 to SLICE_22 meets
-    172.414ns delay constraint less
-      0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns
-
- Physical Path Details:
-
-      Data path SLICE_71 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_71.CLK to    SLICE_71.Q0 SLICE_71 (from PHI2_c)
-ROUTE         1   e 1.441    SLICE_71.Q0 to    SLICE_56.A1 Bank[2]
-CTOF_DEL    ---     0.371    SLICE_56.A1 to    SLICE_56.F1 SLICE_56
-ROUTE         1   e 1.441    SLICE_56.F1 to    SLICE_70.D1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371    SLICE_70.D1 to    SLICE_70.F1 SLICE_70
-ROUTE         6   e 1.441    SLICE_70.F1 to    SLICE_67.D0 N_147
-CTOF_DEL    ---     0.371    SLICE_67.D0 to    SLICE_67.F0 SLICE_67
-ROUTE         5   e 1.441    SLICE_67.F0 to    SLICE_82.A0 XOR8MEG18
-CTOF_DEL    ---     0.371    SLICE_82.A0 to    SLICE_82.F0 SLICE_82
-ROUTE         1   e 1.441    SLICE_82.F0 to    SLICE_22.A0 CmdSubmitted_1_sqmuxa
-CTOF_DEL    ---     0.371    SLICE_22.A0 to    SLICE_22.F0 SLICE_22
-ROUTE         1   e 0.001    SLICE_22.F0 to   SLICE_22.DI0 N_460_0 (to PHI2_c)
-                  --------
-                    9.621   (25.1% logic, 74.9% route), 6 logic levels.
-
-Report:   51.046MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 342.328ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:  400.000MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 342.328ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:  400.000MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            388 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 4.695ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
-
- Constraint Details:
-
-     11.061ns physical path delay SLICE_1 to SLICE_33 meets
-     16.000ns delay constraint less
-      0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q1 SLICE_1 (from RCLK_c)
-ROUTE         3   e 1.441     SLICE_1.Q1 to    SLICE_81.D1 FS[17]
-CTOF_DEL    ---     0.371    SLICE_81.D1 to    SLICE_81.F1 SLICE_81
-ROUTE         1   e 1.441    SLICE_81.F1 to    SLICE_72.C1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371    SLICE_72.C1 to    SLICE_72.F1 SLICE_72
-ROUTE         4   e 1.441    SLICE_72.F1 to    SLICE_58.C1 N_51
-CTOF_DEL    ---     0.371    SLICE_58.C1 to    SLICE_58.F1 SLICE_58
-ROUTE         2   e 1.441    SLICE_58.F1 to    SLICE_87.D0 N_151
-CTOF_DEL    ---     0.371    SLICE_87.D0 to    SLICE_87.F0 SLICE_87
-ROUTE         2   e 1.441    SLICE_87.F0 to    SLICE_69.C0 N_137_8
-CTOF_DEL    ---     0.371    SLICE_69.C0 to    SLICE_69.F0 SLICE_69
-ROUTE         1   e 1.441    SLICE_69.F0 to    SLICE_33.CE N_33 (to RCLK_c)
-                  --------
-                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
-
-Report:   88.456MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   51.046 MHz|   6  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   88.456 MHz|   6  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            129 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.430ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
-
-   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
-
- Constraint Details:
-
-      0.411ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
-ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.B0 C1Submitted
-CTOF_DEL    ---     0.074    SLICE_14.B0 to    SLICE_14.F0 SLICE_14
-ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 C1Submitted_RNO (to PHI2_c)
-                  --------
-                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            388 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.342ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
-
- Constraint Details:
-
-      0.325ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.017ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126   SLICE_75.CLK to    SLICE_75.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_75.Q0 to    SLICE_75.M1 CASr (to RCLK_c)
-                  --------
-                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 20:57:14 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            129 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[2]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:               9.621ns  (25.1% logic, 74.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.621ns physical path delay SLICE_71 to SLICE_22 meets
+    172.414ns delay constraint less
+      0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns
+
+ Physical Path Details:
+
+      Data path SLICE_71 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_71.CLK to    SLICE_71.Q0 SLICE_71 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_71.Q0 to    SLICE_56.A1 Bank[2]
+CTOF_DEL    ---     0.371    SLICE_56.A1 to    SLICE_56.F1 SLICE_56
+ROUTE         1   e 1.441    SLICE_56.F1 to    SLICE_70.D1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371    SLICE_70.D1 to    SLICE_70.F1 SLICE_70
+ROUTE         6   e 1.441    SLICE_70.F1 to    SLICE_67.D0 N_147
+CTOF_DEL    ---     0.371    SLICE_67.D0 to    SLICE_67.F0 SLICE_67
+ROUTE         5   e 1.441    SLICE_67.F0 to    SLICE_82.A0 XOR8MEG18
+CTOF_DEL    ---     0.371    SLICE_82.A0 to    SLICE_82.F0 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F0 to    SLICE_22.A0 CmdSubmitted_1_sqmuxa
+CTOF_DEL    ---     0.371    SLICE_22.A0 to    SLICE_22.F0 SLICE_22
+ROUTE         1   e 0.001    SLICE_22.F0 to   SLICE_22.DI0 N_460_0 (to PHI2_c)
+                  --------
+                    9.621   (25.1% logic, 74.9% route), 6 logic levels.
+
+Report:   51.046MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 342.328ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCCAS
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:  400.000MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 342.328ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCRAS
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:  400.000MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            388 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 4.695ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[17]  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
+
+   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.061ns physical path delay SLICE_1 to SLICE_33 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_1.Q1 to    SLICE_81.D1 FS[17]
+CTOF_DEL    ---     0.371    SLICE_81.D1 to    SLICE_81.F1 SLICE_81
+ROUTE         1   e 1.441    SLICE_81.F1 to    SLICE_72.C1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371    SLICE_72.C1 to    SLICE_72.F1 SLICE_72
+ROUTE         4   e 1.441    SLICE_72.F1 to    SLICE_58.C1 N_51
+CTOF_DEL    ---     0.371    SLICE_58.C1 to    SLICE_58.F1 SLICE_58
+ROUTE         2   e 1.441    SLICE_58.F1 to    SLICE_87.D0 N_151
+CTOF_DEL    ---     0.371    SLICE_87.D0 to    SLICE_87.F0 SLICE_87
+ROUTE         2   e 1.441    SLICE_87.F0 to    SLICE_69.C0 N_137_8
+CTOF_DEL    ---     0.371    SLICE_69.C0 to    SLICE_69.F0 SLICE_69
+ROUTE         1   e 1.441    SLICE_69.F0 to    SLICE_33.CE N_33 (to RCLK_c)
+                  --------
+                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
+
+Report:   88.456MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   51.046 MHz|   6  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   88.456 MHz|   6  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 20:57:14 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            129 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.430ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
+
+   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.411ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.B0 C1Submitted
+CTOF_DEL    ---     0.074    SLICE_14.B0 to    SLICE_14.F0 SLICE_14
+ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 C1Submitted_RNO (to PHI2_c)
+                  --------
+                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            388 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2  (to RCLK_c +)
+
+   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.325ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126   SLICE_75.CLK to    SLICE_75.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_75.Q0 to    SLICE_75.M1 CASr (to RCLK_c)
+                  --------
+                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
index b6f806d..c593152 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
@@ -1,2238 +1,2238 @@
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            129 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 160.663ns (weighted slack = 321.326ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:              11.577ns  (20.9% logic, 79.1% route), 6 logic levels.
-
- Constraint Details:
-
-     11.577ns physical path delay SLICE_77 to SLICE_22 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 172.240ns) by 160.663ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
-ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
-CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
-ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
-CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
-ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
-                  --------
-                   11.577   (20.9% logic, 79.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.013ns (weighted slack = 322.026ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[6]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:              11.227ns  (21.5% logic, 78.5% route), 6 logic levels.
-
- Constraint Details:
-
-     11.227ns physical path delay SLICE_77 to SLICE_22 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.013ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
-ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
-CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
-ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
-CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
-ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
-                  --------
-                   11.227   (21.5% logic, 78.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.212ns (weighted slack = 322.424ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[2]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:              11.028ns  (21.9% logic, 78.1% route), 6 logic levels.
-
- Constraint Details:
-
-     11.028ns physical path delay SLICE_71 to SLICE_22 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.212ns
-
- Physical Path Details:
-
-      Data path SLICE_71 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 SLICE_71 (from PHI2_c)
-ROUTE         1     1.956       R7C4A.Q0 to       R4C9B.C1 Bank[2]
-CTOF_DEL    ---     0.371       R4C9B.C1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
-ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
-CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
-ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
-                  --------
-                   11.028   (21.9% logic, 78.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_71:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C4A.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.405ns (weighted slack = 322.810ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[5]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:              10.835ns  (22.3% logic, 77.7% route), 6 logic levels.
-
- Constraint Details:
-
-     10.835ns physical path delay SLICE_76 to SLICE_22 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.405ns
-
- Physical Path Details:
-
-      Data path SLICE_76 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C4C.CLK to       R7C4C.Q1 SLICE_76 (from PHI2_c)
-ROUTE         1     1.763       R7C4C.Q1 to       R4C9B.D1 Bank[5]
-CTOF_DEL    ---     0.371       R4C9B.D1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
-ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
-CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
-ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
-                  --------
-                   10.835   (22.3% logic, 77.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_76:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C4C.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.733ns (weighted slack = 323.466ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:              10.416ns  (19.6% logic, 80.4% route), 5 logic levels.
-
- Constraint Details:
-
-     10.416ns physical path delay SLICE_77 to SLICE_74 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 161.733ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
-ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
-CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                   10.416   (19.6% logic, 80.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.083ns (weighted slack = 324.166ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[6]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:              10.066ns  (20.3% logic, 79.7% route), 5 logic levels.
-
- Constraint Details:
-
-     10.066ns physical path delay SLICE_77 to SLICE_74 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 162.083ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
-ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
-CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                   10.066   (20.3% logic, 79.7% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.194ns (weighted slack = 324.388ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS  (to PHI2_c -)
-                   FF                        CmdUFMCLK
-
-   Delay:               9.955ns  (20.5% logic, 79.5% route), 5 logic levels.
-
- Constraint Details:
-
-      9.955ns physical path delay SLICE_77 to SLICE_73 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 162.194ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
-ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
-CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.178       R7C5D.F1 to       R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    9.955   (20.5% logic, 79.5% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C8A.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.282ns (weighted slack = 324.564ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[2]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               9.867ns  (20.7% logic, 79.3% route), 5 logic levels.
-
- Constraint Details:
-
-      9.867ns physical path delay SLICE_71 to SLICE_74 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 162.282ns
-
- Physical Path Details:
-
-      Data path SLICE_71 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 SLICE_71 (from PHI2_c)
-ROUTE         1     1.956       R7C4A.Q0 to       R4C9B.C1 Bank[2]
-CTOF_DEL    ---     0.371       R4C9B.C1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    9.867   (20.7% logic, 79.3% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_71:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C4A.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.475ns (weighted slack = 324.950ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[5]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               9.674ns  (21.1% logic, 78.9% route), 5 logic levels.
-
- Constraint Details:
-
-      9.674ns physical path delay SLICE_76 to SLICE_74 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 162.475ns
-
- Physical Path Details:
-
-      Data path SLICE_76 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C4C.CLK to       R7C4C.Q1 SLICE_76 (from PHI2_c)
-ROUTE         1     1.763       R7C4C.Q1 to       R4C9B.D1 Bank[5]
-CTOF_DEL    ---     0.371       R4C9B.D1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    9.674   (21.1% logic, 78.9% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_76:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C4C.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.544ns (weighted slack = 325.088ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank[6]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS  (to PHI2_c -)
-                   FF                        CmdUFMCLK
-
-   Delay:               9.605ns  (21.3% logic, 78.7% route), 5 logic levels.
-
- Constraint Details:
-
-      9.605ns physical path delay SLICE_77 to SLICE_73 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 172.149ns) by 162.544ns
-
- Physical Path Details:
-
-      Data path SLICE_77 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
-ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
-CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
-ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
-CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
-ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
-CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
-CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
-ROUTE         2     1.178       R7C5D.F1 to       R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    9.605   (21.3% logic, 78.7% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     3.682       39.PADDI to      R7C8A.CLK PHI2_c
-                  --------
-                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   42.550MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 342.328ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:  400.000MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 342.328ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:  400.000MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            388 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 7.336ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.420ns  (28.7% logic, 71.3% route), 6 logic levels.
-
- Constraint Details:
-
-      8.420ns physical path delay SLICE_2 to SLICE_58 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.336ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
-ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
-CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
-CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
-ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
-                  --------
-                    8.420   (28.7% logic, 71.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.342ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.414ns  (28.7% logic, 71.3% route), 6 logic levels.
-
- Constraint Details:
-
-      8.414ns physical path delay SLICE_2 to SLICE_33 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.342ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
-ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
-CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
-CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
-ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
-                  --------
-                    8.414   (28.7% logic, 71.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.396ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.360ns  (28.9% logic, 71.1% route), 6 logic levels.
-
- Constraint Details:
-
-      8.360ns physical path delay SLICE_3 to SLICE_58 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.396ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
-CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
-CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
-ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
-                  --------
-                    8.360   (28.9% logic, 71.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.402ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.354ns  (28.9% logic, 71.1% route), 6 logic levels.
-
- Constraint Details:
-
-      8.354ns physical path delay SLICE_3 to SLICE_33 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.402ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
-CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
-CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
-ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
-                  --------
-                    8.354   (28.9% logic, 71.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.475ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
-
-   Delay:               8.344ns  (28.9% logic, 71.1% route), 6 logic levels.
-
- Constraint Details:
-
-      8.344ns physical path delay SLICE_2 to SLICE_52 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.475ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
-ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
-CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
-CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
-ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
-CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
-ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
-                  --------
-                    8.344   (28.9% logic, 71.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.535ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
-
-   Delay:               8.284ns  (29.2% logic, 70.8% route), 6 logic levels.
-
- Constraint Details:
-
-      8.284ns physical path delay SLICE_3 to SLICE_52 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.535ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
-CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
-CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
-ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
-CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
-ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
-                  --------
-                    8.284   (29.2% logic, 70.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.721ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[14]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.035ns  (30.1% logic, 69.9% route), 6 logic levels.
-
- Constraint Details:
-
-      8.035ns physical path delay SLICE_2 to SLICE_58 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.721ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
-CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
-CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
-ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
-                  --------
-                    8.035   (30.1% logic, 69.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.727ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[14]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.029ns  (30.1% logic, 69.9% route), 6 logic levels.
-
- Constraint Details:
-
-      8.029ns physical path delay SLICE_2 to SLICE_33 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.727ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
-CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
-CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
-ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
-                  --------
-                    8.029   (30.1% logic, 69.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.860ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[14]  (from RCLK_c +)
-   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
-
-   Delay:               7.959ns  (30.3% logic, 69.7% route), 6 logic levels.
-
- Constraint Details:
-
-      7.959ns physical path delay SLICE_2 to SLICE_52 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.860ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
-CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
-CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
-ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
-CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
-ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
-                  --------
-                    7.959   (30.3% logic, 69.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_52:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.998ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               7.758ns  (31.1% logic, 68.9% route), 6 logic levels.
-
- Constraint Details:
-
-      7.758ns physical path delay SLICE_1 to SLICE_58 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.998ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C6A.CLK to       R8C6A.Q1 SLICE_1 (from RCLK_c)
-ROUTE         3     0.909       R8C6A.Q1 to       R7C6A.C1 FS[17]
-CTOF_DEL    ---     0.371       R7C6A.C1 to       R7C6A.F1 SLICE_81
-ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
-ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
-CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
-ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
-CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
-ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
-CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
-ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
-                  --------
-                    7.758   (31.1% logic, 68.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R8C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  115.420MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   42.550 MHz|   6  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  115.420 MHz|   6  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            129 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.358ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               0.339ns  (62.2% logic, 37.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.339ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.358ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R6C2A.CLK to       R6C2A.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.128       R6C2A.Q0 to       R6C2A.D0 ADSubmitted
-CTOF_DEL    ---     0.074       R6C2A.D0 to       R6C2A.F0 SLICE_9
-ROUTE         1     0.000       R6C2A.F0 to      R6C2A.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    0.339   (62.2% logic, 37.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.361ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
-
-   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.342ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R7C3C.CLK to       R7C3C.Q0 SLICE_14 (from PHI2_c)
-ROUTE         2     0.131       R7C3C.Q0 to       R7C3C.A0 C1Submitted
-CTOF_DEL    ---     0.074       R7C3C.A0 to       R7C3C.F0 SLICE_14
-ROUTE         1     0.000       R7C3C.F0 to      R7C3C.DI0 C1Submitted_RNO (to PHI2_c)
-                  --------
-                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.364ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:               0.345ns  (61.2% logic, 38.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.345ns physical path delay SLICE_22 to SLICE_22 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.364ns
-
- Physical Path Details:
-
-      Data path SLICE_22 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R8C9D.CLK to       R8C9D.Q0 SLICE_22 (from PHI2_c)
-ROUTE         3     0.134       R8C9D.Q0 to       R8C9D.A0 CmdSubmitted
-CTOF_DEL    ---     0.074       R8C9D.A0 to       R8C9D.F0 SLICE_22
-ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
-                  --------
-                    0.345   (61.2% logic, 38.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_22:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R8C9D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.411ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.392ns  (65.8% logic, 34.2% route), 2 logic levels.
-
- Constraint Details:
-
-      0.392ns physical path delay SLICE_20 to SLICE_20 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.411ns
-
- Physical Path Details:
-
-      Data path SLICE_20 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
-ROUTE         3     0.134       R6C2D.Q0 to       R6C2D.D1 CmdEnable
-CTOOFX_DEL  ---     0.121       R6C2D.D1 to     R6C2D.OFX0 SLICE_20
-ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.392   (65.8% logic, 34.2% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.415ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.396ns  (66.2% logic, 33.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.396ns physical path delay SLICE_20 to SLICE_20 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.415ns
-
- Physical Path Details:
-
-      Data path SLICE_20 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
-ROUTE         3     0.134       R6C2D.Q0 to       R6C2D.A0 CmdEnable
-CTOOFX_DEL  ---     0.125       R6C2D.A0 to     R6C2D.OFX0 SLICE_20
-ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.396   (66.2% logic, 33.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.471ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.452ns  (57.1% logic, 42.9% route), 2 logic levels.
-
- Constraint Details:
-
-      0.452ns physical path delay SLICE_9 to SLICE_20 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.471ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R6C2A.CLK to       R6C2A.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.194       R6C2A.Q0 to       R6C2D.A1 ADSubmitted
-CTOOFX_DEL  ---     0.121       R6C2D.A1 to     R6C2D.OFX0 SLICE_20
-ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.452   (57.1% logic, 42.9% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.611ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Cmdn8MEGEN  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)
-
-   Delay:               0.592ns  (48.1% logic, 51.9% route), 3 logic levels.
-
- Constraint Details:
-
-      0.592ns physical path delay SLICE_26 to SLICE_26 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.611ns
-
- Physical Path Details:
-
-      Data path SLICE_26 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R7C5B.CLK to       R7C5B.Q0 SLICE_26 (from PHI2_c)
-ROUTE         2     0.208       R7C5B.Q0 to       R7C5B.B1 Cmdn8MEGEN
-CTOF_DEL    ---     0.074       R7C5B.B1 to       R7C5B.F1 SLICE_26
-ROUTE         1     0.099       R7C5B.F1 to       R7C5B.C0 Cmdn8MEGEN_4_u_i_0
-CTOF_DEL    ---     0.074       R7C5B.C0 to       R7C5B.F0 SLICE_26
-ROUTE         1     0.000       R7C5B.F0 to      R7C5B.DI0 N_19_i (to PHI2_c)
-                  --------
-                    0.592   (48.1% logic, 51.9% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C5B.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C5B.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.634ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.615ns  (42.6% logic, 57.4% route), 2 logic levels.
-
- Constraint Details:
-
-      0.615ns physical path delay SLICE_14 to SLICE_20 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.634ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R7C3C.CLK to       R7C3C.Q0 SLICE_14 (from PHI2_c)
-ROUTE         2     0.353       R7C3C.Q0 to       R6C2D.C0 C1Submitted
-CTOOFX_DEL  ---     0.125       R6C2D.C0 to     R6C2D.OFX0 SLICE_20
-ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.615   (42.6% logic, 57.4% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.665ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDEN  (from PHI2_c -)
-   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
-
-   Delay:               0.646ns  (44.1% logic, 55.9% route), 3 logic levels.
-
- Constraint Details:
-
-      0.646ns physical path delay SLICE_21 to SLICE_21 meets
-     -0.019ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.665ns
-
- Physical Path Details:
-
-      Data path SLICE_21 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R7C5A.CLK to       R7C5A.Q0 SLICE_21 (from PHI2_c)
-ROUTE         2     0.169       R7C5A.Q0 to       R7C5C.C1 CmdLEDEN
-CTOF_DEL    ---     0.074       R7C5C.C1 to       R7C5C.F1 SLICE_82
-ROUTE         1     0.192       R7C5C.F1 to       R7C5A.A0 N_132
-CTOF_DEL    ---     0.074       R7C5A.A0 to       R7C5A.F0 SLICE_21
-ROUTE         1     0.000       R7C5A.F0 to      R7C5A.DI0 N_21_i (to PHI2_c)
-                  --------
-                    0.646   (44.1% logic, 55.9% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.723ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
-
-   Delay:               0.700ns  (30.1% logic, 69.9% route), 2 logic levels.
-
- Constraint Details:
-
-      0.700ns physical path delay SLICE_20 to SLICE_21 meets
-     -0.023ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.723ns
-
- Physical Path Details:
-
-      Data path SLICE_20 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
-ROUTE         3     0.348       R6C2D.Q0 to       R7C5D.B0 CmdEnable
-CTOF_DEL    ---     0.074       R7C5D.B0 to       R7C5D.F0 SLICE_67
-ROUTE         5     0.141       R7C5D.F0 to       R7C5A.CE XOR8MEG18 (to PHI2_c)
-                  --------
-                    0.700   (30.1% logic, 69.9% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
-                  --------
-                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            388 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.273ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.256ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.017ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R7C4B.CLK to       R7C4B.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1     0.130       R7C4B.Q0 to       R7C4B.M1 CASr (to RCLK_c)
-                  --------
-                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R7C4B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R7C4B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.301ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[17]  (to RCLK_c +)
-                   FF                        FS[16]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_1 to SLICE_1 meets
-     -0.044ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C6A.CLK to       R8C6A.Q1 SLICE_1 (from RCLK_c)
-ROUTE         3     0.131       R8C6A.Q1 to       R8C6A.A1 FS[17] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C6A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C6A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.301ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[14]  (to RCLK_c +)
-                   FF                        FS[15]
-                   FF                        FS[14]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_2 to SLICE_2 meets
-     -0.044ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
-ROUTE         3     0.131       R8C5D.Q1 to       R8C5D.A1 FS[15] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5D.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.301ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[12]  (to RCLK_c +)
-                   FF                        FS[13]
-                   FF                        FS[12]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_3 to SLICE_3 meets
-     -0.044ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     0.131       R8C5C.Q1 to       R8C5C.A1 FS[13] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5C.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5C.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.301ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[5]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[4]  (to RCLK_c +)
-                   FF                        FS[5]
-                   FF                        FS[4]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_7 to SLICE_7 meets
-     -0.044ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C4C.CLK to       R8C4C.Q1 SLICE_7 (from RCLK_c)
-ROUTE         4     0.131       R8C4C.Q1 to       R8C4C.A1 FS[5] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.301ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[3]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[2]  (to RCLK_c +)
-                   FF                        FS[3]
-                   FF                        FS[2]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_8 to SLICE_8 meets
-     -0.044ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C4B.CLK to       R8C4B.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     0.131       R8C4B.Q1 to       R8C4B.A1 FS[3] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.302ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[0]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[0]  (to RCLK_c +)
-                   FF                        FS[1]
-                   FF                        FS[0]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.045ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C4A.CLK to       R8C4A.Q0 SLICE_0 (from RCLK_c)
-ROUTE         3     0.131       R8C4A.Q0 to       R8C4A.A0 FS[0] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.302ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[10]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[10]  (to RCLK_c +)
-                   FF                        FS[11]
-                   FF                        FS[10]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_4 to SLICE_4 meets
-     -0.045ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C5B.CLK to       R8C5B.Q0 SLICE_4 (from RCLK_c)
-ROUTE         5     0.131       R8C5B.Q0 to       R8C5B.A0 FS[10] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5B.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.302ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[8]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[8]  (to RCLK_c +)
-                   FF                        FS[9]
-                   FF                        FS[8]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_5 to SLICE_5 meets
-     -0.045ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C5A.CLK to       R8C5A.Q0 SLICE_5 (from RCLK_c)
-ROUTE         3     0.131       R8C5A.Q0 to       R8C5A.A0 FS[8] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C5A.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.302ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[6]  (from RCLK_c +)
-   Destination:    FF         Data in        FS_cry_0[6]  (to RCLK_c +)
-                   FF                        FS[7]
-                   FF                        FS[6]
-
-   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.257ns physical path delay SLICE_6 to SLICE_6 meets
-     -0.045ns LUT_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.126      R8C4D.CLK to       R8C4D.Q0 SLICE_6 (from RCLK_c)
-ROUTE         3     0.131       R8C4D.Q0 to       R8C4D.A0 FS[6] (to RCLK_c)
-                  --------
-                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        32     0.351       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 20:57:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            129 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 160.663ns (weighted slack = 321.326ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[7]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:              11.577ns  (20.9% logic, 79.1% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.577ns physical path delay SLICE_77 to SLICE_22 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 172.240ns) by 160.663ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
+ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
+CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
+ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
+CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
+ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
+                  --------
+                   11.577   (20.9% logic, 79.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.013ns (weighted slack = 322.026ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:              11.227ns  (21.5% logic, 78.5% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.227ns physical path delay SLICE_77 to SLICE_22 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.013ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
+ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
+CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
+ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
+CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
+ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
+                  --------
+                   11.227   (21.5% logic, 78.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.212ns (weighted slack = 322.424ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[2]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:              11.028ns  (21.9% logic, 78.1% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.028ns physical path delay SLICE_71 to SLICE_22 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.212ns
+
+ Physical Path Details:
+
+      Data path SLICE_71 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 SLICE_71 (from PHI2_c)
+ROUTE         1     1.956       R7C4A.Q0 to       R4C9B.C1 Bank[2]
+CTOF_DEL    ---     0.371       R4C9B.C1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
+ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
+CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
+ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
+                  --------
+                   11.028   (21.9% logic, 78.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_71:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C4A.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.405ns (weighted slack = 322.810ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[5]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:              10.835ns  (22.3% logic, 77.7% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.835ns physical path delay SLICE_76 to SLICE_22 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 172.240ns) by 161.405ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4C.CLK to       R7C4C.Q1 SLICE_76 (from PHI2_c)
+ROUTE         1     1.763       R7C4C.Q1 to       R4C9B.D1 Bank[5]
+CTOF_DEL    ---     0.371       R4C9B.D1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.867       R7C5D.F0 to       R7C5C.C0 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_82
+ROUTE         1     2.090       R7C5C.F0 to       R8C9D.D0 CmdSubmitted_1_sqmuxa
+CTOF_DEL    ---     0.371       R8C9D.D0 to       R8C9D.F0 SLICE_22
+ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
+                  --------
+                   10.835   (22.3% logic, 77.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C4C.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.733ns (weighted slack = 323.466ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[7]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
+
+   Delay:              10.416ns  (19.6% logic, 80.4% route), 5 logic levels.
+
+ Constraint Details:
+
+     10.416ns physical path delay SLICE_77 to SLICE_74 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 161.733ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
+ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
+CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                   10.416   (19.6% logic, 80.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.083ns (weighted slack = 324.166ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
+
+   Delay:              10.066ns  (20.3% logic, 79.7% route), 5 logic levels.
+
+ Constraint Details:
+
+     10.066ns physical path delay SLICE_77 to SLICE_74 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 162.083ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
+ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
+CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                   10.066   (20.3% logic, 79.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.194ns (weighted slack = 324.388ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[7]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS  (to PHI2_c -)
+                   FF                        CmdUFMCLK
+
+   Delay:               9.955ns  (20.5% logic, 79.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.955ns physical path delay SLICE_77 to SLICE_73 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 162.194ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q1 SLICE_77 (from PHI2_c)
+ROUTE         1     2.505       R7C2B.Q1 to       R4C9B.A1 Bank[7]
+CTOF_DEL    ---     0.371       R4C9B.A1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.178       R7C5D.F1 to       R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                    9.955   (20.5% logic, 79.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C8A.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.282ns (weighted slack = 324.564ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[2]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
+
+   Delay:               9.867ns  (20.7% logic, 79.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.867ns physical path delay SLICE_71 to SLICE_74 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 162.282ns
+
+ Physical Path Details:
+
+      Data path SLICE_71 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 SLICE_71 (from PHI2_c)
+ROUTE         1     1.956       R7C4A.Q0 to       R4C9B.C1 Bank[2]
+CTOF_DEL    ---     0.371       R4C9B.C1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                    9.867   (20.7% logic, 79.3% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_71:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C4A.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.475ns (weighted slack = 324.950ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[5]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
+
+   Delay:               9.674ns  (21.1% logic, 78.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.674ns physical path delay SLICE_76 to SLICE_74 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 162.475ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4C.CLK to       R7C4C.Q1 SLICE_76 (from PHI2_c)
+ROUTE         1     1.763       R7C4C.Q1 to       R4C9B.D1 Bank[5]
+CTOF_DEL    ---     0.371       R4C9B.D1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.639       R7C5D.F1 to       R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                    9.674   (21.1% logic, 78.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C4C.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R8C7D.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.544ns (weighted slack = 325.088ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank[6]  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS  (to PHI2_c -)
+                   FF                        CmdUFMCLK
+
+   Delay:               9.605ns  (21.3% logic, 78.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.605ns physical path delay SLICE_77 to SLICE_73 meets
+    172.414ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 172.149ns) by 162.544ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_77 (from PHI2_c)
+ROUTE         1     2.155       R7C2B.Q0 to       R4C9B.B1 Bank[6]
+CTOF_DEL    ---     0.371       R4C9B.B1 to       R4C9B.F1 SLICE_56
+ROUTE         1     2.155       R4C9B.F1 to       R7C2A.B1 C1WR_0_a2_0_11
+CTOF_DEL    ---     0.371       R7C2A.B1 to       R7C2A.F1 SLICE_70
+ROUTE         6     1.545       R7C2A.F1 to       R7C5D.A0 N_147
+CTOF_DEL    ---     0.371       R7C5D.A0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.528       R7C5D.F0 to       R7C5D.C1 XOR8MEG18
+CTOF_DEL    ---     0.371       R7C5D.C1 to       R7C5D.F1 SLICE_67
+ROUTE         2     1.178       R7C5D.F1 to       R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
+                  --------
+                    9.605   (21.3% logic, 78.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C2B.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     3.682       39.PADDI to      R7C8A.CLK PHI2_c
+                  --------
+                    3.682   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   42.550MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 342.328ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCCAS
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:  400.000MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 342.328ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    PIO        PAD            nCRAS
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:  400.000MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            388 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 7.336ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
+
+   Delay:               8.420ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.420ns physical path delay SLICE_2 to SLICE_58 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.336ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
+ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
+CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
+CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
+ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
+                  --------
+                    8.420   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
+
+   Delay:               8.414ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.414ns physical path delay SLICE_2 to SLICE_33 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
+ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
+CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
+CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
+ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
+                  --------
+                    8.414   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
+
+   Delay:               8.360ns  (28.9% logic, 71.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.360ns physical path delay SLICE_3 to SLICE_58 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.396ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
+CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
+CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
+ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
+                  --------
+                    8.360   (28.9% logic, 71.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.402ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
+
+   Delay:               8.354ns  (28.9% logic, 71.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.354ns physical path delay SLICE_3 to SLICE_33 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.402ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
+CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
+CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
+ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
+                  --------
+                    8.354   (28.9% logic, 71.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.475ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
+
+   Delay:               8.344ns  (28.9% logic, 71.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.344ns physical path delay SLICE_2 to SLICE_52 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.475ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
+ROUTE         3     1.571       R8C5D.Q1 to       R7C6A.B1 FS[15]
+CTOF_DEL    ---     0.371       R7C6A.B1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
+CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
+ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
+CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
+ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
+                  --------
+                    8.344   (28.9% logic, 71.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.535ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
+
+   Delay:               8.284ns  (29.2% logic, 70.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.284ns physical path delay SLICE_3 to SLICE_52 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.535ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.511       R8C5C.Q1 to       R7C6A.A1 FS[13]
+CTOF_DEL    ---     0.371       R7C6A.A1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
+CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
+ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
+CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
+ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
+                  --------
+                    8.284   (29.2% logic, 70.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.721ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[14]  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
+
+   Delay:               8.035ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.035ns physical path delay SLICE_2 to SLICE_58 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.721ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
+ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
+CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
+CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
+ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
+                  --------
+                    8.035   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.727ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[14]  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
+
+   Delay:               8.029ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.029ns physical path delay SLICE_2 to SLICE_33 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.727ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
+ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
+CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.716       R8C7B.F0 to       R8C6B.D0 N_137_8
+CTOF_DEL    ---     0.371       R8C6B.D0 to       R8C6B.F0 SLICE_69
+ROUTE         1     1.260       R8C6B.F0 to       R9C9B.CE N_33 (to RCLK_c)
+                  --------
+                    8.029   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.860ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[14]  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI  (to RCLK_c +)
+
+   Delay:               7.959ns  (30.3% logic, 69.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.959ns physical path delay SLICE_2 to SLICE_52 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.860ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C5D.CLK to       R8C5D.Q0 SLICE_2 (from RCLK_c)
+ROUTE         3     1.186       R8C5D.Q0 to       R7C6A.D1 FS[14]
+CTOF_DEL    ---     0.371       R7C6A.D1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.919       R7C6B.F1 to       R8C7B.B1 N_151
+CTOF_DEL    ---     0.371       R8C7B.B1 to       R8C7B.F1 SLICE_87
+ROUTE         1     1.156       R8C7B.F1 to       R9C9C.D0 UFMSDI_r_xx_mm_1
+CTOF_DEL    ---     0.371       R9C9C.D0 to       R9C9C.F0 SLICE_52
+ROUTE         1     0.000       R9C9C.F0 to      R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
+                  --------
+                    7.959   (30.3% logic, 69.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_52:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.998ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[17]  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
+
+   Delay:               7.758ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.758ns physical path delay SLICE_1 to SLICE_58 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.998ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C6A.CLK to       R8C6A.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.909       R8C6A.Q1 to       R7C6A.C1 FS[17]
+CTOF_DEL    ---     0.371       R7C6A.C1 to       R7C6A.F1 SLICE_81
+ROUTE         1     0.626       R7C6A.F1 to       R7C6D.D1 UFMSDI_ens2_i_o2_0_3
+CTOF_DEL    ---     0.371       R7C6D.D1 to       R7C6D.F1 SLICE_72
+ROUTE         4     0.657       R7C6D.F1 to       R7C6B.D1 N_51
+CTOF_DEL    ---     0.371       R7C6B.D1 to       R7C6B.F1 SLICE_58
+ROUTE         2     1.169       R7C6B.F1 to       R8C7B.D0 N_151
+CTOF_DEL    ---     0.371       R8C7B.D0 to       R8C7B.F0 SLICE_87
+ROUTE         2     0.909       R8C7B.F0 to       R8C6C.C0 N_137_8
+CTOF_DEL    ---     0.371       R8C6C.C0 to       R8C6C.F0 SLICE_68
+ROUTE         1     1.073       R8C6C.F0 to       R7C6B.CE N_31 (to RCLK_c)
+                  --------
+                    7.758   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R8C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     1.425       86.PADDI to      R7C6B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:  115.420MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   42.550 MHz|   6  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  115.420 MHz|   6  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Sat Aug 19 20:57:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+            129 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.358ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
+
+   Delay:               0.339ns  (62.2% logic, 37.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.339ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.358ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C2A.CLK to       R6C2A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.128       R6C2A.Q0 to       R6C2A.D0 ADSubmitted
+CTOF_DEL    ---     0.074       R6C2A.D0 to       R6C2A.F0 SLICE_9
+ROUTE         1     0.000       R6C2A.F0 to      R6C2A.DI0 ADSubmitted_r (to PHI2_c)
+                  --------
+                    0.339   (62.2% logic, 37.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R7C3C.CLK to       R7C3C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.131       R7C3C.Q0 to       R7C3C.A0 C1Submitted
+CTOF_DEL    ---     0.074       R7C3C.A0 to       R7C3C.F0 SLICE_14
+ROUTE         1     0.000       R7C3C.F0 to      R7C3C.DI0 C1Submitted_RNO (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.364ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
+
+   Delay:               0.345ns  (61.2% logic, 38.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.345ns physical path delay SLICE_22 to SLICE_22 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.364ns
+
+ Physical Path Details:
+
+      Data path SLICE_22 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R8C9D.CLK to       R8C9D.Q0 SLICE_22 (from PHI2_c)
+ROUTE         3     0.134       R8C9D.Q0 to       R8C9D.A0 CmdSubmitted
+CTOF_DEL    ---     0.074       R8C9D.A0 to       R8C9D.F0 SLICE_22
+ROUTE         1     0.000       R8C9D.F0 to      R8C9D.DI0 N_460_0 (to PHI2_c)
+                  --------
+                    0.345   (61.2% logic, 38.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R8C9D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.411ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.392ns  (65.8% logic, 34.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.392ns physical path delay SLICE_20 to SLICE_20 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_20 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
+ROUTE         3     0.134       R6C2D.Q0 to       R6C2D.D1 CmdEnable
+CTOOFX_DEL  ---     0.121       R6C2D.D1 to     R6C2D.OFX0 SLICE_20
+ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.392   (65.8% logic, 34.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.415ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.396ns  (66.2% logic, 33.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.396ns physical path delay SLICE_20 to SLICE_20 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.415ns
+
+ Physical Path Details:
+
+      Data path SLICE_20 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
+ROUTE         3     0.134       R6C2D.Q0 to       R6C2D.A0 CmdEnable
+CTOOFX_DEL  ---     0.125       R6C2D.A0 to     R6C2D.OFX0 SLICE_20
+ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.396   (66.2% logic, 33.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.452ns  (57.1% logic, 42.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.452ns physical path delay SLICE_9 to SLICE_20 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.471ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C2A.CLK to       R6C2A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.194       R6C2A.Q0 to       R6C2D.A1 ADSubmitted
+CTOOFX_DEL  ---     0.121       R6C2D.A1 to     R6C2D.OFX0 SLICE_20
+ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.452   (57.1% logic, 42.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.611ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Cmdn8MEGEN  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)
+
+   Delay:               0.592ns  (48.1% logic, 51.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.592ns physical path delay SLICE_26 to SLICE_26 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.611ns
+
+ Physical Path Details:
+
+      Data path SLICE_26 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R7C5B.CLK to       R7C5B.Q0 SLICE_26 (from PHI2_c)
+ROUTE         2     0.208       R7C5B.Q0 to       R7C5B.B1 Cmdn8MEGEN
+CTOF_DEL    ---     0.074       R7C5B.B1 to       R7C5B.F1 SLICE_26
+ROUTE         1     0.099       R7C5B.F1 to       R7C5B.C0 Cmdn8MEGEN_4_u_i_0
+CTOF_DEL    ---     0.074       R7C5B.C0 to       R7C5B.F0 SLICE_26
+ROUTE         1     0.000       R7C5B.F0 to      R7C5B.DI0 N_19_i (to PHI2_c)
+                  --------
+                    0.592   (48.1% logic, 51.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C5B.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C5B.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.634ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
+
+   Delay:               0.615ns  (42.6% logic, 57.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.615ns physical path delay SLICE_14 to SLICE_20 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.634ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R7C3C.CLK to       R7C3C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.353       R7C3C.Q0 to       R6C2D.C0 C1Submitted
+CTOOFX_DEL  ---     0.125       R6C2D.C0 to     R6C2D.OFX0 SLICE_20
+ROUTE         1     0.000     R6C2D.OFX0 to      R6C2D.DI0 CmdEnable_s (to PHI2_c)
+                  --------
+                    0.615   (42.6% logic, 57.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C3C.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.665ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdLEDEN  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
+
+   Delay:               0.646ns  (44.1% logic, 55.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.646ns physical path delay SLICE_21 to SLICE_21 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.665ns
+
+ Physical Path Details:
+
+      Data path SLICE_21 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R7C5A.CLK to       R7C5A.Q0 SLICE_21 (from PHI2_c)
+ROUTE         2     0.169       R7C5A.Q0 to       R7C5C.C1 CmdLEDEN
+CTOF_DEL    ---     0.074       R7C5C.C1 to       R7C5C.F1 SLICE_82
+ROUTE         1     0.192       R7C5C.F1 to       R7C5A.A0 N_132
+CTOF_DEL    ---     0.074       R7C5A.A0 to       R7C5A.F0 SLICE_21
+ROUTE         1     0.000       R7C5A.F0 to      R7C5A.DI0 N_21_i (to PHI2_c)
+                  --------
+                    0.646   (44.1% logic, 55.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.723ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
+
+   Delay:               0.700ns  (30.1% logic, 69.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.700ns physical path delay SLICE_20 to SLICE_21 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.723ns
+
+ Physical Path Details:
+
+      Data path SLICE_20 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C2D.CLK to       R6C2D.Q0 SLICE_20 (from PHI2_c)
+ROUTE         3     0.348       R6C2D.Q0 to       R7C5D.B0 CmdEnable
+CTOF_DEL    ---     0.074       R7C5D.B0 to       R7C5D.F0 SLICE_67
+ROUTE         5     0.141       R7C5D.F0 to       R7C5A.CE XOR8MEG18 (to PHI2_c)
+                  --------
+                    0.700   (30.1% logic, 69.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R6C2D.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        15     0.907       39.PADDI to      R7C5A.CLK PHI2_c
+                  --------
+                    0.907   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+            388 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C4B.CLK to       R7C4B.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.130       R7C4B.Q0 to       R7C4B.M1 CASr (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[17]  (from RCLK_c +)
+   Destination:    FF         Data in        FS[17]  (to RCLK_c +)
+                   FF                        FS[16]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C6A.CLK to       R8C6A.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.131       R8C6A.Q1 to       R8C6A.A1 FS[17] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C6A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C6A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[15]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[14]  (to RCLK_c +)
+                   FF                        FS[15]
+                   FF                        FS[14]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_2 to SLICE_2 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5D.CLK to       R8C5D.Q1 SLICE_2 (from RCLK_c)
+ROUTE         3     0.131       R8C5D.Q1 to       R8C5D.A1 FS[15] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[12]  (to RCLK_c +)
+                   FF                        FS[13]
+                   FF                        FS[12]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_3 to SLICE_3 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5C.CLK to       R8C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     0.131       R8C5C.Q1 to       R8C5C.A1 FS[13] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[5]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[4]  (to RCLK_c +)
+                   FF                        FS[5]
+                   FF                        FS[4]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_7 to SLICE_7 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4C.CLK to       R8C4C.Q1 SLICE_7 (from RCLK_c)
+ROUTE         4     0.131       R8C4C.Q1 to       R8C4C.A1 FS[5] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[3]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[2]  (to RCLK_c +)
+                   FF                        FS[3]
+                   FF                        FS[2]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_8 to SLICE_8 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4B.CLK to       R8C4B.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     0.131       R8C4B.Q1 to       R8C4B.A1 FS[3] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.302ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[0]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[0]  (to RCLK_c +)
+                   FF                        FS[1]
+                   FF                        FS[0]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.045ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4A.CLK to       R8C4A.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3     0.131       R8C4A.Q0 to       R8C4A.A0 FS[0] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.302ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[10]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[10]  (to RCLK_c +)
+                   FF                        FS[11]
+                   FF                        FS[10]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_4 to SLICE_4 meets
+     -0.045ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5B.CLK to       R8C5B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         5     0.131       R8C5B.Q0 to       R8C5B.A0 FS[10] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.302ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[8]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[8]  (to RCLK_c +)
+                   FF                        FS[9]
+                   FF                        FS[8]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_5 to SLICE_5 meets
+     -0.045ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5A.CLK to       R8C5A.Q0 SLICE_5 (from RCLK_c)
+ROUTE         3     0.131       R8C5A.Q0 to       R8C5A.A0 FS[8] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.302ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[6]  (from RCLK_c +)
+   Destination:    FF         Data in        FS_cry_0[6]  (to RCLK_c +)
+                   FF                        FS[7]
+                   FF                        FS[6]
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_6 to SLICE_6 meets
+     -0.045ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.045ns) by 0.302ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4D.CLK to       R8C4D.Q0 SLICE_6 (from RCLK_c)
+ROUTE         3     0.131       R8C4D.Q0 to       R8C4D.A0 FS[6] (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        32     0.351       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
+                                        |             |             |
+FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
+                                        |             |             |
+FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
+   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
+   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
index 71517e5..e7b5a82 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
@@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:55 2023
+Sat Aug 19 20:57:26 2023
 
 
-Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Command: bitgen -w -g ES:No -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
 
 Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
 Design name: RAM2GS
@@ -52,7 +52,7 @@ Creating bit map...
 Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
 Total CPU Time: 0 secs 
 Total REAL Time: 0 secs 
-Peak Memory Usage: 46 MB
+Peak Memory Usage: 67 MB
 
 
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt
index 06106c9..c904785 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt
@@ -1,155 +1,155 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-
-# Written on Wed Aug 16 04:50:41 2023
-
-##### DESIGN INFO #######################################################
-
-Top View:                "RAM2GS"
-Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
-
-
-
-
-##### SUMMARY ############################################################
-
-Found 0 issues in 0 out of 4 constraints
-
-
-##### DETAILS ############################################################
-
-
-
-Clock Relationships
-*******************
-
-Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
------------------------------------------------------------------------------------------------------------------------------------
-RCLK         RCLK       |     16.000           |     No paths         |     No paths         |     No paths                         
-RCLK         PHI2       |     2.000            |     No paths         |     1.000            |     No paths                         
-RCLK         nCRAS      |     No paths         |     No paths         |     1.000            |     No paths                         
-PHI2         RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
-PHI2         PHI2       |     No paths         |     350.000          |     175.000          |     175.000                          
-nCRAS        RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
-===================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. 
-
-
-Unconstrained Start/End Points
-******************************
-
-p:CROW[0]
-p:CROW[1]
-p:Din[0]
-p:Din[1]
-p:Din[2]
-p:Din[3]
-p:Din[4]
-p:Din[5]
-p:Din[6]
-p:Din[7]
-p:Dout[0]
-p:Dout[1]
-p:Dout[2]
-p:Dout[3]
-p:Dout[4]
-p:Dout[5]
-p:Dout[6]
-p:Dout[7]
-p:MAin[0]
-p:MAin[1]
-p:MAin[2]
-p:MAin[3]
-p:MAin[4]
-p:MAin[5]
-p:MAin[6]
-p:MAin[7]
-p:MAin[8]
-p:MAin[9]
-p:RA[0]
-p:RA[1]
-p:RA[2]
-p:RA[3]
-p:RA[4]
-p:RA[5]
-p:RA[6]
-p:RA[7]
-p:RA[8]
-p:RA[9]
-p:RA[10]
-p:RA[11]
-p:RBA[0]
-p:RBA[1]
-p:RCKE
-p:RDQMH
-p:RDQML
-p:RD[0] (bidir end point)
-p:RD[0] (bidir start point)
-p:RD[1] (bidir end point)
-p:RD[1] (bidir start point)
-p:RD[2] (bidir end point)
-p:RD[2] (bidir start point)
-p:RD[3] (bidir end point)
-p:RD[3] (bidir start point)
-p:RD[4] (bidir end point)
-p:RD[4] (bidir start point)
-p:RD[5] (bidir end point)
-p:RD[5] (bidir start point)
-p:RD[6] (bidir end point)
-p:RD[6] (bidir start point)
-p:RD[7] (bidir end point)
-p:RD[7] (bidir start point)
-p:UFMCLK
-p:UFMSDI
-p:UFMSDO
-p:nFWE
-p:nRCAS
-p:nRCS
-p:nRRAS
-p:nRWE
-p:nUFMCS
-
-
-Inapplicable constraints
-************************
-
-(none)
-
-
-Applicable constraints with issues
-**********************************
-
-(none)
-
-
-Constraints with matching wildcard expressions
-**********************************************
-
-(none)
-
-
-Library Report
-**************
-
-
-# End of Constraint Checker Report
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+
+# Written on Sat Aug 19 20:57:08 2023
+
+##### DESIGN INFO #######################################################
+
+Top View:                "RAM2GS"
+Constraint File(s):      "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
+
+
+
+
+##### SUMMARY ############################################################
+
+Found 0 issues in 0 out of 4 constraints
+
+
+##### DETAILS ############################################################
+
+
+
+Clock Relationships
+*******************
+
+Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
+-----------------------------------------------------------------------------------------------------------------------------------
+RCLK         RCLK       |     16.000           |     No paths         |     No paths         |     No paths                         
+RCLK         PHI2       |     2.000            |     No paths         |     1.000            |     No paths                         
+RCLK         nCRAS      |     No paths         |     No paths         |     1.000            |     No paths                         
+PHI2         RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
+PHI2         PHI2       |     No paths         |     350.000          |     175.000          |     175.000                          
+nCRAS        RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
+===================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
+@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. 
+@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
+@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. 
+@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. 
+
+
+Unconstrained Start/End Points
+******************************
+
+p:CROW[0]
+p:CROW[1]
+p:Din[0]
+p:Din[1]
+p:Din[2]
+p:Din[3]
+p:Din[4]
+p:Din[5]
+p:Din[6]
+p:Din[7]
+p:Dout[0]
+p:Dout[1]
+p:Dout[2]
+p:Dout[3]
+p:Dout[4]
+p:Dout[5]
+p:Dout[6]
+p:Dout[7]
+p:MAin[0]
+p:MAin[1]
+p:MAin[2]
+p:MAin[3]
+p:MAin[4]
+p:MAin[5]
+p:MAin[6]
+p:MAin[7]
+p:MAin[8]
+p:MAin[9]
+p:RA[0]
+p:RA[1]
+p:RA[2]
+p:RA[3]
+p:RA[4]
+p:RA[5]
+p:RA[6]
+p:RA[7]
+p:RA[8]
+p:RA[9]
+p:RA[10]
+p:RA[11]
+p:RBA[0]
+p:RBA[1]
+p:RCKE
+p:RDQMH
+p:RDQML
+p:RD[0] (bidir end point)
+p:RD[0] (bidir start point)
+p:RD[1] (bidir end point)
+p:RD[1] (bidir start point)
+p:RD[2] (bidir end point)
+p:RD[2] (bidir start point)
+p:RD[3] (bidir end point)
+p:RD[3] (bidir start point)
+p:RD[4] (bidir end point)
+p:RD[4] (bidir start point)
+p:RD[5] (bidir end point)
+p:RD[5] (bidir start point)
+p:RD[6] (bidir end point)
+p:RD[6] (bidir start point)
+p:RD[7] (bidir end point)
+p:RD[7] (bidir start point)
+p:UFMCLK
+p:UFMSDI
+p:UFMSDO
+p:nFWE
+p:nRCAS
+p:nRCS
+p:nRRAS
+p:nRWE
+p:nUFMCS
+
+
+Inapplicable constraints
+************************
+
+(none)
+
+
+Applicable constraints with issues
+**********************************
+
+(none)
+
+
+Constraints with matching wildcard expressions
+**********************************************
+
+(none)
+
+
+Library Report
+**************
+
+
+# End of Constraint Checker Report
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt.db b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt.db
index 55fa29d7f68280f61f0b2d81f71dcf95a299bdd8..10dc1a5b2075d91ba4ab0032304cae6b1b035682 100644
GIT binary patch
delta 171
zcmZp0XmHrTCcrb9fj^LM5$`8nXP(I$3mbWa8+BRPdE*;PrJ0l}t@Mjh3-XI6FOYMY
zJWVECR9>c0hXo{Cj4JCnIYBlMB&*AeMX%)KFS1Qwy-Zm2&H~FYVv&)YTr1zmBrgL1
D3$ilL

delta 264
zcmZp0XmHrTCcvY`z;DA>!MmB~J&)GLLJ1y?MkiJd-bVJuQfVfo6f6DwywsGU%(7Jd
zl>Fq<+|<01V*T{Yl8n-%$;)JBYdOj^I{SmQPQE=UUIv=Bx80O02iqZ1ONa4

delta 36
scmZ4WpLNxL)(IlacY2>~6n`YaR^a~io4)>JMoEWed&%wgl8o7D05!%A!~g&Q

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf
index 127ff2f..fa48bbd 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf
@@ -1,2922 +1,2922 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:48 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1_SLICE_65I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_B")
-    (INSTANCE RD_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_B")
-    (INSTANCE Dout_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2B")
-    (INSTANCE PHI2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2S) (1250:1250:1250))
-      (WIDTH (negedge PHI2S) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDOB")
-    (INSTANCE UFMSDOI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
-      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDIB")
-    (INSTANCE UFMSDII)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLKB")
-    (INSTANCE UFMCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCSB")
-    (INSTANCE nUFMCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMLB")
-    (INSTANCE RDQMLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMHB")
-    (INSTANCE RDQMHI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCASB")
-    (INSTANCE nRCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRASB")
-    (INSTANCE nRRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWEB")
-    (INSTANCE nRWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKEB")
-    (INSTANCE RCKEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLKB")
-    (INSTANCE RCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLKS) (1250:1250:1250))
-      (WIDTH (negedge RCLKS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCSB")
-    (INSTANCE nRCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_B")
-    (INSTANCE RD_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_B")
-    (INSTANCE RD_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_B")
-    (INSTANCE RD_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_B")
-    (INSTANCE RD_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_B")
-    (INSTANCE RD_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_B")
-    (INSTANCE RD_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_B")
-    (INSTANCE RD_1_I0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_B")
-    (INSTANCE RA_11_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_B")
-    (INSTANCE RA_10_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_B")
-    (INSTANCE RA_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_B")
-    (INSTANCE RA_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_B")
-    (INSTANCE RA_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_B")
-    (INSTANCE RA_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_B")
-    (INSTANCE RA_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_B")
-    (INSTANCE RA_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_B")
-    (INSTANCE RA_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_B")
-    (INSTANCE RA_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_B")
-    (INSTANCE RA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_B")
-    (INSTANCE RA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_B")
-    (INSTANCE RBA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_B")
-    (INSTANCE RBA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LEDB")
-    (INSTANCE LEDI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWEB")
-    (INSTANCE nFWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWES) (1250:1250:1250))
-      (WIDTH (negedge nFWES) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRASB")
-    (INSTANCE nCRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRASS) (1250:1250:1250))
-      (WIDTH (negedge nCRASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCASB")
-    (INSTANCE nCCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCASS) (1250:1250:1250))
-      (WIDTH (negedge nCCASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_B")
-    (INSTANCE Dout_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_B")
-    (INSTANCE Dout_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_B")
-    (INSTANCE Dout_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_B")
-    (INSTANCE Dout_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_B")
-    (INSTANCE Dout_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_B")
-    (INSTANCE Dout_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_B")
-    (INSTANCE Dout_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_B")
-    (INSTANCE Din_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_B")
-    (INSTANCE Din_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_B")
-    (INSTANCE Din_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_B")
-    (INSTANCE Din_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_B")
-    (INSTANCE Din_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_B")
-    (INSTANCE Din_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_B")
-    (INSTANCE Din_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_B")
-    (INSTANCE Din_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_B")
-    (INSTANCE CROW_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_B")
-    (INSTANCE CROW_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_B")
-    (INSTANCE MAin_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_B")
-    (INSTANCE MAin_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_B")
-    (INSTANCE MAin_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_B")
-    (INSTANCE MAin_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_B")
-    (INSTANCE MAin_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_B")
-    (INSTANCE MAin_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_B")
-    (INSTANCE MAin_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_B")
-    (INSTANCE MAin_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_B")
-    (INSTANCE MAin_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_B")
-    (INSTANCE MAin_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_9I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_67I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_90I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/F0 SLICE_9I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/F1 SLICE_9I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 SLICE_9I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 SLICE_14I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/F1 SLICE_9I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/F1 SLICE_20I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_9I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/F0 SLICE_14I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F1 SLICE_43I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F1 SLICE_44I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A1 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F0 SLICE_51I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_51I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F1 SLICE_51I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_52I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_52I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_75I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/F1 SLICE_70I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_76I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_0_I/PADDI SLICE_85I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F1 SLICE_57I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_57I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_85I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F0 SLICE_59I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 SLICE_59I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F1 SLICE_59I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F0 SLICE_62I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F1 SLICE_63I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F1 SLICE_64I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F1 SLICE_68I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F0 SLICE_69I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F0 SLICE_68I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F1 SLICE_69I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F1 SLICE_71I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F1 SLICE_72I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F1 SLICE_77I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F1 SLICE_80I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:57:16 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1_SLICE_65I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_B")
+    (INSTANCE RD_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_B")
+    (INSTANCE Dout_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2B")
+    (INSTANCE PHI2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2S) (1250:1250:1250))
+      (WIDTH (negedge PHI2S) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDOB")
+    (INSTANCE UFMSDOI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
+      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDIB")
+    (INSTANCE UFMSDII)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLKB")
+    (INSTANCE UFMCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCSB")
+    (INSTANCE nUFMCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMLB")
+    (INSTANCE RDQMLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMHB")
+    (INSTANCE RDQMHI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCASB")
+    (INSTANCE nRCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRASB")
+    (INSTANCE nRRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWEB")
+    (INSTANCE nRWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKEB")
+    (INSTANCE RCKEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLKB")
+    (INSTANCE RCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLKS) (1250:1250:1250))
+      (WIDTH (negedge RCLKS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCSB")
+    (INSTANCE nRCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_B")
+    (INSTANCE RD_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_B")
+    (INSTANCE RD_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_B")
+    (INSTANCE RD_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_B")
+    (INSTANCE RD_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_B")
+    (INSTANCE RD_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_B")
+    (INSTANCE RD_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_B")
+    (INSTANCE RD_1_I0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_B")
+    (INSTANCE RA_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_B")
+    (INSTANCE RA_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_B")
+    (INSTANCE RA_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_B")
+    (INSTANCE RA_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_B")
+    (INSTANCE RA_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_B")
+    (INSTANCE RA_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_B")
+    (INSTANCE RA_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_B")
+    (INSTANCE RA_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_B")
+    (INSTANCE RA_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_B")
+    (INSTANCE RA_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_B")
+    (INSTANCE RA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_B")
+    (INSTANCE RA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_B")
+    (INSTANCE RBA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_B")
+    (INSTANCE RBA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LEDB")
+    (INSTANCE LEDI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWEB")
+    (INSTANCE nFWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWES) (1250:1250:1250))
+      (WIDTH (negedge nFWES) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRASB")
+    (INSTANCE nCRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRASS) (1250:1250:1250))
+      (WIDTH (negedge nCRASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCASB")
+    (INSTANCE nCCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCASS) (1250:1250:1250))
+      (WIDTH (negedge nCCASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_B")
+    (INSTANCE Dout_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_B")
+    (INSTANCE Dout_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_B")
+    (INSTANCE Dout_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_B")
+    (INSTANCE Dout_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_B")
+    (INSTANCE Dout_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_B")
+    (INSTANCE Dout_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_B")
+    (INSTANCE Dout_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_B")
+    (INSTANCE Din_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_B")
+    (INSTANCE Din_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_B")
+    (INSTANCE Din_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_B")
+    (INSTANCE Din_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_B")
+    (INSTANCE Din_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_B")
+    (INSTANCE Din_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_B")
+    (INSTANCE Din_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_B")
+    (INSTANCE Din_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_B")
+    (INSTANCE CROW_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_B")
+    (INSTANCE CROW_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_B")
+    (INSTANCE MAin_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_B")
+    (INSTANCE MAin_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_B")
+    (INSTANCE MAin_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_B")
+    (INSTANCE MAin_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_B")
+    (INSTANCE MAin_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_B")
+    (INSTANCE MAin_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_B")
+    (INSTANCE MAin_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_B")
+    (INSTANCE MAin_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_B")
+    (INSTANCE MAin_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_B")
+    (INSTANCE MAin_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_9I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_67I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F1 SLICE_90I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F0 SLICE_9I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F1 SLICE_9I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_9I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_14I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F1 SLICE_9I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F1 SLICE_20I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/F0 SLICE_9I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F0 SLICE_14I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_43I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_44I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90I/F1 SLICE_20I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_21I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_67I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_21I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_67I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_75I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_85I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_21I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_57I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_67I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_78I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F1 SLICE_21I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F1 SLICE_26I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/F0 SLICE_21I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/F1 SLICE_21I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_67I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_82I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/F0 SLICE_22I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_68I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_69I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/F1 SLICE_78I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/F1 SLICE_76I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/F1 SLICE_26I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F1 SLICE_29I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F1 SLICE_61I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_29I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_59I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_61I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_59I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_73I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F1 SLICE_94I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/F0 SLICE_31I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F1 SLICE_32I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/F0 SLICE_32I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_32I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_58I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_64I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F1 SLICE_72I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F0 SLICE_32I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F1 SLICE_87I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_33I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F0 SLICE_39I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_39I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_75I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_78I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_6_I/PADDI SLICE_85I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_39I/F1 SLICE_57I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/F1 SLICE_41I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/F1 SLICE_41I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_43I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_61I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F0 SLICE_62I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F0 SLICE_43I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F0 SLICE_44I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/F0 SLICE_51I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F0 SLICE_51I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F0 SLICE_66I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/F1 SLICE_51I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_52I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_51I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_52I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT nCCASI/PADDI SLICE_88I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_75I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/F1 SLICE_70I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_76I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_0_I/PADDI SLICE_85I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/F1 SLICE_57I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_57I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_1_I/PADDI SLICE_85I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/F0 SLICE_59I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F1 SLICE_59I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/F1 SLICE_59I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F0 SLICE_60I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/F0 SLICE_62I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/F1 SLICE_63I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/F1 SLICE_64I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F0 SLICE_74I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F1 SLICE_66I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F1 SLICE_68I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F0 SLICE_69I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F0 SLICE_68I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84I/F0 SLICE_69I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F1 SLICE_69I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F1 SLICE_71I/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81I/F1 SLICE_72I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77I/F1 SLICE_77I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/F1 SLICE_80I/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho
index c1b6306..10da344 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho
@@ -1,24885 +1,24885 @@
-
--- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
--- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd 
--- Netlist created on Wed Aug 16 04:50:46 2023
--- Netlist written on Wed Aug 16 04:50:48 2023
--- Design is for device LCMXO640C
--- Design is for package TQFP100
--- Design is for performance grade 3
-
--- entity vmuxregsre
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
-
-  end vmuxregsre;
-
-  architecture Structure of vmuxregsre is
-    component FL1P3DX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity vcc
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vcc is
-    port (PWR1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
-
-  end vcc;
-
-  architecture Structure of vcc is
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VHI
-      port map (Z=>PWR1);
-  end Structure;
-
--- entity gnd
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity gnd is
-    port (PWR0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
-
-  end gnd;
-
-  architecture Structure of gnd is
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VLO
-      port map (Z=>PWR0);
-  end Structure;
-
--- entity ccu2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu2B is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
-
-  end ccu2B;
-
-  architecture Structure of ccu2B is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_0
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_0 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_0";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
-
-  end SLICE_0;
-
-  architecture Structure of SLICE_0 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_0: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
-                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20001
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu20001 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
-
-  end ccu20001;
-
-  architecture Structure of ccu20001 is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_1
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_1 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_1";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
-
-  end SLICE_1;
-
-  architecture Structure of SLICE_1 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20001
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_17: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_16: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_16: ccu20001
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
-                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_2 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_2";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
-
-  end SLICE_2;
-
-  architecture Structure of SLICE_2 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_15: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_14: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_14: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
-                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_3
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_3 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_3";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
-
-  end SLICE_3;
-
-  architecture Structure of SLICE_3 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_13: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_12: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_12: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
-                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_4 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_4";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
-
-  end SLICE_4;
-
-  architecture Structure of SLICE_4 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_11: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_10: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_10: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
-                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_5
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_5 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_5";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
-
-  end SLICE_5;
-
-  architecture Structure of SLICE_5 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_9: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_8: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_8: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
-                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_6
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_6 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_6";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
-
-  end SLICE_6;
-
-  architecture Structure of SLICE_6 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_7: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_6: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_6: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
-                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_7
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_7 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_7";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
-
-  end SLICE_7;
-
-  architecture Structure of SLICE_7 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_5: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_4: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_4: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
-                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_8
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_8 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_8";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
-
-  end SLICE_8;
-
-  architecture Structure of SLICE_8 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_2: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
-                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut4 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
-
-  end lut4;
-
-  architecture Structure of lut4 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40002
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40002 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
-
-  end lut40002;
-
-  architecture Structure of lut40002 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00F2")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity inverter
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity inverter is
-    port (I: in Std_logic; Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
-
-  end inverter;
-
-  architecture Structure of inverter is
-    component INV
-      port (A: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    INST1: INV
-      port map (A=>I, Z=>Z);
-  end Structure;
-
--- entity SLICE_9
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_9 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_9";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
-
-  end SLICE_9;
-
-  architecture Structure of SLICE_9 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40002
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    ADSubmitted_r: lut40002
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    ADSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40003
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40003 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
-
-  end lut40003;
-
-  architecture Structure of lut40003 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40004
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40004 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
-
-  end lut40004;
-
-  architecture Structure of lut40004 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_14
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_14 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_14";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
-
-  end SLICE_14;
-
-  architecture Structure of SLICE_14 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40003
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2: lut40003
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1Submitted_RNO: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    C1Submitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40005
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40005 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
-
-  end lut40005;
-
-  architecture Structure of lut40005 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40006
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40006 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
-
-  end lut40006;
-
-  architecture Structure of lut40006 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDDDD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0007
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0007 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
-
-  end vmuxregsre0007;
-
-  architecture Structure of vmuxregsre0007 is
-    component FL1P3IY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3IY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_19
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_19 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_19";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
-
-  end SLICE_19;
-
-  architecture Structure of SLICE_19 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNO_0: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40008
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40008 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
-
-  end lut40008;
-
-  architecture Structure of lut40008 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40009
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40009 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
-
-  end lut40009;
-
-  architecture Structure of lut40009 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAC8C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity selmux2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity selmux2 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
-
-  end selmux2;
-
-  architecture Structure of selmux2 is
-    component MUX21
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    INST1: MUX21
-      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
-  end Structure;
-
--- entity SLICE_20
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_20 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_20";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
-
-  end SLICE_20;
-
-  architecture Structure of SLICE_20 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
-    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40009
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_20_K1: lut40008
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
-                Z=>SLICE_20_SLICE_20_K1_H1);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable_s_GATE: lut40009
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>SLICE_20_CmdEnable_s_GATE_H0);
-    CmdEnable: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    SLICE_20_K0K1MUX: selmux2
-      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40010
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40010 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
-
-  end lut40010;
-
-  architecture Structure of lut40010 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0404")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40011
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40011 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
-
-  end lut40011;
-
-  architecture Structure of lut40011 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0203")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_21
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_21 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_21";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
-
-  end SLICE_21;
-
-  architecture Structure of SLICE_21 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40010
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40011
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_a2_2: lut40010
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_RNO: lut40011
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdLEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40012
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40012 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
-
-  end lut40012;
-
-  architecture Structure of lut40012 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_22
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_22 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_22";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
-
-  end SLICE_22;
-
-  architecture Structure of SLICE_22 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40013
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40013 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
-
-  end lut40013;
-
-  architecture Structure of lut40013 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33AB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40014
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40014 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
-
-  end lut40014;
-
-  architecture Structure of lut40014 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5151")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_26
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_26 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_26";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
-
-  end SLICE_26;
-
-  architecture Structure of SLICE_26 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40014
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_0: lut40013
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_RNO: lut40014
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Cmdn8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40015
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40015 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
-
-  end lut40015;
-
-  architecture Structure of lut40015 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF32")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40016
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40016 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
-
-  end lut40016;
-
-  architecture Structure of lut40016 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA9A9")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_29
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_29 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_29";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
-
-  end SLICE_29;
-
-  architecture Structure of SLICE_29 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i: lut40015
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_0: lut40016
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40017
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40017 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
-
-  end lut40017;
-
-  architecture Structure of lut40017 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7878")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40018
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40018 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
-
-  end lut40018;
-
-  architecture Structure of lut40018 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x6666")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_30
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_30 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_30";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
-
-  end SLICE_30;
-
-  architecture Structure of SLICE_30 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40017
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40018
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_2: lut40017
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_n1_0_x2: lut40018
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    IS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    IS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40019
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40019 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
-
-  end lut40019;
-
-  architecture Structure of lut40019 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFEF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40020
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40020 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
-
-  end lut40020;
-
-  architecture Structure of lut40020 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x6AAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_31
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_31 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_31";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
-
-  end SLICE_31;
-
-  architecture Structure of SLICE_31 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40020
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_RNO: lut40019
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_3: lut40020
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    IS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40021
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40021 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
-
-  end lut40021;
-
-  architecture Structure of lut40021 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4555")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_32
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_32 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_32";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
-
-  end SLICE_32;
-
-  architecture Structure of SLICE_32 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40021
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a0: lut40021
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40022
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40022 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
-
-  end lut40022;
-
-  architecture Structure of lut40022 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFBFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40023
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40023 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
-
-  end lut40023;
-
-  architecture Structure of lut40023 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8B8B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_33
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_33 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_33";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
-
-  end SLICE_33;
-
-  architecture Structure of SLICE_33 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40022
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LED_pad_RNO: lut40022
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    LEDEN_5_i_m2: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    LEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40024
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40024 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
-
-  end lut40024;
-
-  architecture Structure of lut40024 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40025
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40025 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
-
-  end lut40025;
-
-  architecture Structure of lut40025 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xC6C6")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_39
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_39 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_39";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
-
-  end SLICE_39;
-
-  architecture Structure of SLICE_39 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40025
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_0: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RA11_2: lut40025
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RA11: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40026
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40026 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
-
-  end lut40026;
-
-  architecture Structure of lut40026 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x70CF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40027
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40027 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
-
-  end lut40027;
-
-  architecture Structure of lut40027 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCCC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_41
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_41 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_41";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
-
-  end SLICE_41;
-
-  architecture Structure of SLICE_41 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40026
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40027
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_1_0: lut40026
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u: lut40027
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40028
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40028 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
-
-  end lut40028;
-
-  architecture Structure of lut40028 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40029
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40029 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
-
-  end lut40029;
-
-  architecture Structure of lut40029 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFE30")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_42
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_42 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_42";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
-
-  end SLICE_42;
-
-  architecture Structure of SLICE_42 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40029
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_5: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKE_2_0: lut40029
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKE: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40030
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40030 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
-
-  end lut40030;
-
-  architecture Structure of lut40030 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5072")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40031
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40031 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
-
-  end lut40031;
-
-  architecture Structure of lut40031 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAEAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_43
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_43 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_43";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
-
-  end SLICE_43;
-
-  architecture Structure of SLICE_43 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40030
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40031
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_RNO: lut40030
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_RNO: lut40031
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_44
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_44 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_44";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
-
-  end SLICE_44;
-
-  architecture Structure of SLICE_44 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_fast_RNO: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RASr: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Ready_fast: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40032
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40032 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
-
-  end lut40032;
-
-  architecture Structure of lut40032 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0202")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_50
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_50 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_50";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
-
-  end SLICE_50;
-
-  architecture Structure of SLICE_50 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_RNO: lut40032
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0_i_o2_1: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    S_1: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40033
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40033 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
-
-  end lut40033;
-
-  architecture Structure of lut40033 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF2F7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40034
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40034 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
-
-  end lut40034;
-
-  architecture Structure of lut40034 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1032")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_51
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_51 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_51";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
-
-  end SLICE_51;
-
-  architecture Structure of SLICE_51 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40033
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_RNO_0: lut40033
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_RNO: lut40034
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40035
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40035 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
-
-  end lut40035;
-
-  architecture Structure of lut40035 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3B33")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40036
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40036 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
-
-  end lut40036;
-
-  architecture Structure of lut40036 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3210")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_52
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_52 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_52";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
-
-  end SLICE_52;
-
-  architecture Structure of SLICE_52 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40036
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    PHI2r3_RNITCN41: lut40035
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_RNO: lut40036
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMSDI: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40037
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40037 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
-
-  end lut40037;
-
-  architecture Structure of lut40037 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xACAC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_55
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_55 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_55";
-
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
-
-  end SLICE_55;
-
-  architecture Structure of SLICE_55 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_4: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
-      F0_out, Q0_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40038
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40038 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
-
-  end lut40038;
-
-  architecture Structure of lut40038 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40039
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40039 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
-
-  end lut40039;
-
-  architecture Structure of lut40039 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2C2C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_56
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_56 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_56";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
-
-  end SLICE_56;
-
-  architecture Structure of SLICE_56 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40039
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_11: lut40038
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_o2: lut40039
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40040
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40040 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
-
-  end lut40040;
-
-  architecture Structure of lut40040 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF7F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_57
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_57 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_57";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
-
-  end SLICE_57;
-
-  architecture Structure of SLICE_57 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG_3_u_0_a3_3: lut40040
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    XOR8MEG: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40041
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40041 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
-
-  end lut40041;
-
-  architecture Structure of lut40041 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0101")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_58
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_58 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_58";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
-
-  end SLICE_58;
-
-  architecture Structure of SLICE_58 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_en_ss0_0_a2_0: lut40041
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    n8MEGEN_5_i_m2: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    n8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40042
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40042 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
-
-  end lut40042;
-
-  architecture Structure of lut40042 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0BFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40043
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40043 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
-
-  end lut40043;
-
-  architecture Structure of lut40043 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2232")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0044
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0044 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0044 : ENTITY IS TRUE;
-
-  end vmuxregsre0044;
-
-  architecture Structure of vmuxregsre0044 is
-    component FL1P3BX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_59
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_59 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_59";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
-
-  end SLICE_59;
-
-  architecture Structure of SLICE_59 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40042
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40043
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_0: lut40042
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCAS_RNO: lut40043
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCAS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40045
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40045 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
-
-  end lut40045;
-
-  architecture Structure of lut40045 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xE6EE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40046
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40046 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
-
-  end lut40046;
-
-  architecture Structure of lut40046 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3233")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_60
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_60 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_60";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
-
-  end SLICE_60;
-
-  architecture Structure of SLICE_60 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40045
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40046
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_RNO_0: lut40045
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCS_RNO: lut40046
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40047
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40047 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
-
-  end lut40047;
-
-  architecture Structure of lut40047 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5400")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40048
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40048 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
-
-  end lut40048;
-
-  architecture Structure of lut40048 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5051")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_61
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_61 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_61";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
-
-  end SLICE_61;
-
-  architecture Structure of SLICE_61 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40047
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40048
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i_0: lut40047
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRRAS_RNO: lut40048
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRRAS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40049
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40049 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
-
-  end lut40049;
-
-  architecture Structure of lut40049 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40050
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40050 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
-
-  end lut40050;
-
-  architecture Structure of lut40050 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF4F7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_62
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_62 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_62";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
-
-  end SLICE_62;
-
-  architecture Structure of SLICE_62 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40050
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0_sqmuxa_1_0_a3: lut40049
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRWE_RNO: lut40050
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRWE: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40051
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40051 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
-
-  end lut40051;
-
-  architecture Structure of lut40051 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40052
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40052 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
-
-  end lut40052;
-
-  architecture Structure of lut40052 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCEC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_63
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_63 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_63";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
-
-  end SLICE_63;
-
-  architecture Structure of SLICE_63 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40051
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_0_0_a3_0: lut40051
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRowColSel_0_0: lut40052
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRowColSel: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40053
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40053 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
-
-  end lut40053;
-
-  architecture Structure of lut40053 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40054
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40054 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
-
-  end lut40054;
-
-  architecture Structure of lut40054 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_64
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_64 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_64";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
-
-  end SLICE_64;
-
-  architecture Structure of SLICE_64 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0044
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40054
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS15_0_a2: lut40053
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nUFMCS_s_0_N_5_i: lut40054
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nUFMCS: vmuxregsre0044
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40055
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40055 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
-
-  end lut40055;
-
-  architecture Structure of lut40055 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40056
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40056 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
-
-  end lut40056;
-
-  architecture Structure of lut40056 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity nRWE_RNO_1_SLICE_65
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWE_RNO_1_SLICE_65 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          OFX0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
-
-  end nRWE_RNO_1_SLICE_65;
-
-  architecture Structure of nRWE_RNO_1_SLICE_65 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40055
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_1_SLICE_65_K1: lut40055
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
-    nRWE_RNO_1_GATE: lut40056
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
-    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
-      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
-                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
-                Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     7 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     8 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40057
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40057 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
-
-  end lut40057;
-
-  architecture Structure of lut40057 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0B0B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_66
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_66 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_66";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
-
-  end SLICE_66;
-
-  architecture Structure of SLICE_66 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS_s_0_N_5_i_N_2L1: lut40057
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_a2_2_2: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40058
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40058 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
-
-  end lut40058;
-
-  architecture Structure of lut40058 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0059
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0059 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0059 : ENTITY IS TRUE;
-
-  end vmuxregsre0059;
-
-  architecture Structure of vmuxregsre0059 is
-    component FL1P3JY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3JY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_67
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_67 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_67";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
-
-  end SLICE_67;
-
-  architecture Structure of SLICE_67 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK_1_sqmuxa_0_a2: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG18_0_a2: lut40005
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_5: vmuxregsre0059
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_4: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
-      Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40060
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40060 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
-
-  end lut40060;
-
-  architecture Structure of lut40060 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEAAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_68
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_68 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_68";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
-
-  end SLICE_68;
-
-  architecture Structure of SLICE_68 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0_1: lut40053
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_14_i_0: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40061
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40061 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
-
-  end lut40061;
-
-  architecture Structure of lut40061 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0100")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_69
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_69 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_69";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
-
-  end SLICE_69;
-
-  architecture Structure of SLICE_69 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_1: lut40061
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_0: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40062
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40062 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
-
-  end lut40062;
-
-  architecture Structure of lut40062 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8888")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_70
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_70 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_70";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
-
-  end SLICE_70;
-
-  architecture Structure of SLICE_70 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_71
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_71 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_71";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
-
-  end SLICE_71;
-
-  architecture Structure of SLICE_71 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_4: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2_0_10: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40063
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40063 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
-
-  end lut40063;
-
-  architecture Structure of lut40063 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFEFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40064
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40064 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
-
-  end lut40064;
-
-  architecture Structure of lut40064 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAAC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_72
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_72 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_72";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
-
-  end SLICE_72;
-
-  architecture Structure of SLICE_72 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0: lut40063
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_m2: lut40064
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_3: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_2: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40065
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40065 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
-
-  end lut40065;
-
-  architecture Structure of lut40065 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFF7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_73
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_73 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_73";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
-
-  end SLICE_73;
-
-  architecture Structure of SLICE_73 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40065
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0: lut40065
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_0_sqmuxa_0_o2: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdUFMCS: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CmdUFMCLK: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_74
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_74 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_74";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
-
-  end SLICE_74;
-
-  architecture Structure of SLICE_74 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    InitReady3_0_a2_3: lut40062
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady3_0_a2: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdUFMSDI: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40066
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40066 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
-
-  end lut40066;
-
-  architecture Structure of lut40066 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFDFD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_75
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_75 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_75";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
-
-  end SLICE_75;
-
-  architecture Structure of SLICE_75 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40066
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_o2_0: lut40066
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_4_u_i_a2_0: lut40041
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    CASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CASr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40067
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40067 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
-
-  end lut40067;
-
-  architecture Structure of lut40067 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0002")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_76
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_76 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_76";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
-
-  end SLICE_76;
-
-  architecture Structure of SLICE_76 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40067
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_4: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_4_0: lut40067
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40068
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40068 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
-
-  end lut40068;
-
-  architecture Structure of lut40068 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4444")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_77
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_77 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_77";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
-
-  end SLICE_77;
-
-  architecture Structure of SLICE_77 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40068
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_1: lut40068
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_5: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40069
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40069 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
-
-  end lut40069;
-
-  architecture Structure of lut40069 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7777")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_78
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_78 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_78";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
-
-  end SLICE_78;
-
-  architecture Structure of SLICE_78 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_o2: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable17_0_a2_4: lut40058
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CBR_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CBR: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40070
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40070 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
-
-  end lut40070;
-
-  architecture Structure of lut40070 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_79
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_79 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_79";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
-
-  end SLICE_79;
-
-  architecture Structure of SLICE_79 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40070
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_2: lut40070
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_RNO_0: lut40038
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40071
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40071 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
-
-  end lut40071;
-
-  architecture Structure of lut40071 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4101")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_80
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_80 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_80";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
-
-  end SLICE_80;
-
-  architecture Structure of SLICE_80 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40071
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_RNO_1: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRCAS_RNO_0: lut40071
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_9: vmuxregsre0059
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_8: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40072
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40072 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
-
-  end lut40072;
-
-  architecture Structure of lut40072 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_81
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_81 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_81";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
-
-  end SLICE_81;
-
-  architecture Structure of SLICE_81 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0_3: lut40072
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_5: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    FWEr_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    FWEr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40073
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40073 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
-
-  end lut40073;
-
-  architecture Structure of lut40073 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40074
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40074 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
-
-  end lut40074;
-
-  architecture Structure of lut40074 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_82
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_82 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_82";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
-
-  end SLICE_82;
-
-  architecture Structure of SLICE_82 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40073
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40074
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2: lut40073
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_1_sqmuxa_0_a2: lut40074
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr3: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40075
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40075 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
-
-  end lut40075;
-
-  architecture Structure of lut40075 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x7F7F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_83
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_83 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_83";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
-
-  end SLICE_83;
-
-  architecture Structure of SLICE_83 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40075
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_o2: lut40063
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_0_sqmuxa_0_o2: lut40075
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    RBA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RBA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_84
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_84 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_84";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
-
-  end SLICE_84;
-
-  architecture Structure of SLICE_84 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a2_4_2: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_a2_6: lut40061
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40076
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40076 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
-
-  end lut40076;
-
-  architecture Structure of lut40076 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0040")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_85
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_85 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_85";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
-
-  end SLICE_85;
-
-  architecture Structure of SLICE_85 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40076
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2_3: lut40076
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_Din_4: lut40053
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_86
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_86 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_86";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
-
-  end SLICE_86;
-
-  architecture Structure of SLICE_86 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQML: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_9: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40077
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40077 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
-
-  end lut40077;
-
-  architecture Structure of lut40077 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3232")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_87
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_87 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_87";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
-
-  end SLICE_87;
-
-  architecture Structure of SLICE_87 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_RNO_0: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_a2_8: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40078
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40078 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
-
-  end lut40078;
-
-  architecture Structure of lut40078 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0808")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_88
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_88 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_88";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
-
-  end SLICE_88;
-
-  architecture Structure of SLICE_88 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40078
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_3: lut40078
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nCCAS_pad_RNI01SJ: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_7: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_6: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, 
-      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40079
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40079 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
-
-  end lut40079;
-
-  architecture Structure of lut40079 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBBBB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_89
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_89 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_89";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
-
-  end SLICE_89;
-
-  architecture Structure of SLICE_89 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40079
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQMH: lut40079
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_8: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40080
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40080 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
-
-  end lut40080;
-
-  architecture Structure of lut40080 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA8A8")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_90
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_90 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_90";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
-
-  end SLICE_90;
-
-  architecture Structure of SLICE_90 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40080
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_CMDWR: lut40080
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_0: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_91
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_91 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_91";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
-
-  end SLICE_91;
-
-  architecture Structure of SLICE_91 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_7: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_1: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_92
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_92 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_92";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
-
-  end SLICE_92;
-
-  architecture Structure of SLICE_92 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_6: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_2: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_93
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_93 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_93";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
-
-  end SLICE_93;
-
-  architecture Structure of SLICE_93 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_5: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_3: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40081
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40081 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
-
-  end lut40081;
-
-  architecture Structure of lut40081 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1111")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_94
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_94 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_94";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
-
-  end SLICE_94;
-
-  architecture Structure of SLICE_94 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0059
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40081
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN_8_u_0_a2_1_s: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RA10: vmuxregsre0059
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf is
-    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-          PAD: out Std_logic; PADI: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
-
-  end mjiobuf;
-
-  architecture Structure of mjiobuf is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-    component OBW
-      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PADI, O=>Z);
-    INST2: OBW
-      port map (I=>I, T=>T, O=>PAD);
-  end Structure;
-
--- entity RD_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD0 	: VitalDelayType := 0 ns;
-      tpw_RD0_posedge	: VitalDelayType := 0 ns;
-      tpw_RD0_negedge	: VitalDelayType := 0 ns;
-      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD0: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
-
-  end RD_0_B;
-
-  architecture Structure of RD_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD0_ipd 	: std_logic := 'X';
-    signal RD0_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_0: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
-                PADI=>RD0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD0_zd         	: std_logic := 'X';
-    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD0_RD0          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD0_ipd,
-        TestSignalName => "RD0",
-        Period => tperiod_RD0,
-        PulseWidthHigh => tpw_RD0_posedge,
-        PulseWidthLow => tpw_RD0_negedge,
-        PeriodData => periodcheckinfo_RD0,
-        Violation => tviol_RD0_RD0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD0_zd 	:= RD0_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
-                           PathDelay => tpd_RD0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD0,
-                           PathCondition => TRUE)),
-      GlitchData => RD0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0082
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0082 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0082 : ENTITY IS TRUE;
-
-  end mjiobuf0082;
-
-  architecture Structure of mjiobuf0082 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity Dout_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
-
-  end Dout_0_B;
-
-  architecture Structure of Dout_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout0_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_0: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
-    VARIABLE Dout0_zd         	: std_logic := 'X';
-    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout0_zd 	:= Dout0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout0,
-                           PathCondition => TRUE)),
-      GlitchData => Dout0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0083
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0083 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0083 : ENTITY IS TRUE;
-
-  end mjiobuf0083;
-
-  architecture Structure of mjiobuf0083 is
-    component IBPD
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPD
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity PHI2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity PHI2B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2B";
-
-      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_PHI2S 	: VitalDelayType := 0 ns;
-      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
-      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; PHI2S: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
-
-  end PHI2B;
-
-  architecture Structure of PHI2B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PHI2S_ipd 	: std_logic := 'X';
-
-    component mjiobuf0083
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    PHI2_pad: mjiobuf0083
-      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
-    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => PHI2S_ipd,
-        TestSignalName => "PHI2S",
-        Period => tperiod_PHI2S,
-        PulseWidthHigh => tpw_PHI2S_posedge,
-        PulseWidthLow => tpw_PHI2S_negedge,
-        PeriodData => periodcheckinfo_PHI2S,
-        Violation => tviol_PHI2S_PHI2S,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
-                           PathDelay => tpd_PHI2S_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0084
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0084 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0084 : ENTITY IS TRUE;
-
-  end mjiobuf0084;
-
-  architecture Structure of mjiobuf0084 is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity UFMSDOB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDOB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDOB";
-
-      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
-
-  end UFMSDOB;
-
-  architecture Structure of UFMSDOB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal UFMSDOS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    UFMSDO_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
-    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => UFMSDOS_ipd,
-        TestSignalName => "UFMSDOS",
-        Period => tperiod_UFMSDOS,
-        PulseWidthHigh => tpw_UFMSDOS_posedge,
-        PulseWidthLow => tpw_UFMSDOS_negedge,
-        PeriodData => periodcheckinfo_UFMSDOS,
-        Violation => tviol_UFMSDOS_UFMSDOS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
-                           PathDelay => tpd_UFMSDOS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0085
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0085 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0085 : ENTITY IS TRUE;
-
-  end mjiobuf0085;
-
-  architecture Structure of mjiobuf0085 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity UFMSDIB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDIB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDIB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
-
-  end UFMSDIB;
-
-  architecture Structure of UFMSDIB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMSDIS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMSDI_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
-    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
-    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMSDIS_zd 	:= UFMSDIS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMSDIS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMSDIS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLKB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
-
-  end UFMCLKB;
-
-  architecture Structure of UFMCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMCLKS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMCLK_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
-    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
-    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMCLKS_zd 	:= UFMCLKS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMCLKS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMCLKS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nUFMCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nUFMCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
-
-  end nUFMCSB;
-
-  architecture Structure of nUFMCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nUFMCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nUFMCS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
-    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
-    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nUFMCSS_zd 	:= nUFMCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nUFMCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nUFMCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMLB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMLB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMLB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
-
-  end RDQMLB;
-
-  architecture Structure of RDQMLB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMLS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQML_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
-    VARIABLE RDQMLS_zd         	: std_logic := 'X';
-    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMLS_zd 	:= RDQMLS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMLS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMLS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMHB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMHB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMHB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
-
-  end RDQMHB;
-
-  architecture Structure of RDQMHB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMHS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQMH_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
-    VARIABLE RDQMHS_zd         	: std_logic := 'X';
-    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMHS_zd 	:= RDQMHS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMHS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMHS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
-
-  end nRCASB;
-
-  architecture Structure of nRCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCASS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCAS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
-    VARIABLE nRCASS_zd         	: std_logic := 'X';
-    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCASS_zd 	:= nRCASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRRASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
-
-  end nRRASB;
-
-  architecture Structure of nRRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRRASS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRRAS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
-    VARIABLE nRRASS_zd         	: std_logic := 'X';
-    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRRASS_zd 	:= nRRASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRRASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRRASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRWES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
-
-  end nRWEB;
-
-  architecture Structure of nRWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRWES_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRWE_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRWES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
-    VARIABLE nRWES_zd         	: std_logic := 'X';
-    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRWES_zd 	:= nRWES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRWES,
-                           PathCondition => TRUE)),
-      GlitchData => nRWES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCKEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RCKES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
-
-  end RCKEB;
-
-  architecture Structure of RCKEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RCKES_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RCKE_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RCKES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
-    VARIABLE RCKES_zd         	: std_logic := 'X';
-    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RCKES_zd 	:= RCKES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RCKES,
-                           PathCondition => TRUE)),
-      GlitchData => RCKES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCLKB";
-
-      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RCLKS 	: VitalDelayType := 0 ns;
-      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
-      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; RCLKS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
-
-  end RCLKB;
-
-  architecture Structure of RCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal RCLKS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    RCLK_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
-    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RCLKS_ipd,
-        TestSignalName => "RCLKS",
-        Period => tperiod_RCLKS,
-        PulseWidthHigh => tpw_RCLKS_posedge,
-        PulseWidthLow => tpw_RCLKS_negedge,
-        PeriodData => periodcheckinfo_RCLKS,
-        Violation => tviol_RCLKS_RCLKS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
-                           PathDelay => tpd_RCLKS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
-
-  end nRCSB;
-
-  architecture Structure of nRCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCS_pad: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
-    VARIABLE nRCSS_zd         	: std_logic := 'X';
-    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCSS_zd 	:= nRCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD7 	: VitalDelayType := 0 ns;
-      tpw_RD7_posedge	: VitalDelayType := 0 ns;
-      tpw_RD7_negedge	: VitalDelayType := 0 ns;
-      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD7: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
-
-  end RD_7_B;
-
-  architecture Structure of RD_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD7_ipd 	: std_logic := 'X';
-    signal RD7_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_7: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
-                PADI=>RD7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD7_zd         	: std_logic := 'X';
-    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD7_RD7          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD7_ipd,
-        TestSignalName => "RD7",
-        Period => tperiod_RD7,
-        PulseWidthHigh => tpw_RD7_posedge,
-        PulseWidthLow => tpw_RD7_negedge,
-        PeriodData => periodcheckinfo_RD7,
-        Violation => tviol_RD7_RD7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD7_zd 	:= RD7_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
-                           PathDelay => tpd_RD7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD7,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD7,
-                           PathCondition => TRUE)),
-      GlitchData => RD7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD6 	: VitalDelayType := 0 ns;
-      tpw_RD6_posedge	: VitalDelayType := 0 ns;
-      tpw_RD6_negedge	: VitalDelayType := 0 ns;
-      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD6: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
-
-  end RD_6_B;
-
-  architecture Structure of RD_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD6_ipd 	: std_logic := 'X';
-    signal RD6_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_6: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
-                PADI=>RD6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD6_zd         	: std_logic := 'X';
-    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD6_RD6          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD6_ipd,
-        TestSignalName => "RD6",
-        Period => tperiod_RD6,
-        PulseWidthHigh => tpw_RD6_posedge,
-        PulseWidthLow => tpw_RD6_negedge,
-        PeriodData => periodcheckinfo_RD6,
-        Violation => tviol_RD6_RD6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD6_zd 	:= RD6_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
-                           PathDelay => tpd_RD6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD6,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD6,
-                           PathCondition => TRUE)),
-      GlitchData => RD6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD5 	: VitalDelayType := 0 ns;
-      tpw_RD5_posedge	: VitalDelayType := 0 ns;
-      tpw_RD5_negedge	: VitalDelayType := 0 ns;
-      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD5: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
-
-  end RD_5_B;
-
-  architecture Structure of RD_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD5_ipd 	: std_logic := 'X';
-    signal RD5_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_5: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
-                PADI=>RD5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD5_zd         	: std_logic := 'X';
-    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD5_RD5          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD5_ipd,
-        TestSignalName => "RD5",
-        Period => tperiod_RD5,
-        PulseWidthHigh => tpw_RD5_posedge,
-        PulseWidthLow => tpw_RD5_negedge,
-        PeriodData => periodcheckinfo_RD5,
-        Violation => tviol_RD5_RD5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD5_zd 	:= RD5_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
-                           PathDelay => tpd_RD5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD5,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD5,
-                           PathCondition => TRUE)),
-      GlitchData => RD5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD4 	: VitalDelayType := 0 ns;
-      tpw_RD4_posedge	: VitalDelayType := 0 ns;
-      tpw_RD4_negedge	: VitalDelayType := 0 ns;
-      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD4: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
-
-  end RD_4_B;
-
-  architecture Structure of RD_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD4_ipd 	: std_logic := 'X';
-    signal RD4_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_4: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
-                PADI=>RD4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD4_zd         	: std_logic := 'X';
-    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD4_RD4          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD4_ipd,
-        TestSignalName => "RD4",
-        Period => tperiod_RD4,
-        PulseWidthHigh => tpw_RD4_posedge,
-        PulseWidthLow => tpw_RD4_negedge,
-        PeriodData => periodcheckinfo_RD4,
-        Violation => tviol_RD4_RD4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD4_zd 	:= RD4_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
-                           PathDelay => tpd_RD4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD4,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD4,
-                           PathCondition => TRUE)),
-      GlitchData => RD4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD3 	: VitalDelayType := 0 ns;
-      tpw_RD3_posedge	: VitalDelayType := 0 ns;
-      tpw_RD3_negedge	: VitalDelayType := 0 ns;
-      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD3: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
-
-  end RD_3_B;
-
-  architecture Structure of RD_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD3_ipd 	: std_logic := 'X';
-    signal RD3_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_3: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
-                PADI=>RD3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD3_zd         	: std_logic := 'X';
-    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD3_RD3          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD3_ipd,
-        TestSignalName => "RD3",
-        Period => tperiod_RD3,
-        PulseWidthHigh => tpw_RD3_posedge,
-        PulseWidthLow => tpw_RD3_negedge,
-        PeriodData => periodcheckinfo_RD3,
-        Violation => tviol_RD3_RD3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD3_zd 	:= RD3_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
-                           PathDelay => tpd_RD3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD3,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD3,
-                           PathCondition => TRUE)),
-      GlitchData => RD3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD2 	: VitalDelayType := 0 ns;
-      tpw_RD2_posedge	: VitalDelayType := 0 ns;
-      tpw_RD2_negedge	: VitalDelayType := 0 ns;
-      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD2: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
-
-  end RD_2_B;
-
-  architecture Structure of RD_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD2_ipd 	: std_logic := 'X';
-    signal RD2_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_2: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
-                PADI=>RD2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD2_zd         	: std_logic := 'X';
-    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD2_RD2          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD2_ipd,
-        TestSignalName => "RD2",
-        Period => tperiod_RD2,
-        PulseWidthHigh => tpw_RD2_posedge,
-        PulseWidthLow => tpw_RD2_negedge,
-        PeriodData => periodcheckinfo_RD2,
-        Violation => tviol_RD2_RD2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD2_zd 	:= RD2_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
-                           PathDelay => tpd_RD2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD2,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD2,
-                           PathCondition => TRUE)),
-      GlitchData => RD2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD1 	: VitalDelayType := 0 ns;
-      tpw_RD1_posedge	: VitalDelayType := 0 ns;
-      tpw_RD1_negedge	: VitalDelayType := 0 ns;
-      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD1: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
-
-  end RD_1_B;
-
-  architecture Structure of RD_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD1_ipd 	: std_logic := 'X';
-    signal RD1_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_1: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
-                PADI=>RD1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD1_zd         	: std_logic := 'X';
-    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD1_RD1          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD1_ipd,
-        TestSignalName => "RD1",
-        Period => tperiod_RD1,
-        PulseWidthHigh => tpw_RD1_posedge,
-        PulseWidthLow => tpw_RD1_negedge,
-        PeriodData => periodcheckinfo_RD1,
-        Violation => tviol_RD1_RD1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD1_zd 	:= RD1_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
-                           PathDelay => tpd_RD1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD1,
-                           PathCondition => TRUE)),
-      GlitchData => RD1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_11_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA11: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
-
-  end RA_11_B;
-
-  architecture Structure of RA_11_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA11_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_11: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA11_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
-    VARIABLE RA11_zd         	: std_logic := 'X';
-    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA11_zd 	:= RA11_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA11,
-                           PathCondition => TRUE)),
-      GlitchData => RA11_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_10_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_10_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA10: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
-
-  end RA_10_B;
-
-  architecture Structure of RA_10_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA10_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_10: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA10_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
-    VARIABLE RA10_zd         	: std_logic := 'X';
-    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA10_zd 	:= RA10_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA10,
-                           PathCondition => TRUE)),
-      GlitchData => RA10_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_9_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA9: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
-
-  end RA_9_B;
-
-  architecture Structure of RA_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA9_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_9: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA9_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
-    VARIABLE RA9_zd         	: std_logic := 'X';
-    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA9_zd 	:= RA9_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA9,
-                           PathCondition => TRUE)),
-      GlitchData => RA9_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_8_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA8: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
-
-  end RA_8_B;
-
-  architecture Structure of RA_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA8_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_8: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA8_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
-    VARIABLE RA8_zd         	: std_logic := 'X';
-    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA8_zd 	:= RA8_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA8,
-                           PathCondition => TRUE)),
-      GlitchData => RA8_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
-
-  end RA_7_B;
-
-  architecture Structure of RA_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA7_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_7: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
-    VARIABLE RA7_zd         	: std_logic := 'X';
-    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA7_zd 	:= RA7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA7,
-                           PathCondition => TRUE)),
-      GlitchData => RA7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
-
-  end RA_6_B;
-
-  architecture Structure of RA_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA6_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_6: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
-    VARIABLE RA6_zd         	: std_logic := 'X';
-    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA6_zd 	:= RA6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA6,
-                           PathCondition => TRUE)),
-      GlitchData => RA6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
-
-  end RA_5_B;
-
-  architecture Structure of RA_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA5_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_5: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
-    VARIABLE RA5_zd         	: std_logic := 'X';
-    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA5_zd 	:= RA5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA5,
-                           PathCondition => TRUE)),
-      GlitchData => RA5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
-
-  end RA_4_B;
-
-  architecture Structure of RA_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA4_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_4: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
-    VARIABLE RA4_zd         	: std_logic := 'X';
-    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA4_zd 	:= RA4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA4,
-                           PathCondition => TRUE)),
-      GlitchData => RA4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
-
-  end RA_3_B;
-
-  architecture Structure of RA_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA3_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_3: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
-    VARIABLE RA3_zd         	: std_logic := 'X';
-    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA3_zd 	:= RA3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA3,
-                           PathCondition => TRUE)),
-      GlitchData => RA3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
-
-  end RA_2_B;
-
-  architecture Structure of RA_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA2_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_2: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
-    VARIABLE RA2_zd         	: std_logic := 'X';
-    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA2_zd 	:= RA2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA2,
-                           PathCondition => TRUE)),
-      GlitchData => RA2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
-
-  end RA_1_B;
-
-  architecture Structure of RA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA1_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_1: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
-    VARIABLE RA1_zd         	: std_logic := 'X';
-    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA1_zd 	:= RA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA1,
-                           PathCondition => TRUE)),
-      GlitchData => RA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
-
-  end RA_0_B;
-
-  architecture Structure of RA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA0_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_0: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
-    VARIABLE RA0_zd         	: std_logic := 'X';
-    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA0_zd 	:= RA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA0,
-                           PathCondition => TRUE)),
-      GlitchData => RA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
-
-  end RBA_1_B;
-
-  architecture Structure of RBA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA1_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_1: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RBA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
-    VARIABLE RBA1_zd         	: std_logic := 'X';
-    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA1_zd 	:= RBA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA1,
-                           PathCondition => TRUE)),
-      GlitchData => RBA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
-
-  end RBA_0_B;
-
-  architecture Structure of RBA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA0_out 	: std_logic := 'X';
-
-    component mjiobuf0085
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_0: mjiobuf0085
-      port map (I=>PADDO_ipd, PAD=>RBA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
-    VARIABLE RBA0_zd         	: std_logic := 'X';
-    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA0_zd 	:= RBA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA0,
-                           PathCondition => TRUE)),
-      GlitchData => RBA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0086
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0086 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0086 : ENTITY IS TRUE;
-
-  end mjiobuf0086;
-
-  architecture Structure of mjiobuf0086 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity LEDB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity LEDB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "LEDB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; LEDS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
-
-  end LEDB;
-
-  architecture Structure of LEDB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal LEDS_out 	: std_logic := 'X';
-
-    component mjiobuf0086
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    LED_pad: mjiobuf0086
-      port map (I=>PADDO_ipd, PAD=>LEDS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
-    VARIABLE LEDS_zd         	: std_logic := 'X';
-    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    LEDS_zd 	:= LEDS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_LEDS,
-                           PathCondition => TRUE)),
-      GlitchData => LEDS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nFWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nFWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nFWEB";
-
-      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nFWES 	: VitalDelayType := 0 ns;
-      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
-      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nFWES: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
-
-  end nFWEB;
-
-  architecture Structure of nFWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nFWES_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nFWE_pad: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
-    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nFWES_ipd,
-        TestSignalName => "nFWES",
-        Period => tperiod_nFWES,
-        PulseWidthHigh => tpw_nFWES_posedge,
-        PulseWidthLow => tpw_nFWES_negedge,
-        PeriodData => periodcheckinfo_nFWES,
-        Violation => tviol_nFWES_nFWES,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
-                           PathDelay => tpd_nFWES_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0087
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0087 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0087 : ENTITY IS TRUE;
-
-  end mjiobuf0087;
-
-  architecture Structure of mjiobuf0087 is
-    component IBPU
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPU
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity nCRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCRASB";
-
-      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCRASS 	: VitalDelayType := 0 ns;
-      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCRASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
-
-  end nCRASB;
-
-  architecture Structure of nCRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCRASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0087
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCRAS_pad: mjiobuf0087
-      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCRASS_ipd,
-        TestSignalName => "nCRASS",
-        Period => tperiod_nCRASS,
-        PulseWidthHigh => tpw_nCRASS_posedge,
-        PulseWidthLow => tpw_nCRASS_negedge,
-        PeriodData => periodcheckinfo_nCRASS,
-        Violation => tviol_nCRASS_nCRASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
-                           PathDelay => tpd_nCRASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCCASB";
-
-      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCCASS 	: VitalDelayType := 0 ns;
-      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCCASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
-
-  end nCCASB;
-
-  architecture Structure of nCCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCCASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0087
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCCAS_pad: mjiobuf0087
-      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCCASS_ipd,
-        TestSignalName => "nCCASS",
-        Period => tperiod_nCCASS,
-        PulseWidthHigh => tpw_nCCASS_posedge,
-        PulseWidthLow => tpw_nCCASS_negedge,
-        PeriodData => periodcheckinfo_nCCASS,
-        Violation => tviol_nCCASS_nCCASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
-                           PathDelay => tpd_nCCASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
-
-  end Dout_7_B;
-
-  architecture Structure of Dout_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout7_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_7: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
-    VARIABLE Dout7_zd         	: std_logic := 'X';
-    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout7_zd 	:= Dout7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout7,
-                           PathCondition => TRUE)),
-      GlitchData => Dout7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
-
-  end Dout_6_B;
-
-  architecture Structure of Dout_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout6_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_6: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
-    VARIABLE Dout6_zd         	: std_logic := 'X';
-    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout6_zd 	:= Dout6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout6,
-                           PathCondition => TRUE)),
-      GlitchData => Dout6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
-
-  end Dout_5_B;
-
-  architecture Structure of Dout_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout5_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_5: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
-    VARIABLE Dout5_zd         	: std_logic := 'X';
-    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout5_zd 	:= Dout5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout5,
-                           PathCondition => TRUE)),
-      GlitchData => Dout5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
-
-  end Dout_4_B;
-
-  architecture Structure of Dout_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout4_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_4: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
-    VARIABLE Dout4_zd         	: std_logic := 'X';
-    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout4_zd 	:= Dout4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout4,
-                           PathCondition => TRUE)),
-      GlitchData => Dout4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
-
-  end Dout_3_B;
-
-  architecture Structure of Dout_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout3_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_3: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
-    VARIABLE Dout3_zd         	: std_logic := 'X';
-    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout3_zd 	:= Dout3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout3,
-                           PathCondition => TRUE)),
-      GlitchData => Dout3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
-
-  end Dout_2_B;
-
-  architecture Structure of Dout_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout2_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_2: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
-    VARIABLE Dout2_zd         	: std_logic := 'X';
-    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout2_zd 	:= Dout2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout2,
-                           PathCondition => TRUE)),
-      GlitchData => Dout2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
-
-  end Dout_1_B;
-
-  architecture Structure of Dout_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout1_out 	: std_logic := 'X';
-
-    component mjiobuf0082
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_1: mjiobuf0082
-      port map (I=>PADDO_ipd, PAD=>Dout1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
-    VARIABLE Dout1_zd         	: std_logic := 'X';
-    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout1_zd 	:= Dout1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout1,
-                           PathCondition => TRUE)),
-      GlitchData => Dout1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_B";
-
-      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din7 	: VitalDelayType := 0 ns;
-      tpw_Din7_posedge	: VitalDelayType := 0 ns;
-      tpw_Din7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
-
-  end Din_7_B;
-
-  architecture Structure of Din_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_7: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din7_Din7          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din7_ipd,
-        TestSignalName => "Din7",
-        Period => tperiod_Din7,
-        PulseWidthHigh => tpw_Din7_posedge,
-        PulseWidthLow => tpw_Din7_negedge,
-        PeriodData => periodcheckinfo_Din7,
-        Violation => tviol_Din7_Din7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
-                           PathDelay => tpd_Din7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_B";
-
-      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din6 	: VitalDelayType := 0 ns;
-      tpw_Din6_posedge	: VitalDelayType := 0 ns;
-      tpw_Din6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
-
-  end Din_6_B;
-
-  architecture Structure of Din_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_6: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din6_Din6          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din6_ipd,
-        TestSignalName => "Din6",
-        Period => tperiod_Din6,
-        PulseWidthHigh => tpw_Din6_posedge,
-        PulseWidthLow => tpw_Din6_negedge,
-        PeriodData => periodcheckinfo_Din6,
-        Violation => tviol_Din6_Din6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
-                           PathDelay => tpd_Din6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_B";
-
-      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din5 	: VitalDelayType := 0 ns;
-      tpw_Din5_posedge	: VitalDelayType := 0 ns;
-      tpw_Din5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
-
-  end Din_5_B;
-
-  architecture Structure of Din_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_5: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din5_Din5          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din5_ipd,
-        TestSignalName => "Din5",
-        Period => tperiod_Din5,
-        PulseWidthHigh => tpw_Din5_posedge,
-        PulseWidthLow => tpw_Din5_negedge,
-        PeriodData => periodcheckinfo_Din5,
-        Violation => tviol_Din5_Din5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
-                           PathDelay => tpd_Din5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_B";
-
-      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din4 	: VitalDelayType := 0 ns;
-      tpw_Din4_posedge	: VitalDelayType := 0 ns;
-      tpw_Din4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
-
-  end Din_4_B;
-
-  architecture Structure of Din_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_4: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din4_Din4          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din4_ipd,
-        TestSignalName => "Din4",
-        Period => tperiod_Din4,
-        PulseWidthHigh => tpw_Din4_posedge,
-        PulseWidthLow => tpw_Din4_negedge,
-        PeriodData => periodcheckinfo_Din4,
-        Violation => tviol_Din4_Din4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
-                           PathDelay => tpd_Din4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_B";
-
-      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din3 	: VitalDelayType := 0 ns;
-      tpw_Din3_posedge	: VitalDelayType := 0 ns;
-      tpw_Din3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
-
-  end Din_3_B;
-
-  architecture Structure of Din_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_3: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din3_Din3          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din3_ipd,
-        TestSignalName => "Din3",
-        Period => tperiod_Din3,
-        PulseWidthHigh => tpw_Din3_posedge,
-        PulseWidthLow => tpw_Din3_negedge,
-        PeriodData => periodcheckinfo_Din3,
-        Violation => tviol_Din3_Din3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
-                           PathDelay => tpd_Din3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_B";
-
-      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din2 	: VitalDelayType := 0 ns;
-      tpw_Din2_posedge	: VitalDelayType := 0 ns;
-      tpw_Din2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
-
-  end Din_2_B;
-
-  architecture Structure of Din_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_2: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din2_Din2          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din2_ipd,
-        TestSignalName => "Din2",
-        Period => tperiod_Din2,
-        PulseWidthHigh => tpw_Din2_posedge,
-        PulseWidthLow => tpw_Din2_negedge,
-        PeriodData => periodcheckinfo_Din2,
-        Violation => tviol_Din2_Din2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
-                           PathDelay => tpd_Din2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_B";
-
-      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din1 	: VitalDelayType := 0 ns;
-      tpw_Din1_posedge	: VitalDelayType := 0 ns;
-      tpw_Din1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
-
-  end Din_1_B;
-
-  architecture Structure of Din_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din1_Din1          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din1_ipd,
-        TestSignalName => "Din1",
-        Period => tperiod_Din1,
-        PulseWidthHigh => tpw_Din1_posedge,
-        PulseWidthLow => tpw_Din1_negedge,
-        PeriodData => periodcheckinfo_Din1,
-        Violation => tviol_Din1_Din1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
-                           PathDelay => tpd_Din1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_B";
-
-      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din0 	: VitalDelayType := 0 ns;
-      tpw_Din0_posedge	: VitalDelayType := 0 ns;
-      tpw_Din0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
-
-  end Din_0_B;
-
-  architecture Structure of Din_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>Din0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din0_Din0          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din0_ipd,
-        TestSignalName => "Din0",
-        Period => tperiod_Din0,
-        PulseWidthHigh => tpw_Din0_posedge,
-        PulseWidthLow => tpw_Din0_negedge,
-        PeriodData => periodcheckinfo_Din0,
-        Violation => tviol_Din0_Din0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
-                           PathDelay => tpd_Din0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_1_B";
-
-      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW1 	: VitalDelayType := 0 ns;
-      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
-
-  end CROW_1_B;
-
-  architecture Structure of CROW_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW1_ipd,
-        TestSignalName => "CROW1",
-        Period => tperiod_CROW1,
-        PulseWidthHigh => tpw_CROW1_posedge,
-        PulseWidthLow => tpw_CROW1_negedge,
-        PeriodData => periodcheckinfo_CROW1,
-        Violation => tviol_CROW1_CROW1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
-                           PathDelay => tpd_CROW1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_0_B";
-
-      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW0 	: VitalDelayType := 0 ns;
-      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
-
-  end CROW_0_B;
-
-  architecture Structure of CROW_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW0_ipd,
-        TestSignalName => "CROW0",
-        Period => tperiod_CROW0,
-        PulseWidthHigh => tpw_CROW0_posedge,
-        PulseWidthLow => tpw_CROW0_negedge,
-        PeriodData => periodcheckinfo_CROW0,
-        Violation => tviol_CROW0_CROW0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
-                           PathDelay => tpd_CROW0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_9_B";
-
-      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin9 	: VitalDelayType := 0 ns;
-      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin9: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
-
-  end MAin_9_B;
-
-  architecture Structure of MAin_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin9_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_9: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin9_ipd,
-        TestSignalName => "MAin9",
-        Period => tperiod_MAin9,
-        PulseWidthHigh => tpw_MAin9_posedge,
-        PulseWidthLow => tpw_MAin9_negedge,
-        PeriodData => periodcheckinfo_MAin9,
-        Violation => tviol_MAin9_MAin9,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
-                           PathDelay => tpd_MAin9_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_8_B";
-
-      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin8 	: VitalDelayType := 0 ns;
-      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin8: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
-
-  end MAin_8_B;
-
-  architecture Structure of MAin_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin8_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_8: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin8_ipd,
-        TestSignalName => "MAin8",
-        Period => tperiod_MAin8,
-        PulseWidthHigh => tpw_MAin8_posedge,
-        PulseWidthLow => tpw_MAin8_negedge,
-        PeriodData => periodcheckinfo_MAin8,
-        Violation => tviol_MAin8_MAin8,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
-                           PathDelay => tpd_MAin8_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_7_B";
-
-      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin7 	: VitalDelayType := 0 ns;
-      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
-
-  end MAin_7_B;
-
-  architecture Structure of MAin_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_7: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin7_ipd,
-        TestSignalName => "MAin7",
-        Period => tperiod_MAin7,
-        PulseWidthHigh => tpw_MAin7_posedge,
-        PulseWidthLow => tpw_MAin7_negedge,
-        PeriodData => periodcheckinfo_MAin7,
-        Violation => tviol_MAin7_MAin7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
-                           PathDelay => tpd_MAin7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_6_B";
-
-      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin6 	: VitalDelayType := 0 ns;
-      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
-
-  end MAin_6_B;
-
-  architecture Structure of MAin_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_6: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin6_ipd,
-        TestSignalName => "MAin6",
-        Period => tperiod_MAin6,
-        PulseWidthHigh => tpw_MAin6_posedge,
-        PulseWidthLow => tpw_MAin6_negedge,
-        PeriodData => periodcheckinfo_MAin6,
-        Violation => tviol_MAin6_MAin6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
-                           PathDelay => tpd_MAin6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_5_B";
-
-      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin5 	: VitalDelayType := 0 ns;
-      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
-
-  end MAin_5_B;
-
-  architecture Structure of MAin_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_5: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin5_ipd,
-        TestSignalName => "MAin5",
-        Period => tperiod_MAin5,
-        PulseWidthHigh => tpw_MAin5_posedge,
-        PulseWidthLow => tpw_MAin5_negedge,
-        PeriodData => periodcheckinfo_MAin5,
-        Violation => tviol_MAin5_MAin5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
-                           PathDelay => tpd_MAin5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_4_B";
-
-      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin4 	: VitalDelayType := 0 ns;
-      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
-
-  end MAin_4_B;
-
-  architecture Structure of MAin_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_4: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin4_ipd,
-        TestSignalName => "MAin4",
-        Period => tperiod_MAin4,
-        PulseWidthHigh => tpw_MAin4_posedge,
-        PulseWidthLow => tpw_MAin4_negedge,
-        PeriodData => periodcheckinfo_MAin4,
-        Violation => tviol_MAin4_MAin4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
-                           PathDelay => tpd_MAin4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_3_B";
-
-      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin3 	: VitalDelayType := 0 ns;
-      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
-
-  end MAin_3_B;
-
-  architecture Structure of MAin_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_3: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin3_ipd,
-        TestSignalName => "MAin3",
-        Period => tperiod_MAin3,
-        PulseWidthHigh => tpw_MAin3_posedge,
-        PulseWidthLow => tpw_MAin3_negedge,
-        PeriodData => periodcheckinfo_MAin3,
-        Violation => tviol_MAin3_MAin3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
-                           PathDelay => tpd_MAin3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_2_B";
-
-      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin2 	: VitalDelayType := 0 ns;
-      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
-
-  end MAin_2_B;
-
-  architecture Structure of MAin_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_2: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin2_ipd,
-        TestSignalName => "MAin2",
-        Period => tperiod_MAin2,
-        PulseWidthHigh => tpw_MAin2_posedge,
-        PulseWidthLow => tpw_MAin2_negedge,
-        PeriodData => periodcheckinfo_MAin2,
-        Violation => tviol_MAin2_MAin2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
-                           PathDelay => tpd_MAin2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_1_B";
-
-      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin1 	: VitalDelayType := 0 ns;
-      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
-
-  end MAin_1_B;
-
-  architecture Structure of MAin_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_1: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin1_ipd,
-        TestSignalName => "MAin1",
-        Period => tperiod_MAin1,
-        PulseWidthHigh => tpw_MAin1_posedge,
-        PulseWidthLow => tpw_MAin1_negedge,
-        PeriodData => periodcheckinfo_MAin1,
-        Violation => tviol_MAin1_MAin1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
-                           PathDelay => tpd_MAin1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_0_B";
-
-      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin0 	: VitalDelayType := 0 ns;
-      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
-
-  end MAin_0_B;
-
-  architecture Structure of MAin_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0084
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_0: mjiobuf0084
-      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin0_ipd,
-        TestSignalName => "MAin0",
-        Period => tperiod_MAin0,
-        PulseWidthHigh => tpw_MAin0_posedge,
-        PulseWidthLow => tpw_MAin0_negedge,
-        PeriodData => periodcheckinfo_MAin0,
-        Violation => tviol_MAin0_MAin0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
-                           PathDelay => tpd_MAin0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RAM2GS
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RAM2GS is
-    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
-          CROW: in Std_logic_vector (1 downto 0); 
-          Din: in Std_logic_vector (7 downto 0); 
-          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
-          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
-          RBA: out Std_logic_vector (1 downto 0); 
-          RA: out Std_logic_vector (11 downto 0); 
-          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
-          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
-          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
-          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
-          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
-
-
-
-  end RAM2GS;
-
-  architecture Structure of RAM2GS is
-    signal FS_1: Std_logic;
-    signal FS_0: Std_logic;
-    signal RCLK_c: Std_logic;
-    signal FS_cry_1: Std_logic;
-    signal FS_17: Std_logic;
-    signal FS_16: Std_logic;
-    signal FS_cry_15: Std_logic;
-    signal FS_15: Std_logic;
-    signal FS_14: Std_logic;
-    signal FS_cry_13: Std_logic;
-    signal FS_13: Std_logic;
-    signal FS_12: Std_logic;
-    signal FS_cry_11: Std_logic;
-    signal FS_11: Std_logic;
-    signal FS_10: Std_logic;
-    signal FS_cry_9: Std_logic;
-    signal FS_9: Std_logic;
-    signal FS_8: Std_logic;
-    signal FS_cry_7: Std_logic;
-    signal FS_7: Std_logic;
-    signal FS_6: Std_logic;
-    signal FS_cry_5: Std_logic;
-    signal FS_5: Std_logic;
-    signal FS_4: Std_logic;
-    signal FS_cry_3: Std_logic;
-    signal FS_3: Std_logic;
-    signal FS_2: Std_logic;
-    signal N_147: Std_logic;
-    signal MAin_c_0: Std_logic;
-    signal CmdEnable17_0_a2_4: Std_logic;
-    signal CmdEnable17_0_a2_3: Std_logic;
-    signal CmdEnable16: Std_logic;
-    signal CmdEnable17: Std_logic;
-    signal C1WR_0_a2: Std_logic;
-    signal ADSubmitted: Std_logic;
-    signal ADSubmitted_r: Std_logic;
-    signal PHI2_c: Std_logic;
-    signal CmdEnable16_0_a2_5: Std_logic;
-    signal CmdEnable16_0_a2_4: Std_logic;
-    signal MAin_c_1: Std_logic;
-    signal C1Submitted: Std_logic;
-    signal C1Submitted_RNO: Std_logic;
-    signal S_1: Std_logic;
-    signal RASr2: Std_logic;
-    signal IS_3: Std_logic;
-    signal CO0: Std_logic;
-    signal N_177_i: Std_logic;
-    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
-    signal CmdEnable: Std_logic;
-    signal un1_CMDWR: Std_logic;
-    signal CmdEnable_s: Std_logic;
-    signal N_128: Std_logic;
-    signal Din_c_5: Std_logic;
-    signal Din_c_3: Std_logic;
-    signal N_152: Std_logic;
-    signal N_133: Std_logic;
-    signal N_132: Std_logic;
-    signal LEDEN: Std_logic;
-    signal N_21_i: Std_logic;
-    signal XOR8MEG18: Std_logic;
-    signal CmdLEDEN: Std_logic;
-    signal PHI2r3: Std_logic;
-    signal PHI2r2: Std_logic;
-    signal InitReady: Std_logic;
-    signal CmdSubmitted: Std_logic;
-    signal CmdSubmitted_1_sqmuxa: Std_logic;
-    signal N_460_0: Std_logic;
-    signal N_136: Std_logic;
-    signal N_43: Std_logic;
-    signal Cmdn8MEGEN: Std_logic;
-    signal CmdEnable16_4: Std_logic;
-    signal n8MEGEN: Std_logic;
-    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
-    signal N_19_i: Std_logic;
-    signal nRRAS_5_u_i_0: Std_logic;
-    signal N_160: Std_logic;
-    signal N_155: Std_logic;
-    signal IS_0: Std_logic;
-    signal Ready: Std_logic;
-    signal N_64_i_i: Std_logic;
-    signal N_24: Std_logic;
-    signal IS_2: Std_logic;
-    signal IS_1: Std_logic;
-    signal N_60_i_i: Std_logic;
-    signal N_56_i: Std_logic;
-    signal N_159_i: Std_logic;
-    signal N_159: Std_logic;
-    signal N_61_i_i: Std_logic;
-    signal RA10s_i: Std_logic;
-    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
-    signal N_126: Std_logic;
-    signal N_51: Std_logic;
-    signal InitReady3: Std_logic;
-    signal N_461_0: Std_logic;
-    signal UFMSDI_ens2_i_a0: Std_logic;
-    signal nCRAS_c: Std_logic;
-    signal CBR: Std_logic;
-    signal UFMSDO_c: Std_logic;
-    signal N_70: Std_logic;
-    signal N_33: Std_logic;
-    signal LED_c: Std_logic;
-    signal un1_Din_4: Std_logic;
-    signal XOR8MEG: Std_logic;
-    signal Din_c_6: Std_logic;
-    signal RA11_2: Std_logic;
-    signal Ready_fast: Std_logic;
-    signal RA_c_11: Std_logic;
-    signal N_171: Std_logic;
-    signal FWEr_fast: Std_logic;
-    signal CASr2: Std_logic;
-    signal RCKEEN_8_u_1: Std_logic;
-    signal RCKEEN_8_u_0_0: Std_logic;
-    signal RCKEEN_8: Std_logic;
-    signal PHI2r: Std_logic;
-    signal RCKEEN: Std_logic;
-    signal RASr3: Std_logic;
-    signal RASr: Std_logic;
-    signal RCKE_2: Std_logic;
-    signal RCKE_c: Std_logic;
-    signal m18_0_a3_3: Std_logic;
-    signal S_0_i_o2_1: Std_logic;
-    signal N_165: Std_logic;
-    signal N_462_0: Std_logic;
-    signal Ready_0_sqmuxa: Std_logic;
-    signal N_463_0: Std_logic;
-    signal nRRAS_0_sqmuxa: Std_logic;
-    signal N_129: Std_logic;
-    signal UFMCLK_r_i_a2_2_2: Std_logic;
-    signal CmdUFMCLK: Std_logic;
-    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
-    signal UFMCLK_c: Std_logic;
-    signal nUFMCS15: Std_logic;
-    signal N_139_i: Std_logic;
-    signal UFMCLK_RNO: Std_logic;
-    signal UFMSDI_r_xx_mm_1: Std_logic;
-    signal UFMSDI_c: Std_logic;
-    signal UFMSDI_RNO: Std_logic;
-    signal nRowColSel: Std_logic;
-    signal RowA_4: Std_logic;
-    signal MAin_c_4: Std_logic;
-    signal Din_c_4: Std_logic;
-    signal nCCAS_c: Std_logic;
-    signal RA_c_4: Std_logic;
-    signal WRD_4: Std_logic;
-    signal WRD_5: Std_logic;
-    signal Bank_7: Std_logic;
-    signal Bank_6: Std_logic;
-    signal Bank_5: Std_logic;
-    signal Bank_2: Std_logic;
-    signal Din_c_7: Std_logic;
-    signal WRD_6: Std_logic;
-    signal C1WR_0_a2_0_11: Std_logic;
-    signal WRD_7: Std_logic;
-    signal Din_c_2: Std_logic;
-    signal Din_c_0: Std_logic;
-    signal XOR8MEG_3_u_0_a3_2: Std_logic;
-    signal Din_c_1: Std_logic;
-    signal XOR8MEG_3: Std_logic;
-    signal N_69: Std_logic;
-    signal N_31: Std_logic;
-    signal N_151: Std_logic;
-    signal g0_1: Std_logic;
-    signal nRCAS_0_sqmuxa_1: Std_logic;
-    signal N_41: Std_logic;
-    signal N_37_i: Std_logic;
-    signal nRCAS_c: Std_logic;
-    signal CASr3: Std_logic;
-    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
-    signal N_28_i_1: Std_logic;
-    signal N_28_i: Std_logic;
-    signal nRCS_c: Std_logic;
-    signal N_24_i: Std_logic;
-    signal nRRAS_c: Std_logic;
-    signal CBR_fast: Std_logic;
-    signal m18_0_a2_1: Std_logic;
-    signal G_17_1: Std_logic;
-    signal FWEr: Std_logic;
-    signal N_39_i: Std_logic;
-    signal nRWE_c: Std_logic;
-    signal N_179: Std_logic;
-    signal nRowColSel_0_0: Std_logic;
-    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
-    signal nUFMCS_c: Std_logic;
-    signal nUFMCS_s_0_N_5_i: Std_logic;
-    signal CmdUFMCS: Std_logic;
-    signal N_95_5: Std_logic;
-    signal N_95_3: Std_logic;
-    signal RowA_0: Std_logic;
-    signal RowA_1: Std_logic;
-    signal MAin_c_5: Std_logic;
-    signal CmdUFMCLK_1_sqmuxa: Std_logic;
-    signal RowA_5: Std_logic;
-    signal un1_FS_14_i_a2_0_1: Std_logic;
-    signal N_137_8: Std_logic;
-    signal N_137_6: Std_logic;
-    signal un1_FS_13_i_a2_1: Std_logic;
-    signal C1WR_0_a2_0_10: Std_logic;
-    signal Bank_1: Std_logic;
-    signal Bank_0: Std_logic;
-    signal MAin_c_7: Std_logic;
-    signal MAin_c_6: Std_logic;
-    signal C1WR_0_a2_0_4: Std_logic;
-    signal C1WR_0_a2_0_3: Std_logic;
-    signal Bank_4: Std_logic;
-    signal Bank_3: Std_logic;
-    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
-    signal MAin_c_3: Std_logic;
-    signal MAin_c_2: Std_logic;
-    signal RowA_2: Std_logic;
-    signal RowA_3: Std_logic;
-    signal CmdUFMSDI: Std_logic;
-    signal CASr: Std_logic;
-    signal CmdEnable16_1: Std_logic;
-    signal m6_0_a2_2: Std_logic;
-    signal WRD_0: Std_logic;
-    signal WRD_1: Std_logic;
-    signal g4_0_0_0: Std_logic;
-    signal MAin_c_9: Std_logic;
-    signal MAin_c_8: Std_logic;
-    signal RowA_8: Std_logic;
-    signal RowA_9: Std_logic;
-    signal nFWE_c: Std_logic;
-    signal CROW_c_1: Std_logic;
-    signal CROW_c_0: Std_logic;
-    signal RBA_c_0: Std_logic;
-    signal RBA_c_1: Std_logic;
-    signal WRD_2: Std_logic;
-    signal WRD_3: Std_logic;
-    signal RA_c_9: Std_logic;
-    signal RDQML_c: Std_logic;
-    signal RD_1_i: Std_logic;
-    signal RowA_6: Std_logic;
-    signal RowA_7: Std_logic;
-    signal RA_c_8: Std_logic;
-    signal RDQMH_c: Std_logic;
-    signal RA_c_0: Std_logic;
-    signal RA_c_1: Std_logic;
-    signal RA_c_7: Std_logic;
-    signal RA_c_2: Std_logic;
-    signal RA_c_6: Std_logic;
-    signal RA_c_3: Std_logic;
-    signal RA_c_5: Std_logic;
-    signal RA_c_10: Std_logic;
-    signal RD_in_0: Std_logic;
-    signal RD_in_7: Std_logic;
-    signal RD_in_6: Std_logic;
-    signal RD_in_5: Std_logic;
-    signal RD_in_4: Std_logic;
-    signal RD_in_3: Std_logic;
-    signal RD_in_2: Std_logic;
-    signal RD_in_1: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI_TSALL: Std_logic;
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-    component PUR
-      port (PUR: in Std_logic);
-    end component;
-    component GSR
-      port (GSR: in Std_logic);
-    end component;
-    component TSALL
-      port (TSALL: in Std_logic);
-    end component;
-    component SLICE_0
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_1
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_2
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_3
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_4
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_5
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_6
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_7
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_8
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_9
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_14
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_19
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_20
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_21
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_22
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_26
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_29
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_30
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_31
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_32
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_33
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_39
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_41
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_42
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_43
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_44
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_50
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_51
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_52
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_55
-      port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_56
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_57
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_58
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_59
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_60
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_61
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_62
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_63
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_64
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component nRWE_RNO_1_SLICE_65
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            OFX0: out Std_logic);
-    end component;
-    component SLICE_66
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_67
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_68
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_69
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_70
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_71
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_72
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_73
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_74
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_75
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_76
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_77
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_78
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_79
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_80
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_81
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_82
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_83
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_84
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_85
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_86
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_87
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_88
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_89
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_90
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_91
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_92
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_93
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_94
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component RD_0_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD0: inout Std_logic);
-    end component;
-    component Dout_0_B
-      port (PADDO: in Std_logic; Dout0: out Std_logic);
-    end component;
-    component PHI2B
-      port (PADDI: out Std_logic; PHI2S: in Std_logic);
-    end component;
-    component UFMSDOB
-      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-    end component;
-    component UFMSDIB
-      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-    end component;
-    component UFMCLKB
-      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-    end component;
-    component nUFMCSB
-      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-    end component;
-    component RDQMLB
-      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-    end component;
-    component RDQMHB
-      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-    end component;
-    component nRCASB
-      port (PADDO: in Std_logic; nRCASS: out Std_logic);
-    end component;
-    component nRRASB
-      port (PADDO: in Std_logic; nRRASS: out Std_logic);
-    end component;
-    component nRWEB
-      port (PADDO: in Std_logic; nRWES: out Std_logic);
-    end component;
-    component RCKEB
-      port (PADDO: in Std_logic; RCKES: out Std_logic);
-    end component;
-    component RCLKB
-      port (PADDI: out Std_logic; RCLKS: in Std_logic);
-    end component;
-    component nRCSB
-      port (PADDO: in Std_logic; nRCSS: out Std_logic);
-    end component;
-    component RD_7_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD7: inout Std_logic);
-    end component;
-    component RD_6_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD6: inout Std_logic);
-    end component;
-    component RD_5_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD5: inout Std_logic);
-    end component;
-    component RD_4_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD4: inout Std_logic);
-    end component;
-    component RD_3_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD3: inout Std_logic);
-    end component;
-    component RD_2_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD2: inout Std_logic);
-    end component;
-    component RD_1_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD1: inout Std_logic);
-    end component;
-    component RA_11_B
-      port (PADDO: in Std_logic; RA11: out Std_logic);
-    end component;
-    component RA_10_B
-      port (PADDO: in Std_logic; RA10: out Std_logic);
-    end component;
-    component RA_9_B
-      port (PADDO: in Std_logic; RA9: out Std_logic);
-    end component;
-    component RA_8_B
-      port (PADDO: in Std_logic; RA8: out Std_logic);
-    end component;
-    component RA_7_B
-      port (PADDO: in Std_logic; RA7: out Std_logic);
-    end component;
-    component RA_6_B
-      port (PADDO: in Std_logic; RA6: out Std_logic);
-    end component;
-    component RA_5_B
-      port (PADDO: in Std_logic; RA5: out Std_logic);
-    end component;
-    component RA_4_B
-      port (PADDO: in Std_logic; RA4: out Std_logic);
-    end component;
-    component RA_3_B
-      port (PADDO: in Std_logic; RA3: out Std_logic);
-    end component;
-    component RA_2_B
-      port (PADDO: in Std_logic; RA2: out Std_logic);
-    end component;
-    component RA_1_B
-      port (PADDO: in Std_logic; RA1: out Std_logic);
-    end component;
-    component RA_0_B
-      port (PADDO: in Std_logic; RA0: out Std_logic);
-    end component;
-    component RBA_1_B
-      port (PADDO: in Std_logic; RBA1: out Std_logic);
-    end component;
-    component RBA_0_B
-      port (PADDO: in Std_logic; RBA0: out Std_logic);
-    end component;
-    component LEDB
-      port (PADDO: in Std_logic; LEDS: out Std_logic);
-    end component;
-    component nFWEB
-      port (PADDI: out Std_logic; nFWES: in Std_logic);
-    end component;
-    component nCRASB
-      port (PADDI: out Std_logic; nCRASS: in Std_logic);
-    end component;
-    component nCCASB
-      port (PADDI: out Std_logic; nCCASS: in Std_logic);
-    end component;
-    component Dout_7_B
-      port (PADDO: in Std_logic; Dout7: out Std_logic);
-    end component;
-    component Dout_6_B
-      port (PADDO: in Std_logic; Dout6: out Std_logic);
-    end component;
-    component Dout_5_B
-      port (PADDO: in Std_logic; Dout5: out Std_logic);
-    end component;
-    component Dout_4_B
-      port (PADDO: in Std_logic; Dout4: out Std_logic);
-    end component;
-    component Dout_3_B
-      port (PADDO: in Std_logic; Dout3: out Std_logic);
-    end component;
-    component Dout_2_B
-      port (PADDO: in Std_logic; Dout2: out Std_logic);
-    end component;
-    component Dout_1_B
-      port (PADDO: in Std_logic; Dout1: out Std_logic);
-    end component;
-    component Din_7_B
-      port (PADDI: out Std_logic; Din7: in Std_logic);
-    end component;
-    component Din_6_B
-      port (PADDI: out Std_logic; Din6: in Std_logic);
-    end component;
-    component Din_5_B
-      port (PADDI: out Std_logic; Din5: in Std_logic);
-    end component;
-    component Din_4_B
-      port (PADDI: out Std_logic; Din4: in Std_logic);
-    end component;
-    component Din_3_B
-      port (PADDI: out Std_logic; Din3: in Std_logic);
-    end component;
-    component Din_2_B
-      port (PADDI: out Std_logic; Din2: in Std_logic);
-    end component;
-    component Din_1_B
-      port (PADDI: out Std_logic; Din1: in Std_logic);
-    end component;
-    component Din_0_B
-      port (PADDI: out Std_logic; Din0: in Std_logic);
-    end component;
-    component CROW_1_B
-      port (PADDI: out Std_logic; CROW1: in Std_logic);
-    end component;
-    component CROW_0_B
-      port (PADDI: out Std_logic; CROW0: in Std_logic);
-    end component;
-    component MAin_9_B
-      port (PADDI: out Std_logic; MAin9: in Std_logic);
-    end component;
-    component MAin_8_B
-      port (PADDI: out Std_logic; MAin8: in Std_logic);
-    end component;
-    component MAin_7_B
-      port (PADDI: out Std_logic; MAin7: in Std_logic);
-    end component;
-    component MAin_6_B
-      port (PADDI: out Std_logic; MAin6: in Std_logic);
-    end component;
-    component MAin_5_B
-      port (PADDI: out Std_logic; MAin5: in Std_logic);
-    end component;
-    component MAin_4_B
-      port (PADDI: out Std_logic; MAin4: in Std_logic);
-    end component;
-    component MAin_3_B
-      port (PADDI: out Std_logic; MAin3: in Std_logic);
-    end component;
-    component MAin_2_B
-      port (PADDI: out Std_logic; MAin2: in Std_logic);
-    end component;
-    component MAin_1_B
-      port (PADDI: out Std_logic; MAin1: in Std_logic);
-    end component;
-    component MAin_0_B
-      port (PADDI: out Std_logic; MAin0: in Std_logic);
-    end component;
-  begin
-    SLICE_0I: SLICE_0
-      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
-                FCO=>FS_cry_1);
-    SLICE_1I: SLICE_1
-      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
-                Q1=>FS_17);
-    SLICE_2I: SLICE_2
-      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
-                Q1=>FS_15, FCO=>FS_cry_15);
-    SLICE_3I: SLICE_3
-      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
-                Q1=>FS_13, FCO=>FS_cry_13);
-    SLICE_4I: SLICE_4
-      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
-                Q1=>FS_11, FCO=>FS_cry_11);
-    SLICE_5I: SLICE_5
-      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
-                Q1=>FS_9, FCO=>FS_cry_9);
-    SLICE_6I: SLICE_6
-      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
-                Q1=>FS_7, FCO=>FS_cry_7);
-    SLICE_7I: SLICE_7
-      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
-                Q1=>FS_5, FCO=>FS_cry_5);
-    SLICE_8I: SLICE_8
-      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
-                Q1=>FS_3, FCO=>FS_cry_3);
-    SLICE_9I: SLICE_9
-      port map (D1=>N_147, C1=>MAin_c_0, B1=>CmdEnable17_0_a2_4, 
-                A1=>CmdEnable17_0_a2_3, D0=>CmdEnable16, C0=>CmdEnable17, 
-                B0=>C1WR_0_a2, A0=>ADSubmitted, DI0=>ADSubmitted_r, 
-                CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted, 
-                F1=>CmdEnable17);
-    SLICE_14I: SLICE_14
-      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
-                D0=>MAin_c_1, C0=>N_147, B0=>C1Submitted, A0=>CmdEnable16, 
-                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
-                Q0=>C1Submitted, F1=>CmdEnable16);
-    SLICE_19I: SLICE_19
-      port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, 
-                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
-                F1=>Ready_0_sqmuxa_0_a3_2);
-    SLICE_20I: SLICE_20
-      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, 
-                B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, 
-                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
-    SLICE_21I: SLICE_21
-      port map (C1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_152, C0=>N_133, 
-                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
-                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
-    SLICE_22I: SLICE_22
-      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
-                B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_460_0, 
-                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
-    SLICE_26I: SLICE_26
-      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
-                C0=>n8MEGEN, B0=>N_152, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_19_i, 
-                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
-                F1=>Cmdn8MEGEN_4_u_i_0);
-    SLICE_29I: SLICE_29
-      port map (D1=>nRRAS_5_u_i_0, C1=>N_160, B1=>N_155, A1=>IS_0, C0=>N_155, 
-                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
-                Q0=>IS_0, F1=>N_24);
-    SLICE_30I: SLICE_30
-      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, 
-                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
-    SLICE_31I: SLICE_31
-      port map (D1=>N_159, C1=>IS_3, B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, 
-                B0=>IS_2, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
-    SLICE_32I: SLICE_32
-      port map (D1=>UFMSDI_ens2_i_a2_4_2, C1=>N_126, B1=>N_51, A1=>InitReady, 
-                B0=>InitReady, A0=>InitReady3, DI0=>N_461_0, CLK=>RCLK_c, 
-                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
-    SLICE_33I: SLICE_33
-      port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, C0=>UFMSDO_c, B0=>InitReady, 
-                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
-                Q0=>LEDEN, F1=>LED_c);
-    SLICE_39I: SLICE_39
-      port map (B1=>un1_Din_4, A1=>XOR8MEG, C0=>n8MEGEN, B0=>XOR8MEG, 
-                A0=>Din_c_6, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
-                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
-    SLICE_41I: SLICE_41
-      port map (D1=>S_1, C1=>FWEr_fast, B1=>CO0, A1=>CASr2, D0=>Ready, 
-                C0=>RCKEEN_8_u_1, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, 
-                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
-                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
-    SLICE_42I: SLICE_42
-      port map (D1=>RASr2, C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>RCKEEN, C0=>RASr3, 
-                B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
-                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
-    SLICE_43I: SLICE_43
-      port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, 
-                D0=>InitReady, C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, 
-                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
-                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
-    SLICE_44I: SLICE_44
-      port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_165, A1=>InitReady, 
-                B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_463_0, M1=>nCRAS_c, 
-                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
-                Q1=>RASr);
-    SLICE_50I: SLICE_50
-      port map (C1=>CO0, B1=>S_1, A1=>Ready, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1, 
-                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
-                F1=>nRRAS_0_sqmuxa);
-    SLICE_51I: SLICE_51
-      port map (D1=>N_129, C1=>UFMCLK_r_i_a2_2_2, B1=>CmdUFMCLK, A1=>InitReady, 
-                D0=>UFMCLK_r_i_m4_xx_mm_1, C0=>UFMCLK_c, B0=>nUFMCS15, 
-                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
-                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
-                Q1=>RASr2);
-    SLICE_52I: SLICE_52
-      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
-                D0=>UFMSDI_r_xx_mm_1, C0=>UFMSDI_c, B0=>nUFMCS15, A0=>N_139_i, 
-                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
-                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
-    SLICE_55I: SLICE_55
-      port map (C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, M1=>Din_c_5, 
-                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
-    SLICE_56I: SLICE_56
-      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, C0=>FS_9, 
-                B0=>FS_7, A0=>FS_5, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
-                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
-    SLICE_57I: SLICE_57
-      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
-                D0=>XOR8MEG_3_u_0_a3_2, C0=>N_171, B0=>LEDEN, A0=>Din_c_1, 
-                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
-                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
-    SLICE_58I: SLICE_58
-      port map (C1=>N_51, B1=>InitReady, A1=>FS_8, C0=>UFMSDO_c, B0=>InitReady, 
-                A0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
-                Q0=>n8MEGEN, F1=>N_151);
-    SLICE_59I: SLICE_59
-      port map (D1=>S_1, C1=>Ready, B1=>N_160, A1=>N_155, D0=>g0_1, C0=>S_1, 
-                B0=>nRCAS_0_sqmuxa_1, A0=>N_41, DI0=>N_37_i, CLK=>RCLK_c, 
-                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
-    SLICE_60I: SLICE_60
-      port map (D1=>CASr2, C1=>CASr3, B1=>CO0, A1=>FWEr_fast, 
-                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
-                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
-    SLICE_61I: SLICE_61
-      port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, D0=>IS_0, 
-                C0=>N_155, B0=>N_160, A0=>nRRAS_5_u_i_0, DI0=>N_24_i, 
-                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
-    SLICE_62I: SLICE_62
-      port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR_fast, 
-                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>G_17_1, A0=>FWEr, 
-                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
-                F1=>nRCAS_0_sqmuxa_1);
-    SLICE_63I: SLICE_63
-      port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, 
-                B0=>N_179, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
-                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
-    SLICE_64I: SLICE_64
-      port map (D1=>N_51, C1=>InitReady, B1=>FS_11, A1=>FS_10, 
-                D0=>nUFMCS_s_0_N_5_i_N_2L1, C0=>nUFMCS_c, B0=>nUFMCS15, 
-                A0=>N_139_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, 
-                F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS15);
-    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
-      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>InitReady, 
-                C0=>m18_0_a3_3, B0=>CO0, A0=>S_1, M0=>Ready, OFX0=>m18_0_a2_1);
-    SLICE_66I: SLICE_66
-      port map (C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, A1=>CmdUFMCS, D0=>N_95_5, 
-                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
-                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
-                Q1=>RowA_1);
-    SLICE_67I: SLICE_67
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_128, A1=>XOR8MEG18, D0=>N_147, 
-                C0=>MAin_c_1, B0=>MAin_c_0, A0=>CmdEnable, M1=>MAin_c_5, 
-                M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, F0=>XOR8MEG18, 
-                Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
-    SLICE_68I: SLICE_68
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_14_i_a2_0_1, 
-                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_31, 
-                F1=>un1_FS_14_i_a2_0_1);
-    SLICE_69I: SLICE_69
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_13_i_a2_1, 
-                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_33, 
-                F1=>un1_FS_13_i_a2_1);
-    SLICE_70I: SLICE_70
-      port map (D1=>C1WR_0_a2_0_11, C1=>C1WR_0_a2_0_10, B1=>Bank_1, A1=>Bank_0, 
-                B0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
-                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
-    SLICE_71I: SLICE_71
-      port map (D1=>MAin_c_7, C1=>MAin_c_6, B1=>MAin_c_5, A1=>MAin_c_4, 
-                D0=>C1WR_0_a2_0_4, C0=>C1WR_0_a2_0_3, B0=>Bank_4, A0=>Bank_3, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
-                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
-    SLICE_72I: SLICE_72
-      port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_12, D0=>N_51, 
-                C0=>FS_11, B0=>FS_4, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
-                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
-                Q1=>RowA_3);
-    SLICE_73I: SLICE_73
-      port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, B0=>Ready, 
-                A0=>N_155, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
-                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
-    SLICE_74I: SLICE_74
-      port map (B1=>FS_14, A1=>FS_11, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
-                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
-    SLICE_75I: SLICE_75
-      port map (C1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, C0=>N_128, B0=>Din_c_5, 
-                A0=>Din_c_1, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
-                Q0=>CASr, F1=>N_128, Q1=>CASr2);
-    SLICE_76I: SLICE_76
-      port map (B1=>Din_c_5, A1=>Din_c_0, D0=>MAin_c_0, C0=>Din_c_3, 
-                B0=>Din_c_1, A0=>CmdEnable16_4, M1=>Din_c_5, M0=>Din_c_4, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
-                F1=>CmdEnable16_4, Q1=>Bank_5);
-    SLICE_77I: SLICE_77
-      port map (B1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>Din_c_6, 
-                B0=>Din_c_2, A0=>CmdEnable16_1, M1=>Din_c_7, M0=>Din_c_6, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
-                F1=>CmdEnable16_1, Q1=>Bank_7);
-    SLICE_78I: SLICE_78
-      port map (B1=>Din_c_5, A1=>Din_c_3, D0=>N_43, C0=>MAin_c_1, B0=>Din_c_6, 
-                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
-                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
-    SLICE_79I: SLICE_79
-      port map (C1=>Ready, B1=>CASr3, A1=>CASr2, D0=>m6_0_a2_2, C0=>S_1, 
-                B0=>CO0, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
-                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
-    SLICE_80I: SLICE_80
-      port map (B1=>CASr3, A1=>CASr2, D0=>g4_0_0_0, C0=>FWEr, B0=>CO0, 
-                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
-    SLICE_81I: SLICE_81
-      port map (D1=>FS_17, C1=>FS_15, B1=>FS_14, A1=>FS_13, D0=>FS_17, 
-                C0=>FS_15, B0=>FS_13, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
-                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
-                Q1=>FWEr_fast);
-    SLICE_82I: SLICE_82
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>CmdLEDEN, A1=>N_128, D0=>Din_c_3, 
-                C0=>Din_c_5, B0=>N_128, A0=>XOR8MEG18, M0=>CASr2, CLK=>RCLK_c, 
-                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
-    SLICE_83I: SLICE_83
-      port map (C1=>IS_3, B1=>IS_2, A1=>IS_1, C0=>IS_2, B0=>IS_1, A0=>IS_0, 
-                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
-    SLICE_84I: SLICE_84
-      port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>FS_10, C0=>FS_7, 
-                B0=>FS_6, A0=>FS_1, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
-    SLICE_85I: SLICE_85
-      port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_0, A1=>Din_c_1, 
-                D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
-                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
-    SLICE_86I: SLICE_86
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, 
-                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
-    SLICE_87I: SLICE_87
-      port map (C1=>N_151, B1=>UFMSDI_ens2_i_a0, A1=>CmdUFMSDI, D0=>N_151, 
-                C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_137_8, 
-                F1=>UFMSDI_r_xx_mm_1);
-    SLICE_88I: SLICE_88
-      port map (C1=>nFWE_c, B1=>MAin_c_3, A1=>MAin_c_2, B0=>nFWE_c, 
-                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
-                Q1=>RowA_7);
-    SLICE_89I: SLICE_89
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, 
-                A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
-    SLICE_90I: SLICE_90
-      port map (C1=>MAin_c_1, B1=>MAin_c_0, A1=>N_147, C0=>nRowColSel, 
-                B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>un1_CMDWR);
-    SLICE_91I: SLICE_91
-      port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, 
-                B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
-    SLICE_92I: SLICE_92
-      port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, 
-                B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
-    SLICE_93I: SLICE_93
-      port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, 
-                B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
-    SLICE_94I: SLICE_94
-      port map (B1=>N_155, A1=>Ready, B0=>S_1, A0=>Ready, M0=>IS_0, 
-                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
-                Q0=>RA_c_10, F1=>N_159_i);
-    RD_0_I: RD_0_B
-      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
-    Dout_0_I: Dout_0_B
-      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
-    PHI2I: PHI2B
-      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
-    UFMSDOI: UFMSDOB
-      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
-    UFMSDII: UFMSDIB
-      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
-    UFMCLKI: UFMCLKB
-      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
-    nUFMCSI: nUFMCSB
-      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
-    RDQMLI: RDQMLB
-      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
-    RDQMHI: RDQMHB
-      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
-    nRCASI: nRCASB
-      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
-    nRRASI: nRRASB
-      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
-    nRWEI: nRWEB
-      port map (PADDO=>nRWE_c, nRWES=>nRWE);
-    RCKEI: RCKEB
-      port map (PADDO=>RCKE_c, RCKES=>RCKE);
-    RCLKI: RCLKB
-      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
-    nRCSI: nRCSB
-      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
-    RD_7_I: RD_7_B
-      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
-    RD_6_I: RD_6_B
-      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
-    RD_5_I: RD_5_B
-      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
-    RD_4_I: RD_4_B
-      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
-    RD_3_I: RD_3_B
-      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
-    RD_2_I: RD_2_B
-      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
-    RD_1_I0: RD_1_B
-      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
-    RA_11_I: RA_11_B
-      port map (PADDO=>RA_c_11, RA11=>RA(11));
-    RA_10_I: RA_10_B
-      port map (PADDO=>RA_c_10, RA10=>RA(10));
-    RA_9_I: RA_9_B
-      port map (PADDO=>RA_c_9, RA9=>RA(9));
-    RA_8_I: RA_8_B
-      port map (PADDO=>RA_c_8, RA8=>RA(8));
-    RA_7_I: RA_7_B
-      port map (PADDO=>RA_c_7, RA7=>RA(7));
-    RA_6_I: RA_6_B
-      port map (PADDO=>RA_c_6, RA6=>RA(6));
-    RA_5_I: RA_5_B
-      port map (PADDO=>RA_c_5, RA5=>RA(5));
-    RA_4_I: RA_4_B
-      port map (PADDO=>RA_c_4, RA4=>RA(4));
-    RA_3_I: RA_3_B
-      port map (PADDO=>RA_c_3, RA3=>RA(3));
-    RA_2_I: RA_2_B
-      port map (PADDO=>RA_c_2, RA2=>RA(2));
-    RA_1_I: RA_1_B
-      port map (PADDO=>RA_c_1, RA1=>RA(1));
-    RA_0_I: RA_0_B
-      port map (PADDO=>RA_c_0, RA0=>RA(0));
-    RBA_1_I: RBA_1_B
-      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
-    RBA_0_I: RBA_0_B
-      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
-    LEDI: LEDB
-      port map (PADDO=>LED_c, LEDS=>LED);
-    nFWEI: nFWEB
-      port map (PADDI=>nFWE_c, nFWES=>nFWE);
-    nCRASI: nCRASB
-      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
-    nCCASI: nCCASB
-      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
-    Dout_7_I: Dout_7_B
-      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
-    Dout_6_I: Dout_6_B
-      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
-    Dout_5_I: Dout_5_B
-      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
-    Dout_4_I: Dout_4_B
-      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
-    Dout_3_I: Dout_3_B
-      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
-    Dout_2_I: Dout_2_B
-      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
-    Dout_1_I: Dout_1_B
-      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
-    Din_7_I: Din_7_B
-      port map (PADDI=>Din_c_7, Din7=>Din(7));
-    Din_6_I: Din_6_B
-      port map (PADDI=>Din_c_6, Din6=>Din(6));
-    Din_5_I: Din_5_B
-      port map (PADDI=>Din_c_5, Din5=>Din(5));
-    Din_4_I: Din_4_B
-      port map (PADDI=>Din_c_4, Din4=>Din(4));
-    Din_3_I: Din_3_B
-      port map (PADDI=>Din_c_3, Din3=>Din(3));
-    Din_2_I: Din_2_B
-      port map (PADDI=>Din_c_2, Din2=>Din(2));
-    Din_1_I: Din_1_B
-      port map (PADDI=>Din_c_1, Din1=>Din(1));
-    Din_0_I: Din_0_B
-      port map (PADDI=>Din_c_0, Din0=>Din(0));
-    CROW_1_I: CROW_1_B
-      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
-    CROW_0_I: CROW_0_B
-      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
-    MAin_9_I: MAin_9_B
-      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
-    MAin_8_I: MAin_8_B
-      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
-    MAin_7_I: MAin_7_B
-      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
-    MAin_6_I: MAin_6_B
-      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
-    MAin_5_I: MAin_5_B
-      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
-    MAin_4_I: MAin_4_B
-      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
-    MAin_3_I: MAin_3_B
-      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
-    MAin_2_I: MAin_2_B
-      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
-    MAin_1_I: MAin_1_B
-      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
-    MAin_0_I: MAin_0_B
-      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
-    VHI_INST: VHI
-      port map (Z=>VCCI);
-    PUR_INST: PUR
-      port map (PUR=>VCCI);
-    GSR_INST: GSR
-      port map (GSR=>VCCI);
-    VLO_INST: VLO
-      port map (Z=>GNDI_TSALL);
-    TSALL_INST: TSALL
-      port map (TSALL=>GNDI_TSALL);
-  end Structure;
-
-
-
-  library IEEE, vital2000, MACHXO;
-  configuration Structure_CON of RAM2GS is
-    for Structure
-    end for;
-  end Structure_CON;
-
-
+
+-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+-- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_mapvho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd 
+-- Netlist created on Sat Aug 19 20:57:13 2023
+-- Netlist written on Sat Aug 19 20:57:16 2023
+-- Design is for device LCMXO640C
+-- Design is for package TQFP100
+-- Design is for performance grade 3
+
+-- entity vmuxregsre
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
+
+  end vmuxregsre;
+
+  architecture Structure of vmuxregsre is
+    component FL1P3DX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity vcc
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vcc is
+    port (PWR1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
+
+  end vcc;
+
+  architecture Structure of vcc is
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VHI
+      port map (Z=>PWR1);
+  end Structure;
+
+-- entity gnd
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity gnd is
+    port (PWR0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
+
+  end gnd;
+
+  architecture Structure of gnd is
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VLO
+      port map (Z=>PWR0);
+  end Structure;
+
+-- entity ccu2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu2B is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
+
+  end ccu2B;
+
+  architecture Structure of ccu2B is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_0
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_0";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
+
+  end SLICE_0;
+
+  architecture Structure of SLICE_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_0: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
+                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20001
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu20001 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
+
+  end ccu20001;
+
+  architecture Structure of ccu20001 is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_1
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_1";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
+
+  end SLICE_1;
+
+  architecture Structure of SLICE_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu20001
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_17: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_16: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_16: ccu20001
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
+                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_2 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_2";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
+
+  end SLICE_2;
+
+  architecture Structure of SLICE_2 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_15: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_14: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_14: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
+                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_3
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_3 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_3";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
+
+  end SLICE_3;
+
+  architecture Structure of SLICE_3 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_13: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_12: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_12: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
+                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_4 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_4";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
+
+  end SLICE_4;
+
+  architecture Structure of SLICE_4 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_11: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_10: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_10: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
+                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_5
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_5 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_5";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
+
+  end SLICE_5;
+
+  architecture Structure of SLICE_5 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_9: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_8: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_8: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
+                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_6
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_6 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_6";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
+
+  end SLICE_6;
+
+  architecture Structure of SLICE_6 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_7: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_6: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_6: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
+                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_7
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_7 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_7";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
+
+  end SLICE_7;
+
+  architecture Structure of SLICE_7 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_5: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_4: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_4: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
+                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_8
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_8 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_8";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
+
+  end SLICE_8;
+
+  architecture Structure of SLICE_8 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_2: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
+                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut4 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
+
+  end lut4;
+
+  architecture Structure of lut4 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40002
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40002 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
+
+  end lut40002;
+
+  architecture Structure of lut40002 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00F2")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity inverter
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity inverter is
+    port (I: in Std_logic; Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
+
+  end inverter;
+
+  architecture Structure of inverter is
+    component INV
+      port (A: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    INST1: INV
+      port map (A=>I, Z=>Z);
+  end Structure;
+
+-- entity SLICE_9
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_9 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_9";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
+
+  end SLICE_9;
+
+  architecture Structure of SLICE_9 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40002
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    ADSubmitted_r: lut40002
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    ADSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40003
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40003 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
+
+  end lut40003;
+
+  architecture Structure of lut40003 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8080")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40004
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40004 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
+
+  end lut40004;
+
+  architecture Structure of lut40004 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_14
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_14 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_14";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
+
+  end SLICE_14;
+
+  architecture Structure of SLICE_14 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40003
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40004
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2: lut40003
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    C1Submitted_RNO: lut40004
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    C1Submitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40005
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40005 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
+
+  end lut40005;
+
+  architecture Structure of lut40005 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40006
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40006 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
+
+  end lut40006;
+
+  architecture Structure of lut40006 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDDDD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0007
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0007 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
+
+  end vmuxregsre0007;
+
+  architecture Structure of vmuxregsre0007 is
+    component FL1P3IY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3IY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_19
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_19 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_19";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
+
+  end SLICE_19;
+
+  architecture Structure of SLICE_19 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40006
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    S_RNO_0: lut40006
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40008
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40008 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
+
+  end lut40008;
+
+  architecture Structure of lut40008 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40009
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40009 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
+
+  end lut40009;
+
+  architecture Structure of lut40009 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAC8C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity selmux2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity selmux2 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
+
+  end selmux2;
+
+  architecture Structure of selmux2 is
+    component MUX21
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    INST1: MUX21
+      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
+  end Structure;
+
+-- entity SLICE_20
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_20 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_20";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
+
+  end SLICE_20;
+
+  architecture Structure of SLICE_20 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
+    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40008
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40009
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    SLICE_20_K1: lut40008
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
+                Z=>SLICE_20_SLICE_20_K1_H1);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable_s_GATE: lut40009
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>SLICE_20_CmdEnable_s_GATE_H0);
+    CmdEnable: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    SLICE_20_K0K1MUX: selmux2
+      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
+                SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40010
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40010 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
+
+  end lut40010;
+
+  architecture Structure of lut40010 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40011
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40011 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
+
+  end lut40011;
+
+  architecture Structure of lut40011 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0203")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_21
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_21 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_21";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
+
+  end SLICE_21;
+
+  architecture Structure of SLICE_21 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40010
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40011
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_a2_2: lut40010
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_RNO: lut40011
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdLEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40012
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40012 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
+
+  end lut40012;
+
+  architecture Structure of lut40012 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_22
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_22 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_22";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
+
+  end SLICE_22;
+
+  architecture Structure of SLICE_22 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40013
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40013 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
+
+  end lut40013;
+
+  architecture Structure of lut40013 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33AB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40014
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40014 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
+
+  end lut40014;
+
+  architecture Structure of lut40014 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5151")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_26
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_26 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_26";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
+
+  end SLICE_26;
+
+  architecture Structure of SLICE_26 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40014
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_0: lut40013
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Cmdn8MEGEN_RNO: lut40014
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Cmdn8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40015
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40015 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
+
+  end lut40015;
+
+  architecture Structure of lut40015 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF32")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40016
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40016 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
+
+  end lut40016;
+
+  architecture Structure of lut40016 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA9A9")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_29
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_29 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_29";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
+
+  end SLICE_29;
+
+  architecture Structure of SLICE_29 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40015
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40016
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i: lut40015
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_0: lut40016
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40017
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40017 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
+
+  end lut40017;
+
+  architecture Structure of lut40017 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7878")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40018
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40018 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
+
+  end lut40018;
+
+  architecture Structure of lut40018 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x6666")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_30
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_30 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_30";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
+
+  end SLICE_30;
+
+  architecture Structure of SLICE_30 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40017
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40018
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_RNO_2: lut40017
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_n1_0_x2: lut40018
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    IS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    IS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40019
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40019 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
+
+  end lut40019;
+
+  architecture Structure of lut40019 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40020
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40020 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
+
+  end lut40020;
+
+  architecture Structure of lut40020 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x6AAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_31
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_31 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_31";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
+
+  end SLICE_31;
+
+  architecture Structure of SLICE_31 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40019
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40020
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RA10_RNO: lut40019
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_3: lut40020
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    IS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40021
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40021 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
+
+  end lut40021;
+
+  architecture Structure of lut40021 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4555")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_32
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_32 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_32";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
+
+  end SLICE_32;
+
+  architecture Structure of SLICE_32 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40021
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a0: lut40021
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40022
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40022 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
+
+  end lut40022;
+
+  architecture Structure of lut40022 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFBFB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40023
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40023 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
+
+  end lut40023;
+
+  architecture Structure of lut40023 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8B8B")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_33
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_33 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_33";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
+
+  end SLICE_33;
+
+  architecture Structure of SLICE_33 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40022
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    LED_pad_RNO: lut40022
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    LEDEN_5_i_m2: lut40023
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    LEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40024
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40024 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
+
+  end lut40024;
+
+  architecture Structure of lut40024 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40025
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40025 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
+
+  end lut40025;
+
+  architecture Structure of lut40025 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xC6C6")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_39
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_39 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_39";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
+
+  end SLICE_39;
+
+  architecture Structure of SLICE_39 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40025
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_0: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RA11_2: lut40025
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RA11: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40026
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40026 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
+
+  end lut40026;
+
+  architecture Structure of lut40026 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x70CF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40027
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40027 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
+
+  end lut40027;
+
+  architecture Structure of lut40027 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_41
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_41 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_41";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
+
+  end SLICE_41;
+
+  architecture Structure of SLICE_41 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40026
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40027
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_1_0: lut40026
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKEEN_8_u: lut40027
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40028
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40028 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
+
+  end lut40028;
+
+  architecture Structure of lut40028 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40029
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40029 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
+
+  end lut40029;
+
+  architecture Structure of lut40029 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFE30")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_42
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_42 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_42";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
+
+  end SLICE_42;
+
+  architecture Structure of SLICE_42 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40029
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_5: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKE_2_0: lut40029
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKE: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40030
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40030 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
+
+  end lut40030;
+
+  architecture Structure of lut40030 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5072")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40031
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40031 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
+
+  end lut40031;
+
+  architecture Structure of lut40031 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAEAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_43
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_43 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_43";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
+
+  end SLICE_43;
+
+  architecture Structure of SLICE_43 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40030
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40031
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_RNO: lut40030
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_RNO: lut40031
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_44
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_44 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_44";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
+
+  end SLICE_44;
+
+  architecture Structure of SLICE_44 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_fast_RNO: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RASr: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Ready_fast: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40032
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40032 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
+
+  end lut40032;
+
+  architecture Structure of lut40032 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0202")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_50
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_50 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_50";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
+
+  end SLICE_50;
+
+  architecture Structure of SLICE_50 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40032
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_RNO: lut40032
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0_i_o2_1: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    S_1: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40033
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40033 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
+
+  end lut40033;
+
+  architecture Structure of lut40033 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF2F7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40034
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40034 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
+
+  end lut40034;
+
+  architecture Structure of lut40034 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1032")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_51
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_51 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_51";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
+
+  end SLICE_51;
+
+  architecture Structure of SLICE_51 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMCLK_RNO_0: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMCLK_RNO: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40035
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40035 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
+
+  end lut40035;
+
+  architecture Structure of lut40035 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3B33")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40036
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40036 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
+
+  end lut40036;
+
+  architecture Structure of lut40036 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3210")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_52
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_52 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_52";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
+
+  end SLICE_52;
+
+  architecture Structure of SLICE_52 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    PHI2r3_RNITCN41: lut40035
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_RNO: lut40036
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMSDI: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40037
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40037 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
+
+  end lut40037;
+
+  architecture Structure of lut40037 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xACAC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_55
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_55 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_55";
+
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
+
+  end SLICE_55;
+
+  architecture Structure of SLICE_55 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_4: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40038
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40038 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
+
+  end lut40038;
+
+  architecture Structure of lut40038 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40039
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40039 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
+
+  end lut40039;
+
+  architecture Structure of lut40039 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2C2C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_56
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_56 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_56";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
+
+  end SLICE_56;
+
+  architecture Structure of SLICE_56 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40039
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_11: lut40038
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_ens2_i_o2: lut40039
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40040
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40040 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
+
+  end lut40040;
+
+  architecture Structure of lut40040 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF7F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_57
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_57 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_57";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
+
+  end SLICE_57;
+
+  architecture Structure of SLICE_57 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG_3_u_0_a3_3: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    XOR8MEG: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40041
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40041 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
+
+  end lut40041;
+
+  architecture Structure of lut40041 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0101")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_58
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_58 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_58";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
+
+  end SLICE_58;
+
+  architecture Structure of SLICE_58 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_en_ss0_0_a2_0: lut40041
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    n8MEGEN_5_i_m2: lut40023
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    n8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40042
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40042 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
+
+  end lut40042;
+
+  architecture Structure of lut40042 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0BFB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40043
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40043 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
+
+  end lut40043;
+
+  architecture Structure of lut40043 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2232")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0044
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0044 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0044 : ENTITY IS TRUE;
+
+  end vmuxregsre0044;
+
+  architecture Structure of vmuxregsre0044 is
+    component FL1P3BX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3BX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_59
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_59 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_59";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
+
+  end SLICE_59;
+
+  architecture Structure of SLICE_59 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40042
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_0: lut40042
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCAS_RNO: lut40043
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCAS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40045
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40045 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
+
+  end lut40045;
+
+  architecture Structure of lut40045 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xE6EE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40046
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40046 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
+
+  end lut40046;
+
+  architecture Structure of lut40046 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3233")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_60
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_60 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_60";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
+
+  end SLICE_60;
+
+  architecture Structure of SLICE_60 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCS_RNO_0: lut40045
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCS_RNO: lut40046
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40047
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40047 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
+
+  end lut40047;
+
+  architecture Structure of lut40047 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5400")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40048
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40048 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
+
+  end lut40048;
+
+  architecture Structure of lut40048 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5051")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_61
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_61 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_61";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
+
+  end SLICE_61;
+
+  architecture Structure of SLICE_61 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40047
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i_0: lut40047
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRRAS_RNO: lut40048
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRRAS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40049
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40049 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
+
+  end lut40049;
+
+  architecture Structure of lut40049 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40050
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40050 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
+
+  end lut40050;
+
+  architecture Structure of lut40050 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF4F7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_62
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_62 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_62";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
+
+  end SLICE_62;
+
+  architecture Structure of SLICE_62 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40050
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_0_sqmuxa_1_0_a3: lut40049
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRWE_RNO: lut40050
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRWE: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40051
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40051 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
+
+  end lut40051;
+
+  architecture Structure of lut40051 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40052
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40052 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
+
+  end lut40052;
+
+  architecture Structure of lut40052 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCEC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_63
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_63 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_63";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
+
+  end SLICE_63;
+
+  architecture Structure of SLICE_63 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40051
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40052
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_0_0_a3_0: lut40051
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRowColSel_0_0: lut40052
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRowColSel: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40053
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40053 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
+
+  end lut40053;
+
+  architecture Structure of lut40053 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40054
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40054 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
+
+  end lut40054;
+
+  architecture Structure of lut40054 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_64
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_64 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_64";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
+
+  end SLICE_64;
+
+  architecture Structure of SLICE_64 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0044
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40054
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS15_0_a2: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nUFMCS_s_0_N_5_i: lut40054
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nUFMCS: vmuxregsre0044
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40055
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40055 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
+
+  end lut40055;
+
+  architecture Structure of lut40055 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40056
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40056 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
+
+  end lut40056;
+
+  architecture Structure of lut40056 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity nRWE_RNO_1_SLICE_65
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWE_RNO_1_SLICE_65 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
+
+  end nRWE_RNO_1_SLICE_65;
+
+  architecture Structure of nRWE_RNO_1_SLICE_65 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40055
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40056
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_1_SLICE_65_K1: lut40055
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
+    nRWE_RNO_1_GATE: lut40056
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
+    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
+      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
+                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
+                Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40057
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40057 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
+
+  end lut40057;
+
+  architecture Structure of lut40057 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0B0B")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_66
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_66 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_66";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
+
+  end SLICE_66;
+
+  architecture Structure of SLICE_66 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS_s_0_N_5_i_N_2L1: lut40057
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_a2_2_2: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40058
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40058 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
+
+  end lut40058;
+
+  architecture Structure of lut40058 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0059
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0059 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0059 : ENTITY IS TRUE;
+
+  end vmuxregsre0059;
+
+  architecture Structure of vmuxregsre0059 is
+    component FL1P3JY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3JY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_67
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_67 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_67";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
+
+  end SLICE_67;
+
+  architecture Structure of SLICE_67 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    CmdUFMCLK_1_sqmuxa_0_a2: lut40058
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG18_0_a2: lut40005
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_5: vmuxregsre0059
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_4: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40060
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40060 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
+
+  end lut40060;
+
+  architecture Structure of lut40060 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEAAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_68
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_68 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_68";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
+
+  end SLICE_68;
+
+  architecture Structure of SLICE_68 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2_0_1: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_14_i_0: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40061
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40061 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
+
+  end lut40061;
+
+  architecture Structure of lut40061 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0100")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_69
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_69 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_69";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
+
+  end SLICE_69;
+
+  architecture Structure of SLICE_69 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_13_i_a2_1: lut40061
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_0: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40062
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40062 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
+
+  end lut40062;
+
+  architecture Structure of lut40062 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8888")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_70
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_70 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_70";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
+
+  end SLICE_70;
+
+  architecture Structure of SLICE_70 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2: lut40062
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_71
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_71 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_71";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
+
+  end SLICE_71;
+
+  architecture Structure of SLICE_71 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_4: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2_0_10: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40063
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40063 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
+
+  end lut40063;
+
+  architecture Structure of lut40063 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFEFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40064
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40064 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
+
+  end lut40064;
+
+  architecture Structure of lut40064 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAAC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_72
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_72 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_72";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
+
+  end SLICE_72;
+
+  architecture Structure of SLICE_72 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0: lut40063
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_m2: lut40064
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_3: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_2: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40065
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40065 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
+
+  end lut40065;
+
+  architecture Structure of lut40065 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFF7")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_73
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_73 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_73";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
+
+  end SLICE_73;
+
+  architecture Structure of SLICE_73 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0: lut40065
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_0_sqmuxa_0_o2: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdUFMCS: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CmdUFMCLK: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_74
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_74 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_74";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
+
+  end SLICE_74;
+
+  architecture Structure of SLICE_74 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    InitReady3_0_a2_3: lut40062
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady3_0_a2: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdUFMSDI: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40066
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40066 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
+
+  end lut40066;
+
+  architecture Structure of lut40066 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFDFD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_75
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_75 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_75";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
+
+  end SLICE_75;
+
+  architecture Structure of SLICE_75 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_o2_0: lut40066
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_4_u_i_a2_0: lut40041
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    CASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CASr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40067
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40067 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
+
+  end lut40067;
+
+  architecture Structure of lut40067 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0002")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_76
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_76 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_76";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
+
+  end SLICE_76;
+
+  architecture Structure of SLICE_76 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40067
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_4: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_4_0: lut40067
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40068
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40068 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
+
+  end lut40068;
+
+  architecture Structure of lut40068 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4444")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_77
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_77 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_77";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
+
+  end SLICE_77;
+
+  architecture Structure of SLICE_77 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40068
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_1: lut40068
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_5: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40069
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40069 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
+
+  end lut40069;
+
+  architecture Structure of lut40069 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7777")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_78
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_78 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_78";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
+
+  end SLICE_78;
+
+  architecture Structure of SLICE_78 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_o2: lut40069
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable17_0_a2_4: lut40058
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CBR_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CBR: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40070
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40070 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
+
+  end lut40070;
+
+  architecture Structure of lut40070 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_79
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_79 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_79";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
+
+  end SLICE_79;
+
+  architecture Structure of SLICE_79 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40070
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_2: lut40070
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRWE_RNO_0: lut40038
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40071
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40071 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
+
+  end lut40071;
+
+  architecture Structure of lut40071 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4101")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_80
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_80 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_80";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
+
+  end SLICE_80;
+
+  architecture Structure of SLICE_80 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40071
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_RNO_1: lut40024
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRCAS_RNO_0: lut40071
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_9: vmuxregsre0059
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_8: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40072
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40072 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
+
+  end lut40072;
+
+  architecture Structure of lut40072 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_81
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_81 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_81";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
+
+  end SLICE_81;
+
+  architecture Structure of SLICE_81 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0_3: lut40072
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady3_0_a2_5: lut4
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    FWEr_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    FWEr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40073
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40073 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
+
+  end lut40073;
+
+  architecture Structure of lut40073 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40074
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40074 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
+
+  end lut40074;
+
+  architecture Structure of lut40074 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0222")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_82
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_82 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_82";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
+
+  end SLICE_82;
+
+  architecture Structure of SLICE_82 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40073
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdLEDEN_4_u_i_a2: lut40073
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_1_sqmuxa_0_a2: lut40074
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr3: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40075
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40075 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
+
+  end lut40075;
+
+  architecture Structure of lut40075 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x7F7F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_83
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_83 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_83";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
+
+  end SLICE_83;
+
+  architecture Structure of SLICE_83 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40075
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_o2: lut40063
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready_0_sqmuxa_0_o2: lut40075
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    RBA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RBA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_84
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_84 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_84";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
+
+  end SLICE_84;
+
+  architecture Structure of SLICE_84 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a2_4_2: lut40028
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_a2_6: lut40061
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40076
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40076 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
+
+  end lut40076;
+
+  architecture Structure of lut40076 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0040")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_85
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_85 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_85";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
+
+  end SLICE_85;
+
+  architecture Structure of SLICE_85 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40076
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2_3: lut40076
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_Din_4: lut40053
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_86
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_86 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_86";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
+
+  end SLICE_86;
+
+  architecture Structure of SLICE_86 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQML: lut40069
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_9: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40077
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40077 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
+
+  end lut40077;
+
+  architecture Structure of lut40077 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3232")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_87
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_87 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_87";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
+
+  end SLICE_87;
+
+  architecture Structure of SLICE_87 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40077
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_RNO_0: lut40077
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un1_FS_13_i_a2_8: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40078
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40078 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
+
+  end lut40078;
+
+  architecture Structure of lut40078 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0808")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_88
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_88 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_88";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
+
+  end SLICE_88;
+
+  architecture Structure of SLICE_88 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40078
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_3: lut40078
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nCCAS_pad_RNI01SJ: lut40012
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    RowA_7: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_6: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, 
+      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40079
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40079 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
+
+  end lut40079;
+
+  architecture Structure of lut40079 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBBBB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_89
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_89 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_89";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
+
+  end SLICE_89;
+
+  architecture Structure of SLICE_89 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40079
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQMH: lut40079
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_8: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40080
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40080 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
+
+  end lut40080;
+
+  architecture Structure of lut40080 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA8A8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_90
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_90 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_90";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
+
+  end SLICE_90;
+
+  architecture Structure of SLICE_90 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40080
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_CMDWR: lut40080
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_0: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_91
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_91 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_91";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
+
+  end SLICE_91;
+
+  architecture Structure of SLICE_91 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_7: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_1: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_92
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_92 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_92";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
+
+  end SLICE_92;
+
+  architecture Structure of SLICE_92 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_6: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_2: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_93
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_93 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_93";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
+
+  end SLICE_93;
+
+  architecture Structure of SLICE_93 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_5: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_3: lut40037
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40081
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40081 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
+
+  end lut40081;
+
+  architecture Structure of lut40081 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1111")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_94
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_94 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_94";
+
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
+
+  end SLICE_94;
+
+  architecture Structure of SLICE_94 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0059
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN_8_u_0_a2_1_s: lut40062
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    RA10: vmuxregsre0059
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf is
+    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+          PAD: out Std_logic; PADI: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
+
+  end mjiobuf;
+
+  architecture Structure of mjiobuf is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+    component OBW
+      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PADI, O=>Z);
+    INST2: OBW
+      port map (I=>I, T=>T, O=>PAD);
+  end Structure;
+
+-- entity RD_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_0_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD0 	: VitalDelayType := 0 ns;
+      tpw_RD0_posedge	: VitalDelayType := 0 ns;
+      tpw_RD0_negedge	: VitalDelayType := 0 ns;
+      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD0: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
+
+  end RD_0_B;
+
+  architecture Structure of RD_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD0_ipd 	: std_logic := 'X';
+    signal RD0_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_0: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
+                PADI=>RD0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD0_zd         	: std_logic := 'X';
+    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD0_RD0          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD0_ipd,
+        TestSignalName => "RD0",
+        Period => tperiod_RD0,
+        PulseWidthHigh => tpw_RD0_posedge,
+        PulseWidthLow => tpw_RD0_negedge,
+        PeriodData => periodcheckinfo_RD0,
+        Violation => tviol_RD0_RD0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD0_zd 	:= RD0_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
+                           PathDelay => tpd_RD0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD0,
+                           PathCondition => TRUE)),
+      GlitchData => RD0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0082
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0082 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0082 : ENTITY IS TRUE;
+
+  end mjiobuf0082;
+
+  architecture Structure of mjiobuf0082 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity Dout_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
+
+  end Dout_0_B;
+
+  architecture Structure of Dout_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout0_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_0: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
+    VARIABLE Dout0_zd         	: std_logic := 'X';
+    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout0_zd 	:= Dout0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout0,
+                           PathCondition => TRUE)),
+      GlitchData => Dout0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0083
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0083 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0083 : ENTITY IS TRUE;
+
+  end mjiobuf0083;
+
+  architecture Structure of mjiobuf0083 is
+    component IBPD
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPD
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity PHI2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity PHI2B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "PHI2B";
+
+      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_PHI2S 	: VitalDelayType := 0 ns;
+      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
+      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; PHI2S: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
+
+  end PHI2B;
+
+  architecture Structure of PHI2B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PHI2S_ipd 	: std_logic := 'X';
+
+    component mjiobuf0083
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    PHI2_pad: mjiobuf0083
+      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
+    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => PHI2S_ipd,
+        TestSignalName => "PHI2S",
+        Period => tperiod_PHI2S,
+        PulseWidthHigh => tpw_PHI2S_posedge,
+        PulseWidthLow => tpw_PHI2S_negedge,
+        PeriodData => periodcheckinfo_PHI2S,
+        Violation => tviol_PHI2S_PHI2S,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
+                           PathDelay => tpd_PHI2S_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0084
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0084 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0084 : ENTITY IS TRUE;
+
+  end mjiobuf0084;
+
+  architecture Structure of mjiobuf0084 is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity UFMSDOB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDOB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDOB";
+
+      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
+
+  end UFMSDOB;
+
+  architecture Structure of UFMSDOB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal UFMSDOS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    UFMSDO_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
+    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => UFMSDOS_ipd,
+        TestSignalName => "UFMSDOS",
+        Period => tperiod_UFMSDOS,
+        PulseWidthHigh => tpw_UFMSDOS_posedge,
+        PulseWidthLow => tpw_UFMSDOS_negedge,
+        PeriodData => periodcheckinfo_UFMSDOS,
+        Violation => tviol_UFMSDOS_UFMSDOS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
+                           PathDelay => tpd_UFMSDOS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0085
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0085 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0085 : ENTITY IS TRUE;
+
+  end mjiobuf0085;
+
+  architecture Structure of mjiobuf0085 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity UFMSDIB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDIB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDIB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
+
+  end UFMSDIB;
+
+  architecture Structure of UFMSDIB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMSDIS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMSDI_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
+    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
+    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMSDIS_zd 	:= UFMSDIS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMSDIS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMSDIS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity UFMCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMCLKB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
+
+  end UFMCLKB;
+
+  architecture Structure of UFMCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMCLKS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMCLK_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
+    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
+    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMCLKS_zd 	:= UFMCLKS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMCLKS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMCLKS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nUFMCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nUFMCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nUFMCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
+
+  end nUFMCSB;
+
+  architecture Structure of nUFMCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nUFMCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nUFMCS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
+    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
+    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nUFMCSS_zd 	:= nUFMCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nUFMCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nUFMCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMLB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMLB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMLB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
+
+  end RDQMLB;
+
+  architecture Structure of RDQMLB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMLS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQML_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
+    VARIABLE RDQMLS_zd         	: std_logic := 'X';
+    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMLS_zd 	:= RDQMLS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMLS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMLS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMHB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMHB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMHB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
+
+  end RDQMHB;
+
+  architecture Structure of RDQMHB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMHS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQMH_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
+    VARIABLE RDQMHS_zd         	: std_logic := 'X';
+    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMHS_zd 	:= RDQMHS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMHS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMHS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
+
+  end nRCASB;
+
+  architecture Structure of nRCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCASS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCAS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
+    VARIABLE nRCASS_zd         	: std_logic := 'X';
+    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCASS_zd 	:= nRCASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRRASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRRASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
+
+  end nRRASB;
+
+  architecture Structure of nRRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRRASS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRRAS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
+    VARIABLE nRRASS_zd         	: std_logic := 'X';
+    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRRASS_zd 	:= nRRASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRRASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRRASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRWES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
+
+  end nRWEB;
+
+  architecture Structure of nRWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRWES_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRWE_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRWES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
+    VARIABLE nRWES_zd         	: std_logic := 'X';
+    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRWES_zd 	:= nRWES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRWES,
+                           PathCondition => TRUE)),
+      GlitchData => nRWES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCKEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCKEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCKEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RCKES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
+
+  end RCKEB;
+
+  architecture Structure of RCKEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RCKES_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RCKE_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RCKES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
+    VARIABLE RCKES_zd         	: std_logic := 'X';
+    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RCKES_zd 	:= RCKES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RCKES,
+                           PathCondition => TRUE)),
+      GlitchData => RCKES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCLKB";
+
+      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RCLKS 	: VitalDelayType := 0 ns;
+      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
+      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; RCLKS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
+
+  end RCLKB;
+
+  architecture Structure of RCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal RCLKS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    RCLK_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
+    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RCLKS_ipd,
+        TestSignalName => "RCLKS",
+        Period => tperiod_RCLKS,
+        PulseWidthHigh => tpw_RCLKS_posedge,
+        PulseWidthLow => tpw_RCLKS_negedge,
+        PeriodData => periodcheckinfo_RCLKS,
+        Violation => tviol_RCLKS_RCLKS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
+                           PathDelay => tpd_RCLKS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
+
+  end nRCSB;
+
+  architecture Structure of nRCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCS_pad: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
+    VARIABLE nRCSS_zd         	: std_logic := 'X';
+    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCSS_zd 	:= nRCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_7_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD7 	: VitalDelayType := 0 ns;
+      tpw_RD7_posedge	: VitalDelayType := 0 ns;
+      tpw_RD7_negedge	: VitalDelayType := 0 ns;
+      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD7: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
+
+  end RD_7_B;
+
+  architecture Structure of RD_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD7_ipd 	: std_logic := 'X';
+    signal RD7_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_7: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
+                PADI=>RD7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD7_zd         	: std_logic := 'X';
+    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD7_RD7          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD7_ipd,
+        TestSignalName => "RD7",
+        Period => tperiod_RD7,
+        PulseWidthHigh => tpw_RD7_posedge,
+        PulseWidthLow => tpw_RD7_negedge,
+        PeriodData => periodcheckinfo_RD7,
+        Violation => tviol_RD7_RD7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD7_zd 	:= RD7_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
+                           PathDelay => tpd_RD7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD7,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD7,
+                           PathCondition => TRUE)),
+      GlitchData => RD7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_6_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD6 	: VitalDelayType := 0 ns;
+      tpw_RD6_posedge	: VitalDelayType := 0 ns;
+      tpw_RD6_negedge	: VitalDelayType := 0 ns;
+      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD6: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
+
+  end RD_6_B;
+
+  architecture Structure of RD_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD6_ipd 	: std_logic := 'X';
+    signal RD6_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_6: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
+                PADI=>RD6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD6_zd         	: std_logic := 'X';
+    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD6_RD6          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD6_ipd,
+        TestSignalName => "RD6",
+        Period => tperiod_RD6,
+        PulseWidthHigh => tpw_RD6_posedge,
+        PulseWidthLow => tpw_RD6_negedge,
+        PeriodData => periodcheckinfo_RD6,
+        Violation => tviol_RD6_RD6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD6_zd 	:= RD6_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
+                           PathDelay => tpd_RD6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD6,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD6,
+                           PathCondition => TRUE)),
+      GlitchData => RD6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_5_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD5 	: VitalDelayType := 0 ns;
+      tpw_RD5_posedge	: VitalDelayType := 0 ns;
+      tpw_RD5_negedge	: VitalDelayType := 0 ns;
+      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD5: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
+
+  end RD_5_B;
+
+  architecture Structure of RD_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD5_ipd 	: std_logic := 'X';
+    signal RD5_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_5: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
+                PADI=>RD5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD5_zd         	: std_logic := 'X';
+    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD5_RD5          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD5_ipd,
+        TestSignalName => "RD5",
+        Period => tperiod_RD5,
+        PulseWidthHigh => tpw_RD5_posedge,
+        PulseWidthLow => tpw_RD5_negedge,
+        PeriodData => periodcheckinfo_RD5,
+        Violation => tviol_RD5_RD5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD5_zd 	:= RD5_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
+                           PathDelay => tpd_RD5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD5,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD5,
+                           PathCondition => TRUE)),
+      GlitchData => RD5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_4_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD4 	: VitalDelayType := 0 ns;
+      tpw_RD4_posedge	: VitalDelayType := 0 ns;
+      tpw_RD4_negedge	: VitalDelayType := 0 ns;
+      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD4: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
+
+  end RD_4_B;
+
+  architecture Structure of RD_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD4_ipd 	: std_logic := 'X';
+    signal RD4_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_4: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
+                PADI=>RD4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD4_zd         	: std_logic := 'X';
+    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD4_RD4          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD4_ipd,
+        TestSignalName => "RD4",
+        Period => tperiod_RD4,
+        PulseWidthHigh => tpw_RD4_posedge,
+        PulseWidthLow => tpw_RD4_negedge,
+        PeriodData => periodcheckinfo_RD4,
+        Violation => tviol_RD4_RD4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD4_zd 	:= RD4_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
+                           PathDelay => tpd_RD4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD4,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD4,
+                           PathCondition => TRUE)),
+      GlitchData => RD4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_3_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD3 	: VitalDelayType := 0 ns;
+      tpw_RD3_posedge	: VitalDelayType := 0 ns;
+      tpw_RD3_negedge	: VitalDelayType := 0 ns;
+      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD3: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
+
+  end RD_3_B;
+
+  architecture Structure of RD_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD3_ipd 	: std_logic := 'X';
+    signal RD3_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_3: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
+                PADI=>RD3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD3_zd         	: std_logic := 'X';
+    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD3_RD3          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD3_ipd,
+        TestSignalName => "RD3",
+        Period => tperiod_RD3,
+        PulseWidthHigh => tpw_RD3_posedge,
+        PulseWidthLow => tpw_RD3_negedge,
+        PeriodData => periodcheckinfo_RD3,
+        Violation => tviol_RD3_RD3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD3_zd 	:= RD3_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
+                           PathDelay => tpd_RD3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD3,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD3,
+                           PathCondition => TRUE)),
+      GlitchData => RD3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_2_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD2 	: VitalDelayType := 0 ns;
+      tpw_RD2_posedge	: VitalDelayType := 0 ns;
+      tpw_RD2_negedge	: VitalDelayType := 0 ns;
+      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD2: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
+
+  end RD_2_B;
+
+  architecture Structure of RD_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD2_ipd 	: std_logic := 'X';
+    signal RD2_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_2: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
+                PADI=>RD2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD2_zd         	: std_logic := 'X';
+    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD2_RD2          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD2_ipd,
+        TestSignalName => "RD2",
+        Period => tperiod_RD2,
+        PulseWidthHigh => tpw_RD2_posedge,
+        PulseWidthLow => tpw_RD2_negedge,
+        PeriodData => periodcheckinfo_RD2,
+        Violation => tviol_RD2_RD2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD2_zd 	:= RD2_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
+                           PathDelay => tpd_RD2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD2,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD2,
+                           PathCondition => TRUE)),
+      GlitchData => RD2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_1_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD1 	: VitalDelayType := 0 ns;
+      tpw_RD1_posedge	: VitalDelayType := 0 ns;
+      tpw_RD1_negedge	: VitalDelayType := 0 ns;
+      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD1: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
+
+  end RD_1_B;
+
+  architecture Structure of RD_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD1_ipd 	: std_logic := 'X';
+    signal RD1_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_1: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
+                PADI=>RD1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD1_zd         	: std_logic := 'X';
+    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD1_RD1          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD1_ipd,
+        TestSignalName => "RD1",
+        Period => tperiod_RD1,
+        PulseWidthHigh => tpw_RD1_posedge,
+        PulseWidthLow => tpw_RD1_negedge,
+        PeriodData => periodcheckinfo_RD1,
+        Violation => tviol_RD1_RD1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD1_zd 	:= RD1_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
+                           PathDelay => tpd_RD1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD1,
+                           PathCondition => TRUE)),
+      GlitchData => RD1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_11_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
+
+  end RA_11_B;
+
+  architecture Structure of RA_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA11_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_11: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
+    VARIABLE RA11_zd         	: std_logic := 'X';
+    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA11_zd 	:= RA11_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA11,
+                           PathCondition => TRUE)),
+      GlitchData => RA11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_10_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
+
+  end RA_10_B;
+
+  architecture Structure of RA_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA10_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_10: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
+    VARIABLE RA10_zd         	: std_logic := 'X';
+    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA10_zd 	:= RA10_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA10,
+                           PathCondition => TRUE)),
+      GlitchData => RA10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
+
+  end RA_9_B;
+
+  architecture Structure of RA_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA9_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_9: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
+    VARIABLE RA9_zd         	: std_logic := 'X';
+    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA9_zd 	:= RA9_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA9,
+                           PathCondition => TRUE)),
+      GlitchData => RA9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
+
+  end RA_8_B;
+
+  architecture Structure of RA_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA8_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_8: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
+    VARIABLE RA8_zd         	: std_logic := 'X';
+    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA8_zd 	:= RA8_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA8,
+                           PathCondition => TRUE)),
+      GlitchData => RA8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
+
+  end RA_7_B;
+
+  architecture Structure of RA_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA7_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_7: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
+    VARIABLE RA7_zd         	: std_logic := 'X';
+    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA7_zd 	:= RA7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA7,
+                           PathCondition => TRUE)),
+      GlitchData => RA7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
+
+  end RA_6_B;
+
+  architecture Structure of RA_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA6_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_6: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
+    VARIABLE RA6_zd         	: std_logic := 'X';
+    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA6_zd 	:= RA6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA6,
+                           PathCondition => TRUE)),
+      GlitchData => RA6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
+
+  end RA_5_B;
+
+  architecture Structure of RA_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA5_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_5: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
+    VARIABLE RA5_zd         	: std_logic := 'X';
+    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA5_zd 	:= RA5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA5,
+                           PathCondition => TRUE)),
+      GlitchData => RA5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
+
+  end RA_4_B;
+
+  architecture Structure of RA_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA4_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_4: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
+    VARIABLE RA4_zd         	: std_logic := 'X';
+    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA4_zd 	:= RA4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA4,
+                           PathCondition => TRUE)),
+      GlitchData => RA4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
+
+  end RA_3_B;
+
+  architecture Structure of RA_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA3_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_3: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
+    VARIABLE RA3_zd         	: std_logic := 'X';
+    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA3_zd 	:= RA3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA3,
+                           PathCondition => TRUE)),
+      GlitchData => RA3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
+
+  end RA_2_B;
+
+  architecture Structure of RA_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA2_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_2: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
+    VARIABLE RA2_zd         	: std_logic := 'X';
+    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA2_zd 	:= RA2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA2,
+                           PathCondition => TRUE)),
+      GlitchData => RA2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
+
+  end RA_1_B;
+
+  architecture Structure of RA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA1_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_1: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
+    VARIABLE RA1_zd         	: std_logic := 'X';
+    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA1_zd 	:= RA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA1,
+                           PathCondition => TRUE)),
+      GlitchData => RA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
+
+  end RA_0_B;
+
+  architecture Structure of RA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA0_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_0: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
+    VARIABLE RA0_zd         	: std_logic := 'X';
+    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA0_zd 	:= RA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA0,
+                           PathCondition => TRUE)),
+      GlitchData => RA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
+
+  end RBA_1_B;
+
+  architecture Structure of RBA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA1_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_1: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RBA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
+    VARIABLE RBA1_zd         	: std_logic := 'X';
+    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA1_zd 	:= RBA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA1,
+                           PathCondition => TRUE)),
+      GlitchData => RBA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
+
+  end RBA_0_B;
+
+  architecture Structure of RBA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA0_out 	: std_logic := 'X';
+
+    component mjiobuf0085
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_0: mjiobuf0085
+      port map (I=>PADDO_ipd, PAD=>RBA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
+    VARIABLE RBA0_zd         	: std_logic := 'X';
+    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA0_zd 	:= RBA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA0,
+                           PathCondition => TRUE)),
+      GlitchData => RBA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0086
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0086 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0086 : ENTITY IS TRUE;
+
+  end mjiobuf0086;
+
+  architecture Structure of mjiobuf0086 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity LEDB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity LEDB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LEDB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; LEDS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
+
+  end LEDB;
+
+  architecture Structure of LEDB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal LEDS_out 	: std_logic := 'X';
+
+    component mjiobuf0086
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    LED_pad: mjiobuf0086
+      port map (I=>PADDO_ipd, PAD=>LEDS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
+    VARIABLE LEDS_zd         	: std_logic := 'X';
+    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    LEDS_zd 	:= LEDS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_LEDS,
+                           PathCondition => TRUE)),
+      GlitchData => LEDS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nFWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nFWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nFWEB";
+
+      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nFWES 	: VitalDelayType := 0 ns;
+      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
+      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nFWES: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
+
+  end nFWEB;
+
+  architecture Structure of nFWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nFWES_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nFWE_pad: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
+    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nFWES_ipd,
+        TestSignalName => "nFWES",
+        Period => tperiod_nFWES,
+        PulseWidthHigh => tpw_nFWES_posedge,
+        PulseWidthLow => tpw_nFWES_negedge,
+        PeriodData => periodcheckinfo_nFWES,
+        Violation => tviol_nFWES_nFWES,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
+                           PathDelay => tpd_nFWES_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0087
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0087 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0087 : ENTITY IS TRUE;
+
+  end mjiobuf0087;
+
+  architecture Structure of mjiobuf0087 is
+    component IBPU
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPU
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity nCRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCRASB";
+
+      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCRASS 	: VitalDelayType := 0 ns;
+      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCRASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
+
+  end nCRASB;
+
+  architecture Structure of nCRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCRASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0087
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCRAS_pad: mjiobuf0087
+      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCRASS_ipd,
+        TestSignalName => "nCRASS",
+        Period => tperiod_nCRASS,
+        PulseWidthHigh => tpw_nCRASS_posedge,
+        PulseWidthLow => tpw_nCRASS_negedge,
+        PeriodData => periodcheckinfo_nCRASS,
+        Violation => tviol_nCRASS_nCRASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
+                           PathDelay => tpd_nCRASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nCCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCCASB";
+
+      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCCASS 	: VitalDelayType := 0 ns;
+      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCCASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
+
+  end nCCASB;
+
+  architecture Structure of nCCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCCASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0087
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCCAS_pad: mjiobuf0087
+      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCCASS_ipd,
+        TestSignalName => "nCCASS",
+        Period => tperiod_nCCASS,
+        PulseWidthHigh => tpw_nCCASS_posedge,
+        PulseWidthLow => tpw_nCCASS_negedge,
+        PeriodData => periodcheckinfo_nCCASS,
+        Violation => tviol_nCCASS_nCCASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
+                           PathDelay => tpd_nCCASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
+
+  end Dout_7_B;
+
+  architecture Structure of Dout_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout7_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_7: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
+    VARIABLE Dout7_zd         	: std_logic := 'X';
+    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout7_zd 	:= Dout7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout7,
+                           PathCondition => TRUE)),
+      GlitchData => Dout7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
+
+  end Dout_6_B;
+
+  architecture Structure of Dout_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout6_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_6: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
+    VARIABLE Dout6_zd         	: std_logic := 'X';
+    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout6_zd 	:= Dout6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout6,
+                           PathCondition => TRUE)),
+      GlitchData => Dout6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
+
+  end Dout_5_B;
+
+  architecture Structure of Dout_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout5_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_5: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
+    VARIABLE Dout5_zd         	: std_logic := 'X';
+    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout5_zd 	:= Dout5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout5,
+                           PathCondition => TRUE)),
+      GlitchData => Dout5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
+
+  end Dout_4_B;
+
+  architecture Structure of Dout_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout4_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_4: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
+    VARIABLE Dout4_zd         	: std_logic := 'X';
+    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout4_zd 	:= Dout4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout4,
+                           PathCondition => TRUE)),
+      GlitchData => Dout4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
+
+  end Dout_3_B;
+
+  architecture Structure of Dout_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout3_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_3: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
+    VARIABLE Dout3_zd         	: std_logic := 'X';
+    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout3_zd 	:= Dout3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout3,
+                           PathCondition => TRUE)),
+      GlitchData => Dout3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
+
+  end Dout_2_B;
+
+  architecture Structure of Dout_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout2_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_2: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
+    VARIABLE Dout2_zd         	: std_logic := 'X';
+    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout2_zd 	:= Dout2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout2,
+                           PathCondition => TRUE)),
+      GlitchData => Dout2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
+
+  end Dout_1_B;
+
+  architecture Structure of Dout_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout1_out 	: std_logic := 'X';
+
+    component mjiobuf0082
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_1: mjiobuf0082
+      port map (I=>PADDO_ipd, PAD=>Dout1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
+    VARIABLE Dout1_zd         	: std_logic := 'X';
+    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout1_zd 	:= Dout1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout1,
+                           PathCondition => TRUE)),
+      GlitchData => Dout1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_7_B";
+
+      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din7 	: VitalDelayType := 0 ns;
+      tpw_Din7_posedge	: VitalDelayType := 0 ns;
+      tpw_Din7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
+
+  end Din_7_B;
+
+  architecture Structure of Din_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_7: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din7_Din7          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din7_ipd,
+        TestSignalName => "Din7",
+        Period => tperiod_Din7,
+        PulseWidthHigh => tpw_Din7_posedge,
+        PulseWidthLow => tpw_Din7_negedge,
+        PeriodData => periodcheckinfo_Din7,
+        Violation => tviol_Din7_Din7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
+                           PathDelay => tpd_Din7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_6_B";
+
+      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din6 	: VitalDelayType := 0 ns;
+      tpw_Din6_posedge	: VitalDelayType := 0 ns;
+      tpw_Din6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
+
+  end Din_6_B;
+
+  architecture Structure of Din_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_6: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din6_Din6          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din6_ipd,
+        TestSignalName => "Din6",
+        Period => tperiod_Din6,
+        PulseWidthHigh => tpw_Din6_posedge,
+        PulseWidthLow => tpw_Din6_negedge,
+        PeriodData => periodcheckinfo_Din6,
+        Violation => tviol_Din6_Din6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
+                           PathDelay => tpd_Din6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_5_B";
+
+      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din5 	: VitalDelayType := 0 ns;
+      tpw_Din5_posedge	: VitalDelayType := 0 ns;
+      tpw_Din5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
+
+  end Din_5_B;
+
+  architecture Structure of Din_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_5: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din5_Din5          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din5_ipd,
+        TestSignalName => "Din5",
+        Period => tperiod_Din5,
+        PulseWidthHigh => tpw_Din5_posedge,
+        PulseWidthLow => tpw_Din5_negedge,
+        PeriodData => periodcheckinfo_Din5,
+        Violation => tviol_Din5_Din5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
+                           PathDelay => tpd_Din5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_4_B";
+
+      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din4 	: VitalDelayType := 0 ns;
+      tpw_Din4_posedge	: VitalDelayType := 0 ns;
+      tpw_Din4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
+
+  end Din_4_B;
+
+  architecture Structure of Din_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_4: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din4_Din4          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din4_ipd,
+        TestSignalName => "Din4",
+        Period => tperiod_Din4,
+        PulseWidthHigh => tpw_Din4_posedge,
+        PulseWidthLow => tpw_Din4_negedge,
+        PeriodData => periodcheckinfo_Din4,
+        Violation => tviol_Din4_Din4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
+                           PathDelay => tpd_Din4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_3_B";
+
+      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din3 	: VitalDelayType := 0 ns;
+      tpw_Din3_posedge	: VitalDelayType := 0 ns;
+      tpw_Din3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
+
+  end Din_3_B;
+
+  architecture Structure of Din_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_3: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din3_Din3          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din3_ipd,
+        TestSignalName => "Din3",
+        Period => tperiod_Din3,
+        PulseWidthHigh => tpw_Din3_posedge,
+        PulseWidthLow => tpw_Din3_negedge,
+        PeriodData => periodcheckinfo_Din3,
+        Violation => tviol_Din3_Din3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
+                           PathDelay => tpd_Din3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_2_B";
+
+      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din2 	: VitalDelayType := 0 ns;
+      tpw_Din2_posedge	: VitalDelayType := 0 ns;
+      tpw_Din2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
+
+  end Din_2_B;
+
+  architecture Structure of Din_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_2: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din2_Din2          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din2_ipd,
+        TestSignalName => "Din2",
+        Period => tperiod_Din2,
+        PulseWidthHigh => tpw_Din2_posedge,
+        PulseWidthLow => tpw_Din2_negedge,
+        PeriodData => periodcheckinfo_Din2,
+        Violation => tviol_Din2_Din2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
+                           PathDelay => tpd_Din2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_1_B";
+
+      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din1 	: VitalDelayType := 0 ns;
+      tpw_Din1_posedge	: VitalDelayType := 0 ns;
+      tpw_Din1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
+
+  end Din_1_B;
+
+  architecture Structure of Din_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din1_Din1          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din1_ipd,
+        TestSignalName => "Din1",
+        Period => tperiod_Din1,
+        PulseWidthHigh => tpw_Din1_posedge,
+        PulseWidthLow => tpw_Din1_negedge,
+        PeriodData => periodcheckinfo_Din1,
+        Violation => tviol_Din1_Din1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
+                           PathDelay => tpd_Din1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_0_B";
+
+      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din0 	: VitalDelayType := 0 ns;
+      tpw_Din0_posedge	: VitalDelayType := 0 ns;
+      tpw_Din0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
+
+  end Din_0_B;
+
+  architecture Structure of Din_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>Din0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din0_Din0          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din0_ipd,
+        TestSignalName => "Din0",
+        Period => tperiod_Din0,
+        PulseWidthHigh => tpw_Din0_posedge,
+        PulseWidthLow => tpw_Din0_negedge,
+        PeriodData => periodcheckinfo_Din0,
+        Violation => tviol_Din0_Din0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
+                           PathDelay => tpd_Din0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_1_B";
+
+      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW1 	: VitalDelayType := 0 ns;
+      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
+
+  end CROW_1_B;
+
+  architecture Structure of CROW_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW1_ipd,
+        TestSignalName => "CROW1",
+        Period => tperiod_CROW1,
+        PulseWidthHigh => tpw_CROW1_posedge,
+        PulseWidthLow => tpw_CROW1_negedge,
+        PeriodData => periodcheckinfo_CROW1,
+        Violation => tviol_CROW1_CROW1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
+                           PathDelay => tpd_CROW1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_0_B";
+
+      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW0 	: VitalDelayType := 0 ns;
+      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
+
+  end CROW_0_B;
+
+  architecture Structure of CROW_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW0_ipd,
+        TestSignalName => "CROW0",
+        Period => tperiod_CROW0,
+        PulseWidthHigh => tpw_CROW0_posedge,
+        PulseWidthLow => tpw_CROW0_negedge,
+        PeriodData => periodcheckinfo_CROW0,
+        Violation => tviol_CROW0_CROW0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
+                           PathDelay => tpd_CROW0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_9_B";
+
+      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin9 	: VitalDelayType := 0 ns;
+      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin9: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
+
+  end MAin_9_B;
+
+  architecture Structure of MAin_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin9_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_9: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin9_ipd,
+        TestSignalName => "MAin9",
+        Period => tperiod_MAin9,
+        PulseWidthHigh => tpw_MAin9_posedge,
+        PulseWidthLow => tpw_MAin9_negedge,
+        PeriodData => periodcheckinfo_MAin9,
+        Violation => tviol_MAin9_MAin9,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
+                           PathDelay => tpd_MAin9_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_8_B";
+
+      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin8 	: VitalDelayType := 0 ns;
+      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin8: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
+
+  end MAin_8_B;
+
+  architecture Structure of MAin_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin8_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_8: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin8_ipd,
+        TestSignalName => "MAin8",
+        Period => tperiod_MAin8,
+        PulseWidthHigh => tpw_MAin8_posedge,
+        PulseWidthLow => tpw_MAin8_negedge,
+        PeriodData => periodcheckinfo_MAin8,
+        Violation => tviol_MAin8_MAin8,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
+                           PathDelay => tpd_MAin8_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_7_B";
+
+      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin7 	: VitalDelayType := 0 ns;
+      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
+
+  end MAin_7_B;
+
+  architecture Structure of MAin_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_7: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin7_ipd,
+        TestSignalName => "MAin7",
+        Period => tperiod_MAin7,
+        PulseWidthHigh => tpw_MAin7_posedge,
+        PulseWidthLow => tpw_MAin7_negedge,
+        PeriodData => periodcheckinfo_MAin7,
+        Violation => tviol_MAin7_MAin7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
+                           PathDelay => tpd_MAin7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_6_B";
+
+      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin6 	: VitalDelayType := 0 ns;
+      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
+
+  end MAin_6_B;
+
+  architecture Structure of MAin_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_6: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin6_ipd,
+        TestSignalName => "MAin6",
+        Period => tperiod_MAin6,
+        PulseWidthHigh => tpw_MAin6_posedge,
+        PulseWidthLow => tpw_MAin6_negedge,
+        PeriodData => periodcheckinfo_MAin6,
+        Violation => tviol_MAin6_MAin6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
+                           PathDelay => tpd_MAin6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_5_B";
+
+      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin5 	: VitalDelayType := 0 ns;
+      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
+
+  end MAin_5_B;
+
+  architecture Structure of MAin_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_5: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin5_ipd,
+        TestSignalName => "MAin5",
+        Period => tperiod_MAin5,
+        PulseWidthHigh => tpw_MAin5_posedge,
+        PulseWidthLow => tpw_MAin5_negedge,
+        PeriodData => periodcheckinfo_MAin5,
+        Violation => tviol_MAin5_MAin5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
+                           PathDelay => tpd_MAin5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_4_B";
+
+      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin4 	: VitalDelayType := 0 ns;
+      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
+
+  end MAin_4_B;
+
+  architecture Structure of MAin_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_4: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin4_ipd,
+        TestSignalName => "MAin4",
+        Period => tperiod_MAin4,
+        PulseWidthHigh => tpw_MAin4_posedge,
+        PulseWidthLow => tpw_MAin4_negedge,
+        PeriodData => periodcheckinfo_MAin4,
+        Violation => tviol_MAin4_MAin4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
+                           PathDelay => tpd_MAin4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_3_B";
+
+      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin3 	: VitalDelayType := 0 ns;
+      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
+
+  end MAin_3_B;
+
+  architecture Structure of MAin_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_3: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin3_ipd,
+        TestSignalName => "MAin3",
+        Period => tperiod_MAin3,
+        PulseWidthHigh => tpw_MAin3_posedge,
+        PulseWidthLow => tpw_MAin3_negedge,
+        PeriodData => periodcheckinfo_MAin3,
+        Violation => tviol_MAin3_MAin3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
+                           PathDelay => tpd_MAin3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_2_B";
+
+      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin2 	: VitalDelayType := 0 ns;
+      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
+
+  end MAin_2_B;
+
+  architecture Structure of MAin_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_2: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin2_ipd,
+        TestSignalName => "MAin2",
+        Period => tperiod_MAin2,
+        PulseWidthHigh => tpw_MAin2_posedge,
+        PulseWidthLow => tpw_MAin2_negedge,
+        PeriodData => periodcheckinfo_MAin2,
+        Violation => tviol_MAin2_MAin2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
+                           PathDelay => tpd_MAin2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_1_B";
+
+      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin1 	: VitalDelayType := 0 ns;
+      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
+
+  end MAin_1_B;
+
+  architecture Structure of MAin_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_1: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin1_ipd,
+        TestSignalName => "MAin1",
+        Period => tperiod_MAin1,
+        PulseWidthHigh => tpw_MAin1_posedge,
+        PulseWidthLow => tpw_MAin1_negedge,
+        PeriodData => periodcheckinfo_MAin1,
+        Violation => tviol_MAin1_MAin1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
+                           PathDelay => tpd_MAin1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_0_B";
+
+      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin0 	: VitalDelayType := 0 ns;
+      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
+
+  end MAin_0_B;
+
+  architecture Structure of MAin_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0084
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_0: mjiobuf0084
+      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin0_ipd,
+        TestSignalName => "MAin0",
+        Period => tperiod_MAin0,
+        PulseWidthHigh => tpw_MAin0_posedge,
+        PulseWidthLow => tpw_MAin0_negedge,
+        PeriodData => periodcheckinfo_MAin0,
+        Violation => tviol_MAin0_MAin0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
+                           PathDelay => tpd_MAin0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RAM2GS
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RAM2GS is
+    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
+          CROW: in Std_logic_vector (1 downto 0); 
+          Din: in Std_logic_vector (7 downto 0); 
+          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
+          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
+          RBA: out Std_logic_vector (1 downto 0); 
+          RA: out Std_logic_vector (11 downto 0); 
+          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
+          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
+          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
+          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
+          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
+
+
+
+  end RAM2GS;
+
+  architecture Structure of RAM2GS is
+    signal FS_1: Std_logic;
+    signal FS_0: Std_logic;
+    signal RCLK_c: Std_logic;
+    signal FS_cry_1: Std_logic;
+    signal FS_17: Std_logic;
+    signal FS_16: Std_logic;
+    signal FS_cry_15: Std_logic;
+    signal FS_15: Std_logic;
+    signal FS_14: Std_logic;
+    signal FS_cry_13: Std_logic;
+    signal FS_13: Std_logic;
+    signal FS_12: Std_logic;
+    signal FS_cry_11: Std_logic;
+    signal FS_11: Std_logic;
+    signal FS_10: Std_logic;
+    signal FS_cry_9: Std_logic;
+    signal FS_9: Std_logic;
+    signal FS_8: Std_logic;
+    signal FS_cry_7: Std_logic;
+    signal FS_7: Std_logic;
+    signal FS_6: Std_logic;
+    signal FS_cry_5: Std_logic;
+    signal FS_5: Std_logic;
+    signal FS_4: Std_logic;
+    signal FS_cry_3: Std_logic;
+    signal FS_3: Std_logic;
+    signal FS_2: Std_logic;
+    signal N_147: Std_logic;
+    signal MAin_c_0: Std_logic;
+    signal CmdEnable17_0_a2_4: Std_logic;
+    signal CmdEnable17_0_a2_3: Std_logic;
+    signal CmdEnable16: Std_logic;
+    signal CmdEnable17: Std_logic;
+    signal C1WR_0_a2: Std_logic;
+    signal ADSubmitted: Std_logic;
+    signal ADSubmitted_r: Std_logic;
+    signal PHI2_c: Std_logic;
+    signal CmdEnable16_0_a2_5: Std_logic;
+    signal CmdEnable16_0_a2_4: Std_logic;
+    signal MAin_c_1: Std_logic;
+    signal C1Submitted: Std_logic;
+    signal C1Submitted_RNO: Std_logic;
+    signal S_1: Std_logic;
+    signal RASr2: Std_logic;
+    signal IS_3: Std_logic;
+    signal CO0: Std_logic;
+    signal N_177_i: Std_logic;
+    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
+    signal CmdEnable: Std_logic;
+    signal un1_CMDWR: Std_logic;
+    signal CmdEnable_s: Std_logic;
+    signal N_128: Std_logic;
+    signal Din_c_5: Std_logic;
+    signal Din_c_3: Std_logic;
+    signal N_152: Std_logic;
+    signal N_133: Std_logic;
+    signal N_132: Std_logic;
+    signal LEDEN: Std_logic;
+    signal N_21_i: Std_logic;
+    signal XOR8MEG18: Std_logic;
+    signal CmdLEDEN: Std_logic;
+    signal PHI2r3: Std_logic;
+    signal PHI2r2: Std_logic;
+    signal InitReady: Std_logic;
+    signal CmdSubmitted: Std_logic;
+    signal CmdSubmitted_1_sqmuxa: Std_logic;
+    signal N_460_0: Std_logic;
+    signal N_136: Std_logic;
+    signal N_43: Std_logic;
+    signal Cmdn8MEGEN: Std_logic;
+    signal CmdEnable16_4: Std_logic;
+    signal n8MEGEN: Std_logic;
+    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
+    signal N_19_i: Std_logic;
+    signal nRRAS_5_u_i_0: Std_logic;
+    signal N_160: Std_logic;
+    signal N_155: Std_logic;
+    signal IS_0: Std_logic;
+    signal Ready: Std_logic;
+    signal N_64_i_i: Std_logic;
+    signal N_24: Std_logic;
+    signal IS_2: Std_logic;
+    signal IS_1: Std_logic;
+    signal N_60_i_i: Std_logic;
+    signal N_56_i: Std_logic;
+    signal N_159_i: Std_logic;
+    signal N_159: Std_logic;
+    signal N_61_i_i: Std_logic;
+    signal RA10s_i: Std_logic;
+    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
+    signal N_126: Std_logic;
+    signal N_51: Std_logic;
+    signal InitReady3: Std_logic;
+    signal N_461_0: Std_logic;
+    signal UFMSDI_ens2_i_a0: Std_logic;
+    signal nCRAS_c: Std_logic;
+    signal CBR: Std_logic;
+    signal UFMSDO_c: Std_logic;
+    signal N_70: Std_logic;
+    signal N_33: Std_logic;
+    signal LED_c: Std_logic;
+    signal un1_Din_4: Std_logic;
+    signal XOR8MEG: Std_logic;
+    signal Din_c_6: Std_logic;
+    signal RA11_2: Std_logic;
+    signal Ready_fast: Std_logic;
+    signal RA_c_11: Std_logic;
+    signal N_171: Std_logic;
+    signal FWEr_fast: Std_logic;
+    signal CASr2: Std_logic;
+    signal RCKEEN_8_u_1: Std_logic;
+    signal RCKEEN_8_u_0_0: Std_logic;
+    signal RCKEEN_8: Std_logic;
+    signal PHI2r: Std_logic;
+    signal RCKEEN: Std_logic;
+    signal RASr3: Std_logic;
+    signal RASr: Std_logic;
+    signal RCKE_2: Std_logic;
+    signal RCKE_c: Std_logic;
+    signal m18_0_a3_3: Std_logic;
+    signal S_0_i_o2_1: Std_logic;
+    signal N_165: Std_logic;
+    signal N_462_0: Std_logic;
+    signal Ready_0_sqmuxa: Std_logic;
+    signal N_463_0: Std_logic;
+    signal nRRAS_0_sqmuxa: Std_logic;
+    signal N_129: Std_logic;
+    signal UFMCLK_r_i_a2_2_2: Std_logic;
+    signal CmdUFMCLK: Std_logic;
+    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
+    signal UFMCLK_c: Std_logic;
+    signal nUFMCS15: Std_logic;
+    signal N_139_i: Std_logic;
+    signal UFMCLK_RNO: Std_logic;
+    signal UFMSDI_r_xx_mm_1: Std_logic;
+    signal UFMSDI_c: Std_logic;
+    signal UFMSDI_RNO: Std_logic;
+    signal nRowColSel: Std_logic;
+    signal RowA_4: Std_logic;
+    signal MAin_c_4: Std_logic;
+    signal Din_c_4: Std_logic;
+    signal nCCAS_c: Std_logic;
+    signal RA_c_4: Std_logic;
+    signal WRD_4: Std_logic;
+    signal WRD_5: Std_logic;
+    signal Bank_7: Std_logic;
+    signal Bank_6: Std_logic;
+    signal Bank_5: Std_logic;
+    signal Bank_2: Std_logic;
+    signal Din_c_7: Std_logic;
+    signal WRD_6: Std_logic;
+    signal C1WR_0_a2_0_11: Std_logic;
+    signal WRD_7: Std_logic;
+    signal Din_c_2: Std_logic;
+    signal Din_c_0: Std_logic;
+    signal XOR8MEG_3_u_0_a3_2: Std_logic;
+    signal Din_c_1: Std_logic;
+    signal XOR8MEG_3: Std_logic;
+    signal N_69: Std_logic;
+    signal N_31: Std_logic;
+    signal N_151: Std_logic;
+    signal g0_1: Std_logic;
+    signal nRCAS_0_sqmuxa_1: Std_logic;
+    signal N_41: Std_logic;
+    signal N_37_i: Std_logic;
+    signal nRCAS_c: Std_logic;
+    signal CASr3: Std_logic;
+    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
+    signal N_28_i_1: Std_logic;
+    signal N_28_i: Std_logic;
+    signal nRCS_c: Std_logic;
+    signal N_24_i: Std_logic;
+    signal nRRAS_c: Std_logic;
+    signal CBR_fast: Std_logic;
+    signal m18_0_a2_1: Std_logic;
+    signal G_17_1: Std_logic;
+    signal FWEr: Std_logic;
+    signal N_39_i: Std_logic;
+    signal nRWE_c: Std_logic;
+    signal N_179: Std_logic;
+    signal nRowColSel_0_0: Std_logic;
+    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
+    signal nUFMCS_c: Std_logic;
+    signal nUFMCS_s_0_N_5_i: Std_logic;
+    signal CmdUFMCS: Std_logic;
+    signal N_95_5: Std_logic;
+    signal N_95_3: Std_logic;
+    signal RowA_0: Std_logic;
+    signal RowA_1: Std_logic;
+    signal MAin_c_5: Std_logic;
+    signal CmdUFMCLK_1_sqmuxa: Std_logic;
+    signal RowA_5: Std_logic;
+    signal un1_FS_14_i_a2_0_1: Std_logic;
+    signal N_137_8: Std_logic;
+    signal N_137_6: Std_logic;
+    signal un1_FS_13_i_a2_1: Std_logic;
+    signal C1WR_0_a2_0_10: Std_logic;
+    signal Bank_1: Std_logic;
+    signal Bank_0: Std_logic;
+    signal MAin_c_7: Std_logic;
+    signal MAin_c_6: Std_logic;
+    signal C1WR_0_a2_0_4: Std_logic;
+    signal C1WR_0_a2_0_3: Std_logic;
+    signal Bank_4: Std_logic;
+    signal Bank_3: Std_logic;
+    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
+    signal MAin_c_3: Std_logic;
+    signal MAin_c_2: Std_logic;
+    signal RowA_2: Std_logic;
+    signal RowA_3: Std_logic;
+    signal CmdUFMSDI: Std_logic;
+    signal CASr: Std_logic;
+    signal CmdEnable16_1: Std_logic;
+    signal m6_0_a2_2: Std_logic;
+    signal WRD_0: Std_logic;
+    signal WRD_1: Std_logic;
+    signal g4_0_0_0: Std_logic;
+    signal MAin_c_9: Std_logic;
+    signal MAin_c_8: Std_logic;
+    signal RowA_8: Std_logic;
+    signal RowA_9: Std_logic;
+    signal nFWE_c: Std_logic;
+    signal CROW_c_1: Std_logic;
+    signal CROW_c_0: Std_logic;
+    signal RBA_c_0: Std_logic;
+    signal RBA_c_1: Std_logic;
+    signal WRD_2: Std_logic;
+    signal WRD_3: Std_logic;
+    signal RA_c_9: Std_logic;
+    signal RDQML_c: Std_logic;
+    signal RD_1_i: Std_logic;
+    signal RowA_6: Std_logic;
+    signal RowA_7: Std_logic;
+    signal RA_c_8: Std_logic;
+    signal RDQMH_c: Std_logic;
+    signal RA_c_0: Std_logic;
+    signal RA_c_1: Std_logic;
+    signal RA_c_7: Std_logic;
+    signal RA_c_2: Std_logic;
+    signal RA_c_6: Std_logic;
+    signal RA_c_3: Std_logic;
+    signal RA_c_5: Std_logic;
+    signal RA_c_10: Std_logic;
+    signal RD_in_0: Std_logic;
+    signal RD_in_7: Std_logic;
+    signal RD_in_6: Std_logic;
+    signal RD_in_5: Std_logic;
+    signal RD_in_4: Std_logic;
+    signal RD_in_3: Std_logic;
+    signal RD_in_2: Std_logic;
+    signal RD_in_1: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI_TSALL: Std_logic;
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+    component PUR
+      port (PUR: in Std_logic);
+    end component;
+    component GSR
+      port (GSR: in Std_logic);
+    end component;
+    component TSALL
+      port (TSALL: in Std_logic);
+    end component;
+    component SLICE_0
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component SLICE_1
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_2
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_3
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_4
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_5
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_6
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_7
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_8
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_9
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_14
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_19
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_20
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component SLICE_21
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_22
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_26
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_29
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_30
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_31
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_32
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_33
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_39
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_41
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_42
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_43
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_44
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_50
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_51
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_52
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_55
+      port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_56
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_57
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_58
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_59
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_60
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_61
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_62
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_63
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_64
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component nRWE_RNO_1_SLICE_65
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component SLICE_66
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_67
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_68
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_69
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_70
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_71
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_72
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_73
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_74
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_75
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_76
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_77
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_78
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_79
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_80
+      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_81
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_82
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_83
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_84
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_85
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_86
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_87
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_88
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_89
+      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_90
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_91
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_92
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_93
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_94
+      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component RD_0_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD0: inout Std_logic);
+    end component;
+    component Dout_0_B
+      port (PADDO: in Std_logic; Dout0: out Std_logic);
+    end component;
+    component PHI2B
+      port (PADDI: out Std_logic; PHI2S: in Std_logic);
+    end component;
+    component UFMSDOB
+      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+    end component;
+    component UFMSDIB
+      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+    end component;
+    component UFMCLKB
+      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+    end component;
+    component nUFMCSB
+      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+    end component;
+    component RDQMLB
+      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+    end component;
+    component RDQMHB
+      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+    end component;
+    component nRCASB
+      port (PADDO: in Std_logic; nRCASS: out Std_logic);
+    end component;
+    component nRRASB
+      port (PADDO: in Std_logic; nRRASS: out Std_logic);
+    end component;
+    component nRWEB
+      port (PADDO: in Std_logic; nRWES: out Std_logic);
+    end component;
+    component RCKEB
+      port (PADDO: in Std_logic; RCKES: out Std_logic);
+    end component;
+    component RCLKB
+      port (PADDI: out Std_logic; RCLKS: in Std_logic);
+    end component;
+    component nRCSB
+      port (PADDO: in Std_logic; nRCSS: out Std_logic);
+    end component;
+    component RD_7_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD7: inout Std_logic);
+    end component;
+    component RD_6_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD6: inout Std_logic);
+    end component;
+    component RD_5_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD5: inout Std_logic);
+    end component;
+    component RD_4_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD4: inout Std_logic);
+    end component;
+    component RD_3_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD3: inout Std_logic);
+    end component;
+    component RD_2_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD2: inout Std_logic);
+    end component;
+    component RD_1_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD1: inout Std_logic);
+    end component;
+    component RA_11_B
+      port (PADDO: in Std_logic; RA11: out Std_logic);
+    end component;
+    component RA_10_B
+      port (PADDO: in Std_logic; RA10: out Std_logic);
+    end component;
+    component RA_9_B
+      port (PADDO: in Std_logic; RA9: out Std_logic);
+    end component;
+    component RA_8_B
+      port (PADDO: in Std_logic; RA8: out Std_logic);
+    end component;
+    component RA_7_B
+      port (PADDO: in Std_logic; RA7: out Std_logic);
+    end component;
+    component RA_6_B
+      port (PADDO: in Std_logic; RA6: out Std_logic);
+    end component;
+    component RA_5_B
+      port (PADDO: in Std_logic; RA5: out Std_logic);
+    end component;
+    component RA_4_B
+      port (PADDO: in Std_logic; RA4: out Std_logic);
+    end component;
+    component RA_3_B
+      port (PADDO: in Std_logic; RA3: out Std_logic);
+    end component;
+    component RA_2_B
+      port (PADDO: in Std_logic; RA2: out Std_logic);
+    end component;
+    component RA_1_B
+      port (PADDO: in Std_logic; RA1: out Std_logic);
+    end component;
+    component RA_0_B
+      port (PADDO: in Std_logic; RA0: out Std_logic);
+    end component;
+    component RBA_1_B
+      port (PADDO: in Std_logic; RBA1: out Std_logic);
+    end component;
+    component RBA_0_B
+      port (PADDO: in Std_logic; RBA0: out Std_logic);
+    end component;
+    component LEDB
+      port (PADDO: in Std_logic; LEDS: out Std_logic);
+    end component;
+    component nFWEB
+      port (PADDI: out Std_logic; nFWES: in Std_logic);
+    end component;
+    component nCRASB
+      port (PADDI: out Std_logic; nCRASS: in Std_logic);
+    end component;
+    component nCCASB
+      port (PADDI: out Std_logic; nCCASS: in Std_logic);
+    end component;
+    component Dout_7_B
+      port (PADDO: in Std_logic; Dout7: out Std_logic);
+    end component;
+    component Dout_6_B
+      port (PADDO: in Std_logic; Dout6: out Std_logic);
+    end component;
+    component Dout_5_B
+      port (PADDO: in Std_logic; Dout5: out Std_logic);
+    end component;
+    component Dout_4_B
+      port (PADDO: in Std_logic; Dout4: out Std_logic);
+    end component;
+    component Dout_3_B
+      port (PADDO: in Std_logic; Dout3: out Std_logic);
+    end component;
+    component Dout_2_B
+      port (PADDO: in Std_logic; Dout2: out Std_logic);
+    end component;
+    component Dout_1_B
+      port (PADDO: in Std_logic; Dout1: out Std_logic);
+    end component;
+    component Din_7_B
+      port (PADDI: out Std_logic; Din7: in Std_logic);
+    end component;
+    component Din_6_B
+      port (PADDI: out Std_logic; Din6: in Std_logic);
+    end component;
+    component Din_5_B
+      port (PADDI: out Std_logic; Din5: in Std_logic);
+    end component;
+    component Din_4_B
+      port (PADDI: out Std_logic; Din4: in Std_logic);
+    end component;
+    component Din_3_B
+      port (PADDI: out Std_logic; Din3: in Std_logic);
+    end component;
+    component Din_2_B
+      port (PADDI: out Std_logic; Din2: in Std_logic);
+    end component;
+    component Din_1_B
+      port (PADDI: out Std_logic; Din1: in Std_logic);
+    end component;
+    component Din_0_B
+      port (PADDI: out Std_logic; Din0: in Std_logic);
+    end component;
+    component CROW_1_B
+      port (PADDI: out Std_logic; CROW1: in Std_logic);
+    end component;
+    component CROW_0_B
+      port (PADDI: out Std_logic; CROW0: in Std_logic);
+    end component;
+    component MAin_9_B
+      port (PADDI: out Std_logic; MAin9: in Std_logic);
+    end component;
+    component MAin_8_B
+      port (PADDI: out Std_logic; MAin8: in Std_logic);
+    end component;
+    component MAin_7_B
+      port (PADDI: out Std_logic; MAin7: in Std_logic);
+    end component;
+    component MAin_6_B
+      port (PADDI: out Std_logic; MAin6: in Std_logic);
+    end component;
+    component MAin_5_B
+      port (PADDI: out Std_logic; MAin5: in Std_logic);
+    end component;
+    component MAin_4_B
+      port (PADDI: out Std_logic; MAin4: in Std_logic);
+    end component;
+    component MAin_3_B
+      port (PADDI: out Std_logic; MAin3: in Std_logic);
+    end component;
+    component MAin_2_B
+      port (PADDI: out Std_logic; MAin2: in Std_logic);
+    end component;
+    component MAin_1_B
+      port (PADDI: out Std_logic; MAin1: in Std_logic);
+    end component;
+    component MAin_0_B
+      port (PADDI: out Std_logic; MAin0: in Std_logic);
+    end component;
+  begin
+    SLICE_0I: SLICE_0
+      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
+                FCO=>FS_cry_1);
+    SLICE_1I: SLICE_1
+      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
+                Q1=>FS_17);
+    SLICE_2I: SLICE_2
+      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
+                Q1=>FS_15, FCO=>FS_cry_15);
+    SLICE_3I: SLICE_3
+      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
+                Q1=>FS_13, FCO=>FS_cry_13);
+    SLICE_4I: SLICE_4
+      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
+                Q1=>FS_11, FCO=>FS_cry_11);
+    SLICE_5I: SLICE_5
+      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
+                Q1=>FS_9, FCO=>FS_cry_9);
+    SLICE_6I: SLICE_6
+      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
+                Q1=>FS_7, FCO=>FS_cry_7);
+    SLICE_7I: SLICE_7
+      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
+                Q1=>FS_5, FCO=>FS_cry_5);
+    SLICE_8I: SLICE_8
+      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
+                Q1=>FS_3, FCO=>FS_cry_3);
+    SLICE_9I: SLICE_9
+      port map (D1=>N_147, C1=>MAin_c_0, B1=>CmdEnable17_0_a2_4, 
+                A1=>CmdEnable17_0_a2_3, D0=>CmdEnable16, C0=>CmdEnable17, 
+                B0=>C1WR_0_a2, A0=>ADSubmitted, DI0=>ADSubmitted_r, 
+                CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted, 
+                F1=>CmdEnable17);
+    SLICE_14I: SLICE_14
+      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
+                D0=>MAin_c_1, C0=>N_147, B0=>C1Submitted, A0=>CmdEnable16, 
+                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
+                Q0=>C1Submitted, F1=>CmdEnable16);
+    SLICE_19I: SLICE_19
+      port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, 
+                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
+                F1=>Ready_0_sqmuxa_0_a3_2);
+    SLICE_20I: SLICE_20
+      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, 
+                B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, 
+                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
+    SLICE_21I: SLICE_21
+      port map (C1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_152, C0=>N_133, 
+                B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
+                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
+    SLICE_22I: SLICE_22
+      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
+                B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_460_0, 
+                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
+    SLICE_26I: SLICE_26
+      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
+                C0=>n8MEGEN, B0=>N_152, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_19_i, 
+                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
+                F1=>Cmdn8MEGEN_4_u_i_0);
+    SLICE_29I: SLICE_29
+      port map (D1=>nRRAS_5_u_i_0, C1=>N_160, B1=>N_155, A1=>IS_0, C0=>N_155, 
+                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
+                Q0=>IS_0, F1=>N_24);
+    SLICE_30I: SLICE_30
+      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, 
+                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
+    SLICE_31I: SLICE_31
+      port map (D1=>N_159, C1=>IS_3, B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, 
+                B0=>IS_2, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
+    SLICE_32I: SLICE_32
+      port map (D1=>UFMSDI_ens2_i_a2_4_2, C1=>N_126, B1=>N_51, A1=>InitReady, 
+                B0=>InitReady, A0=>InitReady3, DI0=>N_461_0, CLK=>RCLK_c, 
+                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
+    SLICE_33I: SLICE_33
+      port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, C0=>UFMSDO_c, B0=>InitReady, 
+                A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
+                Q0=>LEDEN, F1=>LED_c);
+    SLICE_39I: SLICE_39
+      port map (B1=>un1_Din_4, A1=>XOR8MEG, C0=>n8MEGEN, B0=>XOR8MEG, 
+                A0=>Din_c_6, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
+                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
+    SLICE_41I: SLICE_41
+      port map (D1=>S_1, C1=>FWEr_fast, B1=>CO0, A1=>CASr2, D0=>Ready, 
+                C0=>RCKEEN_8_u_1, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, 
+                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
+                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
+    SLICE_42I: SLICE_42
+      port map (D1=>RASr2, C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>RCKEEN, C0=>RASr3, 
+                B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
+                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
+    SLICE_43I: SLICE_43
+      port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, 
+                D0=>InitReady, C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, 
+                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
+                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
+    SLICE_44I: SLICE_44
+      port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_165, A1=>InitReady, 
+                B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_463_0, M1=>nCRAS_c, 
+                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
+                Q1=>RASr);
+    SLICE_50I: SLICE_50
+      port map (C1=>CO0, B1=>S_1, A1=>Ready, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1, 
+                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
+                F1=>nRRAS_0_sqmuxa);
+    SLICE_51I: SLICE_51
+      port map (D1=>N_129, C1=>UFMCLK_r_i_a2_2_2, B1=>CmdUFMCLK, A1=>InitReady, 
+                D0=>UFMCLK_r_i_m4_xx_mm_1, C0=>UFMCLK_c, B0=>nUFMCS15, 
+                A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
+                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
+                Q1=>RASr2);
+    SLICE_52I: SLICE_52
+      port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted, 
+                D0=>UFMSDI_r_xx_mm_1, C0=>UFMSDI_c, B0=>nUFMCS15, A0=>N_139_i, 
+                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
+                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
+    SLICE_55I: SLICE_55
+      port map (C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, M1=>Din_c_5, 
+                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
+    SLICE_56I: SLICE_56
+      port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, C0=>FS_9, 
+                B0=>FS_7, A0=>FS_5, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
+                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
+    SLICE_57I: SLICE_57
+      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
+                D0=>XOR8MEG_3_u_0_a3_2, C0=>N_171, B0=>LEDEN, A0=>Din_c_1, 
+                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
+                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
+    SLICE_58I: SLICE_58
+      port map (C1=>N_51, B1=>InitReady, A1=>FS_8, C0=>UFMSDO_c, B0=>InitReady, 
+                A0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69, 
+                Q0=>n8MEGEN, F1=>N_151);
+    SLICE_59I: SLICE_59
+      port map (D1=>S_1, C1=>Ready, B1=>N_160, A1=>N_155, D0=>g0_1, C0=>S_1, 
+                B0=>nRCAS_0_sqmuxa_1, A0=>N_41, DI0=>N_37_i, CLK=>RCLK_c, 
+                F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
+    SLICE_60I: SLICE_60
+      port map (D1=>CASr2, C1=>CASr3, B1=>CO0, A1=>FWEr_fast, 
+                D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR, 
+                DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
+    SLICE_61I: SLICE_61
+      port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, D0=>IS_0, 
+                C0=>N_155, B0=>N_160, A0=>nRRAS_5_u_i_0, DI0=>N_24_i, 
+                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
+    SLICE_62I: SLICE_62
+      port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR_fast, 
+                D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>G_17_1, A0=>FWEr, 
+                DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, 
+                F1=>nRCAS_0_sqmuxa_1);
+    SLICE_63I: SLICE_63
+      port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, 
+                B0=>N_179, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
+                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
+    SLICE_64I: SLICE_64
+      port map (D1=>N_51, C1=>InitReady, B1=>FS_11, A1=>FS_10, 
+                D0=>nUFMCS_s_0_N_5_i_N_2L1, C0=>nUFMCS_c, B0=>nUFMCS15, 
+                A0=>N_139_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, 
+                F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS15);
+    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
+      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>InitReady, 
+                C0=>m18_0_a3_3, B0=>CO0, A0=>S_1, M0=>Ready, OFX0=>m18_0_a2_1);
+    SLICE_66I: SLICE_66
+      port map (C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, A1=>CmdUFMCS, D0=>N_95_5, 
+                C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1, 
+                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
+                Q1=>RowA_1);
+    SLICE_67I: SLICE_67
+      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_128, A1=>XOR8MEG18, D0=>N_147, 
+                C0=>MAin_c_1, B0=>MAin_c_0, A0=>CmdEnable, M1=>MAin_c_5, 
+                M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, F0=>XOR8MEG18, 
+                Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
+    SLICE_68I: SLICE_68
+      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_14_i_a2_0_1, 
+                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_31, 
+                F1=>un1_FS_14_i_a2_0_1);
+    SLICE_69I: SLICE_69
+      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_13_i_a2_1, 
+                C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_33, 
+                F1=>un1_FS_13_i_a2_1);
+    SLICE_70I: SLICE_70
+      port map (D1=>C1WR_0_a2_0_11, C1=>C1WR_0_a2_0_10, B1=>Bank_1, A1=>Bank_0, 
+                B0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
+                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
+    SLICE_71I: SLICE_71
+      port map (D1=>MAin_c_7, C1=>MAin_c_6, B1=>MAin_c_5, A1=>MAin_c_4, 
+                D0=>C1WR_0_a2_0_4, C0=>C1WR_0_a2_0_3, B0=>Bank_4, A0=>Bank_3, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
+                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
+    SLICE_72I: SLICE_72
+      port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_12, D0=>N_51, 
+                C0=>FS_11, B0=>FS_4, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2, 
+                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
+                Q1=>RowA_3);
+    SLICE_73I: SLICE_73
+      port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, B0=>Ready, 
+                A0=>N_155, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
+                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
+    SLICE_74I: SLICE_74
+      port map (B1=>FS_14, A1=>FS_11, D0=>N_95_5, C0=>N_95_3, B0=>FS_16, 
+                A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
+                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
+    SLICE_75I: SLICE_75
+      port map (C1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, C0=>N_128, B0=>Din_c_5, 
+                A0=>Din_c_1, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
+                Q0=>CASr, F1=>N_128, Q1=>CASr2);
+    SLICE_76I: SLICE_76
+      port map (B1=>Din_c_5, A1=>Din_c_0, D0=>MAin_c_0, C0=>Din_c_3, 
+                B0=>Din_c_1, A0=>CmdEnable16_4, M1=>Din_c_5, M0=>Din_c_4, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
+                F1=>CmdEnable16_4, Q1=>Bank_5);
+    SLICE_77I: SLICE_77
+      port map (B1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>Din_c_6, 
+                B0=>Din_c_2, A0=>CmdEnable16_1, M1=>Din_c_7, M0=>Din_c_6, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
+                F1=>CmdEnable16_1, Q1=>Bank_7);
+    SLICE_78I: SLICE_78
+      port map (B1=>Din_c_5, A1=>Din_c_3, D0=>N_43, C0=>MAin_c_1, B0=>Din_c_6, 
+                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
+                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
+    SLICE_79I: SLICE_79
+      port map (C1=>Ready, B1=>CASr3, A1=>CASr2, D0=>m6_0_a2_2, C0=>S_1, 
+                B0=>CO0, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
+                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
+    SLICE_80I: SLICE_80
+      port map (B1=>CASr3, A1=>CASr2, D0=>g4_0_0_0, C0=>FWEr, B0=>CO0, 
+                A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
+    SLICE_81I: SLICE_81
+      port map (D1=>FS_17, C1=>FS_15, B1=>FS_14, A1=>FS_13, D0=>FS_17, 
+                C0=>FS_15, B0=>FS_13, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c, 
+                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
+                Q1=>FWEr_fast);
+    SLICE_82I: SLICE_82
+      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>CmdLEDEN, A1=>N_128, D0=>Din_c_3, 
+                C0=>Din_c_5, B0=>N_128, A0=>XOR8MEG18, M0=>CASr2, CLK=>RCLK_c, 
+                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
+    SLICE_83I: SLICE_83
+      port map (C1=>IS_3, B1=>IS_2, A1=>IS_1, C0=>IS_2, B0=>IS_1, A0=>IS_0, 
+                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
+    SLICE_84I: SLICE_84
+      port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>FS_10, C0=>FS_7, 
+                B0=>FS_6, A0=>FS_1, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
+    SLICE_85I: SLICE_85
+      port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_0, A1=>Din_c_1, 
+                D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
+                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
+    SLICE_86I: SLICE_86
+      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, 
+                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
+    SLICE_87I: SLICE_87
+      port map (C1=>N_151, B1=>UFMSDI_ens2_i_a0, A1=>CmdUFMSDI, D0=>N_151, 
+                C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_137_8, 
+                F1=>UFMSDI_r_xx_mm_1);
+    SLICE_88I: SLICE_88
+      port map (C1=>nFWE_c, B1=>MAin_c_3, A1=>MAin_c_2, B0=>nFWE_c, 
+                A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
+                Q1=>RowA_7);
+    SLICE_89I: SLICE_89
+      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, 
+                A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
+    SLICE_90I: SLICE_90
+      port map (C1=>MAin_c_1, B1=>MAin_c_0, A1=>N_147, C0=>nRowColSel, 
+                B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>un1_CMDWR);
+    SLICE_91I: SLICE_91
+      port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, 
+                B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
+    SLICE_92I: SLICE_92
+      port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, 
+                B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
+    SLICE_93I: SLICE_93
+      port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, 
+                B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
+    SLICE_94I: SLICE_94
+      port map (B1=>N_155, A1=>Ready, B0=>S_1, A0=>Ready, M0=>IS_0, 
+                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
+                Q0=>RA_c_10, F1=>N_159_i);
+    RD_0_I: RD_0_B
+      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
+    Dout_0_I: Dout_0_B
+      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
+    PHI2I: PHI2B
+      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
+    UFMSDOI: UFMSDOB
+      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
+    UFMSDII: UFMSDIB
+      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
+    UFMCLKI: UFMCLKB
+      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
+    nUFMCSI: nUFMCSB
+      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
+    RDQMLI: RDQMLB
+      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
+    RDQMHI: RDQMHB
+      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
+    nRCASI: nRCASB
+      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
+    nRRASI: nRRASB
+      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
+    nRWEI: nRWEB
+      port map (PADDO=>nRWE_c, nRWES=>nRWE);
+    RCKEI: RCKEB
+      port map (PADDO=>RCKE_c, RCKES=>RCKE);
+    RCLKI: RCLKB
+      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
+    nRCSI: nRCSB
+      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
+    RD_7_I: RD_7_B
+      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
+    RD_6_I: RD_6_B
+      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
+    RD_5_I: RD_5_B
+      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
+    RD_4_I: RD_4_B
+      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
+    RD_3_I: RD_3_B
+      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
+    RD_2_I: RD_2_B
+      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
+    RD_1_I0: RD_1_B
+      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
+    RA_11_I: RA_11_B
+      port map (PADDO=>RA_c_11, RA11=>RA(11));
+    RA_10_I: RA_10_B
+      port map (PADDO=>RA_c_10, RA10=>RA(10));
+    RA_9_I: RA_9_B
+      port map (PADDO=>RA_c_9, RA9=>RA(9));
+    RA_8_I: RA_8_B
+      port map (PADDO=>RA_c_8, RA8=>RA(8));
+    RA_7_I: RA_7_B
+      port map (PADDO=>RA_c_7, RA7=>RA(7));
+    RA_6_I: RA_6_B
+      port map (PADDO=>RA_c_6, RA6=>RA(6));
+    RA_5_I: RA_5_B
+      port map (PADDO=>RA_c_5, RA5=>RA(5));
+    RA_4_I: RA_4_B
+      port map (PADDO=>RA_c_4, RA4=>RA(4));
+    RA_3_I: RA_3_B
+      port map (PADDO=>RA_c_3, RA3=>RA(3));
+    RA_2_I: RA_2_B
+      port map (PADDO=>RA_c_2, RA2=>RA(2));
+    RA_1_I: RA_1_B
+      port map (PADDO=>RA_c_1, RA1=>RA(1));
+    RA_0_I: RA_0_B
+      port map (PADDO=>RA_c_0, RA0=>RA(0));
+    RBA_1_I: RBA_1_B
+      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
+    RBA_0_I: RBA_0_B
+      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
+    LEDI: LEDB
+      port map (PADDO=>LED_c, LEDS=>LED);
+    nFWEI: nFWEB
+      port map (PADDI=>nFWE_c, nFWES=>nFWE);
+    nCRASI: nCRASB
+      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
+    nCCASI: nCCASB
+      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
+    Dout_7_I: Dout_7_B
+      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
+    Dout_6_I: Dout_6_B
+      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
+    Dout_5_I: Dout_5_B
+      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
+    Dout_4_I: Dout_4_B
+      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
+    Dout_3_I: Dout_3_B
+      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
+    Dout_2_I: Dout_2_B
+      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
+    Dout_1_I: Dout_1_B
+      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
+    Din_7_I: Din_7_B
+      port map (PADDI=>Din_c_7, Din7=>Din(7));
+    Din_6_I: Din_6_B
+      port map (PADDI=>Din_c_6, Din6=>Din(6));
+    Din_5_I: Din_5_B
+      port map (PADDI=>Din_c_5, Din5=>Din(5));
+    Din_4_I: Din_4_B
+      port map (PADDI=>Din_c_4, Din4=>Din(4));
+    Din_3_I: Din_3_B
+      port map (PADDI=>Din_c_3, Din3=>Din(3));
+    Din_2_I: Din_2_B
+      port map (PADDI=>Din_c_2, Din2=>Din(2));
+    Din_1_I: Din_1_B
+      port map (PADDI=>Din_c_1, Din1=>Din(1));
+    Din_0_I: Din_0_B
+      port map (PADDI=>Din_c_0, Din0=>Din(0));
+    CROW_1_I: CROW_1_B
+      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
+    CROW_0_I: CROW_0_B
+      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
+    MAin_9_I: MAin_9_B
+      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
+    MAin_8_I: MAin_8_B
+      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
+    MAin_7_I: MAin_7_B
+      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
+    MAin_6_I: MAin_6_B
+      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
+    MAin_5_I: MAin_5_B
+      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
+    MAin_4_I: MAin_4_B
+      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
+    MAin_3_I: MAin_3_B
+      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
+    MAin_2_I: MAin_2_B
+      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
+    MAin_1_I: MAin_1_B
+      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
+    MAin_0_I: MAin_0_B
+      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
+    VHI_INST: VHI
+      port map (Z=>VCCI);
+    PUR_INST: PUR
+      port map (PUR=>VCCI);
+    GSR_INST: GSR
+      port map (GSR=>VCCI);
+    VLO_INST: VLO
+      port map (Z=>GNDI_TSALL);
+    TSALL_INST: TSALL
+      port map (TSALL=>GNDI_TSALL);
+  end Structure;
+
+
+
+  library IEEE, vital2000, MACHXO;
+  configuration Structure_CON of RAM2GS is
+    for Structure
+    end for;
+  end Structure_CON;
+
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf
index 88865b5..18e3f29 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf
@@ -1,2922 +1,2922 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:47 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1\/SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_")
-    (INSTANCE RD\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_")
-    (INSTANCE Dout\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2")
-    (INSTANCE PHI2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2) (1250:1250:1250))
-      (WIDTH (negedge PHI2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDO")
-    (INSTANCE UFMSDO_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDO) (1250:1250:1250))
-      (WIDTH (negedge UFMSDO) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI")
-    (INSTANCE UFMSDI_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK")
-    (INSTANCE UFMCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCS")
-    (INSTANCE nUFMCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQML")
-    (INSTANCE RDQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMH")
-    (INSTANCE RDQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCAS")
-    (INSTANCE nRCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRAS")
-    (INSTANCE nRRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE")
-    (INSTANCE RCKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLK")
-    (INSTANCE RCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLK) (1250:1250:1250))
-      (WIDTH (negedge RCLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCS")
-    (INSTANCE nRCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_")
-    (INSTANCE RD\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_")
-    (INSTANCE RD\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_")
-    (INSTANCE RD\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_")
-    (INSTANCE RD\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_")
-    (INSTANCE RD\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_")
-    (INSTANCE RD\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_")
-    (INSTANCE RD\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_")
-    (INSTANCE RBA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_")
-    (INSTANCE RBA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LED")
-    (INSTANCE LED_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWE")
-    (INSTANCE nFWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWE) (1250:1250:1250))
-      (WIDTH (negedge nFWE) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRAS")
-    (INSTANCE nCRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRAS) (1250:1250:1250))
-      (WIDTH (negedge nCRAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCAS")
-    (INSTANCE nCCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCAS) (1250:1250:1250))
-      (WIDTH (negedge nCCAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_")
-    (INSTANCE Dout\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_")
-    (INSTANCE Dout\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_")
-    (INSTANCE Dout\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_")
-    (INSTANCE Dout\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_")
-    (INSTANCE Dout\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_")
-    (INSTANCE Dout\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_")
-    (INSTANCE Dout\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_")
-    (INSTANCE Din\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_")
-    (INSTANCE Din\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_")
-    (INSTANCE Din\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_")
-    (INSTANCE Din\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_")
-    (INSTANCE Din\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_")
-    (INSTANCE Din\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_")
-    (INSTANCE Din\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_")
-    (INSTANCE Din\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_")
-    (INSTANCE CROW\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_")
-    (INSTANCE CROW\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_")
-    (INSTANCE MAin\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_")
-    (INSTANCE MAin\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_")
-    (INSTANCE MAin\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_")
-    (INSTANCE MAin\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_")
-    (INSTANCE MAin\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_")
-    (INSTANCE MAin\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_")
-    (INSTANCE MAin\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_")
-    (INSTANCE MAin\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_")
-    (INSTANCE MAin\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_")
-    (INSTANCE MAin\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0))
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-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57/F1 SLICE_57/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/F0 SLICE_59/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 SLICE_59/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/F1 SLICE_59/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/Q0 SLICE_60/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/Q0 SLICE_63/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/Q0 SLICE_79/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94/F0 SLICE_60/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78/Q1 SLICE_62/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78/Q1 SLICE_80/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/F0 SLICE_62/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/Q0 SLICE_62/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/Q0 SLICE_63/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/Q0 SLICE_80/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63/F1 SLICE_63/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/F1 SLICE_64/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/Q0 SLICE_64/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q1 SLICE_66/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/F0 SLICE_74/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74/F1 SLICE_66/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/Q0 SLICE_90/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/Q1 SLICE_91/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/Q1 SLICE_93/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/F1 SLICE_68/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87/F0 SLICE_68/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87/F0 SLICE_69/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84/F0 SLICE_68/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84/F0 SLICE_69/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69/F1 SLICE_69/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/Q1 SLICE_70/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70/Q0 SLICE_70/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F1 SLICE_71/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/Q1 SLICE_71/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/F1 SLICE_72/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72/Q0 SLICE_92/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72/Q1 SLICE_93/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74/Q0 SLICE_87/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F1 SLICE_77/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/F1 SLICE_80/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/Q0 SLICE_92/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_88/Q1 SLICE_91/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:57:15 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1\/SLICE_65)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_")
+    (INSTANCE RD\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_")
+    (INSTANCE Dout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2")
+    (INSTANCE PHI2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2) (1250:1250:1250))
+      (WIDTH (negedge PHI2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDO")
+    (INSTANCE UFMSDO_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDO) (1250:1250:1250))
+      (WIDTH (negedge UFMSDO) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDI")
+    (INSTANCE UFMSDI_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLK")
+    (INSTANCE UFMCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCS")
+    (INSTANCE nUFMCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQML")
+    (INSTANCE RDQML_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMH")
+    (INSTANCE RDQMH_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCAS")
+    (INSTANCE nRCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRAS")
+    (INSTANCE nRRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE")
+    (INSTANCE nRWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKE")
+    (INSTANCE RCKE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLK")
+    (INSTANCE RCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLK) (1250:1250:1250))
+      (WIDTH (negedge RCLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCS")
+    (INSTANCE nRCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_")
+    (INSTANCE RD\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_")
+    (INSTANCE RD\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_")
+    (INSTANCE RD\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_")
+    (INSTANCE RD\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_")
+    (INSTANCE RD\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_")
+    (INSTANCE RD\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_")
+    (INSTANCE RD\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_")
+    (INSTANCE RA\[11\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_")
+    (INSTANCE RA\[10\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_")
+    (INSTANCE RA\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_")
+    (INSTANCE RA\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_")
+    (INSTANCE RA\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_")
+    (INSTANCE RA\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_")
+    (INSTANCE RA\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_")
+    (INSTANCE RA\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_")
+    (INSTANCE RA\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_")
+    (INSTANCE RA\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_")
+    (INSTANCE RA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_")
+    (INSTANCE RA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_")
+    (INSTANCE RBA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_")
+    (INSTANCE RBA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LED")
+    (INSTANCE LED_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWE")
+    (INSTANCE nFWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWE) (1250:1250:1250))
+      (WIDTH (negedge nFWE) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRAS")
+    (INSTANCE nCRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRAS) (1250:1250:1250))
+      (WIDTH (negedge nCRAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCAS")
+    (INSTANCE nCCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCAS) (1250:1250:1250))
+      (WIDTH (negedge nCCAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_")
+    (INSTANCE Dout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_")
+    (INSTANCE Dout\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_")
+    (INSTANCE Dout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_")
+    (INSTANCE Dout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_")
+    (INSTANCE Dout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_")
+    (INSTANCE Dout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_")
+    (INSTANCE Dout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_")
+    (INSTANCE Din\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_")
+    (INSTANCE Din\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_")
+    (INSTANCE Din\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_")
+    (INSTANCE Din\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_")
+    (INSTANCE Din\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_")
+    (INSTANCE Din\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_")
+    (INSTANCE Din\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_")
+    (INSTANCE Din\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_")
+    (INSTANCE CROW\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_")
+    (INSTANCE CROW\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_")
+    (INSTANCE MAin\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_")
+    (INSTANCE MAin\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_")
+    (INSTANCE MAin\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_")
+    (INSTANCE MAin\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_")
+    (INSTANCE MAin\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_")
+    (INSTANCE MAin\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_")
+    (INSTANCE MAin\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_")
+    (INSTANCE MAin\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_")
+    (INSTANCE MAin\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_")
+    (INSTANCE MAin\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_72/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_74/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_81/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_87/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_87/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_84/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_56/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_69/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_72/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_68/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_9/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_67/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F1 SLICE_90/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78/F0 SLICE_9/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85/F1 SLICE_9/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_9/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F1 SLICE_20/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/F0 SLICE_9/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/Q0 SLICE_20/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_41/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/Q0 SLICE_94/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_43/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_61/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_62/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_51/Q1 SLICE_73/A1 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_31/Q0 SLICE_31/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31/Q0 SLICE_83/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_41/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_60/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_63/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_73/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_79/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_80/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/F1 SLICE_43/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/F1 SLICE_44/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20/Q0 SLICE_67/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90/F1 SLICE_20/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_21/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_67/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21/F1 SLICE_26/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_82/F1 SLICE_21/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/F0 SLICE_82/A0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_41/Q1 SLICE_52/C1 (0:0:0)(0:0:0))
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+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57/F1 SLICE_57/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80/F0 SLICE_59/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/F1 SLICE_59/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59/F1 SLICE_59/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82/Q0 SLICE_60/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82/Q0 SLICE_63/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82/Q0 SLICE_79/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94/F0 SLICE_60/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78/Q1 SLICE_62/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_78/Q1 SLICE_80/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79/F0 SLICE_62/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/Q0 SLICE_62/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/Q0 SLICE_63/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/Q0 SLICE_80/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63/F1 SLICE_63/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66/F1 SLICE_64/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64/Q0 SLICE_64/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73/Q1 SLICE_66/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/F0 SLICE_74/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74/F1 SLICE_66/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66/Q0 SLICE_90/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_66/Q1 SLICE_91/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/Q1 SLICE_93/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68/F1 SLICE_68/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87/F0 SLICE_68/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87/F0 SLICE_69/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84/F0 SLICE_68/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_84/F0 SLICE_69/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69/F1 SLICE_69/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/Q1 SLICE_70/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_70/Q0 SLICE_70/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F1 SLICE_71/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_71/Q1 SLICE_71/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_81/F1 SLICE_72/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72/Q0 SLICE_92/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_72/Q1 SLICE_93/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_74/Q0 SLICE_87/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_77/F1 SLICE_77/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80/F1 SLICE_80/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0))
+        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/Q0 SLICE_92/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_88/Q1 SLICE_91/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo
index 2bd84fc..ddc55d0 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo
@@ -1,3540 +1,3540 @@
-
-// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
-// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd 
-// Netlist created on Wed Aug 16 04:50:46 2023
-// Netlist written on Wed Aug 16 04:50:47 2023
-// Design is for device LCMXO640C
-// Design is for package TQFP100
-// Design is for performance grade 3
-
-`timescale 1 ns / 1 ps
-
-module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
-                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
-                UFMCLK, UFMSDI, UFMSDO );
-  input  PHI2;
-  input  [9:0] MAin;
-  input  [1:0] CROW;
-  input  [7:0] Din;
-  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
-  output [7:0] Dout;
-  output LED;
-  output [1:0] RBA;
-  output [11:0] RA;
-  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
-  inout  [7:0] RD;
-  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
-         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
-         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
-         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
-         \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, 
-         CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, 
-         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
-         \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , 
-         CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
-         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, 
-         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, 
-         CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
-         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
-         N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , 
-         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, 
-         UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, 
-         UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, 
-         un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, 
-         FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, 
-         RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, 
-         N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, 
-         UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, 
-         nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, 
-         nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , 
-         \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , 
-         \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , 
-         \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, 
-         N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, 
-         RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, 
-         CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, 
-         nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, 
-         CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , 
-         CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, 
-         un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , 
-         \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , 
-         UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , 
-         CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , 
-         g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, 
-         \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , 
-         \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, 
-         \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , 
-         \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
-         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
-
-  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
-    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
-  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
-  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
-  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
-  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
-  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
-    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
-  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
-    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
-  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
-    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
-  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
-    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
-  SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), 
-    .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), 
-    .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
-    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
-  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
-    .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), 
-    .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
-    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
-  SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
-    .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
-  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
-    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
-    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
-  SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), 
-    .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
-  SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
-    .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), 
-    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
-  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
-    .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), 
-    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
-    .F1(Cmdn8MEGEN_4_u_i_0));
-  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), 
-    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
-    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
-  SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
-    .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
-    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
-  SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), 
-    .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
-    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
-  SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), 
-    .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), 
-    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
-  SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), 
-    .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
-    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
-  SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), 
-    .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), 
-    .Q0(\RA_c[11] ), .F1(N_171));
-  SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), 
-    .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
-    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
-    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
-  SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), 
-    .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), 
-    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
-  SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), 
-    .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
-    .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
-    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
-  SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), 
-    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), 
-    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
-    .F1(Ready_0_sqmuxa), .Q1(RASr));
-  SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), 
-    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
-    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
-  SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), 
-    .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), 
-    .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), 
-    .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
-  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
-    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), 
-    .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
-    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
-  SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), 
-    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
-    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
-  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
-    .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
-    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
-  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), 
-    .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
-    .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
-  SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), 
-    .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
-    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
-  SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), 
-    .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), 
-    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
-  SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), 
-    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
-    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
-  SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), 
-    .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), 
-    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
-  SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), 
-    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), 
-    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
-    .F1(nRCAS_0_sqmuxa_1));
-  SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
-    .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), 
-    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
-    .F1(N_179));
-  SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), 
-    .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), 
-    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
-    .F1(nUFMCS15));
-  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
-    .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), 
-    .M0(Ready), .OFX0(m18_0_a2_1));
-  SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), 
-    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
-    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
-    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
-  SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), 
-    .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), 
-    .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
-    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
-    .Q1(\RowA[5] ));
-  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), 
-    .F1(un1_FS_14_i_a2_0_1));
-  SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), 
-    .F1(un1_FS_13_i_a2_1));
-  SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), 
-    .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
-    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
-    .Q1(\Bank[1] ));
-  SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), 
-    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), 
-    .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
-    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
-  SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), 
-    .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
-    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
-    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
-  SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
-    .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
-    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
-    .F1(N_155), .Q1(CmdUFMCS));
-  SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), 
-    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
-  SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
-    .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), 
-    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
-  SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), 
-    .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), 
-    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
-    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
-  SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
-    .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
-    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
-  SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), 
-    .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), 
-    .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), 
-    .Q1(CBR_fast));
-  SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), 
-    .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
-    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
-  SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), 
-    .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
-    .Q1(\RowA[9] ));
-  SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), 
-    .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), 
-    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
-    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
-  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), 
-    .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), 
-    .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), 
-    .F1(N_132));
-  SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), 
-    .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
-    .Q1(\RBA_c[1] ));
-  SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), 
-    .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), 
-    .F1(UFMSDI_ens2_i_a2_4_2));
-  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), 
-    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), 
-    .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
-    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
-  SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
-  SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), 
-    .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), 
-    .F1(UFMSDI_r_xx_mm_1));
-  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), 
-    .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
-    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
-  SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
-  SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), 
-    .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), 
-    .F1(un1_CMDWR));
-  SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
-    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
-    .F1(\RA_c[7] ));
-  SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
-    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
-    .F1(\RA_c[6] ));
-  SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
-    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
-    .F1(\RA_c[5] ));
-  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), 
-    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
-    .Q0(\RA_c[10] ), .F1(N_159_i));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
-    .RD0(RD[0]));
-  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
-  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
-  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
-  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
-  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
-  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
-  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
-  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
-  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
-  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
-  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
-  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
-  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
-  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
-    .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
-    .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
-    .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
-    .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
-    .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
-    .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
-    .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
-  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
-  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
-  LED LED_I( .PADDO(LED_c), .LED(LED));
-  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
-  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
-  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
-  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
-  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
-  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
-  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
-  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
-  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
-  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
-  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
-  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
-  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
-  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
-  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
-  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
-  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
-  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
-  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
-  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
-  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
-  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
-  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
-  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
-  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
-  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
-  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
-  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
-  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
-  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
-  VHI VHI_INST( .Z(VCCI));
-  PUR PUR_INST( .PUR(VCCI));
-  GSR GSR_INST( .GSR(VCCI));
-  VLO VLO_INST( .Z(GNDI_TSALL));
-  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
-endmodule
-
-module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
-         A1_dly, CLK_dly, A0_dly;
-
-  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
-    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-  endspecify
-
-endmodule
-
-module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module vcc ( output PWR1 );
-
-  VHI INST1( .Z(PWR1));
-endmodule
-
-module gnd ( output PWR0 );
-
-  VLO INST1( .Z(PWR0));
-endmodule
-
-module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h300a;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
-  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
-    .CO1());
-
-  specify
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h5002;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
-
-  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut4 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40002 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
-module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40003 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40004 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40005 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40006 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
-         CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(\SLICE_20/SLICE_20_K1_H1 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
-  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
-    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
-  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40012 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40014 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40017 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40022 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40026 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40027 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40028 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40039 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40040 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40050 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40053 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
-    OFX0 );
-  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
-         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
-
-  lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
-  lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
-  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
-    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
-    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (C1 => OFX0) = (0:0:0,0:0:0);
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40056 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
-
-  lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
-
-  lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
-
-  lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40066 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40071 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40072 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, M0_dly, CLK_dly;
-
-  lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40073 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40074 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40075 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40076 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
-
-  lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
-
-  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
-
-  specify
-    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD0) = (0:0:0,0:0:0);
-    (RD0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD0, 0:0:0);
-    $width (negedge RD0, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf ( input I, T, output Z, PAD, input PADI );
-
-  IB INST1( .I(PADI), .O(Z));
-  OBW INST2( .I(I), .T(T), .O(PAD));
-endmodule
-
-module Dout_0_ ( input PADDO, output Dout0 );
-
-  mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
-
-  specify
-    (PADDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0082 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module PHI2 ( output PADDI, input PHI2 );
-
-  mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2));
-
-  specify
-    (PHI2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge PHI2, 0:0:0);
-    $width (negedge PHI2, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0083 ( output Z, input PAD );
-
-  IBPD INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDO ( output PADDI, input UFMSDO );
-
-  mjiobuf0084 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
-
-  specify
-    (UFMSDO => PADDI) = (0:0:0,0:0:0);
-    $width (posedge UFMSDO, 0:0:0);
-    $width (negedge UFMSDO, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0084 ( output Z, input PAD );
-
-  IB INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDI ( input PADDO, output UFMSDI );
-
-  mjiobuf0085 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
-
-  specify
-    (PADDO => UFMSDI) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0085 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module UFMCLK ( input PADDO, output UFMCLK );
-
-  mjiobuf0085 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
-
-  specify
-    (PADDO => UFMCLK) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS ( input PADDO, output nUFMCS );
-
-  mjiobuf0085 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
-
-  specify
-    (PADDO => nUFMCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQML ( input PADDO, output RDQML );
-
-  mjiobuf0085 RDQML_pad( .I(PADDO), .PAD(RDQML));
-
-  specify
-    (PADDO => RDQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQMH ( input PADDO, output RDQMH );
-
-  mjiobuf0085 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
-
-  specify
-    (PADDO => RDQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS ( input PADDO, output nRCAS );
-
-  mjiobuf0085 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
-
-  specify
-    (PADDO => nRCAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS ( input PADDO, output nRRAS );
-
-  mjiobuf0085 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
-
-  specify
-    (PADDO => nRRAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE ( input PADDO, output nRWE );
-
-  mjiobuf0085 nRWE_pad( .I(PADDO), .PAD(nRWE));
-
-  specify
-    (PADDO => nRWE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE ( input PADDO, output RCKE );
-
-  mjiobuf0085 RCKE_pad( .I(PADDO), .PAD(RCKE));
-
-  specify
-    (PADDO => RCKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCLK ( output PADDI, input RCLK );
-
-  mjiobuf0084 RCLK_pad( .Z(PADDI), .PAD(RCLK));
-
-  specify
-    (RCLK => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RCLK, 0:0:0);
-    $width (negedge RCLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS ( input PADDO, output nRCS );
-
-  mjiobuf0085 nRCS_pad( .I(PADDO), .PAD(nRCS));
-
-  specify
-    (PADDO => nRCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
-
-  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
-
-  specify
-    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD7) = (0:0:0,0:0:0);
-    (RD7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD7, 0:0:0);
-    $width (negedge RD7, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
-
-  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
-
-  specify
-    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD6) = (0:0:0,0:0:0);
-    (RD6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD6, 0:0:0);
-    $width (negedge RD6, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
-
-  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
-
-  specify
-    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD5) = (0:0:0,0:0:0);
-    (RD5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD5, 0:0:0);
-    $width (negedge RD5, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
-
-  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
-
-  specify
-    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD4) = (0:0:0,0:0:0);
-    (RD4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD4, 0:0:0);
-    $width (negedge RD4, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
-
-  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
-
-  specify
-    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD3) = (0:0:0,0:0:0);
-    (RD3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD3, 0:0:0);
-    $width (negedge RD3, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
-
-  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
-
-  specify
-    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD2) = (0:0:0,0:0:0);
-    (RD2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD2, 0:0:0);
-    $width (negedge RD2, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
-
-  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
-
-  specify
-    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD1) = (0:0:0,0:0:0);
-    (RD1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD1, 0:0:0);
-    $width (negedge RD1, 0:0:0);
-  endspecify
-
-endmodule
-
-module RA_11_ ( input PADDO, output RA11 );
-
-  mjiobuf0085 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
-
-  specify
-    (PADDO => RA11) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10_ ( input PADDO, output RA10 );
-
-  mjiobuf0085 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
-
-  specify
-    (PADDO => RA10) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_9_ ( input PADDO, output RA9 );
-
-  mjiobuf0085 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
-
-  specify
-    (PADDO => RA9) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_8_ ( input PADDO, output RA8 );
-
-  mjiobuf0085 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
-
-  specify
-    (PADDO => RA8) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_7_ ( input PADDO, output RA7 );
-
-  mjiobuf0085 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
-
-  specify
-    (PADDO => RA7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_6_ ( input PADDO, output RA6 );
-
-  mjiobuf0085 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
-
-  specify
-    (PADDO => RA6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_5_ ( input PADDO, output RA5 );
-
-  mjiobuf0085 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
-
-  specify
-    (PADDO => RA5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_4_ ( input PADDO, output RA4 );
-
-  mjiobuf0085 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
-
-  specify
-    (PADDO => RA4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_3_ ( input PADDO, output RA3 );
-
-  mjiobuf0085 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
-
-  specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2_ ( input PADDO, output RA2 );
-
-  mjiobuf0085 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
-
-  specify
-    (PADDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_1_ ( input PADDO, output RA1 );
-
-  mjiobuf0085 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
-
-  specify
-    (PADDO => RA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_0_ ( input PADDO, output RA0 );
-
-  mjiobuf0085 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
-
-  specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1_ ( input PADDO, output RBA1 );
-
-  mjiobuf0085 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
-
-  specify
-    (PADDO => RBA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_0_ ( input PADDO, output RBA0 );
-
-  mjiobuf0085 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
-
-  specify
-    (PADDO => RBA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module LED ( input PADDO, output LED );
-
-  mjiobuf0086 LED_pad( .I(PADDO), .PAD(LED));
-
-  specify
-    (PADDO => LED) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0086 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module nFWE ( output PADDI, input nFWE );
-
-  mjiobuf0084 nFWE_pad( .Z(PADDI), .PAD(nFWE));
-
-  specify
-    (nFWE => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nFWE, 0:0:0);
-    $width (negedge nFWE, 0:0:0);
-  endspecify
-
-endmodule
-
-module nCRAS ( output PADDI, input nCRAS );
-
-  mjiobuf0087 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
-
-  specify
-    (nCRAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCRAS, 0:0:0);
-    $width (negedge nCRAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0087 ( output Z, input PAD );
-
-  IBPU INST1( .I(PAD), .O(Z));
-endmodule
-
-module nCCAS ( output PADDI, input nCCAS );
-
-  mjiobuf0087 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
-
-  specify
-    (nCCAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCCAS, 0:0:0);
-    $width (negedge nCCAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_7_ ( input PADDO, output Dout7 );
-
-  mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
-
-  specify
-    (PADDO => Dout7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_6_ ( input PADDO, output Dout6 );
-
-  mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
-
-  specify
-    (PADDO => Dout6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_5_ ( input PADDO, output Dout5 );
-
-  mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
-
-  specify
-    (PADDO => Dout5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_4_ ( input PADDO, output Dout4 );
-
-  mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
-
-  specify
-    (PADDO => Dout4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input PADDO, output Dout3 );
-
-  mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
-
-  specify
-    (PADDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input PADDO, output Dout2 );
-
-  mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
-
-  specify
-    (PADDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input PADDO, output Dout1 );
-
-  mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
-
-  specify
-    (PADDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7_ ( output PADDI, input Din7 );
-
-  mjiobuf0084 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
-
-  specify
-    (Din7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din7, 0:0:0);
-    $width (negedge Din7, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6_ ( output PADDI, input Din6 );
-
-  mjiobuf0084 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
-
-  specify
-    (Din6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din6, 0:0:0);
-    $width (negedge Din6, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5_ ( output PADDI, input Din5 );
-
-  mjiobuf0084 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
-
-  specify
-    (Din5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din5, 0:0:0);
-    $width (negedge Din5, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4_ ( output PADDI, input Din4 );
-
-  mjiobuf0084 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
-
-  specify
-    (Din4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din4, 0:0:0);
-    $width (negedge Din4, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3_ ( output PADDI, input Din3 );
-
-  mjiobuf0084 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
-
-  specify
-    (Din3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din3, 0:0:0);
-    $width (negedge Din3, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2_ ( output PADDI, input Din2 );
-
-  mjiobuf0084 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
-
-  specify
-    (Din2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din2, 0:0:0);
-    $width (negedge Din2, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_1_ ( output PADDI, input Din1 );
-
-  mjiobuf0084 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
-
-  specify
-    (Din1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din1, 0:0:0);
-    $width (negedge Din1, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_0_ ( output PADDI, input Din0 );
-
-  mjiobuf0084 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
-
-  specify
-    (Din0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din0, 0:0:0);
-    $width (negedge Din0, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_1_ ( output PADDI, input CROW1 );
-
-  mjiobuf0084 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
-
-  specify
-    (CROW1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW1, 0:0:0);
-    $width (negedge CROW1, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_0_ ( output PADDI, input CROW0 );
-
-  mjiobuf0084 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
-
-  specify
-    (CROW0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW0, 0:0:0);
-    $width (negedge CROW0, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_9_ ( output PADDI, input MAin9 );
-
-  mjiobuf0084 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
-
-  specify
-    (MAin9 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin9, 0:0:0);
-    $width (negedge MAin9, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_8_ ( output PADDI, input MAin8 );
-
-  mjiobuf0084 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
-
-  specify
-    (MAin8 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin8, 0:0:0);
-    $width (negedge MAin8, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_7_ ( output PADDI, input MAin7 );
-
-  mjiobuf0084 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
-
-  specify
-    (MAin7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin7, 0:0:0);
-    $width (negedge MAin7, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_6_ ( output PADDI, input MAin6 );
-
-  mjiobuf0084 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
-
-  specify
-    (MAin6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin6, 0:0:0);
-    $width (negedge MAin6, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_5_ ( output PADDI, input MAin5 );
-
-  mjiobuf0084 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
-
-  specify
-    (MAin5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin5, 0:0:0);
-    $width (negedge MAin5, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_4_ ( output PADDI, input MAin4 );
-
-  mjiobuf0084 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
-
-  specify
-    (MAin4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin4, 0:0:0);
-    $width (negedge MAin4, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_3_ ( output PADDI, input MAin3 );
-
-  mjiobuf0084 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
-
-  specify
-    (MAin3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin3, 0:0:0);
-    $width (negedge MAin3, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_2_ ( output PADDI, input MAin2 );
-
-  mjiobuf0084 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
-
-  specify
-    (MAin2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin2, 0:0:0);
-    $width (negedge MAin2, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_1_ ( output PADDI, input MAin1 );
-
-  mjiobuf0084 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
-
-  specify
-    (MAin1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin1, 0:0:0);
-    $width (negedge MAin1, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_0_ ( output PADDI, input MAin0 );
-
-  mjiobuf0084 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
-
-  specify
-    (MAin0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin0, 0:0:0);
-    $width (negedge MAin0, 0:0:0);
-  endspecify
-
-endmodule
+
+// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_mapvo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd 
+// Netlist created on Sat Aug 19 20:57:13 2023
+// Netlist written on Sat Aug 19 20:57:15 2023
+// Design is for device LCMXO640C
+// Design is for package TQFP100
+// Design is for performance grade 3
+
+`timescale 1 ns / 1 ps
+
+module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
+                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
+                UFMCLK, UFMSDI, UFMSDO );
+  input  PHI2;
+  input  [9:0] MAin;
+  input  [1:0] CROW;
+  input  [7:0] Din;
+  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
+  output [7:0] Dout;
+  output LED;
+  output [1:0] RBA;
+  output [11:0] RA;
+  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
+  inout  [7:0] RD;
+  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
+         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
+         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
+         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
+         \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, 
+         CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, 
+         ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, 
+         \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , 
+         CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, 
+         CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, 
+         LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, 
+         CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, 
+         CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, 
+         N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , 
+         N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, 
+         UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, 
+         UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, 
+         un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, 
+         FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, 
+         RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, 
+         N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, 
+         UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, 
+         nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, 
+         nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , 
+         \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , 
+         \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , 
+         \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, 
+         N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, 
+         RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, 
+         CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, 
+         nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, 
+         CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , 
+         CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, 
+         un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , 
+         \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , 
+         UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , 
+         CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , 
+         g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, 
+         \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , 
+         \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, 
+         \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , 
+         \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
+         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
+
+  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
+    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
+  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
+  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
+  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
+  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
+  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
+    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
+  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
+    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
+  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
+    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
+  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
+    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
+  SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), 
+    .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), 
+    .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), 
+    .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
+  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
+    .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), 
+    .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
+    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
+  SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
+    .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
+    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+  SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
+    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
+    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
+  SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), 
+    .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), 
+    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
+  SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
+    .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), 
+    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
+  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
+    .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), 
+    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
+    .F1(Cmdn8MEGEN_4_u_i_0));
+  SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), 
+    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
+    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
+  SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
+    .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
+    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
+  SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), 
+    .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), 
+    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
+  SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), 
+    .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), 
+    .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
+  SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), 
+    .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
+    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
+  SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), 
+    .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), 
+    .Q0(\RA_c[11] ), .F1(N_171));
+  SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), 
+    .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
+    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
+    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
+  SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), 
+    .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), 
+    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
+  SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), 
+    .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
+    .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
+    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
+  SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), 
+    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), 
+    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
+    .F1(Ready_0_sqmuxa), .Q1(RASr));
+  SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), 
+    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
+    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
+  SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), 
+    .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), 
+    .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), 
+    .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
+  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), 
+    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), 
+    .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
+    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
+  SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), 
+    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
+    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
+  SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
+    .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
+    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
+  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), 
+    .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
+    .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
+  SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), 
+    .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
+    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
+  SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), 
+    .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), 
+    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
+  SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), 
+    .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), 
+    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
+  SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), 
+    .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), 
+    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
+  SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), 
+    .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), 
+    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
+    .F1(nRCAS_0_sqmuxa_1));
+  SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
+    .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), 
+    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
+    .F1(N_179));
+  SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), 
+    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
+    .F1(nUFMCS15));
+  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
+    .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), 
+    .M0(Ready), .OFX0(m18_0_a2_1));
+  SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), 
+    .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), 
+    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
+    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
+  SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), 
+    .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), 
+    .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), 
+    .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), 
+    .Q1(\RowA[5] ));
+  SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
+    .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), 
+    .F1(un1_FS_14_i_a2_0_1));
+  SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
+    .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), 
+    .F1(un1_FS_13_i_a2_1));
+  SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), 
+    .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), 
+    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
+    .Q1(\Bank[1] ));
+  SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), 
+    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), 
+    .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
+    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
+  SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), 
+    .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), 
+    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
+    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
+  SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
+    .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
+    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
+    .F1(N_155), .Q1(CmdUFMCS));
+  SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), 
+    .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
+    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
+  SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), 
+    .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), 
+    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
+  SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), 
+    .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), 
+    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
+    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
+  SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
+    .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
+    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
+  SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), 
+    .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), 
+    .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), 
+    .Q1(CBR_fast));
+  SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), 
+    .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
+    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
+  SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), 
+    .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
+    .Q1(\RowA[9] ));
+  SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), 
+    .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), 
+    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
+    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
+  SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), 
+    .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), 
+    .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), 
+    .F1(N_132));
+  SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), 
+    .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
+    .Q1(\RBA_c[1] ));
+  SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), 
+    .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), 
+    .F1(UFMSDI_ens2_i_a2_4_2));
+  SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), 
+    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), 
+    .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
+    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
+  SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
+    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
+  SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), 
+    .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), 
+    .F1(UFMSDI_r_xx_mm_1));
+  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), 
+    .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
+    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
+  SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
+    .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
+  SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), 
+    .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), 
+    .F1(un1_CMDWR));
+  SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
+    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
+    .F1(\RA_c[7] ));
+  SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
+    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
+    .F1(\RA_c[6] ));
+  SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
+    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
+    .F1(\RA_c[5] ));
+  SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), 
+    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
+    .Q0(\RA_c[10] ), .F1(N_159_i));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
+    .RD0(RD[0]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
+  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
+  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
+  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
+  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
+  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
+  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
+  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
+  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
+  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
+  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
+  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
+  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
+    .RD7(RD[7]));
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
+    .RD6(RD[6]));
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
+    .RD5(RD[5]));
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
+    .RD4(RD[4]));
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
+    .RD3(RD[3]));
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
+    .RD2(RD[2]));
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
+    .RD1(RD[1]));
+  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
+  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
+  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
+  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
+  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
+  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
+  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
+  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
+  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
+  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
+  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
+  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
+  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
+  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
+  LED LED_I( .PADDO(LED_c), .LED(LED));
+  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
+  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
+  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
+  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
+  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
+  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
+  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
+  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
+  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
+  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
+  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
+  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
+  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
+  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
+  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
+  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
+  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
+  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
+  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
+  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
+  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
+  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
+  VHI VHI_INST( .Z(VCCI));
+  PUR PUR_INST( .PUR(VCCI));
+  GSR GSR_INST( .GSR(VCCI));
+  VLO VLO_INST( .Z(GNDI_TSALL));
+  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
+endmodule
+
+module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
+         A1_dly, CLK_dly, A0_dly;
+
+  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
+    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+  endspecify
+
+endmodule
+
+module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module vcc ( output PWR1 );
+
+  VHI INST1( .Z(PWR1));
+endmodule
+
+module gnd ( output PWR0 );
+
+  VLO INST1( .Z(PWR0));
+endmodule
+
+module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h300a;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
+  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
+    .CO1());
+
+  specify
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h5002;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
+
+  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40002 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module inverter ( input I, output Z );
+
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40004 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40005 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40006 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
+  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
+         CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(\SLICE_20/SLICE_20_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
+  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
+    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40009 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40010 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40011 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40012 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40013 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40014 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40020 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40025 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40032 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40033 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40034 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40035 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40036 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40037 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40038 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40039 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40040 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40041 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40042 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40045 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40046 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40047 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40048 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40049 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40050 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40051 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40053 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40054 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
+         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
+
+  lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
+  lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
+  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
+    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
+    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40055 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40056 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40058 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40061 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40062 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
+
+  lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40063 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40064 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
+
+  lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40065 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+
+  lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40066 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40067 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40068 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40070 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40071 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40072 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, M0_dly, CLK_dly;
+
+  lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40073 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40074 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40075 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40076 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40077 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40078 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40079 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40080 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
+
+  lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40081 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
+
+  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
+
+  specify
+    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD0) = (0:0:0,0:0:0);
+    (RD0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD0, 0:0:0);
+    $width (negedge RD0, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf ( input I, T, output Z, PAD, input PADI );
+
+  IB INST1( .I(PADI), .O(Z));
+  OBW INST2( .I(I), .T(T), .O(PAD));
+endmodule
+
+module Dout_0_ ( input PADDO, output Dout0 );
+
+  mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+
+  specify
+    (PADDO => Dout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0082 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module PHI2 ( output PADDI, input PHI2 );
+
+  mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+
+  specify
+    (PHI2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge PHI2, 0:0:0);
+    $width (negedge PHI2, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0083 ( output Z, input PAD );
+
+  IBPD INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDO ( output PADDI, input UFMSDO );
+
+  mjiobuf0084 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
+
+  specify
+    (UFMSDO => PADDI) = (0:0:0,0:0:0);
+    $width (posedge UFMSDO, 0:0:0);
+    $width (negedge UFMSDO, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0084 ( output Z, input PAD );
+
+  IB INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDI ( input PADDO, output UFMSDI );
+
+  mjiobuf0085 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
+
+  specify
+    (PADDO => UFMSDI) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0085 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module UFMCLK ( input PADDO, output UFMCLK );
+
+  mjiobuf0085 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
+
+  specify
+    (PADDO => UFMCLK) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nUFMCS ( input PADDO, output nUFMCS );
+
+  mjiobuf0085 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
+
+  specify
+    (PADDO => nUFMCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQML ( input PADDO, output RDQML );
+
+  mjiobuf0085 RDQML_pad( .I(PADDO), .PAD(RDQML));
+
+  specify
+    (PADDO => RDQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQMH ( input PADDO, output RDQMH );
+
+  mjiobuf0085 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+
+  specify
+    (PADDO => RDQMH) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRCAS ( input PADDO, output nRCAS );
+
+  mjiobuf0085 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
+
+  specify
+    (PADDO => nRCAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRRAS ( input PADDO, output nRRAS );
+
+  mjiobuf0085 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
+
+  specify
+    (PADDO => nRRAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRWE ( input PADDO, output nRWE );
+
+  mjiobuf0085 nRWE_pad( .I(PADDO), .PAD(nRWE));
+
+  specify
+    (PADDO => nRWE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCKE ( input PADDO, output RCKE );
+
+  mjiobuf0085 RCKE_pad( .I(PADDO), .PAD(RCKE));
+
+  specify
+    (PADDO => RCKE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCLK ( output PADDI, input RCLK );
+
+  mjiobuf0084 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+
+  specify
+    (RCLK => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RCLK, 0:0:0);
+    $width (negedge RCLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module nRCS ( input PADDO, output nRCS );
+
+  mjiobuf0085 nRCS_pad( .I(PADDO), .PAD(nRCS));
+
+  specify
+    (PADDO => nRCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
+
+  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
+
+  specify
+    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD7) = (0:0:0,0:0:0);
+    (RD7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD7, 0:0:0);
+    $width (negedge RD7, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
+
+  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
+
+  specify
+    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD6) = (0:0:0,0:0:0);
+    (RD6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD6, 0:0:0);
+    $width (negedge RD6, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
+
+  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
+
+  specify
+    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD5) = (0:0:0,0:0:0);
+    (RD5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD5, 0:0:0);
+    $width (negedge RD5, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
+
+  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
+
+  specify
+    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD4) = (0:0:0,0:0:0);
+    (RD4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD4, 0:0:0);
+    $width (negedge RD4, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
+
+  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
+
+  specify
+    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD3) = (0:0:0,0:0:0);
+    (RD3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD3, 0:0:0);
+    $width (negedge RD3, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
+
+  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
+
+  specify
+    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD2) = (0:0:0,0:0:0);
+    (RD2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD2, 0:0:0);
+    $width (negedge RD2, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
+
+  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
+
+  specify
+    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD1) = (0:0:0,0:0:0);
+    (RD1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD1, 0:0:0);
+    $width (negedge RD1, 0:0:0);
+  endspecify
+
+endmodule
+
+module RA_11_ ( input PADDO, output RA11 );
+
+  mjiobuf0085 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
+
+  specify
+    (PADDO => RA11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_10_ ( input PADDO, output RA10 );
+
+  mjiobuf0085 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
+
+  specify
+    (PADDO => RA10) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_9_ ( input PADDO, output RA9 );
+
+  mjiobuf0085 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+
+  specify
+    (PADDO => RA9) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_8_ ( input PADDO, output RA8 );
+
+  mjiobuf0085 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+
+  specify
+    (PADDO => RA8) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_7_ ( input PADDO, output RA7 );
+
+  mjiobuf0085 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+
+  specify
+    (PADDO => RA7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_6_ ( input PADDO, output RA6 );
+
+  mjiobuf0085 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+
+  specify
+    (PADDO => RA6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_5_ ( input PADDO, output RA5 );
+
+  mjiobuf0085 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+
+  specify
+    (PADDO => RA5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_4_ ( input PADDO, output RA4 );
+
+  mjiobuf0085 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+
+  specify
+    (PADDO => RA4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_3_ ( input PADDO, output RA3 );
+
+  mjiobuf0085 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+
+  specify
+    (PADDO => RA3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_2_ ( input PADDO, output RA2 );
+
+  mjiobuf0085 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+
+  specify
+    (PADDO => RA2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_1_ ( input PADDO, output RA1 );
+
+  mjiobuf0085 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+
+  specify
+    (PADDO => RA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_0_ ( input PADDO, output RA0 );
+
+  mjiobuf0085 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+
+  specify
+    (PADDO => RA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_1_ ( input PADDO, output RBA1 );
+
+  mjiobuf0085 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
+
+  specify
+    (PADDO => RBA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_0_ ( input PADDO, output RBA0 );
+
+  mjiobuf0085 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
+
+  specify
+    (PADDO => RBA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module LED ( input PADDO, output LED );
+
+  mjiobuf0086 LED_pad( .I(PADDO), .PAD(LED));
+
+  specify
+    (PADDO => LED) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0086 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module nFWE ( output PADDI, input nFWE );
+
+  mjiobuf0084 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+
+  specify
+    (nFWE => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nFWE, 0:0:0);
+    $width (negedge nFWE, 0:0:0);
+  endspecify
+
+endmodule
+
+module nCRAS ( output PADDI, input nCRAS );
+
+  mjiobuf0087 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+
+  specify
+    (nCRAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCRAS, 0:0:0);
+    $width (negedge nCRAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0087 ( output Z, input PAD );
+
+  IBPU INST1( .I(PAD), .O(Z));
+endmodule
+
+module nCCAS ( output PADDI, input nCCAS );
+
+  mjiobuf0087 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+
+  specify
+    (nCCAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCCAS, 0:0:0);
+    $width (negedge nCCAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_7_ ( input PADDO, output Dout7 );
+
+  mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+
+  specify
+    (PADDO => Dout7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_6_ ( input PADDO, output Dout6 );
+
+  mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+
+  specify
+    (PADDO => Dout6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_5_ ( input PADDO, output Dout5 );
+
+  mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+
+  specify
+    (PADDO => Dout5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_4_ ( input PADDO, output Dout4 );
+
+  mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+
+  specify
+    (PADDO => Dout4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_3_ ( input PADDO, output Dout3 );
+
+  mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+
+  specify
+    (PADDO => Dout3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_2_ ( input PADDO, output Dout2 );
+
+  mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+
+  specify
+    (PADDO => Dout2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_1_ ( input PADDO, output Dout1 );
+
+  mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+
+  specify
+    (PADDO => Dout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Din_7_ ( output PADDI, input Din7 );
+
+  mjiobuf0084 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+
+  specify
+    (Din7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din7, 0:0:0);
+    $width (negedge Din7, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_6_ ( output PADDI, input Din6 );
+
+  mjiobuf0084 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+
+  specify
+    (Din6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din6, 0:0:0);
+    $width (negedge Din6, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_5_ ( output PADDI, input Din5 );
+
+  mjiobuf0084 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+
+  specify
+    (Din5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din5, 0:0:0);
+    $width (negedge Din5, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_4_ ( output PADDI, input Din4 );
+
+  mjiobuf0084 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+
+  specify
+    (Din4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din4, 0:0:0);
+    $width (negedge Din4, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_3_ ( output PADDI, input Din3 );
+
+  mjiobuf0084 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+
+  specify
+    (Din3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din3, 0:0:0);
+    $width (negedge Din3, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_2_ ( output PADDI, input Din2 );
+
+  mjiobuf0084 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+
+  specify
+    (Din2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din2, 0:0:0);
+    $width (negedge Din2, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_1_ ( output PADDI, input Din1 );
+
+  mjiobuf0084 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+
+  specify
+    (Din1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din1, 0:0:0);
+    $width (negedge Din1, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_0_ ( output PADDI, input Din0 );
+
+  mjiobuf0084 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+
+  specify
+    (Din0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din0, 0:0:0);
+    $width (negedge Din0, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_1_ ( output PADDI, input CROW1 );
+
+  mjiobuf0084 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+
+  specify
+    (CROW1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW1, 0:0:0);
+    $width (negedge CROW1, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_0_ ( output PADDI, input CROW0 );
+
+  mjiobuf0084 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+
+  specify
+    (CROW0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW0, 0:0:0);
+    $width (negedge CROW0, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_9_ ( output PADDI, input MAin9 );
+
+  mjiobuf0084 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+
+  specify
+    (MAin9 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin9, 0:0:0);
+    $width (negedge MAin9, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_8_ ( output PADDI, input MAin8 );
+
+  mjiobuf0084 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+
+  specify
+    (MAin8 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin8, 0:0:0);
+    $width (negedge MAin8, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_7_ ( output PADDI, input MAin7 );
+
+  mjiobuf0084 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+
+  specify
+    (MAin7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin7, 0:0:0);
+    $width (negedge MAin7, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_6_ ( output PADDI, input MAin6 );
+
+  mjiobuf0084 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+
+  specify
+    (MAin6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin6, 0:0:0);
+    $width (negedge MAin6, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_5_ ( output PADDI, input MAin5 );
+
+  mjiobuf0084 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+
+  specify
+    (MAin5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin5, 0:0:0);
+    $width (negedge MAin5, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_4_ ( output PADDI, input MAin4 );
+
+  mjiobuf0084 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+
+  specify
+    (MAin4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin4, 0:0:0);
+    $width (negedge MAin4, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_3_ ( output PADDI, input MAin3 );
+
+  mjiobuf0084 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+
+  specify
+    (MAin3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin3, 0:0:0);
+    $width (negedge MAin3, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_2_ ( output PADDI, input MAin2 );
+
+  mjiobuf0084 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+
+  specify
+    (MAin2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin2, 0:0:0);
+    $width (negedge MAin2, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_1_ ( output PADDI, input MAin1 );
+
+  mjiobuf0084 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+
+  specify
+    (MAin1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin1, 0:0:0);
+    $width (negedge MAin1, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_0_ ( output PADDI, input MAin0 );
+
+  mjiobuf0084 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+
+  specify
+    (MAin0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin0, 0:0:0);
+    $width (negedge MAin0, 0:0:0);
+  endspecify
+
+endmodule
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
index edaf6e7..5cb4aa5 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
@@ -15,17 +15,15 @@
 
 Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial -ioreg
      b RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
-     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/
-     Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplif
-     y.lpf -lpf
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c
-     0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf
+     Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf
+     -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO.lpf -c 0 -gui -msgset
+     Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO640CTQFP100
 Target Performance:   3
 Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/16/23  04:50:46
+Mapped on:  08/19/23  20:57:13
 
 
 Design Summary
@@ -67,9 +65,9 @@ Mapped on:  08/16/23  04:50:46
      Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
      Net RASr2: 2 loads, 2 LSLICEs
      Net Ready_fast: 7 loads, 7 LSLICEs
-
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
+
      Net InitReady: 16 loads
      Net Ready: 16 loads
      Net S[1]: 13 loads
@@ -127,9 +125,9 @@ Mapped on:  08/16/23  04:50:46
 +---------------------+-----------+-----------+------------+------------+
 | nRWE                | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
-
 | RCKE                | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
+
 | RCLK                | INPUT     | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
 | nRCS                | OUTPUT    | LVCMOS33  |            |            |
@@ -184,9 +182,9 @@ Mapped on:  08/16/23  04:50:46
 +---------------------+-----------+-----------+------------+------------+
 | nCCAS               | INPUT     | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
-
 | Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
+
 | Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
 +---------------------+-----------+-----------+------------+------------+
 | Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
@@ -244,6 +242,8 @@ Mapped on:  08/16/23  04:50:46
 
 
 
+
+
 Removed logic
 
 Block GSR_INST undriven or does not drive anything - clipped.
@@ -285,7 +285,7 @@ Block VCC was optimized away.
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 30 MB
+   Peak Memory Usage: 51 MB
         
 
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_ngd.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_ngd.asd
index c265c78..8440a7e 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_ngd.asd
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_ngd.asd
@@ -1 +1 @@
-[ActiveSupport NGD]
+[ActiveSupport NGD]
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
index 633dcd2..b171e28 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.17
 
-Wed Aug 16 04:50:52 2023
+Sat Aug 19 20:57:21 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+----------------------------------+
@@ -358,7 +358,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:52 2023
+Sat Aug 19 20:57:21 2023
 
 
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
index 979b886..5c3777f 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
@@ -12,12 +12,12 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:48 2023
+Sat Aug 19 20:57:16 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
 RAM2GS_LCMXO640C_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
+Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml
 
 
 Preference file: RAM2GS_LCMXO640C_impl1.prf.
@@ -26,22 +26,22 @@ Preference file: RAM2GS_LCMXO640C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            7.336        0            0.273        0            04           Completed
+5_1   *      0            7.336        0            0.273        0            06           Completed
 * : Design saved.
 
-Total (real) run time for 1-seed: 4 secs 
+Total (real) run time for 1-seed: 6 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Wed Aug 16 04:50:48 2023
+Sat Aug 19 20:57:16 2023
 
 
 Best Par Run
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
 Preference file: RAM2GS_LCMXO640C_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
@@ -90,12 +90,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 .............
 Placer score = 956294.
-Finished Placer Phase 1.  REAL time: 4 secs 
+Finished Placer Phase 1.  REAL time: 5 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  953137
-Finished Placer Phase 2.  REAL time: 4 secs 
+Finished Placer Phase 2.  REAL time: 5 secs 
 
 
 
@@ -132,7 +132,7 @@ I/O Bank Usage Summary:
 | 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 3 secs 
+Total placer CPU time: 5 secs 
 
 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
 
@@ -144,9 +144,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=8 clock_loads=4
 
-Completed router resource preassignment. Real time: 4 secs 
+Completed router resource preassignment. Real time: 6 secs 
 
-Start NBR router at 04:50:52 08/16/23
+Start NBR router at 20:57:22 08/19/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -161,44 +161,44 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 04:50:52 08/16/23
+Start NBR special constraint process at 20:57:22 08/19/23
 
-Start NBR section for initial routing at 04:50:52 08/16/23
+Start NBR section for initial routing at 20:57:22 08/19/23
 Level 1, iteration 1
 1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.325ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.325ns/0.000ns; real time: 6 secs 
 Level 2, iteration 1
 1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.532ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.532ns/0.000ns; real time: 6 secs 
 Level 3, iteration 1
 0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.449ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.449ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
 8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 6 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 04:50:52 08/16/23
+Start NBR section for normal routing at 20:57:22 08/19/23
 Level 4, iteration 1
 5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 6 secs 
 Level 4, iteration 2
 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 6 secs 
 Level 4, iteration 3
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 6 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:52 08/16/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:57:22 08/19/23
 
-Start NBR section for re-routing at 04:50:52 08/16/23
+Start NBR section for re-routing at 20:57:22 08/19/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 6 secs 
 
-Start NBR section for post-routing at 04:50:52 08/16/23
+Start NBR section for post-routing at 20:57:22 08/19/23
 
 End NBR router with 0 unrouted connection
 
@@ -216,8 +216,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=8 clock_loads=4
 
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
 Completely routed.
 End of route.  633 routed (100.00%); 0 unrouted.
 
@@ -239,8 +239,8 @@ PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt
index ab934cf..33d5310 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt
@@ -1,59 +1,59 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-
-# Written on Wed Aug 16 04:50:40 2023
-
-##### FILES SYNTAX CHECKED ##############################################
-Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
-
-#Run constraint checker to find more issues with constraints.
-#########################################################################
-
-
-
-No issues found in constraint syntax.
-
-
-
-Clock Summary
-*************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-Clock Load Summary
-******************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+
+# Written on Sat Aug 19 20:57:07 2023
+
+##### FILES SYNTAX CHECKED ##############################################
+Constraint File(s):      "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
+
+#Run constraint checker to find more issues with constraints.
+#########################################################################
+
+
+
+No issues found in constraint syntax.
+
+
+
+Clock Summary
+*************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+Clock Load Summary
+******************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
index 755533f..97f67a6 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
@@ -24,7 +24,7 @@
 
 
 Last Process:
-JEDEC File
+IBIS Model
 State:
 Passed
 
@@ -48,7 +48,7 @@
 
 
 Logic preference file:
-RAM2GS_LCMXO640C.lpf
+RAM2GS-LCMXO.lpf
 
 
 Physical Preference file:
@@ -62,15 +62,15 @@
 
 
 Updated:
-2023/08/16 05:03:17
+2023/08/20 05:55:53
 
 
 Implementation Location:
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1
+Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1
 
 
 Project File:
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
+Y:/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
 
 
 
    
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html
index b0aa4d8..94c8d3e 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html
@@ -10,9 +10,9 @@
 #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
 #install: C:\lscc\diamond\3.12\synpbase
 #OS: Windows 8 6.2
-#Hostname: ZANEPC
+#Hostname: ZANEMACWIN11
 
-# Wed Aug 16 04:50:37 2023
+# Sat Aug 19 20:57:05 2023
 
 #Implementation: impl1
 
@@ -27,7 +27,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -45,7 +45,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -57,29 +57,27 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
+Options changed - recompiling
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
 
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:38 2023
+# Sat Aug 19 20:57:05 2023
 
 ###########################################################]
 ###########################################################[
@@ -94,34 +92,34 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:38 2023
+# Sat Aug 19 20:57:05 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
 
 @END
 
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:38 2023
+# Sat Aug 19 20:57:05 2023
 
 ###########################################################]
 ###########################################################[
@@ -136,7 +134,7 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -144,15 +142,17 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 @N|Running in 64-bit mode
 File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Wed Aug 16 04:50:39 2023
+# Sat Aug 19 20:57:06 2023
 
 ###########################################################]
-# Wed Aug 16 04:50:39 2023
+Premap Report
+
+# Sat Aug 19 20:57:07 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -165,34 +165,34 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
 
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
 
 @N: FX493 |Applying initial value "0" on instance InitReady.
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@@ -218,20 +218,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
 
@@ -298,23 +298,25 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:41 2023
+# Sat Aug 19 20:57:08 2023
 
 ###########################################################]
-# Wed Aug 16 04:50:41 2023
+Map & Optimize Report
+
+# Sat Aug 19 20:57:08 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -327,70 +329,70 @@ Build: R-2021.03L-SP1
 Install: C:\lscc\diamond\3.12\synpbase
 OS: Windows 6.2
 
-Hostname: ZANEPC
+Hostname: ZANEMACWIN11
 
 Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
@@ -400,45 +402,45 @@ Pass		 CPU time		Worst Slack		Luts / Registers
    4		0h:00m:01s		    -3.23ns		 123 /        89
    5		0h:00m:01s		    -3.23ns		 124 /        89
    6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
 Timing driven replication report
 Added 3 Registers via timing driven replication
 Added 1 LUTs via timing driven replication
 
-   7		0h:00m:02s		    -2.99ns		 128 /        92
+   7		0h:00m:01s		    -2.99ns		 128 /        92
 
 
-   8		0h:00m:02s		    -2.99ns		 127 /        92
-   9		0h:00m:02s		    -3.09ns		 127 /        92
-  10		0h:00m:02s		    -3.19ns		 127 /        92
-  11		0h:00m:02s		    -3.19ns		 127 /        92
-  12		0h:00m:02s		    -3.19ns		 127 /        92
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
 
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
@@ -447,7 +449,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:45 2023
+# Timing report written on Sat Aug 19 20:57:11 2023
 #
 
 
@@ -455,7 +457,7 @@ Top view:               RAM2GS
 Requested Frequency:    2.9 MHz
 Wire load mode:         top
 Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
                        
 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
 
@@ -934,10 +936,10 @@ nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
 
 ---------------------------------------
 Resource Usage Report
@@ -967,10 +969,10 @@ VHI:            1
 VLO:            1
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 196MB)
 
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Wed Aug 16 04:50:45 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:57:12 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf
index 2b0f89b..ca24d6c 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf
@@ -1,24 +1,24 @@
-#
-# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
-#
-
-# Period Constraints 
-FREQUENCY PORT "PHI2" 2.9 MHz;
-FREQUENCY PORT "nCCAS" 2.9 MHz;
-FREQUENCY PORT "nCRAS" 2.9 MHz;
-FREQUENCY PORT "RCLK" 62.5 MHz;
-
-
-# Output Constraints 
-
-# Input Constraints 
-
-# Point-to-point Delay Constraints 
-
-
-
-# Block Path Constraints 
-
-BLOCK ASYNCPATHS;
-
-# End of generated Logical Preferences.
+#
+# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
+#
+
+# Period Constraints 
+FREQUENCY PORT "PHI2" 2.9 MHz;
+FREQUENCY PORT "nCCAS" 2.9 MHz;
+FREQUENCY PORT "nCRAS" 2.9 MHz;
+FREQUENCY PORT "RCLK" 62.5 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.tcl b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.tcl
index 2f392b6..9dfcd14 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.tcl
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.tcl
@@ -1,65 +1,65 @@
-#-- Lattice Semiconductor Corporation Ltd.
-#-- Synplify OEM project file
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO640C
-set_option -package T100C
-set_option -speed_grade -3
-
-#compilation/mapping options
-set_option -symbolic_fsm_compiler true
-set_option -resource_sharing true
-
-#use verilog 2001 standard option
-set_option -vlog_std v2001
-
-#map options
-set_option -frequency 70
-set_option -maxfan 1000
-set_option -auto_constrain_io 0
-set_option -disable_io_insertion false
-set_option -retiming false; set_option -pipe false
-set_option -force_gsr auto
-set_option -compiler_compatible 0
-set_option -dup false
-
-add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc}
-set_option -default_enum_encoding default
-
-#simulation options
-
-
-#timing analysis options
-set_option -num_critical_paths 3
-
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#synplifyPro options
-set_option -fix_gated_and_generated_clocks 1
-set_option -update_models_cp 0
-set_option -resolve_multiple_driver 0
-
-
-set_option -seqshift_no_replicate 0
-
-#-- add_file options
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C}
-add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v}
-
-#-- top module name
-set_option -top_module RAM2GS
-
-#-- set result format/file last
-project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi}
-
-#-- error message log file
-project -log_file {RAM2GS_LCMXO640C_impl1.srf}
-
-#-- set any command lines input by customer
-
-
-#-- run Synplify with 'arrange HDL file'
-project -run -clean
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO640C
+set_option -package T100C
+set_option -speed_grade -3
+
+#compilation/mapping options
+set_option -symbolic_fsm_compiler true
+set_option -resource_sharing true
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 70
+set_option -maxfan 1000
+set_option -auto_constrain_io 0
+set_option -disable_io_insertion false
+set_option -retiming false; set_option -pipe false
+set_option -force_gsr auto
+set_option -compiler_compatible 0
+set_option -dup false
+
+add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
+set_option -default_enum_encoding default
+
+#simulation options
+
+
+#timing analysis options
+set_option -num_critical_paths 3
+
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#synplifyPro options
+set_option -fix_gated_and_generated_clocks 1
+set_option -update_models_cp 0
+set_option -resolve_multiple_driver 0
+
+
+set_option -seqshift_no_replicate 0
+
+#-- add_file options
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO640C}
+add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v}
+
+#-- top module name
+set_option -top_module RAM2GS
+
+#-- set result format/file last
+project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi}
+
+#-- error message log file
+project -log_file {RAM2GS_LCMXO640C_impl1.srf}
+
+#-- set any command lines input by customer
+
+
+#-- run Synplify with 'arrange HDL file'
+project -run -clean
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
index c8fba6a..e08c8f3 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
+Sat Aug 19 20:57:14 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
 Design file:     ram2gs_lcmxo640c_impl1_map.ncd
 Preference file: ram2gs_lcmxo640c_impl1.prf
 Device,speed:    LCMXO640C,3
@@ -253,7 +253,7 @@ Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
+Sat Aug 19 20:57:14 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -263,7 +263,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
 Design file:     ram2gs_lcmxo640c_impl1_map.ncd
 Preference file: ram2gs_lcmxo640c_impl1.prf
 Device,speed:    LCMXO640C,M
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
index fe8751d..b93319a 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
+Sat Aug 19 20:57:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
 Design file:     ram2gs_lcmxo640c_impl1.ncd
 Preference file: ram2gs_lcmxo640c_impl1.prf
 Device,speed:    LCMXO640C,3
@@ -1231,7 +1231,7 @@ Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
+Sat Aug 19 20:57:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1241,7 +1241,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
 Design file:     ram2gs_lcmxo640c_impl1.ncd
 Preference file: ram2gs_lcmxo640c_impl1.prf
 Device,speed:    LCMXO640C,m
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.sdf
index d3d13b4..93d8db6 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.sdf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.sdf
@@ -1,2928 +1,2928 @@
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-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1_SLICE_65I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_B")
-    (INSTANCE RD_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_B")
-    (INSTANCE Dout_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2B")
-    (INSTANCE PHI2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2S) (1250:1250:1250))
-      (WIDTH (negedge PHI2S) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDOB")
-    (INSTANCE UFMSDOI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
-      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDIB")
-    (INSTANCE UFMSDII)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLKB")
-    (INSTANCE UFMCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCSB")
-    (INSTANCE nUFMCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMLB")
-    (INSTANCE RDQMLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMHB")
-    (INSTANCE RDQMHI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCASB")
-    (INSTANCE nRCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRASB")
-    (INSTANCE nRRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWEB")
-    (INSTANCE nRWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKEB")
-    (INSTANCE RCKEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLKB")
-    (INSTANCE RCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLKS) (1250:1250:1250))
-      (WIDTH (negedge RCLKS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCSB")
-    (INSTANCE nRCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_B")
-    (INSTANCE RD_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_B")
-    (INSTANCE RD_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_B")
-    (INSTANCE RD_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_B")
-    (INSTANCE RD_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_B")
-    (INSTANCE RD_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_B")
-    (INSTANCE RD_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_B")
-    (INSTANCE RD_1_I0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_B")
-    (INSTANCE RA_11_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_B")
-    (INSTANCE RA_10_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_B")
-    (INSTANCE RA_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_B")
-    (INSTANCE RA_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_B")
-    (INSTANCE RA_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_B")
-    (INSTANCE RA_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_B")
-    (INSTANCE RA_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_B")
-    (INSTANCE RA_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_B")
-    (INSTANCE RA_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_B")
-    (INSTANCE RA_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_B")
-    (INSTANCE RA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_B")
-    (INSTANCE RA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_B")
-    (INSTANCE RBA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_B")
-    (INSTANCE RBA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LEDB")
-    (INSTANCE LEDI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWEB")
-    (INSTANCE nFWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWES) (1250:1250:1250))
-      (WIDTH (negedge nFWES) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRASB")
-    (INSTANCE nCRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRASS) (1250:1250:1250))
-      (WIDTH (negedge nCRASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCASB")
-    (INSTANCE nCCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCASS) (1250:1250:1250))
-      (WIDTH (negedge nCCASS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_B")
-    (INSTANCE Dout_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_B")
-    (INSTANCE Dout_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_B")
-    (INSTANCE Dout_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_B")
-    (INSTANCE Dout_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_B")
-    (INSTANCE Dout_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_B")
-    (INSTANCE Dout_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_B")
-    (INSTANCE Dout_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_B")
-    (INSTANCE Din_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_B")
-    (INSTANCE Din_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_B")
-    (INSTANCE Din_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_B")
-    (INSTANCE Din_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_B")
-    (INSTANCE Din_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_B")
-    (INSTANCE Din_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_B")
-    (INSTANCE Din_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_B")
-    (INSTANCE Din_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_B")
-    (INSTANCE CROW_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_B")
-    (INSTANCE CROW_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_B")
-    (INSTANCE MAin_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_B")
-    (INSTANCE MAin_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_B")
-    (INSTANCE MAin_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_B")
-    (INSTANCE MAin_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_B")
-    (INSTANCE MAin_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_B")
-    (INSTANCE MAin_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_B")
-    (INSTANCE MAin_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_B")
-    (INSTANCE MAin_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_B")
-    (INSTANCE MAin_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_B")
-    (INSTANCE MAin_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/D0 (1405:1526:1647)(1405:1526:1647))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/C0 (754:836:918)(754:836:918))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C0 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/B0 (917:1024:1131)(917:1024:1131))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/C1 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/D0 (602:670:739)(602:670:739))
-        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B0 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/D1 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/D1 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/D0 (963:1075:1187)(963:1075:1187))
-        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (1823:1986:2149)(1823:1986:2149))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/B0 (1823:1986:2149)(1823:1986:2149))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/B1 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/B1 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/B0 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/D1 (1404:1527:1650)(1404:1527:1650))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/B0 (913:1016:1120)(913:1016:1120))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (1560:1708:1856)(1560:1708:1856))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/B0 (913:1016:1120)(913:1016:1120))
-        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (2087:2267:2448)(2087:2267:2448))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/C0 (754:836:918)(754:836:918))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/C1 (1149:1260:1372)(1149:1260:1372))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/D1 (1397:1518:1640)(1397:1518:1640))
-        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/A0 (2201:2394:2587)(2201:2394:2587))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/D0 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (1225:1371:1517)(1225:1371:1517))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A0 (1225:1371:1517)(1225:1371:1517))
-        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/D0 (1803:1960:2118)(1803:1960:2118))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/A1 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/A1 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/D1 (876:974:1072)(876:974:1072))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/D1 (876:974:1072)(876:974:1072))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_78I/F0 SLICE_9I/D1 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_70I/F1 SLICE_9I/C1 (769:851:933)(769:851:933))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_70I/F1 SLICE_67I/A0 (1295:1420:1545)(1295:1420:1545))
-        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (606:674:742)(606:674:742))
-        (INTERCONNECT SLICE_70I/F1 SLICE_90I/C1 (769:851:933)(769:851:933))
-        (INTERCONNECT SLICE_85I/F1 SLICE_9I/B1 (2100:2300:2500)(2100:2300:2500))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (1802:1995:2189)(1802:1995:2189))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (1606:1757:1909)(1606:1757:1909))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/C0 (2131:2353:2575)(2131:2353:2575))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (2379:2611:2843)(2379:2611:2843))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (1395:1576:1757)(1395:1576:1757))
-        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B0 (1395:1576:1757)(1395:1576:1757))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/D0 (517:575:634)(517:575:634))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/A1 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_70I/F0 SLICE_9I/C0 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_9I/F1 SLICE_9I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_9I/F1 SLICE_20I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_14I/F1 SLICE_9I/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_14I/F1 SLICE_14I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (1301:1429:1558)(1301:1429:1558))
-        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (2017:2199:2381)(2017:2199:2381))
-        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_76I/F0 SLICE_14I/A1 (837:931:1026)(837:931:1026))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/B0 (1984:2189:2395)(1984:2189:2395))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (1925:2114:2304)(1925:2114:2304))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/D0 (1636:1793:1950)(1636:1793:1950))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/C0 (2423:2682:2941)(2423:2682:2941))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/D0 (2046:2232:2419)(2046:2232:2419))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/D0 (1522:1684:1847)(1522:1684:1847))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/A1 (2718:2965:3212)(2718:2965:3212))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/B0 (2379:2611:2843)(2379:2611:2843))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/C0 (1431:1576:1722)(1431:1576:1722))
-        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/D1 (571:629:687)(571:629:687))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (575:636:697)(575:636:697))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (808:893:978)(808:893:978))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C0 (808:893:978)(808:893:978))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/C1 (1211:1325:1439)(1211:1325:1439))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/B0 (968:1072:1177)(968:1072:1177))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (1236:1372:1509)
-          (1236:1372:1509))
-        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (1236:1372:1509)
-          (1236:1372:1509))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/B1 (947:1054:1161)(947:1054:1161))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/D0 (653:719:785)(653:719:785))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/A0 (922:1019:1117)(922:1019:1117))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C1 (788:872:957)(788:872:957))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C0 (788:872:957)(788:872:957))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/A1 (1312:1438:1565)(1312:1438:1565))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A1 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C1 (1839:2035:2231)(1839:2035:2231))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/B0 (1710:1891:2072)(1710:1891:2072))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/A0 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A1 (1191:1322:1454)
-          (1191:1322:1454))
-        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/D0 (633:698:764)(633:698:764))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/D1 (1332:1461:1591)(1332:1461:1591))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/A0 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/C0 (2356:2575:2795)(2356:2575:2795))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/B1 (863:960:1057)(863:960:1057))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A1 (810:899:989)(810:899:989))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/C0 (696:773:850)(696:773:850))
-        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/B1 (863:960:1057)(863:960:1057))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/A1 (1282:1411:1540)(1282:1411:1540))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (1320:1453:1587)(1320:1453:1587))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A1 (1688:1854:2020)(1688:1854:2020))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A0 (1688:1854:2020)(1688:1854:2020))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/B1 (1328:1464:1600)(1328:1464:1600))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (1320:1453:1587)(1320:1453:1587))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (889:990:1091)(889:990:1091))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/B1 (1726:1896:2067)(1726:1896:2067))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/A1 (2115:2317:2519)(2115:2317:2519))
-        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (582:647:712)(582:647:712))
-        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/C1 (1571:1716:1862)(1571:1716:1862))
-        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F1 SLICE_43I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_19I/F1 SLICE_44I/B1 (1394:1526:1659)(1394:1526:1659))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/B0 (1409:1541:1674)(1409:1541:1674))
-        (INTERCONNECT SLICE_90I/F1 SLICE_20I/B0 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_21I/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (2758:3009:3261)(2758:3009:3261))
-        (INTERCONNECT Din_5_I/PADDI SLICE_67I/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din_5_I/PADDI SLICE_75I/A0 (1511:1671:1831)(1511:1671:1831))
-        (INTERCONNECT Din_5_I/PADDI SLICE_76I/D1 (1242:1370:1499)(1242:1370:1499))
-        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (1549:1713:1878)(1549:1713:1878))
-        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (2391:2619:2848)(2391:2619:2848))
-        (INTERCONNECT Din_5_I/PADDI SLICE_82I/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din_5_I/PADDI SLICE_82I/D0 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din_5_I/PADDI SLICE_85I/A0 (1876:2059:2243)(1876:2059:2243))
-        (INTERCONNECT Din_3_I/PADDI SLICE_21I/C1 (1790:1964:2139)(1790:1964:2139))
-        (INTERCONNECT Din_3_I/PADDI SLICE_57I/C1 (2200:2404:2608)(2200:2404:2608))
-        (INTERCONNECT Din_3_I/PADDI SLICE_67I/B1 (1930:2123:2316)(1930:2123:2316))
-        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (2355:2576:2798)(2355:2576:2798))
-        (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (2606:2857:3109)(2606:2857:3109))
-        (INTERCONNECT Din_3_I/PADDI SLICE_78I/C1 (1790:1964:2139)(1790:1964:2139))
-        (INTERCONNECT Din_3_I/PADDI SLICE_82I/A1 (1904:2091:2278)(1904:2091:2278))
-        (INTERCONNECT Din_3_I/PADDI SLICE_82I/A0 (1904:2091:2278)(1904:2091:2278))
-        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (1922:2112:2303)(1922:2112:2303))
-        (INTERCONNECT SLICE_75I/F1 SLICE_21I/B1 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (616:686:757)(616:686:757))
-        (INTERCONNECT SLICE_75I/F1 SLICE_67I/A1 (864:963:1063)(864:963:1063))
-        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B1 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_21I/F1 SLICE_21I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_21I/F1 SLICE_26I/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/C0 (1644:1786:1929)(1644:1786:1929))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/D1 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (2611:2837:3063)(2611:2837:3063))
-        (INTERCONNECT SLICE_75I/F0 SLICE_21I/B0 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_82I/F1 SLICE_21I/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (573:634:695)(573:634:695))
-        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (573:634:695)(573:634:695))
-        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (906:1005:1104)(906:1005:1104))
-        (INTERCONNECT SLICE_67I/F0 SLICE_67I/C1 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_67I/F0 SLICE_82I/C0 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/B0 (1797:1958:2120)(1797:1958:2120))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (1157:1286:1415)(1157:1286:1415))
-        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/C1 (1016:1133:1251)(1016:1133:1251))
-        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/D1 (861:959:1058)(861:959:1058))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/B1 (1300:1432:1564)(1300:1432:1564))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (1695:1853:2012)(1695:1853:2012))
-        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/B1 (1703:1864:2025)(1703:1864:2025))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/A1 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/C1 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/D0 (1042:1139:1236)(1042:1139:1236))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/A1 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/A0 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/A1 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/C1 (1197:1313:1429)(1197:1313:1429))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/C1 (1197:1313:1429)(1197:1313:1429))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/A1 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/A0 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/A1 (1311:1439:1568)(1311:1439:1568))
-        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/A0 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/C1 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/C0 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/A1 (1304:1431:1559)(1304:1431:1559))
-        (INTERCONNECT SLICE_82I/F0 SLICE_22I/D0 (1778:1934:2090)(1778:1934:2090))
-        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/F1 SLICE_68I/D0 (975:1068:1161)(975:1068:1161))
-        (INTERCONNECT SLICE_22I/F1 SLICE_69I/B0 (1290:1421:1553)(1290:1421:1553))
-        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (735:822:909)(735:822:909))
-        (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/B0 (899:1000:1102)(899:1000:1102))
-        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (1348:1473:1599)(1348:1473:1599))
-        (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/D0 (580:648:716)(580:648:716))
-        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/A0 (2063:2250:2438)(2063:2250:2438))
-        (INTERCONNECT SLICE_26I/F1 SLICE_26I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/F1 SLICE_29I/D1 (1406:1541:1676)(1406:1541:1676))
-        (INTERCONNECT SLICE_83I/F1 SLICE_59I/A1 (2154:2337:2521)(2154:2337:2521))
-        (INTERCONNECT SLICE_83I/F1 SLICE_61I/D0 (1695:1864:2034)(1695:1864:2034))
-        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C1 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C0 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73I/F1 SLICE_59I/B1 (1836:2003:2171)(1836:2003:2171))
-        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73I/F1 SLICE_73I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_73I/F1 SLICE_94I/C1 (1680:1833:1986)(1680:1833:1986))
-        (INTERCONNECT SLICE_61I/F1 SLICE_29I/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A1 (832:922:1012)(832:922:1012))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D1 (623:687:752)(623:687:752))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D0 (623:687:752)(623:687:752))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/A0 (1302:1427:1553)(1302:1427:1553))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/B1 (1703:1883:2063)(1703:1883:2063))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/A0 (832:922:1012)(832:922:1012))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/D0 (1033:1127:1221)(1033:1127:1221))
-        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (2098:2304:2511)(2098:2304:2511))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (1347:1503:1660)(1347:1503:1660))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/B0 (948:1050:1153)(948:1050:1153))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/D1 (578:636:695)(578:636:695))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/D0 (578:636:695)(578:636:695))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/D1 (633:697:761)(633:697:761))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/D1 (1435:1582:1729)(1435:1582:1729))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/C1 (1476:1647:1819)(1476:1647:1819))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/B1 (2176:2379:2582)(2176:2379:2582))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C1 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C0 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (640:705:770)(640:705:770))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/A0 (1191:1321:1451)(1191:1321:1451))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/C1 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/D1 (2271:2465:2659)(2271:2465:2659))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/D0 (2271:2465:2659)(2271:2465:2659))
-        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/C1 (696:773:850)(696:773:850))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D1 (991:1107:1224)(991:1107:1224))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D0 (991:1107:1224)(991:1107:1224))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/C1 (1560:1700:1840)(1560:1700:1840))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C1 (1146:1281:1417)(1146:1281:1417))
-        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C0 (1146:1281:1417)(1146:1281:1417))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A1 (825:914:1004)(825:914:1004))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B1 (943:1046:1150)(943:1046:1150))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B0 (943:1046:1150)(943:1046:1150))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/D1 (1109:1203:1297)(1109:1203:1297))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A1 (897:993:1090)(897:993:1090))
-        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A0 (897:993:1090)(897:993:1090))
-        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (1885:2046:2208)(1885:2046:2208))
-        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (2184:2374:2565)(2184:2374:2565))
-        (INTERCONNECT SLICE_73I/F0 SLICE_31I/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (1908:2070:2233)(1908:2070:2233))
-        (INTERCONNECT SLICE_56I/F0 SLICE_32I/D1 (1374:1495:1616)(1374:1495:1616))
-        (INTERCONNECT SLICE_84I/F1 SLICE_32I/B1 (1172:1308:1444)(1172:1308:1444))
-        (INTERCONNECT SLICE_72I/F1 SLICE_32I/A1 (1239:1383:1527)(1239:1383:1527))
-        (INTERCONNECT SLICE_72I/F1 SLICE_58I/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_72I/F1 SLICE_64I/C1 (1575:1727:1879)(1575:1727:1879))
-        (INTERCONNECT SLICE_72I/F1 SLICE_72I/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_74I/F0 SLICE_32I/D0 (245:274:304)(245:274:304))
-        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32I/F1 SLICE_87I/D1 (245:274:304)(245:274:304))
-        (INTERCONNECT nCRASI/PADDI SLICE_33I/C1 (1635:1825:2016)(1635:1825:2016))
-        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (1526:1687:1849)(1526:1687:1849))
-        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (1758:1913:2068)(1758:1913:2068))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/D0 (1892:2044:2197)(1892:2044:2197))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/D0 (1405:1538:1671)(1405:1538:1671))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/A1 (1634:1807:1981)(1634:1807:1981))
-        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/B0 (1969:2184:2399)(1969:2184:2399))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/A0 (1377:1528:1680)(1377:1528:1680))
-        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/D0 (2317:2524:2731)(2317:2524:2731))
-        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (1070:1165:1260)(1070:1165:1260))
-        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/D1 (1908:2070:2232)(1908:2070:2232))
-        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/D0 (1908:2070:2232)(1908:2070:2232))
-        (INTERCONNECT SLICE_85I/F0 SLICE_39I/B1 (1792:1955:2118)(1792:1955:2118))
-        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (1477:1601:1726)(1477:1601:1726))
-        (INTERCONNECT Din_6_I/PADDI SLICE_39I/B0 (2577:2847:3118)(2577:2847:3118))
-        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT Din_6_I/PADDI SLICE_75I/A1 (2528:2792:3057)(2528:2792:3057))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/B0 (2695:2961:3228)(2695:2961:3228))
-        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (2387:2616:2845)(2387:2616:2845))
-        (INTERCONNECT Din_6_I/PADDI SLICE_78I/C0 (2520:2764:3008)(2520:2764:3008))
-        (INTERCONNECT Din_6_I/PADDI SLICE_85I/D0 (1973:2170:2368)(1973:2170:2368))
-        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (1723:1881:2040)(1723:1881:2040))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (910:1010:1110)(910:1010:1110))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (1730:1889:2048)(1730:1889:2048))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (1730:1889:2048)(1730:1889:2048))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (1320:1449:1579)(1320:1449:1579))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (910:1010:1110)(910:1010:1110))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (1723:1881:2040)(1723:1881:2040))
-        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_39I/F1 SLICE_57I/A0 (2170:2363:2556)(2170:2363:2556))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/C1 (2032:2205:2379)(2032:2205:2379))
-        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/B1 (1789:1953:2117)(1789:1953:2117))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/B1 (1295:1427:1559)(1295:1427:1559))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/A1 (2074:2266:2459)(2074:2266:2459))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/B1 (1717:1887:2058)(1717:1887:2058))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/C1 (1557:1708:1859)(1557:1708:1859))
-        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (884:984:1085)(884:984:1085))
-        (INTERCONNECT SLICE_41I/F1 SLICE_41I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_43I/F1 SLICE_41I/A0 (833:932:1032)(833:932:1032))
-        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (1773:1932:2091)(1773:1932:2091))
-        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/B0 (1781:1942:2104)(1781:1942:2104))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/D0 (1398:1530:1663)(1398:1530:1663))
-        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (1386:1516:1646)(1386:1516:1646))
-        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (1621:1763:1905)(1621:1763:1905))
-        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/A1 (1247:1371:1495)(1247:1371:1495))
-        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/C1 (2228:2432:2636)
-          (2228:2432:2636))
-        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/C0 (1537:1688:1840)
-          (1537:1688:1840))
-        (INTERCONNECT SLICE_50I/F0 SLICE_43I/C1 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (31:31:31)(31:31:31))
-        (INTERCONNECT SLICE_50I/F0 SLICE_61I/D1 (970:1082:1195)(970:1082:1195))
-        (INTERCONNECT SLICE_50I/F0 SLICE_62I/C1 (1575:1727:1879)(1575:1727:1879))
-        (INTERCONNECT SLICE_83I/F0 SLICE_43I/C0 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_83I/F0 SLICE_44I/C1 (739:821:903)(739:821:903))
-        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/D1 (1335:1476:1617)(1335:1476:1617))
-        (INTERCONNECT SLICE_72I/F0 SLICE_51I/B1 (1781:1942:2104)(1781:1942:2104))
-        (INTERCONNECT SLICE_66I/F0 SLICE_51I/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_66I/F0 SLICE_66I/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_52I/F1 SLICE_51I/D0 (877:975:1074)(877:975:1074))
-        (INTERCONNECT SLICE_52I/F1 SLICE_52I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_51I/F1 SLICE_51I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_64I/F1 SLICE_52I/A0 (868:962:1057)(868:962:1057))
-        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (1184:1361:1538)(1184:1361:1538))
-        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/D0 (1466:1589:1712)(1466:1589:1712))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/B0 (2114:2313:2513)(2114:2313:2513))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/A1 (1678:1840:2002)(1678:1840:2002))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/A0 (1678:1840:2002)(1678:1840:2002))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D1 (2224:2421:2618)(2224:2421:2618))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D0 (2224:2421:2618)(2224:2421:2618))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/A0 (1802:1970:2138)(1802:1970:2138))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/D1 (1796:1956:2117)(1796:1956:2117))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (1954:2134:2314)(1954:2134:2314))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/D1 (2320:2504:2689)(2320:2504:2689))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/D0 (2320:2504:2689)(2320:2504:2689))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B1 (2543:2782:3021)(2543:2782:3021))
-        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B0 (2543:2782:3021)(2543:2782:3021))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (2220:2446:2672)(2220:2446:2672))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (2701:2972:3244)(2701:2972:3244))
-        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (2663:2930:3197)(2663:2930:3197))
-        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (2067:2260:2454)(2067:2260:2454))
-        (INTERCONNECT Din_4_I/PADDI SLICE_75I/C1 (1378:1524:1670)(1378:1524:1670))
-        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (1530:1693:1856)(1530:1693:1856))
-        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (2732:2985:3238)(2732:2985:3238))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/B1 (1973:2177:2381)(1973:2177:2381))
-        (INTERCONNECT Din_4_I/PADDI SLICE_85I/B0 (1973:2177:2381)(1973:2177:2381))
-        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (1242:1370:1498)(1242:1370:1498))
-        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (2109:2309:2510)(2109:2309:2510))
-        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (1503:1660:1818)(1503:1660:1818))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (2373:2602:2831)(2373:2602:2831))
-        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (2373:2602:2831)(2373:2602:2831))
-        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (1706:1877:2049)(1706:1877:2049))
-        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (1706:1877:2049)(1706:1877:2049))
-        (INTERCONNECT nCCASI/PADDI SLICE_88I/D0 (2063:2255:2448)(2063:2255:2448))
-        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (2378:2648:2918)(2378:2648:2918))
-        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (1982:2228:2475)(1982:2228:2475))
-        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/D1 (1498:1630:1763)(1498:1630:1763))
-        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/C1 (1653:1804:1956)(1653:1804:1956))
-        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/B1 (1813:1984:2155)(1813:1984:2155))
-        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/A1 (2138:2321:2505)(2138:2321:2505))
-        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (2264:2497:2730)(2264:2497:2730))
-        (INTERCONNECT Din_7_I/PADDI SLICE_75I/B1 (1828:2016:2205)(1828:2016:2205))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/C1 (1272:1412:1553)(1272:1412:1553))
-        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (1424:1581:1739)(1424:1581:1739))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (2522:2767:3013)(2522:2767:3013))
-        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C0 (2522:2767:3013)(2522:2767:3013))
-        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_56I/F1 SLICE_70I/B1 (1813:1984:2155)(1813:1984:2155))
-        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (1547:1713:1879)(1547:1713:1879))
-        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (1539:1702:1866)(1539:1702:1866))
-        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (1921:2109:2298)(1921:2109:2298))
-        (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (1904:2092:2280)(1904:2092:2280))
-        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (1904:2092:2280)(1904:2092:2280))
-        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (2324:2541:2759)(2324:2541:2759))
-        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (1891:2077:2264)(1891:2077:2264))
-        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (2325:2544:2764)(2325:2544:2764))
-        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (1529:1691:1854)(1529:1691:1854))
-        (INTERCONNECT Din_0_I/PADDI SLICE_76I/B1 (1937:2130:2324)(1937:2130:2324))
-        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (2739:2994:3250)(2739:2994:3250))
-        (INTERCONNECT Din_0_I/PADDI SLICE_85I/A1 (2297:2513:2729)(2297:2513:2729))
-        (INTERCONNECT Din_1_I/PADDI SLICE_57I/D0 (1217:1343:1469)(1217:1343:1469))
-        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (714:807:900)(714:807:900))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (1521:1678:1835)(1521:1678:1835))
-        (INTERCONNECT Din_1_I/PADDI SLICE_75I/D0 (1217:1343:1469)(1217:1343:1469))
-        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (1421:1579:1738)(1421:1579:1738))
-        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (1959:2159:2360)(1959:2159:2360))
-        (INTERCONNECT Din_1_I/PADDI SLICE_85I/D1 (1941:2140:2339)(1941:2140:2339))
-        (INTERCONNECT SLICE_57I/F1 SLICE_57I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (875:974:1073)(875:974:1073))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/B1 (1544:1731:1919)(1544:1731:1919))
-        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (940:1054:1169)(940:1054:1169))
-        (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_62I/F1 SLICE_59I/C0 (1669:1820:1972)(1669:1820:1972))
-        (INTERCONNECT SLICE_62I/F1 SLICE_62I/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_80I/F0 SLICE_59I/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/D1 (1509:1643:1777)(1509:1643:1777))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/D1 (1491:1617:1743)(1491:1617:1743))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/D1 (1491:1617:1743)(1491:1617:1743))
-        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (2209:2402:2596)(2209:2402:2596))
-        (INTERCONNECT SLICE_94I/F0 SLICE_60I/C0 (1529:1669:1809)(1529:1669:1809))
-        (INTERCONNECT SLICE_60I/F1 SLICE_60I/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (1291:1473:1656)(1291:1473:1656))
-        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (1935:2190:2445)(1935:2190:2445))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/D1 (1079:1173:1267)(1079:1173:1267))
-        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/C0 (1637:1779:1921)(1637:1779:1921))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/D0 (1679:1834:1990)(1679:1834:1990))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/B1 (1691:1860:2030)(1691:1860:2030))
-        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/D0 (1376:1507:1638)(1376:1507:1638))
-        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/C0 (1653:1804:1956)
-          (1653:1804:1956))
-        (INTERCONNECT SLICE_79I/F0 SLICE_62I/A0 (1651:1815:1979)(1651:1815:1979))
-        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (2095:2345:2595)(2095:2345:2595))
-        (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (1548:1774:2000)(1548:1774:2000))
-        (INTERCONNECT SLICE_66I/F1 SLICE_64I/C0 (1529:1669:1809)(1529:1669:1809))
-        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/B1 (1247:1397:1548)(1247:1397:1548))
-        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (1383:1512:1642)(1383:1512:1642))
-        (INTERCONNECT SLICE_81I/F0 SLICE_74I/A0 (1652:1813:1974)(1652:1813:1974))
-        (INTERCONNECT SLICE_74I/F1 SLICE_66I/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/D0 (1375:1502:1629)(1375:1502:1629))
-        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/D0 (1901:2062:2224)(1901:2062:2224))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (1621:1774:1928)(1621:1774:1928))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/D1 (1614:1766:1919)(1614:1766:1919))
-        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (1908:2101:2294)(1908:2101:2294))
-        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (1350:1494:1639)(1350:1494:1639))
-        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/D1 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (735:822:909)(735:822:909))
-        (INTERCONNECT SLICE_87I/F0 SLICE_69I/D0 (580:648:716)(580:648:716))
-        (INTERCONNECT SLICE_68I/F1 SLICE_68I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_84I/F0 SLICE_68I/A0 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_84I/F0 SLICE_69I/A0 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_69I/F1 SLICE_69I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/A1 (514:575:636)(514:575:636))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/C1 (1805:1987:2169)(1805:1987:2169))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (1657:1821:1985)(1657:1821:1985))
-        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/B1 (2368:2598:2829)(2368:2598:2829))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/B1 (1951:2152:2353)(1951:2152:2353))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (2353:2581:2809)(2353:2581:2809))
-        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/C1 (3008:3283:3558)(3008:3283:3558))
-        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_88I/F1 SLICE_71I/A0 (1490:1668:1846)(1490:1668:1846))
-        (INTERCONNECT SLICE_81I/F1 SLICE_72I/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (1657:1821:1985)(1657:1821:1985))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/A1 (1919:2113:2308)(1919:2113:2308))
-        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (2322:2545:2769)(2322:2545:2769))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (1606:1757:1909)(1606:1757:1909))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/B1 (1519:1681:1844)(1519:1681:1844))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/B0 (2326:2552:2779)(2326:2552:2779))
-        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/C0 (1653:1804:1956)(1653:1804:1956))
-        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/D0 (1466:1589:1712)(1466:1589:1712))
-        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/C1 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_77I/F1 SLICE_77I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_79I/F1 SLICE_79I/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (1164:1346:1528)(1164:1346:1528))
-        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/C1 (1769:1940:2112)(1769:1940:2112))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/C0 (1769:1940:2112)(1769:1940:2112))
-        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/C1 (2608:2849:3090)(2608:2849:3090))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (1508:1668:1828)(1508:1668:1828))
-        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/C0 (3001:3275:3550)(3001:3275:3550))
-        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (1247:1397:1548)(1247:1397:1548))
-        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (2204:2414:2624)(2204:2414:2624))
-        (INTERCONNECT nFWEI/PADDI SLICE_88I/C0 (2204:2414:2624)(2204:2414:2624))
-        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (2038:2228:2418)(2038:2228:2418))
-        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (2307:2528:2750)(2307:2528:2750))
-        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (2466:2735:3005)(2466:2735:3005))
-        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (1568:1777:1987)(1568:1777:1987))
-        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (2477:2778:3080)(2477:2778:3080))
-        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (1756:2001:2247)(1756:2001:2247))
-        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (2571:2883:3195)(2571:2883:3195))
-        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (2571:2883:3195)(2571:2883:3195))
-        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (2538:2838:3139)(2538:2838:3139))
-        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (2538:2838:3139)(2538:2838:3139))
-        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (1741:1997:2254)(1741:1997:2254))
-        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (1741:1997:2254)(1741:1997:2254))
-        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (2098:2368:2638)(2098:2368:2638))
-        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/A1 (1735:1889:2044)(1735:1889:2044))
-        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/C1 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (1979:2229:2479)(1979:2229:2479))
-        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (1723:1947:2172)(1723:1947:2172))
-        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (1971:2209:2448)(1971:2209:2448))
-        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (1610:1831:2052)(1610:1831:2052))
-        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (1982:2228:2475)(1982:2228:2475))
-        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (2942:3272:3602)(2942:3272:3602))
-        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (2505:2806:3107)(2505:2806:3107))
-        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (2540:2847:3154)(2540:2847:3154))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:57:26 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1_SLICE_65I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_B")
+    (INSTANCE RD_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_B")
+    (INSTANCE Dout_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2B")
+    (INSTANCE PHI2I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2S) (1250:1250:1250))
+      (WIDTH (negedge PHI2S) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDOB")
+    (INSTANCE UFMSDOI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDOS) (1250:1250:1250))
+      (WIDTH (negedge UFMSDOS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDIB")
+    (INSTANCE UFMSDII)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDIS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLKB")
+    (INSTANCE UFMCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLKS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCSB")
+    (INSTANCE nUFMCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMLB")
+    (INSTANCE RDQMLI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMLS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMHB")
+    (INSTANCE RDQMHI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMHS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCASB")
+    (INSTANCE nRCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRASB")
+    (INSTANCE nRRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRASS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWEB")
+    (INSTANCE nRWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKEB")
+    (INSTANCE RCKEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKES (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLKB")
+    (INSTANCE RCLKI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLKS) (1250:1250:1250))
+      (WIDTH (negedge RCLKS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCSB")
+    (INSTANCE nRCSI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCSS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_B")
+    (INSTANCE RD_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_B")
+    (INSTANCE RD_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_B")
+    (INSTANCE RD_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_B")
+    (INSTANCE RD_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_B")
+    (INSTANCE RD_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_B")
+    (INSTANCE RD_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_B")
+    (INSTANCE RD_1_I0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_B")
+    (INSTANCE RA_11_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_B")
+    (INSTANCE RA_10_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_B")
+    (INSTANCE RA_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_B")
+    (INSTANCE RA_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_B")
+    (INSTANCE RA_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_B")
+    (INSTANCE RA_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_B")
+    (INSTANCE RA_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_B")
+    (INSTANCE RA_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_B")
+    (INSTANCE RA_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_B")
+    (INSTANCE RA_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_B")
+    (INSTANCE RA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_B")
+    (INSTANCE RA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_B")
+    (INSTANCE RBA_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_B")
+    (INSTANCE RBA_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LEDB")
+    (INSTANCE LEDI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LEDS (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWEB")
+    (INSTANCE nFWEI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWES PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWES) (1250:1250:1250))
+      (WIDTH (negedge nFWES) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRASB")
+    (INSTANCE nCRASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRASS) (1250:1250:1250))
+      (WIDTH (negedge nCRASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCASB")
+    (INSTANCE nCCASI)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCASS) (1250:1250:1250))
+      (WIDTH (negedge nCCASS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_B")
+    (INSTANCE Dout_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_B")
+    (INSTANCE Dout_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_B")
+    (INSTANCE Dout_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_B")
+    (INSTANCE Dout_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_B")
+    (INSTANCE Dout_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_B")
+    (INSTANCE Dout_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_B")
+    (INSTANCE Dout_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_B")
+    (INSTANCE Din_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_B")
+    (INSTANCE Din_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_B")
+    (INSTANCE Din_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_B")
+    (INSTANCE Din_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_B")
+    (INSTANCE Din_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_B")
+    (INSTANCE Din_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_B")
+    (INSTANCE Din_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_B")
+    (INSTANCE Din_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_B")
+    (INSTANCE CROW_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_B")
+    (INSTANCE CROW_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_B")
+    (INSTANCE MAin_9_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_B")
+    (INSTANCE MAin_8_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_B")
+    (INSTANCE MAin_7_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_B")
+    (INSTANCE MAin_6_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_B")
+    (INSTANCE MAin_5_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_B")
+    (INSTANCE MAin_4_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_B")
+    (INSTANCE MAin_3_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_B")
+    (INSTANCE MAin_2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_B")
+    (INSTANCE MAin_1_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_B")
+    (INSTANCE MAin_0_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_72I/D0 (1405:1526:1647)(1405:1526:1647))
+        (INTERCONNECT SLICE_0I/Q1 SLICE_84I/C0 (754:836:918)(754:836:918))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_0I/Q0 SLICE_69I/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_19I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_42I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_50I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_51I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_52I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLKI/PADDI SLICE_94I/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT SLICE_0I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1I/Q1 SLICE_81I/C0 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_66I/B0 (917:1024:1131)(917:1024:1131))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/C1 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_1I/Q0 SLICE_74I/D0 (602:670:739)(602:670:739))
+        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2I/Q1 SLICE_81I/B0 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_74I/D1 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_2I/Q0 SLICE_81I/D1 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A1 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_3I/Q1 SLICE_81I/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/A1 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_3I/Q0 SLICE_81I/D0 (963:1075:1187)(963:1075:1187))
+        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_64I/B1 (1823:1986:2149)(1823:1986:2149))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/B0 (1823:1986:2149)(1823:1986:2149))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_74I/B1 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_84I/B1 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4I/Q1 SLICE_87I/B0 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/D1 (1404:1527:1650)(1404:1527:1650))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_74I/B0 (913:1016:1120)(913:1016:1120))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/C1 (1560:1708:1856)(1560:1708:1856))
+        (INTERCONNECT SLICE_4I/Q0 SLICE_84I/B0 (913:1016:1120)(913:1016:1120))
+        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_56I/C0 (2087:2267:2448)(2087:2267:2448))
+        (INTERCONNECT SLICE_5I/Q1 SLICE_87I/C0 (754:836:918)(754:836:918))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_58I/C1 (1149:1260:1372)(1149:1260:1372))
+        (INTERCONNECT SLICE_5I/Q0 SLICE_84I/D1 (1397:1518:1640)(1397:1518:1640))
+        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_56I/A0 (2201:2394:2587)(2201:2394:2587))
+        (INTERCONNECT SLICE_6I/Q1 SLICE_84I/D0 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A1 (1225:1371:1517)(1225:1371:1517))
+        (INTERCONNECT SLICE_6I/Q0 SLICE_84I/A0 (1225:1371:1517)(1225:1371:1517))
+        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_56I/D0 (1803:1960:2118)(1803:1960:2118))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_68I/A1 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_7I/Q1 SLICE_69I/A1 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_72I/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_68I/D1 (876:974:1072)(876:974:1072))
+        (INTERCONNECT SLICE_8I/Q1 SLICE_69I/D1 (876:974:1072)(876:974:1072))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_68I/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_8I/Q0 SLICE_69I/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_78I/F0 SLICE_9I/D1 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_70I/F1 SLICE_9I/C1 (769:851:933)(769:851:933))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C1 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_70I/F1 SLICE_14I/C0 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_70I/F1 SLICE_67I/A0 (1295:1420:1545)(1295:1420:1545))
+        (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (606:674:742)(606:674:742))
+        (INTERCONNECT SLICE_70I/F1 SLICE_90I/C1 (769:851:933)(769:851:933))
+        (INTERCONNECT SLICE_85I/F1 SLICE_9I/B1 (2100:2300:2500)(2100:2300:2500))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (1802:1995:2189)(1802:1995:2189))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_66I/M0 (1606:1757:1909)(1606:1757:1909))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_67I/C0 (2131:2353:2575)(2131:2353:2575))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D0 (2379:2611:2843)(2379:2611:2843))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B1 (1395:1576:1757)(1395:1576:1757))
+        (INTERCONNECT MAin_0_I/PADDI SLICE_90I/B0 (1395:1576:1757)(1395:1576:1757))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/D0 (517:575:634)(517:575:634))
+        (INTERCONNECT SLICE_9I/Q0 SLICE_20I/A1 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_70I/F0 SLICE_9I/C0 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_9I/F1 SLICE_9I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_9I/F1 SLICE_20I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_14I/F1 SLICE_9I/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_14I/F1 SLICE_14I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_14I/F1 SLICE_20I/M0 (1301:1429:1558)(1301:1429:1558))
+        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_22I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_26I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_39I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_42I/M1 (2017:2199:2381)(2017:2199:2381))
+        (INTERCONNECT PHI2I/PADDI SLICE_57I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_70I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_71I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_73I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_74I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_76I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2I/PADDI SLICE_77I/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT SLICE_77I/F0 SLICE_14I/B1 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_76I/F0 SLICE_14I/A1 (837:931:1026)(837:931:1026))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_14I/B0 (1984:2189:2395)(1984:2189:2395))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_66I/M1 (1925:2114:2304)(1925:2114:2304))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_67I/D0 (1636:1793:1950)(1636:1793:1950))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_70I/C0 (2423:2682:2941)(2423:2682:2941))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_77I/D0 (2046:2232:2419)(2046:2232:2419))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_78I/D0 (1522:1684:1847)(1522:1684:1847))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_90I/A1 (2718:2965:3212)(2718:2965:3212))
+        (INTERCONNECT MAin_1_I/PADDI SLICE_91I/B0 (2379:2611:2843)(2379:2611:2843))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_14I/Q0 SLICE_20I/C0 (1431:1576:1722)(1431:1576:1722))
+        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/D1 (571:629:687)(571:629:687))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_19I/A0 (575:636:697)(575:636:697))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_41I/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C1 (808:893:978)(808:893:978))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_50I/C0 (808:893:978)(808:893:978))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_60I/C1 (1211:1325:1439)(1211:1325:1439))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_63I/B0 (968:1072:1177)(968:1072:1177))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B1 (1236:1372:1509)
+          (1236:1372:1509))
+        (INTERCONNECT SLICE_19I/Q0 nRWE_RNO_1_SLICE_65I/B0 (1236:1372:1509)
+          (1236:1372:1509))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_73I/B1 (947:1054:1161)(947:1054:1161))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_79I/D0 (653:719:785)(653:719:785))
+        (INTERCONNECT SLICE_19I/Q0 SLICE_80I/A0 (922:1019:1117)(922:1019:1117))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C1 (788:872:957)(788:872:957))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_19I/C0 (788:872:957)(788:872:957))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_41I/A1 (1312:1438:1565)(1312:1438:1565))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A1 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_50I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/C1 (1839:2035:2231)(1839:2035:2231))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_59I/B0 (1710:1891:2072)(1710:1891:2072))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_63I/A0 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/A1 (1191:1322:1454)
+          (1191:1322:1454))
+        (INTERCONNECT SLICE_50I/Q0 nRWE_RNO_1_SLICE_65I/D0 (633:698:764)(633:698:764))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_73I/D1 (1332:1461:1591)(1332:1461:1591))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_79I/A0 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50I/Q0 SLICE_94I/C0 (2356:2575:2795)(2356:2575:2795))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_19I/B1 (863:960:1057)(863:960:1057))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/A1 (810:899:989)(810:899:989))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_31I/C0 (696:773:850)(696:773:850))
+        (INTERCONNECT SLICE_31I/Q0 SLICE_83I/B1 (863:960:1057)(863:960:1057))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/A1 (1282:1411:1540)(1282:1411:1540))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_19I/LSR (1320:1453:1587)(1320:1453:1587))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A1 (1688:1854:2020)(1688:1854:2020))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_42I/A0 (1688:1854:2020)(1688:1854:2020))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_43I/B1 (1328:1464:1600)(1328:1464:1600))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_50I/LSR (1320:1453:1587)(1320:1453:1587))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_52I/M1 (889:990:1091)(889:990:1091))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_61I/B1 (1726:1896:2067)(1726:1896:2067))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_62I/A1 (2115:2317:2519)(2115:2317:2519))
+        (INTERCONNECT SLICE_51I/Q1 nRWE_RNO_1_SLICE_65I/D1 (582:647:712)(582:647:712))
+        (INTERCONNECT SLICE_51I/Q1 SLICE_73I/C1 (1571:1716:1862)(1571:1716:1862))
+        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19I/F1 SLICE_43I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_19I/F1 SLICE_44I/B1 (1394:1526:1659)(1394:1526:1659))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_20I/Q0 SLICE_67I/B0 (1409:1541:1674)(1409:1541:1674))
+        (INTERCONNECT SLICE_90I/F1 SLICE_20I/B0 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_20I/OFX0 SLICE_20I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din_5_I/PADDI SLICE_21I/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din_5_I/PADDI SLICE_55I/M1 (2758:3009:3261)(2758:3009:3261))
+        (INTERCONNECT Din_5_I/PADDI SLICE_67I/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din_5_I/PADDI SLICE_75I/A0 (1511:1671:1831)(1511:1671:1831))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/D1 (1242:1370:1499)(1242:1370:1499))
+        (INTERCONNECT Din_5_I/PADDI SLICE_76I/M1 (1549:1713:1878)(1549:1713:1878))
+        (INTERCONNECT Din_5_I/PADDI SLICE_78I/B1 (2391:2619:2848)(2391:2619:2848))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din_5_I/PADDI SLICE_82I/D0 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din_5_I/PADDI SLICE_85I/A0 (1876:2059:2243)(1876:2059:2243))
+        (INTERCONNECT Din_3_I/PADDI SLICE_21I/C1 (1790:1964:2139)(1790:1964:2139))
+        (INTERCONNECT Din_3_I/PADDI SLICE_57I/C1 (2200:2404:2608)(2200:2404:2608))
+        (INTERCONNECT Din_3_I/PADDI SLICE_67I/B1 (1930:2123:2316)(1930:2123:2316))
+        (INTERCONNECT Din_3_I/PADDI SLICE_71I/M1 (2355:2576:2798)(2355:2576:2798))
+        (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (2606:2857:3109)(2606:2857:3109))
+        (INTERCONNECT Din_3_I/PADDI SLICE_78I/C1 (1790:1964:2139)(1790:1964:2139))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/A1 (1904:2091:2278)(1904:2091:2278))
+        (INTERCONNECT Din_3_I/PADDI SLICE_82I/A0 (1904:2091:2278)(1904:2091:2278))
+        (INTERCONNECT Din_3_I/PADDI SLICE_85I/M1 (1922:2112:2303)(1922:2112:2303))
+        (INTERCONNECT SLICE_75I/F1 SLICE_21I/B1 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_75I/F1 SLICE_26I/D1 (616:686:757)(616:686:757))
+        (INTERCONNECT SLICE_75I/F1 SLICE_67I/A1 (864:963:1063)(864:963:1063))
+        (INTERCONNECT SLICE_75I/F1 SLICE_75I/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B1 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_75I/F1 SLICE_82I/B0 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_21I/F1 SLICE_21I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_21I/F1 SLICE_26I/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_21I/C0 (1644:1786:1929)(1644:1786:1929))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/D1 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_33I/Q0 SLICE_57I/B0 (2611:2837:3063)(2611:2837:3063))
+        (INTERCONNECT SLICE_75I/F0 SLICE_21I/B0 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_82I/F1 SLICE_21I/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/F0 SLICE_21I/CE (573:634:695)(573:634:695))
+        (INTERCONNECT SLICE_67I/F0 SLICE_26I/CE (573:634:695)(573:634:695))
+        (INTERCONNECT SLICE_67I/F0 SLICE_57I/CE (906:1005:1104)(906:1005:1104))
+        (INTERCONNECT SLICE_67I/F0 SLICE_67I/C1 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_67I/F0 SLICE_82I/C0 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_33I/B0 (1797:1958:2120)(1797:1958:2120))
+        (INTERCONNECT SLICE_21I/Q0 SLICE_82I/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_22I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_22I/Q0 SLICE_52I/A1 (1157:1286:1415)(1157:1286:1415))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_22I/C1 (1016:1133:1251)(1016:1133:1251))
+        (INTERCONNECT SLICE_43I/Q1 SLICE_52I/D1 (861:959:1058)(861:959:1058))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_22I/B1 (1300:1432:1564)(1300:1432:1564))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_43I/M1 (1695:1853:2012)(1695:1853:2012))
+        (INTERCONNECT SLICE_41I/Q1 SLICE_52I/B1 (1703:1864:2025)(1703:1864:2025))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_22I/A1 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/C1 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_32I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_33I/D0 (1042:1139:1236)(1042:1139:1236))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/A1 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_43I/A0 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_44I/A1 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_51I/C1 (1197:1313:1429)(1197:1313:1429))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_52I/C1 (1197:1313:1429)(1197:1313:1429))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/A1 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_58I/A0 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_64I/A1 (1311:1439:1568)(1311:1439:1568))
+        (INTERCONNECT SLICE_32I/Q0 nRWE_RNO_1_SLICE_65I/A0 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/C1 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_66I/C0 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32I/Q0 SLICE_73I/A1 (1304:1431:1559)(1304:1431:1559))
+        (INTERCONNECT SLICE_82I/F0 SLICE_22I/D0 (1778:1934:2090)(1778:1934:2090))
+        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22I/F1 SLICE_68I/D0 (975:1068:1161)(975:1068:1161))
+        (INTERCONNECT SLICE_22I/F1 SLICE_69I/B0 (1290:1421:1553)(1290:1421:1553))
+        (INTERCONNECT SLICE_78I/F1 SLICE_26I/C1 (735:822:909)(735:822:909))
+        (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_26I/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_26I/Q0 SLICE_58I/B0 (899:1000:1102)(899:1000:1102))
+        (INTERCONNECT SLICE_76I/F1 SLICE_26I/A1 (1348:1473:1599)(1348:1473:1599))
+        (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_26I/D0 (580:648:716)(580:648:716))
+        (INTERCONNECT SLICE_58I/Q0 SLICE_39I/A0 (2063:2250:2438)(2063:2250:2438))
+        (INTERCONNECT SLICE_26I/F1 SLICE_26I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83I/F1 SLICE_29I/D1 (1406:1541:1676)(1406:1541:1676))
+        (INTERCONNECT SLICE_83I/F1 SLICE_59I/A1 (2154:2337:2521)(2154:2337:2521))
+        (INTERCONNECT SLICE_83I/F1 SLICE_61I/D0 (1695:1864:2034)(1695:1864:2034))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C1 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73I/F1 SLICE_29I/C0 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73I/F1 SLICE_59I/B1 (1836:2003:2171)(1836:2003:2171))
+        (INTERCONNECT SLICE_73I/F1 SLICE_61I/C0 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73I/F1 SLICE_73I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_73I/F1 SLICE_94I/C1 (1680:1833:1986)(1680:1833:1986))
+        (INTERCONNECT SLICE_61I/F1 SLICE_29I/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A1 (832:922:1012)(832:922:1012))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_29I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D1 (623:687:752)(623:687:752))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_30I/D0 (623:687:752)(623:687:752))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_31I/A0 (1302:1427:1553)(1302:1427:1553))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_42I/B1 (1703:1883:2063)(1703:1883:2063))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_61I/A0 (832:922:1012)(832:922:1012))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_83I/D0 (1033:1127:1221)(1033:1127:1221))
+        (INTERCONNECT SLICE_29I/Q0 SLICE_94I/M0 (2098:2304:2511)(2098:2304:2511))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_29I/B0 (1347:1503:1660)(1347:1503:1660))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_41I/B0 (948:1050:1153)(948:1050:1153))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/D1 (578:636:695)(578:636:695))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_43I/D0 (578:636:695)(578:636:695))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_44I/D1 (633:697:761)(633:697:761))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_50I/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_59I/D1 (1435:1582:1729)(1435:1582:1729))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_61I/C1 (1476:1647:1819)(1476:1647:1819))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_62I/B1 (2176:2379:2582)(2176:2379:2582))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C1 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_63I/C0 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43I/Q0 nRWE_RNO_1_SLICE_65I/M0 (640:705:770)(640:705:770))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_73I/A0 (1191:1321:1451)(1191:1321:1451))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_79I/C1 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/D1 (2271:2465:2659)(2271:2465:2659))
+        (INTERCONNECT SLICE_43I/Q0 SLICE_94I/D0 (2271:2465:2659)(2271:2465:2659))
+        (INTERCONNECT SLICE_29I/F0 SLICE_29I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29I/F1 SLICE_60I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_30I/C1 (696:773:850)(696:773:850))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D1 (991:1107:1224)(991:1107:1224))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_31I/D0 (991:1107:1224)(991:1107:1224))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_42I/C1 (1560:1700:1840)(1560:1700:1840))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C1 (1146:1281:1417)(1146:1281:1417))
+        (INTERCONNECT SLICE_30I/Q1 SLICE_83I/C0 (1146:1281:1417)(1146:1281:1417))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A1 (825:914:1004)(825:914:1004))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_30I/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B1 (943:1046:1150)(943:1046:1150))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_31I/B0 (943:1046:1150)(943:1046:1150))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_42I/D1 (1109:1203:1297)(1109:1203:1297))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A1 (897:993:1090)(897:993:1090))
+        (INTERCONNECT SLICE_30I/Q0 SLICE_83I/A0 (897:993:1090)(897:993:1090))
+        (INTERCONNECT SLICE_30I/F1 SLICE_30I/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94I/F1 SLICE_30I/CE (1885:2046:2208)(1885:2046:2208))
+        (INTERCONNECT SLICE_94I/F1 SLICE_31I/CE (2184:2374:2565)(2184:2374:2565))
+        (INTERCONNECT SLICE_73I/F0 SLICE_31I/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31I/F1 SLICE_94I/LSR (1908:2070:2233)(1908:2070:2233))
+        (INTERCONNECT SLICE_56I/F0 SLICE_32I/D1 (1374:1495:1616)(1374:1495:1616))
+        (INTERCONNECT SLICE_84I/F1 SLICE_32I/B1 (1172:1308:1444)(1172:1308:1444))
+        (INTERCONNECT SLICE_72I/F1 SLICE_32I/A1 (1239:1383:1527)(1239:1383:1527))
+        (INTERCONNECT SLICE_72I/F1 SLICE_58I/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_72I/F1 SLICE_64I/C1 (1575:1727:1879)(1575:1727:1879))
+        (INTERCONNECT SLICE_72I/F1 SLICE_72I/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_74I/F0 SLICE_32I/D0 (245:274:304)(245:274:304))
+        (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32I/F1 SLICE_87I/D1 (245:274:304)(245:274:304))
+        (INTERCONNECT nCRASI/PADDI SLICE_33I/C1 (1635:1825:2016)(1635:1825:2016))
+        (INTERCONNECT nCRASI/PADDI SLICE_44I/M1 (1526:1687:1849)(1526:1687:1849))
+        (INTERCONNECT nCRASI/PADDI SLICE_66I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_67I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_72I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_80I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_81I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_83I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRASI/PADDI SLICE_88I/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_33I/A1 (1758:1913:2068)(1758:1913:2068))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_41I/D0 (1892:2044:2197)(1892:2044:2197))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_60I/D0 (1405:1538:1671)(1405:1538:1671))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_63I/A1 (1634:1807:1981)(1634:1807:1981))
+        (INTERCONNECT SLICE_78I/Q0 SLICE_79I/B0 (1969:2184:2399)(1969:2184:2399))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_33I/A0 (1377:1528:1680)(1377:1528:1680))
+        (INTERCONNECT UFMSDOI/PADDI SLICE_58I/D0 (2317:2524:2731)(2317:2524:2731))
+        (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69I/F0 SLICE_33I/CE (1070:1165:1260)(1070:1165:1260))
+        (INTERCONNECT SLICE_33I/F1 LEDI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/D1 (1908:2070:2232)(1908:2070:2232))
+        (INTERCONNECT SLICE_57I/Q0 SLICE_39I/D0 (1908:2070:2232)(1908:2070:2232))
+        (INTERCONNECT SLICE_85I/F0 SLICE_39I/B1 (1792:1955:2118)(1792:1955:2118))
+        (INTERCONNECT SLICE_85I/F0 SLICE_57I/D1 (1477:1601:1726)(1477:1601:1726))
+        (INTERCONNECT Din_6_I/PADDI SLICE_39I/B0 (2577:2847:3118)(2577:2847:3118))
+        (INTERCONNECT Din_6_I/PADDI SLICE_56I/M0 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT Din_6_I/PADDI SLICE_75I/A1 (2528:2792:3057)(2528:2792:3057))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/B0 (2695:2961:3228)(2695:2961:3228))
+        (INTERCONNECT Din_6_I/PADDI SLICE_77I/M0 (2387:2616:2845)(2387:2616:2845))
+        (INTERCONNECT Din_6_I/PADDI SLICE_78I/C0 (2520:2764:3008)(2520:2764:3008))
+        (INTERCONNECT Din_6_I/PADDI SLICE_85I/D0 (1973:2170:2368)(1973:2170:2368))
+        (INTERCONNECT SLICE_39I/F0 SLICE_39I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_39I/LSR (1723:1881:2040)(1723:1881:2040))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_44I/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_66I/LSR (910:1010:1110)(910:1010:1110))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_67I/LSR (1730:1889:2048)(1730:1889:2048))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_72I/LSR (1730:1889:2048)(1730:1889:2048))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/LSR (1320:1449:1579)(1320:1449:1579))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/LSR (910:1010:1110)(910:1010:1110))
+        (INTERCONNECT SLICE_44I/Q0 SLICE_88I/LSR (1723:1881:2040)(1723:1881:2040))
+        (INTERCONNECT SLICE_39I/Q0 RA_11_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_39I/F1 SLICE_57I/A0 (2170:2363:2556)(2170:2363:2556))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_41I/C1 (2032:2205:2379)(2032:2205:2379))
+        (INTERCONNECT SLICE_81I/Q1 SLICE_60I/B1 (1789:1953:2117)(1789:1953:2117))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_41I/B1 (1295:1427:1559)(1295:1427:1559))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_60I/A1 (2074:2266:2459)(2074:2266:2459))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_79I/B1 (1717:1887:2058)(1717:1887:2058))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_80I/C1 (1557:1708:1859)(1557:1708:1859))
+        (INTERCONNECT SLICE_75I/Q1 SLICE_82I/M0 (884:984:1085)(884:984:1085))
+        (INTERCONNECT SLICE_41I/F1 SLICE_41I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_43I/F1 SLICE_41I/A0 (833:932:1032)(833:932:1032))
+        (INTERCONNECT SLICE_41I/F0 SLICE_41I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q1 SLICE_41I/M1 (1773:1932:2091)(1773:1932:2091))
+        (INTERCONNECT SLICE_41I/Q0 SLICE_42I/B0 (1781:1942:2104)(1781:1942:2104))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_42I/D0 (1398:1530:1663)(1398:1530:1663))
+        (INTERCONNECT SLICE_44I/Q1 SLICE_51I/M1 (1386:1516:1646)(1386:1516:1646))
+        (INTERCONNECT SLICE_52I/Q1 SLICE_42I/C0 (1621:1763:1905)(1621:1763:1905))
+        (INTERCONNECT SLICE_42I/F0 SLICE_42I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42I/Q0 SLICE_61I/A1 (1247:1371:1495)(1247:1371:1495))
+        (INTERCONNECT SLICE_42I/Q0 nRWE_RNO_1_SLICE_65I/C1 (2228:2432:2636)
+          (2228:2432:2636))
+        (INTERCONNECT SLICE_42I/Q0 RCKEI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_42I/F1 nRWE_RNO_1_SLICE_65I/C0 (1537:1688:1840)
+          (1537:1688:1840))
+        (INTERCONNECT SLICE_50I/F0 SLICE_43I/C1 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (31:31:31)(31:31:31))
+        (INTERCONNECT SLICE_50I/F0 SLICE_61I/D1 (970:1082:1195)(970:1082:1195))
+        (INTERCONNECT SLICE_50I/F0 SLICE_62I/C1 (1575:1727:1879)(1575:1727:1879))
+        (INTERCONNECT SLICE_83I/F0 SLICE_43I/C0 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_83I/F0 SLICE_44I/C1 (739:821:903)(739:821:903))
+        (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50I/F1 SLICE_63I/LSR (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_73I/Q0 SLICE_51I/D1 (1335:1476:1617)(1335:1476:1617))
+        (INTERCONNECT SLICE_72I/F0 SLICE_51I/B1 (1781:1942:2104)(1781:1942:2104))
+        (INTERCONNECT SLICE_66I/F0 SLICE_51I/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_66I/F0 SLICE_66I/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_52I/F1 SLICE_51I/D0 (877:975:1074)(877:975:1074))
+        (INTERCONNECT SLICE_52I/F1 SLICE_52I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_52I/F1 SLICE_64I/A0 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_51I/F1 SLICE_51I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_64I/F1 SLICE_51I/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_64I/F1 SLICE_52I/A0 (868:962:1057)(868:962:1057))
+        (INTERCONNECT SLICE_64I/F1 SLICE_64I/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_51I/Q0 SLICE_51I/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_51I/Q0 UFMCLKI/PADDO (1184:1361:1538)(1184:1361:1538))
+        (INTERCONNECT SLICE_51I/F0 SLICE_51I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87I/F1 SLICE_52I/D0 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_52I/Q0 SLICE_52I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_52I/Q0 UFMSDII/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_52I/F0 SLICE_52I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67I/Q0 SLICE_55I/D0 (1466:1589:1712)(1466:1589:1712))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_55I/B0 (2114:2313:2513)(2114:2313:2513))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/A1 (1678:1840:2002)(1678:1840:2002))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_86I/A0 (1678:1840:2002)(1678:1840:2002))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D1 (2224:2421:2618)(2224:2421:2618))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_89I/D0 (2224:2421:2618)(2224:2421:2618))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_90I/A0 (1802:1970:2138)(1802:1970:2138))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/D1 (1796:1956:2117)(1796:1956:2117))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_91I/C0 (1954:2134:2314)(1954:2134:2314))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/D1 (2320:2504:2689)(2320:2504:2689))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_92I/D0 (2320:2504:2689)(2320:2504:2689))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B1 (2543:2782:3021)(2543:2782:3021))
+        (INTERCONNECT SLICE_63I/Q0 SLICE_93I/B0 (2543:2782:3021)(2543:2782:3021))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_55I/A0 (2220:2446:2672)(2220:2446:2672))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_67I/M0 (2701:2972:3244)(2701:2972:3244))
+        (INTERCONNECT MAin_4_I/PADDI SLICE_71I/A1 (2663:2930:3197)(2663:2930:3197))
+        (INTERCONNECT Din_4_I/PADDI SLICE_55I/M0 (2067:2260:2454)(2067:2260:2454))
+        (INTERCONNECT Din_4_I/PADDI SLICE_75I/C1 (1378:1524:1670)(1378:1524:1670))
+        (INTERCONNECT Din_4_I/PADDI SLICE_76I/M0 (1530:1693:1856)(1530:1693:1856))
+        (INTERCONNECT Din_4_I/PADDI SLICE_77I/A1 (2732:2985:3238)(2732:2985:3238))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/B1 (1973:2177:2381)(1973:2177:2381))
+        (INTERCONNECT Din_4_I/PADDI SLICE_85I/B0 (1973:2177:2381)(1973:2177:2381))
+        (INTERCONNECT nCCASI/PADDI SLICE_55I/CLK (1242:1370:1498)(1242:1370:1498))
+        (INTERCONNECT nCCASI/PADDI SLICE_56I/CLK (2109:2309:2510)(2109:2309:2510))
+        (INTERCONNECT nCCASI/PADDI SLICE_75I/M0 (1503:1660:1818)(1503:1660:1818))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M0 (2373:2602:2831)(2373:2602:2831))
+        (INTERCONNECT nCCASI/PADDI SLICE_78I/M1 (2373:2602:2831)(2373:2602:2831))
+        (INTERCONNECT nCCASI/PADDI SLICE_79I/CLK (1706:1877:2049)(1706:1877:2049))
+        (INTERCONNECT nCCASI/PADDI SLICE_85I/CLK (1706:1877:2049)(1706:1877:2049))
+        (INTERCONNECT nCCASI/PADDI SLICE_88I/D0 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_55I/F0 RA_4_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_55I/Q0 RD_4_I/PADDO (2378:2648:2918)(2378:2648:2918))
+        (INTERCONNECT SLICE_55I/Q1 RD_5_I/PADDO (1982:2228:2475)(1982:2228:2475))
+        (INTERCONNECT SLICE_76I/Q1 SLICE_56I/D1 (1498:1630:1763)(1498:1630:1763))
+        (INTERCONNECT SLICE_71I/Q0 SLICE_56I/C1 (1653:1804:1956)(1653:1804:1956))
+        (INTERCONNECT SLICE_77I/Q0 SLICE_56I/B1 (1813:1984:2155)(1813:1984:2155))
+        (INTERCONNECT SLICE_77I/Q1 SLICE_56I/A1 (2138:2321:2505)(2138:2321:2505))
+        (INTERCONNECT Din_7_I/PADDI SLICE_56I/M1 (2264:2497:2730)(2264:2497:2730))
+        (INTERCONNECT Din_7_I/PADDI SLICE_75I/B1 (1828:2016:2205)(1828:2016:2205))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/C1 (1272:1412:1553)(1272:1412:1553))
+        (INTERCONNECT Din_7_I/PADDI SLICE_77I/M1 (1424:1581:1739)(1424:1581:1739))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C1 (2522:2767:3013)(2522:2767:3013))
+        (INTERCONNECT Din_7_I/PADDI SLICE_85I/C0 (2522:2767:3013)(2522:2767:3013))
+        (INTERCONNECT SLICE_56I/Q0 RD_6_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_56I/F1 SLICE_70I/B1 (1813:1984:2155)(1813:1984:2155))
+        (INTERCONNECT SLICE_56I/Q1 RD_7_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT Din_2_I/PADDI SLICE_57I/B1 (1547:1713:1879)(1547:1713:1879))
+        (INTERCONNECT Din_2_I/PADDI SLICE_71I/M0 (1539:1702:1866)(1539:1702:1866))
+        (INTERCONNECT Din_2_I/PADDI SLICE_73I/M1 (1921:2109:2298)(1921:2109:2298))
+        (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (1904:2092:2280)(1904:2092:2280))
+        (INTERCONNECT Din_2_I/PADDI SLICE_78I/A0 (1904:2092:2280)(1904:2092:2280))
+        (INTERCONNECT Din_2_I/PADDI SLICE_85I/M0 (2324:2541:2759)(2324:2541:2759))
+        (INTERCONNECT Din_0_I/PADDI SLICE_57I/A1 (1891:2077:2264)(1891:2077:2264))
+        (INTERCONNECT Din_0_I/PADDI SLICE_70I/M0 (2325:2544:2764)(2325:2544:2764))
+        (INTERCONNECT Din_0_I/PADDI SLICE_74I/M0 (1529:1691:1854)(1529:1691:1854))
+        (INTERCONNECT Din_0_I/PADDI SLICE_76I/B1 (1937:2130:2324)(1937:2130:2324))
+        (INTERCONNECT Din_0_I/PADDI SLICE_79I/M0 (2739:2994:3250)(2739:2994:3250))
+        (INTERCONNECT Din_0_I/PADDI SLICE_85I/A1 (2297:2513:2729)(2297:2513:2729))
+        (INTERCONNECT Din_1_I/PADDI SLICE_57I/D0 (1217:1343:1469)(1217:1343:1469))
+        (INTERCONNECT Din_1_I/PADDI SLICE_70I/M1 (714:807:900)(714:807:900))
+        (INTERCONNECT Din_1_I/PADDI SLICE_73I/M0 (1521:1678:1835)(1521:1678:1835))
+        (INTERCONNECT Din_1_I/PADDI SLICE_75I/D0 (1217:1343:1469)(1217:1343:1469))
+        (INTERCONNECT Din_1_I/PADDI SLICE_76I/B0 (1421:1579:1738)(1421:1579:1738))
+        (INTERCONNECT Din_1_I/PADDI SLICE_79I/M1 (1959:2159:2360)(1959:2159:2360))
+        (INTERCONNECT Din_1_I/PADDI SLICE_85I/D1 (1941:2140:2339)(1941:2140:2339))
+        (INTERCONNECT SLICE_57I/F1 SLICE_57I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58I/F0 SLICE_58I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68I/F0 SLICE_58I/CE (875:974:1073)(875:974:1073))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/B1 (1544:1731:1919)(1544:1731:1919))
+        (INTERCONNECT SLICE_58I/F1 SLICE_87I/D0 (940:1054:1169)(940:1054:1169))
+        (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_62I/F1 SLICE_59I/C0 (1669:1820:1972)(1669:1820:1972))
+        (INTERCONNECT SLICE_62I/F1 SLICE_62I/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_80I/F0 SLICE_59I/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_60I/D1 (1509:1643:1777)(1509:1643:1777))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_63I/D1 (1491:1617:1743)(1491:1617:1743))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_79I/D1 (1491:1617:1743)(1491:1617:1743))
+        (INTERCONNECT SLICE_82I/Q0 SLICE_80I/B1 (2209:2402:2596)(2209:2402:2596))
+        (INTERCONNECT SLICE_94I/F0 SLICE_60I/C0 (1529:1669:1809)(1529:1669:1809))
+        (INTERCONNECT SLICE_60I/F1 SLICE_60I/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (1291:1473:1656)(1291:1473:1656))
+        (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (1935:2190:2445)(1935:2190:2445))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_62I/D1 (1079:1173:1267)(1079:1173:1267))
+        (INTERCONNECT SLICE_78I/Q1 SLICE_80I/C0 (1637:1779:1921)(1637:1779:1921))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_62I/D0 (1679:1834:1990)(1679:1834:1990))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_63I/B1 (1691:1860:2030)(1691:1860:2030))
+        (INTERCONNECT SLICE_81I/Q0 SLICE_80I/D0 (1376:1507:1638)(1376:1507:1638))
+        (INTERCONNECT nRWE_RNO_1_SLICE_65I/OFX0 SLICE_62I/C0 (1653:1804:1956)
+          (1653:1804:1956))
+        (INTERCONNECT SLICE_79I/F0 SLICE_62I/A0 (1651:1815:1979)(1651:1815:1979))
+        (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62I/Q0 nRWEI/PADDO (2095:2345:2595)(2095:2345:2595))
+        (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64I/Q0 SLICE_64I/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_64I/Q0 nUFMCSI/PADDO (1548:1774:2000)(1548:1774:2000))
+        (INTERCONNECT SLICE_66I/F1 SLICE_64I/C0 (1529:1669:1809)(1529:1669:1809))
+        (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73I/Q1 SLICE_66I/B1 (1247:1397:1548)(1247:1397:1548))
+        (INTERCONNECT SLICE_81I/F0 SLICE_66I/D0 (1383:1512:1642)(1383:1512:1642))
+        (INTERCONNECT SLICE_81I/F0 SLICE_74I/A0 (1652:1813:1974)(1652:1813:1974))
+        (INTERCONNECT SLICE_74I/F1 SLICE_66I/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_74I/F1 SLICE_74I/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_66I/Q0 SLICE_90I/D0 (1375:1502:1629)(1375:1502:1629))
+        (INTERCONNECT SLICE_66I/Q1 SLICE_91I/D0 (1901:2062:2224)(1901:2062:2224))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_67I/M1 (1621:1774:1928)(1621:1774:1928))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_71I/D1 (1614:1766:1919)(1614:1766:1919))
+        (INTERCONNECT MAin_5_I/PADDI SLICE_93I/A1 (1908:2101:2294)(1908:2101:2294))
+        (INTERCONNECT SLICE_67I/F1 SLICE_73I/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_67I/F1 SLICE_74I/CE (1350:1494:1639)(1350:1494:1639))
+        (INTERCONNECT SLICE_67I/Q1 SLICE_93I/D1 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT SLICE_87I/F0 SLICE_68I/C0 (735:822:909)(735:822:909))
+        (INTERCONNECT SLICE_87I/F0 SLICE_69I/D0 (580:648:716)(580:648:716))
+        (INTERCONNECT SLICE_68I/F1 SLICE_68I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_84I/F0 SLICE_68I/A0 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_84I/F0 SLICE_69I/A0 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_69I/F1 SLICE_69I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_70I/Q0 SLICE_70I/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71I/F0 SLICE_70I/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_70I/Q1 SLICE_70I/A1 (514:575:636)(514:575:636))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_71I/C1 (1805:1987:2169)(1805:1987:2169))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_88I/M1 (1657:1821:1985)(1657:1821:1985))
+        (INTERCONNECT MAin_7_I/PADDI SLICE_91I/B1 (2368:2598:2829)(2368:2598:2829))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_71I/B1 (1951:2152:2353)(1951:2152:2353))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_88I/M0 (2353:2581:2809)(2353:2581:2809))
+        (INTERCONNECT MAin_6_I/PADDI SLICE_92I/C1 (3008:3283:3558)(3008:3283:3558))
+        (INTERCONNECT SLICE_71I/F1 SLICE_71I/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71I/Q1 SLICE_71I/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_76I/Q0 SLICE_71I/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_88I/F1 SLICE_71I/A0 (1490:1668:1846)(1490:1668:1846))
+        (INTERCONNECT SLICE_81I/F1 SLICE_72I/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_72I/M1 (1657:1821:1985)(1657:1821:1985))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_88I/A1 (1919:2113:2308)(1919:2113:2308))
+        (INTERCONNECT MAin_3_I/PADDI SLICE_93I/A0 (2322:2545:2769)(2322:2545:2769))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_72I/M0 (1606:1757:1909)(1606:1757:1909))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_88I/B1 (1519:1681:1844)(1519:1681:1844))
+        (INTERCONNECT MAin_2_I/PADDI SLICE_92I/B0 (2326:2552:2779)(2326:2552:2779))
+        (INTERCONNECT SLICE_72I/Q0 SLICE_92I/C0 (1653:1804:1956)(1653:1804:1956))
+        (INTERCONNECT SLICE_72I/Q1 SLICE_93I/D0 (1466:1589:1712)(1466:1589:1712))
+        (INTERCONNECT SLICE_74I/Q0 SLICE_87I/C1 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_77I/F1 SLICE_77I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_79I/F1 SLICE_79I/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_79I/Q0 RD_0_I/PADDO (1164:1346:1528)(1164:1346:1528))
+        (INTERCONNECT SLICE_79I/Q1 RD_1_I0/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_80I/M1 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/C1 (1769:1940:2112)(1769:1940:2112))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_86I/C0 (1769:1940:2112)(1769:1940:2112))
+        (INTERCONNECT MAin_9_I/PADDI SLICE_89I/C1 (2608:2849:3090)(2608:2849:3090))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_80I/M0 (1508:1668:1828)(1508:1668:1828))
+        (INTERCONNECT MAin_8_I/PADDI SLICE_89I/C0 (3001:3275:3550)(3001:3275:3550))
+        (INTERCONNECT SLICE_80I/Q0 SLICE_89I/B0 (1247:1397:1548)(1247:1397:1548))
+        (INTERCONNECT SLICE_80I/Q1 SLICE_86I/B0 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M0 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT nFWEI/PADDI SLICE_81I/M1 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C1 (2204:2414:2624)(2204:2414:2624))
+        (INTERCONNECT nFWEI/PADDI SLICE_88I/C0 (2204:2414:2624)(2204:2414:2624))
+        (INTERCONNECT CROW_1_I/PADDI SLICE_83I/M1 (2038:2228:2418)(2038:2228:2418))
+        (INTERCONNECT CROW_0_I/PADDI SLICE_83I/M0 (2307:2528:2750)(2307:2528:2750))
+        (INTERCONNECT SLICE_83I/Q0 RBA_0_I/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_83I/Q1 RBA_1_I/PADDO (2466:2735:3005)(2466:2735:3005))
+        (INTERCONNECT SLICE_85I/Q0 RD_2_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_85I/Q1 RD_3_I/PADDO (1568:1777:1987)(1568:1777:1987))
+        (INTERCONNECT SLICE_86I/F0 RA_9_I/PADDO (2477:2778:3080)(2477:2778:3080))
+        (INTERCONNECT SLICE_86I/F1 RDQMLI/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT SLICE_88I/F0 RD_0_I/PADDT (1756:2001:2247)(1756:2001:2247))
+        (INTERCONNECT SLICE_88I/F0 RD_7_I/PADDT (2571:2883:3195)(2571:2883:3195))
+        (INTERCONNECT SLICE_88I/F0 RD_6_I/PADDT (2571:2883:3195)(2571:2883:3195))
+        (INTERCONNECT SLICE_88I/F0 RD_5_I/PADDT (2538:2838:3139)(2538:2838:3139))
+        (INTERCONNECT SLICE_88I/F0 RD_4_I/PADDT (2538:2838:3139)(2538:2838:3139))
+        (INTERCONNECT SLICE_88I/F0 RD_3_I/PADDT (1741:1997:2254)(1741:1997:2254))
+        (INTERCONNECT SLICE_88I/F0 RD_2_I/PADDT (1741:1997:2254)(1741:1997:2254))
+        (INTERCONNECT SLICE_88I/F0 RD_1_I0/PADDT (2098:2368:2638)(2098:2368:2638))
+        (INTERCONNECT SLICE_88I/Q0 SLICE_92I/A1 (1735:1889:2044)(1735:1889:2044))
+        (INTERCONNECT SLICE_88I/Q1 SLICE_91I/C1 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_89I/F0 RA_8_I/PADDO (1979:2229:2479)(1979:2229:2479))
+        (INTERCONNECT SLICE_89I/F1 RDQMHI/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_90I/F0 RA_0_I/PADDO (1723:1947:2172)(1723:1947:2172))
+        (INTERCONNECT SLICE_91I/F0 RA_1_I/PADDO (1971:2209:2448)(1971:2209:2448))
+        (INTERCONNECT SLICE_91I/F1 RA_7_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_92I/F0 RA_2_I/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_92I/F1 RA_6_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_93I/F0 RA_3_I/PADDO (1610:1831:2052)(1610:1831:2052))
+        (INTERCONNECT SLICE_93I/F1 RA_5_I/PADDO (1982:2228:2475)(1982:2228:2475))
+        (INTERCONNECT SLICE_94I/Q0 RA_10_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (2942:3272:3602)(2942:3272:3602))
+        (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (2505:2806:3107)(2505:2806:3107))
+        (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD_1_I0/PADDI Dout_1_I/PADDO (2540:2847:3154)(2540:2847:3154))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.vho b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.vho
index a1cd0a4..ce89e62 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.vho
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vho.vho
@@ -1,25833 +1,25833 @@
-
--- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
--- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_vho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd 
--- Netlist created on Wed Aug 16 04:50:46 2023
--- Netlist written on Wed Aug 16 04:50:55 2023
--- Design is for device LCMXO640C
--- Design is for package TQFP100
--- Design is for performance grade 3
-
--- entity vmuxregsre
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
-
-  end vmuxregsre;
-
-  architecture Structure of vmuxregsre is
-    component FL1P3DX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity vcc
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vcc is
-    port (PWR1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
-
-  end vcc;
-
-  architecture Structure of vcc is
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VHI
-      port map (Z=>PWR1);
-  end Structure;
-
--- entity gnd
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity gnd is
-    port (PWR0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
-
-  end gnd;
-
-  architecture Structure of gnd is
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-  begin
-    INST1: VLO
-      port map (Z=>PWR0);
-  end Structure;
-
--- entity ccu2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu2B is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
-
-  end ccu2B;
-
-  architecture Structure of ccu2B is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_0
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_0 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_0";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
-
-  end SLICE_0;
-
-  architecture Structure of SLICE_0 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_0: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
-                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20001
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity ccu20001 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-          CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
-
-  end ccu20001;
-
-  architecture Structure of ccu20001 is
-    component CCU2
-      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
-               INJECT1_1: String);
-      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
-            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
-            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
-            COUT1: out Std_logic);
-    end component;
-  begin
-    inst1: CCU2
-      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
-  end Structure;
-
--- entity SLICE_1
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_1 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_1";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
-
-  end SLICE_1;
-
-  architecture Structure of SLICE_1 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20001
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_17: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_16: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_16: ccu20001
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
-                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_2 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_2";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
-
-  end SLICE_2;
-
-  architecture Structure of SLICE_2 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_15: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_14: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_14: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
-                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_3
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_3 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_3";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
-
-  end SLICE_3;
-
-  architecture Structure of SLICE_3 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_13: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_12: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_12: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
-                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_4 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_4";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
-
-  end SLICE_4;
-
-  architecture Structure of SLICE_4 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_11: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_10: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_10: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
-                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_5
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_5 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_5";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
-
-  end SLICE_5;
-
-  architecture Structure of SLICE_5 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_9: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_8: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_8: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
-                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_6
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_6 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_6";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
-
-  end SLICE_6;
-
-  architecture Structure of SLICE_6 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_7: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_6: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_6: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
-                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_7
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_7 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_7";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
-
-  end SLICE_7;
-
-  architecture Structure of SLICE_7 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_5: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_4: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_4: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
-                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_8
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_8 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_8";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_A1_CLK	: VitalDelayType := 0 ns;
-      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_A0_CLK	: VitalDelayType := 0 ns;
-      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_FCI_CLK	: VitalDelayType := 0 ns;
-      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-          FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
-
-  end SLICE_8;
-
-  architecture Structure of SLICE_8 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A1_dly 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal A0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal FCI_dly 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
-            CO1: out Std_logic);
-    end component;
-  begin
-    FS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
-                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_2: ccu2B
-      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
-                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
-      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
-      FCO_out)
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_A1_CLK       	: x01 := '0';
-    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_A0_CLK       	: x01 := '0';
-    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_FCI_CLK       	: x01 := '0';
-    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => A1_dly,
-        TestSignalName => "A1",
-        TestDelay => tisd_A1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A1_CLK_noedge_posedge,
-        SetupLow => tsetup_A1_CLK_noedge_posedge,
-        HoldHigh => thold_A1_CLK_noedge_posedge,
-        HoldLow => thold_A1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A1_CLK_TimingDatash,
-        Violation => tviol_A1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => A0_dly,
-        TestSignalName => "A0",
-        TestDelay => tisd_A0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_A0_CLK_noedge_posedge,
-        SetupLow => tsetup_A0_CLK_noedge_posedge,
-        HoldHigh => thold_A0_CLK_noedge_posedge,
-        HoldLow => thold_A0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => A0_CLK_TimingDatash,
-        Violation => tviol_A0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => FCI_dly,
-        TestSignalName => "FCI",
-        TestDelay => tisd_FCI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
-        SetupLow => tsetup_FCI_CLK_noedge_posedge,
-        HoldHigh => thold_FCI_CLK_noedge_posedge,
-        HoldLow => thold_FCI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => FCI_CLK_TimingDatash,
-        Violation => tviol_FCI_CLK,
-        MsgSeverity => warning);
-
-    END IF;
-
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_dly'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_dly'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut4
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut4 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
-
-  end lut4;
-
-  architecture Structure of lut4 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40002
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40002 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
-
-  end lut40002;
-
-  architecture Structure of lut40002 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4544")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity inverter
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity inverter is
-    port (I: in Std_logic; Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
-
-  end inverter;
-
-  architecture Structure of inverter is
-    component INV
-      port (A: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    INST1: INV
-      port map (A=>I, Z=>Z);
-  end Structure;
-
--- entity SLICE_9
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_9 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_9";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
-
-  end SLICE_9;
-
-  architecture Structure of SLICE_9 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40002
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    ADSubmitted_r: lut40002
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    ADSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40003
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40003 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
-
-  end lut40003;
-
-  architecture Structure of lut40003 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40004
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40004 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
-
-  end lut40004;
-
-  architecture Structure of lut40004 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF2A")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_14
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_14 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_14";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
-
-  end SLICE_14;
-
-  architecture Structure of SLICE_14 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40003
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2: lut40003
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1Submitted_RNO: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    C1Submitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40005
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40005 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
-
-  end lut40005;
-
-  architecture Structure of lut40005 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40006
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40006 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
-
-  end lut40006;
-
-  architecture Structure of lut40006 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF5F5")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0007
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0007 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
-
-  end vmuxregsre0007;
-
-  architecture Structure of vmuxregsre0007 is
-    component FL1P3IY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3IY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_19
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_19 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_19";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
-
-  end SLICE_19;
-
-  architecture Structure of SLICE_19 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3_2: lut40005
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNO_0: lut40006
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40008
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40008 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
-
-  end lut40008;
-
-  architecture Structure of lut40008 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40009
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40009 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
-
-  end lut40009;
-
-  architecture Structure of lut40009 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEA22")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity selmux2
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity selmux2 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
-
-  end selmux2;
-
-  architecture Structure of selmux2 is
-    component MUX21
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    INST1: MUX21
-      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
-  end Structure;
-
--- entity SLICE_20
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_20 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_20";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
-
-  end SLICE_20;
-
-  architecture Structure of SLICE_20 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
-    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40009
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_20_K1: lut40008
-      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, 
-                Z=>SLICE_20_SLICE_20_K1_H1);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable_s_GATE: lut40009
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>SLICE_20_CmdEnable_s_GATE_H0);
-    CmdEnable: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    SLICE_20_K0K1MUX: selmux2
-      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40010
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40010 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
-
-  end lut40010;
-
-  architecture Structure of lut40010 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0300")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40011
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40011 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
-
-  end lut40011;
-
-  architecture Structure of lut40011 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1011")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_21
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_21 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_21";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
-
-  end SLICE_21;
-
-  architecture Structure of SLICE_21 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40010
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40011
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_a2_2: lut40010
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_RNO: lut40011
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdLEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40012
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40012 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
-
-  end lut40012;
-
-  architecture Structure of lut40012 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40013
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40013 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
-
-  end lut40013;
-
-  architecture Structure of lut40013 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_22
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_22 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_22";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
-
-  end SLICE_22;
-
-  architecture Structure of SLICE_22 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2: lut40012
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_RNO: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40014
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40014 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
-
-  end lut40014;
-
-  architecture Structure of lut40014 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x33AB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40015
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40015 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
-
-  end lut40015;
-
-  architecture Structure of lut40015 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0F05")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_26
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_26 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_26";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
-
-  end SLICE_26;
-
-  architecture Structure of SLICE_26 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40014
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_0: lut40014
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_RNO: lut40015
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Cmdn8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40016
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40016 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
-
-  end lut40016;
-
-  architecture Structure of lut40016 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCFCE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40017
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40017 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
-
-  end lut40017;
-
-  architecture Structure of lut40017 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xA9A9")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_29
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_29 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_29";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
-
-  end SLICE_29;
-
-  architecture Structure of SLICE_29 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40017
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i: lut40016
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_0: lut40017
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40018
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40018 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
-
-  end lut40018;
-
-  architecture Structure of lut40018 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5AF0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40019
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40019 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
-
-  end lut40019;
-
-  architecture Structure of lut40019 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x55AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_30
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_30 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_30";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
-
-  end SLICE_30;
-
-  architecture Structure of SLICE_30 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40018
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_2: lut40018
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_n1_0_x2: lut40019
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    IS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    IS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40020
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40020 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
-
-  end lut40020;
-
-  architecture Structure of lut40020 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40021
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40021 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
-
-  end lut40021;
-
-  architecture Structure of lut40021 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x78F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_31
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_31 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_31";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
-
-  end SLICE_31;
-
-  architecture Structure of SLICE_31 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40020
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40021
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_RNO: lut40020
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_3: lut40021
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    IS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40022
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40022 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
-
-  end lut40022;
-
-  architecture Structure of lut40022 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0B0F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_32
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_32 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_32";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
-
-  end SLICE_32;
-
-  architecture Structure of SLICE_32 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40022
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a0: lut40022
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady_RNO: lut40013
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40023
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40023 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
-
-  end lut40023;
-
-  architecture Structure of lut40023 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFAFF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40024
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40024 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
-
-  end lut40024;
-
-  architecture Structure of lut40024 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCC55")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_33
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_33 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_33";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
-
-  end SLICE_33;
-
-  architecture Structure of SLICE_33 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LED_pad_RNO: lut40023
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    LEDEN_5_i_m2: lut40024
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    LEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40025
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40025 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
-
-  end lut40025;
-
-  architecture Structure of lut40025 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3300")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40026
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40026 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
-
-  end lut40026;
-
-  architecture Structure of lut40026 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBB44")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_39
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_39 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_39";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
-
-  end SLICE_39;
-
-  architecture Structure of SLICE_39 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40025
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40026
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_0: lut40025
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RA11_2: lut40026
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    RA11: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40027
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40027 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
-
-  end lut40027;
-
-  architecture Structure of lut40027 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x75A5")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40028
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40028 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
-
-  end lut40028;
-
-  architecture Structure of lut40028 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xAAEA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_41
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_41 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_41";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
-
-  end SLICE_41;
-
-  architecture Structure of SLICE_41 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40027
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_1_0: lut40027
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40029
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40029 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
-
-  end lut40029;
-
-  architecture Structure of lut40029 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0008")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40030
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40030 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
-
-  end lut40030;
-
-  architecture Structure of lut40030 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDCD8")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_42
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_42 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_42";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
-
-  end SLICE_42;
-
-  architecture Structure of SLICE_42 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40029
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40030
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_5: lut40029
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKE_2_0: lut40030
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKE: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40031
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40031 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
-
-  end lut40031;
-
-  architecture Structure of lut40031 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x03AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40032
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40032 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
-
-  end lut40032;
-
-  architecture Structure of lut40032 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF08")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_43
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_43 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_43";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
-
-  end SLICE_43;
-
-  architecture Structure of SLICE_43 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40031
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_RNO: lut40031
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_RNO: lut40032
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40033
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40033 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
-
-  end lut40033;
-
-  architecture Structure of lut40033 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0008")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40034
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40034 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
-
-  end lut40034;
-
-  architecture Structure of lut40034 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_44
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_44 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_44";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
-
-  end SLICE_44;
-
-  architecture Structure of SLICE_44 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40033
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3: lut40033
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_fast_RNO: lut40034
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RASr: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Ready_fast: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40035
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40035 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
-
-  end lut40035;
-
-  architecture Structure of lut40035 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0500")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40036
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40036 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
-
-  end lut40036;
-
-  architecture Structure of lut40036 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFAFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_50
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_50 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_50";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
-
-  end SLICE_50;
-
-  architecture Structure of SLICE_50 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40036
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_RNO: lut40035
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0_i_o2_1: lut40036
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    S_1: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI0_dly, 
-      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40037
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40037 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
-
-  end lut40037;
-
-  architecture Structure of lut40037 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xABFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40038
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40038 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
-
-  end lut40038;
-
-  architecture Structure of lut40038 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0322")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_51
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_51 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_51";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
-
-  end SLICE_51;
-
-  architecture Structure of SLICE_51 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_RNO_0: lut40037
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_RNO: lut40038
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40039
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40039 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
-
-  end lut40039;
-
-  architecture Structure of lut40039 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2F0F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40040
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40040 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
-
-  end lut40040;
-
-  architecture Structure of lut40040 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5404")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_52
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_52 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_52";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
-
-  end SLICE_52;
-
-  architecture Structure of SLICE_52 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40039
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    PHI2r3_RNITCN41: lut40039
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_RNO: lut40040
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMSDI: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40041
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40041 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
-
-  end lut40041;
-
-  architecture Structure of lut40041 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBB88")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_55
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_55 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_55";
-
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
-
-  end SLICE_55;
-
-  architecture Structure of SLICE_55 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_4: lut40041
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
-      F0_out, Q0_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40042
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40042 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
-
-  end lut40042;
-
-  architecture Structure of lut40042 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40043
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40043 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
-
-  end lut40043;
-
-  architecture Structure of lut40043 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5A0A")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_56
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_56 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_56";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
-
-  end SLICE_56;
-
-  architecture Structure of SLICE_56 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40042
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40043
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_11: lut40042
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_o2: lut40043
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    WRD_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40044
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40044 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
-
-  end lut40044;
-
-  architecture Structure of lut40044 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40045
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40045 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
-
-  end lut40045;
-
-  architecture Structure of lut40045 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xBAFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_57
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_57 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_57";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
-
-  end SLICE_57;
-
-  architecture Structure of SLICE_57 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40044
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40045
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_0_a3_2: lut40044
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG_3_u_0_a3_3: lut40045
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    XOR8MEG: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40046
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40046 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
-
-  end lut40046;
-
-  architecture Structure of lut40046 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0005")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40047
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40047 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
-
-  end lut40047;
-
-  architecture Structure of lut40047 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x88DD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_58
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_58 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_58";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
-
-  end SLICE_58;
-
-  architecture Structure of SLICE_58 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40046
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40047
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_en_ss0_0_a2_0: lut40046
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    n8MEGEN_5_i_m2: lut40047
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-    n8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40048
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40048 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
-
-  end lut40048;
-
-  architecture Structure of lut40048 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0FDD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40049
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40049 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
-
-  end lut40049;
-
-  architecture Structure of lut40049 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0F04")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0050
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0050 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0050 : ENTITY IS TRUE;
-
-  end vmuxregsre0050;
-
-  architecture Structure of vmuxregsre0050 is
-    component FL1P3BX
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_59
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_59 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_59";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
-
-  end SLICE_59;
-
-  architecture Structure of SLICE_59 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40048
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0050
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_0: lut40048
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCAS_RNO: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCAS: vmuxregsre0050
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40051
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40051 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
-
-  end lut40051;
-
-  architecture Structure of lut40051 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFC7C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40052
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40052 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
-
-  end lut40052;
-
-  architecture Structure of lut40052 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3323")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_60
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_60 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_60";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
-
-  end SLICE_60;
-
-  architecture Structure of SLICE_60 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0050
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40051
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_RNO_0: lut40051
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCS_RNO: lut40052
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRCS: vmuxregsre0050
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40053
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40053 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
-
-  end lut40053;
-
-  architecture Structure of lut40053 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00E0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40054
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40054 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
-
-  end lut40054;
-
-  architecture Structure of lut40054 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3031")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_61
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_61 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_61";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
-
-  end SLICE_61;
-
-  architecture Structure of SLICE_61 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0050
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40054
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i_0: lut40053
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRRAS_RNO: lut40054
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRRAS: vmuxregsre0050
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40055
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40055 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
-
-  end lut40055;
-
-  architecture Structure of lut40055 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40056
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40056 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
-
-  end lut40056;
-
-  architecture Structure of lut40056 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCDEF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_62
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_62 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_62";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
-
-  end SLICE_62;
-
-  architecture Structure of SLICE_62 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0050
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40055
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0_sqmuxa_1_0_a3: lut40055
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRWE_RNO: lut40056
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRWE: vmuxregsre0050
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40057
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40057 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
-
-  end lut40057;
-
-  architecture Structure of lut40057 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0040")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40058
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40058 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
-
-  end lut40058;
-
-  architecture Structure of lut40058 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF60")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_63
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_63 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_63";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
-
-  end SLICE_63;
-
-  architecture Structure of SLICE_63 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_0_0_a3_0: lut40057
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRowColSel_0_0: lut40058
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRowColSel: vmuxregsre0007
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40059
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40059 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
-
-  end lut40059;
-
-  architecture Structure of lut40059 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40060
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40060 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
-
-  end lut40060;
-
-  architecture Structure of lut40060 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDFCE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_64
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_64 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_64";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
-
-  end SLICE_64;
-
-  architecture Structure of SLICE_64 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component vmuxregsre0050
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40059
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS15_0_a2: lut40059
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nUFMCS_s_0_N_5_i: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nUFMCS: vmuxregsre0050
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40061
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40061 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
-
-  end lut40061;
-
-  architecture Structure of lut40061 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40062
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40062 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
-
-  end lut40062;
-
-  architecture Structure of lut40062 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity nRWE_RNO_1_SLICE_65
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWE_RNO_1_SLICE_65 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          OFX0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
-
-  end nRWE_RNO_1_SLICE_65;
-
-  architecture Structure of nRWE_RNO_1_SLICE_65 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
-    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_1_SLICE_65_K1: lut40061
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
-    nRWE_RNO_1_GATE: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
-    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
-      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
-                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
-                Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     7 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     8 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40063
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40063 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
-
-  end lut40063;
-
-  architecture Structure of lut40063 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4545")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40064
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40064 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
-
-  end lut40064;
-
-  architecture Structure of lut40064 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_66
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_66 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_66";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
-
-  end SLICE_66;
-
-  architecture Structure of SLICE_66 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS_s_0_N_5_i_N_2L1: lut40063
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_a2_2_2: lut40064
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40065
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40065 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
-
-  end lut40065;
-
-  architecture Structure of lut40065 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40066
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40066 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
-
-  end lut40066;
-
-  architecture Structure of lut40066 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0067
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity vmuxregsre0067 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0067 : ENTITY IS TRUE;
-
-  end vmuxregsre0067;
-
-  architecture Structure of vmuxregsre0067 is
-    component FL1P3JY
-      generic (GSR: String);
-      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
-            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    INST01: FL1P3JY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_67
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_67 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_67";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
-
-  end SLICE_67;
-
-  architecture Structure of SLICE_67 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40065
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40066
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0067
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK_1_sqmuxa_0_a2: lut40065
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG18_0_a2: lut40066
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_5: vmuxregsre0067
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_4: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
-      Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40068
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40068 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
-
-  end lut40068;
-
-  architecture Structure of lut40068 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40069
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40069 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
-
-  end lut40069;
-
-  architecture Structure of lut40069 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFF80")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_68
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_68 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_68";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
-
-  end SLICE_68;
-
-  architecture Structure of SLICE_68 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40068
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0_1: lut40068
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_14_i_0: lut40069
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40070
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40070 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
-
-  end lut40070;
-
-  architecture Structure of lut40070 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0002")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40071
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40071 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
-
-  end lut40071;
-
-  architecture Structure of lut40071 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xECCC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_69
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_69 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_69";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
-
-  end SLICE_69;
-
-  architecture Structure of SLICE_69 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40070
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40071
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_1: lut40070
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_0: lut40071
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40072
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40072 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
-
-  end lut40072;
-
-  architecture Structure of lut40072 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40073
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40073 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
-
-  end lut40073;
-
-  architecture Structure of lut40073 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xC0C0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_70
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_70 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_70";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
-
-  end SLICE_70;
-
-  architecture Structure of SLICE_70 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40073
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0: lut40072
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2: lut40073
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40074
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40074 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
-
-  end lut40074;
-
-  architecture Structure of lut40074 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40075
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40075 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
-
-  end lut40075;
-
-  architecture Structure of lut40075 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_71
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_71 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_71";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
-
-  end SLICE_71;
-
-  architecture Structure of SLICE_71 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40074
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40075
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_4: lut40074
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1WR_0_a2_0_10: lut40075
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Bank_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40076
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40076 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
-
-  end lut40076;
-
-  architecture Structure of lut40076 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40077
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40077 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
-
-  end lut40077;
-
-  architecture Structure of lut40077 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF808")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_72
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_72 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_72";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
-
-  end SLICE_72;
-
-  architecture Structure of SLICE_72 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40076
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0: lut40076
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_m2: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_3: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_2: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40078
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40078 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
-
-  end lut40078;
-
-  architecture Structure of lut40078 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFDF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_73
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_73 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_73";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
-
-  end SLICE_73;
-
-  architecture Structure of SLICE_73 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40078
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0: lut40078
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_0_sqmuxa_0_o2: lut40034
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdUFMCS: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CmdUFMCLK: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40079
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40079 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
-
-  end lut40079;
-
-  architecture Structure of lut40079 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCC00")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40080
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40080 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
-
-  end lut40080;
-
-  architecture Structure of lut40080 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_74
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_74 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_74";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
-
-  end SLICE_74;
-
-  architecture Structure of SLICE_74 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40079
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40080
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    InitReady3_0_a2_3: lut40079
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady3_0_a2: lut40080
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdUFMSDI: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40081
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40081 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
-
-  end lut40081;
-
-  architecture Structure of lut40081 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xEFEF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40082
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40082 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
-
-  end lut40082;
-
-  architecture Structure of lut40082 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0005")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_75
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_75 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_75";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
-
-  end SLICE_75;
-
-  architecture Structure of SLICE_75 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40081
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40082
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_o2_0: lut40081
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_4_u_i_a2_0: lut40082
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CASr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40083
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40083 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
-
-  end lut40083;
-
-  architecture Structure of lut40083 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00CC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40084
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40084 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
-
-  end lut40084;
-
-  architecture Structure of lut40084 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_76
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_76 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_76";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
-
-  end SLICE_76;
-
-  architecture Structure of SLICE_76 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40083
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40084
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_4: lut40083
-      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_4_0: lut40084
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_5: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_4: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40085
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40085 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
-
-  end lut40085;
-
-  architecture Structure of lut40085 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5050")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40086
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40086 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
-
-  end lut40086;
-
-  architecture Structure of lut40086 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_77
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_77 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_77";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
-
-  end SLICE_77;
-
-  architecture Structure of SLICE_77 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40085
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40086
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_0_a2_1: lut40085
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_0_a2_5: lut40086
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_7: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_6: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40087
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40087 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
-
-  end lut40087;
-
-  architecture Structure of lut40087 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3F3F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40088
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40088 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
-
-  end lut40088;
-
-  architecture Structure of lut40088 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_78
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_78 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_78";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
-
-  end SLICE_78;
-
-  architecture Structure of SLICE_78 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40087
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40088
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_o2: lut40087
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable17_0_a2_4: lut40088
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CBR_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    CBR: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40089
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40089 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
-
-  end lut40089;
-
-  architecture Structure of lut40089 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00C0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40090
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40090 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
-
-  end lut40090;
-
-  architecture Structure of lut40090 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_79
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_79 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_79";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
-
-  end SLICE_79;
-
-  architecture Structure of SLICE_79 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40089
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40090
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_RNO_2: lut40089
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_RNO_0: lut40090
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40091
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40091 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
-
-  end lut40091;
-
-  architecture Structure of lut40091 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x3030")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40092
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40092 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
-
-  end lut40092;
-
-  architecture Structure of lut40092 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0805")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_80
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_80 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_80";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
-
-  end SLICE_80;
-
-  architecture Structure of SLICE_80 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vmuxregsre0067
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40091
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40092
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_RNO_1: lut40091
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRCAS_RNO_0: lut40092
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_9: vmuxregsre0067
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_8: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40093
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40093 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
-
-  end lut40093;
-
-  architecture Structure of lut40093 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40094
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40094 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
-
-  end lut40094;
-
-  architecture Structure of lut40094 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_81
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_81 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_81";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
-
-  end SLICE_81;
-
-  architecture Structure of SLICE_81 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal M1_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40093
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40094
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0_3: lut40093
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_5: lut40094
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    FWEr_fast: vmuxregsre
-      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    M1_INVERTERIN: inverter
-      port map (I=>M1_dly, Z=>M1_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    FWEr: vmuxregsre
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40095
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40095 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
-
-  end lut40095;
-
-  architecture Structure of lut40095 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0E0C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40096
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40096 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
-
-  end lut40096;
-
-  architecture Structure of lut40096 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x1030")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_82
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_82 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_82";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
-
-  end SLICE_82;
-
-  architecture Structure of SLICE_82 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40095
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40096
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2: lut40095
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_1_sqmuxa_0_a2: lut40096
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr3: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40097
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40097 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
-
-  end lut40097;
-
-  architecture Structure of lut40097 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFEFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40098
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40098 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
-
-  end lut40098;
-
-  architecture Structure of lut40098 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5FFF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_83
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_83 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_83";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
-
-  end SLICE_83;
-
-  architecture Structure of SLICE_83 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40097
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40098
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_o2: lut40097
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_0_sqmuxa_0_o2: lut40098
-      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RBA_1: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RBA_0: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
-      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40099
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40099 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
-
-  end lut40099;
-
-  architecture Structure of lut40099 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0008")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40100
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40100 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
-
-  end lut40100;
-
-  architecture Structure of lut40100 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0004")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_84
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_84 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_84";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
-
-  end SLICE_84;
-
-  architecture Structure of SLICE_84 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40099
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40100
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a2_4_2: lut40099
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_a2_6: lut40100
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40101
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40101 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
-
-  end lut40101;
-
-  architecture Structure of lut40101 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40102
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40102 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
-
-  end lut40102;
-
-  architecture Structure of lut40102 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_85
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_85 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_85";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
-
-  end SLICE_85;
-
-  architecture Structure of SLICE_85 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40101
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40102
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17_0_a2_3: lut40101
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_Din_4: lut40102
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    WRD_3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    WRD_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40103
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40103 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
-
-  end lut40103;
-
-  architecture Structure of lut40103 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x5F5F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40104
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40104 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
-
-  end lut40104;
-
-  architecture Structure of lut40104 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xE4E4")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_86
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_86 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_86";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
-
-  end SLICE_86;
-
-  architecture Structure of SLICE_86 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40103
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40104
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQML: lut40103
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_9: lut40104
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40105
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40105 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE;
-
-  end lut40105;
-
-  architecture Structure of lut40105 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x00FC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40106
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40106 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
-
-  end lut40106;
-
-  architecture Structure of lut40106 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_87
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_87 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_87";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
-
-  end SLICE_87;
-
-  architecture Structure of SLICE_87 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40105
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40106
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_RNO_0: lut40105
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_a2_8: lut40106
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40107
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40107 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
-
-  end lut40107;
-
-  architecture Structure of lut40107 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x0808")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40108
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40108 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
-
-  end lut40108;
-
-  architecture Structure of lut40108 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xFFF0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_88
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_88 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_88";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; M1: in Std_logic; 
-          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
-
-  end SLICE_88;
-
-  architecture Structure of SLICE_88 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0007
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40107
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40108
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_0_a2_0_3: lut40107
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nCCAS_pad_RNI01SJ: lut40108
-      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RowA_7: vmuxregsre0007
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-    RowA_6: vmuxregsre0007
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, M1_dly, 
-      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_negedge,
-        SetupLow => tsetup_M1_CLK_noedge_negedge,
-        HoldHigh => thold_M1_CLK_noedge_negedge,
-        HoldLow => thold_M1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
-        SetupLow => tsetup_LSR_CLK_noedge_negedge,
-        HoldHigh => thold_LSR_CLK_noedge_negedge,
-        HoldLow => thold_LSR_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40109
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40109 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
-
-  end lut40109;
-
-  architecture Structure of lut40109 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF0FF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40110
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40110 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE;
-
-  end lut40110;
-
-  architecture Structure of lut40110 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF0CC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_89
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_89 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_89";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
-
-  end SLICE_89;
-
-  architecture Structure of SLICE_89 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40109
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40110
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQMH: lut40109
-      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_8: lut40110
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40111
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40111 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE;
-
-  end lut40111;
-
-  architecture Structure of lut40111 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xE0E0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40112
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40112 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE;
-
-  end lut40112;
-
-  architecture Structure of lut40112 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xDD88")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_90
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_90 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_90";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
-
-  end SLICE_90;
-
-  architecture Structure of SLICE_90 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40111
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40112
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_CMDWR: lut40111
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_0: lut40112
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40113
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40113 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE;
-
-  end lut40113;
-
-  architecture Structure of lut40113 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCCF0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40114
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40114 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE;
-
-  end lut40114;
-
-  architecture Structure of lut40114 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xCFC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_91
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_91 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_91";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
-
-  end SLICE_91;
-
-  architecture Structure of SLICE_91 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40113
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40114
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_7: lut40113
-      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_1: lut40114
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40115
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40115 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE;
-
-  end lut40115;
-
-  architecture Structure of lut40115 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF0AA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_92
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_92 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_92";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
-
-  end SLICE_92;
-
-  architecture Structure of SLICE_92 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40113
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40115
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_6: lut40115
-      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_2: lut40113
-      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_93
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_93 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_93";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
-
-  end SLICE_93;
-
-  architecture Structure of SLICE_93 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_5: lut40041
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_3: lut40041
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40116
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40116 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE;
-
-  end lut40116;
-
-  architecture Structure of lut40116 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0x000F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40117
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity lut40117 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40117 : ENTITY IS TRUE;
-
-  end lut40117;
-
-  architecture Structure of lut40117 is
-    component ROM16X1
-      generic (initval: String);
-      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
-            AD3: in Std_logic; DO0: out Std_logic);
-    end component;
-  begin
-    INST10: ROM16X1
-      generic map (initval => "0xF000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_94
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity SLICE_94 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_94";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
-
-  end SLICE_94;
-
-  architecture Structure of SLICE_94 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal M0_NOTIN: Std_logic;
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component vmuxregsre0067
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40116
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40117
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40116
-      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKEEN_8_u_0_a2_1_s: lut40117
-      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RA10: vmuxregsre0067
-      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    M0_INVERTERIN: inverter
-      port map (I=>M0_dly, Z=>M0_NOTIN);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, M0_dly, LSR_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf is
-    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-          PAD: out Std_logic; PADI: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
-
-  end mjiobuf;
-
-  architecture Structure of mjiobuf is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-    component OBW
-      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PADI, O=>Z);
-    INST2: OBW
-      port map (I=>I, T=>T, O=>PAD);
-  end Structure;
-
--- entity RD_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD0 	: VitalDelayType := 0 ns;
-      tpw_RD0_posedge	: VitalDelayType := 0 ns;
-      tpw_RD0_negedge	: VitalDelayType := 0 ns;
-      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD0: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
-
-  end RD_0_B;
-
-  architecture Structure of RD_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD0_ipd 	: std_logic := 'X';
-    signal RD0_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_0: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
-                PADI=>RD0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD0_zd         	: std_logic := 'X';
-    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD0_RD0          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD0_ipd,
-        TestSignalName => "RD0",
-        Period => tperiod_RD0,
-        PulseWidthHigh => tpw_RD0_posedge,
-        PulseWidthLow => tpw_RD0_negedge,
-        PeriodData => periodcheckinfo_RD0,
-        Violation => tviol_RD0_RD0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD0_zd 	:= RD0_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
-                           PathDelay => tpd_RD0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD0,
-                           PathCondition => TRUE)),
-      GlitchData => RD0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0118
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0118 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0118 : ENTITY IS TRUE;
-
-  end mjiobuf0118;
-
-  architecture Structure of mjiobuf0118 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity Dout_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
-
-  end Dout_0_B;
-
-  architecture Structure of Dout_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout0_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_0: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
-    VARIABLE Dout0_zd         	: std_logic := 'X';
-    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout0_zd 	:= Dout0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout0,
-                           PathCondition => TRUE)),
-      GlitchData => Dout0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0119
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0119 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0119 : ENTITY IS TRUE;
-
-  end mjiobuf0119;
-
-  architecture Structure of mjiobuf0119 is
-    component IBPD
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPD
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity PHI2B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity PHI2B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2B";
-
-      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_PHI2S 	: VitalDelayType := 0 ns;
-      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
-      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; PHI2S: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
-
-  end PHI2B;
-
-  architecture Structure of PHI2B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PHI2S_ipd 	: std_logic := 'X';
-
-    component mjiobuf0119
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    PHI2_pad: mjiobuf0119
-      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
-    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => PHI2S_ipd,
-        TestSignalName => "PHI2S",
-        Period => tperiod_PHI2S,
-        PulseWidthHigh => tpw_PHI2S_posedge,
-        PulseWidthLow => tpw_PHI2S_negedge,
-        PeriodData => periodcheckinfo_PHI2S,
-        Violation => tviol_PHI2S_PHI2S,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
-                           PathDelay => tpd_PHI2S_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0120
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0120 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0120 : ENTITY IS TRUE;
-
-  end mjiobuf0120;
-
-  architecture Structure of mjiobuf0120 is
-    component IB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IB
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity UFMSDOB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDOB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDOB";
-
-      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
-
-  end UFMSDOB;
-
-  architecture Structure of UFMSDOB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal UFMSDOS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    UFMSDO_pad: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
-    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => UFMSDOS_ipd,
-        TestSignalName => "UFMSDOS",
-        Period => tperiod_UFMSDOS,
-        PulseWidthHigh => tpw_UFMSDOS_posedge,
-        PulseWidthLow => tpw_UFMSDOS_negedge,
-        PeriodData => periodcheckinfo_UFMSDOS,
-        Violation => tviol_UFMSDOS_UFMSDOS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
-                           PathDelay => tpd_UFMSDOS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0121
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0121 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0121 : ENTITY IS TRUE;
-
-  end mjiobuf0121;
-
-  architecture Structure of mjiobuf0121 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity UFMSDIB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMSDIB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDIB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
-
-  end UFMSDIB;
-
-  architecture Structure of UFMSDIB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMSDIS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMSDI_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
-    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
-    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMSDIS_zd 	:= UFMSDIS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMSDIS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMSDIS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity UFMCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLKB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
-
-  end UFMCLKB;
-
-  architecture Structure of UFMCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal UFMCLKS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMCLK_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
-    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
-    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMCLKS_zd 	:= UFMCLKS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_UFMCLKS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMCLKS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nUFMCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nUFMCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-
-        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
-
-  end nUFMCSB;
-
-  architecture Structure of nUFMCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nUFMCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nUFMCS_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
-    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
-    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nUFMCSS_zd 	:= nUFMCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nUFMCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nUFMCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMLB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMLB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMLB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
-
-  end RDQMLB;
-
-  architecture Structure of RDQMLB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMLS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQML_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
-    VARIABLE RDQMLS_zd         	: std_logic := 'X';
-    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMLS_zd 	:= RDQMLS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMLS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMLS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMHB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RDQMHB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMHB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
-
-  end RDQMHB;
-
-  architecture Structure of RDQMHB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMHS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQMH_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
-    VARIABLE RDQMHS_zd         	: std_logic := 'X';
-    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMHS_zd 	:= RDQMHS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMHS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMHS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
-
-  end nRCASB;
-
-  architecture Structure of nRCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCASS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCAS_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
-    VARIABLE nRCASS_zd         	: std_logic := 'X';
-    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCASS_zd 	:= nRCASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRASB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRRASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
-
-  end nRRASB;
-
-  architecture Structure of nRRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRRASS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRRAS_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
-    VARIABLE nRRASS_zd         	: std_logic := 'X';
-    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRRASS_zd 	:= nRRASS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRRASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRRASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRWES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
-
-  end nRWEB;
-
-  architecture Structure of nRWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRWES_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRWE_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>nRWES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
-    VARIABLE nRWES_zd         	: std_logic := 'X';
-    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRWES_zd 	:= nRWES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRWES,
-                           PathCondition => TRUE)),
-      GlitchData => nRWES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCKEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKEB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RCKES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
-
-  end RCKEB;
-
-  architecture Structure of RCKEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RCKES_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RCKE_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RCKES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
-    VARIABLE RCKES_zd         	: std_logic := 'X';
-    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RCKES_zd 	:= RCKES_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RCKES,
-                           PathCondition => TRUE)),
-      GlitchData => RCKES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCLKB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCLKB";
-
-      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RCLKS 	: VitalDelayType := 0 ns;
-      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
-      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; RCLKS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
-
-  end RCLKB;
-
-  architecture Structure of RCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal RCLKS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    RCLK_pad: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
-    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RCLKS_ipd,
-        TestSignalName => "RCLKS",
-        Period => tperiod_RCLKS,
-        PulseWidthHigh => tpw_RCLKS_posedge,
-        PulseWidthLow => tpw_RCLKS_negedge,
-        PeriodData => periodcheckinfo_RCLKS,
-        Violation => tviol_RCLKS_RCLKS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
-                           PathDelay => tpd_RCLKS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCSB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nRCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCSB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; nRCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
-
-  end nRCSB;
-
-  architecture Structure of nRCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal nRCSS_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCS_pad: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
-    VARIABLE nRCSS_zd         	: std_logic := 'X';
-    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCSS_zd 	:= nRCSS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_nRCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD7 	: VitalDelayType := 0 ns;
-      tpw_RD7_posedge	: VitalDelayType := 0 ns;
-      tpw_RD7_negedge	: VitalDelayType := 0 ns;
-      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD7: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
-
-  end RD_7_B;
-
-  architecture Structure of RD_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD7_ipd 	: std_logic := 'X';
-    signal RD7_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_7: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
-                PADI=>RD7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD7_zd         	: std_logic := 'X';
-    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD7_RD7          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD7_ipd,
-        TestSignalName => "RD7",
-        Period => tperiod_RD7,
-        PulseWidthHigh => tpw_RD7_posedge,
-        PulseWidthLow => tpw_RD7_negedge,
-        PeriodData => periodcheckinfo_RD7,
-        Violation => tviol_RD7_RD7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD7_zd 	:= RD7_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
-                           PathDelay => tpd_RD7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD7,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD7,
-                           PathCondition => TRUE)),
-      GlitchData => RD7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD6 	: VitalDelayType := 0 ns;
-      tpw_RD6_posedge	: VitalDelayType := 0 ns;
-      tpw_RD6_negedge	: VitalDelayType := 0 ns;
-      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD6: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
-
-  end RD_6_B;
-
-  architecture Structure of RD_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD6_ipd 	: std_logic := 'X';
-    signal RD6_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_6: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
-                PADI=>RD6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD6_zd         	: std_logic := 'X';
-    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD6_RD6          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD6_ipd,
-        TestSignalName => "RD6",
-        Period => tperiod_RD6,
-        PulseWidthHigh => tpw_RD6_posedge,
-        PulseWidthLow => tpw_RD6_negedge,
-        PeriodData => periodcheckinfo_RD6,
-        Violation => tviol_RD6_RD6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD6_zd 	:= RD6_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
-                           PathDelay => tpd_RD6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD6,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD6,
-                           PathCondition => TRUE)),
-      GlitchData => RD6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD5 	: VitalDelayType := 0 ns;
-      tpw_RD5_posedge	: VitalDelayType := 0 ns;
-      tpw_RD5_negedge	: VitalDelayType := 0 ns;
-      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD5: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
-
-  end RD_5_B;
-
-  architecture Structure of RD_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD5_ipd 	: std_logic := 'X';
-    signal RD5_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_5: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
-                PADI=>RD5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD5_zd         	: std_logic := 'X';
-    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD5_RD5          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD5_ipd,
-        TestSignalName => "RD5",
-        Period => tperiod_RD5,
-        PulseWidthHigh => tpw_RD5_posedge,
-        PulseWidthLow => tpw_RD5_negedge,
-        PeriodData => periodcheckinfo_RD5,
-        Violation => tviol_RD5_RD5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD5_zd 	:= RD5_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
-                           PathDelay => tpd_RD5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD5,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD5,
-                           PathCondition => TRUE)),
-      GlitchData => RD5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD4 	: VitalDelayType := 0 ns;
-      tpw_RD4_posedge	: VitalDelayType := 0 ns;
-      tpw_RD4_negedge	: VitalDelayType := 0 ns;
-      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD4: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
-
-  end RD_4_B;
-
-  architecture Structure of RD_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD4_ipd 	: std_logic := 'X';
-    signal RD4_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_4: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
-                PADI=>RD4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD4_zd         	: std_logic := 'X';
-    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD4_RD4          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD4_ipd,
-        TestSignalName => "RD4",
-        Period => tperiod_RD4,
-        PulseWidthHigh => tpw_RD4_posedge,
-        PulseWidthLow => tpw_RD4_negedge,
-        PeriodData => periodcheckinfo_RD4,
-        Violation => tviol_RD4_RD4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD4_zd 	:= RD4_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
-                           PathDelay => tpd_RD4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD4,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD4,
-                           PathCondition => TRUE)),
-      GlitchData => RD4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD3 	: VitalDelayType := 0 ns;
-      tpw_RD3_posedge	: VitalDelayType := 0 ns;
-      tpw_RD3_negedge	: VitalDelayType := 0 ns;
-      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD3: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
-
-  end RD_3_B;
-
-  architecture Structure of RD_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD3_ipd 	: std_logic := 'X';
-    signal RD3_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_3: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
-                PADI=>RD3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD3_zd         	: std_logic := 'X';
-    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD3_RD3          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD3_ipd,
-        TestSignalName => "RD3",
-        Period => tperiod_RD3,
-        PulseWidthHigh => tpw_RD3_posedge,
-        PulseWidthLow => tpw_RD3_negedge,
-        PeriodData => periodcheckinfo_RD3,
-        Violation => tviol_RD3_RD3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD3_zd 	:= RD3_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
-                           PathDelay => tpd_RD3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD3,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD3,
-                           PathCondition => TRUE)),
-      GlitchData => RD3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD2 	: VitalDelayType := 0 ns;
-      tpw_RD2_posedge	: VitalDelayType := 0 ns;
-      tpw_RD2_negedge	: VitalDelayType := 0 ns;
-      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD2: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
-
-  end RD_2_B;
-
-  architecture Structure of RD_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD2_ipd 	: std_logic := 'X';
-    signal RD2_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_2: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
-                PADI=>RD2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD2_zd         	: std_logic := 'X';
-    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD2_RD2          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD2_ipd,
-        TestSignalName => "RD2",
-        Period => tperiod_RD2,
-        PulseWidthHigh => tpw_RD2_posedge,
-        PulseWidthLow => tpw_RD2_negedge,
-        PeriodData => periodcheckinfo_RD2,
-        Violation => tviol_RD2_RD2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD2_zd 	:= RD2_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
-                           PathDelay => tpd_RD2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD2,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD2,
-                           PathCondition => TRUE)),
-      GlitchData => RD2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RD_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_B";
-
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RD1 	: VitalDelayType := 0 ns;
-      tpw_RD1_posedge	: VitalDelayType := 0 ns;
-      tpw_RD1_negedge	: VitalDelayType := 0 ns;
-      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-          RD1: inout Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
-
-  end RD_1_B;
-
-  architecture Structure of RD_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RD1_ipd 	: std_logic := 'X';
-    signal RD1_out 	: std_logic := 'Z';
-
-    component mjiobuf
-      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
-            PAD: out Std_logic; PADI: in Std_logic);
-    end component;
-  begin
-    RD_pad_1: mjiobuf
-      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
-                PADI=>RD1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-    VARIABLE RD1_zd         	: std_logic := 'X';
-    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RD1_RD1          	: x01 := '0';
-    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RD1_ipd,
-        TestSignalName => "RD1",
-        Period => tperiod_RD1,
-        PulseWidthHigh => tpw_RD1_posedge,
-        PulseWidthLow => tpw_RD1_negedge,
-        PeriodData => periodcheckinfo_RD1,
-        Violation => tviol_RD1_RD1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-    RD1_zd 	:= RD1_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
-                           PathDelay => tpd_RD1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01Z (
-      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
-      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RD1,
-                           PathCondition => TRUE)),
-      GlitchData => RD1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_11_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA11: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
-
-  end RA_11_B;
-
-  architecture Structure of RA_11_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA11_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_11: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA11_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
-    VARIABLE RA11_zd         	: std_logic := 'X';
-    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA11_zd 	:= RA11_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA11,
-                           PathCondition => TRUE)),
-      GlitchData => RA11_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_10_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_10_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RA10: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
-
-  end RA_10_B;
-
-  architecture Structure of RA_10_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA10_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_10: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA10_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
-    VARIABLE RA10_zd         	: std_logic := 'X';
-    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA10_zd 	:= RA10_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA10,
-                           PathCondition => TRUE)),
-      GlitchData => RA10_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_9_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA9: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
-
-  end RA_9_B;
-
-  architecture Structure of RA_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA9_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_9: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA9_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
-    VARIABLE RA9_zd         	: std_logic := 'X';
-    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA9_zd 	:= RA9_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA9,
-                           PathCondition => TRUE)),
-      GlitchData => RA9_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_8_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA8: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
-
-  end RA_8_B;
-
-  architecture Structure of RA_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA8_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_8: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA8_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
-    VARIABLE RA8_zd         	: std_logic := 'X';
-    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA8_zd 	:= RA8_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA8,
-                           PathCondition => TRUE)),
-      GlitchData => RA8_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
-
-  end RA_7_B;
-
-  architecture Structure of RA_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA7_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_7: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
-    VARIABLE RA7_zd         	: std_logic := 'X';
-    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA7_zd 	:= RA7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA7,
-                           PathCondition => TRUE)),
-      GlitchData => RA7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
-
-  end RA_6_B;
-
-  architecture Structure of RA_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA6_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_6: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
-    VARIABLE RA6_zd         	: std_logic := 'X';
-    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA6_zd 	:= RA6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA6,
-                           PathCondition => TRUE)),
-      GlitchData => RA6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
-
-  end RA_5_B;
-
-  architecture Structure of RA_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA5_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_5: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
-    VARIABLE RA5_zd         	: std_logic := 'X';
-    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA5_zd 	:= RA5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA5,
-                           PathCondition => TRUE)),
-      GlitchData => RA5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
-
-  end RA_4_B;
-
-  architecture Structure of RA_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA4_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_4: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
-    VARIABLE RA4_zd         	: std_logic := 'X';
-    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA4_zd 	:= RA4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA4,
-                           PathCondition => TRUE)),
-      GlitchData => RA4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
-
-  end RA_3_B;
-
-  architecture Structure of RA_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA3_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_3: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
-    VARIABLE RA3_zd         	: std_logic := 'X';
-    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA3_zd 	:= RA3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA3,
-                           PathCondition => TRUE)),
-      GlitchData => RA3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
-
-  end RA_2_B;
-
-  architecture Structure of RA_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA2_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_2: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
-    VARIABLE RA2_zd         	: std_logic := 'X';
-    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA2_zd 	:= RA2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA2,
-                           PathCondition => TRUE)),
-      GlitchData => RA2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
-
-  end RA_1_B;
-
-  architecture Structure of RA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA1_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_1: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
-    VARIABLE RA1_zd         	: std_logic := 'X';
-    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA1_zd 	:= RA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA1,
-                           PathCondition => TRUE)),
-      GlitchData => RA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
-
-  end RA_0_B;
-
-  architecture Structure of RA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA0_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_0: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
-    VARIABLE RA0_zd         	: std_logic := 'X';
-    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA0_zd 	:= RA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA0,
-                           PathCondition => TRUE)),
-      GlitchData => RA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
-
-  end RBA_1_B;
-
-  architecture Structure of RBA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA1_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_1: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RBA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
-    VARIABLE RBA1_zd         	: std_logic := 'X';
-    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA1_zd 	:= RBA1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA1,
-                           PathCondition => TRUE)),
-      GlitchData => RBA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RBA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; RBA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
-
-  end RBA_0_B;
-
-  architecture Structure of RBA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RBA0_out 	: std_logic := 'X';
-
-    component mjiobuf0121
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_0: mjiobuf0121
-      port map (I=>PADDO_ipd, PAD=>RBA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
-    VARIABLE RBA0_zd         	: std_logic := 'X';
-    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA0_zd 	:= RBA0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RBA0,
-                           PathCondition => TRUE)),
-      GlitchData => RBA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0122
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0122 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0122 : ENTITY IS TRUE;
-
-  end mjiobuf0122;
-
-  architecture Structure of mjiobuf0122 is
-    component OB
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity LEDB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity LEDB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "LEDB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; LEDS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
-
-  end LEDB;
-
-  architecture Structure of LEDB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal LEDS_out 	: std_logic := 'X';
-
-    component mjiobuf0122
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    LED_pad: mjiobuf0122
-      port map (I=>PADDO_ipd, PAD=>LEDS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
-    VARIABLE LEDS_zd         	: std_logic := 'X';
-    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    LEDS_zd 	:= LEDS_out;
-
-    VitalPathDelay01Z (
-      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_LEDS,
-                           PathCondition => TRUE)),
-      GlitchData => LEDS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nFWEB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nFWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nFWEB";
-
-      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nFWES 	: VitalDelayType := 0 ns;
-      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
-      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nFWES: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
-
-  end nFWEB;
-
-  architecture Structure of nFWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nFWES_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nFWE_pad: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
-    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nFWES_ipd,
-        TestSignalName => "nFWES",
-        Period => tperiod_nFWES,
-        PulseWidthHigh => tpw_nFWES_posedge,
-        PulseWidthLow => tpw_nFWES_negedge,
-        PeriodData => periodcheckinfo_nFWES,
-        Violation => tviol_nFWES_nFWES,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
-                           PathDelay => tpd_nFWES_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mjiobuf0123
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity mjiobuf0123 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mjiobuf0123 : ENTITY IS TRUE;
-
-  end mjiobuf0123;
-
-  architecture Structure of mjiobuf0123 is
-    component IBPU
-      port (I: in Std_logic; O: out Std_logic);
-    end component;
-  begin
-    INST1: IBPU
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity nCRASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCRASB";
-
-      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCRASS 	: VitalDelayType := 0 ns;
-      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCRASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
-
-  end nCRASB;
-
-  architecture Structure of nCRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCRASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0123
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCRAS_pad: mjiobuf0123
-      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCRASS_ipd,
-        TestSignalName => "nCRASS",
-        Period => tperiod_nCRASS,
-        PulseWidthHigh => tpw_nCRASS_posedge,
-        PulseWidthLow => tpw_nCRASS_negedge,
-        PeriodData => periodcheckinfo_nCRASS,
-        Violation => tviol_nCRASS_nCRASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
-                           PathDelay => tpd_nCRASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCCASB
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity nCCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCCASB";
-
-      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCCASS 	: VitalDelayType := 0 ns;
-      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCCASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
-
-  end nCCASB;
-
-  architecture Structure of nCCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCCASS_ipd 	: std_logic := 'X';
-
-    component mjiobuf0123
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCCAS_pad: mjiobuf0123
-      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCCASS_ipd,
-        TestSignalName => "nCCASS",
-        Period => tperiod_nCCASS,
-        PulseWidthHigh => tpw_nCCASS_posedge,
-        PulseWidthLow => tpw_nCCASS_negedge,
-        PeriodData => periodcheckinfo_nCCASS,
-        Violation => tviol_nCCASS_nCCASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
-                           PathDelay => tpd_nCCASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
-
-  end Dout_7_B;
-
-  architecture Structure of Dout_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout7_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_7: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
-    VARIABLE Dout7_zd         	: std_logic := 'X';
-    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout7_zd 	:= Dout7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout7,
-                           PathCondition => TRUE)),
-      GlitchData => Dout7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
-
-  end Dout_6_B;
-
-  architecture Structure of Dout_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout6_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_6: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
-    VARIABLE Dout6_zd         	: std_logic := 'X';
-    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout6_zd 	:= Dout6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout6,
-                           PathCondition => TRUE)),
-      GlitchData => Dout6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
-
-  end Dout_5_B;
-
-  architecture Structure of Dout_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout5_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_5: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
-    VARIABLE Dout5_zd         	: std_logic := 'X';
-    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout5_zd 	:= Dout5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout5,
-                           PathCondition => TRUE)),
-      GlitchData => Dout5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
-
-  end Dout_4_B;
-
-  architecture Structure of Dout_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout4_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_4: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
-    VARIABLE Dout4_zd         	: std_logic := 'X';
-    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout4_zd 	:= Dout4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout4,
-                           PathCondition => TRUE)),
-      GlitchData => Dout4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
-
-  end Dout_3_B;
-
-  architecture Structure of Dout_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout3_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_3: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
-    VARIABLE Dout3_zd         	: std_logic := 'X';
-    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout3_zd 	:= Dout3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout3,
-                           PathCondition => TRUE)),
-      GlitchData => Dout3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
-
-  end Dout_2_B;
-
-  architecture Structure of Dout_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout2_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_2: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
-    VARIABLE Dout2_zd         	: std_logic := 'X';
-    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout2_zd 	:= Dout2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout2,
-                           PathCondition => TRUE)),
-      GlitchData => Dout2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Dout_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
-        );
-
-    port (PADDO: in Std_logic; Dout1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
-
-  end Dout_1_B;
-
-  architecture Structure of Dout_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout1_out 	: std_logic := 'X';
-
-    component mjiobuf0118
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_1: mjiobuf0118
-      port map (I=>PADDO_ipd, PAD=>Dout1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
-    VARIABLE Dout1_zd         	: std_logic := 'X';
-    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout1_zd 	:= Dout1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout1,
-                           PathCondition => TRUE)),
-      GlitchData => Dout1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_B";
-
-      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din7 	: VitalDelayType := 0 ns;
-      tpw_Din7_posedge	: VitalDelayType := 0 ns;
-      tpw_Din7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
-
-  end Din_7_B;
-
-  architecture Structure of Din_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_7: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din7_Din7          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din7_ipd,
-        TestSignalName => "Din7",
-        Period => tperiod_Din7,
-        PulseWidthHigh => tpw_Din7_posedge,
-        PulseWidthLow => tpw_Din7_negedge,
-        PeriodData => periodcheckinfo_Din7,
-        Violation => tviol_Din7_Din7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
-                           PathDelay => tpd_Din7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_B";
-
-      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din6 	: VitalDelayType := 0 ns;
-      tpw_Din6_posedge	: VitalDelayType := 0 ns;
-      tpw_Din6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
-
-  end Din_6_B;
-
-  architecture Structure of Din_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_6: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din6_Din6          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din6_ipd,
-        TestSignalName => "Din6",
-        Period => tperiod_Din6,
-        PulseWidthHigh => tpw_Din6_posedge,
-        PulseWidthLow => tpw_Din6_negedge,
-        PeriodData => periodcheckinfo_Din6,
-        Violation => tviol_Din6_Din6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
-                           PathDelay => tpd_Din6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_B";
-
-      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din5 	: VitalDelayType := 0 ns;
-      tpw_Din5_posedge	: VitalDelayType := 0 ns;
-      tpw_Din5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
-
-  end Din_5_B;
-
-  architecture Structure of Din_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_5: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din5_Din5          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din5_ipd,
-        TestSignalName => "Din5",
-        Period => tperiod_Din5,
-        PulseWidthHigh => tpw_Din5_posedge,
-        PulseWidthLow => tpw_Din5_negedge,
-        PeriodData => periodcheckinfo_Din5,
-        Violation => tviol_Din5_Din5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
-                           PathDelay => tpd_Din5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_B";
-
-      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din4 	: VitalDelayType := 0 ns;
-      tpw_Din4_posedge	: VitalDelayType := 0 ns;
-      tpw_Din4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
-
-  end Din_4_B;
-
-  architecture Structure of Din_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_4: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din4_Din4          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din4_ipd,
-        TestSignalName => "Din4",
-        Period => tperiod_Din4,
-        PulseWidthHigh => tpw_Din4_posedge,
-        PulseWidthLow => tpw_Din4_negedge,
-        PeriodData => periodcheckinfo_Din4,
-        Violation => tviol_Din4_Din4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
-                           PathDelay => tpd_Din4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_B";
-
-      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din3 	: VitalDelayType := 0 ns;
-      tpw_Din3_posedge	: VitalDelayType := 0 ns;
-      tpw_Din3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
-
-  end Din_3_B;
-
-  architecture Structure of Din_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_3: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din3_Din3          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din3_ipd,
-        TestSignalName => "Din3",
-        Period => tperiod_Din3,
-        PulseWidthHigh => tpw_Din3_posedge,
-        PulseWidthLow => tpw_Din3_negedge,
-        PeriodData => periodcheckinfo_Din3,
-        Violation => tviol_Din3_Din3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
-                           PathDelay => tpd_Din3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_B";
-
-      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din2 	: VitalDelayType := 0 ns;
-      tpw_Din2_posedge	: VitalDelayType := 0 ns;
-      tpw_Din2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
-
-  end Din_2_B;
-
-  architecture Structure of Din_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_2: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din2_Din2          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din2_ipd,
-        TestSignalName => "Din2",
-        Period => tperiod_Din2,
-        PulseWidthHigh => tpw_Din2_posedge,
-        PulseWidthLow => tpw_Din2_negedge,
-        PeriodData => periodcheckinfo_Din2,
-        Violation => tviol_Din2_Din2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
-                           PathDelay => tpd_Din2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_B";
-
-      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din1 	: VitalDelayType := 0 ns;
-      tpw_Din1_posedge	: VitalDelayType := 0 ns;
-      tpw_Din1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
-
-  end Din_1_B;
-
-  architecture Structure of Din_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_1: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din1_Din1          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din1_ipd,
-        TestSignalName => "Din1",
-        Period => tperiod_Din1,
-        PulseWidthHigh => tpw_Din1_posedge,
-        PulseWidthLow => tpw_Din1_negedge,
-        PeriodData => periodcheckinfo_Din1,
-        Violation => tviol_Din1_Din1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
-                           PathDelay => tpd_Din1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity Din_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_B";
-
-      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din0 	: VitalDelayType := 0 ns;
-      tpw_Din0_posedge	: VitalDelayType := 0 ns;
-      tpw_Din0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
-
-  end Din_0_B;
-
-  architecture Structure of Din_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_0: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>Din0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din0_Din0          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din0_ipd,
-        TestSignalName => "Din0",
-        Period => tperiod_Din0,
-        PulseWidthHigh => tpw_Din0_posedge,
-        PulseWidthLow => tpw_Din0_negedge,
-        PeriodData => periodcheckinfo_Din0,
-        Violation => tviol_Din0_Din0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
-                           PathDelay => tpd_Din0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_1_B";
-
-      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW1 	: VitalDelayType := 0 ns;
-      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
-
-  end CROW_1_B;
-
-  architecture Structure of CROW_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_1: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW1_ipd,
-        TestSignalName => "CROW1",
-        Period => tperiod_CROW1,
-        PulseWidthHigh => tpw_CROW1_posedge,
-        PulseWidthLow => tpw_CROW1_negedge,
-        PeriodData => periodcheckinfo_CROW1,
-        Violation => tviol_CROW1_CROW1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
-                           PathDelay => tpd_CROW1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity CROW_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_0_B";
-
-      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW0 	: VitalDelayType := 0 ns;
-      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
-
-  end CROW_0_B;
-
-  architecture Structure of CROW_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_0: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW0_ipd,
-        TestSignalName => "CROW0",
-        Period => tperiod_CROW0,
-        PulseWidthHigh => tpw_CROW0_posedge,
-        PulseWidthLow => tpw_CROW0_negedge,
-        PeriodData => periodcheckinfo_CROW0,
-        Violation => tviol_CROW0_CROW0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
-                           PathDelay => tpd_CROW0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_9_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_9_B";
-
-      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin9 	: VitalDelayType := 0 ns;
-      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin9: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
-
-  end MAin_9_B;
-
-  architecture Structure of MAin_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin9_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_9: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin9_ipd,
-        TestSignalName => "MAin9",
-        Period => tperiod_MAin9,
-        PulseWidthHigh => tpw_MAin9_posedge,
-        PulseWidthLow => tpw_MAin9_negedge,
-        PeriodData => periodcheckinfo_MAin9,
-        Violation => tviol_MAin9_MAin9,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
-                           PathDelay => tpd_MAin9_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_8_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_8_B";
-
-      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin8 	: VitalDelayType := 0 ns;
-      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin8: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
-
-  end MAin_8_B;
-
-  architecture Structure of MAin_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin8_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_8: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin8_ipd,
-        TestSignalName => "MAin8",
-        Period => tperiod_MAin8,
-        PulseWidthHigh => tpw_MAin8_posedge,
-        PulseWidthLow => tpw_MAin8_negedge,
-        PeriodData => periodcheckinfo_MAin8,
-        Violation => tviol_MAin8_MAin8,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
-                           PathDelay => tpd_MAin8_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_7_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_7_B";
-
-      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin7 	: VitalDelayType := 0 ns;
-      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
-
-  end MAin_7_B;
-
-  architecture Structure of MAin_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin7_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_7: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin7_ipd,
-        TestSignalName => "MAin7",
-        Period => tperiod_MAin7,
-        PulseWidthHigh => tpw_MAin7_posedge,
-        PulseWidthLow => tpw_MAin7_negedge,
-        PeriodData => periodcheckinfo_MAin7,
-        Violation => tviol_MAin7_MAin7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
-                           PathDelay => tpd_MAin7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_6_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_6_B";
-
-      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin6 	: VitalDelayType := 0 ns;
-      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
-
-  end MAin_6_B;
-
-  architecture Structure of MAin_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin6_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_6: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin6_ipd,
-        TestSignalName => "MAin6",
-        Period => tperiod_MAin6,
-        PulseWidthHigh => tpw_MAin6_posedge,
-        PulseWidthLow => tpw_MAin6_negedge,
-        PeriodData => periodcheckinfo_MAin6,
-        Violation => tviol_MAin6_MAin6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
-                           PathDelay => tpd_MAin6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_5_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_5_B";
-
-      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin5 	: VitalDelayType := 0 ns;
-      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
-
-  end MAin_5_B;
-
-  architecture Structure of MAin_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin5_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_5: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin5_ipd,
-        TestSignalName => "MAin5",
-        Period => tperiod_MAin5,
-        PulseWidthHigh => tpw_MAin5_posedge,
-        PulseWidthLow => tpw_MAin5_negedge,
-        PeriodData => periodcheckinfo_MAin5,
-        Violation => tviol_MAin5_MAin5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
-                           PathDelay => tpd_MAin5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_4_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_4_B";
-
-      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin4 	: VitalDelayType := 0 ns;
-      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
-
-  end MAin_4_B;
-
-  architecture Structure of MAin_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin4_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_4: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin4_ipd,
-        TestSignalName => "MAin4",
-        Period => tperiod_MAin4,
-        PulseWidthHigh => tpw_MAin4_posedge,
-        PulseWidthLow => tpw_MAin4_negedge,
-        PeriodData => periodcheckinfo_MAin4,
-        Violation => tviol_MAin4_MAin4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
-                           PathDelay => tpd_MAin4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_3_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_3_B";
-
-      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin3 	: VitalDelayType := 0 ns;
-      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
-
-  end MAin_3_B;
-
-  architecture Structure of MAin_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin3_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_3: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin3_ipd,
-        TestSignalName => "MAin3",
-        Period => tperiod_MAin3,
-        PulseWidthHigh => tpw_MAin3_posedge,
-        PulseWidthLow => tpw_MAin3_negedge,
-        PeriodData => periodcheckinfo_MAin3,
-        Violation => tviol_MAin3_MAin3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
-                           PathDelay => tpd_MAin3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_2_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_2_B";
-
-      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin2 	: VitalDelayType := 0 ns;
-      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
-
-  end MAin_2_B;
-
-  architecture Structure of MAin_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin2_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_2: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin2_ipd,
-        TestSignalName => "MAin2",
-        Period => tperiod_MAin2,
-        PulseWidthHigh => tpw_MAin2_posedge,
-        PulseWidthLow => tpw_MAin2_negedge,
-        PeriodData => periodcheckinfo_MAin2,
-        Violation => tviol_MAin2_MAin2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
-                           PathDelay => tpd_MAin2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_1_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_1_B";
-
-      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin1 	: VitalDelayType := 0 ns;
-      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
-
-  end MAin_1_B;
-
-  architecture Structure of MAin_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin1_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_1: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin1_ipd,
-        TestSignalName => "MAin1",
-        Period => tperiod_MAin1,
-        PulseWidthHigh => tpw_MAin1_posedge,
-        PulseWidthLow => tpw_MAin1_negedge,
-        PeriodData => periodcheckinfo_MAin1,
-        Violation => tviol_MAin1_MAin1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
-                           PathDelay => tpd_MAin1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_0_B
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity MAin_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_0_B";
-
-      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin0 	: VitalDelayType := 0 ns;
-      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
-
-  end MAin_0_B;
-
-  architecture Structure of MAin_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin0_ipd 	: std_logic := 'X';
-
-    component mjiobuf0120
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_0: mjiobuf0120
-      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin0_ipd,
-        TestSignalName => "MAin0",
-        Period => tperiod_MAin0,
-        PulseWidthHigh => tpw_MAin0_posedge,
-        PulseWidthLow => tpw_MAin0_negedge,
-        PeriodData => periodcheckinfo_MAin0,
-        Violation => tviol_MAin0_MAin0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
-                           PathDelay => tpd_MAin0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RAM2GS
-  library IEEE, vital2000, MACHXO;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO.COMPONENTS.ALL;
-
-  entity RAM2GS is
-    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
-          CROW: in Std_logic_vector (1 downto 0); 
-          Din: in Std_logic_vector (7 downto 0); 
-          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
-          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
-          RBA: out Std_logic_vector (1 downto 0); 
-          RA: out Std_logic_vector (11 downto 0); 
-          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
-          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
-          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
-          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
-          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
-
-
-
-  end RAM2GS;
-
-  architecture Structure of RAM2GS is
-    signal FS_1: Std_logic;
-    signal FS_0: Std_logic;
-    signal RCLK_c: Std_logic;
-    signal FS_cry_1: Std_logic;
-    signal FS_17: Std_logic;
-    signal FS_16: Std_logic;
-    signal FS_cry_15: Std_logic;
-    signal FS_15: Std_logic;
-    signal FS_14: Std_logic;
-    signal FS_cry_13: Std_logic;
-    signal FS_13: Std_logic;
-    signal FS_12: Std_logic;
-    signal FS_cry_11: Std_logic;
-    signal FS_11: Std_logic;
-    signal FS_10: Std_logic;
-    signal FS_cry_9: Std_logic;
-    signal FS_9: Std_logic;
-    signal FS_8: Std_logic;
-    signal FS_cry_7: Std_logic;
-    signal FS_7: Std_logic;
-    signal FS_6: Std_logic;
-    signal FS_cry_5: Std_logic;
-    signal FS_5: Std_logic;
-    signal FS_4: Std_logic;
-    signal FS_cry_3: Std_logic;
-    signal FS_3: Std_logic;
-    signal FS_2: Std_logic;
-    signal CmdEnable17_0_a2_4: Std_logic;
-    signal N_147: Std_logic;
-    signal CmdEnable17_0_a2_3: Std_logic;
-    signal MAin_c_0: Std_logic;
-    signal ADSubmitted: Std_logic;
-    signal C1WR_0_a2: Std_logic;
-    signal CmdEnable17: Std_logic;
-    signal CmdEnable16: Std_logic;
-    signal ADSubmitted_r: Std_logic;
-    signal PHI2_c: Std_logic;
-    signal CmdEnable16_0_a2_5: Std_logic;
-    signal CmdEnable16_0_a2_4: Std_logic;
-    signal MAin_c_1: Std_logic;
-    signal C1Submitted: Std_logic;
-    signal C1Submitted_RNO: Std_logic;
-    signal CO0: Std_logic;
-    signal S_1: Std_logic;
-    signal IS_3: Std_logic;
-    signal RASr2: Std_logic;
-    signal N_177_i: Std_logic;
-    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
-    signal CmdEnable: Std_logic;
-    signal un1_CMDWR: Std_logic;
-    signal CmdEnable_s: Std_logic;
-    signal Din_c_5: Std_logic;
-    signal Din_c_3: Std_logic;
-    signal N_128: Std_logic;
-    signal N_152: Std_logic;
-    signal LEDEN: Std_logic;
-    signal N_133: Std_logic;
-    signal N_132: Std_logic;
-    signal N_21_i: Std_logic;
-    signal XOR8MEG18: Std_logic;
-    signal CmdLEDEN: Std_logic;
-    signal CmdSubmitted: Std_logic;
-    signal PHI2r3: Std_logic;
-    signal PHI2r2: Std_logic;
-    signal InitReady: Std_logic;
-    signal CmdSubmitted_1_sqmuxa: Std_logic;
-    signal N_460_0: Std_logic;
-    signal N_136: Std_logic;
-    signal N_43: Std_logic;
-    signal Cmdn8MEGEN: Std_logic;
-    signal CmdEnable16_4: Std_logic;
-    signal n8MEGEN: Std_logic;
-    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
-    signal N_19_i: Std_logic;
-    signal N_160: Std_logic;
-    signal N_155: Std_logic;
-    signal nRRAS_5_u_i_0: Std_logic;
-    signal IS_0: Std_logic;
-    signal Ready: Std_logic;
-    signal N_64_i_i: Std_logic;
-    signal N_24: Std_logic;
-    signal IS_2: Std_logic;
-    signal IS_1: Std_logic;
-    signal N_60_i_i: Std_logic;
-    signal N_56_i: Std_logic;
-    signal N_159_i: Std_logic;
-    signal N_159: Std_logic;
-    signal N_61_i_i: Std_logic;
-    signal RA10s_i: Std_logic;
-    signal N_126: Std_logic;
-    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
-    signal N_51: Std_logic;
-    signal InitReady3: Std_logic;
-    signal N_461_0: Std_logic;
-    signal UFMSDI_ens2_i_a0: Std_logic;
-    signal nCRAS_c: Std_logic;
-    signal CBR: Std_logic;
-    signal UFMSDO_c: Std_logic;
-    signal N_70: Std_logic;
-    signal N_33: Std_logic;
-    signal LED_c: Std_logic;
-    signal XOR8MEG: Std_logic;
-    signal un1_Din_4: Std_logic;
-    signal Din_c_6: Std_logic;
-    signal RA11_2: Std_logic;
-    signal Ready_fast: Std_logic;
-    signal RA_c_11: Std_logic;
-    signal N_171: Std_logic;
-    signal FWEr_fast: Std_logic;
-    signal CASr2: Std_logic;
-    signal RCKEEN_8_u_1: Std_logic;
-    signal RCKEEN_8_u_0_0: Std_logic;
-    signal RCKEEN_8: Std_logic;
-    signal PHI2r: Std_logic;
-    signal RCKEEN: Std_logic;
-    signal RASr: Std_logic;
-    signal RASr3: Std_logic;
-    signal RCKE_2: Std_logic;
-    signal RCKE_c: Std_logic;
-    signal m18_0_a3_3: Std_logic;
-    signal S_0_i_o2_1: Std_logic;
-    signal N_165: Std_logic;
-    signal N_462_0: Std_logic;
-    signal Ready_0_sqmuxa: Std_logic;
-    signal N_463_0: Std_logic;
-    signal nRRAS_0_sqmuxa: Std_logic;
-    signal CmdUFMCLK: Std_logic;
-    signal N_129: Std_logic;
-    signal UFMCLK_r_i_a2_2_2: Std_logic;
-    signal N_139_i: Std_logic;
-    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
-    signal nUFMCS15: Std_logic;
-    signal UFMCLK_c: Std_logic;
-    signal UFMCLK_RNO: Std_logic;
-    signal UFMSDI_r_xx_mm_1: Std_logic;
-    signal UFMSDI_c: Std_logic;
-    signal UFMSDI_RNO: Std_logic;
-    signal RowA_4: Std_logic;
-    signal nRowColSel: Std_logic;
-    signal MAin_c_4: Std_logic;
-    signal Din_c_4: Std_logic;
-    signal nCCAS_c: Std_logic;
-    signal RA_c_4: Std_logic;
-    signal WRD_4: Std_logic;
-    signal WRD_5: Std_logic;
-    signal Bank_5: Std_logic;
-    signal Bank_2: Std_logic;
-    signal Bank_6: Std_logic;
-    signal Bank_7: Std_logic;
-    signal Din_c_7: Std_logic;
-    signal WRD_6: Std_logic;
-    signal C1WR_0_a2_0_11: Std_logic;
-    signal WRD_7: Std_logic;
-    signal Din_c_2: Std_logic;
-    signal Din_c_0: Std_logic;
-    signal Din_c_1: Std_logic;
-    signal XOR8MEG_3_u_0_a3_2: Std_logic;
-    signal XOR8MEG_3: Std_logic;
-    signal N_69: Std_logic;
-    signal N_31: Std_logic;
-    signal N_151: Std_logic;
-    signal N_41: Std_logic;
-    signal nRCAS_0_sqmuxa_1: Std_logic;
-    signal g0_1: Std_logic;
-    signal N_37_i: Std_logic;
-    signal nRCAS_c: Std_logic;
-    signal CASr3: Std_logic;
-    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
-    signal N_28_i_1: Std_logic;
-    signal N_28_i: Std_logic;
-    signal nRCS_c: Std_logic;
-    signal N_24_i: Std_logic;
-    signal nRRAS_c: Std_logic;
-    signal CBR_fast: Std_logic;
-    signal FWEr: Std_logic;
-    signal m18_0_a2_1: Std_logic;
-    signal G_17_1: Std_logic;
-    signal N_39_i: Std_logic;
-    signal nRWE_c: Std_logic;
-    signal N_179: Std_logic;
-    signal nRowColSel_0_0: Std_logic;
-    signal nUFMCS_c: Std_logic;
-    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
-    signal nUFMCS_s_0_N_5_i: Std_logic;
-    signal CmdUFMCS: Std_logic;
-    signal N_95_5: Std_logic;
-    signal N_95_3: Std_logic;
-    signal RowA_0: Std_logic;
-    signal RowA_1: Std_logic;
-    signal MAin_c_5: Std_logic;
-    signal CmdUFMCLK_1_sqmuxa: Std_logic;
-    signal RowA_5: Std_logic;
-    signal N_137_8: Std_logic;
-    signal un1_FS_14_i_a2_0_1: Std_logic;
-    signal N_137_6: Std_logic;
-    signal un1_FS_13_i_a2_1: Std_logic;
-    signal Bank_0: Std_logic;
-    signal C1WR_0_a2_0_10: Std_logic;
-    signal Bank_1: Std_logic;
-    signal MAin_c_7: Std_logic;
-    signal MAin_c_6: Std_logic;
-    signal C1WR_0_a2_0_4: Std_logic;
-    signal Bank_3: Std_logic;
-    signal Bank_4: Std_logic;
-    signal C1WR_0_a2_0_3: Std_logic;
-    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
-    signal MAin_c_3: Std_logic;
-    signal MAin_c_2: Std_logic;
-    signal RowA_2: Std_logic;
-    signal RowA_3: Std_logic;
-    signal CmdUFMSDI: Std_logic;
-    signal CASr: Std_logic;
-    signal CmdEnable16_1: Std_logic;
-    signal m6_0_a2_2: Std_logic;
-    signal WRD_0: Std_logic;
-    signal WRD_1: Std_logic;
-    signal g4_0_0_0: Std_logic;
-    signal MAin_c_9: Std_logic;
-    signal MAin_c_8: Std_logic;
-    signal RowA_8: Std_logic;
-    signal RowA_9: Std_logic;
-    signal nFWE_c: Std_logic;
-    signal CROW_c_1: Std_logic;
-    signal CROW_c_0: Std_logic;
-    signal RBA_c_0: Std_logic;
-    signal RBA_c_1: Std_logic;
-    signal WRD_2: Std_logic;
-    signal WRD_3: Std_logic;
-    signal RA_c_9: Std_logic;
-    signal RDQML_c: Std_logic;
-    signal RD_1_i: Std_logic;
-    signal RowA_6: Std_logic;
-    signal RowA_7: Std_logic;
-    signal RA_c_8: Std_logic;
-    signal RDQMH_c: Std_logic;
-    signal RA_c_0: Std_logic;
-    signal RA_c_1: Std_logic;
-    signal RA_c_7: Std_logic;
-    signal RA_c_2: Std_logic;
-    signal RA_c_6: Std_logic;
-    signal RA_c_3: Std_logic;
-    signal RA_c_5: Std_logic;
-    signal RA_c_10: Std_logic;
-    signal RD_in_0: Std_logic;
-    signal RD_in_7: Std_logic;
-    signal RD_in_6: Std_logic;
-    signal RD_in_5: Std_logic;
-    signal RD_in_4: Std_logic;
-    signal RD_in_3: Std_logic;
-    signal RD_in_2: Std_logic;
-    signal RD_in_1: Std_logic;
-    signal VCCI: Std_logic;
-    signal GNDI_TSALL: Std_logic;
-    component VHI
-      port (Z: out Std_logic);
-    end component;
-    component VLO
-      port (Z: out Std_logic);
-    end component;
-    component PUR
-      port (PUR: in Std_logic);
-    end component;
-    component GSR
-      port (GSR: in Std_logic);
-    end component;
-    component TSALL
-      port (TSALL: in Std_logic);
-    end component;
-    component SLICE_0
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_1
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_2
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_3
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_4
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_5
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_6
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_7
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_8
-      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
-            FCO: out Std_logic);
-    end component;
-    component SLICE_9
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_14
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_19
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_20
-      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_21
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_22
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_26
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_29
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_30
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_31
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_32
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_33
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_39
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_41
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_42
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_43
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_44
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_50
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_51
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_52
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_55
-      port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_56
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_57
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_58
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_59
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_60
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_61
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_62
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_63
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_64
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component nRWE_RNO_1_SLICE_65
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            OFX0: out Std_logic);
-    end component;
-    component SLICE_66
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_67
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_68
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_69
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_70
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_71
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_72
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_73
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_74
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_75
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_76
-      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_77
-      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_78
-      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_79
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_80
-      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_81
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_82
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_83
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_84
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_85
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_86
-      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_87
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_88
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; M1: in Std_logic; 
-            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_89
-      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_90
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_91
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_92
-      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_93
-      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_94
-      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component RD_0_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD0: inout Std_logic);
-    end component;
-    component Dout_0_B
-      port (PADDO: in Std_logic; Dout0: out Std_logic);
-    end component;
-    component PHI2B
-      port (PADDI: out Std_logic; PHI2S: in Std_logic);
-    end component;
-    component UFMSDOB
-      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-    end component;
-    component UFMSDIB
-      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
-    end component;
-    component UFMCLKB
-      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
-    end component;
-    component nUFMCSB
-      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
-    end component;
-    component RDQMLB
-      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-    end component;
-    component RDQMHB
-      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-    end component;
-    component nRCASB
-      port (PADDO: in Std_logic; nRCASS: out Std_logic);
-    end component;
-    component nRRASB
-      port (PADDO: in Std_logic; nRRASS: out Std_logic);
-    end component;
-    component nRWEB
-      port (PADDO: in Std_logic; nRWES: out Std_logic);
-    end component;
-    component RCKEB
-      port (PADDO: in Std_logic; RCKES: out Std_logic);
-    end component;
-    component RCLKB
-      port (PADDI: out Std_logic; RCLKS: in Std_logic);
-    end component;
-    component nRCSB
-      port (PADDO: in Std_logic; nRCSS: out Std_logic);
-    end component;
-    component RD_7_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD7: inout Std_logic);
-    end component;
-    component RD_6_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD6: inout Std_logic);
-    end component;
-    component RD_5_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD5: inout Std_logic);
-    end component;
-    component RD_4_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD4: inout Std_logic);
-    end component;
-    component RD_3_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD3: inout Std_logic);
-    end component;
-    component RD_2_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD2: inout Std_logic);
-    end component;
-    component RD_1_B
-      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
-            RD1: inout Std_logic);
-    end component;
-    component RA_11_B
-      port (PADDO: in Std_logic; RA11: out Std_logic);
-    end component;
-    component RA_10_B
-      port (PADDO: in Std_logic; RA10: out Std_logic);
-    end component;
-    component RA_9_B
-      port (PADDO: in Std_logic; RA9: out Std_logic);
-    end component;
-    component RA_8_B
-      port (PADDO: in Std_logic; RA8: out Std_logic);
-    end component;
-    component RA_7_B
-      port (PADDO: in Std_logic; RA7: out Std_logic);
-    end component;
-    component RA_6_B
-      port (PADDO: in Std_logic; RA6: out Std_logic);
-    end component;
-    component RA_5_B
-      port (PADDO: in Std_logic; RA5: out Std_logic);
-    end component;
-    component RA_4_B
-      port (PADDO: in Std_logic; RA4: out Std_logic);
-    end component;
-    component RA_3_B
-      port (PADDO: in Std_logic; RA3: out Std_logic);
-    end component;
-    component RA_2_B
-      port (PADDO: in Std_logic; RA2: out Std_logic);
-    end component;
-    component RA_1_B
-      port (PADDO: in Std_logic; RA1: out Std_logic);
-    end component;
-    component RA_0_B
-      port (PADDO: in Std_logic; RA0: out Std_logic);
-    end component;
-    component RBA_1_B
-      port (PADDO: in Std_logic; RBA1: out Std_logic);
-    end component;
-    component RBA_0_B
-      port (PADDO: in Std_logic; RBA0: out Std_logic);
-    end component;
-    component LEDB
-      port (PADDO: in Std_logic; LEDS: out Std_logic);
-    end component;
-    component nFWEB
-      port (PADDI: out Std_logic; nFWES: in Std_logic);
-    end component;
-    component nCRASB
-      port (PADDI: out Std_logic; nCRASS: in Std_logic);
-    end component;
-    component nCCASB
-      port (PADDI: out Std_logic; nCCASS: in Std_logic);
-    end component;
-    component Dout_7_B
-      port (PADDO: in Std_logic; Dout7: out Std_logic);
-    end component;
-    component Dout_6_B
-      port (PADDO: in Std_logic; Dout6: out Std_logic);
-    end component;
-    component Dout_5_B
-      port (PADDO: in Std_logic; Dout5: out Std_logic);
-    end component;
-    component Dout_4_B
-      port (PADDO: in Std_logic; Dout4: out Std_logic);
-    end component;
-    component Dout_3_B
-      port (PADDO: in Std_logic; Dout3: out Std_logic);
-    end component;
-    component Dout_2_B
-      port (PADDO: in Std_logic; Dout2: out Std_logic);
-    end component;
-    component Dout_1_B
-      port (PADDO: in Std_logic; Dout1: out Std_logic);
-    end component;
-    component Din_7_B
-      port (PADDI: out Std_logic; Din7: in Std_logic);
-    end component;
-    component Din_6_B
-      port (PADDI: out Std_logic; Din6: in Std_logic);
-    end component;
-    component Din_5_B
-      port (PADDI: out Std_logic; Din5: in Std_logic);
-    end component;
-    component Din_4_B
-      port (PADDI: out Std_logic; Din4: in Std_logic);
-    end component;
-    component Din_3_B
-      port (PADDI: out Std_logic; Din3: in Std_logic);
-    end component;
-    component Din_2_B
-      port (PADDI: out Std_logic; Din2: in Std_logic);
-    end component;
-    component Din_1_B
-      port (PADDI: out Std_logic; Din1: in Std_logic);
-    end component;
-    component Din_0_B
-      port (PADDI: out Std_logic; Din0: in Std_logic);
-    end component;
-    component CROW_1_B
-      port (PADDI: out Std_logic; CROW1: in Std_logic);
-    end component;
-    component CROW_0_B
-      port (PADDI: out Std_logic; CROW0: in Std_logic);
-    end component;
-    component MAin_9_B
-      port (PADDI: out Std_logic; MAin9: in Std_logic);
-    end component;
-    component MAin_8_B
-      port (PADDI: out Std_logic; MAin8: in Std_logic);
-    end component;
-    component MAin_7_B
-      port (PADDI: out Std_logic; MAin7: in Std_logic);
-    end component;
-    component MAin_6_B
-      port (PADDI: out Std_logic; MAin6: in Std_logic);
-    end component;
-    component MAin_5_B
-      port (PADDI: out Std_logic; MAin5: in Std_logic);
-    end component;
-    component MAin_4_B
-      port (PADDI: out Std_logic; MAin4: in Std_logic);
-    end component;
-    component MAin_3_B
-      port (PADDI: out Std_logic; MAin3: in Std_logic);
-    end component;
-    component MAin_2_B
-      port (PADDI: out Std_logic; MAin2: in Std_logic);
-    end component;
-    component MAin_1_B
-      port (PADDI: out Std_logic; MAin1: in Std_logic);
-    end component;
-    component MAin_0_B
-      port (PADDI: out Std_logic; MAin0: in Std_logic);
-    end component;
-  begin
-    SLICE_0I: SLICE_0
-      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
-                FCO=>FS_cry_1);
-    SLICE_1I: SLICE_1
-      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
-                Q1=>FS_17);
-    SLICE_2I: SLICE_2
-      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
-                Q1=>FS_15, FCO=>FS_cry_15);
-    SLICE_3I: SLICE_3
-      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
-                Q1=>FS_13, FCO=>FS_cry_13);
-    SLICE_4I: SLICE_4
-      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
-                Q1=>FS_11, FCO=>FS_cry_11);
-    SLICE_5I: SLICE_5
-      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
-                Q1=>FS_9, FCO=>FS_cry_9);
-    SLICE_6I: SLICE_6
-      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
-                Q1=>FS_7, FCO=>FS_cry_7);
-    SLICE_7I: SLICE_7
-      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
-                Q1=>FS_5, FCO=>FS_cry_5);
-    SLICE_8I: SLICE_8
-      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
-                Q1=>FS_3, FCO=>FS_cry_3);
-    SLICE_9I: SLICE_9
-      port map (D1=>CmdEnable17_0_a2_4, C1=>N_147, B1=>CmdEnable17_0_a2_3, 
-                A1=>MAin_c_0, D0=>ADSubmitted, C0=>C1WR_0_a2, B0=>CmdEnable17, 
-                A0=>CmdEnable16, DI0=>ADSubmitted_r, CLK=>PHI2_c, 
-                F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
-    SLICE_14I: SLICE_14
-      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
-                D0=>CmdEnable16, C0=>N_147, B0=>MAin_c_1, A0=>C1Submitted, 
-                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
-                Q0=>C1Submitted, F1=>CmdEnable16);
-    SLICE_19I: SLICE_19
-      port map (D1=>CO0, C1=>S_1, B1=>IS_3, A1=>RASr2, C0=>S_1, A0=>CO0, 
-                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
-                F1=>Ready_0_sqmuxa_0_a3_2);
-    SLICE_20I: SLICE_20
-      port map (D1=>CmdEnable, A1=>ADSubmitted, D0=>CmdEnable17, 
-                C0=>C1Submitted, B0=>un1_CMDWR, A0=>CmdEnable, 
-                DI0=>CmdEnable_s, M0=>CmdEnable16, CLK=>PHI2_c, 
-                OFX0=>CmdEnable_s, Q0=>CmdEnable);
-    SLICE_21I: SLICE_21
-      port map (D1=>Din_c_5, C1=>Din_c_3, B1=>N_128, D0=>N_152, C0=>LEDEN, 
-                B0=>N_133, A0=>N_132, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
-                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
-    SLICE_22I: SLICE_22
-      port map (D1=>CmdSubmitted, C1=>PHI2r3, B1=>PHI2r2, A1=>InitReady, 
-                D0=>CmdSubmitted_1_sqmuxa, A0=>CmdSubmitted, DI0=>N_460_0, 
-                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
-    SLICE_26I: SLICE_26
-      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
-                D0=>n8MEGEN, C0=>Cmdn8MEGEN_4_u_i_0, A0=>N_152, DI0=>N_19_i, 
-                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
-                F1=>Cmdn8MEGEN_4_u_i_0);
-    SLICE_29I: SLICE_29
-      port map (D1=>N_160, C1=>N_155, B1=>nRRAS_5_u_i_0, A1=>IS_0, C0=>N_155, 
-                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
-                Q0=>IS_0, F1=>N_24);
-    SLICE_30I: SLICE_30
-      port map (D1=>IS_0, C1=>IS_2, A1=>IS_1, D0=>IS_0, A0=>IS_1, 
-                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
-    SLICE_31I: SLICE_31
-      port map (D1=>IS_2, C1=>N_159, B1=>IS_1, A1=>IS_3, D0=>IS_2, C0=>IS_3, 
-                B0=>IS_1, A0=>IS_0, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
-                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
-    SLICE_32I: SLICE_32
-      port map (D1=>N_126, C1=>InitReady, B1=>UFMSDI_ens2_i_a2_4_2, A1=>N_51, 
-                D0=>InitReady3, A0=>InitReady, DI0=>N_461_0, CLK=>RCLK_c, 
-                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
-    SLICE_33I: SLICE_33
-      port map (D1=>LEDEN, C1=>nCRAS_c, A1=>CBR, D0=>InitReady, B0=>CmdLEDEN, 
-                A0=>UFMSDO_c, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
-                Q0=>LEDEN, F1=>LED_c);
-    SLICE_39I: SLICE_39
-      port map (D1=>XOR8MEG, B1=>un1_Din_4, D0=>XOR8MEG, B0=>Din_c_6, 
-                A0=>n8MEGEN, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
-                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
-    SLICE_41I: SLICE_41
-      port map (D1=>CO0, C1=>FWEr_fast, B1=>CASr2, A1=>S_1, D0=>CBR, 
-                C0=>RCKEEN_8_u_1, B0=>Ready, A0=>RCKEEN_8_u_0_0, DI0=>RCKEEN_8, 
-                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
-                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
-    SLICE_42I: SLICE_42
-      port map (D1=>IS_1, C1=>IS_2, B1=>IS_0, A1=>RASr2, D0=>RASr, C0=>RASr3, 
-                B0=>RCKEEN, A0=>RASr2, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
-                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
-    SLICE_43I: SLICE_43
-      port map (D1=>Ready, C1=>S_0_i_o2_1, B1=>RASr2, A1=>InitReady, D0=>Ready, 
-                C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>InitReady, 
-                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
-                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
-    SLICE_44I: SLICE_44
-      port map (D1=>Ready, C1=>N_165, B1=>Ready_0_sqmuxa_0_a3_2, A1=>InitReady, 
-                B0=>Ready_0_sqmuxa, A0=>Ready_fast, DI0=>N_463_0, M1=>nCRAS_c, 
-                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
-                Q1=>RASr);
-    SLICE_50I: SLICE_50
-      port map (D1=>Ready, C1=>CO0, A1=>S_1, C0=>CO0, A0=>S_1, DI0=>S_0_i_o2_1, 
-                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
-                F1=>nRRAS_0_sqmuxa);
-    SLICE_51I: SLICE_51
-      port map (D1=>CmdUFMCLK, C1=>InitReady, B1=>N_129, A1=>UFMCLK_r_i_a2_2_2, 
-                D0=>N_139_i, C0=>UFMCLK_r_i_m4_xx_mm_1, B0=>nUFMCS15, 
-                A0=>UFMCLK_c, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
-                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
-                Q1=>RASr2);
-    SLICE_52I: SLICE_52
-      port map (D1=>PHI2r3, C1=>InitReady, B1=>PHI2r2, A1=>CmdSubmitted, 
-                D0=>UFMSDI_r_xx_mm_1, C0=>N_139_i, B0=>UFMSDI_c, A0=>nUFMCS15, 
-                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
-                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
-    SLICE_55I: SLICE_55
-      port map (D0=>RowA_4, B0=>nRowColSel, A0=>MAin_c_4, M1=>Din_c_5, 
-                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
-    SLICE_56I: SLICE_56
-      port map (D1=>Bank_5, C1=>Bank_2, B1=>Bank_6, A1=>Bank_7, D0=>FS_5, 
-                C0=>FS_9, A0=>FS_7, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
-                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
-    SLICE_57I: SLICE_57
-      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
-                D0=>Din_c_1, C0=>XOR8MEG_3_u_0_a3_2, B0=>LEDEN, A0=>N_171, 
-                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
-                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
-    SLICE_58I: SLICE_58
-      port map (D1=>N_51, C1=>FS_8, A1=>InitReady, D0=>UFMSDO_c, 
-                B0=>Cmdn8MEGEN, A0=>InitReady, DI0=>N_69, CE=>N_31, 
-                CLK=>RCLK_c, F0=>N_69, Q0=>n8MEGEN, F1=>N_151);
-    SLICE_59I: SLICE_59
-      port map (D1=>Ready, C1=>S_1, B1=>N_155, A1=>N_160, D0=>N_41, 
-                C0=>nRCAS_0_sqmuxa_1, B0=>S_1, A0=>g0_1, DI0=>N_37_i, 
-                CLK=>RCLK_c, F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
-    SLICE_60I: SLICE_60
-      port map (D1=>CASr3, C1=>CO0, B1=>FWEr_fast, A1=>CASr2, D0=>CBR, 
-                C0=>RCKEEN_8_u_0_a2_1_out, B0=>N_24, A0=>N_28_i_1, DI0=>N_28_i, 
-                CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
-    SLICE_61I: SLICE_61
-      port map (D1=>S_0_i_o2_1, C1=>Ready, B1=>RASr2, A1=>RCKE_c, D0=>N_160, 
-                C0=>N_155, B0=>nRRAS_5_u_i_0, A0=>IS_0, DI0=>N_24_i, 
-                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
-    SLICE_62I: SLICE_62
-      port map (D1=>CBR_fast, C1=>S_0_i_o2_1, B1=>Ready, A1=>RASr2, D0=>FWEr, 
-                C0=>m18_0_a2_1, B0=>nRCAS_0_sqmuxa_1, A0=>G_17_1, DI0=>N_39_i, 
-                CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, F1=>nRCAS_0_sqmuxa_1);
-    SLICE_63I: SLICE_63
-      port map (D1=>CASr3, C1=>Ready, B1=>FWEr, A1=>CBR, D0=>N_179, C0=>Ready, 
-                B0=>CO0, A0=>S_1, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
-                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
-    SLICE_64I: SLICE_64
-      port map (D1=>FS_10, C1=>N_51, B1=>FS_11, A1=>InitReady, D0=>nUFMCS_c, 
-                C0=>nUFMCS_s_0_N_5_i_N_2L1, B0=>nUFMCS15, A0=>N_139_i, 
-                DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, F0=>nUFMCS_s_0_N_5_i, 
-                Q0=>nUFMCS_c, F1=>nUFMCS15);
-    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
-      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>S_1, 
-                C0=>m18_0_a3_3, B0=>CO0, A0=>InitReady, M0=>Ready, 
-                OFX0=>m18_0_a2_1);
-    SLICE_66I: SLICE_66
-      port map (C1=>InitReady, B1=>CmdUFMCS, A1=>UFMCLK_r_i_a2_2_2, D0=>N_95_5, 
-                C0=>InitReady, B0=>FS_16, A0=>N_95_3, M1=>MAin_c_1, 
-                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
-                Q1=>RowA_1);
-    SLICE_67I: SLICE_67
-      port map (D1=>Din_c_5, C1=>XOR8MEG18, B1=>Din_c_3, A1=>N_128, 
-                D0=>MAin_c_1, C0=>MAin_c_0, B0=>CmdEnable, A0=>N_147, 
-                M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>XOR8MEG18, Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
-    SLICE_68I: SLICE_68
-      port map (D1=>FS_3, C1=>FS_0, B1=>FS_2, A1=>FS_5, D0=>N_136, C0=>N_137_8, 
-                B0=>un1_FS_14_i_a2_0_1, A0=>N_137_6, F0=>N_31, 
-                F1=>un1_FS_14_i_a2_0_1);
-    SLICE_69I: SLICE_69
-      port map (D1=>FS_3, C1=>FS_0, B1=>FS_2, A1=>FS_5, D0=>N_137_8, 
-                C0=>un1_FS_13_i_a2_1, B0=>N_136, A0=>N_137_6, F0=>N_33, 
-                F1=>un1_FS_13_i_a2_1);
-    SLICE_70I: SLICE_70
-      port map (D1=>Bank_0, C1=>C1WR_0_a2_0_10, B1=>C1WR_0_a2_0_11, A1=>Bank_1, 
-                C0=>MAin_c_1, B0=>N_147, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
-                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
-    SLICE_71I: SLICE_71
-      port map (D1=>MAin_c_5, C1=>MAin_c_7, B1=>MAin_c_6, A1=>MAin_c_4, 
-                D0=>C1WR_0_a2_0_4, C0=>Bank_3, B0=>Bank_4, A0=>C1WR_0_a2_0_3, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
-                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
-    SLICE_72I: SLICE_72
-      port map (D1=>UFMSDI_ens2_i_o2_0_3, C1=>FS_16, A1=>FS_12, D0=>FS_1, 
-                C0=>N_51, B0=>FS_11, A0=>FS_4, M1=>MAin_c_3, M0=>MAin_c_2, 
-                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
-                Q1=>RowA_3);
-    SLICE_73I: SLICE_73
-      port map (D1=>S_1, C1=>RASr2, B1=>CO0, A1=>InitReady, B0=>N_155, 
-                A0=>Ready, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
-                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
-    SLICE_74I: SLICE_74
-      port map (D1=>FS_14, B1=>FS_11, D0=>FS_16, C0=>N_95_3, B0=>FS_10, 
-                A0=>N_95_5, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
-    SLICE_75I: SLICE_75
-      port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, D0=>Din_c_1, C0=>N_128, 
-                A0=>Din_c_5, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
-                Q0=>CASr, F1=>N_128, Q1=>CASr2);
-    SLICE_76I: SLICE_76
-      port map (D1=>Din_c_5, B1=>Din_c_0, D0=>MAin_c_0, C0=>CmdEnable16_4, 
-                B0=>Din_c_1, A0=>Din_c_3, M1=>Din_c_5, M0=>Din_c_4, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
-                F1=>CmdEnable16_4, Q1=>Bank_5);
-    SLICE_77I: SLICE_77
-      port map (C1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>CmdEnable16_1, 
-                B0=>Din_c_6, A0=>Din_c_2, M1=>Din_c_7, M0=>Din_c_6, 
-                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
-                F1=>CmdEnable16_1, Q1=>Bank_7);
-    SLICE_78I: SLICE_78
-      port map (C1=>Din_c_3, B1=>Din_c_5, D0=>MAin_c_1, C0=>Din_c_6, B0=>N_43, 
-                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
-                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
-    SLICE_79I: SLICE_79
-      port map (D1=>CASr3, C1=>Ready, B1=>CASr2, D0=>CO0, C0=>m6_0_a2_2, 
-                B0=>CBR, A0=>S_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
-                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
-    SLICE_80I: SLICE_80
-      port map (C1=>CASr2, B1=>CASr3, D0=>FWEr, C0=>CBR_fast, B0=>g4_0_0_0, 
-                A0=>CO0, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
-    SLICE_81I: SLICE_81
-      port map (D1=>FS_14, C1=>FS_17, B1=>FS_15, A1=>FS_13, D0=>FS_12, 
-                C0=>FS_17, B0=>FS_15, A0=>FS_13, M1=>nFWE_c, M0=>nFWE_c, 
-                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
-                Q1=>FWEr_fast);
-    SLICE_82I: SLICE_82
-      port map (D1=>Din_c_5, C1=>CmdLEDEN, B1=>N_128, A1=>Din_c_3, D0=>Din_c_5, 
-                C0=>XOR8MEG18, B0=>N_128, A0=>Din_c_3, M0=>CASr2, CLK=>RCLK_c, 
-                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
-    SLICE_83I: SLICE_83
-      port map (C1=>IS_2, B1=>IS_3, A1=>IS_1, D0=>IS_0, C0=>IS_2, A0=>IS_1, 
-                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
-                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
-    SLICE_84I: SLICE_84
-      port map (D1=>FS_8, C1=>FS_10, B1=>FS_11, A1=>FS_6, D0=>FS_7, C0=>FS_1, 
-                B0=>FS_10, A0=>FS_6, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
-    SLICE_85I: SLICE_85
-      port map (D1=>Din_c_1, C1=>Din_c_7, B1=>Din_c_4, A1=>Din_c_0, 
-                D0=>Din_c_6, C0=>Din_c_7, B0=>Din_c_4, A0=>Din_c_5, 
-                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
-                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
-    SLICE_86I: SLICE_86
-      port map (C1=>MAin_c_9, A1=>nRowColSel, C0=>MAin_c_9, B0=>RowA_9, 
-                A0=>nRowColSel, F0=>RA_c_9, F1=>RDQML_c);
-    SLICE_87I: SLICE_87
-      port map (D1=>UFMSDI_ens2_i_a0, C1=>CmdUFMSDI, B1=>N_151, D0=>N_151, 
-                C0=>FS_9, B0=>FS_11, A0=>FS_4, F0=>N_137_8, 
-                F1=>UFMSDI_r_xx_mm_1);
-    SLICE_88I: SLICE_88
-      port map (C1=>nFWE_c, B1=>MAin_c_2, A1=>MAin_c_3, D0=>nCCAS_c, 
-                C0=>nFWE_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
-                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
-                Q1=>RowA_7);
-    SLICE_89I: SLICE_89
-      port map (D1=>nRowColSel, C1=>MAin_c_9, D0=>nRowColSel, C0=>MAin_c_8, 
-                B0=>RowA_8, F0=>RA_c_8, F1=>RDQMH_c);
-    SLICE_90I: SLICE_90
-      port map (C1=>N_147, B1=>MAin_c_0, A1=>MAin_c_1, D0=>RowA_0, 
-                B0=>MAin_c_0, A0=>nRowColSel, F0=>RA_c_0, F1=>un1_CMDWR);
-    SLICE_91I: SLICE_91
-      port map (D1=>nRowColSel, C1=>RowA_7, B1=>MAin_c_7, D0=>RowA_1, 
-                C0=>nRowColSel, B0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
-    SLICE_92I: SLICE_92
-      port map (D1=>nRowColSel, C1=>MAin_c_6, A1=>RowA_6, D0=>nRowColSel, 
-                C0=>RowA_2, B0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
-    SLICE_93I: SLICE_93
-      port map (D1=>RowA_5, B1=>nRowColSel, A1=>MAin_c_5, D0=>RowA_3, 
-                B0=>nRowColSel, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
-    SLICE_94I: SLICE_94
-      port map (D1=>Ready, C1=>N_155, D0=>Ready, C0=>S_1, M0=>IS_0, 
-                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
-                Q0=>RA_c_10, F1=>N_159_i);
-    RD_0_I: RD_0_B
-      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
-    Dout_0_I: Dout_0_B
-      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
-    PHI2I: PHI2B
-      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
-    UFMSDOI: UFMSDOB
-      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
-    UFMSDII: UFMSDIB
-      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
-    UFMCLKI: UFMCLKB
-      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
-    nUFMCSI: nUFMCSB
-      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
-    RDQMLI: RDQMLB
-      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
-    RDQMHI: RDQMHB
-      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
-    nRCASI: nRCASB
-      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
-    nRRASI: nRRASB
-      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
-    nRWEI: nRWEB
-      port map (PADDO=>nRWE_c, nRWES=>nRWE);
-    RCKEI: RCKEB
-      port map (PADDO=>RCKE_c, RCKES=>RCKE);
-    RCLKI: RCLKB
-      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
-    nRCSI: nRCSB
-      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
-    RD_7_I: RD_7_B
-      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
-    RD_6_I: RD_6_B
-      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
-    RD_5_I: RD_5_B
-      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
-    RD_4_I: RD_4_B
-      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
-    RD_3_I: RD_3_B
-      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
-    RD_2_I: RD_2_B
-      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
-    RD_1_I0: RD_1_B
-      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
-    RA_11_I: RA_11_B
-      port map (PADDO=>RA_c_11, RA11=>RA(11));
-    RA_10_I: RA_10_B
-      port map (PADDO=>RA_c_10, RA10=>RA(10));
-    RA_9_I: RA_9_B
-      port map (PADDO=>RA_c_9, RA9=>RA(9));
-    RA_8_I: RA_8_B
-      port map (PADDO=>RA_c_8, RA8=>RA(8));
-    RA_7_I: RA_7_B
-      port map (PADDO=>RA_c_7, RA7=>RA(7));
-    RA_6_I: RA_6_B
-      port map (PADDO=>RA_c_6, RA6=>RA(6));
-    RA_5_I: RA_5_B
-      port map (PADDO=>RA_c_5, RA5=>RA(5));
-    RA_4_I: RA_4_B
-      port map (PADDO=>RA_c_4, RA4=>RA(4));
-    RA_3_I: RA_3_B
-      port map (PADDO=>RA_c_3, RA3=>RA(3));
-    RA_2_I: RA_2_B
-      port map (PADDO=>RA_c_2, RA2=>RA(2));
-    RA_1_I: RA_1_B
-      port map (PADDO=>RA_c_1, RA1=>RA(1));
-    RA_0_I: RA_0_B
-      port map (PADDO=>RA_c_0, RA0=>RA(0));
-    RBA_1_I: RBA_1_B
-      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
-    RBA_0_I: RBA_0_B
-      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
-    LEDI: LEDB
-      port map (PADDO=>LED_c, LEDS=>LED);
-    nFWEI: nFWEB
-      port map (PADDI=>nFWE_c, nFWES=>nFWE);
-    nCRASI: nCRASB
-      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
-    nCCASI: nCCASB
-      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
-    Dout_7_I: Dout_7_B
-      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
-    Dout_6_I: Dout_6_B
-      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
-    Dout_5_I: Dout_5_B
-      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
-    Dout_4_I: Dout_4_B
-      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
-    Dout_3_I: Dout_3_B
-      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
-    Dout_2_I: Dout_2_B
-      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
-    Dout_1_I: Dout_1_B
-      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
-    Din_7_I: Din_7_B
-      port map (PADDI=>Din_c_7, Din7=>Din(7));
-    Din_6_I: Din_6_B
-      port map (PADDI=>Din_c_6, Din6=>Din(6));
-    Din_5_I: Din_5_B
-      port map (PADDI=>Din_c_5, Din5=>Din(5));
-    Din_4_I: Din_4_B
-      port map (PADDI=>Din_c_4, Din4=>Din(4));
-    Din_3_I: Din_3_B
-      port map (PADDI=>Din_c_3, Din3=>Din(3));
-    Din_2_I: Din_2_B
-      port map (PADDI=>Din_c_2, Din2=>Din(2));
-    Din_1_I: Din_1_B
-      port map (PADDI=>Din_c_1, Din1=>Din(1));
-    Din_0_I: Din_0_B
-      port map (PADDI=>Din_c_0, Din0=>Din(0));
-    CROW_1_I: CROW_1_B
-      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
-    CROW_0_I: CROW_0_B
-      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
-    MAin_9_I: MAin_9_B
-      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
-    MAin_8_I: MAin_8_B
-      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
-    MAin_7_I: MAin_7_B
-      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
-    MAin_6_I: MAin_6_B
-      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
-    MAin_5_I: MAin_5_B
-      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
-    MAin_4_I: MAin_4_B
-      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
-    MAin_3_I: MAin_3_B
-      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
-    MAin_2_I: MAin_2_B
-      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
-    MAin_1_I: MAin_1_B
-      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
-    MAin_0_I: MAin_0_B
-      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
-    VHI_INST: VHI
-      port map (Z=>VCCI);
-    PUR_INST: PUR
-      port map (PUR=>VCCI);
-    GSR_INST: GSR
-      port map (GSR=>VCCI);
-    VLO_INST: VLO
-      port map (Z=>GNDI_TSALL);
-    TSALL_INST: TSALL
-      port map (TSALL=>GNDI_TSALL);
-  end Structure;
-
-
-
-  library IEEE, vital2000, MACHXO;
-  configuration Structure_CON of RAM2GS is
-    for Structure
-    end for;
-  end Structure_CON;
-
-
+
+-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+-- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_vho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd 
+-- Netlist created on Sat Aug 19 20:57:13 2023
+-- Netlist written on Sat Aug 19 20:57:26 2023
+-- Design is for device LCMXO640C
+-- Design is for package TQFP100
+-- Design is for performance grade 3
+
+-- entity vmuxregsre
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
+
+  end vmuxregsre;
+
+  architecture Structure of vmuxregsre is
+    component FL1P3DX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3DX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity vcc
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vcc is
+    port (PWR1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
+
+  end vcc;
+
+  architecture Structure of vcc is
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VHI
+      port map (Z=>PWR1);
+  end Structure;
+
+-- entity gnd
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity gnd is
+    port (PWR0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
+
+  end gnd;
+
+  architecture Structure of gnd is
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+  begin
+    INST1: VLO
+      port map (Z=>PWR0);
+  end Structure;
+
+-- entity ccu2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu2B is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
+
+  end ccu2B;
+
+  architecture Structure of ccu2B is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_0
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_0 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_0";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
+
+  end SLICE_0;
+
+  architecture Structure of SLICE_0 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_0_FS_cry_0_0_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_0: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0, 
+                S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity ccu20001
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity ccu20001 is
+    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+          S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+          CO1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
+
+  end ccu20001;
+
+  architecture Structure of ccu20001 is
+    component CCU2
+      generic (INIT0: String; INIT1: String; INJECT1_0: String; 
+               INJECT1_1: String);
+      port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; 
+            C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; 
+            B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; 
+            COUT1: out Std_logic);
+    end component;
+  begin
+    inst1: CCU2
+      generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO", 
+                   INJECT1_1 => "NO")
+      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
+                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
+  end Structure;
+
+-- entity SLICE_1
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_1 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_1";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
+
+  end SLICE_1;
+
+  architecture Structure of SLICE_1 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_1_FS_cry_0_16_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu20001
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_17: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_16: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_16: ccu20001
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0, 
+                S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_2 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_2";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
+
+  end SLICE_2;
+
+  architecture Structure of SLICE_2 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_2_FS_cry_0_14_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_15: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_14: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_14: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0, 
+                S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_3
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_3 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_3";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
+
+  end SLICE_3;
+
+  architecture Structure of SLICE_3 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_3_FS_cry_0_12_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_13: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_12: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_12: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0, 
+                S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_4 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_4";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
+
+  end SLICE_4;
+
+  architecture Structure of SLICE_4 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_4_FS_cry_0_10_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_11: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_10: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_10: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0, 
+                S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_5
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_5 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_5";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
+
+  end SLICE_5;
+
+  architecture Structure of SLICE_5 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_5_FS_cry_0_8_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_9: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_8: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_8: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0, 
+                S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_6
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_6 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_6";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
+
+  end SLICE_6;
+
+  architecture Structure of SLICE_6 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_6_FS_cry_0_6_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_7: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_6: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_6: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0, 
+                S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_7
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_7 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_7";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
+
+  end SLICE_7;
+
+  architecture Structure of SLICE_7 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_7_FS_cry_0_4_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_5: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_4: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_4: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0, 
+                S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_8
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_8 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_8";
+
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_A1_CLK	: VitalDelayType := 0 ns;
+      tsetup_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_A0_CLK	: VitalDelayType := 0 ns;
+      tsetup_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_A0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_FCI_CLK	: VitalDelayType := 0 ns;
+      tsetup_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_FCI_CLK_noedge_posedge	: VitalDelayType := 0 ns);
+
+    port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+          FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+          FCO: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
+
+  end SLICE_8;
+
+  architecture Structure of SLICE_8 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal A1_ipd 	: std_logic := 'X';
+    signal A1_dly 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal A0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal FCI_ipd 	: std_logic := 'X';
+    signal FCI_dly 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+    signal FCO_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S1: Std_logic;
+    signal GNDI: Std_logic;
+    signal SLICE_8_FS_cry_0_2_S0: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component ccu2B
+      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
+            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
+            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
+            S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; 
+            CO1: out Std_logic);
+    end component;
+  begin
+    FS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    FS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI, 
+                CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
+    FS_cry_0_2: ccu2B
+      port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, 
+                C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0, 
+                S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
+      VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+      VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, 
+      FCO_out)
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE FCO_zd         	: std_logic := 'X';
+    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_A1_CLK       	: x01 := '0';
+    VARIABLE A1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_A0_CLK       	: x01 := '0';
+    VARIABLE A0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_FCI_CLK       	: x01 := '0';
+    VARIABLE FCI_CLK_TimingDatash	: VitalTimingDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => A1_dly,
+        TestSignalName => "A1",
+        TestDelay => tisd_A1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A1_CLK_noedge_posedge,
+        SetupLow => tsetup_A1_CLK_noedge_posedge,
+        HoldHigh => thold_A1_CLK_noedge_posedge,
+        HoldLow => thold_A1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A1_CLK_TimingDatash,
+        Violation => tviol_A1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => A0_dly,
+        TestSignalName => "A0",
+        TestDelay => tisd_A0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_A0_CLK_noedge_posedge,
+        SetupLow => tsetup_A0_CLK_noedge_posedge,
+        HoldHigh => thold_A0_CLK_noedge_posedge,
+        HoldLow => thold_A0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => A0_CLK_TimingDatash,
+        Violation => tviol_A0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => FCI_dly,
+        TestSignalName => "FCI",
+        TestDelay => tisd_FCI_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_FCI_CLK_noedge_posedge,
+        SetupLow => tsetup_FCI_CLK_noedge_posedge,
+        HoldHigh => thold_FCI_CLK_noedge_posedge,
+        HoldLow => thold_FCI_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => FCI_CLK_TimingDatash,
+        Violation => tviol_FCI_CLK,
+        MsgSeverity => warning);
+
+    END IF;
+
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+    FCO_zd 	:= FCO_out;
+
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
+      Paths      => (0 => (InputChangeTime => A1_dly'last_event,
+                           PathDelay => tpd_A1_FCO,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_dly'last_event,
+                           PathDelay => tpd_A0_FCO,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => FCI_dly'last_event,
+                           PathDelay => tpd_FCI_FCO,
+                           PathCondition => TRUE)),
+      GlitchData => FCO_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut4
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut4 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
+
+  end lut4;
+
+  architecture Structure of lut4 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40002
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40002 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
+
+  end lut40002;
+
+  architecture Structure of lut40002 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4544")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity inverter
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity inverter is
+    port (I: in Std_logic; Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
+
+  end inverter;
+
+  architecture Structure of inverter is
+    component INV
+      port (A: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    INST1: INV
+      port map (A=>I, Z=>Z);
+  end Structure;
+
+-- entity SLICE_9
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_9 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_9";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
+
+  end SLICE_9;
+
+  architecture Structure of SLICE_9 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut4
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40002
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2: lut4
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    ADSubmitted_r: lut40002
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    ADSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40003
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40003 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
+
+  end lut40003;
+
+  architecture Structure of lut40003 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8080")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40004
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40004 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
+
+  end lut40004;
+
+  architecture Structure of lut40004 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF2A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_14
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_14 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_14";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
+
+  end SLICE_14;
+
+  architecture Structure of SLICE_14 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40003
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40004
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2: lut40003
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    C1Submitted_RNO: lut40004
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    C1Submitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40005
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40005 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
+
+  end lut40005;
+
+  architecture Structure of lut40005 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40006
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40006 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
+
+  end lut40006;
+
+  architecture Structure of lut40006 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF5F5")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0007
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0007 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
+
+  end vmuxregsre0007;
+
+  architecture Structure of vmuxregsre0007 is
+    component FL1P3IY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3IY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_19
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_19 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_19";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
+
+  end SLICE_19;
+
+  architecture Structure of SLICE_19 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40005
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40006
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3_2: lut40005
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    S_RNO_0: lut40006
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, A0_ipd, 
+      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40008
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40008 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
+
+  end lut40008;
+
+  architecture Structure of lut40008 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40009
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40009 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
+
+  end lut40009;
+
+  architecture Structure of lut40009 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEA22")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity selmux2
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity selmux2 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
+
+  end selmux2;
+
+  architecture Structure of selmux2 is
+    component MUX21
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    INST1: MUX21
+      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
+  end Structure;
+
+-- entity SLICE_20
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_20 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_20";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          OFX0: out Std_logic; Q0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
+
+  end SLICE_20;
+
+  architecture Structure of SLICE_20 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal SLICE_20_SLICE_20_K1_H1: Std_logic;
+    signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40008
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40009
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    SLICE_20_K1: lut40008
+      port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, 
+                Z=>SLICE_20_SLICE_20_K1_H1);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable_s_GATE: lut40009
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>SLICE_20_CmdEnable_s_GATE_H0);
+    CmdEnable: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    SLICE_20_K0K1MUX: selmux2
+      port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1, 
+                SD=>M0_ipd, Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+    Q0_zd 	:= Q0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40010
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40010 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
+
+  end lut40010;
+
+  architecture Structure of lut40010 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40011
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40011 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
+
+  end lut40011;
+
+  architecture Structure of lut40011 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1011")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_21
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_21 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_21";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
+
+  end SLICE_21;
+
+  architecture Structure of SLICE_21 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40010
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40011
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_a2_2: lut40010
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_RNO: lut40011
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdLEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40012
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40012 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
+
+  end lut40012;
+
+  architecture Structure of lut40012 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40013
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40013 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
+
+  end lut40013;
+
+  architecture Structure of lut40013 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFAA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_22
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_22 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_22";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
+
+  end SLICE_22;
+
+  architecture Structure of SLICE_22 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40012
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2: lut40012
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_RNO: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdSubmitted: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40014
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40014 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
+
+  end lut40014;
+
+  architecture Structure of lut40014 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x33AB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40015
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40015 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
+
+  end lut40015;
+
+  architecture Structure of lut40015 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0F05")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_26
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_26 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_26";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
+
+  end SLICE_26;
+
+  architecture Structure of SLICE_26 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40014
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40015
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_0: lut40014
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Cmdn8MEGEN_RNO: lut40015
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Cmdn8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40016
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40016 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
+
+  end lut40016;
+
+  architecture Structure of lut40016 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCFCE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40017
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40017 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
+
+  end lut40017;
+
+  architecture Structure of lut40017 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xA9A9")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_29
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_29 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_29";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
+
+  end SLICE_29;
+
+  architecture Structure of SLICE_29 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40016
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40017
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i: lut40016
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_0: lut40017
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_0: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40018
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40018 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
+
+  end lut40018;
+
+  architecture Structure of lut40018 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5AF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40019
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40019 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
+
+  end lut40019;
+
+  architecture Structure of lut40019 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x55AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_30
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_30 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_30";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI1_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
+
+  end SLICE_30;
+
+  architecture Structure of SLICE_30 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI1_ipd 	: std_logic := 'X';
+    signal DI1_dly 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40018
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40019
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_RNO_2: lut40018
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    IS_n1_0_x2: lut40019
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    IS_2: vmuxregsre
+      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    IS_1: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI1_CLK       	: x01 := '0';
+    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI1_dly,
+        TestSignalName => "DI1",
+        TestDelay => tisd_DI1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
+        SetupLow => tsetup_DI1_CLK_noedge_posedge,
+        HoldHigh => thold_DI1_CLK_noedge_posedge,
+        HoldLow => thold_DI1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI1_CLK_TimingDatash,
+        Violation => tviol_DI1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40020
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40020 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
+
+  end lut40020;
+
+  architecture Structure of lut40020 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40021
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40021 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
+
+  end lut40021;
+
+  architecture Structure of lut40021 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x78F0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_31
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_31 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_31";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
+
+  end SLICE_31;
+
+  architecture Structure of SLICE_31 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40020
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40021
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RA10_RNO: lut40020
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_RNO_3: lut40021
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    IS_3: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40022
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40022 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
+
+  end lut40022;
+
+  architecture Structure of lut40022 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0B0F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_32
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_32 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_32";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
+
+  end SLICE_32;
+
+  architecture Structure of SLICE_32 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40013
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40022
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a0: lut40022
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady_RNO: lut40013
+      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, A0_ipd, 
+      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40023
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40023 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
+
+  end lut40023;
+
+  architecture Structure of lut40023 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFAFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40024
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40024 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
+
+  end lut40024;
+
+  architecture Structure of lut40024 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCC55")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_33
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_33 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_33";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
+
+  end SLICE_33;
+
+  architecture Structure of SLICE_33 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40023
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40024
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    LED_pad_RNO: lut40023
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    LEDEN_5_i_m2: lut40024
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    LEDEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40025
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40025 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
+
+  end lut40025;
+
+  architecture Structure of lut40025 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3300")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40026
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40026 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
+
+  end lut40026;
+
+  architecture Structure of lut40026 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBB44")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_39
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_39 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_39";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
+
+  end SLICE_39;
+
+  architecture Structure of SLICE_39 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40025
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40026
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_0: lut40025
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RA11_2: lut40026
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    RA11: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40027
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40027 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
+
+  end lut40027;
+
+  architecture Structure of lut40027 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x75A5")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40028
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40028 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
+
+  end lut40028;
+
+  architecture Structure of lut40028 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xAAEA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_41
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_41 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_41";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
+
+  end SLICE_41;
+
+  architecture Structure of SLICE_41 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40027
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40028
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_1_0: lut40027
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKEEN_8_u: lut40028
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40029
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40029 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
+
+  end lut40029;
+
+  architecture Structure of lut40029 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0008")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40030
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40030 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
+
+  end lut40030;
+
+  architecture Structure of lut40030 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDCD8")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_42
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_42 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_42";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
+
+  end SLICE_42;
+
+  architecture Structure of SLICE_42 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40029
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40030
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_5: lut40029
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    RCKE_2_0: lut40030
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKE: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40031
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40031 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
+
+  end lut40031;
+
+  architecture Structure of lut40031 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x03AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40032
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40032 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
+
+  end lut40032;
+
+  architecture Structure of lut40032 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF08")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_43
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_43 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_43";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
+
+  end SLICE_43;
+
+  architecture Structure of SLICE_43 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40031
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40032
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RCKEEN_8_u_RNO: lut40031
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_RNO: lut40032
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    PHI2r3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40033
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40033 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
+
+  end lut40033;
+
+  architecture Structure of lut40033 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0008")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40034
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40034 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
+
+  end lut40034;
+
+  architecture Structure of lut40034 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEEEE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_44
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_44 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_44";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
+
+  end SLICE_44;
+
+  architecture Structure of SLICE_44 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40033
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Ready_0_sqmuxa_0_a3: lut40033
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    Ready_fast_RNO: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RASr: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Ready_fast: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40035
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40035 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
+
+  end lut40035;
+
+  architecture Structure of lut40035 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0500")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40036
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40036 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
+
+  end lut40036;
+
+  architecture Structure of lut40036 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFAFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_50
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_50 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_50";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
+
+  end SLICE_50;
+
+  architecture Structure of SLICE_50 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40035
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40036
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_RNO: lut40035
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    S_0_i_o2_1: lut40036
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    S_1: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI0_dly, 
+      LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40037
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40037 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
+
+  end lut40037;
+
+  architecture Structure of lut40037 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xABFB")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40038
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40038 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
+
+  end lut40038;
+
+  architecture Structure of lut40038 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0322")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_51
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_51 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_51";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
+
+  end SLICE_51;
+
+  architecture Structure of SLICE_51 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40037
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40038
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMCLK_RNO_0: lut40037
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMCLK_RNO: lut40038
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40039
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40039 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
+
+  end lut40039;
+
+  architecture Structure of lut40039 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2F0F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40040
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40040 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
+
+  end lut40040;
+
+  architecture Structure of lut40040 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5404")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_52
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_52 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_52";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
+
+  end SLICE_52;
+
+  architecture Structure of SLICE_52 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40039
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40040
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    PHI2r3_RNITCN41: lut40039
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_RNO: lut40040
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RASr3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMSDI: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40041
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40041 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
+
+  end lut40041;
+
+  architecture Structure of lut40041 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBB88")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_55
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_55 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_55";
+
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
+
+  end SLICE_55;
+
+  architecture Structure of SLICE_55 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_4: lut40041
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, 
+      F0_out, Q0_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40042
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40042 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
+
+  end lut40042;
+
+  architecture Structure of lut40042 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40043
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40043 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
+
+  end lut40043;
+
+  architecture Structure of lut40043 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5A0A")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_56
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_56 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_56";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
+
+  end SLICE_56;
+
+  architecture Structure of SLICE_56 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40042
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40043
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_11: lut40042
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    UFMSDI_ens2_i_o2: lut40043
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    WRD_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40044
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40044 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
+
+  end lut40044;
+
+  architecture Structure of lut40044 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40045
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40045 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
+
+  end lut40045;
+
+  architecture Structure of lut40045 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xBAFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_57
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_57 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_57";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
+
+  end SLICE_57;
+
+  architecture Structure of SLICE_57 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40044
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40045
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    XOR8MEG_3_u_0_a3_2: lut40044
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG_3_u_0_a3_3: lut40045
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    XOR8MEG: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
+        SetupLow => tsetup_DI0_CLK_noedge_negedge,
+        HoldHigh => thold_DI0_CLK_noedge_negedge,
+        HoldLow => thold_DI0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40046
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40046 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
+
+  end lut40046;
+
+  architecture Structure of lut40046 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0005")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40047
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40047 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
+
+  end lut40047;
+
+  architecture Structure of lut40047 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x88DD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_58
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_58 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_58";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
+
+  end SLICE_58;
+
+  architecture Structure of SLICE_58 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40046
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40047
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_en_ss0_0_a2_0: lut40046
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    n8MEGEN_5_i_m2: lut40047
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+    n8MEGEN: vmuxregsre
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_posedge,
+        SetupLow => tsetup_CE_CLK_noedge_posedge,
+        HoldHigh => thold_CE_CLK_noedge_posedge,
+        HoldLow => thold_CE_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40048
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40048 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
+
+  end lut40048;
+
+  architecture Structure of lut40048 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0FDD")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40049
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40049 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
+
+  end lut40049;
+
+  architecture Structure of lut40049 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0F04")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0050
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0050 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0050 : ENTITY IS TRUE;
+
+  end vmuxregsre0050;
+
+  architecture Structure of vmuxregsre0050 is
+    component FL1P3BX
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3BX
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_59
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_59 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_59";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
+
+  end SLICE_59;
+
+  architecture Structure of SLICE_59 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40048
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40049
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0050
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_0: lut40048
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCAS_RNO: lut40049
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCAS: vmuxregsre0050
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40051
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40051 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
+
+  end lut40051;
+
+  architecture Structure of lut40051 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFC7C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40052
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40052 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
+
+  end lut40052;
+
+  architecture Structure of lut40052 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3323")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_60
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_60 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_60";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
+
+  end SLICE_60;
+
+  architecture Structure of SLICE_60 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0050
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40051
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40052
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCS_RNO_0: lut40051
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRCS_RNO: lut40052
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRCS: vmuxregsre0050
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40053
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40053 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
+
+  end lut40053;
+
+  architecture Structure of lut40053 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00E0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40054
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40054 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
+
+  end lut40054;
+
+  architecture Structure of lut40054 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3031")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_61
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_61 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_61";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
+
+  end SLICE_61;
+
+  architecture Structure of SLICE_61 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0050
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40053
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40054
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRRAS_5_u_i_0: lut40053
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRRAS_RNO: lut40054
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRRAS: vmuxregsre0050
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40055
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40055 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
+
+  end lut40055;
+
+  architecture Structure of lut40055 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40056
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40056 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
+
+  end lut40056;
+
+  architecture Structure of lut40056 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCDEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_62
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_62 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_62";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
+
+  end SLICE_62;
+
+  architecture Structure of SLICE_62 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0050
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40055
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40056
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_0_sqmuxa_1_0_a3: lut40055
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRWE_RNO: lut40056
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRWE: vmuxregsre0050
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40057
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40057 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
+
+  end lut40057;
+
+  architecture Structure of lut40057 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0040")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40058
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40058 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
+
+  end lut40058;
+
+  architecture Structure of lut40058 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF60")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_63
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_63 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_63";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
+
+  end SLICE_63;
+
+  architecture Structure of SLICE_63 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40057
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40058
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRowColSel_0_0_a3_0: lut40057
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nRowColSel_0_0: lut40058
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nRowColSel: vmuxregsre0007
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40059
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40059 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
+
+  end lut40059;
+
+  architecture Structure of lut40059 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40060
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40060 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
+
+  end lut40060;
+
+  architecture Structure of lut40060 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDFCE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_64
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_64 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_64";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_DI0_CLK	: VitalDelayType := 0 ns;
+      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
+
+  end SLICE_64;
+
+  architecture Structure of SLICE_64 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal DI0_ipd 	: std_logic := 'X';
+    signal DI0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component vmuxregsre0050
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40059
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40060
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS15_0_a2: lut40059
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    nUFMCS_s_0_N_5_i: lut40060
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    nUFMCS: vmuxregsre0050
+      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_DI0_CLK       	: x01 := '0';
+    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => DI0_dly,
+        TestSignalName => "DI0",
+        TestDelay => tisd_DI0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
+        SetupLow => tsetup_DI0_CLK_noedge_posedge,
+        HoldHigh => thold_DI0_CLK_noedge_posedge,
+        HoldLow => thold_DI0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => DI0_CLK_TimingDatash,
+        Violation => tviol_DI0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40061
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40061 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
+
+  end lut40061;
+
+  architecture Structure of lut40061 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40062
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40062 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
+
+  end lut40062;
+
+  architecture Structure of lut40062 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity nRWE_RNO_1_SLICE_65
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWE_RNO_1_SLICE_65 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWE_RNO_1_SLICE_65";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          OFX0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
+
+  end nRWE_RNO_1_SLICE_65;
+
+  architecture Structure of nRWE_RNO_1_SLICE_65 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal OFX0_out 	: std_logic := 'X';
+
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
+    signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
+    component selmux2
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40061
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40062
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_1_SLICE_65_K1: lut40061
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
+    nRWE_RNO_1_GATE: lut40062
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
+                Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
+    nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
+      port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0, 
+                D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd, 
+                Z=>OFX0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_ipd, OFX0_out)
+    VARIABLE OFX0_zd         	: std_logic := 'X';
+    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    OFX0_zd 	:= OFX0_out;
+
+    VitalPathDelay01 (
+      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_OFX0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_OFX0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_OFX0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_OFX0,
+                           PathCondition => TRUE),
+                     4 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_OFX0,
+                           PathCondition => TRUE),
+                     5 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_OFX0,
+                           PathCondition => TRUE),
+                     6 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_OFX0,
+                           PathCondition => TRUE),
+                     7 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_OFX0,
+                           PathCondition => TRUE),
+                     8 => (InputChangeTime => M0_ipd'last_event,
+                           PathDelay => tpd_M0_OFX0,
+                           PathCondition => TRUE)),
+      GlitchData => OFX0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40063
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40063 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
+
+  end lut40063;
+
+  architecture Structure of lut40063 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4545")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40064
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40064 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
+
+  end lut40064;
+
+  architecture Structure of lut40064 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_66
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_66 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_66";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
+
+  end SLICE_66;
+
+  architecture Structure of SLICE_66 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40063
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40064
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nUFMCS_s_0_N_5_i_N_2L1: lut40063
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_a2_2_2: lut40064
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40065
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40065 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
+
+  end lut40065;
+
+  architecture Structure of lut40065 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40066
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40066 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
+
+  end lut40066;
+
+  architecture Structure of lut40066 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0080")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity vmuxregsre0067
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity vmuxregsre0067 is
+    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+          Q: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF vmuxregsre0067 : ENTITY IS TRUE;
+
+  end vmuxregsre0067;
+
+  architecture Structure of vmuxregsre0067 is
+    component FL1P3JY
+      generic (GSR: String);
+      port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; 
+            CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    INST01: FL1P3JY
+      generic map (GSR => "DISABLED")
+      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
+  end Structure;
+
+-- entity SLICE_67
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_67 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_67";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
+
+  end SLICE_67;
+
+  architecture Structure of SLICE_67 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40065
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40066
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component vmuxregsre0067
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+  begin
+    CmdUFMCLK_1_sqmuxa_0_a2: lut40065
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    XOR8MEG18_0_a2: lut40066
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_5: vmuxregsre0067
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_4: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, 
+      Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40068
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40068 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
+
+  end lut40068;
+
+  architecture Structure of lut40068 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40069
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40069 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
+
+  end lut40069;
+
+  architecture Structure of lut40069 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFF80")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_68
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_68 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_68";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
+
+  end SLICE_68;
+
+  architecture Structure of SLICE_68 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40068
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40069
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_14_i_a2_0_1: lut40068
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_14_i_0: lut40069
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40070
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40070 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
+
+  end lut40070;
+
+  architecture Structure of lut40070 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0002")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40071
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40071 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
+
+  end lut40071;
+
+  architecture Structure of lut40071 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xECCC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_69
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_69 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_69";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
+
+  end SLICE_69;
+
+  architecture Structure of SLICE_69 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40070
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40071
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_FS_13_i_a2_1: lut40070
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_0: lut40071
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40072
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40072 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
+
+  end lut40072;
+
+  architecture Structure of lut40072 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40073
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40073 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
+
+  end lut40073;
+
+  architecture Structure of lut40073 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xC0C0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_70
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_70 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_70";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
+
+  end SLICE_70;
+
+  architecture Structure of SLICE_70 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40072
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40073
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0: lut40072
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2: lut40073
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40074
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40074 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
+
+  end lut40074;
+
+  architecture Structure of lut40074 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40075
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40075 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
+
+  end lut40075;
+
+  architecture Structure of lut40075 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_71
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_71 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_71";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
+
+  end SLICE_71;
+
+  architecture Structure of SLICE_71 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40074
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40075
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_4: lut40074
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    C1WR_0_a2_0_10: lut40075
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Bank_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40076
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40076 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
+
+  end lut40076;
+
+  architecture Structure of lut40076 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40077
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40077 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
+
+  end lut40077;
+
+  architecture Structure of lut40077 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF808")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_72
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_72 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_72";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
+
+  end SLICE_72;
+
+  architecture Structure of SLICE_72 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40076
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40077
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0: lut40076
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    UFMCLK_r_i_m2: lut40077
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_3: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_2: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40078
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40078 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
+
+  end lut40078;
+
+  architecture Structure of lut40078 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFDF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_73
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_73 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_73";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
+
+  end SLICE_73;
+
+  architecture Structure of SLICE_73 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40034
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40078
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0: lut40078
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    IS_0_sqmuxa_0_o2: lut40034
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdUFMCS: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CmdUFMCLK: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40079
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40079 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
+
+  end lut40079;
+
+  architecture Structure of lut40079 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCC00")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40080
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40080 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
+
+  end lut40080;
+
+  architecture Structure of lut40080 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_74
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_74 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_74";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_CE_CLK	: VitalDelayType := 0 ns;
+      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
+
+  end SLICE_74;
+
+  architecture Structure of SLICE_74 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CE_ipd 	: std_logic := 'X';
+    signal CE_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40079
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40080
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    InitReady3_0_a2_3: lut40079
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    InitReady3_0_a2: lut40080
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CmdUFMSDI: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CE_ipd, CE, tipd_CE);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CE_CLK       	: x01 := '0';
+    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => CE_dly,
+        TestSignalName => "CE",
+        TestDelay => tisd_CE_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_CE_CLK_noedge_negedge,
+        SetupLow => tsetup_CE_CLK_noedge_negedge,
+        HoldHigh => thold_CE_CLK_noedge_negedge,
+        HoldLow => thold_CE_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => CE_CLK_TimingDatash,
+        Violation => tviol_CE_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40081
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40081 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
+
+  end lut40081;
+
+  architecture Structure of lut40081 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xEFEF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40082
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40082 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
+
+  end lut40082;
+
+  architecture Structure of lut40082 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0005")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_75
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_75 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_75";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
+
+  end SLICE_75;
+
+  architecture Structure of SLICE_75 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40081
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40082
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    Cmdn8MEGEN_4_u_i_o2_0: lut40081
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdLEDEN_4_u_i_a2_0: lut40082
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr2: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CASr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40083
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40083 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
+
+  end lut40083;
+
+  architecture Structure of lut40083 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40084
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40084 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
+
+  end lut40084;
+
+  architecture Structure of lut40084 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0010")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_76
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_76 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_76";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
+
+  end SLICE_76;
+
+  architecture Structure of SLICE_76 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40083
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40084
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_4: lut40083
+      port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_4_0: lut40084
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_5: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_4: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40085
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40085 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
+
+  end lut40085;
+
+  architecture Structure of lut40085 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5050")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40086
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40086 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
+
+  end lut40086;
+
+  architecture Structure of lut40086 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x4000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_77
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_77 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_77";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
+
+  end SLICE_77;
+
+  architecture Structure of SLICE_77 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40085
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40086
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable16_0_a2_1: lut40085
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable16_0_a2_5: lut40086
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    Bank_7: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    Bank_6: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_posedge,
+        SetupLow => tsetup_M1_CLK_noedge_posedge,
+        HoldHigh => thold_M1_CLK_noedge_posedge,
+        HoldLow => thold_M1_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40087
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40087 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
+
+  end lut40087;
+
+  architecture Structure of lut40087 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3F3F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40088
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40088 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
+
+  end lut40088;
+
+  architecture Structure of lut40088 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0200")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_78
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_78 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_78";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
+
+  end SLICE_78;
+
+  architecture Structure of SLICE_78 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40087
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40088
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_o2: lut40087
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CmdEnable17_0_a2_4: lut40088
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CBR_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    CBR: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40089
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40089 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
+
+  end lut40089;
+
+  architecture Structure of lut40089 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00C0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40090
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40090 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
+
+  end lut40090;
+
+  architecture Structure of lut40090 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x2000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_79
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_79 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_79";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
+
+  end SLICE_79;
+
+  architecture Structure of SLICE_79 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40089
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40090
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRWE_RNO_2: lut40089
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRWE_RNO_0: lut40090
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_1: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_0: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40091
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40091 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
+
+  end lut40091;
+
+  architecture Structure of lut40091 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x3030")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40092
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40092 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
+
+  end lut40092;
+
+  architecture Structure of lut40092 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0805")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_80
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_80 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_80";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
+
+  end SLICE_80;
+
+  architecture Structure of SLICE_80 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vmuxregsre0067
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40091
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40092
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    nRCAS_RNO_1: lut40091
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nRCAS_RNO_0: lut40092
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_9: vmuxregsre0067
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_8: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40093
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40093 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
+
+  end lut40093;
+
+  architecture Structure of lut40093 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40094
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40094 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
+
+  end lut40094;
+
+  architecture Structure of lut40094 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x8000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_81
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_81 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_81";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
+
+  end SLICE_81;
+
+  architecture Structure of SLICE_81 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal M1_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40093
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40094
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_o2_0_3: lut40093
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    InitReady3_0_a2_5: lut40094
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    FWEr_fast: vmuxregsre
+      port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    M1_INVERTERIN: inverter
+      port map (I=>M1_dly, Z=>M1_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    FWEr: vmuxregsre
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40095
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40095 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
+
+  end lut40095;
+
+  architecture Structure of lut40095 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0E0C")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40096
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40096 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
+
+  end lut40096;
+
+  architecture Structure of lut40096 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x1030")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_82
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_82 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_82";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
+
+  end SLICE_82;
+
+  architecture Structure of SLICE_82 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40095
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40096
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdLEDEN_4_u_i_a2: lut40095
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    CmdSubmitted_1_sqmuxa_0_a2: lut40096
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    CASr3: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>GNDI, Q=>Q0_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40097
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40097 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
+
+  end lut40097;
+
+  architecture Structure of lut40097 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFEFE")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40098
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40098 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
+
+  end lut40098;
+
+  architecture Structure of lut40098 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5FFF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_83
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_83 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_83";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+          M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
+
+  end SLICE_83;
+
+  architecture Structure of SLICE_83 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40097
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40098
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_nRCAS_6_sqmuxa_i_o2: lut40097
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    Ready_0_sqmuxa_0_o2: lut40098
+      port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RBA_1: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RBA_0: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, 
+      M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40099
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40099 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
+
+  end lut40099;
+
+  architecture Structure of lut40099 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0008")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40100
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40100 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
+
+  end lut40100;
+
+  architecture Structure of lut40100 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0004")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_84
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_84 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_84";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
+
+  end SLICE_84;
+
+  architecture Structure of SLICE_84 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    component lut40099
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40100
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_ens2_i_a2_4_2: lut40099
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_FS_13_i_a2_6: lut40100
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40101
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40101 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
+
+  end lut40101;
+
+  architecture Structure of lut40101 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0020")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40102
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40102 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
+
+  end lut40102;
+
+  architecture Structure of lut40102 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0001")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_85
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_85 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_85";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+          Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
+
+  end SLICE_85;
+
+  architecture Structure of SLICE_85 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal VCCI: Std_logic;
+    signal GNDI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    component vmuxregsre
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component lut40101
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40102
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    CmdEnable17_0_a2_3: lut40101
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    un1_Din_4: lut40102
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    WRD_3: vmuxregsre
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    WRD_2: vmuxregsre
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>GNDI, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
+      B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40103
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40103 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
+
+  end lut40103;
+
+  architecture Structure of lut40103 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x5F5F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40104
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40104 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
+
+  end lut40104;
+
+  architecture Structure of lut40104 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xE4E4")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_86
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_86 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_86";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
+
+  end SLICE_86;
+
+  architecture Structure of SLICE_86 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40103
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40104
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQML: lut40103
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_9: lut40104
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40105
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40105 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE;
+
+  end lut40105;
+
+  architecture Structure of lut40105 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x00FC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40106
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40106 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
+
+  end lut40106;
+
+  architecture Structure of lut40106 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0800")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_87
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_87 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_87";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
+
+  end SLICE_87;
+
+  architecture Structure of SLICE_87 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40105
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40106
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    UFMSDI_RNO_0: lut40105
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un1_FS_13_i_a2_8: lut40106
+      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      A0_ipd, F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     3 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40107
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40107 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
+
+  end lut40107;
+
+  architecture Structure of lut40107 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x0808")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40108
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40108 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
+
+  end lut40108;
+
+  architecture Structure of lut40108 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xFFF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_88
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_88 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_88";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns;
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M1_CLK	: VitalDelayType := 0 ns;
+      tsetup_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_negedge	: VitalDelayType := 0 ns);
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; M1: in Std_logic; 
+          M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+          Q1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
+
+  end SLICE_88;
+
+  architecture Structure of SLICE_88 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M1_ipd 	: std_logic := 'X';
+    signal M1_dly 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+    signal Q1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal VCCI: Std_logic;
+    signal CLK_NOTIN: Std_logic;
+    signal LSR_NOTIN: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0007
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40107
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40108
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    C1WR_0_a2_0_3: lut40107
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    nCCAS_pad_RNI01SJ: lut40108
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RowA_7: vmuxregsre0007
+      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q1_out);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+    CLK_INVERTERIN: inverter
+      port map (I=>CLK_dly, Z=>CLK_NOTIN);
+    LSR_INVERTERIN: inverter
+      port map (I=>LSR_dly, Z=>LSR_NOTIN);
+    RowA_6: vmuxregsre0007
+      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
+                LSR=>LSR_NOTIN, Q=>Q0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M1_ipd, M1, tipd_M1);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, M1_dly, 
+      M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q1_zd         	: std_logic := 'X';
+    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M1_CLK       	: x01 := '0';
+    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M1_dly,
+        TestSignalName => "M1",
+        TestDelay => tisd_M1_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M1_CLK_noedge_negedge,
+        SetupLow => tsetup_M1_CLK_noedge_negedge,
+        HoldHigh => thold_M1_CLK_noedge_negedge,
+        HoldLow => thold_M1_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M1_CLK_TimingDatash,
+        Violation => tviol_M1_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_negedge,
+        SetupLow => tsetup_M0_CLK_noedge_negedge,
+        HoldHigh => thold_M0_CLK_noedge_negedge,
+        HoldLow => thold_M0_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_negedge,
+        SetupLow => tsetup_LSR_CLK_noedge_negedge,
+        HoldHigh => thold_LSR_CLK_noedge_negedge,
+        HoldLow => thold_LSR_CLK_noedge_negedge,
+        CheckEnabled => TRUE,
+        RefTransition => '\',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+    Q1_zd 	:= Q1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q1,
+                           PathCondition => TRUE)),
+      GlitchData => Q1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40109
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40109 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
+
+  end lut40109;
+
+  architecture Structure of lut40109 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF0FF")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40110
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40110 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE;
+
+  end lut40110;
+
+  architecture Structure of lut40110 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF0CC")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_89
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_89 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_89";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
+
+  end SLICE_89;
+
+  architecture Structure of SLICE_89 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40109
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40110
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    RDQMH: lut40109
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_8: lut40110
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, F0_out, 
+      F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40111
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40111 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE;
+
+  end lut40111;
+
+  architecture Structure of lut40111 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xE0E0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40112
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40112 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE;
+
+  end lut40112;
+
+  architecture Structure of lut40112 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xDD88")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_90
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_90 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_90";
+
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
+
+  end SLICE_90;
+
+  architecture Structure of SLICE_90 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40111
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40112
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un1_CMDWR: lut40111
+      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_0: lut40112
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40113
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40113 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE;
+
+  end lut40113;
+
+  architecture Structure of lut40113 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCCF0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40114
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40114 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE;
+
+  end lut40114;
+
+  architecture Structure of lut40114 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xCFC0")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_91
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_91 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_91";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
+
+  end SLICE_91;
+
+  architecture Structure of SLICE_91 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40113
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40114
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_7: lut40113
+      port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_1: lut40114
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40115
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40115 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE;
+
+  end lut40115;
+
+  architecture Structure of lut40115 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF0AA")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_92
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_92 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_92";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
+
+  end SLICE_92;
+
+  architecture Structure of SLICE_92 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40113
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40115
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_6: lut40115
+      port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_2: lut40113
+      port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity SLICE_93
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_93 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_93";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
+
+    port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+          D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+          F0: out Std_logic; F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
+
+  end SLICE_93;
+
+  architecture Structure of SLICE_93 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal B1_ipd 	: std_logic := 'X';
+    signal A1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal B0_ipd 	: std_logic := 'X';
+    signal A0_ipd 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component lut40041
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    un9_RA_5: lut40041
+      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    un9_RA_3: lut40041
+      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(B1_ipd, B1, tipd_B1);
+      VitalWireDelay(A1_ipd, A1, tipd_A1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(B0_ipd, B0, tipd_B0);
+      VitalWireDelay(A0_ipd, A0, tipd_A0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, 
+      F0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B0_ipd'last_event,
+                           PathDelay => tpd_B0_F0,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A0_ipd'last_event,
+                           PathDelay => tpd_A0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => B1_ipd'last_event,
+                           PathDelay => tpd_B1_F1,
+                           PathCondition => TRUE),
+                     2 => (InputChangeTime => A1_ipd'last_event,
+                           PathDelay => tpd_A1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity lut40116
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40116 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE;
+
+  end lut40116;
+
+  architecture Structure of lut40116 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0x000F")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity lut40117
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity lut40117 is
+    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+          Z: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF lut40117 : ENTITY IS TRUE;
+
+  end lut40117;
+
+  architecture Structure of lut40117 is
+    component ROM16X1
+      generic (initval: String);
+      port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; 
+            AD3: in Std_logic; DO0: out Std_logic);
+    end component;
+  begin
+    INST10: ROM16X1
+      generic map (initval => "0xF000")
+      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
+  end Structure;
+
+-- entity SLICE_94
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity SLICE_94 is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "SLICE_94";
+
+      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
+      ticd_CLK	: VitalDelayType := 0 ns;
+      tisd_M0_CLK	: VitalDelayType := 0 ns;
+      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tisd_LSR_CLK	: VitalDelayType := 0 ns;
+      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
+      tperiod_CLK 	: VitalDelayType := 0 ns;
+      tpw_CLK_posedge	: VitalDelayType := 0 ns;
+      tpw_CLK_negedge	: VitalDelayType := 0 ns);
+
+    port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+          C0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+          F1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
+
+  end SLICE_94;
+
+  architecture Structure of SLICE_94 is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal D1_ipd 	: std_logic := 'X';
+    signal C1_ipd 	: std_logic := 'X';
+    signal D0_ipd 	: std_logic := 'X';
+    signal C0_ipd 	: std_logic := 'X';
+    signal M0_ipd 	: std_logic := 'X';
+    signal M0_dly 	: std_logic := 'X';
+    signal LSR_ipd 	: std_logic := 'X';
+    signal LSR_dly 	: std_logic := 'X';
+    signal CLK_ipd 	: std_logic := 'X';
+    signal CLK_dly 	: std_logic := 'X';
+    signal F0_out 	: std_logic := 'X';
+    signal Q0_out 	: std_logic := 'X';
+    signal F1_out 	: std_logic := 'X';
+
+    signal GNDI: Std_logic;
+    signal M0_NOTIN: Std_logic;
+    signal VCCI: Std_logic;
+    component vcc
+      port (PWR1: out Std_logic);
+    end component;
+    component gnd
+      port (PWR0: out Std_logic);
+    end component;
+    component inverter
+      port (I: in Std_logic; Z: out Std_logic);
+    end component;
+    component vmuxregsre0067
+      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
+            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
+            Q: out Std_logic);
+    end component;
+    component lut40116
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+    component lut40117
+      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
+            Z: out Std_logic);
+    end component;
+  begin
+    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40116
+      port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
+    DRIVEGND: gnd
+      port map (PWR0=>GNDI);
+    RCKEEN_8_u_0_a2_1_s: lut40117
+      port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
+    RA10: vmuxregsre0067
+      port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
+                LSR=>LSR_dly, Q=>Q0_out);
+    M0_INVERTERIN: inverter
+      port map (I=>M0_dly, Z=>M0_NOTIN);
+    DRIVEVCC: vcc
+      port map (PWR1=>VCCI);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(D1_ipd, D1, tipd_D1);
+      VitalWireDelay(C1_ipd, C1, tipd_C1);
+      VitalWireDelay(D0_ipd, D0, tipd_D0);
+      VitalWireDelay(C0_ipd, C0, tipd_C0);
+      VitalWireDelay(M0_ipd, M0, tipd_M0);
+      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
+      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
+    END BLOCK;
+
+    --  Setup and Hold DELAYs
+    SignalDelay : BLOCK
+    BEGIN
+      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
+      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
+      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, M0_dly, LSR_dly, 
+      CLK_dly, F0_out, Q0_out, F1_out)
+    VARIABLE F0_zd         	: std_logic := 'X';
+    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE Q0_zd         	: std_logic := 'X';
+    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
+    VARIABLE F1_zd         	: std_logic := 'X';
+    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_M0_CLK       	: x01 := '0';
+    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_LSR_CLK       	: x01 := '0';
+    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
+    VARIABLE tviol_CLK_CLK          	: x01 := '0';
+    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalSetupHoldCheck (
+        TestSignal => M0_dly,
+        TestSignalName => "M0",
+        TestDelay => tisd_M0_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_M0_CLK_noedge_posedge,
+        SetupLow => tsetup_M0_CLK_noedge_posedge,
+        HoldHigh => thold_M0_CLK_noedge_posedge,
+        HoldLow => thold_M0_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => M0_CLK_TimingDatash,
+        Violation => tviol_M0_CLK,
+        MsgSeverity => warning);
+      VitalSetupHoldCheck (
+        TestSignal => LSR_dly,
+        TestSignalName => "LSR",
+        TestDelay => tisd_LSR_CLK,
+        RefSignal => CLK_dly,
+        RefSignalName => "CLK",
+        RefDelay => ticd_CLK,
+        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
+        SetupLow => tsetup_LSR_CLK_noedge_posedge,
+        HoldHigh => thold_LSR_CLK_noedge_posedge,
+        HoldLow => thold_LSR_CLK_noedge_posedge,
+        CheckEnabled => TRUE,
+        RefTransition => '/',
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        TimingData => LSR_CLK_TimingDatash,
+        Violation => tviol_LSR_CLK,
+        MsgSeverity => warning);
+      VitalPeriodPulseCheck (
+        TestSignal => CLK_ipd,
+        TestSignalName => "CLK",
+        Period => tperiod_CLK,
+        PulseWidthHigh => tpw_CLK_posedge,
+        PulseWidthLow => tpw_CLK_negedge,
+        PeriodData => periodcheckinfo_CLK,
+        Violation => tviol_CLK_CLK,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    F0_zd 	:= F0_out;
+    Q0_zd 	:= Q0_out;
+    F1_zd 	:= F1_out;
+
+    VitalPathDelay01 (
+      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
+      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
+                           PathDelay => tpd_D0_F0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C0_ipd'last_event,
+                           PathDelay => tpd_C0_F0,
+                           PathCondition => TRUE)),
+      GlitchData => F0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
+      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
+                           PathDelay => tpd_CLK_Q0,
+                           PathCondition => TRUE)),
+      GlitchData => Q0_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01 (
+      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
+      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
+                           PathDelay => tpd_D1_F1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => C1_ipd'last_event,
+                           PathDelay => tpd_C1_F1,
+                           PathCondition => TRUE)),
+      GlitchData => F1_GlitchData,
+      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf is
+    port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+          PAD: out Std_logic; PADI: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
+
+  end mjiobuf;
+
+  architecture Structure of mjiobuf is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+    component OBW
+      port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PADI, O=>Z);
+    INST2: OBW
+      port map (I=>I, T=>T, O=>PAD);
+  end Structure;
+
+-- entity RD_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_0_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD0 	: VitalDelayType := 0 ns;
+      tpw_RD0_posedge	: VitalDelayType := 0 ns;
+      tpw_RD0_negedge	: VitalDelayType := 0 ns;
+      tpd_RD0_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD0: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
+
+  end RD_0_B;
+
+  architecture Structure of RD_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD0_ipd 	: std_logic := 'X';
+    signal RD0_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_0: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, 
+                PADI=>RD0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD0_zd         	: std_logic := 'X';
+    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD0_RD0          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD0_ipd,
+        TestSignalName => "RD0",
+        Period => tperiod_RD0,
+        PulseWidthHigh => tpw_RD0_posedge,
+        PulseWidthLow => tpw_RD0_negedge,
+        PeriodData => periodcheckinfo_RD0,
+        Violation => tviol_RD0_RD0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD0_zd 	:= RD0_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD0_ipd'last_event,
+                           PathDelay => tpd_RD0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD0,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD0,
+                           PathCondition => TRUE)),
+      GlitchData => RD0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0118
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0118 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0118 : ENTITY IS TRUE;
+
+  end mjiobuf0118;
+
+  architecture Structure of mjiobuf0118 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity Dout_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
+
+  end Dout_0_B;
+
+  architecture Structure of Dout_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout0_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_0: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
+    VARIABLE Dout0_zd         	: std_logic := 'X';
+    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout0_zd 	:= Dout0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout0,
+                           PathCondition => TRUE)),
+      GlitchData => Dout0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0119
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0119 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0119 : ENTITY IS TRUE;
+
+  end mjiobuf0119;
+
+  architecture Structure of mjiobuf0119 is
+    component IBPD
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPD
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity PHI2B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity PHI2B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "PHI2B";
+
+      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_PHI2S 	: VitalDelayType := 0 ns;
+      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
+      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; PHI2S: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
+
+  end PHI2B;
+
+  architecture Structure of PHI2B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PHI2S_ipd 	: std_logic := 'X';
+
+    component mjiobuf0119
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    PHI2_pad: mjiobuf0119
+      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
+    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => PHI2S_ipd,
+        TestSignalName => "PHI2S",
+        Period => tperiod_PHI2S,
+        PulseWidthHigh => tpw_PHI2S_posedge,
+        PulseWidthLow => tpw_PHI2S_negedge,
+        PeriodData => periodcheckinfo_PHI2S,
+        Violation => tviol_PHI2S_PHI2S,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
+                           PathDelay => tpd_PHI2S_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0120
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0120 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0120 : ENTITY IS TRUE;
+
+  end mjiobuf0120;
+
+  architecture Structure of mjiobuf0120 is
+    component IB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IB
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity UFMSDOB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDOB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDOB";
+
+      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
+      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
+
+  end UFMSDOB;
+
+  architecture Structure of UFMSDOB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal UFMSDOS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    UFMSDO_pad: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
+    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => UFMSDOS_ipd,
+        TestSignalName => "UFMSDOS",
+        Period => tperiod_UFMSDOS,
+        PulseWidthHigh => tpw_UFMSDOS_posedge,
+        PulseWidthLow => tpw_UFMSDOS_negedge,
+        PeriodData => periodcheckinfo_UFMSDOS,
+        Violation => tviol_UFMSDOS_UFMSDOS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
+                           PathDelay => tpd_UFMSDOS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0121
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0121 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0121 : ENTITY IS TRUE;
+
+  end mjiobuf0121;
+
+  architecture Structure of mjiobuf0121 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity UFMSDIB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMSDIB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMSDIB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMSDIS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
+
+  end UFMSDIB;
+
+  architecture Structure of UFMSDIB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMSDIS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMSDI_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
+    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
+    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMSDIS_zd 	:= UFMSDIS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMSDIS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMSDIS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity UFMCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity UFMCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "UFMCLKB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_UFMCLKS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
+
+  end UFMCLKB;
+
+  architecture Structure of UFMCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal UFMCLKS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    UFMCLK_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
+    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
+    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    UFMCLKS_zd 	:= UFMCLKS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_UFMCLKS,
+                           PathCondition => TRUE)),
+      GlitchData => UFMCLKS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nUFMCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nUFMCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nUFMCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+
+        tpd_PADDO_nUFMCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
+
+  end nUFMCSB;
+
+  architecture Structure of nUFMCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nUFMCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nUFMCS_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
+    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
+    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nUFMCSS_zd 	:= nUFMCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nUFMCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nUFMCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMLB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMLB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMLB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMLS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
+
+  end RDQMLB;
+
+  architecture Structure of RDQMLB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMLS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQML_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
+    VARIABLE RDQMLS_zd         	: std_logic := 'X';
+    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMLS_zd 	:= RDQMLS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMLS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMLS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RDQMHB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RDQMHB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RDQMHB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RDQMHS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
+
+  end RDQMHB;
+
+  architecture Structure of RDQMHB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RDQMHS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RDQMH_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
+    VARIABLE RDQMHS_zd         	: std_logic := 'X';
+    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RDQMHS_zd 	:= RDQMHS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RDQMHS,
+                           PathCondition => TRUE)),
+      GlitchData => RDQMHS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
+
+  end nRCASB;
+
+  architecture Structure of nRCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCASS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCAS_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>nRCASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
+    VARIABLE nRCASS_zd         	: std_logic := 'X';
+    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCASS_zd 	:= nRCASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRRASB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRRASS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRRASS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
+
+  end nRRASB;
+
+  architecture Structure of nRRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRRASS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRRAS_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>nRRASS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
+    VARIABLE nRRASS_zd         	: std_logic := 'X';
+    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRRASS_zd 	:= nRRASS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRRASS,
+                           PathCondition => TRUE)),
+      GlitchData => nRRASS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRWEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRWES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRWES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
+
+  end nRWEB;
+
+  architecture Structure of nRWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRWES_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRWE_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>nRWES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
+    VARIABLE nRWES_zd         	: std_logic := 'X';
+    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRWES_zd 	:= nRWES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRWES,
+                           PathCondition => TRUE)),
+      GlitchData => nRWES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCKEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCKEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCKEB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RCKES	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RCKES: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
+
+  end RCKEB;
+
+  architecture Structure of RCKEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RCKES_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RCKE_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RCKES_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
+    VARIABLE RCKES_zd         	: std_logic := 'X';
+    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RCKES_zd 	:= RCKES_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RCKES,
+                           PathCondition => TRUE)),
+      GlitchData => RCKES_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RCLKB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RCLKB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RCLKB";
+
+      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RCLKS 	: VitalDelayType := 0 ns;
+      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
+      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; RCLKS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
+
+  end RCLKB;
+
+  architecture Structure of RCLKB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal RCLKS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    RCLK_pad: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
+    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RCLKS_ipd,
+        TestSignalName => "RCLKS",
+        Period => tperiod_RCLKS,
+        PulseWidthHigh => tpw_RCLKS_posedge,
+        PulseWidthLow => tpw_RCLKS_negedge,
+        PeriodData => periodcheckinfo_RCLKS,
+        Violation => tviol_RCLKS_RCLKS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
+                           PathDelay => tpd_RCLKS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nRCSB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nRCSB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nRCSB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_nRCSS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; nRCSS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
+
+  end nRCSB;
+
+  architecture Structure of nRCSB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal nRCSS_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    nRCS_pad: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>nRCSS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
+    VARIABLE nRCSS_zd         	: std_logic := 'X';
+    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    nRCSS_zd 	:= nRCSS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_nRCSS,
+                           PathCondition => TRUE)),
+      GlitchData => nRCSS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_7_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD7 	: VitalDelayType := 0 ns;
+      tpw_RD7_posedge	: VitalDelayType := 0 ns;
+      tpw_RD7_negedge	: VitalDelayType := 0 ns;
+      tpd_RD7_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD7: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
+
+  end RD_7_B;
+
+  architecture Structure of RD_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD7_ipd 	: std_logic := 'X';
+    signal RD7_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_7: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, 
+                PADI=>RD7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD7_zd         	: std_logic := 'X';
+    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD7_RD7          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD7_ipd,
+        TestSignalName => "RD7",
+        Period => tperiod_RD7,
+        PulseWidthHigh => tpw_RD7_posedge,
+        PulseWidthLow => tpw_RD7_negedge,
+        PeriodData => periodcheckinfo_RD7,
+        Violation => tviol_RD7_RD7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD7_zd 	:= RD7_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD7_ipd'last_event,
+                           PathDelay => tpd_RD7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD7,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD7,
+                           PathCondition => TRUE)),
+      GlitchData => RD7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_6_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD6 	: VitalDelayType := 0 ns;
+      tpw_RD6_posedge	: VitalDelayType := 0 ns;
+      tpw_RD6_negedge	: VitalDelayType := 0 ns;
+      tpd_RD6_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD6: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
+
+  end RD_6_B;
+
+  architecture Structure of RD_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD6_ipd 	: std_logic := 'X';
+    signal RD6_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_6: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, 
+                PADI=>RD6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD6_zd         	: std_logic := 'X';
+    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD6_RD6          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD6_ipd,
+        TestSignalName => "RD6",
+        Period => tperiod_RD6,
+        PulseWidthHigh => tpw_RD6_posedge,
+        PulseWidthLow => tpw_RD6_negedge,
+        PeriodData => periodcheckinfo_RD6,
+        Violation => tviol_RD6_RD6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD6_zd 	:= RD6_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD6_ipd'last_event,
+                           PathDelay => tpd_RD6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD6,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD6,
+                           PathCondition => TRUE)),
+      GlitchData => RD6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_5_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD5 	: VitalDelayType := 0 ns;
+      tpw_RD5_posedge	: VitalDelayType := 0 ns;
+      tpw_RD5_negedge	: VitalDelayType := 0 ns;
+      tpd_RD5_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD5: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
+
+  end RD_5_B;
+
+  architecture Structure of RD_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD5_ipd 	: std_logic := 'X';
+    signal RD5_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_5: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, 
+                PADI=>RD5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD5_zd         	: std_logic := 'X';
+    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD5_RD5          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD5_ipd,
+        TestSignalName => "RD5",
+        Period => tperiod_RD5,
+        PulseWidthHigh => tpw_RD5_posedge,
+        PulseWidthLow => tpw_RD5_negedge,
+        PeriodData => periodcheckinfo_RD5,
+        Violation => tviol_RD5_RD5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD5_zd 	:= RD5_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD5_ipd'last_event,
+                           PathDelay => tpd_RD5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD5,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD5,
+                           PathCondition => TRUE)),
+      GlitchData => RD5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_4_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD4 	: VitalDelayType := 0 ns;
+      tpw_RD4_posedge	: VitalDelayType := 0 ns;
+      tpw_RD4_negedge	: VitalDelayType := 0 ns;
+      tpd_RD4_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD4: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
+
+  end RD_4_B;
+
+  architecture Structure of RD_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD4_ipd 	: std_logic := 'X';
+    signal RD4_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_4: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, 
+                PADI=>RD4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD4_zd         	: std_logic := 'X';
+    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD4_RD4          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD4_ipd,
+        TestSignalName => "RD4",
+        Period => tperiod_RD4,
+        PulseWidthHigh => tpw_RD4_posedge,
+        PulseWidthLow => tpw_RD4_negedge,
+        PeriodData => periodcheckinfo_RD4,
+        Violation => tviol_RD4_RD4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD4_zd 	:= RD4_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD4_ipd'last_event,
+                           PathDelay => tpd_RD4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD4,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD4,
+                           PathCondition => TRUE)),
+      GlitchData => RD4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_3_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD3 	: VitalDelayType := 0 ns;
+      tpw_RD3_posedge	: VitalDelayType := 0 ns;
+      tpw_RD3_negedge	: VitalDelayType := 0 ns;
+      tpd_RD3_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD3: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
+
+  end RD_3_B;
+
+  architecture Structure of RD_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD3_ipd 	: std_logic := 'X';
+    signal RD3_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_3: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, 
+                PADI=>RD3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD3_zd         	: std_logic := 'X';
+    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD3_RD3          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD3_ipd,
+        TestSignalName => "RD3",
+        Period => tperiod_RD3,
+        PulseWidthHigh => tpw_RD3_posedge,
+        PulseWidthLow => tpw_RD3_negedge,
+        PeriodData => periodcheckinfo_RD3,
+        Violation => tviol_RD3_RD3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD3_zd 	:= RD3_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD3_ipd'last_event,
+                           PathDelay => tpd_RD3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD3,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD3,
+                           PathCondition => TRUE)),
+      GlitchData => RD3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_2_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD2 	: VitalDelayType := 0 ns;
+      tpw_RD2_posedge	: VitalDelayType := 0 ns;
+      tpw_RD2_negedge	: VitalDelayType := 0 ns;
+      tpd_RD2_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD2: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
+
+  end RD_2_B;
+
+  architecture Structure of RD_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD2_ipd 	: std_logic := 'X';
+    signal RD2_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_2: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, 
+                PADI=>RD2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD2_zd         	: std_logic := 'X';
+    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD2_RD2          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD2_ipd,
+        TestSignalName => "RD2",
+        Period => tperiod_RD2,
+        PulseWidthHigh => tpw_RD2_posedge,
+        PulseWidthLow => tpw_RD2_negedge,
+        PeriodData => periodcheckinfo_RD2,
+        Violation => tviol_RD2_RD2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD2_zd 	:= RD2_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD2_ipd'last_event,
+                           PathDelay => tpd_RD2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD2,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD2,
+                           PathCondition => TRUE)),
+      GlitchData => RD2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RD_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RD_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RD_1_B";
+
+      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tipd_RD1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_PADDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
+      tpd_RD1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_RD1 	: VitalDelayType := 0 ns;
+      tpw_RD1_posedge	: VitalDelayType := 0 ns;
+      tpw_RD1_negedge	: VitalDelayType := 0 ns;
+      tpd_RD1_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+          RD1: inout Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
+
+  end RD_1_B;
+
+  architecture Structure of RD_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal PADDT_ipd 	: std_logic := 'X';
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RD1_ipd 	: std_logic := 'X';
+    signal RD1_out 	: std_logic := 'Z';
+
+    component mjiobuf
+      port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; 
+            PAD: out Std_logic; PADI: in Std_logic);
+    end component;
+  begin
+    RD_pad_1: mjiobuf
+      port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, 
+                PADI=>RD1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+      VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+    VARIABLE RD1_zd         	: std_logic := 'X';
+    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_RD1_RD1          	: x01 := '0';
+    VARIABLE periodcheckinfo_RD1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => RD1_ipd,
+        TestSignalName => "RD1",
+        Period => tperiod_RD1,
+        PulseWidthHigh => tpw_RD1_posedge,
+        PulseWidthLow => tpw_RD1_negedge,
+        PeriodData => periodcheckinfo_RD1,
+        Violation => tviol_RD1_RD1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+    RD1_zd 	:= RD1_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => RD1_ipd'last_event,
+                           PathDelay => tpd_RD1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+    VitalPathDelay01Z (
+      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
+      Paths      => (0 => (InputChangeTime => PADDT_ipd'last_event,
+                           PathDelay => tpd_PADDT_RD1,
+                           PathCondition => TRUE),
+                     1 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RD1,
+                           PathCondition => TRUE)),
+      GlitchData => RD1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_11_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_11_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_11_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA11	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA11: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
+
+  end RA_11_B;
+
+  architecture Structure of RA_11_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA11_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_11: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA11_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
+    VARIABLE RA11_zd         	: std_logic := 'X';
+    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA11_zd 	:= RA11_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA11,
+                           PathCondition => TRUE)),
+      GlitchData => RA11_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_10_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_10_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_10_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA10	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RA10: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
+
+  end RA_10_B;
+
+  architecture Structure of RA_10_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA10_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_10: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA10_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
+    VARIABLE RA10_zd         	: std_logic := 'X';
+    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA10_zd 	:= RA10_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA10,
+                           PathCondition => TRUE)),
+      GlitchData => RA10_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_9_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA9	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA9: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
+
+  end RA_9_B;
+
+  architecture Structure of RA_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA9_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_9: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA9_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
+    VARIABLE RA9_zd         	: std_logic := 'X';
+    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA9_zd 	:= RA9_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA9,
+                           PathCondition => TRUE)),
+      GlitchData => RA9_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_8_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA8	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA8: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
+
+  end RA_8_B;
+
+  architecture Structure of RA_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA8_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_8: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA8_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
+    VARIABLE RA8_zd         	: std_logic := 'X';
+    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA8_zd 	:= RA8_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA8,
+                           PathCondition => TRUE)),
+      GlitchData => RA8_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
+
+  end RA_7_B;
+
+  architecture Structure of RA_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA7_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_7: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
+    VARIABLE RA7_zd         	: std_logic := 'X';
+    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA7_zd 	:= RA7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA7,
+                           PathCondition => TRUE)),
+      GlitchData => RA7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
+
+  end RA_6_B;
+
+  architecture Structure of RA_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA6_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_6: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
+    VARIABLE RA6_zd         	: std_logic := 'X';
+    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA6_zd 	:= RA6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA6,
+                           PathCondition => TRUE)),
+      GlitchData => RA6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
+
+  end RA_5_B;
+
+  architecture Structure of RA_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA5_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_5: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
+    VARIABLE RA5_zd         	: std_logic := 'X';
+    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA5_zd 	:= RA5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA5,
+                           PathCondition => TRUE)),
+      GlitchData => RA5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
+
+  end RA_4_B;
+
+  architecture Structure of RA_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA4_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_4: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
+    VARIABLE RA4_zd         	: std_logic := 'X';
+    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA4_zd 	:= RA4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA4,
+                           PathCondition => TRUE)),
+      GlitchData => RA4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
+
+  end RA_3_B;
+
+  architecture Structure of RA_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA3_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_3: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
+    VARIABLE RA3_zd         	: std_logic := 'X';
+    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA3_zd 	:= RA3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA3,
+                           PathCondition => TRUE)),
+      GlitchData => RA3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
+
+  end RA_2_B;
+
+  architecture Structure of RA_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA2_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_2: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
+    VARIABLE RA2_zd         	: std_logic := 'X';
+    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA2_zd 	:= RA2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA2,
+                           PathCondition => TRUE)),
+      GlitchData => RA2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
+
+  end RA_1_B;
+
+  architecture Structure of RA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA1_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_1: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
+    VARIABLE RA1_zd         	: std_logic := 'X';
+    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA1_zd 	:= RA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA1,
+                           PathCondition => TRUE)),
+      GlitchData => RA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
+
+    port (PADDO: in Std_logic; RA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
+
+  end RA_0_B;
+
+  architecture Structure of RA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RA0_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RA_pad_0: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
+    VARIABLE RA0_zd         	: std_logic := 'X';
+    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RA0_zd 	:= RA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RA0,
+                           PathCondition => TRUE)),
+      GlitchData => RA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
+
+  end RBA_1_B;
+
+  architecture Structure of RBA_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA1_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_1: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RBA1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
+    VARIABLE RBA1_zd         	: std_logic := 'X';
+    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA1_zd 	:= RBA1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA1,
+                           PathCondition => TRUE)),
+      GlitchData => RBA1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RBA_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RBA_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "RBA_0_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_RBA0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; RBA0: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
+
+  end RBA_0_B;
+
+  architecture Structure of RBA_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal RBA0_out 	: std_logic := 'X';
+
+    component mjiobuf0121
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    RBA_pad_0: mjiobuf0121
+      port map (I=>PADDO_ipd, PAD=>RBA0_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
+    VARIABLE RBA0_zd         	: std_logic := 'X';
+    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    RBA0_zd 	:= RBA0_out;
+
+    VitalPathDelay01Z (
+      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_RBA0,
+                           PathCondition => TRUE)),
+      GlitchData => RBA0_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0122
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0122 is
+    port (I: in Std_logic; PAD: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0122 : ENTITY IS TRUE;
+
+  end mjiobuf0122;
+
+  architecture Structure of mjiobuf0122 is
+    component OB
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST5: OB
+      port map (I=>I, O=>PAD);
+  end Structure;
+
+-- entity LEDB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity LEDB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "LEDB";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_LEDS	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; LEDS: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
+
+  end LEDB;
+
+  architecture Structure of LEDB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal LEDS_out 	: std_logic := 'X';
+
+    component mjiobuf0122
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    LED_pad: mjiobuf0122
+      port map (I=>PADDO_ipd, PAD=>LEDS_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
+    VARIABLE LEDS_zd         	: std_logic := 'X';
+    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    LEDS_zd 	:= LEDS_out;
+
+    VitalPathDelay01Z (
+      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_LEDS,
+                           PathCondition => TRUE)),
+      GlitchData => LEDS_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nFWEB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nFWEB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nFWEB";
+
+      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nFWES 	: VitalDelayType := 0 ns;
+      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
+      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nFWES: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
+
+  end nFWEB;
+
+  architecture Structure of nFWEB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nFWES_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nFWE_pad: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
+    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nFWES_ipd,
+        TestSignalName => "nFWES",
+        Period => tperiod_nFWES,
+        PulseWidthHigh => tpw_nFWES_posedge,
+        PulseWidthLow => tpw_nFWES_negedge,
+        PeriodData => periodcheckinfo_nFWES,
+        Violation => tviol_nFWES_nFWES,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
+                           PathDelay => tpd_nFWES_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity mjiobuf0123
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity mjiobuf0123 is
+    port (Z: out Std_logic; PAD: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF mjiobuf0123 : ENTITY IS TRUE;
+
+  end mjiobuf0123;
+
+  architecture Structure of mjiobuf0123 is
+    component IBPU
+      port (I: in Std_logic; O: out Std_logic);
+    end component;
+  begin
+    INST1: IBPU
+      port map (I=>PAD, O=>Z);
+  end Structure;
+
+-- entity nCRASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCRASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCRASB";
+
+      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCRASS 	: VitalDelayType := 0 ns;
+      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCRASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
+
+  end nCRASB;
+
+  architecture Structure of nCRASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCRASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0123
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCRAS_pad: mjiobuf0123
+      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCRASS_ipd,
+        TestSignalName => "nCRASS",
+        Period => tperiod_nCRASS,
+        PulseWidthHigh => tpw_nCRASS_posedge,
+        PulseWidthLow => tpw_nCRASS_negedge,
+        PeriodData => periodcheckinfo_nCRASS,
+        Violation => tviol_nCRASS_nCRASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
+                           PathDelay => tpd_nCRASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity nCCASB
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity nCCASB is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "nCCASB";
+
+      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_nCCASS 	: VitalDelayType := 0 ns;
+      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
+      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; nCCASS: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
+
+  end nCCASB;
+
+  architecture Structure of nCCASB is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal nCCASS_ipd 	: std_logic := 'X';
+
+    component mjiobuf0123
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    nCCAS_pad: mjiobuf0123
+      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
+    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => nCCASS_ipd,
+        TestSignalName => "nCCASS",
+        Period => tperiod_nCCASS,
+        PulseWidthHigh => tpw_nCCASS_posedge,
+        PulseWidthLow => tpw_nCCASS_negedge,
+        PeriodData => periodcheckinfo_nCCASS,
+        Violation => tviol_nCCASS_nCCASS,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
+                           PathDelay => tpd_nCCASS_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_7_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout7: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
+
+  end Dout_7_B;
+
+  architecture Structure of Dout_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout7_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_7: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout7_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
+    VARIABLE Dout7_zd         	: std_logic := 'X';
+    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout7_zd 	:= Dout7_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout7,
+                           PathCondition => TRUE)),
+      GlitchData => Dout7_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_6_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout6: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
+
+  end Dout_6_B;
+
+  architecture Structure of Dout_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout6_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_6: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout6_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
+    VARIABLE Dout6_zd         	: std_logic := 'X';
+    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout6_zd 	:= Dout6_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout6,
+                           PathCondition => TRUE)),
+      GlitchData => Dout6_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_5_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout5: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
+
+  end Dout_5_B;
+
+  architecture Structure of Dout_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout5_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_5: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout5_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
+    VARIABLE Dout5_zd         	: std_logic := 'X';
+    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout5_zd 	:= Dout5_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout5,
+                           PathCondition => TRUE)),
+      GlitchData => Dout5_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_4_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout4: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
+
+  end Dout_4_B;
+
+  architecture Structure of Dout_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout4_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_4: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout4_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
+    VARIABLE Dout4_zd         	: std_logic := 'X';
+    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout4_zd 	:= Dout4_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout4,
+                           PathCondition => TRUE)),
+      GlitchData => Dout4_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_3_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout3: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
+
+  end Dout_3_B;
+
+  architecture Structure of Dout_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout3_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_3: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout3_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
+    VARIABLE Dout3_zd         	: std_logic := 'X';
+    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout3_zd 	:= Dout3_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout3,
+                           PathCondition => TRUE)),
+      GlitchData => Dout3_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_2_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout2: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
+
+  end Dout_2_B;
+
+  architecture Structure of Dout_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout2_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_2: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout2_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
+    VARIABLE Dout2_zd         	: std_logic := 'X';
+    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout2_zd 	:= Dout2_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout2,
+                           PathCondition => TRUE)),
+      GlitchData => Dout2_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Dout_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Dout_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Dout_1_B";
+
+      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_PADDO_Dout1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
+        );
+
+    port (PADDO: in Std_logic; Dout1: out Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
+
+  end Dout_1_B;
+
+  architecture Structure of Dout_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDO_ipd 	: std_logic := 'X';
+    signal Dout1_out 	: std_logic := 'X';
+
+    component mjiobuf0118
+      port (I: in Std_logic; PAD: out Std_logic);
+    end component;
+  begin
+    Dout_pad_1: mjiobuf0118
+      port map (I=>PADDO_ipd, PAD=>Dout1_out);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
+    VARIABLE Dout1_zd         	: std_logic := 'X';
+    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
+
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+
+    END IF;
+
+    Dout1_zd 	:= Dout1_out;
+
+    VitalPathDelay01Z (
+      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
+      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
+                           PathDelay => tpd_PADDO_Dout1,
+                           PathCondition => TRUE)),
+      GlitchData => Dout1_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_7_B";
+
+      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din7 	: VitalDelayType := 0 ns;
+      tpw_Din7_posedge	: VitalDelayType := 0 ns;
+      tpw_Din7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
+
+  end Din_7_B;
+
+  architecture Structure of Din_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_7: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din7_Din7          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din7_ipd,
+        TestSignalName => "Din7",
+        Period => tperiod_Din7,
+        PulseWidthHigh => tpw_Din7_posedge,
+        PulseWidthLow => tpw_Din7_negedge,
+        PeriodData => periodcheckinfo_Din7,
+        Violation => tviol_Din7_Din7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
+                           PathDelay => tpd_Din7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_6_B";
+
+      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din6 	: VitalDelayType := 0 ns;
+      tpw_Din6_posedge	: VitalDelayType := 0 ns;
+      tpw_Din6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
+
+  end Din_6_B;
+
+  architecture Structure of Din_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_6: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din6_Din6          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din6_ipd,
+        TestSignalName => "Din6",
+        Period => tperiod_Din6,
+        PulseWidthHigh => tpw_Din6_posedge,
+        PulseWidthLow => tpw_Din6_negedge,
+        PeriodData => periodcheckinfo_Din6,
+        Violation => tviol_Din6_Din6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
+                           PathDelay => tpd_Din6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_5_B";
+
+      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din5 	: VitalDelayType := 0 ns;
+      tpw_Din5_posedge	: VitalDelayType := 0 ns;
+      tpw_Din5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
+
+  end Din_5_B;
+
+  architecture Structure of Din_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_5: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din5_Din5          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din5_ipd,
+        TestSignalName => "Din5",
+        Period => tperiod_Din5,
+        PulseWidthHigh => tpw_Din5_posedge,
+        PulseWidthLow => tpw_Din5_negedge,
+        PeriodData => periodcheckinfo_Din5,
+        Violation => tviol_Din5_Din5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
+                           PathDelay => tpd_Din5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_4_B";
+
+      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din4 	: VitalDelayType := 0 ns;
+      tpw_Din4_posedge	: VitalDelayType := 0 ns;
+      tpw_Din4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
+
+  end Din_4_B;
+
+  architecture Structure of Din_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_4: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din4_Din4          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din4_ipd,
+        TestSignalName => "Din4",
+        Period => tperiod_Din4,
+        PulseWidthHigh => tpw_Din4_posedge,
+        PulseWidthLow => tpw_Din4_negedge,
+        PeriodData => periodcheckinfo_Din4,
+        Violation => tviol_Din4_Din4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
+                           PathDelay => tpd_Din4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_3_B";
+
+      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din3 	: VitalDelayType := 0 ns;
+      tpw_Din3_posedge	: VitalDelayType := 0 ns;
+      tpw_Din3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
+
+  end Din_3_B;
+
+  architecture Structure of Din_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_3: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din3_Din3          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din3_ipd,
+        TestSignalName => "Din3",
+        Period => tperiod_Din3,
+        PulseWidthHigh => tpw_Din3_posedge,
+        PulseWidthLow => tpw_Din3_negedge,
+        PeriodData => periodcheckinfo_Din3,
+        Violation => tviol_Din3_Din3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
+                           PathDelay => tpd_Din3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_2_B";
+
+      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din2 	: VitalDelayType := 0 ns;
+      tpw_Din2_posedge	: VitalDelayType := 0 ns;
+      tpw_Din2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
+
+  end Din_2_B;
+
+  architecture Structure of Din_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_2: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din2_Din2          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din2_ipd,
+        TestSignalName => "Din2",
+        Period => tperiod_Din2,
+        PulseWidthHigh => tpw_Din2_posedge,
+        PulseWidthLow => tpw_Din2_negedge,
+        PeriodData => periodcheckinfo_Din2,
+        Violation => tviol_Din2_Din2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
+                           PathDelay => tpd_Din2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_1_B";
+
+      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din1 	: VitalDelayType := 0 ns;
+      tpw_Din1_posedge	: VitalDelayType := 0 ns;
+      tpw_Din1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
+
+  end Din_1_B;
+
+  architecture Structure of Din_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_1: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din1_Din1          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din1_ipd,
+        TestSignalName => "Din1",
+        Period => tperiod_Din1,
+        PulseWidthHigh => tpw_Din1_posedge,
+        PulseWidthLow => tpw_Din1_negedge,
+        PeriodData => periodcheckinfo_Din1,
+        Violation => tviol_Din1_Din1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
+                           PathDelay => tpd_Din1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity Din_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity Din_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "Din_0_B";
+
+      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_Din0 	: VitalDelayType := 0 ns;
+      tpw_Din0_posedge	: VitalDelayType := 0 ns;
+      tpw_Din0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; Din0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
+
+  end Din_0_B;
+
+  architecture Structure of Din_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal Din0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    Din_pad_0: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>Din0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_Din0_Din0          	: x01 := '0';
+    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => Din0_ipd,
+        TestSignalName => "Din0",
+        Period => tperiod_Din0,
+        PulseWidthHigh => tpw_Din0_posedge,
+        PulseWidthLow => tpw_Din0_negedge,
+        PeriodData => periodcheckinfo_Din0,
+        Violation => tviol_Din0_Din0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
+                           PathDelay => tpd_Din0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_1_B";
+
+      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW1 	: VitalDelayType := 0 ns;
+      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
+
+  end CROW_1_B;
+
+  architecture Structure of CROW_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_1: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW1_ipd,
+        TestSignalName => "CROW1",
+        Period => tperiod_CROW1,
+        PulseWidthHigh => tpw_CROW1_posedge,
+        PulseWidthLow => tpw_CROW1_negedge,
+        PeriodData => periodcheckinfo_CROW1,
+        Violation => tviol_CROW1_CROW1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
+                           PathDelay => tpd_CROW1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity CROW_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity CROW_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "CROW_0_B";
+
+      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_CROW0 	: VitalDelayType := 0 ns;
+      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
+      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; CROW0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
+
+  end CROW_0_B;
+
+  architecture Structure of CROW_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal CROW0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    CROW_pad_0: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
+    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => CROW0_ipd,
+        TestSignalName => "CROW0",
+        Period => tperiod_CROW0,
+        PulseWidthHigh => tpw_CROW0_posedge,
+        PulseWidthLow => tpw_CROW0_negedge,
+        PeriodData => periodcheckinfo_CROW0,
+        Violation => tviol_CROW0_CROW0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
+                           PathDelay => tpd_CROW0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_9_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_9_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_9_B";
+
+      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin9 	: VitalDelayType := 0 ns;
+      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin9: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
+
+  end MAin_9_B;
+
+  architecture Structure of MAin_9_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin9_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_9: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin9_ipd,
+        TestSignalName => "MAin9",
+        Period => tperiod_MAin9,
+        PulseWidthHigh => tpw_MAin9_posedge,
+        PulseWidthLow => tpw_MAin9_negedge,
+        PeriodData => periodcheckinfo_MAin9,
+        Violation => tviol_MAin9_MAin9,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
+                           PathDelay => tpd_MAin9_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_8_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_8_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_8_B";
+
+      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin8 	: VitalDelayType := 0 ns;
+      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin8: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
+
+  end MAin_8_B;
+
+  architecture Structure of MAin_8_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin8_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_8: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin8_ipd,
+        TestSignalName => "MAin8",
+        Period => tperiod_MAin8,
+        PulseWidthHigh => tpw_MAin8_posedge,
+        PulseWidthLow => tpw_MAin8_negedge,
+        PeriodData => periodcheckinfo_MAin8,
+        Violation => tviol_MAin8_MAin8,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
+                           PathDelay => tpd_MAin8_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_7_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_7_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_7_B";
+
+      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin7 	: VitalDelayType := 0 ns;
+      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin7: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
+
+  end MAin_7_B;
+
+  architecture Structure of MAin_7_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin7_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_7: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin7_ipd,
+        TestSignalName => "MAin7",
+        Period => tperiod_MAin7,
+        PulseWidthHigh => tpw_MAin7_posedge,
+        PulseWidthLow => tpw_MAin7_negedge,
+        PeriodData => periodcheckinfo_MAin7,
+        Violation => tviol_MAin7_MAin7,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
+                           PathDelay => tpd_MAin7_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_6_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_6_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_6_B";
+
+      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin6 	: VitalDelayType := 0 ns;
+      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin6: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
+
+  end MAin_6_B;
+
+  architecture Structure of MAin_6_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin6_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_6: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin6_ipd,
+        TestSignalName => "MAin6",
+        Period => tperiod_MAin6,
+        PulseWidthHigh => tpw_MAin6_posedge,
+        PulseWidthLow => tpw_MAin6_negedge,
+        PeriodData => periodcheckinfo_MAin6,
+        Violation => tviol_MAin6_MAin6,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
+                           PathDelay => tpd_MAin6_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_5_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_5_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_5_B";
+
+      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin5 	: VitalDelayType := 0 ns;
+      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin5: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
+
+  end MAin_5_B;
+
+  architecture Structure of MAin_5_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin5_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_5: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin5_ipd,
+        TestSignalName => "MAin5",
+        Period => tperiod_MAin5,
+        PulseWidthHigh => tpw_MAin5_posedge,
+        PulseWidthLow => tpw_MAin5_negedge,
+        PeriodData => periodcheckinfo_MAin5,
+        Violation => tviol_MAin5_MAin5,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
+                           PathDelay => tpd_MAin5_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_4_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_4_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_4_B";
+
+      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin4 	: VitalDelayType := 0 ns;
+      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin4: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
+
+  end MAin_4_B;
+
+  architecture Structure of MAin_4_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin4_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_4: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin4_ipd,
+        TestSignalName => "MAin4",
+        Period => tperiod_MAin4,
+        PulseWidthHigh => tpw_MAin4_posedge,
+        PulseWidthLow => tpw_MAin4_negedge,
+        PeriodData => periodcheckinfo_MAin4,
+        Violation => tviol_MAin4_MAin4,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
+                           PathDelay => tpd_MAin4_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_3_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_3_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_3_B";
+
+      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin3 	: VitalDelayType := 0 ns;
+      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin3: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
+
+  end MAin_3_B;
+
+  architecture Structure of MAin_3_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin3_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_3: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin3_ipd,
+        TestSignalName => "MAin3",
+        Period => tperiod_MAin3,
+        PulseWidthHigh => tpw_MAin3_posedge,
+        PulseWidthLow => tpw_MAin3_negedge,
+        PeriodData => periodcheckinfo_MAin3,
+        Violation => tviol_MAin3_MAin3,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
+                           PathDelay => tpd_MAin3_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_2_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_2_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_2_B";
+
+      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin2 	: VitalDelayType := 0 ns;
+      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin2: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
+
+  end MAin_2_B;
+
+  architecture Structure of MAin_2_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin2_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_2: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin2_ipd,
+        TestSignalName => "MAin2",
+        Period => tperiod_MAin2,
+        PulseWidthHigh => tpw_MAin2_posedge,
+        PulseWidthLow => tpw_MAin2_negedge,
+        PeriodData => periodcheckinfo_MAin2,
+        Violation => tviol_MAin2_MAin2,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
+                           PathDelay => tpd_MAin2_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_1_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_1_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_1_B";
+
+      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin1 	: VitalDelayType := 0 ns;
+      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin1: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
+
+  end MAin_1_B;
+
+  architecture Structure of MAin_1_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin1_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_1: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin1_ipd,
+        TestSignalName => "MAin1",
+        Period => tperiod_MAin1,
+        PulseWidthHigh => tpw_MAin1_posedge,
+        PulseWidthLow => tpw_MAin1_negedge,
+        PeriodData => periodcheckinfo_MAin1,
+        Violation => tviol_MAin1_MAin1,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
+                           PathDelay => tpd_MAin1_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity MAin_0_B
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity MAin_0_B is
+    -- miscellaneous vital GENERICs
+    GENERIC (
+      TimingChecksOn	: boolean := TRUE;
+      XOn           	: boolean := FALSE;
+      MsgOn         	: boolean := TRUE;
+      InstancePath  	: string := "MAin_0_B";
+
+      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
+      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
+      tperiod_MAin0 	: VitalDelayType := 0 ns;
+      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
+      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
+
+    port (PADDI: out Std_logic; MAin0: in Std_logic);
+
+    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
+
+  end MAin_0_B;
+
+  architecture Structure of MAin_0_B is
+    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
+
+    signal PADDI_out 	: std_logic := 'X';
+    signal MAin0_ipd 	: std_logic := 'X';
+
+    component mjiobuf0120
+      port (Z: out Std_logic; PAD: in Std_logic);
+    end component;
+  begin
+    MAin_pad_0: mjiobuf0120
+      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
+
+    --  INPUT PATH DELAYs
+    WireDelay : BLOCK
+    BEGIN
+      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
+    END BLOCK;
+
+    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
+    VARIABLE PADDI_zd         	: std_logic := 'X';
+    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
+
+    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
+    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
+
+    BEGIN
+
+    IF (TimingChecksOn) THEN
+      VitalPeriodPulseCheck (
+        TestSignal => MAin0_ipd,
+        TestSignalName => "MAin0",
+        Period => tperiod_MAin0,
+        PulseWidthHigh => tpw_MAin0_posedge,
+        PulseWidthLow => tpw_MAin0_negedge,
+        PeriodData => periodcheckinfo_MAin0,
+        Violation => tviol_MAin0_MAin0,
+        MsgOn => MsgOn, XOn => XOn,
+        HeaderMsg => InstancePath,
+        CheckEnabled => TRUE,
+        MsgSeverity => warning);
+
+    END IF;
+
+    PADDI_zd 	:= PADDI_out;
+
+    VitalPathDelay01 (
+      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
+      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
+                           PathDelay => tpd_MAin0_PADDI,
+                           PathCondition => TRUE)),
+      GlitchData => PADDI_GlitchData,
+      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
+
+    END PROCESS;
+
+  end Structure;
+
+-- entity RAM2GS
+  library IEEE, vital2000, MACHXO;
+  use IEEE.STD_LOGIC_1164.all;
+  use vital2000.vital_timing.all;
+  use MACHXO.COMPONENTS.ALL;
+
+  entity RAM2GS is
+    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
+          CROW: in Std_logic_vector (1 downto 0); 
+          Din: in Std_logic_vector (7 downto 0); 
+          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
+          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
+          RBA: out Std_logic_vector (1 downto 0); 
+          RA: out Std_logic_vector (11 downto 0); 
+          RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
+          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
+          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
+          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
+          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
+
+
+
+  end RAM2GS;
+
+  architecture Structure of RAM2GS is
+    signal FS_1: Std_logic;
+    signal FS_0: Std_logic;
+    signal RCLK_c: Std_logic;
+    signal FS_cry_1: Std_logic;
+    signal FS_17: Std_logic;
+    signal FS_16: Std_logic;
+    signal FS_cry_15: Std_logic;
+    signal FS_15: Std_logic;
+    signal FS_14: Std_logic;
+    signal FS_cry_13: Std_logic;
+    signal FS_13: Std_logic;
+    signal FS_12: Std_logic;
+    signal FS_cry_11: Std_logic;
+    signal FS_11: Std_logic;
+    signal FS_10: Std_logic;
+    signal FS_cry_9: Std_logic;
+    signal FS_9: Std_logic;
+    signal FS_8: Std_logic;
+    signal FS_cry_7: Std_logic;
+    signal FS_7: Std_logic;
+    signal FS_6: Std_logic;
+    signal FS_cry_5: Std_logic;
+    signal FS_5: Std_logic;
+    signal FS_4: Std_logic;
+    signal FS_cry_3: Std_logic;
+    signal FS_3: Std_logic;
+    signal FS_2: Std_logic;
+    signal CmdEnable17_0_a2_4: Std_logic;
+    signal N_147: Std_logic;
+    signal CmdEnable17_0_a2_3: Std_logic;
+    signal MAin_c_0: Std_logic;
+    signal ADSubmitted: Std_logic;
+    signal C1WR_0_a2: Std_logic;
+    signal CmdEnable17: Std_logic;
+    signal CmdEnable16: Std_logic;
+    signal ADSubmitted_r: Std_logic;
+    signal PHI2_c: Std_logic;
+    signal CmdEnable16_0_a2_5: Std_logic;
+    signal CmdEnable16_0_a2_4: Std_logic;
+    signal MAin_c_1: Std_logic;
+    signal C1Submitted: Std_logic;
+    signal C1Submitted_RNO: Std_logic;
+    signal CO0: Std_logic;
+    signal S_1: Std_logic;
+    signal IS_3: Std_logic;
+    signal RASr2: Std_logic;
+    signal N_177_i: Std_logic;
+    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
+    signal CmdEnable: Std_logic;
+    signal un1_CMDWR: Std_logic;
+    signal CmdEnable_s: Std_logic;
+    signal Din_c_5: Std_logic;
+    signal Din_c_3: Std_logic;
+    signal N_128: Std_logic;
+    signal N_152: Std_logic;
+    signal LEDEN: Std_logic;
+    signal N_133: Std_logic;
+    signal N_132: Std_logic;
+    signal N_21_i: Std_logic;
+    signal XOR8MEG18: Std_logic;
+    signal CmdLEDEN: Std_logic;
+    signal CmdSubmitted: Std_logic;
+    signal PHI2r3: Std_logic;
+    signal PHI2r2: Std_logic;
+    signal InitReady: Std_logic;
+    signal CmdSubmitted_1_sqmuxa: Std_logic;
+    signal N_460_0: Std_logic;
+    signal N_136: Std_logic;
+    signal N_43: Std_logic;
+    signal Cmdn8MEGEN: Std_logic;
+    signal CmdEnable16_4: Std_logic;
+    signal n8MEGEN: Std_logic;
+    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
+    signal N_19_i: Std_logic;
+    signal N_160: Std_logic;
+    signal N_155: Std_logic;
+    signal nRRAS_5_u_i_0: Std_logic;
+    signal IS_0: Std_logic;
+    signal Ready: Std_logic;
+    signal N_64_i_i: Std_logic;
+    signal N_24: Std_logic;
+    signal IS_2: Std_logic;
+    signal IS_1: Std_logic;
+    signal N_60_i_i: Std_logic;
+    signal N_56_i: Std_logic;
+    signal N_159_i: Std_logic;
+    signal N_159: Std_logic;
+    signal N_61_i_i: Std_logic;
+    signal RA10s_i: Std_logic;
+    signal N_126: Std_logic;
+    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
+    signal N_51: Std_logic;
+    signal InitReady3: Std_logic;
+    signal N_461_0: Std_logic;
+    signal UFMSDI_ens2_i_a0: Std_logic;
+    signal nCRAS_c: Std_logic;
+    signal CBR: Std_logic;
+    signal UFMSDO_c: Std_logic;
+    signal N_70: Std_logic;
+    signal N_33: Std_logic;
+    signal LED_c: Std_logic;
+    signal XOR8MEG: Std_logic;
+    signal un1_Din_4: Std_logic;
+    signal Din_c_6: Std_logic;
+    signal RA11_2: Std_logic;
+    signal Ready_fast: Std_logic;
+    signal RA_c_11: Std_logic;
+    signal N_171: Std_logic;
+    signal FWEr_fast: Std_logic;
+    signal CASr2: Std_logic;
+    signal RCKEEN_8_u_1: Std_logic;
+    signal RCKEEN_8_u_0_0: Std_logic;
+    signal RCKEEN_8: Std_logic;
+    signal PHI2r: Std_logic;
+    signal RCKEEN: Std_logic;
+    signal RASr: Std_logic;
+    signal RASr3: Std_logic;
+    signal RCKE_2: Std_logic;
+    signal RCKE_c: Std_logic;
+    signal m18_0_a3_3: Std_logic;
+    signal S_0_i_o2_1: Std_logic;
+    signal N_165: Std_logic;
+    signal N_462_0: Std_logic;
+    signal Ready_0_sqmuxa: Std_logic;
+    signal N_463_0: Std_logic;
+    signal nRRAS_0_sqmuxa: Std_logic;
+    signal CmdUFMCLK: Std_logic;
+    signal N_129: Std_logic;
+    signal UFMCLK_r_i_a2_2_2: Std_logic;
+    signal N_139_i: Std_logic;
+    signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
+    signal nUFMCS15: Std_logic;
+    signal UFMCLK_c: Std_logic;
+    signal UFMCLK_RNO: Std_logic;
+    signal UFMSDI_r_xx_mm_1: Std_logic;
+    signal UFMSDI_c: Std_logic;
+    signal UFMSDI_RNO: Std_logic;
+    signal RowA_4: Std_logic;
+    signal nRowColSel: Std_logic;
+    signal MAin_c_4: Std_logic;
+    signal Din_c_4: Std_logic;
+    signal nCCAS_c: Std_logic;
+    signal RA_c_4: Std_logic;
+    signal WRD_4: Std_logic;
+    signal WRD_5: Std_logic;
+    signal Bank_5: Std_logic;
+    signal Bank_2: Std_logic;
+    signal Bank_6: Std_logic;
+    signal Bank_7: Std_logic;
+    signal Din_c_7: Std_logic;
+    signal WRD_6: Std_logic;
+    signal C1WR_0_a2_0_11: Std_logic;
+    signal WRD_7: Std_logic;
+    signal Din_c_2: Std_logic;
+    signal Din_c_0: Std_logic;
+    signal Din_c_1: Std_logic;
+    signal XOR8MEG_3_u_0_a3_2: Std_logic;
+    signal XOR8MEG_3: Std_logic;
+    signal N_69: Std_logic;
+    signal N_31: Std_logic;
+    signal N_151: Std_logic;
+    signal N_41: Std_logic;
+    signal nRCAS_0_sqmuxa_1: Std_logic;
+    signal g0_1: Std_logic;
+    signal N_37_i: Std_logic;
+    signal nRCAS_c: Std_logic;
+    signal CASr3: Std_logic;
+    signal RCKEEN_8_u_0_a2_1_out: Std_logic;
+    signal N_28_i_1: Std_logic;
+    signal N_28_i: Std_logic;
+    signal nRCS_c: Std_logic;
+    signal N_24_i: Std_logic;
+    signal nRRAS_c: Std_logic;
+    signal CBR_fast: Std_logic;
+    signal FWEr: Std_logic;
+    signal m18_0_a2_1: Std_logic;
+    signal G_17_1: Std_logic;
+    signal N_39_i: Std_logic;
+    signal nRWE_c: Std_logic;
+    signal N_179: Std_logic;
+    signal nRowColSel_0_0: Std_logic;
+    signal nUFMCS_c: Std_logic;
+    signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
+    signal nUFMCS_s_0_N_5_i: Std_logic;
+    signal CmdUFMCS: Std_logic;
+    signal N_95_5: Std_logic;
+    signal N_95_3: Std_logic;
+    signal RowA_0: Std_logic;
+    signal RowA_1: Std_logic;
+    signal MAin_c_5: Std_logic;
+    signal CmdUFMCLK_1_sqmuxa: Std_logic;
+    signal RowA_5: Std_logic;
+    signal N_137_8: Std_logic;
+    signal un1_FS_14_i_a2_0_1: Std_logic;
+    signal N_137_6: Std_logic;
+    signal un1_FS_13_i_a2_1: Std_logic;
+    signal Bank_0: Std_logic;
+    signal C1WR_0_a2_0_10: Std_logic;
+    signal Bank_1: Std_logic;
+    signal MAin_c_7: Std_logic;
+    signal MAin_c_6: Std_logic;
+    signal C1WR_0_a2_0_4: Std_logic;
+    signal Bank_3: Std_logic;
+    signal Bank_4: Std_logic;
+    signal C1WR_0_a2_0_3: Std_logic;
+    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
+    signal MAin_c_3: Std_logic;
+    signal MAin_c_2: Std_logic;
+    signal RowA_2: Std_logic;
+    signal RowA_3: Std_logic;
+    signal CmdUFMSDI: Std_logic;
+    signal CASr: Std_logic;
+    signal CmdEnable16_1: Std_logic;
+    signal m6_0_a2_2: Std_logic;
+    signal WRD_0: Std_logic;
+    signal WRD_1: Std_logic;
+    signal g4_0_0_0: Std_logic;
+    signal MAin_c_9: Std_logic;
+    signal MAin_c_8: Std_logic;
+    signal RowA_8: Std_logic;
+    signal RowA_9: Std_logic;
+    signal nFWE_c: Std_logic;
+    signal CROW_c_1: Std_logic;
+    signal CROW_c_0: Std_logic;
+    signal RBA_c_0: Std_logic;
+    signal RBA_c_1: Std_logic;
+    signal WRD_2: Std_logic;
+    signal WRD_3: Std_logic;
+    signal RA_c_9: Std_logic;
+    signal RDQML_c: Std_logic;
+    signal RD_1_i: Std_logic;
+    signal RowA_6: Std_logic;
+    signal RowA_7: Std_logic;
+    signal RA_c_8: Std_logic;
+    signal RDQMH_c: Std_logic;
+    signal RA_c_0: Std_logic;
+    signal RA_c_1: Std_logic;
+    signal RA_c_7: Std_logic;
+    signal RA_c_2: Std_logic;
+    signal RA_c_6: Std_logic;
+    signal RA_c_3: Std_logic;
+    signal RA_c_5: Std_logic;
+    signal RA_c_10: Std_logic;
+    signal RD_in_0: Std_logic;
+    signal RD_in_7: Std_logic;
+    signal RD_in_6: Std_logic;
+    signal RD_in_5: Std_logic;
+    signal RD_in_4: Std_logic;
+    signal RD_in_3: Std_logic;
+    signal RD_in_2: Std_logic;
+    signal RD_in_1: Std_logic;
+    signal VCCI: Std_logic;
+    signal GNDI_TSALL: Std_logic;
+    component VHI
+      port (Z: out Std_logic);
+    end component;
+    component VLO
+      port (Z: out Std_logic);
+    end component;
+    component PUR
+      port (PUR: in Std_logic);
+    end component;
+    component GSR
+      port (GSR: in Std_logic);
+    end component;
+    component TSALL
+      port (TSALL: in Std_logic);
+    end component;
+    component SLICE_0
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
+    end component;
+    component SLICE_1
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_2
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_3
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_4
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_5
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_6
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_7
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_8
+      port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; 
+            FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; 
+            FCO: out Std_logic);
+    end component;
+    component SLICE_9
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_14
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_19
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_20
+      port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            OFX0: out Std_logic; Q0: out Std_logic);
+    end component;
+    component SLICE_21
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_22
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_26
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_29
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_30
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_31
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_32
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_33
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_39
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_41
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_42
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_43
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_44
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_50
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_51
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_52
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_55
+      port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_56
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_57
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_58
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_59
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_60
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_61
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_62
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_63
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_64
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component nRWE_RNO_1_SLICE_65
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            OFX0: out Std_logic);
+    end component;
+    component SLICE_66
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_67
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_68
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_69
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_70
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_71
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_72
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_73
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_74
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_75
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_76
+      port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_77
+      port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_78
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_79
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_80
+      port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_81
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_82
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_83
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; 
+            M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_84
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_85
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
+            Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
+    end component;
+    component SLICE_86
+      port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
+            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_87
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_88
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; M1: in Std_logic; 
+            M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
+            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
+            Q1: out Std_logic);
+    end component;
+    component SLICE_89
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component SLICE_90
+      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_91
+      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_92
+      port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_93
+      port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
+            D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
+            F0: out Std_logic; F1: out Std_logic);
+    end component;
+    component SLICE_94
+      port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; 
+            C0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; 
+            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
+            F1: out Std_logic);
+    end component;
+    component RD_0_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD0: inout Std_logic);
+    end component;
+    component Dout_0_B
+      port (PADDO: in Std_logic; Dout0: out Std_logic);
+    end component;
+    component PHI2B
+      port (PADDI: out Std_logic; PHI2S: in Std_logic);
+    end component;
+    component UFMSDOB
+      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
+    end component;
+    component UFMSDIB
+      port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
+    end component;
+    component UFMCLKB
+      port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
+    end component;
+    component nUFMCSB
+      port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
+    end component;
+    component RDQMLB
+      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
+    end component;
+    component RDQMHB
+      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
+    end component;
+    component nRCASB
+      port (PADDO: in Std_logic; nRCASS: out Std_logic);
+    end component;
+    component nRRASB
+      port (PADDO: in Std_logic; nRRASS: out Std_logic);
+    end component;
+    component nRWEB
+      port (PADDO: in Std_logic; nRWES: out Std_logic);
+    end component;
+    component RCKEB
+      port (PADDO: in Std_logic; RCKES: out Std_logic);
+    end component;
+    component RCLKB
+      port (PADDI: out Std_logic; RCLKS: in Std_logic);
+    end component;
+    component nRCSB
+      port (PADDO: in Std_logic; nRCSS: out Std_logic);
+    end component;
+    component RD_7_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD7: inout Std_logic);
+    end component;
+    component RD_6_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD6: inout Std_logic);
+    end component;
+    component RD_5_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD5: inout Std_logic);
+    end component;
+    component RD_4_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD4: inout Std_logic);
+    end component;
+    component RD_3_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD3: inout Std_logic);
+    end component;
+    component RD_2_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD2: inout Std_logic);
+    end component;
+    component RD_1_B
+      port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; 
+            RD1: inout Std_logic);
+    end component;
+    component RA_11_B
+      port (PADDO: in Std_logic; RA11: out Std_logic);
+    end component;
+    component RA_10_B
+      port (PADDO: in Std_logic; RA10: out Std_logic);
+    end component;
+    component RA_9_B
+      port (PADDO: in Std_logic; RA9: out Std_logic);
+    end component;
+    component RA_8_B
+      port (PADDO: in Std_logic; RA8: out Std_logic);
+    end component;
+    component RA_7_B
+      port (PADDO: in Std_logic; RA7: out Std_logic);
+    end component;
+    component RA_6_B
+      port (PADDO: in Std_logic; RA6: out Std_logic);
+    end component;
+    component RA_5_B
+      port (PADDO: in Std_logic; RA5: out Std_logic);
+    end component;
+    component RA_4_B
+      port (PADDO: in Std_logic; RA4: out Std_logic);
+    end component;
+    component RA_3_B
+      port (PADDO: in Std_logic; RA3: out Std_logic);
+    end component;
+    component RA_2_B
+      port (PADDO: in Std_logic; RA2: out Std_logic);
+    end component;
+    component RA_1_B
+      port (PADDO: in Std_logic; RA1: out Std_logic);
+    end component;
+    component RA_0_B
+      port (PADDO: in Std_logic; RA0: out Std_logic);
+    end component;
+    component RBA_1_B
+      port (PADDO: in Std_logic; RBA1: out Std_logic);
+    end component;
+    component RBA_0_B
+      port (PADDO: in Std_logic; RBA0: out Std_logic);
+    end component;
+    component LEDB
+      port (PADDO: in Std_logic; LEDS: out Std_logic);
+    end component;
+    component nFWEB
+      port (PADDI: out Std_logic; nFWES: in Std_logic);
+    end component;
+    component nCRASB
+      port (PADDI: out Std_logic; nCRASS: in Std_logic);
+    end component;
+    component nCCASB
+      port (PADDI: out Std_logic; nCCASS: in Std_logic);
+    end component;
+    component Dout_7_B
+      port (PADDO: in Std_logic; Dout7: out Std_logic);
+    end component;
+    component Dout_6_B
+      port (PADDO: in Std_logic; Dout6: out Std_logic);
+    end component;
+    component Dout_5_B
+      port (PADDO: in Std_logic; Dout5: out Std_logic);
+    end component;
+    component Dout_4_B
+      port (PADDO: in Std_logic; Dout4: out Std_logic);
+    end component;
+    component Dout_3_B
+      port (PADDO: in Std_logic; Dout3: out Std_logic);
+    end component;
+    component Dout_2_B
+      port (PADDO: in Std_logic; Dout2: out Std_logic);
+    end component;
+    component Dout_1_B
+      port (PADDO: in Std_logic; Dout1: out Std_logic);
+    end component;
+    component Din_7_B
+      port (PADDI: out Std_logic; Din7: in Std_logic);
+    end component;
+    component Din_6_B
+      port (PADDI: out Std_logic; Din6: in Std_logic);
+    end component;
+    component Din_5_B
+      port (PADDI: out Std_logic; Din5: in Std_logic);
+    end component;
+    component Din_4_B
+      port (PADDI: out Std_logic; Din4: in Std_logic);
+    end component;
+    component Din_3_B
+      port (PADDI: out Std_logic; Din3: in Std_logic);
+    end component;
+    component Din_2_B
+      port (PADDI: out Std_logic; Din2: in Std_logic);
+    end component;
+    component Din_1_B
+      port (PADDI: out Std_logic; Din1: in Std_logic);
+    end component;
+    component Din_0_B
+      port (PADDI: out Std_logic; Din0: in Std_logic);
+    end component;
+    component CROW_1_B
+      port (PADDI: out Std_logic; CROW1: in Std_logic);
+    end component;
+    component CROW_0_B
+      port (PADDI: out Std_logic; CROW0: in Std_logic);
+    end component;
+    component MAin_9_B
+      port (PADDI: out Std_logic; MAin9: in Std_logic);
+    end component;
+    component MAin_8_B
+      port (PADDI: out Std_logic; MAin8: in Std_logic);
+    end component;
+    component MAin_7_B
+      port (PADDI: out Std_logic; MAin7: in Std_logic);
+    end component;
+    component MAin_6_B
+      port (PADDI: out Std_logic; MAin6: in Std_logic);
+    end component;
+    component MAin_5_B
+      port (PADDI: out Std_logic; MAin5: in Std_logic);
+    end component;
+    component MAin_4_B
+      port (PADDI: out Std_logic; MAin4: in Std_logic);
+    end component;
+    component MAin_3_B
+      port (PADDI: out Std_logic; MAin3: in Std_logic);
+    end component;
+    component MAin_2_B
+      port (PADDI: out Std_logic; MAin2: in Std_logic);
+    end component;
+    component MAin_1_B
+      port (PADDI: out Std_logic; MAin1: in Std_logic);
+    end component;
+    component MAin_0_B
+      port (PADDI: out Std_logic; MAin0: in Std_logic);
+    end component;
+  begin
+    SLICE_0I: SLICE_0
+      port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, 
+                FCO=>FS_cry_1);
+    SLICE_1I: SLICE_1
+      port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16, 
+                Q1=>FS_17);
+    SLICE_2I: SLICE_2
+      port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14, 
+                Q1=>FS_15, FCO=>FS_cry_15);
+    SLICE_3I: SLICE_3
+      port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12, 
+                Q1=>FS_13, FCO=>FS_cry_13);
+    SLICE_4I: SLICE_4
+      port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10, 
+                Q1=>FS_11, FCO=>FS_cry_11);
+    SLICE_5I: SLICE_5
+      port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8, 
+                Q1=>FS_9, FCO=>FS_cry_9);
+    SLICE_6I: SLICE_6
+      port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6, 
+                Q1=>FS_7, FCO=>FS_cry_7);
+    SLICE_7I: SLICE_7
+      port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4, 
+                Q1=>FS_5, FCO=>FS_cry_5);
+    SLICE_8I: SLICE_8
+      port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2, 
+                Q1=>FS_3, FCO=>FS_cry_3);
+    SLICE_9I: SLICE_9
+      port map (D1=>CmdEnable17_0_a2_4, C1=>N_147, B1=>CmdEnable17_0_a2_3, 
+                A1=>MAin_c_0, D0=>ADSubmitted, C0=>C1WR_0_a2, B0=>CmdEnable17, 
+                A0=>CmdEnable16, DI0=>ADSubmitted_r, CLK=>PHI2_c, 
+                F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
+    SLICE_14I: SLICE_14
+      port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4, 
+                D0=>CmdEnable16, C0=>N_147, B0=>MAin_c_1, A0=>C1Submitted, 
+                DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO, 
+                Q0=>C1Submitted, F1=>CmdEnable16);
+    SLICE_19I: SLICE_19
+      port map (D1=>CO0, C1=>S_1, B1=>IS_3, A1=>RASr2, C0=>S_1, A0=>CO0, 
+                DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0, 
+                F1=>Ready_0_sqmuxa_0_a3_2);
+    SLICE_20I: SLICE_20
+      port map (D1=>CmdEnable, A1=>ADSubmitted, D0=>CmdEnable17, 
+                C0=>C1Submitted, B0=>un1_CMDWR, A0=>CmdEnable, 
+                DI0=>CmdEnable_s, M0=>CmdEnable16, CLK=>PHI2_c, 
+                OFX0=>CmdEnable_s, Q0=>CmdEnable);
+    SLICE_21I: SLICE_21
+      port map (D1=>Din_c_5, C1=>Din_c_3, B1=>N_128, D0=>N_152, C0=>LEDEN, 
+                B0=>N_133, A0=>N_132, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
+                F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
+    SLICE_22I: SLICE_22
+      port map (D1=>CmdSubmitted, C1=>PHI2r3, B1=>PHI2r2, A1=>InitReady, 
+                D0=>CmdSubmitted_1_sqmuxa, A0=>CmdSubmitted, DI0=>N_460_0, 
+                CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
+    SLICE_26I: SLICE_26
+      port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4, 
+                D0=>n8MEGEN, C0=>Cmdn8MEGEN_4_u_i_0, A0=>N_152, DI0=>N_19_i, 
+                CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN, 
+                F1=>Cmdn8MEGEN_4_u_i_0);
+    SLICE_29I: SLICE_29
+      port map (D1=>N_160, C1=>N_155, B1=>nRRAS_5_u_i_0, A1=>IS_0, C0=>N_155, 
+                B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i, 
+                Q0=>IS_0, F1=>N_24);
+    SLICE_30I: SLICE_30
+      port map (D1=>IS_0, C1=>IS_2, A1=>IS_1, D0=>IS_0, A0=>IS_1, 
+                DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
+    SLICE_31I: SLICE_31
+      port map (D1=>IS_2, C1=>N_159, B1=>IS_1, A1=>IS_3, D0=>IS_2, C0=>IS_3, 
+                B0=>IS_1, A0=>IS_0, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c, 
+                F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
+    SLICE_32I: SLICE_32
+      port map (D1=>N_126, C1=>InitReady, B1=>UFMSDI_ens2_i_a2_4_2, A1=>N_51, 
+                D0=>InitReady3, A0=>InitReady, DI0=>N_461_0, CLK=>RCLK_c, 
+                F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
+    SLICE_33I: SLICE_33
+      port map (D1=>LEDEN, C1=>nCRAS_c, A1=>CBR, D0=>InitReady, B0=>CmdLEDEN, 
+                A0=>UFMSDO_c, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70, 
+                Q0=>LEDEN, F1=>LED_c);
+    SLICE_39I: SLICE_39
+      port map (D1=>XOR8MEG, B1=>un1_Din_4, D0=>XOR8MEG, B0=>Din_c_6, 
+                A0=>n8MEGEN, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c, 
+                F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
+    SLICE_41I: SLICE_41
+      port map (D1=>CO0, C1=>FWEr_fast, B1=>CASr2, A1=>S_1, D0=>CBR, 
+                C0=>RCKEEN_8_u_1, B0=>Ready, A0=>RCKEEN_8_u_0_0, DI0=>RCKEEN_8, 
+                M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, 
+                F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
+    SLICE_42I: SLICE_42
+      port map (D1=>IS_1, C1=>IS_2, B1=>IS_0, A1=>RASr2, D0=>RASr, C0=>RASr3, 
+                B0=>RCKEEN, A0=>RASr2, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c, 
+                F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
+    SLICE_43I: SLICE_43
+      port map (D1=>Ready, C1=>S_0_i_o2_1, B1=>RASr2, A1=>InitReady, D0=>Ready, 
+                C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>InitReady, 
+                DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready, 
+                F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
+    SLICE_44I: SLICE_44
+      port map (D1=>Ready, C1=>N_165, B1=>Ready_0_sqmuxa_0_a3_2, A1=>InitReady, 
+                B0=>Ready_0_sqmuxa, A0=>Ready_fast, DI0=>N_463_0, M1=>nCRAS_c, 
+                CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa, 
+                Q1=>RASr);
+    SLICE_50I: SLICE_50
+      port map (D1=>Ready, C1=>CO0, A1=>S_1, C0=>CO0, A0=>S_1, DI0=>S_0_i_o2_1, 
+                LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, 
+                F1=>nRRAS_0_sqmuxa);
+    SLICE_51I: SLICE_51
+      port map (D1=>CmdUFMCLK, C1=>InitReady, B1=>N_129, A1=>UFMCLK_r_i_a2_2_2, 
+                D0=>N_139_i, C0=>UFMCLK_r_i_m4_xx_mm_1, B0=>nUFMCS15, 
+                A0=>UFMCLK_c, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c, 
+                F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1, 
+                Q1=>RASr2);
+    SLICE_52I: SLICE_52
+      port map (D1=>PHI2r3, C1=>InitReady, B1=>PHI2r2, A1=>CmdSubmitted, 
+                D0=>UFMSDI_r_xx_mm_1, C0=>N_139_i, B0=>UFMSDI_c, A0=>nUFMCS15, 
+                DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO, 
+                Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
+    SLICE_55I: SLICE_55
+      port map (D0=>RowA_4, B0=>nRowColSel, A0=>MAin_c_4, M1=>Din_c_5, 
+                M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
+    SLICE_56I: SLICE_56
+      port map (D1=>Bank_5, C1=>Bank_2, B1=>Bank_6, A1=>Bank_7, D0=>FS_5, 
+                C0=>FS_9, A0=>FS_7, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, 
+                F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
+    SLICE_57I: SLICE_57
+      port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0, 
+                D0=>Din_c_1, C0=>XOR8MEG_3_u_0_a3_2, B0=>LEDEN, A0=>N_171, 
+                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
+                Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
+    SLICE_58I: SLICE_58
+      port map (D1=>N_51, C1=>FS_8, A1=>InitReady, D0=>UFMSDO_c, 
+                B0=>Cmdn8MEGEN, A0=>InitReady, DI0=>N_69, CE=>N_31, 
+                CLK=>RCLK_c, F0=>N_69, Q0=>n8MEGEN, F1=>N_151);
+    SLICE_59I: SLICE_59
+      port map (D1=>Ready, C1=>S_1, B1=>N_155, A1=>N_160, D0=>N_41, 
+                C0=>nRCAS_0_sqmuxa_1, B0=>S_1, A0=>g0_1, DI0=>N_37_i, 
+                CLK=>RCLK_c, F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
+    SLICE_60I: SLICE_60
+      port map (D1=>CASr3, C1=>CO0, B1=>FWEr_fast, A1=>CASr2, D0=>CBR, 
+                C0=>RCKEEN_8_u_0_a2_1_out, B0=>N_24, A0=>N_28_i_1, DI0=>N_28_i, 
+                CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
+    SLICE_61I: SLICE_61
+      port map (D1=>S_0_i_o2_1, C1=>Ready, B1=>RASr2, A1=>RCKE_c, D0=>N_160, 
+                C0=>N_155, B0=>nRRAS_5_u_i_0, A0=>IS_0, DI0=>N_24_i, 
+                CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
+    SLICE_62I: SLICE_62
+      port map (D1=>CBR_fast, C1=>S_0_i_o2_1, B1=>Ready, A1=>RASr2, D0=>FWEr, 
+                C0=>m18_0_a2_1, B0=>nRCAS_0_sqmuxa_1, A0=>G_17_1, DI0=>N_39_i, 
+                CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c, F1=>nRCAS_0_sqmuxa_1);
+    SLICE_63I: SLICE_63
+      port map (D1=>CASr3, C1=>Ready, B1=>FWEr, A1=>CBR, D0=>N_179, C0=>Ready, 
+                B0=>CO0, A0=>S_1, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
+                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
+    SLICE_64I: SLICE_64
+      port map (D1=>FS_10, C1=>N_51, B1=>FS_11, A1=>InitReady, D0=>nUFMCS_c, 
+                C0=>nUFMCS_s_0_N_5_i_N_2L1, B0=>nUFMCS15, A0=>N_139_i, 
+                DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, F0=>nUFMCS_s_0_N_5_i, 
+                Q0=>nUFMCS_c, F1=>nUFMCS15);
+    nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
+      port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>S_1, 
+                C0=>m18_0_a3_3, B0=>CO0, A0=>InitReady, M0=>Ready, 
+                OFX0=>m18_0_a2_1);
+    SLICE_66I: SLICE_66
+      port map (C1=>InitReady, B1=>CmdUFMCS, A1=>UFMCLK_r_i_a2_2_2, D0=>N_95_5, 
+                C0=>InitReady, B0=>FS_16, A0=>N_95_3, M1=>MAin_c_1, 
+                M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1, 
+                Q1=>RowA_1);
+    SLICE_67I: SLICE_67
+      port map (D1=>Din_c_5, C1=>XOR8MEG18, B1=>Din_c_3, A1=>N_128, 
+                D0=>MAin_c_1, C0=>MAin_c_0, B0=>CmdEnable, A0=>N_147, 
+                M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>XOR8MEG18, Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
+    SLICE_68I: SLICE_68
+      port map (D1=>FS_3, C1=>FS_0, B1=>FS_2, A1=>FS_5, D0=>N_136, C0=>N_137_8, 
+                B0=>un1_FS_14_i_a2_0_1, A0=>N_137_6, F0=>N_31, 
+                F1=>un1_FS_14_i_a2_0_1);
+    SLICE_69I: SLICE_69
+      port map (D1=>FS_3, C1=>FS_0, B1=>FS_2, A1=>FS_5, D0=>N_137_8, 
+                C0=>un1_FS_13_i_a2_1, B0=>N_136, A0=>N_137_6, F0=>N_33, 
+                F1=>un1_FS_13_i_a2_1);
+    SLICE_70I: SLICE_70
+      port map (D1=>Bank_0, C1=>C1WR_0_a2_0_10, B1=>C1WR_0_a2_0_11, A1=>Bank_1, 
+                C0=>MAin_c_1, B0=>N_147, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
+                F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
+    SLICE_71I: SLICE_71
+      port map (D1=>MAin_c_5, C1=>MAin_c_7, B1=>MAin_c_6, A1=>MAin_c_4, 
+                D0=>C1WR_0_a2_0_4, C0=>Bank_3, B0=>Bank_4, A0=>C1WR_0_a2_0_3, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10, 
+                Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
+    SLICE_72I: SLICE_72
+      port map (D1=>UFMSDI_ens2_i_o2_0_3, C1=>FS_16, A1=>FS_12, D0=>FS_1, 
+                C0=>N_51, B0=>FS_11, A0=>FS_4, M1=>MAin_c_3, M0=>MAin_c_2, 
+                LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51, 
+                Q1=>RowA_3);
+    SLICE_73I: SLICE_73
+      port map (D1=>S_1, C1=>RASr2, B1=>CO0, A1=>InitReady, B0=>N_155, 
+                A0=>Ready, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, 
+                CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
+    SLICE_74I: SLICE_74
+      port map (D1=>FS_14, B1=>FS_11, D0=>FS_16, C0=>N_95_3, B0=>FS_10, 
+                A0=>N_95_5, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
+                F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
+    SLICE_75I: SLICE_75
+      port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, D0=>Din_c_1, C0=>N_128, 
+                A0=>Din_c_5, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133, 
+                Q0=>CASr, F1=>N_128, Q1=>CASr2);
+    SLICE_76I: SLICE_76
+      port map (D1=>Din_c_5, B1=>Din_c_0, D0=>MAin_c_0, C0=>CmdEnable16_4, 
+                B0=>Din_c_1, A0=>Din_c_3, M1=>Din_c_5, M0=>Din_c_4, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4, 
+                F1=>CmdEnable16_4, Q1=>Bank_5);
+    SLICE_77I: SLICE_77
+      port map (C1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>CmdEnable16_1, 
+                B0=>Din_c_6, A0=>Din_c_2, M1=>Din_c_7, M0=>Din_c_6, 
+                CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6, 
+                F1=>CmdEnable16_1, Q1=>Bank_7);
+    SLICE_78I: SLICE_78
+      port map (C1=>Din_c_3, B1=>Din_c_5, D0=>MAin_c_1, C0=>Din_c_6, B0=>N_43, 
+                A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c, 
+                F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
+    SLICE_79I: SLICE_79
+      port map (D1=>CASr3, C1=>Ready, B1=>CASr2, D0=>CO0, C0=>m6_0_a2_2, 
+                B0=>CBR, A0=>S_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, 
+                F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
+    SLICE_80I: SLICE_80
+      port map (C1=>CASr2, B1=>CASr3, D0=>FWEr, C0=>CBR_fast, B0=>g4_0_0_0, 
+                A0=>CO0, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
+    SLICE_81I: SLICE_81
+      port map (D1=>FS_14, C1=>FS_17, B1=>FS_15, A1=>FS_13, D0=>FS_12, 
+                C0=>FS_17, B0=>FS_15, A0=>FS_13, M1=>nFWE_c, M0=>nFWE_c, 
+                CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3, 
+                Q1=>FWEr_fast);
+    SLICE_82I: SLICE_82
+      port map (D1=>Din_c_5, C1=>CmdLEDEN, B1=>N_128, A1=>Din_c_3, D0=>Din_c_5, 
+                C0=>XOR8MEG18, B0=>N_128, A0=>Din_c_3, M0=>CASr2, CLK=>RCLK_c, 
+                F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
+    SLICE_83I: SLICE_83
+      port map (C1=>IS_2, B1=>IS_3, A1=>IS_1, D0=>IS_0, C0=>IS_2, A0=>IS_1, 
+                M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c, 
+                F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
+    SLICE_84I: SLICE_84
+      port map (D1=>FS_8, C1=>FS_10, B1=>FS_11, A1=>FS_6, D0=>FS_7, C0=>FS_1, 
+                B0=>FS_10, A0=>FS_6, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
+    SLICE_85I: SLICE_85
+      port map (D1=>Din_c_1, C1=>Din_c_7, B1=>Din_c_4, A1=>Din_c_0, 
+                D0=>Din_c_6, C0=>Din_c_7, B0=>Din_c_4, A0=>Din_c_5, 
+                M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4, 
+                Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
+    SLICE_86I: SLICE_86
+      port map (C1=>MAin_c_9, A1=>nRowColSel, C0=>MAin_c_9, B0=>RowA_9, 
+                A0=>nRowColSel, F0=>RA_c_9, F1=>RDQML_c);
+    SLICE_87I: SLICE_87
+      port map (D1=>UFMSDI_ens2_i_a0, C1=>CmdUFMSDI, B1=>N_151, D0=>N_151, 
+                C0=>FS_9, B0=>FS_11, A0=>FS_4, F0=>N_137_8, 
+                F1=>UFMSDI_r_xx_mm_1);
+    SLICE_88I: SLICE_88
+      port map (C1=>nFWE_c, B1=>MAin_c_2, A1=>MAin_c_3, D0=>nCCAS_c, 
+                C0=>nFWE_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast, 
+                CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3, 
+                Q1=>RowA_7);
+    SLICE_89I: SLICE_89
+      port map (D1=>nRowColSel, C1=>MAin_c_9, D0=>nRowColSel, C0=>MAin_c_8, 
+                B0=>RowA_8, F0=>RA_c_8, F1=>RDQMH_c);
+    SLICE_90I: SLICE_90
+      port map (C1=>N_147, B1=>MAin_c_0, A1=>MAin_c_1, D0=>RowA_0, 
+                B0=>MAin_c_0, A0=>nRowColSel, F0=>RA_c_0, F1=>un1_CMDWR);
+    SLICE_91I: SLICE_91
+      port map (D1=>nRowColSel, C1=>RowA_7, B1=>MAin_c_7, D0=>RowA_1, 
+                C0=>nRowColSel, B0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
+    SLICE_92I: SLICE_92
+      port map (D1=>nRowColSel, C1=>MAin_c_6, A1=>RowA_6, D0=>nRowColSel, 
+                C0=>RowA_2, B0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
+    SLICE_93I: SLICE_93
+      port map (D1=>RowA_5, B1=>nRowColSel, A1=>MAin_c_5, D0=>RowA_3, 
+                B0=>nRowColSel, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
+    SLICE_94I: SLICE_94
+      port map (D1=>Ready, C1=>N_155, D0=>Ready, C0=>S_1, M0=>IS_0, 
+                LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out, 
+                Q0=>RA_c_10, F1=>N_159_i);
+    RD_0_I: RD_0_B
+      port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
+    Dout_0_I: Dout_0_B
+      port map (PADDO=>RD_in_0, Dout0=>Dout(0));
+    PHI2I: PHI2B
+      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
+    UFMSDOI: UFMSDOB
+      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
+    UFMSDII: UFMSDIB
+      port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
+    UFMCLKI: UFMCLKB
+      port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
+    nUFMCSI: nUFMCSB
+      port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
+    RDQMLI: RDQMLB
+      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
+    RDQMHI: RDQMHB
+      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
+    nRCASI: nRCASB
+      port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
+    nRRASI: nRRASB
+      port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
+    nRWEI: nRWEB
+      port map (PADDO=>nRWE_c, nRWES=>nRWE);
+    RCKEI: RCKEB
+      port map (PADDO=>RCKE_c, RCKES=>RCKE);
+    RCLKI: RCLKB
+      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
+    nRCSI: nRCSB
+      port map (PADDO=>nRCS_c, nRCSS=>nRCS);
+    RD_7_I: RD_7_B
+      port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
+    RD_6_I: RD_6_B
+      port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
+    RD_5_I: RD_5_B
+      port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
+    RD_4_I: RD_4_B
+      port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
+    RD_3_I: RD_3_B
+      port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
+    RD_2_I: RD_2_B
+      port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
+    RD_1_I0: RD_1_B
+      port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
+    RA_11_I: RA_11_B
+      port map (PADDO=>RA_c_11, RA11=>RA(11));
+    RA_10_I: RA_10_B
+      port map (PADDO=>RA_c_10, RA10=>RA(10));
+    RA_9_I: RA_9_B
+      port map (PADDO=>RA_c_9, RA9=>RA(9));
+    RA_8_I: RA_8_B
+      port map (PADDO=>RA_c_8, RA8=>RA(8));
+    RA_7_I: RA_7_B
+      port map (PADDO=>RA_c_7, RA7=>RA(7));
+    RA_6_I: RA_6_B
+      port map (PADDO=>RA_c_6, RA6=>RA(6));
+    RA_5_I: RA_5_B
+      port map (PADDO=>RA_c_5, RA5=>RA(5));
+    RA_4_I: RA_4_B
+      port map (PADDO=>RA_c_4, RA4=>RA(4));
+    RA_3_I: RA_3_B
+      port map (PADDO=>RA_c_3, RA3=>RA(3));
+    RA_2_I: RA_2_B
+      port map (PADDO=>RA_c_2, RA2=>RA(2));
+    RA_1_I: RA_1_B
+      port map (PADDO=>RA_c_1, RA1=>RA(1));
+    RA_0_I: RA_0_B
+      port map (PADDO=>RA_c_0, RA0=>RA(0));
+    RBA_1_I: RBA_1_B
+      port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
+    RBA_0_I: RBA_0_B
+      port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
+    LEDI: LEDB
+      port map (PADDO=>LED_c, LEDS=>LED);
+    nFWEI: nFWEB
+      port map (PADDI=>nFWE_c, nFWES=>nFWE);
+    nCRASI: nCRASB
+      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
+    nCCASI: nCCASB
+      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
+    Dout_7_I: Dout_7_B
+      port map (PADDO=>RD_in_7, Dout7=>Dout(7));
+    Dout_6_I: Dout_6_B
+      port map (PADDO=>RD_in_6, Dout6=>Dout(6));
+    Dout_5_I: Dout_5_B
+      port map (PADDO=>RD_in_5, Dout5=>Dout(5));
+    Dout_4_I: Dout_4_B
+      port map (PADDO=>RD_in_4, Dout4=>Dout(4));
+    Dout_3_I: Dout_3_B
+      port map (PADDO=>RD_in_3, Dout3=>Dout(3));
+    Dout_2_I: Dout_2_B
+      port map (PADDO=>RD_in_2, Dout2=>Dout(2));
+    Dout_1_I: Dout_1_B
+      port map (PADDO=>RD_in_1, Dout1=>Dout(1));
+    Din_7_I: Din_7_B
+      port map (PADDI=>Din_c_7, Din7=>Din(7));
+    Din_6_I: Din_6_B
+      port map (PADDI=>Din_c_6, Din6=>Din(6));
+    Din_5_I: Din_5_B
+      port map (PADDI=>Din_c_5, Din5=>Din(5));
+    Din_4_I: Din_4_B
+      port map (PADDI=>Din_c_4, Din4=>Din(4));
+    Din_3_I: Din_3_B
+      port map (PADDI=>Din_c_3, Din3=>Din(3));
+    Din_2_I: Din_2_B
+      port map (PADDI=>Din_c_2, Din2=>Din(2));
+    Din_1_I: Din_1_B
+      port map (PADDI=>Din_c_1, Din1=>Din(1));
+    Din_0_I: Din_0_B
+      port map (PADDI=>Din_c_0, Din0=>Din(0));
+    CROW_1_I: CROW_1_B
+      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
+    CROW_0_I: CROW_0_B
+      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
+    MAin_9_I: MAin_9_B
+      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
+    MAin_8_I: MAin_8_B
+      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
+    MAin_7_I: MAin_7_B
+      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
+    MAin_6_I: MAin_6_B
+      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
+    MAin_5_I: MAin_5_B
+      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
+    MAin_4_I: MAin_4_B
+      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
+    MAin_3_I: MAin_3_B
+      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
+    MAin_2_I: MAin_2_B
+      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
+    MAin_1_I: MAin_1_B
+      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
+    MAin_0_I: MAin_0_B
+      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
+    VHI_INST: VHI
+      port map (Z=>VCCI);
+    PUR_INST: PUR
+      port map (PUR=>VCCI);
+    GSR_INST: GSR
+      port map (GSR=>VCCI);
+    VLO_INST: VLO
+      port map (Z=>GNDI_TSALL);
+    TSALL_INST: TSALL
+      port map (TSALL=>GNDI_TSALL);
+  end Structure;
+
+
+
+  library IEEE, vital2000, MACHXO;
+  configuration Structure_CON of RAM2GS is
+    for Structure
+    end for;
+  end Structure_CON;
+
+
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf
index d91dc50..281ca28 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf
@@ -1,2923 +1,2923 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Wed Aug 16 04:50:54 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 FCO (619:692:766)(619:692:766))
-        (IOPATH A0 FCO (713:797:882)(713:797:882))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-        (IOPATH FCI FCO (115:128:141)(115:128:141))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
-      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
-      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_30")
-    (INSTANCE SLICE_30)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_RNO_1_SLICE_65")
-    (INSTANCE nRWE_RNO_1\/SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
-        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
-        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-        (IOPATH CLK Q1 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (560:586:613)(560:586:613))
-        (IOPATH CLK Q1 (560:586:613)(560:586:613))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
-      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH B1 F1 (301:336:371)(301:336:371))
-        (IOPATH A1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH B0 F0 (301:336:371)(301:336:371))
-        (IOPATH A0 F0 (301:336:371)(301:336:371))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (301:336:371)(301:336:371))
-        (IOPATH C1 F1 (301:336:371)(301:336:371))
-        (IOPATH D0 F0 (301:336:371)(301:336:371))
-        (IOPATH C0 F0 (301:336:371)(301:336:371))
-        (IOPATH CLK Q0 (515:537:560)(515:537:560))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
-      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1000:1000:1000))
-      (WIDTH (negedge CLK) (1000:1000:1000))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_")
-    (INSTANCE RD\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD0) (1250:1250:1250))
-      (WIDTH (negedge RD0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_")
-    (INSTANCE Dout\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2")
-    (INSTANCE PHI2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2) (1250:1250:1250))
-      (WIDTH (negedge PHI2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDO")
-    (INSTANCE UFMSDO_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDO) (1250:1250:1250))
-      (WIDTH (negedge UFMSDO) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI")
-    (INSTANCE UFMSDI_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK")
-    (INSTANCE UFMCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCS")
-    (INSTANCE nUFMCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQML")
-    (INSTANCE RDQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMH")
-    (INSTANCE RDQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCAS")
-    (INSTANCE nRCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRAS")
-    (INSTANCE nRRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE")
-    (INSTANCE RCKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLK")
-    (INSTANCE RCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLK) (1250:1250:1250))
-      (WIDTH (negedge RCLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCS")
-    (INSTANCE nRCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_")
-    (INSTANCE RD\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD7) (1250:1250:1250))
-      (WIDTH (negedge RD7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_")
-    (INSTANCE RD\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD6) (1250:1250:1250))
-      (WIDTH (negedge RD6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_")
-    (INSTANCE RD\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD5) (1250:1250:1250))
-      (WIDTH (negedge RD5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_")
-    (INSTANCE RD\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD4) (1250:1250:1250))
-      (WIDTH (negedge RD4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_")
-    (INSTANCE RD\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD3) (1250:1250:1250))
-      (WIDTH (negedge RD3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_")
-    (INSTANCE RD\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD2) (1250:1250:1250))
-      (WIDTH (negedge RD2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_")
-    (INSTANCE RD\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
-          (3001:3001:3001)(3001:3001:3001))
-        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
-        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RD1) (1250:1250:1250))
-      (WIDTH (negedge RD1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_")
-    (INSTANCE RBA\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_")
-    (INSTANCE RBA\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "LED")
-    (INSTANCE LED_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWE")
-    (INSTANCE nFWE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWE) (1250:1250:1250))
-      (WIDTH (negedge nFWE) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRAS")
-    (INSTANCE nCRAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRAS) (1250:1250:1250))
-      (WIDTH (negedge nCRAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCAS")
-    (INSTANCE nCCAS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCAS) (1250:1250:1250))
-      (WIDTH (negedge nCCAS) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_")
-    (INSTANCE Dout\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_")
-    (INSTANCE Dout\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_")
-    (INSTANCE Dout\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_")
-    (INSTANCE Dout\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_")
-    (INSTANCE Dout\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_")
-    (INSTANCE Dout\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_")
-    (INSTANCE Dout\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_")
-    (INSTANCE Din\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (1250:1250:1250))
-      (WIDTH (negedge Din7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_")
-    (INSTANCE Din\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (1250:1250:1250))
-      (WIDTH (negedge Din6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_")
-    (INSTANCE Din\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (1250:1250:1250))
-      (WIDTH (negedge Din5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_")
-    (INSTANCE Din\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (1250:1250:1250))
-      (WIDTH (negedge Din4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_")
-    (INSTANCE Din\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (1250:1250:1250))
-      (WIDTH (negedge Din3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_")
-    (INSTANCE Din\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (1250:1250:1250))
-      (WIDTH (negedge Din2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_")
-    (INSTANCE Din\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (1250:1250:1250))
-      (WIDTH (negedge Din1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_")
-    (INSTANCE Din\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (1250:1250:1250))
-      (WIDTH (negedge Din0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_")
-    (INSTANCE CROW\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (1250:1250:1250))
-      (WIDTH (negedge CROW1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_")
-    (INSTANCE CROW\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (1250:1250:1250))
-      (WIDTH (negedge CROW0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_")
-    (INSTANCE MAin\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (1250:1250:1250))
-      (WIDTH (negedge MAin9) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_")
-    (INSTANCE MAin\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (1250:1250:1250))
-      (WIDTH (negedge MAin8) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_")
-    (INSTANCE MAin\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (1250:1250:1250))
-      (WIDTH (negedge MAin7) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_")
-    (INSTANCE MAin\[6\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (1250:1250:1250))
-      (WIDTH (negedge MAin6) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_")
-    (INSTANCE MAin\[5\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (1250:1250:1250))
-      (WIDTH (negedge MAin5) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_")
-    (INSTANCE MAin\[4\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (1250:1250:1250))
-      (WIDTH (negedge MAin4) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_")
-    (INSTANCE MAin\[3\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (1250:1250:1250))
-      (WIDTH (negedge MAin3) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_")
-    (INSTANCE MAin\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (1250:1250:1250))
-      (WIDTH (negedge MAin2) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_")
-    (INSTANCE MAin\[1\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (1250:1250:1250))
-      (WIDTH (negedge MAin1) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_")
-    (INSTANCE MAin\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (1250:1250:1250))
-      (WIDTH (negedge MAin0) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_0/Q1 SLICE_72/D0 (1405:1526:1647)(1405:1526:1647))
-        (INTERCONNECT SLICE_0/Q1 SLICE_84/C0 (754:836:918)(754:836:918))
-        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_0/Q0 SLICE_68/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_0/Q0 SLICE_69/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (732:1078:1425)(732:1078:1425))
-        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/C1 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_1/Q0 SLICE_66/B0 (917:1024:1131)(917:1024:1131))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_1/Q0 SLICE_74/D0 (602:670:739)(602:670:739))
-        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/D1 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_2/Q0 SLICE_81/D1 (1002:1094:1186)(1002:1094:1186))
-        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_3/Q1 SLICE_81/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_3/Q0 SLICE_81/D0 (963:1075:1187)(963:1075:1187))
-        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (1823:1986:2149)(1823:1986:2149))
-        (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1823:1986:2149)(1823:1986:2149))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (923:1026:1129)(923:1026:1129))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/D1 (1404:1527:1650)(1404:1527:1650))
-        (INTERCONNECT SLICE_4/Q0 SLICE_74/B0 (913:1016:1120)(913:1016:1120))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1560:1708:1856)(1560:1708:1856))
-        (INTERCONNECT SLICE_4/Q0 SLICE_84/B0 (913:1016:1120)(913:1016:1120))
-        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (2087:2267:2448)(2087:2267:2448))
-        (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (754:836:918)(754:836:918))
-        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_5/Q0 SLICE_58/C1 (1149:1260:1372)(1149:1260:1372))
-        (INTERCONNECT SLICE_5/Q0 SLICE_84/D1 (1397:1518:1640)(1397:1518:1640))
-        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_6/Q1 SLICE_56/A0 (2201:2394:2587)(2201:2394:2587))
-        (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725))
-        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (1225:1371:1517)(1225:1371:1517))
-        (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (1225:1371:1517)(1225:1371:1517))
-        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1803:1960:2118)(1803:1960:2118))
-        (INTERCONNECT SLICE_7/Q1 SLICE_68/A1 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_7/Q1 SLICE_69/A1 (862:958:1054)(862:958:1054))
-        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_7/Q0 SLICE_72/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1271:1394:1518)(1271:1394:1518))
-        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8/Q1 SLICE_68/D1 (876:974:1072)(876:974:1072))
-        (INTERCONNECT SLICE_8/Q1 SLICE_69/D1 (876:974:1072)(876:974:1072))
-        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (903:1005:1108)(903:1005:1108))
-        (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_70/F1 SLICE_9/C1 (769:851:933)(769:851:933))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (778:861:945)(778:861:945))
-        (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (1295:1420:1545)(1295:1420:1545))
-        (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (606:674:742)(606:674:742))
-        (INTERCONNECT SLICE_70/F1 SLICE_90/C1 (769:851:933)(769:851:933))
-        (INTERCONNECT SLICE_85/F1 SLICE_9/B1 (2100:2300:2500)(2100:2300:2500))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (1802:1995:2189)(1802:1995:2189))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1606:1757:1909)(1606:1757:1909))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (2131:2353:2575)(2131:2353:2575))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (2379:2611:2843)(2379:2611:2843))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (1395:1576:1757)(1395:1576:1757))
-        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B0 (1395:1576:1757)(1395:1576:1757))
-        (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634))
-        (INTERCONNECT SLICE_9/Q0 SLICE_20/A1 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_70/F0 SLICE_9/C0 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_9/F1 SLICE_9/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_14/F1 SLICE_9/A0 (1263:1387:1511)(1263:1387:1511))
-        (INTERCONNECT SLICE_14/F1 SLICE_14/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (1301:1429:1558)(1301:1429:1558))
-        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2017:2199:2381)(2017:2199:2381))
-        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2497:3089:3682)(2497:3089:3682))
-        (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (837:931:1026)(837:931:1026))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/B0 (1984:2189:2395)(1984:2189:2395))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1925:2114:2304)(1925:2114:2304))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/D0 (1636:1793:1950)(1636:1793:1950))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/C0 (2423:2682:2941)(2423:2682:2941))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (2046:2232:2419)(2046:2232:2419))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1522:1684:1847)(1522:1684:1847))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/A1 (2718:2965:3212)(2718:2965:3212))
-        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (2379:2611:2843)(2379:2611:2843))
-        (INTERCONNECT SLICE_14/Q0 SLICE_14/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_14/Q0 SLICE_20/C0 (1431:1576:1722)(1431:1576:1722))
-        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/D1 (571:629:687)(571:629:687))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (575:636:697)(575:636:697))
-        (INTERCONNECT SLICE_19/Q0 SLICE_41/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (808:893:978)(808:893:978))
-        (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (808:893:978)(808:893:978))
-        (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1211:1325:1439)(1211:1325:1439))
-        (INTERCONNECT SLICE_19/Q0 SLICE_63/B0 (968:1072:1177)(968:1072:1177))
-        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1236:1372:1509)(1236:1372:1509))
-        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1236:1372:1509)(1236:1372:1509))
-        (INTERCONNECT SLICE_19/Q0 SLICE_73/B1 (947:1054:1161)(947:1054:1161))
-        (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (653:719:785)(653:719:785))
-        (INTERCONNECT SLICE_19/Q0 SLICE_80/A0 (922:1019:1117)(922:1019:1117))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (788:872:957)(788:872:957))
-        (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (788:872:957)(788:872:957))
-        (INTERCONNECT SLICE_50/Q0 SLICE_41/A1 (1312:1438:1565)(1312:1438:1565))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (1839:2035:2231)(1839:2035:2231))
-        (INTERCONNECT SLICE_50/Q0 SLICE_59/B0 (1710:1891:2072)(1710:1891:2072))
-        (INTERCONNECT SLICE_50/Q0 SLICE_63/A0 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (1191:1322:1454)(1191:1322:1454))
-        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/D0 (633:698:764)(633:698:764))
-        (INTERCONNECT SLICE_50/Q0 SLICE_73/D1 (1332:1461:1591)(1332:1461:1591))
-        (INTERCONNECT SLICE_50/Q0 SLICE_79/A0 (839:930:1021)(839:930:1021))
-        (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2356:2575:2795)(2356:2575:2795))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/B1 (863:960:1057)(863:960:1057))
-        (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (810:899:989)(810:899:989))
-        (INTERCONNECT SLICE_31/Q0 SLICE_31/C0 (696:773:850)(696:773:850))
-        (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (863:960:1057)(863:960:1057))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/A1 (1282:1411:1540)(1282:1411:1540))
-        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (1320:1453:1587)(1320:1453:1587))
-        (INTERCONNECT SLICE_51/Q1 SLICE_42/A1 (1688:1854:2020)(1688:1854:2020))
-        (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (1688:1854:2020)(1688:1854:2020))
-        (INTERCONNECT SLICE_51/Q1 SLICE_43/B1 (1328:1464:1600)(1328:1464:1600))
-        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (1320:1453:1587)(1320:1453:1587))
-        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (889:990:1091)(889:990:1091))
-        (INTERCONNECT SLICE_51/Q1 SLICE_61/B1 (1726:1896:2067)(1726:1896:2067))
-        (INTERCONNECT SLICE_51/Q1 SLICE_62/A1 (2115:2317:2519)(2115:2317:2519))
-        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (582:647:712)(582:647:712))
-        (INTERCONNECT SLICE_51/Q1 SLICE_73/C1 (1571:1716:1862)(1571:1716:1862))
-        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/F1 SLICE_43/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (1394:1526:1659)(1394:1526:1659))
-        (INTERCONNECT SLICE_20/Q0 SLICE_20/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_20/Q0 SLICE_67/B0 (1409:1541:1674)(1409:1541:1674))
-        (INTERCONNECT SLICE_90/F1 SLICE_20/B0 (1286:1416:1547)(1286:1416:1547))
-        (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2758:3009:3261)(2758:3009:3261))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A0 (1511:1671:1831)(1511:1671:1831))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/D1 (1242:1370:1499)(1242:1370:1499))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1549:1713:1878)(1549:1713:1878))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2391:2619:2848)(2391:2619:2848))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D1 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D0 (1673:1834:1995)(1673:1834:1995))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/A0 (1876:2059:2243)(1876:2059:2243))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/C1 (1790:1964:2139)(1790:1964:2139))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/C1 (2200:2404:2608)(2200:2404:2608))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/B1 (1930:2123:2316)(1930:2123:2316))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (2355:2576:2798)(2355:2576:2798))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (2606:2857:3109)(2606:2857:3109))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/C1 (1790:1964:2139)(1790:1964:2139))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A1 (1904:2091:2278)(1904:2091:2278))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A0 (1904:2091:2278)(1904:2091:2278))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (1922:2112:2303)(1922:2112:2303))
-        (INTERCONNECT SLICE_75/F1 SLICE_21/B1 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (616:686:757)(616:686:757))
-        (INTERCONNECT SLICE_75/F1 SLICE_67/A1 (864:963:1063)(864:963:1063))
-        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_75/F1 SLICE_82/B1 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (931:1040:1149)(931:1040:1149))
-        (INTERCONNECT SLICE_21/F1 SLICE_21/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_33/Q0 SLICE_21/C0 (1644:1786:1929)(1644:1786:1929))
-        (INTERCONNECT SLICE_33/Q0 SLICE_33/D1 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (2611:2837:3063)(2611:2837:3063))
-        (INTERCONNECT SLICE_75/F0 SLICE_21/B0 (883:984:1086)(883:984:1086))
-        (INTERCONNECT SLICE_82/F1 SLICE_21/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F0 SLICE_21/CE (573:634:695)(573:634:695))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (573:634:695)(573:634:695))
-        (INTERCONNECT SLICE_67/F0 SLICE_57/CE (906:1005:1104)(906:1005:1104))
-        (INTERCONNECT SLICE_67/F0 SLICE_67/C1 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_67/F0 SLICE_82/C0 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_21/Q0 SLICE_33/B0 (1797:1958:2120)(1797:1958:2120))
-        (INTERCONNECT SLICE_21/Q0 SLICE_82/C1 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1157:1286:1415)(1157:1286:1415))
-        (INTERCONNECT SLICE_43/Q1 SLICE_22/C1 (1016:1133:1251)(1016:1133:1251))
-        (INTERCONNECT SLICE_43/Q1 SLICE_52/D1 (861:959:1058)(861:959:1058))
-        (INTERCONNECT SLICE_41/Q1 SLICE_22/B1 (1300:1432:1564)(1300:1432:1564))
-        (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (1695:1853:2012)(1695:1853:2012))
-        (INTERCONNECT SLICE_41/Q1 SLICE_52/B1 (1703:1864:2025)(1703:1864:2025))
-        (INTERCONNECT SLICE_32/Q0 SLICE_22/A1 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/C1 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_32/Q0 SLICE_33/D0 (1042:1139:1236)(1042:1139:1236))
-        (INTERCONNECT SLICE_32/Q0 SLICE_43/A1 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32/Q0 SLICE_43/A0 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32/Q0 SLICE_44/A1 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32/Q0 SLICE_51/C1 (1197:1313:1429)(1197:1313:1429))
-        (INTERCONNECT SLICE_32/Q0 SLICE_52/C1 (1197:1313:1429)(1197:1313:1429))
-        (INTERCONNECT SLICE_32/Q0 SLICE_58/A1 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32/Q0 SLICE_58/A0 (1714:1871:2028)(1714:1871:2028))
-        (INTERCONNECT SLICE_32/Q0 SLICE_64/A1 (1311:1439:1568)(1311:1439:1568))
-        (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (887:984:1081)(887:984:1081))
-        (INTERCONNECT SLICE_32/Q0 SLICE_66/C1 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32/Q0 SLICE_66/C0 (710:788:867)(710:788:867))
-        (INTERCONNECT SLICE_32/Q0 SLICE_73/A1 (1304:1431:1559)(1304:1431:1559))
-        (INTERCONNECT SLICE_82/F0 SLICE_22/D0 (1778:1934:2090)(1778:1934:2090))
-        (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22/F1 SLICE_68/D0 (975:1068:1161)(975:1068:1161))
-        (INTERCONNECT SLICE_22/F1 SLICE_69/B0 (1290:1421:1553)(1290:1421:1553))
-        (INTERCONNECT SLICE_78/F1 SLICE_26/C1 (735:822:909)(735:822:909))
-        (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_26/Q0 SLICE_58/B0 (899:1000:1102)(899:1000:1102))
-        (INTERCONNECT SLICE_76/F1 SLICE_26/A1 (1348:1473:1599)(1348:1473:1599))
-        (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (580:648:716)(580:648:716))
-        (INTERCONNECT SLICE_58/Q0 SLICE_39/A0 (2063:2250:2438)(2063:2250:2438))
-        (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83/F1 SLICE_29/D1 (1406:1541:1676)(1406:1541:1676))
-        (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (2154:2337:2521)(2154:2337:2521))
-        (INTERCONNECT SLICE_83/F1 SLICE_61/D0 (1695:1864:2034)(1695:1864:2034))
-        (INTERCONNECT SLICE_73/F1 SLICE_29/C1 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73/F1 SLICE_29/C0 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73/F1 SLICE_59/B1 (1836:2003:2171)(1836:2003:2171))
-        (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1273:1392:1511)(1273:1392:1511))
-        (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_73/F1 SLICE_94/C1 (1680:1833:1986)(1680:1833:1986))
-        (INTERCONNECT SLICE_61/F1 SLICE_29/B1 (841:937:1034)(841:937:1034))
-        (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_29/Q0 SLICE_29/A1 (832:922:1012)(832:922:1012))
-        (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (623:687:752)(623:687:752))
-        (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (623:687:752)(623:687:752))
-        (INTERCONNECT SLICE_29/Q0 SLICE_31/A0 (1302:1427:1553)(1302:1427:1553))
-        (INTERCONNECT SLICE_29/Q0 SLICE_42/B1 (1703:1883:2063)(1703:1883:2063))
-        (INTERCONNECT SLICE_29/Q0 SLICE_61/A0 (832:922:1012)(832:922:1012))
-        (INTERCONNECT SLICE_29/Q0 SLICE_83/D0 (1033:1127:1221)(1033:1127:1221))
-        (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (2098:2304:2511)(2098:2304:2511))
-        (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (1347:1503:1660)(1347:1503:1660))
-        (INTERCONNECT SLICE_43/Q0 SLICE_41/B0 (948:1050:1153)(948:1050:1153))
-        (INTERCONNECT SLICE_43/Q0 SLICE_43/D1 (578:636:695)(578:636:695))
-        (INTERCONNECT SLICE_43/Q0 SLICE_43/D0 (578:636:695)(578:636:695))
-        (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (633:697:761)(633:697:761))
-        (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (632:700:769)(632:700:769))
-        (INTERCONNECT SLICE_43/Q0 SLICE_59/D1 (1435:1582:1729)(1435:1582:1729))
-        (INTERCONNECT SLICE_43/Q0 SLICE_61/C1 (1476:1647:1819)(1476:1647:1819))
-        (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2176:2379:2582)(2176:2379:2582))
-        (INTERCONNECT SLICE_43/Q0 SLICE_63/C1 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43/Q0 SLICE_63/C0 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (640:705:770)(640:705:770))
-        (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1191:1321:1451)(1191:1321:1451))
-        (INTERCONNECT SLICE_43/Q0 SLICE_79/C1 (801:890:980)(801:890:980))
-        (INTERCONNECT SLICE_43/Q0 SLICE_94/D1 (2271:2465:2659)(2271:2465:2659))
-        (INTERCONNECT SLICE_43/Q0 SLICE_94/D0 (2271:2465:2659)(2271:2465:2659))
-        (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_30/Q1 SLICE_30/C1 (696:773:850)(696:773:850))
-        (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (991:1107:1224)(991:1107:1224))
-        (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (991:1107:1224)(991:1107:1224))
-        (INTERCONNECT SLICE_30/Q1 SLICE_42/C1 (1560:1700:1840)(1560:1700:1840))
-        (INTERCONNECT SLICE_30/Q1 SLICE_83/C1 (1146:1281:1417)(1146:1281:1417))
-        (INTERCONNECT SLICE_30/Q1 SLICE_83/C0 (1146:1281:1417)(1146:1281:1417))
-        (INTERCONNECT SLICE_30/Q0 SLICE_30/A1 (825:914:1004)(825:914:1004))
-        (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682))
-        (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (943:1046:1150)(943:1046:1150))
-        (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (943:1046:1150)(943:1046:1150))
-        (INTERCONNECT SLICE_30/Q0 SLICE_42/D1 (1109:1203:1297)(1109:1203:1297))
-        (INTERCONNECT SLICE_30/Q0 SLICE_83/A1 (897:993:1090)(897:993:1090))
-        (INTERCONNECT SLICE_30/Q0 SLICE_83/A0 (897:993:1090)(897:993:1090))
-        (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_94/F1 SLICE_30/CE (1885:2046:2208)(1885:2046:2208))
-        (INTERCONNECT SLICE_94/F1 SLICE_31/CE (2184:2374:2565)(2184:2374:2565))
-        (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (1908:2070:2233)(1908:2070:2233))
-        (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1374:1495:1616)(1374:1495:1616))
-        (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (1172:1308:1444)(1172:1308:1444))
-        (INTERCONNECT SLICE_72/F1 SLICE_32/A1 (1239:1383:1527)(1239:1383:1527))
-        (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (541:599:657)(541:599:657))
-        (INTERCONNECT SLICE_72/F1 SLICE_64/C1 (1575:1727:1879)(1575:1727:1879))
-        (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (431:479:528)(431:479:528))
-        (INTERCONNECT SLICE_74/F0 SLICE_32/D0 (245:274:304)(245:274:304))
-        (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (245:274:304)(245:274:304))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_33/C1 (1635:1825:2016)(1635:1825:2016))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (1526:1687:1849)(1526:1687:1849))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (3109:3772:4435)(3109:3772:4435))
-        (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1758:1913:2068)(1758:1913:2068))
-        (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1892:2044:2197)(1892:2044:2197))
-        (INTERCONNECT SLICE_78/Q0 SLICE_60/D0 (1405:1538:1671)(1405:1538:1671))
-        (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1634:1807:1981)(1634:1807:1981))
-        (INTERCONNECT SLICE_78/Q0 SLICE_79/B0 (1969:2184:2399)(1969:2184:2399))
-        (INTERCONNECT UFMSDO_I/PADDI SLICE_33/A0 (1377:1528:1680)(1377:1528:1680))
-        (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (2317:2524:2731)(2317:2524:2731))
-        (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69/F0 SLICE_33/CE (1070:1165:1260)(1070:1165:1260))
-        (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_57/Q0 SLICE_39/D1 (1908:2070:2232)(1908:2070:2232))
-        (INTERCONNECT SLICE_57/Q0 SLICE_39/D0 (1908:2070:2232)(1908:2070:2232))
-        (INTERCONNECT SLICE_85/F0 SLICE_39/B1 (1792:1955:2118)(1792:1955:2118))
-        (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (1477:1601:1726)(1477:1601:1726))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/B0 (2577:2847:3118)(2577:2847:3118))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (2415:2652:2889)(2415:2652:2889))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A1 (2528:2792:3057)(2528:2792:3057))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/B0 (2695:2961:3228)(2695:2961:3228))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2387:2616:2845)(2387:2616:2845))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/C0 (2520:2764:3008)(2520:2764:3008))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/D0 (1973:2170:2368)(1973:2170:2368))
-        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1723:1881:2040)(1723:1881:2040))
-        (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667))
-        (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (910:1010:1110)(910:1010:1110))
-        (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1730:1889:2048)(1730:1889:2048))
-        (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1730:1889:2048)(1730:1889:2048))
-        (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (1320:1449:1579)(1320:1449:1579))
-        (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (910:1010:1110)(910:1010:1110))
-        (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1723:1881:2040)(1723:1881:2040))
-        (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (2170:2363:2556)(2170:2363:2556))
-        (INTERCONNECT SLICE_81/Q1 SLICE_41/C1 (2032:2205:2379)(2032:2205:2379))
-        (INTERCONNECT SLICE_81/Q1 SLICE_60/B1 (1789:1953:2117)(1789:1953:2117))
-        (INTERCONNECT SLICE_75/Q1 SLICE_41/B1 (1295:1427:1559)(1295:1427:1559))
-        (INTERCONNECT SLICE_75/Q1 SLICE_60/A1 (2074:2266:2459)(2074:2266:2459))
-        (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1717:1887:2058)(1717:1887:2058))
-        (INTERCONNECT SLICE_75/Q1 SLICE_80/C1 (1557:1708:1859)(1557:1708:1859))
-        (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (884:984:1085)(884:984:1085))
-        (INTERCONNECT SLICE_41/F1 SLICE_41/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_43/F1 SLICE_41/A0 (833:932:1032)(833:932:1032))
-        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1773:1932:2091)(1773:1932:2091))
-        (INTERCONNECT SLICE_41/Q0 SLICE_42/B0 (1781:1942:2104)(1781:1942:2104))
-        (INTERCONNECT SLICE_44/Q1 SLICE_42/D0 (1398:1530:1663)(1398:1530:1663))
-        (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (1386:1516:1646)(1386:1516:1646))
-        (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1621:1763:1905)(1621:1763:1905))
-        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 SLICE_61/A1 (1247:1371:1495)(1247:1371:1495))
-        (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/C1 (2228:2432:2636)(2228:2432:2636))
-        (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/C0 (1537:1688:1840)(1537:1688:1840))
-        (INTERCONNECT SLICE_50/F0 SLICE_43/C1 (750:837:924)(750:837:924))
-        (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (31:31:31)(31:31:31))
-        (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (970:1082:1195)(970:1082:1195))
-        (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1575:1727:1879)(1575:1727:1879))
-        (INTERCONNECT SLICE_83/F0 SLICE_43/C0 (681:758:835)(681:758:835))
-        (INTERCONNECT SLICE_83/F0 SLICE_44/C1 (739:821:903)(739:821:903))
-        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1335:1476:1617)(1335:1476:1617))
-        (INTERCONNECT SLICE_72/F0 SLICE_51/B1 (1781:1942:2104)(1781:1942:2104))
-        (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503))
-        (INTERCONNECT SLICE_66/F0 SLICE_66/A1 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_52/F1 SLICE_51/D0 (877:975:1074)(877:975:1074))
-        (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_52/F1 SLICE_64/A0 (857:952:1048)(857:952:1048))
-        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (868:962:1057)(868:962:1057))
-        (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727))
-        (INTERCONNECT SLICE_51/Q0 SLICE_51/A0 (530:591:652)(530:591:652))
-        (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1184:1361:1538)(1184:1361:1538))
-        (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (932:1044:1156)(932:1044:1156))
-        (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/Q0 SLICE_55/D0 (1466:1589:1712)(1466:1589:1712))
-        (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (2114:2313:2513)(2114:2313:2513))
-        (INTERCONNECT SLICE_63/Q0 SLICE_86/A1 (1678:1840:2002)(1678:1840:2002))
-        (INTERCONNECT SLICE_63/Q0 SLICE_86/A0 (1678:1840:2002)(1678:1840:2002))
-        (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (2224:2421:2618)(2224:2421:2618))
-        (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (2224:2421:2618)(2224:2421:2618))
-        (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (1802:1970:2138)(1802:1970:2138))
-        (INTERCONNECT SLICE_63/Q0 SLICE_91/D1 (1796:1956:2117)(1796:1956:2117))
-        (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (1954:2134:2314)(1954:2134:2314))
-        (INTERCONNECT SLICE_63/Q0 SLICE_92/D1 (2320:2504:2689)(2320:2504:2689))
-        (INTERCONNECT SLICE_63/Q0 SLICE_92/D0 (2320:2504:2689)(2320:2504:2689))
-        (INTERCONNECT SLICE_63/Q0 SLICE_93/B1 (2543:2782:3021)(2543:2782:3021))
-        (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2543:2782:3021)(2543:2782:3021))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/A0 (2220:2446:2672)(2220:2446:2672))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (2701:2972:3244)(2701:2972:3244))
-        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/A1 (2663:2930:3197)(2663:2930:3197))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2067:2260:2454)(2067:2260:2454))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/C1 (1378:1524:1670)(1378:1524:1670))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1530:1693:1856)(1530:1693:1856))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/A1 (2732:2985:3238)(2732:2985:3238))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B1 (1973:2177:2381)(1973:2177:2381))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B0 (1973:2177:2381)(1973:2177:2381))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (1242:1370:1498)(1242:1370:1498))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2109:2309:2510)(2109:2309:2510))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (1503:1660:1818)(1503:1660:1818))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (2373:2602:2831)(2373:2602:2831))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (2373:2602:2831)(2373:2602:2831))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (1706:1877:2049)(1706:1877:2049))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1706:1877:2049)(1706:1877:2049))
-        (INTERCONNECT nCCAS_I/PADDI SLICE_88/D0 (2063:2255:2448)(2063:2255:2448))
-        (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (2378:2648:2918)(2378:2648:2918))
-        (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475))
-        (INTERCONNECT SLICE_76/Q1 SLICE_56/D1 (1498:1630:1763)(1498:1630:1763))
-        (INTERCONNECT SLICE_71/Q0 SLICE_56/C1 (1653:1804:1956)(1653:1804:1956))
-        (INTERCONNECT SLICE_77/Q0 SLICE_56/B1 (1813:1984:2155)(1813:1984:2155))
-        (INTERCONNECT SLICE_77/Q1 SLICE_56/A1 (2138:2321:2505)(2138:2321:2505))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2264:2497:2730)(2264:2497:2730))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/B1 (1828:2016:2205)(1828:2016:2205))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/C1 (1272:1412:1553)(1272:1412:1553))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (1424:1581:1739)(1424:1581:1739))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C1 (2522:2767:3013)(2522:2767:3013))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C0 (2522:2767:3013)(2522:2767:3013))
-        (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1813:1984:2155)(1813:1984:2155))
-        (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1547:1713:1879)(1547:1713:1879))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1539:1702:1866)(1539:1702:1866))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1921:2109:2298)(1921:2109:2298))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1904:2092:2280)(1904:2092:2280))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1904:2092:2280)(1904:2092:2280))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (2324:2541:2759)(2324:2541:2759))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/A1 (1891:2077:2264)(1891:2077:2264))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (2325:2544:2764)(2325:2544:2764))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (1529:1691:1854)(1529:1691:1854))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/B1 (1937:2130:2324)(1937:2130:2324))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (2739:2994:3250)(2739:2994:3250))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/A1 (2297:2513:2729)(2297:2513:2729))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (1217:1343:1469)(1217:1343:1469))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (714:807:900)(714:807:900))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1521:1678:1835)(1521:1678:1835))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1217:1343:1469)(1217:1343:1469))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1421:1579:1738)(1421:1579:1738))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (1959:2159:2360)(1959:2159:2360))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/D1 (1941:2140:2339)(1941:2140:2339))
-        (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (1544:1731:1919)(1544:1731:1919))
-        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (940:1054:1169)(940:1054:1169))
-        (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_62/F1 SLICE_59/C0 (1669:1820:1972)(1669:1820:1972))
-        (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (576:644:712)(576:644:712))
-        (INTERCONNECT SLICE_80/F0 SLICE_59/A0 (1201:1344:1488)(1201:1344:1488))
-        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_82/Q0 SLICE_60/D1 (1509:1643:1777)(1509:1643:1777))
-        (INTERCONNECT SLICE_82/Q0 SLICE_63/D1 (1491:1617:1743)(1491:1617:1743))
-        (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (1491:1617:1743)(1491:1617:1743))
-        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (2209:2402:2596)(2209:2402:2596))
-        (INTERCONNECT SLICE_94/F0 SLICE_60/C0 (1529:1669:1809)(1529:1669:1809))
-        (INTERCONNECT SLICE_60/F1 SLICE_60/A0 (779:868:958)(779:868:958))
-        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (1291:1473:1656)(1291:1473:1656))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1935:2190:2445)(1935:2190:2445))
-        (INTERCONNECT SLICE_78/Q1 SLICE_62/D1 (1079:1173:1267)(1079:1173:1267))
-        (INTERCONNECT SLICE_78/Q1 SLICE_80/C0 (1637:1779:1921)(1637:1779:1921))
-        (INTERCONNECT SLICE_81/Q0 SLICE_62/D0 (1679:1834:1990)(1679:1834:1990))
-        (INTERCONNECT SLICE_81/Q0 SLICE_63/B1 (1691:1860:2030)(1691:1860:2030))
-        (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1376:1507:1638)(1376:1507:1638))
-        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/C0 (1653:1804:1956)
-          (1653:1804:1956))
-        (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1651:1815:1979)(1651:1815:1979))
-        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (2095:2345:2595)(2095:2345:2595))
-        (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/Q0 SLICE_64/D0 (526:584:642)(526:584:642))
-        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1548:1774:2000)(1548:1774:2000))
-        (INTERCONNECT SLICE_66/F1 SLICE_64/C0 (1529:1669:1809)(1529:1669:1809))
-        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q1 SLICE_66/B1 (1247:1397:1548)(1247:1397:1548))
-        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (1383:1512:1642)(1383:1512:1642))
-        (INTERCONNECT SLICE_81/F0 SLICE_74/A0 (1652:1813:1974)(1652:1813:1974))
-        (INTERCONNECT SLICE_74/F1 SLICE_66/A0 (795:884:974)(795:884:974))
-        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (416:464:513)(416:464:513))
-        (INTERCONNECT SLICE_66/Q0 SLICE_90/D0 (1375:1502:1629)(1375:1502:1629))
-        (INTERCONNECT SLICE_66/Q1 SLICE_91/D0 (1901:2062:2224)(1901:2062:2224))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (1621:1774:1928)(1621:1774:1928))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/D1 (1614:1766:1919)(1614:1766:1919))
-        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/A1 (1908:2101:2294)(1908:2101:2294))
-        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (947:1062:1178)(947:1062:1178))
-        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (1350:1494:1639)(1350:1494:1639))
-        (INTERCONNECT SLICE_67/Q1 SLICE_93/D1 (1063:1157:1251)(1063:1157:1251))
-        (INTERCONNECT SLICE_87/F0 SLICE_68/C0 (735:822:909)(735:822:909))
-        (INTERCONNECT SLICE_87/F0 SLICE_69/D0 (580:648:716)(580:648:716))
-        (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_84/F0 SLICE_68/A0 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_84/F0 SLICE_69/A0 (786:876:966)(786:876:966))
-        (INTERCONNECT SLICE_69/F1 SLICE_69/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_70/Q0 SLICE_70/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (723:805:887)(723:805:887))
-        (INTERCONNECT SLICE_70/Q1 SLICE_70/A1 (514:575:636)(514:575:636))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/C1 (1805:1987:2169)(1805:1987:2169))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (1657:1821:1985)(1657:1821:1985))
-        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/B1 (2368:2598:2829)(2368:2598:2829))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/B1 (1951:2152:2353)(1951:2152:2353))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (2353:2581:2809)(2353:2581:2809))
-        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/C1 (3008:3283:3558)(3008:3283:3558))
-        (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (510:568:626)(510:568:626))
-        (INTERCONNECT SLICE_71/Q1 SLICE_71/C0 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (825:921:1018)(825:921:1018))
-        (INTERCONNECT SLICE_88/F1 SLICE_71/A0 (1490:1668:1846)(1490:1668:1846))
-        (INTERCONNECT SLICE_81/F1 SLICE_72/D1 (510:568:626)(510:568:626))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (1657:1821:1985)(1657:1821:1985))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/A1 (1919:2113:2308)(1919:2113:2308))
-        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (2322:2545:2769)(2322:2545:2769))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (1606:1757:1909)(1606:1757:1909))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/B1 (1519:1681:1844)(1519:1681:1844))
-        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/B0 (2326:2552:2779)(2326:2552:2779))
-        (INTERCONNECT SLICE_72/Q0 SLICE_92/C0 (1653:1804:1956)(1653:1804:1956))
-        (INTERCONNECT SLICE_72/Q1 SLICE_93/D0 (1466:1589:1712)(1466:1589:1712))
-        (INTERCONNECT SLICE_74/Q0 SLICE_87/C1 (665:742:819)(665:742:819))
-        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (528:587:647)(528:587:647))
-        (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (400:448:497)(400:448:497))
-        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (1164:1346:1528)(1164:1346:1528))
-        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (560:628:696)(560:628:696))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C1 (1769:1940:2112)(1769:1940:2112))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C0 (1769:1940:2112)(1769:1940:2112))
-        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2608:2849:3090)(2608:2849:3090))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828))
-        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/C0 (3001:3275:3550)(3001:3275:3550))
-        (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (1247:1397:1548)(1247:1397:1548))
-        (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (1378:1510:1643)(1378:1510:1643))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1654:1819:1984)(1654:1819:1984))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (2204:2414:2624)(2204:2414:2624))
-        (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (2204:2414:2624)(2204:2414:2624))
-        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (2038:2228:2418)(2038:2228:2418))
-        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (2307:2528:2750)(2307:2528:2750))
-        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
-        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2466:2735:3005)(2466:2735:3005))
-        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1568:1777:1987)(1568:1777:1987))
-        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (2477:2778:3080)(2477:2778:3080))
-        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1532:1758:1984)(1532:1758:1984))
-        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1756:2001:2247)(1756:2001:2247))
-        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2571:2883:3195)(2571:2883:3195))
-        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2571:2883:3195)(2571:2883:3195))
-        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2538:2838:3139)(2538:2838:3139))
-        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (2538:2838:3139)(2538:2838:3139))
-        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (1741:1997:2254)(1741:1997:2254))
-        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1741:1997:2254)(1741:1997:2254))
-        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (2098:2368:2638)(2098:2368:2638))
-        (INTERCONNECT SLICE_88/Q0 SLICE_92/A1 (1735:1889:2044)(1735:1889:2044))
-        (INTERCONNECT SLICE_88/Q1 SLICE_91/C1 (1218:1331:1444)(1218:1331:1444))
-        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1979:2229:2479)(1979:2229:2479))
-        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (1723:1947:2172)(1723:1947:2172))
-        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1971:2209:2448)(1971:2209:2448))
-        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
-        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (1168:1345:1522)(1168:1345:1522))
-        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1610:1831:2052)(1610:1831:2052))
-        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475))
-        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (646:731:817)(646:731:817))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2942:3272:3602)(2942:3272:3602))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2505:2806:3107)(2505:2806:3107))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2540:2847:3154)(2540:2847:3154))
-      )
-    )
-  )
-)
+(DELAYFILE
+  (SDFVERSION "3.0")
+  (DESIGN "RAM2GS")
+  (DATE "Sat Aug 19 20:57:25 2023")
+  (VENDOR "Lattice")
+  (PROGRAM "ldbanno")
+  (VERSION "Diamond (64-bit) 3.12.1.454")
+  (DIVIDER /)
+  (VOLTAGE 1.26:1.20:1.14)
+  (PROCESS "default")
+  (TEMPERATURE -40:25:85)
+  (TIMESCALE 1ps)
+  (CELL
+    (CELLTYPE "SLICE_0")
+    (INSTANCE SLICE_0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_1")
+    (INSTANCE SLICE_1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_2")
+    (INSTANCE SLICE_2)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_3")
+    (INSTANCE SLICE_3)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_4")
+    (INSTANCE SLICE_4)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_5")
+    (INSTANCE SLICE_5)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_6")
+    (INSTANCE SLICE_6)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_7")
+    (INSTANCE SLICE_7)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_8")
+    (INSTANCE SLICE_8)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH A1 FCO (619:692:766)(619:692:766))
+        (IOPATH A0 FCO (713:797:882)(713:797:882))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+        (IOPATH FCI FCO (115:128:141)(115:128:141))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179))
+      (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185))
+      (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_9")
+    (INSTANCE SLICE_9)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_14")
+    (INSTANCE SLICE_14)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_20")
+    (INSTANCE SLICE_20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_21")
+    (INSTANCE SLICE_21)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_22")
+    (INSTANCE SLICE_22)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_26")
+    (INSTANCE SLICE_26)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_29")
+    (INSTANCE SLICE_29)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_30")
+    (INSTANCE SLICE_30)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_31")
+    (INSTANCE SLICE_31)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_32")
+    (INSTANCE SLICE_32)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_33")
+    (INSTANCE SLICE_33)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_39")
+    (INSTANCE SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_41")
+    (INSTANCE SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_42")
+    (INSTANCE SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_43")
+    (INSTANCE SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_44")
+    (INSTANCE SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_50")
+    (INSTANCE SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_51")
+    (INSTANCE SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_52")
+    (INSTANCE SLICE_52)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_55")
+    (INSTANCE SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_56")
+    (INSTANCE SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_57")
+    (INSTANCE SLICE_57)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_58")
+    (INSTANCE SLICE_58)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_59")
+    (INSTANCE SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_60")
+    (INSTANCE SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_61")
+    (INSTANCE SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_62")
+    (INSTANCE SLICE_62)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_63")
+    (INSTANCE SLICE_63)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_64")
+    (INSTANCE SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE_RNO_1_SLICE_65")
+    (INSTANCE nRWE_RNO_1\/SLICE_65)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH C1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH B1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH A1 OFX0 (496:555:615)(496:555:615))
+        (IOPATH D0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH C0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH B0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH A0 OFX0 (508:569:631)(508:569:631))
+        (IOPATH M0 OFX0 (405:453:501)(405:453:501))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_66")
+    (INSTANCE SLICE_66)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_67")
+    (INSTANCE SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_68")
+    (INSTANCE SLICE_68)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_69")
+    (INSTANCE SLICE_69)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_70")
+    (INSTANCE SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_71")
+    (INSTANCE SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_72")
+    (INSTANCE SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_73")
+    (INSTANCE SLICE_73)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_74")
+    (INSTANCE SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_75")
+    (INSTANCE SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_76")
+    (INSTANCE SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_77")
+    (INSTANCE SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+        (IOPATH CLK Q1 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_78")
+    (INSTANCE SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_79")
+    (INSTANCE SLICE_79)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_80")
+    (INSTANCE SLICE_80)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_81")
+    (INSTANCE SLICE_81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_82")
+    (INSTANCE SLICE_82)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_83")
+    (INSTANCE SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_84")
+    (INSTANCE SLICE_84)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_85")
+    (INSTANCE SLICE_85)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_86")
+    (INSTANCE SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_87")
+    (INSTANCE SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_88")
+    (INSTANCE SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (560:586:613)(560:586:613))
+        (IOPATH CLK Q1 (560:586:613)(560:586:613))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25))
+      (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_89")
+    (INSTANCE SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_90")
+    (INSTANCE SLICE_90)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_91")
+    (INSTANCE SLICE_91)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_92")
+    (INSTANCE SLICE_92)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_93")
+    (INSTANCE SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH B1 F1 (301:336:371)(301:336:371))
+        (IOPATH A1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH B0 F0 (301:336:371)(301:336:371))
+        (IOPATH A0 F0 (301:336:371)(301:336:371))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_94")
+    (INSTANCE SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (301:336:371)(301:336:371))
+        (IOPATH C1 F1 (301:336:371)(301:336:371))
+        (IOPATH D0 F0 (301:336:371)(301:336:371))
+        (IOPATH C0 F0 (301:336:371)(301:336:371))
+        (IOPATH CLK Q0 (515:537:560)(515:537:560))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69))
+      (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1000:1000:1000))
+      (WIDTH (negedge CLK) (1000:1000:1000))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_0_")
+    (INSTANCE RD\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD0 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD0 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD0) (1250:1250:1250))
+      (WIDTH (negedge RD0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_0_")
+    (INSTANCE Dout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout0 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "PHI2")
+    (INSTANCE PHI2_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge PHI2) (1250:1250:1250))
+      (WIDTH (negedge PHI2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDO")
+    (INSTANCE UFMSDO_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge UFMSDO) (1250:1250:1250))
+      (WIDTH (negedge UFMSDO) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMSDI")
+    (INSTANCE UFMSDI_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMSDI (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "UFMCLK")
+    (INSTANCE UFMCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO UFMCLK (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nUFMCS")
+    (INSTANCE nUFMCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nUFMCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQML")
+    (INSTANCE RDQML_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQML (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RDQMH")
+    (INSTANCE RDQMH_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RDQMH (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCAS")
+    (INSTANCE nRCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRRAS")
+    (INSTANCE nRRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRRAS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nRWE")
+    (INSTANCE nRWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRWE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCKE")
+    (INSTANCE RCKE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RCKE (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RCLK")
+    (INSTANCE RCLK_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH RCLK PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RCLK) (1250:1250:1250))
+      (WIDTH (negedge RCLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nRCS")
+    (INSTANCE nRCS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO nRCS (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_7_")
+    (INSTANCE RD\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD7 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD7 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD7) (1250:1250:1250))
+      (WIDTH (negedge RD7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_6_")
+    (INSTANCE RD\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD6 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD6 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD6) (1250:1250:1250))
+      (WIDTH (negedge RD6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_5_")
+    (INSTANCE RD\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD5 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD5 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD5) (1250:1250:1250))
+      (WIDTH (negedge RD5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_4_")
+    (INSTANCE RD\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD4 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD4 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD4) (1250:1250:1250))
+      (WIDTH (negedge RD4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_3_")
+    (INSTANCE RD\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD3 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD3 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD3) (1250:1250:1250))
+      (WIDTH (negedge RD3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_2_")
+    (INSTANCE RD\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD2 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD2 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD2) (1250:1250:1250))
+      (WIDTH (negedge RD2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RD_1_")
+    (INSTANCE RD\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDT RD1 (3001:3001:3001)(3001:3001:3001)(3001:3001:3001)(3001:3001:3001)
+          (3001:3001:3001)(3001:3001:3001))
+        (IOPATH PADDO RD1 (2471:2471:2471)(2471:2471:2471))
+        (IOPATH RD1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge RD1) (1250:1250:1250))
+      (WIDTH (negedge RD1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_11_")
+    (INSTANCE RA\[11\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA11 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_10_")
+    (INSTANCE RA\[10\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA10 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_9_")
+    (INSTANCE RA\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA9 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_8_")
+    (INSTANCE RA\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA8 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_7_")
+    (INSTANCE RA\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA7 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_6_")
+    (INSTANCE RA\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA6 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_5_")
+    (INSTANCE RA\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA5 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_4_")
+    (INSTANCE RA\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA4 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_3_")
+    (INSTANCE RA\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA3 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_2_")
+    (INSTANCE RA\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA2 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_1_")
+    (INSTANCE RA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RA_0_")
+    (INSTANCE RA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_1_")
+    (INSTANCE RBA\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA1 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RBA_0_")
+    (INSTANCE RBA\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO RBA0 (2478:2478:2478)(2478:2478:2478))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "LED")
+    (INSTANCE LED_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO LED (2843:2843:2843)(2843:2843:2843))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "nFWE")
+    (INSTANCE nFWE_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nFWE PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nFWE) (1250:1250:1250))
+      (WIDTH (negedge nFWE) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCRAS")
+    (INSTANCE nCRAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCRAS) (1250:1250:1250))
+      (WIDTH (negedge nCRAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "nCCAS")
+    (INSTANCE nCCAS_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge nCCAS) (1250:1250:1250))
+      (WIDTH (negedge nCCAS) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_7_")
+    (INSTANCE Dout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout7 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_6_")
+    (INSTANCE Dout\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout6 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_5_")
+    (INSTANCE Dout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout5 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_4_")
+    (INSTANCE Dout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout4 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_3_")
+    (INSTANCE Dout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout3 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_2_")
+    (INSTANCE Dout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout2 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Dout_1_")
+    (INSTANCE Dout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH PADDO Dout1 (1858:1858:1858)(1858:1858:1858))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_7_")
+    (INSTANCE Din\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din7) (1250:1250:1250))
+      (WIDTH (negedge Din7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_6_")
+    (INSTANCE Din\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din6) (1250:1250:1250))
+      (WIDTH (negedge Din6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_5_")
+    (INSTANCE Din\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din5) (1250:1250:1250))
+      (WIDTH (negedge Din5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_4_")
+    (INSTANCE Din\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din4) (1250:1250:1250))
+      (WIDTH (negedge Din4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_3_")
+    (INSTANCE Din\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din3) (1250:1250:1250))
+      (WIDTH (negedge Din3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_2_")
+    (INSTANCE Din\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din2) (1250:1250:1250))
+      (WIDTH (negedge Din2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_1_")
+    (INSTANCE Din\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din1) (1250:1250:1250))
+      (WIDTH (negedge Din1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "Din_0_")
+    (INSTANCE Din\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH Din0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge Din0) (1250:1250:1250))
+      (WIDTH (negedge Din0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_1_")
+    (INSTANCE CROW\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW1) (1250:1250:1250))
+      (WIDTH (negedge CROW1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "CROW_0_")
+    (INSTANCE CROW\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CROW0) (1250:1250:1250))
+      (WIDTH (negedge CROW0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_9_")
+    (INSTANCE MAin\[9\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin9) (1250:1250:1250))
+      (WIDTH (negedge MAin9) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_8_")
+    (INSTANCE MAin\[8\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin8) (1250:1250:1250))
+      (WIDTH (negedge MAin8) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_7_")
+    (INSTANCE MAin\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin7) (1250:1250:1250))
+      (WIDTH (negedge MAin7) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_6_")
+    (INSTANCE MAin\[6\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin6) (1250:1250:1250))
+      (WIDTH (negedge MAin6) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_5_")
+    (INSTANCE MAin\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin5) (1250:1250:1250))
+      (WIDTH (negedge MAin5) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_4_")
+    (INSTANCE MAin\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin4) (1250:1250:1250))
+      (WIDTH (negedge MAin4) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_3_")
+    (INSTANCE MAin\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin3) (1250:1250:1250))
+      (WIDTH (negedge MAin3) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_2_")
+    (INSTANCE MAin\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin2) (1250:1250:1250))
+      (WIDTH (negedge MAin2) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_1_")
+    (INSTANCE MAin\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin1) (1250:1250:1250))
+      (WIDTH (negedge MAin1) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "MAin_0_")
+    (INSTANCE MAin\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge MAin0) (1250:1250:1250))
+      (WIDTH (negedge MAin0) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAM2GS")
+    (INSTANCE )
+    (DELAY
+      (ABSOLUTE
+        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_0/Q1 SLICE_72/D0 (1405:1526:1647)(1405:1526:1647))
+        (INTERCONNECT SLICE_0/Q1 SLICE_84/C0 (754:836:918)(754:836:918))
+        (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_0/Q0 SLICE_68/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_0/Q0 SLICE_69/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (732:1078:1425)(732:1078:1425))
+        (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/C1 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_1/Q0 SLICE_66/B0 (917:1024:1131)(917:1024:1131))
+        (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_1/Q0 SLICE_74/D0 (602:670:739)(602:670:739))
+        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_2/Q0 SLICE_74/D1 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_2/Q0 SLICE_81/D1 (1002:1094:1186)(1002:1094:1186))
+        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_3/Q1 SLICE_81/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_3/Q0 SLICE_81/D0 (963:1075:1187)(963:1075:1187))
+        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (1823:1986:2149)(1823:1986:2149))
+        (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1823:1986:2149)(1823:1986:2149))
+        (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (923:1026:1129)(923:1026:1129))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_4/Q0 SLICE_64/D1 (1404:1527:1650)(1404:1527:1650))
+        (INTERCONNECT SLICE_4/Q0 SLICE_74/B0 (913:1016:1120)(913:1016:1120))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1560:1708:1856)(1560:1708:1856))
+        (INTERCONNECT SLICE_4/Q0 SLICE_84/B0 (913:1016:1120)(913:1016:1120))
+        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (2087:2267:2448)(2087:2267:2448))
+        (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (754:836:918)(754:836:918))
+        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_5/Q0 SLICE_58/C1 (1149:1260:1372)(1149:1260:1372))
+        (INTERCONNECT SLICE_5/Q0 SLICE_84/D1 (1397:1518:1640)(1397:1518:1640))
+        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_6/Q1 SLICE_56/A0 (2201:2394:2587)(2201:2394:2587))
+        (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (1225:1371:1517)(1225:1371:1517))
+        (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (1225:1371:1517)(1225:1371:1517))
+        (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1803:1960:2118)(1803:1960:2118))
+        (INTERCONNECT SLICE_7/Q1 SLICE_68/A1 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_7/Q1 SLICE_69/A1 (862:958:1054)(862:958:1054))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_7/Q0 SLICE_72/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1271:1394:1518)(1271:1394:1518))
+        (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8/Q1 SLICE_68/D1 (876:974:1072)(876:974:1072))
+        (INTERCONNECT SLICE_8/Q1 SLICE_69/D1 (876:974:1072)(876:974:1072))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (903:1005:1108)(903:1005:1108))
+        (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_70/F1 SLICE_9/C1 (769:851:933)(769:851:933))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (778:861:945)(778:861:945))
+        (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (1295:1420:1545)(1295:1420:1545))
+        (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (606:674:742)(606:674:742))
+        (INTERCONNECT SLICE_70/F1 SLICE_90/C1 (769:851:933)(769:851:933))
+        (INTERCONNECT SLICE_85/F1 SLICE_9/B1 (2100:2300:2500)(2100:2300:2500))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (1802:1995:2189)(1802:1995:2189))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1606:1757:1909)(1606:1757:1909))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (2131:2353:2575)(2131:2353:2575))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (2379:2611:2843)(2379:2611:2843))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (1395:1576:1757)(1395:1576:1757))
+        (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B0 (1395:1576:1757)(1395:1576:1757))
+        (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634))
+        (INTERCONNECT SLICE_9/Q0 SLICE_20/A1 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_70/F0 SLICE_9/C0 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_9/F1 SLICE_9/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_14/F1 SLICE_9/A0 (1263:1387:1511)(1263:1387:1511))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (1301:1429:1558)(1301:1429:1558))
+        (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2017:2199:2381)(2017:2199:2381))
+        (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2497:3089:3682)(2497:3089:3682))
+        (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (837:931:1026)(837:931:1026))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/B0 (1984:2189:2395)(1984:2189:2395))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1925:2114:2304)(1925:2114:2304))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/D0 (1636:1793:1950)(1636:1793:1950))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/C0 (2423:2682:2941)(2423:2682:2941))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (2046:2232:2419)(2046:2232:2419))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1522:1684:1847)(1522:1684:1847))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/A1 (2718:2965:3212)(2718:2965:3212))
+        (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (2379:2611:2843)(2379:2611:2843))
+        (INTERCONNECT SLICE_14/Q0 SLICE_14/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_14/Q0 SLICE_20/C0 (1431:1576:1722)(1431:1576:1722))
+        (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/D1 (571:629:687)(571:629:687))
+        (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (575:636:697)(575:636:697))
+        (INTERCONNECT SLICE_19/Q0 SLICE_41/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (808:893:978)(808:893:978))
+        (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (808:893:978)(808:893:978))
+        (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1211:1325:1439)(1211:1325:1439))
+        (INTERCONNECT SLICE_19/Q0 SLICE_63/B0 (968:1072:1177)(968:1072:1177))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1236:1372:1509)(1236:1372:1509))
+        (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1236:1372:1509)(1236:1372:1509))
+        (INTERCONNECT SLICE_19/Q0 SLICE_73/B1 (947:1054:1161)(947:1054:1161))
+        (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (653:719:785)(653:719:785))
+        (INTERCONNECT SLICE_19/Q0 SLICE_80/A0 (922:1019:1117)(922:1019:1117))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (788:872:957)(788:872:957))
+        (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (788:872:957)(788:872:957))
+        (INTERCONNECT SLICE_50/Q0 SLICE_41/A1 (1312:1438:1565)(1312:1438:1565))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (1839:2035:2231)(1839:2035:2231))
+        (INTERCONNECT SLICE_50/Q0 SLICE_59/B0 (1710:1891:2072)(1710:1891:2072))
+        (INTERCONNECT SLICE_50/Q0 SLICE_63/A0 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (1191:1322:1454)(1191:1322:1454))
+        (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/D0 (633:698:764)(633:698:764))
+        (INTERCONNECT SLICE_50/Q0 SLICE_73/D1 (1332:1461:1591)(1332:1461:1591))
+        (INTERCONNECT SLICE_50/Q0 SLICE_79/A0 (839:930:1021)(839:930:1021))
+        (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2356:2575:2795)(2356:2575:2795))
+        (INTERCONNECT SLICE_31/Q0 SLICE_19/B1 (863:960:1057)(863:960:1057))
+        (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (810:899:989)(810:899:989))
+        (INTERCONNECT SLICE_31/Q0 SLICE_31/C0 (696:773:850)(696:773:850))
+        (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (863:960:1057)(863:960:1057))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/A1 (1282:1411:1540)(1282:1411:1540))
+        (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (1320:1453:1587)(1320:1453:1587))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/A1 (1688:1854:2020)(1688:1854:2020))
+        (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (1688:1854:2020)(1688:1854:2020))
+        (INTERCONNECT SLICE_51/Q1 SLICE_43/B1 (1328:1464:1600)(1328:1464:1600))
+        (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (1320:1453:1587)(1320:1453:1587))
+        (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (889:990:1091)(889:990:1091))
+        (INTERCONNECT SLICE_51/Q1 SLICE_61/B1 (1726:1896:2067)(1726:1896:2067))
+        (INTERCONNECT SLICE_51/Q1 SLICE_62/A1 (2115:2317:2519)(2115:2317:2519))
+        (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (582:647:712)(582:647:712))
+        (INTERCONNECT SLICE_51/Q1 SLICE_73/C1 (1571:1716:1862)(1571:1716:1862))
+        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_19/F1 SLICE_43/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (1394:1526:1659)(1394:1526:1659))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_20/Q0 SLICE_67/B0 (1409:1541:1674)(1409:1541:1674))
+        (INTERCONNECT SLICE_90/F1 SLICE_20/B0 (1286:1416:1547)(1286:1416:1547))
+        (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2758:3009:3261)(2758:3009:3261))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A0 (1511:1671:1831)(1511:1671:1831))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/D1 (1242:1370:1499)(1242:1370:1499))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1549:1713:1878)(1549:1713:1878))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2391:2619:2848)(2391:2619:2848))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D1 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D0 (1673:1834:1995)(1673:1834:1995))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/A0 (1876:2059:2243)(1876:2059:2243))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/C1 (1790:1964:2139)(1790:1964:2139))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/C1 (2200:2404:2608)(2200:2404:2608))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/B1 (1930:2123:2316)(1930:2123:2316))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (2355:2576:2798)(2355:2576:2798))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (2606:2857:3109)(2606:2857:3109))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/C1 (1790:1964:2139)(1790:1964:2139))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A1 (1904:2091:2278)(1904:2091:2278))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A0 (1904:2091:2278)(1904:2091:2278))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (1922:2112:2303)(1922:2112:2303))
+        (INTERCONNECT SLICE_75/F1 SLICE_21/B1 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (616:686:757)(616:686:757))
+        (INTERCONNECT SLICE_75/F1 SLICE_67/A1 (864:963:1063)(864:963:1063))
+        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/B1 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (931:1040:1149)(931:1040:1149))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_33/Q0 SLICE_21/C0 (1644:1786:1929)(1644:1786:1929))
+        (INTERCONNECT SLICE_33/Q0 SLICE_33/D1 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (2611:2837:3063)(2611:2837:3063))
+        (INTERCONNECT SLICE_75/F0 SLICE_21/B0 (883:984:1086)(883:984:1086))
+        (INTERCONNECT SLICE_82/F1 SLICE_21/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/F0 SLICE_21/CE (573:634:695)(573:634:695))
+        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (573:634:695)(573:634:695))
+        (INTERCONNECT SLICE_67/F0 SLICE_57/CE (906:1005:1104)(906:1005:1104))
+        (INTERCONNECT SLICE_67/F0 SLICE_67/C1 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_67/F0 SLICE_82/C0 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_21/Q0 SLICE_33/B0 (1797:1958:2120)(1797:1958:2120))
+        (INTERCONNECT SLICE_21/Q0 SLICE_82/C1 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1157:1286:1415)(1157:1286:1415))
+        (INTERCONNECT SLICE_43/Q1 SLICE_22/C1 (1016:1133:1251)(1016:1133:1251))
+        (INTERCONNECT SLICE_43/Q1 SLICE_52/D1 (861:959:1058)(861:959:1058))
+        (INTERCONNECT SLICE_41/Q1 SLICE_22/B1 (1300:1432:1564)(1300:1432:1564))
+        (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (1695:1853:2012)(1695:1853:2012))
+        (INTERCONNECT SLICE_41/Q1 SLICE_52/B1 (1703:1864:2025)(1703:1864:2025))
+        (INTERCONNECT SLICE_32/Q0 SLICE_22/A1 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/C1 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_32/Q0 SLICE_33/D0 (1042:1139:1236)(1042:1139:1236))
+        (INTERCONNECT SLICE_32/Q0 SLICE_43/A1 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32/Q0 SLICE_43/A0 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32/Q0 SLICE_44/A1 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32/Q0 SLICE_51/C1 (1197:1313:1429)(1197:1313:1429))
+        (INTERCONNECT SLICE_32/Q0 SLICE_52/C1 (1197:1313:1429)(1197:1313:1429))
+        (INTERCONNECT SLICE_32/Q0 SLICE_58/A1 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32/Q0 SLICE_58/A0 (1714:1871:2028)(1714:1871:2028))
+        (INTERCONNECT SLICE_32/Q0 SLICE_64/A1 (1311:1439:1568)(1311:1439:1568))
+        (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (887:984:1081)(887:984:1081))
+        (INTERCONNECT SLICE_32/Q0 SLICE_66/C1 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32/Q0 SLICE_66/C0 (710:788:867)(710:788:867))
+        (INTERCONNECT SLICE_32/Q0 SLICE_73/A1 (1304:1431:1559)(1304:1431:1559))
+        (INTERCONNECT SLICE_82/F0 SLICE_22/D0 (1778:1934:2090)(1778:1934:2090))
+        (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22/F1 SLICE_68/D0 (975:1068:1161)(975:1068:1161))
+        (INTERCONNECT SLICE_22/F1 SLICE_69/B0 (1290:1421:1553)(1290:1421:1553))
+        (INTERCONNECT SLICE_78/F1 SLICE_26/C1 (735:822:909)(735:822:909))
+        (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_26/Q0 SLICE_58/B0 (899:1000:1102)(899:1000:1102))
+        (INTERCONNECT SLICE_76/F1 SLICE_26/A1 (1348:1473:1599)(1348:1473:1599))
+        (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (580:648:716)(580:648:716))
+        (INTERCONNECT SLICE_58/Q0 SLICE_39/A0 (2063:2250:2438)(2063:2250:2438))
+        (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_83/F1 SLICE_29/D1 (1406:1541:1676)(1406:1541:1676))
+        (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (2154:2337:2521)(2154:2337:2521))
+        (INTERCONNECT SLICE_83/F1 SLICE_61/D0 (1695:1864:2034)(1695:1864:2034))
+        (INTERCONNECT SLICE_73/F1 SLICE_29/C1 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73/F1 SLICE_29/C0 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73/F1 SLICE_59/B1 (1836:2003:2171)(1836:2003:2171))
+        (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1273:1392:1511)(1273:1392:1511))
+        (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_73/F1 SLICE_94/C1 (1680:1833:1986)(1680:1833:1986))
+        (INTERCONNECT SLICE_61/F1 SLICE_29/B1 (841:937:1034)(841:937:1034))
+        (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_29/Q0 SLICE_29/A1 (832:922:1012)(832:922:1012))
+        (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (623:687:752)(623:687:752))
+        (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (623:687:752)(623:687:752))
+        (INTERCONNECT SLICE_29/Q0 SLICE_31/A0 (1302:1427:1553)(1302:1427:1553))
+        (INTERCONNECT SLICE_29/Q0 SLICE_42/B1 (1703:1883:2063)(1703:1883:2063))
+        (INTERCONNECT SLICE_29/Q0 SLICE_61/A0 (832:922:1012)(832:922:1012))
+        (INTERCONNECT SLICE_29/Q0 SLICE_83/D0 (1033:1127:1221)(1033:1127:1221))
+        (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (2098:2304:2511)(2098:2304:2511))
+        (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (1347:1503:1660)(1347:1503:1660))
+        (INTERCONNECT SLICE_43/Q0 SLICE_41/B0 (948:1050:1153)(948:1050:1153))
+        (INTERCONNECT SLICE_43/Q0 SLICE_43/D1 (578:636:695)(578:636:695))
+        (INTERCONNECT SLICE_43/Q0 SLICE_43/D0 (578:636:695)(578:636:695))
+        (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (633:697:761)(633:697:761))
+        (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (632:700:769)(632:700:769))
+        (INTERCONNECT SLICE_43/Q0 SLICE_59/D1 (1435:1582:1729)(1435:1582:1729))
+        (INTERCONNECT SLICE_43/Q0 SLICE_61/C1 (1476:1647:1819)(1476:1647:1819))
+        (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2176:2379:2582)(2176:2379:2582))
+        (INTERCONNECT SLICE_43/Q0 SLICE_63/C1 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43/Q0 SLICE_63/C0 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (640:705:770)(640:705:770))
+        (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1191:1321:1451)(1191:1321:1451))
+        (INTERCONNECT SLICE_43/Q0 SLICE_79/C1 (801:890:980)(801:890:980))
+        (INTERCONNECT SLICE_43/Q0 SLICE_94/D1 (2271:2465:2659)(2271:2465:2659))
+        (INTERCONNECT SLICE_43/Q0 SLICE_94/D0 (2271:2465:2659)(2271:2465:2659))
+        (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_30/Q1 SLICE_30/C1 (696:773:850)(696:773:850))
+        (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (991:1107:1224)(991:1107:1224))
+        (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (991:1107:1224)(991:1107:1224))
+        (INTERCONNECT SLICE_30/Q1 SLICE_42/C1 (1560:1700:1840)(1560:1700:1840))
+        (INTERCONNECT SLICE_30/Q1 SLICE_83/C1 (1146:1281:1417)(1146:1281:1417))
+        (INTERCONNECT SLICE_30/Q1 SLICE_83/C0 (1146:1281:1417)(1146:1281:1417))
+        (INTERCONNECT SLICE_30/Q0 SLICE_30/A1 (825:914:1004)(825:914:1004))
+        (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682))
+        (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (943:1046:1150)(943:1046:1150))
+        (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (943:1046:1150)(943:1046:1150))
+        (INTERCONNECT SLICE_30/Q0 SLICE_42/D1 (1109:1203:1297)(1109:1203:1297))
+        (INTERCONNECT SLICE_30/Q0 SLICE_83/A1 (897:993:1090)(897:993:1090))
+        (INTERCONNECT SLICE_30/Q0 SLICE_83/A0 (897:993:1090)(897:993:1090))
+        (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_94/F1 SLICE_30/CE (1885:2046:2208)(1885:2046:2208))
+        (INTERCONNECT SLICE_94/F1 SLICE_31/CE (2184:2374:2565)(2184:2374:2565))
+        (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (1908:2070:2233)(1908:2070:2233))
+        (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1374:1495:1616)(1374:1495:1616))
+        (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (1172:1308:1444)(1172:1308:1444))
+        (INTERCONNECT SLICE_72/F1 SLICE_32/A1 (1239:1383:1527)(1239:1383:1527))
+        (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (541:599:657)(541:599:657))
+        (INTERCONNECT SLICE_72/F1 SLICE_64/C1 (1575:1727:1879)(1575:1727:1879))
+        (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (431:479:528)(431:479:528))
+        (INTERCONNECT SLICE_74/F0 SLICE_32/D0 (245:274:304)(245:274:304))
+        (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (245:274:304)(245:274:304))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_33/C1 (1635:1825:2016)(1635:1825:2016))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (1526:1687:1849)(1526:1687:1849))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (3109:3772:4435)(3109:3772:4435))
+        (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1758:1913:2068)(1758:1913:2068))
+        (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1892:2044:2197)(1892:2044:2197))
+        (INTERCONNECT SLICE_78/Q0 SLICE_60/D0 (1405:1538:1671)(1405:1538:1671))
+        (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1634:1807:1981)(1634:1807:1981))
+        (INTERCONNECT SLICE_78/Q0 SLICE_79/B0 (1969:2184:2399)(1969:2184:2399))
+        (INTERCONNECT UFMSDO_I/PADDI SLICE_33/A0 (1377:1528:1680)(1377:1528:1680))
+        (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (2317:2524:2731)(2317:2524:2731))
+        (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_69/F0 SLICE_33/CE (1070:1165:1260)(1070:1165:1260))
+        (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_57/Q0 SLICE_39/D1 (1908:2070:2232)(1908:2070:2232))
+        (INTERCONNECT SLICE_57/Q0 SLICE_39/D0 (1908:2070:2232)(1908:2070:2232))
+        (INTERCONNECT SLICE_85/F0 SLICE_39/B1 (1792:1955:2118)(1792:1955:2118))
+        (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (1477:1601:1726)(1477:1601:1726))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/B0 (2577:2847:3118)(2577:2847:3118))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (2415:2652:2889)(2415:2652:2889))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A1 (2528:2792:3057)(2528:2792:3057))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/B0 (2695:2961:3228)(2695:2961:3228))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2387:2616:2845)(2387:2616:2845))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/C0 (2520:2764:3008)(2520:2764:3008))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/D0 (1973:2170:2368)(1973:2170:2368))
+        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1723:1881:2040)(1723:1881:2040))
+        (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667))
+        (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (910:1010:1110)(910:1010:1110))
+        (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1730:1889:2048)(1730:1889:2048))
+        (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1730:1889:2048)(1730:1889:2048))
+        (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (1320:1449:1579)(1320:1449:1579))
+        (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (910:1010:1110)(910:1010:1110))
+        (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1723:1881:2040)(1723:1881:2040))
+        (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (2170:2363:2556)(2170:2363:2556))
+        (INTERCONNECT SLICE_81/Q1 SLICE_41/C1 (2032:2205:2379)(2032:2205:2379))
+        (INTERCONNECT SLICE_81/Q1 SLICE_60/B1 (1789:1953:2117)(1789:1953:2117))
+        (INTERCONNECT SLICE_75/Q1 SLICE_41/B1 (1295:1427:1559)(1295:1427:1559))
+        (INTERCONNECT SLICE_75/Q1 SLICE_60/A1 (2074:2266:2459)(2074:2266:2459))
+        (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1717:1887:2058)(1717:1887:2058))
+        (INTERCONNECT SLICE_75/Q1 SLICE_80/C1 (1557:1708:1859)(1557:1708:1859))
+        (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (884:984:1085)(884:984:1085))
+        (INTERCONNECT SLICE_41/F1 SLICE_41/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_43/F1 SLICE_41/A0 (833:932:1032)(833:932:1032))
+        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1773:1932:2091)(1773:1932:2091))
+        (INTERCONNECT SLICE_41/Q0 SLICE_42/B0 (1781:1942:2104)(1781:1942:2104))
+        (INTERCONNECT SLICE_44/Q1 SLICE_42/D0 (1398:1530:1663)(1398:1530:1663))
+        (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (1386:1516:1646)(1386:1516:1646))
+        (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1621:1763:1905)(1621:1763:1905))
+        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_42/Q0 SLICE_61/A1 (1247:1371:1495)(1247:1371:1495))
+        (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/C1 (2228:2432:2636)(2228:2432:2636))
+        (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/C0 (1537:1688:1840)(1537:1688:1840))
+        (INTERCONNECT SLICE_50/F0 SLICE_43/C1 (750:837:924)(750:837:924))
+        (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (31:31:31)(31:31:31))
+        (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (970:1082:1195)(970:1082:1195))
+        (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1575:1727:1879)(1575:1727:1879))
+        (INTERCONNECT SLICE_83/F0 SLICE_43/C0 (681:758:835)(681:758:835))
+        (INTERCONNECT SLICE_83/F0 SLICE_44/C1 (739:821:903)(739:821:903))
+        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1335:1476:1617)(1335:1476:1617))
+        (INTERCONNECT SLICE_72/F0 SLICE_51/B1 (1781:1942:2104)(1781:1942:2104))
+        (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503))
+        (INTERCONNECT SLICE_66/F0 SLICE_66/A1 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_52/F1 SLICE_51/D0 (877:975:1074)(877:975:1074))
+        (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_52/F1 SLICE_64/A0 (857:952:1048)(857:952:1048))
+        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (868:962:1057)(868:962:1057))
+        (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727))
+        (INTERCONNECT SLICE_51/Q0 SLICE_51/A0 (530:591:652)(530:591:652))
+        (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1184:1361:1538)(1184:1361:1538))
+        (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (932:1044:1156)(932:1044:1156))
+        (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_67/Q0 SLICE_55/D0 (1466:1589:1712)(1466:1589:1712))
+        (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (2114:2313:2513)(2114:2313:2513))
+        (INTERCONNECT SLICE_63/Q0 SLICE_86/A1 (1678:1840:2002)(1678:1840:2002))
+        (INTERCONNECT SLICE_63/Q0 SLICE_86/A0 (1678:1840:2002)(1678:1840:2002))
+        (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (2224:2421:2618)(2224:2421:2618))
+        (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (2224:2421:2618)(2224:2421:2618))
+        (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (1802:1970:2138)(1802:1970:2138))
+        (INTERCONNECT SLICE_63/Q0 SLICE_91/D1 (1796:1956:2117)(1796:1956:2117))
+        (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (1954:2134:2314)(1954:2134:2314))
+        (INTERCONNECT SLICE_63/Q0 SLICE_92/D1 (2320:2504:2689)(2320:2504:2689))
+        (INTERCONNECT SLICE_63/Q0 SLICE_92/D0 (2320:2504:2689)(2320:2504:2689))
+        (INTERCONNECT SLICE_63/Q0 SLICE_93/B1 (2543:2782:3021)(2543:2782:3021))
+        (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2543:2782:3021)(2543:2782:3021))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/A0 (2220:2446:2672)(2220:2446:2672))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (2701:2972:3244)(2701:2972:3244))
+        (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/A1 (2663:2930:3197)(2663:2930:3197))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2067:2260:2454)(2067:2260:2454))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/C1 (1378:1524:1670)(1378:1524:1670))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1530:1693:1856)(1530:1693:1856))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/A1 (2732:2985:3238)(2732:2985:3238))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B1 (1973:2177:2381)(1973:2177:2381))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B0 (1973:2177:2381)(1973:2177:2381))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (1242:1370:1498)(1242:1370:1498))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2109:2309:2510)(2109:2309:2510))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (1503:1660:1818)(1503:1660:1818))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (2373:2602:2831)(2373:2602:2831))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (2373:2602:2831)(2373:2602:2831))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (1706:1877:2049)(1706:1877:2049))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1706:1877:2049)(1706:1877:2049))
+        (INTERCONNECT nCCAS_I/PADDI SLICE_88/D0 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (2378:2648:2918)(2378:2648:2918))
+        (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475))
+        (INTERCONNECT SLICE_76/Q1 SLICE_56/D1 (1498:1630:1763)(1498:1630:1763))
+        (INTERCONNECT SLICE_71/Q0 SLICE_56/C1 (1653:1804:1956)(1653:1804:1956))
+        (INTERCONNECT SLICE_77/Q0 SLICE_56/B1 (1813:1984:2155)(1813:1984:2155))
+        (INTERCONNECT SLICE_77/Q1 SLICE_56/A1 (2138:2321:2505)(2138:2321:2505))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2264:2497:2730)(2264:2497:2730))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/B1 (1828:2016:2205)(1828:2016:2205))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/C1 (1272:1412:1553)(1272:1412:1553))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (1424:1581:1739)(1424:1581:1739))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C1 (2522:2767:3013)(2522:2767:3013))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C0 (2522:2767:3013)(2522:2767:3013))
+        (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1813:1984:2155)(1813:1984:2155))
+        (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1547:1713:1879)(1547:1713:1879))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1539:1702:1866)(1539:1702:1866))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1921:2109:2298)(1921:2109:2298))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1904:2092:2280)(1904:2092:2280))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1904:2092:2280)(1904:2092:2280))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (2324:2541:2759)(2324:2541:2759))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/A1 (1891:2077:2264)(1891:2077:2264))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (2325:2544:2764)(2325:2544:2764))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (1529:1691:1854)(1529:1691:1854))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/B1 (1937:2130:2324)(1937:2130:2324))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (2739:2994:3250)(2739:2994:3250))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/A1 (2297:2513:2729)(2297:2513:2729))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (1217:1343:1469)(1217:1343:1469))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (714:807:900)(714:807:900))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1521:1678:1835)(1521:1678:1835))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1217:1343:1469)(1217:1343:1469))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1421:1579:1738)(1421:1579:1738))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (1959:2159:2360)(1959:2159:2360))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/D1 (1941:2140:2339)(1941:2140:2339))
+        (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (1544:1731:1919)(1544:1731:1919))
+        (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (940:1054:1169)(940:1054:1169))
+        (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_62/F1 SLICE_59/C0 (1669:1820:1972)(1669:1820:1972))
+        (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (576:644:712)(576:644:712))
+        (INTERCONNECT SLICE_80/F0 SLICE_59/A0 (1201:1344:1488)(1201:1344:1488))
+        (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_82/Q0 SLICE_60/D1 (1509:1643:1777)(1509:1643:1777))
+        (INTERCONNECT SLICE_82/Q0 SLICE_63/D1 (1491:1617:1743)(1491:1617:1743))
+        (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (1491:1617:1743)(1491:1617:1743))
+        (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (2209:2402:2596)(2209:2402:2596))
+        (INTERCONNECT SLICE_94/F0 SLICE_60/C0 (1529:1669:1809)(1529:1669:1809))
+        (INTERCONNECT SLICE_60/F1 SLICE_60/A0 (779:868:958)(779:868:958))
+        (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (1291:1473:1656)(1291:1473:1656))
+        (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1935:2190:2445)(1935:2190:2445))
+        (INTERCONNECT SLICE_78/Q1 SLICE_62/D1 (1079:1173:1267)(1079:1173:1267))
+        (INTERCONNECT SLICE_78/Q1 SLICE_80/C0 (1637:1779:1921)(1637:1779:1921))
+        (INTERCONNECT SLICE_81/Q0 SLICE_62/D0 (1679:1834:1990)(1679:1834:1990))
+        (INTERCONNECT SLICE_81/Q0 SLICE_63/B1 (1691:1860:2030)(1691:1860:2030))
+        (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1376:1507:1638)(1376:1507:1638))
+        (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/C0 (1653:1804:1956)
+          (1653:1804:1956))
+        (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1651:1815:1979)(1651:1815:1979))
+        (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (2095:2345:2595)(2095:2345:2595))
+        (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_64/Q0 SLICE_64/D0 (526:584:642)(526:584:642))
+        (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1548:1774:2000)(1548:1774:2000))
+        (INTERCONNECT SLICE_66/F1 SLICE_64/C0 (1529:1669:1809)(1529:1669:1809))
+        (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_73/Q1 SLICE_66/B1 (1247:1397:1548)(1247:1397:1548))
+        (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (1383:1512:1642)(1383:1512:1642))
+        (INTERCONNECT SLICE_81/F0 SLICE_74/A0 (1652:1813:1974)(1652:1813:1974))
+        (INTERCONNECT SLICE_74/F1 SLICE_66/A0 (795:884:974)(795:884:974))
+        (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (416:464:513)(416:464:513))
+        (INTERCONNECT SLICE_66/Q0 SLICE_90/D0 (1375:1502:1629)(1375:1502:1629))
+        (INTERCONNECT SLICE_66/Q1 SLICE_91/D0 (1901:2062:2224)(1901:2062:2224))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (1621:1774:1928)(1621:1774:1928))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/D1 (1614:1766:1919)(1614:1766:1919))
+        (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/A1 (1908:2101:2294)(1908:2101:2294))
+        (INTERCONNECT SLICE_67/F1 SLICE_73/CE (947:1062:1178)(947:1062:1178))
+        (INTERCONNECT SLICE_67/F1 SLICE_74/CE (1350:1494:1639)(1350:1494:1639))
+        (INTERCONNECT SLICE_67/Q1 SLICE_93/D1 (1063:1157:1251)(1063:1157:1251))
+        (INTERCONNECT SLICE_87/F0 SLICE_68/C0 (735:822:909)(735:822:909))
+        (INTERCONNECT SLICE_87/F0 SLICE_69/D0 (580:648:716)(580:648:716))
+        (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_84/F0 SLICE_68/A0 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_84/F0 SLICE_69/A0 (786:876:966)(786:876:966))
+        (INTERCONNECT SLICE_69/F1 SLICE_69/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_70/Q0 SLICE_70/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (723:805:887)(723:805:887))
+        (INTERCONNECT SLICE_70/Q1 SLICE_70/A1 (514:575:636)(514:575:636))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/C1 (1805:1987:2169)(1805:1987:2169))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (1657:1821:1985)(1657:1821:1985))
+        (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/B1 (2368:2598:2829)(2368:2598:2829))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/B1 (1951:2152:2353)(1951:2152:2353))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (2353:2581:2809)(2353:2581:2809))
+        (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/C1 (3008:3283:3558)(3008:3283:3558))
+        (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (510:568:626)(510:568:626))
+        (INTERCONNECT SLICE_71/Q1 SLICE_71/C0 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (825:921:1018)(825:921:1018))
+        (INTERCONNECT SLICE_88/F1 SLICE_71/A0 (1490:1668:1846)(1490:1668:1846))
+        (INTERCONNECT SLICE_81/F1 SLICE_72/D1 (510:568:626)(510:568:626))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (1657:1821:1985)(1657:1821:1985))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/A1 (1919:2113:2308)(1919:2113:2308))
+        (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (2322:2545:2769)(2322:2545:2769))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (1606:1757:1909)(1606:1757:1909))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/B1 (1519:1681:1844)(1519:1681:1844))
+        (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/B0 (2326:2552:2779)(2326:2552:2779))
+        (INTERCONNECT SLICE_72/Q0 SLICE_92/C0 (1653:1804:1956)(1653:1804:1956))
+        (INTERCONNECT SLICE_72/Q1 SLICE_93/D0 (1466:1589:1712)(1466:1589:1712))
+        (INTERCONNECT SLICE_74/Q0 SLICE_87/C1 (665:742:819)(665:742:819))
+        (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (528:587:647)(528:587:647))
+        (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (400:448:497)(400:448:497))
+        (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (1164:1346:1528)(1164:1346:1528))
+        (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (560:628:696)(560:628:696))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C1 (1769:1940:2112)(1769:1940:2112))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C0 (1769:1940:2112)(1769:1940:2112))
+        (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2608:2849:3090)(2608:2849:3090))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828))
+        (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/C0 (3001:3275:3550)(3001:3275:3550))
+        (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (1247:1397:1548)(1247:1397:1548))
+        (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (1378:1510:1643)(1378:1510:1643))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1654:1819:1984)(1654:1819:1984))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (2204:2414:2624)(2204:2414:2624))
+        (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (2204:2414:2624)(2204:2414:2624))
+        (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (2038:2228:2418)(2038:2228:2418))
+        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (2307:2528:2750)(2307:2528:2750))
+        (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (1165:1345:1526)(1165:1345:1526))
+        (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2466:2735:3005)(2466:2735:3005))
+        (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1568:1777:1987)(1568:1777:1987))
+        (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (2477:2778:3080)(2477:2778:3080))
+        (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1532:1758:1984)(1532:1758:1984))
+        (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1756:2001:2247)(1756:2001:2247))
+        (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2571:2883:3195)(2571:2883:3195))
+        (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2571:2883:3195)(2571:2883:3195))
+        (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2538:2838:3139)(2538:2838:3139))
+        (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (2538:2838:3139)(2538:2838:3139))
+        (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (1741:1997:2254)(1741:1997:2254))
+        (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1741:1997:2254)(1741:1997:2254))
+        (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (2098:2368:2638)(2098:2368:2638))
+        (INTERCONNECT SLICE_88/Q0 SLICE_92/A1 (1735:1889:2044)(1735:1889:2044))
+        (INTERCONNECT SLICE_88/Q1 SLICE_91/C1 (1218:1331:1444)(1218:1331:1444))
+        (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1979:2229:2479)(1979:2229:2479))
+        (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (1723:1947:2172)(1723:1947:2172))
+        (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1971:2209:2448)(1971:2209:2448))
+        (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660))
+        (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (1168:1345:1522)(1168:1345:1522))
+        (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1610:1831:2052)(1610:1831:2052))
+        (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475))
+        (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (646:731:817)(646:731:817))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2942:3272:3602)(2942:3272:3602))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2505:2806:3107)(2505:2806:3107))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2508:2805:3103)(2508:2805:3103))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2540:2847:3154)(2540:2847:3154))
+      )
+    )
+  )
+)
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo
index 7ec7a54..14b38c2 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo
@@ -1,3718 +1,3718 @@
-
-// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
-// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_vo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd 
-// Netlist created on Wed Aug 16 04:50:46 2023
-// Netlist written on Wed Aug 16 04:50:54 2023
-// Design is for device LCMXO640C
-// Design is for package TQFP100
-// Design is for performance grade 3
-
-`timescale 1 ns / 1 ps
-
-module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
-                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
-                UFMCLK, UFMSDI, UFMSDO );
-  input  PHI2;
-  input  [9:0] MAin;
-  input  [1:0] CROW;
-  input  [7:0] Din;
-  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
-  output [7:0] Dout;
-  output LED;
-  output [1:0] RBA;
-  output [11:0] RA;
-  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
-  inout  [7:0] RD;
-  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
-         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
-         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
-         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
-         \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, N_147, 
-         CmdEnable17_0_a2_3, \MAin_c[0] , ADSubmitted, C1WR_0_a2, CmdEnable17, 
-         CmdEnable16, ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, 
-         CmdEnable16_0_a2_4, \MAin_c[1] , C1Submitted, C1Submitted_RNO, CO0, 
-         \S[1] , \IS[3] , RASr2, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, 
-         un1_CMDWR, CmdEnable_s, \Din_c[5] , \Din_c[3] , N_128, N_152, LEDEN, 
-         N_133, N_132, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, PHI2r3, 
-         PHI2r2, InitReady, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, 
-         Cmdn8MEGEN, CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, N_160, 
-         N_155, nRRAS_5_u_i_0, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , 
-         \IS[1] , N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, 
-         UFMSDI_ens2_i_a2_4_2, N_51, InitReady3, N_461_0, UFMSDI_ens2_i_a0, 
-         nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, XOR8MEG, un1_Din_4, 
-         \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, FWEr_fast, CASr2, 
-         RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RASr, RASr3, 
-         RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, 
-         Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, 
-         UFMCLK_r_i_a2_2_2, N_139_i, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, UFMCLK_c, 
-         UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \RowA[4] , 
-         nRowColSel, \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , 
-         \WRD[5] , \Bank[5] , \Bank[2] , \Bank[6] , \Bank[7] , \Din_c[7] , 
-         \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , \Din_c[0] , 
-         \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, 
-         nRCAS_0_sqmuxa_1, g0_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, 
-         N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, FWEr, m18_0_a2_1, 
-         G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, 
-         nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, 
-         \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , 
-         N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , 
-         C1WR_0_a2_0_10, \Bank[1] , \MAin_c[7] , \MAin_c[6] , C1WR_0_a2_0_4, 
-         \Bank[3] , \Bank[4] , C1WR_0_a2_0_3, UFMSDI_ens2_i_o2_0_3, 
-         \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, 
-         CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , 
-         \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , 
-         \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, 
-         RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , 
-         \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , 
-         \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
-         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
-
-  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
-    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
-  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
-  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
-  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
-  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
-  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
-    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
-  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
-    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
-  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
-    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
-  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
-    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
-  SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(N_147), 
-    .B1(CmdEnable17_0_a2_3), .A1(\MAin_c[0] ), .D0(ADSubmitted), 
-    .C0(C1WR_0_a2), .B0(CmdEnable17), .A0(CmdEnable16), .DI0(ADSubmitted_r), 
-    .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
-  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
-    .A1(CmdEnable16_0_a2_4), .D0(CmdEnable16), .C0(N_147), .B0(\MAin_c[1] ), 
-    .A0(C1Submitted), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
-    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
-  SLICE_19 SLICE_19( .D1(CO0), .C1(\S[1] ), .B1(\IS[3] ), .A1(RASr2), 
-    .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
-  SLICE_20 SLICE_20( .D1(CmdEnable), .A1(ADSubmitted), .D0(CmdEnable17), 
-    .C0(C1Submitted), .B0(un1_CMDWR), .A0(CmdEnable), .DI0(CmdEnable_s), 
-    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
-  SLICE_21 SLICE_21( .D1(\Din_c[5] ), .C1(\Din_c[3] ), .B1(N_128), .D0(N_152), 
-    .C0(LEDEN), .B0(N_133), .A0(N_132), .DI0(N_21_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
-  SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(PHI2r3), .B1(PHI2r2), 
-    .A1(InitReady), .D0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), 
-    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
-  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
-    .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), 
-    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
-    .F1(Cmdn8MEGEN_4_u_i_0));
-  SLICE_29 SLICE_29( .D1(N_160), .C1(N_155), .B1(nRRAS_5_u_i_0), .A1(\IS[0] ), 
-    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
-    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
-  SLICE_30 SLICE_30( .D1(\IS[0] ), .C1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), 
-    .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
-    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
-  SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), 
-    .D0(\IS[2] ), .C0(\IS[3] ), .B0(\IS[1] ), .A0(\IS[0] ), .DI0(N_61_i_i), 
-    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
-  SLICE_32 SLICE_32( .D1(N_126), .C1(InitReady), .B1(UFMSDI_ens2_i_a2_4_2), 
-    .A1(N_51), .D0(InitReady3), .A0(InitReady), .DI0(N_461_0), .CLK(RCLK_c), 
-    .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
-  SLICE_33 SLICE_33( .D1(LEDEN), .C1(nCRAS_c), .A1(CBR), .D0(InitReady), 
-    .B0(CmdLEDEN), .A0(UFMSDO_c), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
-    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
-  SLICE_39 SLICE_39( .D1(XOR8MEG), .B1(un1_Din_4), .D0(XOR8MEG), 
-    .B0(\Din_c[6] ), .A0(n8MEGEN), .DI0(RA11_2), .LSR(Ready_fast), 
-    .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171));
-  SLICE_41 SLICE_41( .D1(CO0), .C1(FWEr_fast), .B1(CASr2), .A1(\S[1] ), 
-    .D0(CBR), .C0(RCKEEN_8_u_1), .B0(Ready), .A0(RCKEEN_8_u_0_0), 
-    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
-    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
-  SLICE_42 SLICE_42( .D1(\IS[1] ), .C1(\IS[2] ), .B1(\IS[0] ), .A1(RASr2), 
-    .D0(RASr), .C0(RASr3), .B0(RCKEEN), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), 
-    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
-  SLICE_43 SLICE_43( .D1(Ready), .C1(\S_0_i_o2[1] ), .B1(RASr2), 
-    .A1(InitReady), .D0(Ready), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
-    .A0(InitReady), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
-    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
-  SLICE_44 SLICE_44( .D1(Ready), .C1(N_165), .B1(Ready_0_sqmuxa_0_a3_2), 
-    .A1(InitReady), .B0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), 
-    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
-    .F1(Ready_0_sqmuxa), .Q1(RASr));
-  SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ), 
-    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
-    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
-  SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(InitReady), .B1(N_129), 
-    .A1(UFMCLK_r_i_a2_2_2), .D0(N_139_i), .C0(UFMCLK_r_i_m4_xx_mm_1), 
-    .B0(nUFMCS15), .A0(UFMCLK_c), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), 
-    .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
-  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(InitReady), .B1(PHI2r2), 
-    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), 
-    .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
-    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
-  SLICE_55 SLICE_55( .D0(\RowA[4] ), .B0(nRowColSel), .A0(\MAin_c[4] ), 
-    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
-    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
-  SLICE_56 SLICE_56( .D1(\Bank[5] ), .C1(\Bank[2] ), .B1(\Bank[6] ), 
-    .A1(\Bank[7] ), .D0(\FS[5] ), .C0(\FS[9] ), .A0(\FS[7] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
-    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
-  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[0] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), 
-    .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), 
-    .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
-  SLICE_58 SLICE_58( .D1(N_51), .C1(\FS[8] ), .A1(InitReady), .D0(UFMSDO_c), 
-    .B0(Cmdn8MEGEN), .A0(InitReady), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
-    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
-  SLICE_59 SLICE_59( .D1(Ready), .C1(\S[1] ), .B1(N_155), .A1(N_160), 
-    .D0(N_41), .C0(nRCAS_0_sqmuxa_1), .B0(\S[1] ), .A0(g0_1), .DI0(N_37_i), 
-    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
-  SLICE_60 SLICE_60( .D1(CASr3), .C1(CO0), .B1(FWEr_fast), .A1(CASr2), 
-    .D0(CBR), .C0(RCKEEN_8_u_0_a2_1_out), .B0(N_24), .A0(N_28_i_1), 
-    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
-  SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(Ready), .B1(RASr2), .A1(RCKE_c), 
-    .D0(N_160), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(\IS[0] ), .DI0(N_24_i), 
-    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
-  SLICE_62 SLICE_62( .D1(CBR_fast), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(RASr2), 
-    .D0(FWEr), .C0(m18_0_a2_1), .B0(nRCAS_0_sqmuxa_1), .A0(G_17_1), 
-    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
-    .F1(nRCAS_0_sqmuxa_1));
-  SLICE_63 SLICE_63( .D1(CASr3), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(N_179), 
-    .C0(Ready), .B0(CO0), .A0(\S[1] ), .DI0(nRowColSel_0_0), 
-    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
-    .F1(N_179));
-  SLICE_64 SLICE_64( .D1(\FS[10] ), .C1(N_51), .B1(\FS[11] ), .A1(InitReady), 
-    .D0(nUFMCS_c), .C0(nUFMCS_s_0_N_5_i_N_2L1), .B0(nUFMCS15), .A0(N_139_i), 
-    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
-    .F1(nUFMCS15));
-  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
-    .A1(\S[1] ), .D0(\S[1] ), .C0(m18_0_a3_3), .B0(CO0), .A0(InitReady), 
-    .M0(Ready), .OFX0(m18_0_a2_1));
-  SLICE_66 SLICE_66( .C1(InitReady), .B1(CmdUFMCS), .A1(UFMCLK_r_i_a2_2_2), 
-    .D0(N_95_5), .C0(InitReady), .B0(\FS[16] ), .A0(N_95_3), .M1(\MAin_c[1] ), 
-    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
-    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
-  SLICE_67 SLICE_67( .D1(\Din_c[5] ), .C1(XOR8MEG18), .B1(\Din_c[3] ), 
-    .A1(N_128), .D0(\MAin_c[1] ), .C0(\MAin_c[0] ), .B0(CmdEnable), .A0(N_147), 
-    .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), 
-    .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), .Q1(\RowA[5] ));
-  SLICE_68 SLICE_68( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), 
-    .D0(N_136), .C0(N_137_8), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), 
-    .F1(un1_FS_14_i_a2_0_1));
-  SLICE_69 SLICE_69( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), 
-    .D0(N_137_8), .C0(un1_FS_13_i_a2_1), .B0(N_136), .A0(N_137_6), .F0(N_33), 
-    .F1(un1_FS_13_i_a2_1));
-  SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), 
-    .A1(\Bank[1] ), .C0(\MAin_c[1] ), .B0(N_147), .M1(\Din_c[1] ), 
-    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
-    .Q1(\Bank[1] ));
-  SLICE_71 SLICE_71( .D1(\MAin_c[5] ), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), 
-    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(\Bank[3] ), .B0(\Bank[4] ), 
-    .A0(C1WR_0_a2_0_3), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
-    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
-  SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), 
-    .D0(\FS[1] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[4] ), .M1(\MAin_c[3] ), 
-    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
-    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
-  SLICE_73 SLICE_73( .D1(\S[1] ), .C1(RASr2), .B1(CO0), .A1(InitReady), 
-    .B0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
-    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
-    .F1(N_155), .Q1(CmdUFMCS));
-  SLICE_74 SLICE_74( .D1(\FS[14] ), .B1(\FS[11] ), .D0(\FS[16] ), .C0(N_95_3), 
-    .B0(\FS[10] ), .A0(N_95_5), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
-  SLICE_75 SLICE_75( .C1(\Din_c[4] ), .B1(\Din_c[7] ), .A1(\Din_c[6] ), 
-    .D0(\Din_c[1] ), .C0(N_128), .A0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), 
-    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
-  SLICE_76 SLICE_76( .D1(\Din_c[5] ), .B1(\Din_c[0] ), .D0(\MAin_c[0] ), 
-    .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), 
-    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
-    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
-  SLICE_77 SLICE_77( .C1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
-    .C0(CmdEnable16_1), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(\Din_c[7] ), 
-    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
-    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
-  SLICE_78 SLICE_78( .C1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), 
-    .C0(\Din_c[6] ), .B0(N_43), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), 
-    .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast));
-  SLICE_79 SLICE_79( .D1(CASr3), .C1(Ready), .B1(CASr2), .D0(CO0), 
-    .C0(m6_0_a2_2), .B0(CBR), .A0(\S[1] ), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
-    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
-  SLICE_80 SLICE_80( .C1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CBR_fast), 
-    .B0(g4_0_0_0), .A0(CO0), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
-    .Q1(\RowA[9] ));
-  SLICE_81 SLICE_81( .D1(\FS[14] ), .C1(\FS[17] ), .B1(\FS[15] ), 
-    .A1(\FS[13] ), .D0(\FS[12] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[13] ), 
-    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
-    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
-  SLICE_82 SLICE_82( .D1(\Din_c[5] ), .C1(CmdLEDEN), .B1(N_128), 
-    .A1(\Din_c[3] ), .D0(\Din_c[5] ), .C0(XOR8MEG18), .B0(N_128), 
-    .A0(\Din_c[3] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), 
-    .Q0(CASr3), .F1(N_132));
-  SLICE_83 SLICE_83( .C1(\IS[2] ), .B1(\IS[3] ), .A1(\IS[1] ), .D0(\IS[0] ), 
-    .C0(\IS[2] ), .A0(\IS[1] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
-    .Q1(\RBA_c[1] ));
-  SLICE_84 SLICE_84( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[6] ), 
-    .D0(\FS[7] ), .C0(\FS[1] ), .B0(\FS[10] ), .A0(\FS[6] ), .F0(N_137_6), 
-    .F1(UFMSDI_ens2_i_a2_4_2));
-  SLICE_85 SLICE_85( .D1(\Din_c[1] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), 
-    .A1(\Din_c[0] ), .D0(\Din_c[6] ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), 
-    .A0(\Din_c[5] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
-    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
-  SLICE_86 SLICE_86( .C1(\MAin_c[9] ), .A1(nRowColSel), .C0(\MAin_c[9] ), 
-    .B0(\RowA[9] ), .A0(nRowColSel), .F0(\RA_c[9] ), .F1(RDQML_c));
-  SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .C1(CmdUFMSDI), .B1(N_151), 
-    .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), 
-    .F1(UFMSDI_r_xx_mm_1));
-  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[2] ), .A1(\MAin_c[3] ), 
-    .D0(nCCAS_c), .C0(nFWE_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
-    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
-    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
-  SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), 
-    .C0(\MAin_c[8] ), .B0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
-  SLICE_90 SLICE_90( .C1(N_147), .B1(\MAin_c[0] ), .A1(\MAin_c[1] ), 
-    .D0(\RowA[0] ), .B0(\MAin_c[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), 
-    .F1(un1_CMDWR));
-  SLICE_91 SLICE_91( .D1(nRowColSel), .C1(\RowA[7] ), .B1(\MAin_c[7] ), 
-    .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), 
-    .F1(\RA_c[7] ));
-  SLICE_92 SLICE_92( .D1(nRowColSel), .C1(\MAin_c[6] ), .A1(\RowA[6] ), 
-    .D0(nRowColSel), .C0(\RowA[2] ), .B0(\MAin_c[2] ), .F0(\RA_c[2] ), 
-    .F1(\RA_c[6] ));
-  SLICE_93 SLICE_93( .D1(\RowA[5] ), .B1(nRowColSel), .A1(\MAin_c[5] ), 
-    .D0(\RowA[3] ), .B0(nRowColSel), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
-    .F1(\RA_c[5] ));
-  SLICE_94 SLICE_94( .D1(Ready), .C1(N_155), .D0(Ready), .C0(\S[1] ), 
-    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
-    .Q0(\RA_c[10] ), .F1(N_159_i));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
-    .RD0(RD[0]));
-  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
-  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
-  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
-  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
-  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
-  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
-  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
-  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
-  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
-  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
-  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
-  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
-  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
-  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
-    .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
-    .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
-    .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
-    .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
-    .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
-    .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
-    .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
-  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
-  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
-  LED LED_I( .PADDO(LED_c), .LED(LED));
-  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
-  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
-  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
-  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
-  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
-  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
-  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
-  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
-  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
-  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
-  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
-  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
-  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
-  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
-  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
-  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
-  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
-  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
-  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
-  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
-  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
-  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
-  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
-  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
-  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
-  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
-  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
-  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
-  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
-  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
-  VHI VHI_INST( .Z(VCCI));
-  PUR PUR_INST( .PUR(VCCI));
-  GSR GSR_INST( .GSR(VCCI));
-  VLO VLO_INST( .Z(GNDI_TSALL));
-  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
-endmodule
-
-module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
-         A1_dly, CLK_dly, A0_dly;
-
-  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
-    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-  endspecify
-
-endmodule
-
-module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module vcc ( output PWR1 );
-
-  VHI INST1( .Z(PWR1));
-endmodule
-
-module gnd ( output PWR0 );
-
-  VLO INST1( .Z(PWR0));
-endmodule
-
-module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h300a;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
-  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
-    .CO1());
-
-  specify
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
-    CO1 );
-
-  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
-  defparam inst1.INIT0 = 16'h300a;
-  defparam inst1.INIT1 = 16'h5002;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
-  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
-         A1_dly, CLK_dly, A0_dly, FCI_dly;
-
-  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
-    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
-    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
-    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
-    .CO1(FCO));
-
-  specify
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
-    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
-    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
-  endspecify
-
-endmodule
-
-module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
-
-  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut4 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40002 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4544) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
-module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40003 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40004 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40005 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40006 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_20 ( input D1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
-         CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40008 SLICE_20_K1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), 
-    .Z(\SLICE_20/SLICE_20_K1_H1 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
-  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
-    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEA22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
-  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_21 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40012 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40014 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40017 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_30 ( input D1, C1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40018 \IS_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5AF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40013 InitReady_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40022 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0B0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_33 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40023 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40024 LEDEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCC55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input D1, B1, D0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40025 XOR8MEG_3_u_0_a3_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 RA11_2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40026 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBB44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40027 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40028 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40027 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h75A5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40028 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40029 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40030 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDCD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40031 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40032 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h03AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40033 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40034 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_50 ( input D1, C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40035 nRowColSel_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40036 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40037 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40038 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hABFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40039 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40040 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40039 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40040 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40041 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40042 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40043 UFMSDI_ens2_i_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40044 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40045 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40044 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40046 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40047 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h88DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40048 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40049 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0050 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0FDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0F04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0050 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40051 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40052 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0050 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFC7C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3323) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40053 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40054 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0050 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40053 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40055 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40056 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0050 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40056 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCDEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40057 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40058 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF60) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40059 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0050 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40059 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
-    OFX0 );
-  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
-         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
-
-  lut40061 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
-  lut40062 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
-  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
-    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
-    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (C1 => OFX0) = (0:0:0,0:0:0);
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40063 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40064 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40065 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40066 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0067 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40066 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0067 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40068 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40069 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40070 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40071 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40071 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, C0, B0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40072 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 C1WR_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40072 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40073 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
-
-  lut40074 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40075 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40074 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40075 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40076 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40076 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
-
-  lut40078 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40034 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_74 ( input D1, B1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
-
-  lut40079 InitReady3_0_a2_3( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40080 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_75 ( input C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40081 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40082 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40082 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40083 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40084 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40083 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40084 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40085 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40086 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40085 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40086 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40087 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40088 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40087 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40088 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40089 nRWE_RNO_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40090 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40089 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40090 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40091 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40092 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0067 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40091 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40092 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0805) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40093 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40094 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40093 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40094 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, M0_dly, CLK_dly;
-
-  lut40095 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40096 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40095 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0E0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40096 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h1030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input C1, B1, A1, D0, C0, A0, M1, M0, LSR, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40097 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40098 Ready_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40097 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40098 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40099 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40099 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40100 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
-  lut40101 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40102 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40101 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40102 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_86 ( input C1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40103 RDQML( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40103 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40104 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_87 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40105 UFMSDI_RNO_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40106 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40105 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h00FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40106 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input C1, B1, A1, D0, C0, M1, M0, LSR, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
-
-  lut40107 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40108 nCCAS_pad_RNI01SJ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-  endspecify
-
-endmodule
-
-module lut40107 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40108 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input D1, C1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40109 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40110 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40109 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40110 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40111 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40112 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40111 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40112 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input D1, C1, B1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40113 \un9_RA[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40114 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40113 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40114 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40115 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40113 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40115 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_93 ( input D1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40041 \un9_RA[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_94 ( input D1, C1, D0, C0, M0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
-
-  lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40117 RCKEEN_8_u_0_a2_1_s( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0067 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40116 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40117 ( input A, B, C, D, output Z );
-
-  ROM16X1 #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
-
-  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
-
-  specify
-    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD0) = (0:0:0,0:0:0);
-    (RD0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD0, 0:0:0);
-    $width (negedge RD0, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf ( input I, T, output Z, PAD, input PADI );
-
-  IB INST1( .I(PADI), .O(Z));
-  OBW INST2( .I(I), .T(T), .O(PAD));
-endmodule
-
-module Dout_0_ ( input PADDO, output Dout0 );
-
-  mjiobuf0118 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
-
-  specify
-    (PADDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0118 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module PHI2 ( output PADDI, input PHI2 );
-
-  mjiobuf0119 PHI2_pad( .Z(PADDI), .PAD(PHI2));
-
-  specify
-    (PHI2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge PHI2, 0:0:0);
-    $width (negedge PHI2, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0119 ( output Z, input PAD );
-
-  IBPD INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDO ( output PADDI, input UFMSDO );
-
-  mjiobuf0120 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
-
-  specify
-    (UFMSDO => PADDI) = (0:0:0,0:0:0);
-    $width (posedge UFMSDO, 0:0:0);
-    $width (negedge UFMSDO, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0120 ( output Z, input PAD );
-
-  IB INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDI ( input PADDO, output UFMSDI );
-
-  mjiobuf0121 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
-
-  specify
-    (PADDO => UFMSDI) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0121 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module UFMCLK ( input PADDO, output UFMCLK );
-
-  mjiobuf0121 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
-
-  specify
-    (PADDO => UFMCLK) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS ( input PADDO, output nUFMCS );
-
-  mjiobuf0121 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
-
-  specify
-    (PADDO => nUFMCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQML ( input PADDO, output RDQML );
-
-  mjiobuf0121 RDQML_pad( .I(PADDO), .PAD(RDQML));
-
-  specify
-    (PADDO => RDQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQMH ( input PADDO, output RDQMH );
-
-  mjiobuf0121 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
-
-  specify
-    (PADDO => RDQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS ( input PADDO, output nRCAS );
-
-  mjiobuf0121 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
-
-  specify
-    (PADDO => nRCAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS ( input PADDO, output nRRAS );
-
-  mjiobuf0121 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
-
-  specify
-    (PADDO => nRRAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE ( input PADDO, output nRWE );
-
-  mjiobuf0121 nRWE_pad( .I(PADDO), .PAD(nRWE));
-
-  specify
-    (PADDO => nRWE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE ( input PADDO, output RCKE );
-
-  mjiobuf0121 RCKE_pad( .I(PADDO), .PAD(RCKE));
-
-  specify
-    (PADDO => RCKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCLK ( output PADDI, input RCLK );
-
-  mjiobuf0120 RCLK_pad( .Z(PADDI), .PAD(RCLK));
-
-  specify
-    (RCLK => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RCLK, 0:0:0);
-    $width (negedge RCLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS ( input PADDO, output nRCS );
-
-  mjiobuf0121 nRCS_pad( .I(PADDO), .PAD(nRCS));
-
-  specify
-    (PADDO => nRCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
-
-  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
-
-  specify
-    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD7) = (0:0:0,0:0:0);
-    (RD7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD7, 0:0:0);
-    $width (negedge RD7, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
-
-  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
-
-  specify
-    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD6) = (0:0:0,0:0:0);
-    (RD6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD6, 0:0:0);
-    $width (negedge RD6, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
-
-  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
-
-  specify
-    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD5) = (0:0:0,0:0:0);
-    (RD5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD5, 0:0:0);
-    $width (negedge RD5, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
-
-  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
-
-  specify
-    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD4) = (0:0:0,0:0:0);
-    (RD4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD4, 0:0:0);
-    $width (negedge RD4, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
-
-  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
-
-  specify
-    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD3) = (0:0:0,0:0:0);
-    (RD3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD3, 0:0:0);
-    $width (negedge RD3, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
-
-  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
-
-  specify
-    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD2) = (0:0:0,0:0:0);
-    (RD2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD2, 0:0:0);
-    $width (negedge RD2, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
-
-  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
-
-  specify
-    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-    (PADDO => RD1) = (0:0:0,0:0:0);
-    (RD1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RD1, 0:0:0);
-    $width (negedge RD1, 0:0:0);
-  endspecify
-
-endmodule
-
-module RA_11_ ( input PADDO, output RA11 );
-
-  mjiobuf0121 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
-
-  specify
-    (PADDO => RA11) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10_ ( input PADDO, output RA10 );
-
-  mjiobuf0121 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
-
-  specify
-    (PADDO => RA10) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_9_ ( input PADDO, output RA9 );
-
-  mjiobuf0121 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
-
-  specify
-    (PADDO => RA9) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_8_ ( input PADDO, output RA8 );
-
-  mjiobuf0121 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
-
-  specify
-    (PADDO => RA8) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_7_ ( input PADDO, output RA7 );
-
-  mjiobuf0121 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
-
-  specify
-    (PADDO => RA7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_6_ ( input PADDO, output RA6 );
-
-  mjiobuf0121 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
-
-  specify
-    (PADDO => RA6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_5_ ( input PADDO, output RA5 );
-
-  mjiobuf0121 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
-
-  specify
-    (PADDO => RA5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_4_ ( input PADDO, output RA4 );
-
-  mjiobuf0121 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
-
-  specify
-    (PADDO => RA4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_3_ ( input PADDO, output RA3 );
-
-  mjiobuf0121 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
-
-  specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2_ ( input PADDO, output RA2 );
-
-  mjiobuf0121 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
-
-  specify
-    (PADDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_1_ ( input PADDO, output RA1 );
-
-  mjiobuf0121 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
-
-  specify
-    (PADDO => RA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_0_ ( input PADDO, output RA0 );
-
-  mjiobuf0121 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
-
-  specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1_ ( input PADDO, output RBA1 );
-
-  mjiobuf0121 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
-
-  specify
-    (PADDO => RBA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_0_ ( input PADDO, output RBA0 );
-
-  mjiobuf0121 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
-
-  specify
-    (PADDO => RBA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module LED ( input PADDO, output LED );
-
-  mjiobuf0122 LED_pad( .I(PADDO), .PAD(LED));
-
-  specify
-    (PADDO => LED) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0122 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module nFWE ( output PADDI, input nFWE );
-
-  mjiobuf0120 nFWE_pad( .Z(PADDI), .PAD(nFWE));
-
-  specify
-    (nFWE => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nFWE, 0:0:0);
-    $width (negedge nFWE, 0:0:0);
-  endspecify
-
-endmodule
-
-module nCRAS ( output PADDI, input nCRAS );
-
-  mjiobuf0123 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
-
-  specify
-    (nCRAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCRAS, 0:0:0);
-    $width (negedge nCRAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module mjiobuf0123 ( output Z, input PAD );
-
-  IBPU INST1( .I(PAD), .O(Z));
-endmodule
-
-module nCCAS ( output PADDI, input nCCAS );
-
-  mjiobuf0123 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
-
-  specify
-    (nCCAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCCAS, 0:0:0);
-    $width (negedge nCCAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_7_ ( input PADDO, output Dout7 );
-
-  mjiobuf0118 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
-
-  specify
-    (PADDO => Dout7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_6_ ( input PADDO, output Dout6 );
-
-  mjiobuf0118 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
-
-  specify
-    (PADDO => Dout6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_5_ ( input PADDO, output Dout5 );
-
-  mjiobuf0118 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
-
-  specify
-    (PADDO => Dout5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_4_ ( input PADDO, output Dout4 );
-
-  mjiobuf0118 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
-
-  specify
-    (PADDO => Dout4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input PADDO, output Dout3 );
-
-  mjiobuf0118 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
-
-  specify
-    (PADDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input PADDO, output Dout2 );
-
-  mjiobuf0118 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
-
-  specify
-    (PADDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input PADDO, output Dout1 );
-
-  mjiobuf0118 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
-
-  specify
-    (PADDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7_ ( output PADDI, input Din7 );
-
-  mjiobuf0120 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
-
-  specify
-    (Din7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din7, 0:0:0);
-    $width (negedge Din7, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6_ ( output PADDI, input Din6 );
-
-  mjiobuf0120 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
-
-  specify
-    (Din6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din6, 0:0:0);
-    $width (negedge Din6, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5_ ( output PADDI, input Din5 );
-
-  mjiobuf0120 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
-
-  specify
-    (Din5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din5, 0:0:0);
-    $width (negedge Din5, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4_ ( output PADDI, input Din4 );
-
-  mjiobuf0120 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
-
-  specify
-    (Din4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din4, 0:0:0);
-    $width (negedge Din4, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3_ ( output PADDI, input Din3 );
-
-  mjiobuf0120 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
-
-  specify
-    (Din3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din3, 0:0:0);
-    $width (negedge Din3, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2_ ( output PADDI, input Din2 );
-
-  mjiobuf0120 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
-
-  specify
-    (Din2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din2, 0:0:0);
-    $width (negedge Din2, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_1_ ( output PADDI, input Din1 );
-
-  mjiobuf0120 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
-
-  specify
-    (Din1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din1, 0:0:0);
-    $width (negedge Din1, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_0_ ( output PADDI, input Din0 );
-
-  mjiobuf0120 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
-
-  specify
-    (Din0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din0, 0:0:0);
-    $width (negedge Din0, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_1_ ( output PADDI, input CROW1 );
-
-  mjiobuf0120 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
-
-  specify
-    (CROW1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW1, 0:0:0);
-    $width (negedge CROW1, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_0_ ( output PADDI, input CROW0 );
-
-  mjiobuf0120 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
-
-  specify
-    (CROW0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW0, 0:0:0);
-    $width (negedge CROW0, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_9_ ( output PADDI, input MAin9 );
-
-  mjiobuf0120 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
-
-  specify
-    (MAin9 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin9, 0:0:0);
-    $width (negedge MAin9, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_8_ ( output PADDI, input MAin8 );
-
-  mjiobuf0120 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
-
-  specify
-    (MAin8 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin8, 0:0:0);
-    $width (negedge MAin8, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_7_ ( output PADDI, input MAin7 );
-
-  mjiobuf0120 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
-
-  specify
-    (MAin7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin7, 0:0:0);
-    $width (negedge MAin7, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_6_ ( output PADDI, input MAin6 );
-
-  mjiobuf0120 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
-
-  specify
-    (MAin6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin6, 0:0:0);
-    $width (negedge MAin6, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_5_ ( output PADDI, input MAin5 );
-
-  mjiobuf0120 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
-
-  specify
-    (MAin5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin5, 0:0:0);
-    $width (negedge MAin5, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_4_ ( output PADDI, input MAin4 );
-
-  mjiobuf0120 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
-
-  specify
-    (MAin4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin4, 0:0:0);
-    $width (negedge MAin4, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_3_ ( output PADDI, input MAin3 );
-
-  mjiobuf0120 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
-
-  specify
-    (MAin3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin3, 0:0:0);
-    $width (negedge MAin3, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_2_ ( output PADDI, input MAin2 );
-
-  mjiobuf0120 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
-
-  specify
-    (MAin2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin2, 0:0:0);
-    $width (negedge MAin2, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_1_ ( output PADDI, input MAin1 );
-
-  mjiobuf0120 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
-
-  specify
-    (MAin1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin1, 0:0:0);
-    $width (negedge MAin1, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_0_ ( output PADDI, input MAin0 );
-
-  mjiobuf0120 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
-
-  specify
-    (MAin0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin0, 0:0:0);
-    $width (negedge MAin0, 0:0:0);
-  endspecify
-
-endmodule
+
+// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
+
+// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_vo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd 
+// Netlist created on Sat Aug 19 20:57:13 2023
+// Netlist written on Sat Aug 19 20:57:25 2023
+// Design is for device LCMXO640C
+// Design is for package TQFP100
+// Design is for performance grade 3
+
+`timescale 1 ns / 1 ps
+
+module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
+                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
+                UFMCLK, UFMSDI, UFMSDO );
+  input  PHI2;
+  input  [9:0] MAin;
+  input  [1:0] CROW;
+  input  [7:0] Din;
+  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
+  output [7:0] Dout;
+  output LED;
+  output [1:0] RBA;
+  output [11:0] RA;
+  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
+  inout  [7:0] RD;
+  wire   \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] , 
+         \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , 
+         \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , 
+         \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , 
+         \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, N_147, 
+         CmdEnable17_0_a2_3, \MAin_c[0] , ADSubmitted, C1WR_0_a2, CmdEnable17, 
+         CmdEnable16, ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, 
+         CmdEnable16_0_a2_4, \MAin_c[1] , C1Submitted, C1Submitted_RNO, CO0, 
+         \S[1] , \IS[3] , RASr2, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, 
+         un1_CMDWR, CmdEnable_s, \Din_c[5] , \Din_c[3] , N_128, N_152, LEDEN, 
+         N_133, N_132, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, PHI2r3, 
+         PHI2r2, InitReady, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, 
+         Cmdn8MEGEN, CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, N_160, 
+         N_155, nRRAS_5_u_i_0, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , 
+         \IS[1] , N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, 
+         UFMSDI_ens2_i_a2_4_2, N_51, InitReady3, N_461_0, UFMSDI_ens2_i_a0, 
+         nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, XOR8MEG, un1_Din_4, 
+         \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, FWEr_fast, CASr2, 
+         RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RASr, RASr3, 
+         RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, 
+         Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, 
+         UFMCLK_r_i_a2_2_2, N_139_i, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, UFMCLK_c, 
+         UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \RowA[4] , 
+         nRowColSel, \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , 
+         \WRD[5] , \Bank[5] , \Bank[2] , \Bank[6] , \Bank[7] , \Din_c[7] , 
+         \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , \Din_c[0] , 
+         \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, 
+         nRCAS_0_sqmuxa_1, g0_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, 
+         N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, FWEr, m18_0_a2_1, 
+         G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, 
+         nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, 
+         \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , 
+         N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , 
+         C1WR_0_a2_0_10, \Bank[1] , \MAin_c[7] , \MAin_c[6] , C1WR_0_a2_0_4, 
+         \Bank[3] , \Bank[4] , C1WR_0_a2_0_3, UFMSDI_ens2_i_o2_0_3, 
+         \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, 
+         CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , 
+         \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , 
+         \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, 
+         RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , 
+         \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , 
+         \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , 
+         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL;
+
+  SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), 
+    .Q1(\FS[1] ), .FCO(\FS_cry[1] ));
+  SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
+  SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
+  SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
+  SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c), 
+    .FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
+  SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ), 
+    .Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
+  SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ), 
+    .Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
+  SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ), 
+    .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
+  SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), 
+    .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
+  SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(N_147), 
+    .B1(CmdEnable17_0_a2_3), .A1(\MAin_c[0] ), .D0(ADSubmitted), 
+    .C0(C1WR_0_a2), .B0(CmdEnable17), .A0(CmdEnable16), .DI0(ADSubmitted_r), 
+    .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17));
+  SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), 
+    .A1(CmdEnable16_0_a2_4), .D0(CmdEnable16), .C0(N_147), .B0(\MAin_c[1] ), 
+    .A0(C1Submitted), .DI0(C1Submitted_RNO), .CLK(PHI2_c), 
+    .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
+  SLICE_19 SLICE_19( .D1(CO0), .C1(\S[1] ), .B1(\IS[3] ), .A1(RASr2), 
+    .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), 
+    .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+  SLICE_20 SLICE_20( .D1(CmdEnable), .A1(ADSubmitted), .D0(CmdEnable17), 
+    .C0(C1Submitted), .B0(un1_CMDWR), .A0(CmdEnable), .DI0(CmdEnable_s), 
+    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
+  SLICE_21 SLICE_21( .D1(\Din_c[5] ), .C1(\Din_c[3] ), .B1(N_128), .D0(N_152), 
+    .C0(LEDEN), .B0(N_133), .A0(N_132), .DI0(N_21_i), .CE(XOR8MEG18), 
+    .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152));
+  SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(PHI2r3), .B1(PHI2r2), 
+    .A1(InitReady), .D0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), 
+    .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136));
+  SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), 
+    .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), 
+    .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), 
+    .F1(Cmdn8MEGEN_4_u_i_0));
+  SLICE_29 SLICE_29( .D1(N_160), .C1(N_155), .B1(nRRAS_5_u_i_0), .A1(\IS[0] ), 
+    .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), 
+    .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24));
+  SLICE_30 SLICE_30( .D1(\IS[0] ), .C1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), 
+    .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), 
+    .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] ));
+  SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), 
+    .D0(\IS[2] ), .C0(\IS[3] ), .B0(\IS[1] ), .A0(\IS[0] ), .DI0(N_61_i_i), 
+    .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
+  SLICE_32 SLICE_32( .D1(N_126), .C1(InitReady), .B1(UFMSDI_ens2_i_a2_4_2), 
+    .A1(N_51), .D0(InitReady3), .A0(InitReady), .DI0(N_461_0), .CLK(RCLK_c), 
+    .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
+  SLICE_33 SLICE_33( .D1(LEDEN), .C1(nCRAS_c), .A1(CBR), .D0(InitReady), 
+    .B0(CmdLEDEN), .A0(UFMSDO_c), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), 
+    .F0(N_70), .Q0(LEDEN), .F1(LED_c));
+  SLICE_39 SLICE_39( .D1(XOR8MEG), .B1(un1_Din_4), .D0(XOR8MEG), 
+    .B0(\Din_c[6] ), .A0(n8MEGEN), .DI0(RA11_2), .LSR(Ready_fast), 
+    .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171));
+  SLICE_41 SLICE_41( .D1(CO0), .C1(FWEr_fast), .B1(CASr2), .A1(\S[1] ), 
+    .D0(CBR), .C0(RCKEEN_8_u_1), .B0(Ready), .A0(RCKEEN_8_u_0_0), 
+    .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
+    .F1(RCKEEN_8_u_1), .Q1(PHI2r2));
+  SLICE_42 SLICE_42( .D1(\IS[1] ), .C1(\IS[2] ), .B1(\IS[0] ), .A1(RASr2), 
+    .D0(RASr), .C0(RASr3), .B0(RCKEEN), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), 
+    .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r));
+  SLICE_43 SLICE_43( .D1(Ready), .C1(\S_0_i_o2[1] ), .B1(RASr2), 
+    .A1(InitReady), .D0(Ready), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), 
+    .A0(InitReady), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), 
+    .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
+  SLICE_44 SLICE_44( .D1(Ready), .C1(N_165), .B1(Ready_0_sqmuxa_0_a3_2), 
+    .A1(InitReady), .B0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), 
+    .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), 
+    .F1(Ready_0_sqmuxa), .Q1(RASr));
+  SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ), 
+    .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), 
+    .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
+  SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(InitReady), .B1(N_129), 
+    .A1(UFMCLK_r_i_a2_2_2), .D0(N_139_i), .C0(UFMCLK_r_i_m4_xx_mm_1), 
+    .B0(nUFMCS15), .A0(UFMCLK_c), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), 
+    .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2));
+  SLICE_52 SLICE_52( .D1(PHI2r3), .C1(InitReady), .B1(PHI2r2), 
+    .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), 
+    .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), 
+    .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3));
+  SLICE_55 SLICE_55( .D0(\RowA[4] ), .B0(nRowColSel), .A0(\MAin_c[4] ), 
+    .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), 
+    .Q0(\WRD[4] ), .Q1(\WRD[5] ));
+  SLICE_56 SLICE_56( .D1(\Bank[5] ), .C1(\Bank[2] ), .B1(\Bank[6] ), 
+    .A1(\Bank[7] ), .D0(\FS[5] ), .C0(\FS[9] ), .A0(\FS[7] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), 
+    .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] ));
+  SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), 
+    .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), 
+    .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2));
+  SLICE_58 SLICE_58( .D1(N_51), .C1(\FS[8] ), .A1(InitReady), .D0(UFMSDO_c), 
+    .B0(Cmdn8MEGEN), .A0(InitReady), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), 
+    .F0(N_69), .Q0(n8MEGEN), .F1(N_151));
+  SLICE_59 SLICE_59( .D1(Ready), .C1(\S[1] ), .B1(N_155), .A1(N_160), 
+    .D0(N_41), .C0(nRCAS_0_sqmuxa_1), .B0(\S[1] ), .A0(g0_1), .DI0(N_37_i), 
+    .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41));
+  SLICE_60 SLICE_60( .D1(CASr3), .C1(CO0), .B1(FWEr_fast), .A1(CASr2), 
+    .D0(CBR), .C0(RCKEEN_8_u_0_a2_1_out), .B0(N_24), .A0(N_28_i_1), 
+    .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1));
+  SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(Ready), .B1(RASr2), .A1(RCKE_c), 
+    .D0(N_160), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(\IS[0] ), .DI0(N_24_i), 
+    .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
+  SLICE_62 SLICE_62( .D1(CBR_fast), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(RASr2), 
+    .D0(FWEr), .C0(m18_0_a2_1), .B0(nRCAS_0_sqmuxa_1), .A0(G_17_1), 
+    .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), 
+    .F1(nRCAS_0_sqmuxa_1));
+  SLICE_63 SLICE_63( .D1(CASr3), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(N_179), 
+    .C0(Ready), .B0(CO0), .A0(\S[1] ), .DI0(nRowColSel_0_0), 
+    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
+    .F1(N_179));
+  SLICE_64 SLICE_64( .D1(\FS[10] ), .C1(N_51), .B1(\FS[11] ), .A1(InitReady), 
+    .D0(nUFMCS_c), .C0(nUFMCS_s_0_N_5_i_N_2L1), .B0(nUFMCS15), .A0(N_139_i), 
+    .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), 
+    .F1(nUFMCS15));
+  nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), 
+    .A1(\S[1] ), .D0(\S[1] ), .C0(m18_0_a3_3), .B0(CO0), .A0(InitReady), 
+    .M0(Ready), .OFX0(m18_0_a2_1));
+  SLICE_66 SLICE_66( .C1(InitReady), .B1(CmdUFMCS), .A1(UFMCLK_r_i_a2_2_2), 
+    .D0(N_95_5), .C0(InitReady), .B0(\FS[16] ), .A0(N_95_3), .M1(\MAin_c[1] ), 
+    .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), 
+    .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] ));
+  SLICE_67 SLICE_67( .D1(\Din_c[5] ), .C1(XOR8MEG18), .B1(\Din_c[3] ), 
+    .A1(N_128), .D0(\MAin_c[1] ), .C0(\MAin_c[0] ), .B0(CmdEnable), .A0(N_147), 
+    .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), 
+    .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), .Q1(\RowA[5] ));
+  SLICE_68 SLICE_68( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), 
+    .D0(N_136), .C0(N_137_8), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), 
+    .F1(un1_FS_14_i_a2_0_1));
+  SLICE_69 SLICE_69( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), 
+    .D0(N_137_8), .C0(un1_FS_13_i_a2_1), .B0(N_136), .A0(N_137_6), .F0(N_33), 
+    .F1(un1_FS_13_i_a2_1));
+  SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), 
+    .A1(\Bank[1] ), .C0(\MAin_c[1] ), .B0(N_147), .M1(\Din_c[1] ), 
+    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), 
+    .Q1(\Bank[1] ));
+  SLICE_71 SLICE_71( .D1(\MAin_c[5] ), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), 
+    .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(\Bank[3] ), .B0(\Bank[4] ), 
+    .A0(C1WR_0_a2_0_3), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), 
+    .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] ));
+  SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), 
+    .D0(\FS[1] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[4] ), .M1(\MAin_c[3] ), 
+    .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), 
+    .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] ));
+  SLICE_73 SLICE_73( .D1(\S[1] ), .C1(RASr2), .B1(CO0), .A1(InitReady), 
+    .B0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), 
+    .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), 
+    .F1(N_155), .Q1(CmdUFMCS));
+  SLICE_74 SLICE_74( .D1(\FS[14] ), .B1(\FS[11] ), .D0(\FS[16] ), .C0(N_95_3), 
+    .B0(\FS[10] ), .A0(N_95_5), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
+    .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3));
+  SLICE_75 SLICE_75( .C1(\Din_c[4] ), .B1(\Din_c[7] ), .A1(\Din_c[6] ), 
+    .D0(\Din_c[1] ), .C0(N_128), .A0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), 
+    .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2));
+  SLICE_76 SLICE_76( .D1(\Din_c[5] ), .B1(\Din_c[0] ), .D0(\MAin_c[0] ), 
+    .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), 
+    .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), 
+    .F1(CmdEnable16_4), .Q1(\Bank[5] ));
+  SLICE_77 SLICE_77( .C1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), 
+    .C0(CmdEnable16_1), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(\Din_c[7] ), 
+    .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), 
+    .F1(CmdEnable16_1), .Q1(\Bank[7] ));
+  SLICE_78 SLICE_78( .C1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), 
+    .C0(\Din_c[6] ), .B0(N_43), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), 
+    .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast));
+  SLICE_79 SLICE_79( .D1(CASr3), .C1(Ready), .B1(CASr2), .D0(CO0), 
+    .C0(m6_0_a2_2), .B0(CBR), .A0(\S[1] ), .M1(\Din_c[1] ), .M0(\Din_c[0] ), 
+    .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] ));
+  SLICE_80 SLICE_80( .C1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CBR_fast), 
+    .B0(g4_0_0_0), .A0(CO0), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), 
+    .Q1(\RowA[9] ));
+  SLICE_81 SLICE_81( .D1(\FS[14] ), .C1(\FS[17] ), .B1(\FS[15] ), 
+    .A1(\FS[13] ), .D0(\FS[12] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[13] ), 
+    .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), 
+    .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast));
+  SLICE_82 SLICE_82( .D1(\Din_c[5] ), .C1(CmdLEDEN), .B1(N_128), 
+    .A1(\Din_c[3] ), .D0(\Din_c[5] ), .C0(XOR8MEG18), .B0(N_128), 
+    .A0(\Din_c[3] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), 
+    .Q0(CASr3), .F1(N_132));
+  SLICE_83 SLICE_83( .C1(\IS[2] ), .B1(\IS[3] ), .A1(\IS[1] ), .D0(\IS[0] ), 
+    .C0(\IS[2] ), .A0(\IS[1] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), 
+    .Q1(\RBA_c[1] ));
+  SLICE_84 SLICE_84( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[6] ), 
+    .D0(\FS[7] ), .C0(\FS[1] ), .B0(\FS[10] ), .A0(\FS[6] ), .F0(N_137_6), 
+    .F1(UFMSDI_ens2_i_a2_4_2));
+  SLICE_85 SLICE_85( .D1(\Din_c[1] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), 
+    .A1(\Din_c[0] ), .D0(\Din_c[6] ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), 
+    .A0(\Din_c[5] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), 
+    .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] ));
+  SLICE_86 SLICE_86( .C1(\MAin_c[9] ), .A1(nRowColSel), .C0(\MAin_c[9] ), 
+    .B0(\RowA[9] ), .A0(nRowColSel), .F0(\RA_c[9] ), .F1(RDQML_c));
+  SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .C1(CmdUFMSDI), .B1(N_151), 
+    .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), 
+    .F1(UFMSDI_r_xx_mm_1));
+  SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[2] ), .A1(\MAin_c[3] ), 
+    .D0(nCCAS_c), .C0(nFWE_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), 
+    .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), 
+    .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] ));
+  SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), 
+    .C0(\MAin_c[8] ), .B0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
+  SLICE_90 SLICE_90( .C1(N_147), .B1(\MAin_c[0] ), .A1(\MAin_c[1] ), 
+    .D0(\RowA[0] ), .B0(\MAin_c[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), 
+    .F1(un1_CMDWR));
+  SLICE_91 SLICE_91( .D1(nRowColSel), .C1(\RowA[7] ), .B1(\MAin_c[7] ), 
+    .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), 
+    .F1(\RA_c[7] ));
+  SLICE_92 SLICE_92( .D1(nRowColSel), .C1(\MAin_c[6] ), .A1(\RowA[6] ), 
+    .D0(nRowColSel), .C0(\RowA[2] ), .B0(\MAin_c[2] ), .F0(\RA_c[2] ), 
+    .F1(\RA_c[6] ));
+  SLICE_93 SLICE_93( .D1(\RowA[5] ), .B1(nRowColSel), .A1(\MAin_c[5] ), 
+    .D0(\RowA[3] ), .B0(nRowColSel), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
+    .F1(\RA_c[5] ));
+  SLICE_94 SLICE_94( .D1(Ready), .C1(N_155), .D0(Ready), .C0(\S[1] ), 
+    .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), 
+    .Q0(\RA_c[10] ), .F1(N_159_i));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), 
+    .RD0(RD[0]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
+  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
+  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
+  UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
+  UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
+  nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
+  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
+  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
+  nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
+  nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
+  nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
+  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
+  nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ), 
+    .RD7(RD[7]));
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ), 
+    .RD6(RD[6]));
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ), 
+    .RD5(RD[5]));
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ), 
+    .RD4(RD[4]));
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ), 
+    .RD3(RD[3]));
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ), 
+    .RD2(RD[2]));
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ), 
+    .RD1(RD[1]));
+  RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
+  RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
+  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
+  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
+  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
+  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
+  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
+  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
+  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
+  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
+  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
+  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
+  RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
+  RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
+  LED LED_I( .PADDO(LED_c), .LED(LED));
+  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
+  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
+  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
+  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
+  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
+  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
+  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
+  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
+  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
+  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
+  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
+  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
+  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
+  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
+  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
+  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
+  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
+  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
+  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
+  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
+  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
+  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
+  VHI VHI_INST( .Z(VCCI));
+  PUR PUR_INST( .PUR(VCCI));
+  GSR GSR_INST( .GSR(VCCI));
+  VLO VLO_INST( .Z(GNDI_TSALL));
+  TSALL TSALL_INST( .TSALL(GNDI_TSALL));
+endmodule
+
+module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 , 
+         A1_dly, CLK_dly, A0_dly;
+
+  vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI), 
+    .S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+  endspecify
+
+endmodule
+
+module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module vcc ( output PWR1 );
+
+  VHI INST1( .Z(PWR1));
+endmodule
+
+module gnd ( output PWR0 );
+
+  VLO INST1( .Z(PWR0));
+endmodule
+
+module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h300a;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
+  wire   VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(), 
+    .CO1());
+
+  specify
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, 
+    CO1 );
+
+  CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
+    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
+  defparam inst1.INIT0 = 16'h300a;
+  defparam inst1.INIT1 = 16'h5002;
+  defparam inst1.INJECT1_0 = "NO";
+  defparam inst1.INJECT1_1 = "NO";
+endmodule
+
+module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
+  wire   VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 , 
+         A1_dly, CLK_dly, A0_dly, FCI_dly;
+
+  vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), 
+    .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), 
+    .S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(), 
+    .CO1(FCO));
+
+  specify
+    (A1 => FCO) = (0:0:0,0:0:0);
+    (A0 => FCO) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    (FCI => FCO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
+    $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
+    $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
+  endspecify
+
+endmodule
+
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
+
+  lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40002 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4544) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module inverter ( input I, output Z );
+
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40004 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40005 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40006 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_20 ( input D1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
+  wire   GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, 
+         CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40008 SLICE_20_K1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), 
+    .Z(\SLICE_20/SLICE_20_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\SLICE_20/CmdEnable_s/GATE_H0 ));
+  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), 
+    .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40009 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEA22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module SLICE_21 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40010 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40011 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
+
+  lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+  endspecify
+
+endmodule
+
+module lut40012 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40013 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40014 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_30 ( input D1, C1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40018 \IS_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5AF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40020 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly;
+
+  lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 InitReady_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0B0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40023 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40024 LEDEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCC55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_39 ( input D1, B1, D0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40025 XOR8MEG_3_u_0_a3_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40026 RA11_2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40025 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBB44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40027 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40028 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h75A5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40029 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40030 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDCD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40031 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40032 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h03AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40032 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40033 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40033 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40034 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_50 ( input D1, C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40035 nRowColSel_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40036 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40035 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40036 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40037 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40038 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40037 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hABFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40038 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
+
+  lut40039 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40040 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40039 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40040 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40041 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40041 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40042 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40043 UFMSDI_ens2_i_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40042 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40044 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40045 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40044 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40045 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_58 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40046 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40047 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40046 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40047 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h88DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40048 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40049 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0050 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40048 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0FDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40049 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0F04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0050 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40051 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40052 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0050 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40051 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFC7C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3323) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40053 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40054 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0050 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40053 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40054 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40055 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40056 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0050 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40055 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40056 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCDEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40057 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40058 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40058 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF60) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40059 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0050 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40059 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , 
+         \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
+
+  lut40061 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
+  lut40062 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
+  selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( 
+    .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), 
+    .D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40061 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40062 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40063 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40064 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40063 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40064 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40065 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40066 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0067 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40065 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40066 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0067 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40068 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40069 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40068 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40070 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40071 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40070 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40071 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_70 ( input D1, C1, B1, A1, C0, B0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40072 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40073 C1WR_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40072 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40073 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
+
+  lut40074 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40075 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40074 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40075 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40076 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40077 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40076 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40077 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
+
+  lut40078 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40078 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_74 ( input D1, B1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+
+  lut40079 InitReady3_0_a2_3( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40080 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+  endspecify
+
+endmodule
+
+module lut40079 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40080 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_75 ( input C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40081 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40082 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40081 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40082 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40083 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40084 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40083 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40084 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_77 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
+
+  lut40085 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40086 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40085 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40086 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_78 ( input C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
+    Q1 );
+  wire   GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40087 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40088 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40087 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40088 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40089 nRWE_RNO_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40090 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40089 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40090 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40091 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40092 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0067 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40091 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40092 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0805) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40093 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40094 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40093 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40094 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, M0_dly, CLK_dly;
+
+  lut40095 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40096 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
+    .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40095 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0E0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40096 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h1030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_83 ( input C1, B1, A1, D0, C0, A0, M1, M0, LSR, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40097 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40098 Ready_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40097 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40098 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+  lut40099 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40100 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40099 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40100 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
+
+  lut40101 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40102 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+  endspecify
+
+endmodule
+
+module lut40101 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40102 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_86 ( input C1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40103 RDQML( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40104 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40103 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40104 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_87 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40105 UFMSDI_RNO_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40106 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40105 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h00FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40106 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_88 ( input C1, B1, A1, D0, C0, M1, M0, LSR, CLK, output F0, Q0, 
+    F1, Q1 );
+  wire   GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
+
+  lut40107 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40108 nCCAS_pad_RNI01SJ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
+  vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
+    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+  endspecify
+
+endmodule
+
+module lut40107 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40108 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_89 ( input D1, C1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40109 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40110 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40109 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40110 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_90 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40111 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40112 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40111 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40112 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_91 ( input D1, C1, B1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40113 \un9_RA[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40114 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40113 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40114 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40115 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40113 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40115 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_93 ( input D1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40041 \un9_RA[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_94 ( input D1, C1, D0, C0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly;
+
+  lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40117 RCKEEN_8_u_0_a2_1_s( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0067 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40116 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40117 ( input A, B, C, D, output Z );
+
+  ROM16X1 #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
+
+  mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
+
+  specify
+    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD0) = (0:0:0,0:0:0);
+    (RD0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD0, 0:0:0);
+    $width (negedge RD0, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf ( input I, T, output Z, PAD, input PADI );
+
+  IB INST1( .I(PADI), .O(Z));
+  OBW INST2( .I(I), .T(T), .O(PAD));
+endmodule
+
+module Dout_0_ ( input PADDO, output Dout0 );
+
+  mjiobuf0118 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+
+  specify
+    (PADDO => Dout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0118 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module PHI2 ( output PADDI, input PHI2 );
+
+  mjiobuf0119 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+
+  specify
+    (PHI2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge PHI2, 0:0:0);
+    $width (negedge PHI2, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0119 ( output Z, input PAD );
+
+  IBPD INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDO ( output PADDI, input UFMSDO );
+
+  mjiobuf0120 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
+
+  specify
+    (UFMSDO => PADDI) = (0:0:0,0:0:0);
+    $width (posedge UFMSDO, 0:0:0);
+    $width (negedge UFMSDO, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0120 ( output Z, input PAD );
+
+  IB INST1( .I(PAD), .O(Z));
+endmodule
+
+module UFMSDI ( input PADDO, output UFMSDI );
+
+  mjiobuf0121 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
+
+  specify
+    (PADDO => UFMSDI) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0121 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module UFMCLK ( input PADDO, output UFMCLK );
+
+  mjiobuf0121 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
+
+  specify
+    (PADDO => UFMCLK) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nUFMCS ( input PADDO, output nUFMCS );
+
+  mjiobuf0121 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
+
+  specify
+    (PADDO => nUFMCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQML ( input PADDO, output RDQML );
+
+  mjiobuf0121 RDQML_pad( .I(PADDO), .PAD(RDQML));
+
+  specify
+    (PADDO => RDQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RDQMH ( input PADDO, output RDQMH );
+
+  mjiobuf0121 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+
+  specify
+    (PADDO => RDQMH) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRCAS ( input PADDO, output nRCAS );
+
+  mjiobuf0121 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
+
+  specify
+    (PADDO => nRCAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRRAS ( input PADDO, output nRRAS );
+
+  mjiobuf0121 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
+
+  specify
+    (PADDO => nRRAS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module nRWE ( input PADDO, output nRWE );
+
+  mjiobuf0121 nRWE_pad( .I(PADDO), .PAD(nRWE));
+
+  specify
+    (PADDO => nRWE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCKE ( input PADDO, output RCKE );
+
+  mjiobuf0121 RCKE_pad( .I(PADDO), .PAD(RCKE));
+
+  specify
+    (PADDO => RCKE) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RCLK ( output PADDI, input RCLK );
+
+  mjiobuf0120 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+
+  specify
+    (RCLK => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RCLK, 0:0:0);
+    $width (negedge RCLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module nRCS ( input PADDO, output nRCS );
+
+  mjiobuf0121 nRCS_pad( .I(PADDO), .PAD(nRCS));
+
+  specify
+    (PADDO => nRCS) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
+
+  mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
+
+  specify
+    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD7) = (0:0:0,0:0:0);
+    (RD7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD7, 0:0:0);
+    $width (negedge RD7, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
+
+  mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
+
+  specify
+    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD6) = (0:0:0,0:0:0);
+    (RD6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD6, 0:0:0);
+    $width (negedge RD6, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
+
+  mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
+
+  specify
+    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD5) = (0:0:0,0:0:0);
+    (RD5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD5, 0:0:0);
+    $width (negedge RD5, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
+
+  mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
+
+  specify
+    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD4) = (0:0:0,0:0:0);
+    (RD4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD4, 0:0:0);
+    $width (negedge RD4, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
+
+  mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
+
+  specify
+    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD3) = (0:0:0,0:0:0);
+    (RD3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD3, 0:0:0);
+    $width (negedge RD3, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
+
+  mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
+
+  specify
+    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD2) = (0:0:0,0:0:0);
+    (RD2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD2, 0:0:0);
+    $width (negedge RD2, 0:0:0);
+  endspecify
+
+endmodule
+
+module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
+
+  mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
+
+  specify
+    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
+    (PADDO => RD1) = (0:0:0,0:0:0);
+    (RD1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge RD1, 0:0:0);
+    $width (negedge RD1, 0:0:0);
+  endspecify
+
+endmodule
+
+module RA_11_ ( input PADDO, output RA11 );
+
+  mjiobuf0121 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
+
+  specify
+    (PADDO => RA11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_10_ ( input PADDO, output RA10 );
+
+  mjiobuf0121 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
+
+  specify
+    (PADDO => RA10) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_9_ ( input PADDO, output RA9 );
+
+  mjiobuf0121 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+
+  specify
+    (PADDO => RA9) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_8_ ( input PADDO, output RA8 );
+
+  mjiobuf0121 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+
+  specify
+    (PADDO => RA8) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_7_ ( input PADDO, output RA7 );
+
+  mjiobuf0121 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+
+  specify
+    (PADDO => RA7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_6_ ( input PADDO, output RA6 );
+
+  mjiobuf0121 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+
+  specify
+    (PADDO => RA6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_5_ ( input PADDO, output RA5 );
+
+  mjiobuf0121 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+
+  specify
+    (PADDO => RA5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_4_ ( input PADDO, output RA4 );
+
+  mjiobuf0121 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+
+  specify
+    (PADDO => RA4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_3_ ( input PADDO, output RA3 );
+
+  mjiobuf0121 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+
+  specify
+    (PADDO => RA3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_2_ ( input PADDO, output RA2 );
+
+  mjiobuf0121 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+
+  specify
+    (PADDO => RA2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_1_ ( input PADDO, output RA1 );
+
+  mjiobuf0121 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+
+  specify
+    (PADDO => RA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RA_0_ ( input PADDO, output RA0 );
+
+  mjiobuf0121 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+
+  specify
+    (PADDO => RA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_1_ ( input PADDO, output RBA1 );
+
+  mjiobuf0121 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
+
+  specify
+    (PADDO => RBA1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RBA_0_ ( input PADDO, output RBA0 );
+
+  mjiobuf0121 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
+
+  specify
+    (PADDO => RBA0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module LED ( input PADDO, output LED );
+
+  mjiobuf0122 LED_pad( .I(PADDO), .PAD(LED));
+
+  specify
+    (PADDO => LED) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0122 ( input I, output PAD );
+
+  OB INST5( .I(I), .O(PAD));
+endmodule
+
+module nFWE ( output PADDI, input nFWE );
+
+  mjiobuf0120 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+
+  specify
+    (nFWE => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nFWE, 0:0:0);
+    $width (negedge nFWE, 0:0:0);
+  endspecify
+
+endmodule
+
+module nCRAS ( output PADDI, input nCRAS );
+
+  mjiobuf0123 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+
+  specify
+    (nCRAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCRAS, 0:0:0);
+    $width (negedge nCRAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module mjiobuf0123 ( output Z, input PAD );
+
+  IBPU INST1( .I(PAD), .O(Z));
+endmodule
+
+module nCCAS ( output PADDI, input nCCAS );
+
+  mjiobuf0123 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+
+  specify
+    (nCCAS => PADDI) = (0:0:0,0:0:0);
+    $width (posedge nCCAS, 0:0:0);
+    $width (negedge nCCAS, 0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_7_ ( input PADDO, output Dout7 );
+
+  mjiobuf0118 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+
+  specify
+    (PADDO => Dout7) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_6_ ( input PADDO, output Dout6 );
+
+  mjiobuf0118 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+
+  specify
+    (PADDO => Dout6) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_5_ ( input PADDO, output Dout5 );
+
+  mjiobuf0118 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+
+  specify
+    (PADDO => Dout5) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_4_ ( input PADDO, output Dout4 );
+
+  mjiobuf0118 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+
+  specify
+    (PADDO => Dout4) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_3_ ( input PADDO, output Dout3 );
+
+  mjiobuf0118 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+
+  specify
+    (PADDO => Dout3) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_2_ ( input PADDO, output Dout2 );
+
+  mjiobuf0118 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+
+  specify
+    (PADDO => Dout2) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Dout_1_ ( input PADDO, output Dout1 );
+
+  mjiobuf0118 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+
+  specify
+    (PADDO => Dout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module Din_7_ ( output PADDI, input Din7 );
+
+  mjiobuf0120 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+
+  specify
+    (Din7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din7, 0:0:0);
+    $width (negedge Din7, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_6_ ( output PADDI, input Din6 );
+
+  mjiobuf0120 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+
+  specify
+    (Din6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din6, 0:0:0);
+    $width (negedge Din6, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_5_ ( output PADDI, input Din5 );
+
+  mjiobuf0120 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+
+  specify
+    (Din5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din5, 0:0:0);
+    $width (negedge Din5, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_4_ ( output PADDI, input Din4 );
+
+  mjiobuf0120 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+
+  specify
+    (Din4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din4, 0:0:0);
+    $width (negedge Din4, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_3_ ( output PADDI, input Din3 );
+
+  mjiobuf0120 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+
+  specify
+    (Din3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din3, 0:0:0);
+    $width (negedge Din3, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_2_ ( output PADDI, input Din2 );
+
+  mjiobuf0120 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+
+  specify
+    (Din2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din2, 0:0:0);
+    $width (negedge Din2, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_1_ ( output PADDI, input Din1 );
+
+  mjiobuf0120 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+
+  specify
+    (Din1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din1, 0:0:0);
+    $width (negedge Din1, 0:0:0);
+  endspecify
+
+endmodule
+
+module Din_0_ ( output PADDI, input Din0 );
+
+  mjiobuf0120 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+
+  specify
+    (Din0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge Din0, 0:0:0);
+    $width (negedge Din0, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_1_ ( output PADDI, input CROW1 );
+
+  mjiobuf0120 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+
+  specify
+    (CROW1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW1, 0:0:0);
+    $width (negedge CROW1, 0:0:0);
+  endspecify
+
+endmodule
+
+module CROW_0_ ( output PADDI, input CROW0 );
+
+  mjiobuf0120 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+
+  specify
+    (CROW0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge CROW0, 0:0:0);
+    $width (negedge CROW0, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_9_ ( output PADDI, input MAin9 );
+
+  mjiobuf0120 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+
+  specify
+    (MAin9 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin9, 0:0:0);
+    $width (negedge MAin9, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_8_ ( output PADDI, input MAin8 );
+
+  mjiobuf0120 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+
+  specify
+    (MAin8 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin8, 0:0:0);
+    $width (negedge MAin8, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_7_ ( output PADDI, input MAin7 );
+
+  mjiobuf0120 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+
+  specify
+    (MAin7 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin7, 0:0:0);
+    $width (negedge MAin7, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_6_ ( output PADDI, input MAin6 );
+
+  mjiobuf0120 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+
+  specify
+    (MAin6 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin6, 0:0:0);
+    $width (negedge MAin6, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_5_ ( output PADDI, input MAin5 );
+
+  mjiobuf0120 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+
+  specify
+    (MAin5 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin5, 0:0:0);
+    $width (negedge MAin5, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_4_ ( output PADDI, input MAin4 );
+
+  mjiobuf0120 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+
+  specify
+    (MAin4 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin4, 0:0:0);
+    $width (negedge MAin4, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_3_ ( output PADDI, input MAin3 );
+
+  mjiobuf0120 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+
+  specify
+    (MAin3 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin3, 0:0:0);
+    $width (negedge MAin3, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_2_ ( output PADDI, input MAin2 );
+
+  mjiobuf0120 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+
+  specify
+    (MAin2 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin2, 0:0:0);
+    $width (negedge MAin2, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_1_ ( output PADDI, input MAin1 );
+
+  mjiobuf0120 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+
+  specify
+    (MAin1 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin1, 0:0:0);
+    $width (negedge MAin1, 0:0:0);
+  endspecify
+
+endmodule
+
+module MAin_0_ ( output PADDI, input MAin0 );
+
+  mjiobuf0120 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+
+  specify
+    (MAin0 => PADDI) = (0:0:0,0:0:0);
+    $width (posedge MAin0, 0:0:0);
+    $width (negedge MAin0, 0:0:0);
+  endspecify
+
+endmodule
diff --git a/CPLD/LCMXO640C/impl1/automake.log b/CPLD/LCMXO640C/impl1/automake.log
index d170583..8d00265 100644
--- a/CPLD/LCMXO640C/impl1/automake.log
+++ b/CPLD/LCMXO640C/impl1/automake.log
@@ -1,2312 +1,490 @@
 
-synpwrap -msg -prj "RAM2GS_LCMXO640C_impl1_synplify.tcl" -log "RAM2GS_LCMXO640C_impl1.srf"
-Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved.
-Lattice Diamond Version 3.12.1.454
-    
-
-==contents of RAM2GS_LCMXO640C_impl1.srf
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:37 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:39 2023
-
-###########################################################]
-# Wed Aug 16 04:50:39 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:41 2023
-
-###########################################################]
-# Wed Aug 16 04:50:41 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:02s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:02s		    -2.99ns		 127 /        92
-   9		0h:00m:02s		    -3.09ns		 127 /        92
-  10		0h:00m:02s		    -3.19ns		 127 /        92
-  11		0h:00m:02s		    -3.19ns		 127 /        92
-  12		0h:00m:02s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:45 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo640c-3
-
-Register bits: 92 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Wed Aug 16 04:50:45 2023
-
-###########################################################]
-
-
-Synthesis exit by 0.
-
-edif2ngd  -l "MachXO" -d LCMXO640C -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1" -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C"   "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi" "RAM2GS_LCMXO640C_impl1.ngo"   
-edif2ngd:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Writing the design to RAM2GS_LCMXO640C_impl1.ngo...
-
-Total CPU Time: 0 secs  
-Total REAL Time: 0 secs  
-Peak Memory Usage: 11 MB
-
-
-ngdbuild  -a "MachXO" -d LCMXO640C  -p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data"  -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1" -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C"  "RAM2GS_LCMXO640C_impl1.ngo" "RAM2GS_LCMXO640C_impl1.ngd"  	
-ngdbuild:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Reading 'RAM2GS_LCMXO640C_impl1.ngo' ...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-
-Design Results:
-    300 blocks expanded
-Complete the first expansion.
-Writing 'RAM2GS_LCMXO640C_impl1.ngd' ...
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 18 MB
-
-
-map -a "MachXO" -p LCMXO640C -t TQFP100 -s 3 -oc Commercial  -ioreg b "RAM2GS_LCMXO640C_impl1.ngd" -o "RAM2GS_LCMXO640C_impl1_map.ncd" -pr "RAM2GS_LCMXO640C_impl1.prf" -mp "RAM2GS_LCMXO640C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf"  -c 0           
-map:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-   Process the file: RAM2GS_LCMXO640C_impl1.ngd
-   Picdevice="LCMXO640C"
-
-   Pictype="TQFP100"
-
-   Picspeed=3
-
-   Remove unused logic
-
-   Do not produce over sized NCDs.
-
-Part used: LCMXO640CTQFP100, Performance used: 3.
-
-Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Running general design DRC...
-
-Removing unused logic...
-
-Optimizing...
-
-
-
-
-Design Summary:
-   Number of PFU registers:    92 out of   640 (14%)
-   Number of SLICEs:        69 out of   320 (22%)
-      SLICEs as Logic/ROM:     69 out of   320 (22%)
-      SLICEs as RAM:            0 out of   192 (0%)
-      SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        137 out of   640 (21%)
-      Number used as logic LUTs:        119
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 74 (91%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  5
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net N_31: 1 loads, 1 LSLICEs
-     Net N_33: 1 loads, 1 LSLICEs
-     Net N_159_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
-   Number of LSRs:  4
-     Net RA10s_i: 1 loads, 1 LSLICEs
-     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
-     Net RASr2: 2 loads, 2 LSLICEs
-     Net Ready_fast: 7 loads, 7 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net InitReady: 16 loads
-     Net Ready: 16 loads
-     Net S[1]: 13 loads
-     Net CO0: 12 loads
-     Net nRowColSel: 12 loads
-     Net RASr2: 11 loads
-     Net Din_c[5]: 10 loads
-     Net Din_c[3]: 9 loads
-     Net IS[0]: 9 loads
-     Net MAin_c[1]: 8 loads
- 
-
-   Number of warnings:  0
-   Number of errors:    0
-
-
-
-Total CPU Time: 0 secs  
-Total REAL Time: 0 secs  
-Peak Memory Usage: 30 MB
-
-Dumping design to file RAM2GS_LCMXO640C_impl1_map.ncd.
-
-ncd2eqn "RAM2GS_LCMXO640C_impl1_map.ncd"
-ncd2eqn:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Start loading RAM2GS_LCMXO640C_impl1_map.ncd.
-
-Loading design for application ncd2eqn from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application ncd2eqn from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Finish loading RAM2GS_LCMXO640C_impl1_map.ncd.
-ncd2eqn runs successfully.
-
-trce -f "RAM2GS_LCMXO640C_impl1.mt" -o "RAM2GS_LCMXO640C_impl1.tw1" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.prf"
-trce:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:47 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 32 MB
-
-
-ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO640C_impl1_mapvo.vo" -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format.
-Writing Verilog netlist to file RAM2GS_LCMXO640C_impl1_mapvo.vo
-Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvo.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 30 MB
-
-ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO640C_impl1_mapvho.vho" -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format.
-Writing VHDL netlist to file RAM2GS_LCMXO640C_impl1_mapvho.vho
-Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvho.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 30 MB
-
-mpartrce -p "RAM2GS_LCMXO640C_impl1.p2t" -f "RAM2GS_LCMXO640C_impl1.p3t" -tf "RAM2GS_LCMXO640C_impl1.pt" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.ncd"
-
----- MParTrce Tool ----
-Removing old design directory at request of -rem command line option to this program.
-Running par. Please wait . . .
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Wed Aug 16 04:50:48 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)      67/159          42% used
-                     67/74           90% bonded
-   SLICE             69/320          21% used
-
-
-
-Number of Signals: 251
-Number of Connections: 633
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 32)
-    PHI2_c (driver: PHI2, clk load #: 14)
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-.........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-.............
-Placer score = 956294.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  953137
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 1 out of 160 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 4 (50%)
-  SECONDARY: 1 out of 4 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 out of 159 (42.1%) PIO sites used.
-   67 out of 74 (90.5%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
-| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-| 2        | 13 / 14 ( 92%) | -          | -          | -          |
-| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-0 connections routed; 633 unrouted.
-Starting router resource preassignment
-    
-    
-
-    
-
-Completed router resource preassignment. Real time: 4 secs 
-
-Start NBR router at 04:50:52 08/16/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 04:50:52 08/16/23
-
-Start NBR section for initial routing at 04:50:52 08/16/23
-Level 1, iteration 1
-1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.325ns/0.000ns; real time: 4 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.532ns/0.000ns; real time: 4 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.449ns/0.000ns; real time: 4 secs 
-Level 4, iteration 1
-8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:52 08/16/23
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 2
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:52 08/16/23
-
-Start NBR section for re-routing at 04:50:52 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 7.336ns/0.000ns; real time: 4 secs 
-
-Start NBR section for post-routing at 04:50:52 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 7.336ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-    
-
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 7.336
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Exiting par with exit code 0
-Exiting mpartrce with exit code 0
-
-trce -f "RAM2GS_LCMXO640C_impl1.pt" -o "RAM2GS_LCMXO640C_impl1.twr" "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf"
-trce:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Wed Aug 16 04:50:53 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 32 MB
-
-
-iotiming  "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf"
-I/O Timing Report:
-:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application iotiming from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 3
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 4
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: 5
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Running Performance Grade: M
-Computing Setup Time ...
-Computing Max Clock to Output Delay ...
-Computing Hold Time ...
-Computing Min Clock to Output Delay ...
-Done.
-
 ibisgen "RAM2GS_LCMXO640C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
-IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
-
-Wed Aug 16 04:50:53 2023
-
-Comp: CROW[0]
- Site: 32
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: CROW[1]
- Site: 34
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[0]
- Site: 21
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[1]
- Site: 15
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[2]
- Site: 14
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[3]
- Site: 16
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[4]
- Site: 18
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[5]
- Site: 17
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[6]
- Site: 20
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Din[7]
- Site: 19
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: Dout[0]
- Site: 1
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[1]
- Site: 7
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[2]
- Site: 8
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[3]
- Site: 6
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[4]
- Site: 4
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[5]
- Site: 5
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[6]
- Site: 2
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: Dout[7]
- Site: 3
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=FAST 
------------------------
-Comp: LED
- Site: 57
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=14mA 
- SLEW=SLOW 
------------------------
-Comp: MAin[0]
- Site: 23
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[1]
- Site: 38
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[2]
- Site: 37
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[3]
- Site: 47
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[4]
- Site: 46
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[5]
- Site: 45
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[6]
- Site: 49
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[7]
- Site: 44
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[8]
- Site: 50
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: MAin[9]
- Site: 51
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: PHI2
- Site: 39
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=DOWN 
------------------------
-Comp: RA[0]
- Site: 98
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[10]
- Site: 87
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[11]
- Site: 79
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[1]
- Site: 89
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[2]
- Site: 94
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[3]
- Site: 97
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[4]
- Site: 99
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[5]
- Site: 95
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[6]
- Site: 91
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[7]
- Site: 100
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[8]
- Site: 96
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[9]
- Site: 85
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[0]
- Site: 63
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[1]
- Site: 83
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCKE
- Site: 82
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCLK
- Site: 86
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: RDQMH
- Site: 76
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RDQML
- Site: 61
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RD[0]
- Site: 64
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[1]
- Site: 65
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[2]
- Site: 66
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[3]
- Site: 67
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[4]
- Site: 68
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[5]
- Site: 69
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[6]
- Site: 70
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[7]
- Site: 71
- Type: BIDI
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: UFMCLK
- Site: 58
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDI
- Site: 56
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDO
- Site: 55
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nCCAS
- Site: 27
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=UP 
------------------------
-Comp: nCRAS
- Site: 43
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=UP 
------------------------
-Comp: nFWE
- Site: 22
- Type: IN
- IO_TYPE=LVCMOS33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nRCAS
- Site: 78
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRCS
- Site: 77
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRRAS
- Site: 73
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRWE
- Site: 72
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nUFMCS
- Site: 53
- Type: OUT
- IO_TYPE=LVCMOS33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Created design models.
-
-
-Generating: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\IBIS\RAM2GS_LCMXO640C_im~.ibs
-
-
-    
-
-ldbanno "RAM2GS_LCMXO640C_impl1.ncd" -n Verilog  -o "RAM2GS_LCMXO640C_impl1_vo.vo"         -w -neg
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1 design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO640C_impl1.ncd into .ldb format.
-Loading preferences from ram2gs_lcmxo640c_impl1.prf.
-Writing Verilog netlist to file RAM2GS_LCMXO640C_impl1_vo.vo
-Writing SDF timing to file RAM2GS_LCMXO640C_impl1_vo.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 32 MB
-
-ldbanno "RAM2GS_LCMXO640C_impl1.ncd" -n VHDL -o "RAM2GS_LCMXO640C_impl1_vho.vho"         -w -neg 
-ldbanno: version Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1 design file.
-
-
-Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Converting design RAM2GS_LCMXO640C_impl1.ncd into .ldb format.
-Loading preferences from ram2gs_lcmxo640c_impl1.prf.
-Writing VHDL netlist to file RAM2GS_LCMXO640C_impl1_vho.vho
-Writing SDF timing to file RAM2GS_LCMXO640C_impl1_vho.sdf
-    
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 32 MB
-
-tmcheck -par "RAM2GS_LCMXO640C_impl1.par" 
-
-bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf"
-
-
-BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-
-Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
-
-Preference Summary:
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 46 MB
-
-ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed"  -comment "RAM2GS_LCMXO640C_impl1.alt" 
-Lattice Diamond Deployment Tool 3.12 Command Line
-
-Loading Programmer Device Database...
-
-Generating JED.....
-Device Name: LCMXO640C-XXT100
-Reading Input File: RAM2GS_LCMXO640C_impl1.bit
-Output File: RAM2GS_LCMXO640C_impl1.jed
-Comment file RAM2GS_LCMXO640C_impl1.alt.
-Generating JEDEC.....
-File RAM2GS_LCMXO640C_impl1.jed generated successfully.
-Lattice Diamond Deployment Tool has exited successfully.
-
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
+
+Sun Aug 20 05:55:52 2023
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=FAST 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=14mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=DOWN 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=UP 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=UP 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVCMOS33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVCMOS33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\IBIS\RAM2GS_LCMXO640C_im~.ibs
+
+
+    
diff --git a/CPLD/LCMXO640C/impl1/dm/layer0.xdm b/CPLD/LCMXO640C/impl1/dm/layer0.xdm
index 80ddd36..36c7233 100644
--- a/CPLD/LCMXO640C/impl1/dm/layer0.xdm
+++ b/CPLD/LCMXO640C/impl1/dm/layer0.xdm
@@ -1,32 +1,32 @@
-%%% protect protected_file
-@EG
--
-]17p0Osk0CksRsPC#MHF=3"4j
-">
-!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
-S
-SS1S
-SF<1kCsOR"b=BD:\#\OO8lHNF\M8d.34\M#$b#LNCH\DLD\PFEo\$sbCl#F83RP"N.=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S
-S"/
-S1S
-SF<1kCsOR"b=7m:\MsC7H\PC7kFOl0CM#H\t0L]k\v)q.\t1B7up\v)q.-t113uQPN"R=""nR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
-/S<1sFkO>C#
-<
-S!R--vkF8DsCRFRF0-
-->SF<)FM0R=F"Is)	3qtv.1C3PsFHDo>"/
-<
-S!R--vkF8D7CRCMVHHF0HM-R-><
-S7RCVMI="F3s	).qvtP13CDsHFRo"DP="CDsHF>o"
-SqS"/
-
-
-
-
-/S<7>CV
-]sC
-
-@ 
+%%% protect protected_file
+@EG
+-
+]17p0Osk0CksRsPC#MHF=3"4j
+">
+!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
+S
+SS1S
+SF<1kCsOR"b=BD:\#\OO8lHNF\M8d.34\M#$b#LNCH\DLD\PFEo\$sbCl#F83RP"N.=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S
+S"/
+S1S
+SF<1kCsOR"b=Y):\C#bF\v)q.\t1B7up\v)q.-t113uQPN"R=""nR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
+/S<1sFkO>C#
+<
+S!R--vkF8DsCRFRF0-
+->SF<)FM0R=F"Is)	3qtv.1C3PsFHDo>"/
+<
+S!R--vkF8D7CRCMVHHF0HM-R-><
+S7RCVMI="F3s	).qvtP13CDsHFRo"DP="CDsHF>o"
+SqS"/
+
+
+
+
+/S<7>CV
+]sC
+
+@ 
diff --git a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html
index 8e04933..c7f4530 100644
--- a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html
@@ -1,9 +1,9 @@
-         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS'
 Done: design load finished with (0) errors, and (0) warnings
 
 
    
\ No newline at end of file
diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
index c915f30..a6882de 100644
--- a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
+++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
@@ -1,138 +1,138 @@
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo640c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Wed Aug 16 04:50:53 2023
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F    -0.012      M       2.299     3
-CROW[1] nCRAS F    -0.094      M       2.568     3
-Din[0]  PHI2  F     5.117      3       2.324     3
-Din[0]  nCCAS F     1.863      3      -0.129     M
-Din[1]  PHI2  F     4.727      3       3.095     3
-Din[1]  nCCAS F     0.973      3       0.261     3
-Din[2]  PHI2  F     4.040      3       2.270     3
-Din[2]  nCCAS F     1.372      3      -0.027     M
-Din[3]  PHI2  F     4.809      3       1.454     3
-Din[3]  nCCAS F     0.916      3       0.298     3
-Din[4]  PHI2  F     6.041      3       2.279     3
-Din[4]  nCCAS F     1.531      3      -0.100     M
-Din[5]  PHI2  F     5.903      3       2.260     3
-Din[5]  nCCAS F     2.338      3      -0.268     M
-Din[6]  PHI2  F     6.028      3       1.422     3
-Din[6]  nCCAS F     1.099      3       0.266     3
-Din[7]  PHI2  F     6.673      3       2.385     3
-Din[7]  nCCAS F     0.940      3       0.417     3
-MAin[0] PHI2  F     4.543      3       0.820     3
-MAin[0] nCRAS F    -0.219      M       3.000     3
-MAin[1] PHI2  F     4.179      3       1.515     3
-MAin[1] nCRAS F    -0.122      M       2.681     3
-MAin[2] PHI2  F     9.178      3      -0.474     M
-MAin[2] nCRAS F    -0.219      M       3.000     3
-MAin[3] PHI2  F     9.642      3      -0.572     M
-MAin[3] nCRAS F    -0.200      M       2.949     3
-MAin[4] PHI2  F     9.311      3      -0.515     M
-MAin[4] nCRAS F     0.454      3       1.905     3
-MAin[5] PHI2  F     8.033      3      -0.256     M
-MAin[5] nCRAS F    -0.214      M       2.985     3
-MAin[6] PHI2  F     8.467      3      -0.339     M
-MAin[6] nCRAS F     0.019      3       2.253     3
-MAin[7] PHI2  F     8.283      3      -0.303     M
-MAin[7] nCRAS F    -0.200      M       2.949     3
-MAin[8] nCRAS F    -0.239      M       3.098     3
-MAin[9] nCRAS F    -0.200      M       2.952     3
-PHI2    RCLK  R     2.024      3      -0.115     M
-UFMSDO  RCLK  R     2.747      3      -0.023     M
-nCCAS   RCLK  R     1.461      3       0.049     3
-nCCAS   nCRAS F     0.041      3       2.233     3
-nCRAS   RCLK  R     1.492      3       0.026     3
-nFWE    PHI2  F     9.958      3      -0.643     M
-nFWE    nCRAS F    -0.200      M       2.952     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R     7.721         3        1.581          M
-LED    nCRAS F    12.210         3        2.483          M
-RA[0]  RCLK  R    10.207         3        2.072          M
-RA[0]  nCRAS F    12.761         3        2.565          M
-RA[10] RCLK  R     6.343         3        1.287          M
-RA[11] PHI2  R     8.600         3        1.723          M
-RA[1]  RCLK  R    10.659         3        2.170          M
-RA[1]  nCRAS F    13.632         3        2.755          M
-RA[2]  RCLK  R    10.108         3        2.063          M
-RA[2]  nCRAS F    12.438         3        2.497          M
-RA[3]  RCLK  R    10.970         3        2.227          M
-RA[3]  nCRAS F    12.724         3        2.559          M
-RA[4]  RCLK  R    10.070         3        2.042          M
-RA[4]  nCRAS F    12.332         3        2.480          M
-RA[5]  RCLK  R    11.393         3        2.319          M
-RA[5]  nCRAS F    12.686         3        2.552          M
-RA[6]  RCLK  R     9.403         3        1.934          M
-RA[6]  nCRAS F    11.821         3        2.387          M
-RA[7]  RCLK  R     9.674         3        1.963          M
-RA[7]  nCRAS F    12.064         3        2.419          M
-RA[8]  RCLK  R    10.994         3        2.239          M
-RA[8]  nCRAS F    12.987         3        2.596          M
-RA[9]  RCLK  R    10.979         3        2.227          M
-RA[9]  nCRAS F    13.683         3        2.751          M
-RBA[0] nCRAS F    10.115         3        2.013          M
-RBA[1] nCRAS F    11.594         3        2.334          M
-RCKE   RCLK  R     6.343         3        1.287          M
-RDQMH  RCLK  R     9.332         3        1.910          M
-RDQML  RCLK  R     9.883         3        1.994          M
-RD[0]  nCCAS F     7.724         3        1.665          M
-RD[1]  nCCAS F     7.722         3        1.665          M
-RD[2]  nCCAS F     7.013         3        1.537          M
-RD[3]  nCCAS F     8.183         3        1.765          M
-RD[4]  nCCAS F     8.563         3        1.850          M
-RD[5]  nCCAS F     8.120         3        1.753          M
-RD[6]  nCCAS F     7.474         3        1.636          M
-RD[7]  nCCAS F     8.641         3        1.855          M
-UFMCLK RCLK  R     7.064         3        1.420          M
-UFMSDI RCLK  R     6.343         3        1.287          M
-nRCAS  RCLK  R     6.343         3        1.287          M
-nRCS   RCLK  R     7.182         3        1.446          M
-nRRAS  RCLK  R     7.971         3        1.605          M
-nRWE   RCLK  R     8.121         3        1.645          M
-nUFMCS RCLK  R     7.526         3        1.510          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Sat Aug 19 20:57:24 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.012      M       2.299     3
+CROW[1] nCRAS F    -0.094      M       2.568     3
+Din[0]  PHI2  F     5.117      3       2.324     3
+Din[0]  nCCAS F     1.863      3      -0.129     M
+Din[1]  PHI2  F     4.727      3       3.095     3
+Din[1]  nCCAS F     0.973      3       0.261     3
+Din[2]  PHI2  F     4.040      3       2.270     3
+Din[2]  nCCAS F     1.372      3      -0.027     M
+Din[3]  PHI2  F     4.809      3       1.454     3
+Din[3]  nCCAS F     0.916      3       0.298     3
+Din[4]  PHI2  F     6.041      3       2.279     3
+Din[4]  nCCAS F     1.531      3      -0.100     M
+Din[5]  PHI2  F     5.903      3       2.260     3
+Din[5]  nCCAS F     2.338      3      -0.268     M
+Din[6]  PHI2  F     6.028      3       1.422     3
+Din[6]  nCCAS F     1.099      3       0.266     3
+Din[7]  PHI2  F     6.673      3       2.385     3
+Din[7]  nCCAS F     0.940      3       0.417     3
+MAin[0] PHI2  F     4.543      3       0.820     3
+MAin[0] nCRAS F    -0.219      M       3.000     3
+MAin[1] PHI2  F     4.179      3       1.515     3
+MAin[1] nCRAS F    -0.122      M       2.681     3
+MAin[2] PHI2  F     9.178      3      -0.474     M
+MAin[2] nCRAS F    -0.219      M       3.000     3
+MAin[3] PHI2  F     9.642      3      -0.572     M
+MAin[3] nCRAS F    -0.200      M       2.949     3
+MAin[4] PHI2  F     9.311      3      -0.515     M
+MAin[4] nCRAS F     0.454      3       1.905     3
+MAin[5] PHI2  F     8.033      3      -0.256     M
+MAin[5] nCRAS F    -0.214      M       2.985     3
+MAin[6] PHI2  F     8.467      3      -0.339     M
+MAin[6] nCRAS F     0.019      3       2.253     3
+MAin[7] PHI2  F     8.283      3      -0.303     M
+MAin[7] nCRAS F    -0.200      M       2.949     3
+MAin[8] nCRAS F    -0.239      M       3.098     3
+MAin[9] nCRAS F    -0.200      M       2.952     3
+PHI2    RCLK  R     2.024      3      -0.115     M
+UFMSDO  RCLK  R     2.747      3      -0.023     M
+nCCAS   RCLK  R     1.461      3       0.049     3
+nCCAS   nCRAS F     0.041      3       2.233     3
+nCRAS   RCLK  R     1.492      3       0.026     3
+nFWE    PHI2  F     9.958      3      -0.643     M
+nFWE    nCRAS F    -0.200      M       2.952     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.721         3        1.581          M
+LED    nCRAS F    12.210         3        2.483          M
+RA[0]  RCLK  R    10.207         3        2.072          M
+RA[0]  nCRAS F    12.761         3        2.565          M
+RA[10] RCLK  R     6.343         3        1.287          M
+RA[11] PHI2  R     8.600         3        1.723          M
+RA[1]  RCLK  R    10.659         3        2.170          M
+RA[1]  nCRAS F    13.632         3        2.755          M
+RA[2]  RCLK  R    10.108         3        2.063          M
+RA[2]  nCRAS F    12.438         3        2.497          M
+RA[3]  RCLK  R    10.970         3        2.227          M
+RA[3]  nCRAS F    12.724         3        2.559          M
+RA[4]  RCLK  R    10.070         3        2.042          M
+RA[4]  nCRAS F    12.332         3        2.480          M
+RA[5]  RCLK  R    11.393         3        2.319          M
+RA[5]  nCRAS F    12.686         3        2.552          M
+RA[6]  RCLK  R     9.403         3        1.934          M
+RA[6]  nCRAS F    11.821         3        2.387          M
+RA[7]  RCLK  R     9.674         3        1.963          M
+RA[7]  nCRAS F    12.064         3        2.419          M
+RA[8]  RCLK  R    10.994         3        2.239          M
+RA[8]  nCRAS F    12.987         3        2.596          M
+RA[9]  RCLK  R    10.979         3        2.227          M
+RA[9]  nCRAS F    13.683         3        2.751          M
+RBA[0] nCRAS F    10.115         3        2.013          M
+RBA[1] nCRAS F    11.594         3        2.334          M
+RCKE   RCLK  R     6.343         3        1.287          M
+RDQMH  RCLK  R     9.332         3        1.910          M
+RDQML  RCLK  R     9.883         3        1.994          M
+RD[0]  nCCAS F     7.724         3        1.665          M
+RD[1]  nCCAS F     7.722         3        1.665          M
+RD[2]  nCCAS F     7.013         3        1.537          M
+RD[3]  nCCAS F     8.183         3        1.765          M
+RD[4]  nCCAS F     8.563         3        1.850          M
+RD[5]  nCCAS F     8.120         3        1.753          M
+RD[6]  nCCAS F     7.474         3        1.636          M
+RD[7]  nCCAS F     8.641         3        1.855          M
+UFMCLK RCLK  R     7.064         3        1.420          M
+UFMSDI RCLK  R     6.343         3        1.287          M
+nRCAS  RCLK  R     6.343         3        1.287          M
+nRCS   RCLK  R     7.182         3        1.446          M
+nRRAS  RCLK  R     7.971         3        1.605          M
+nRWE   RCLK  R     8.121         3        1.645          M
+nUFMCS RCLK  R     7.526         3        1.510          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
index aa59e0b..c8a1d3c 100644
--- a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
+++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
@@ -1,17 +1,17 @@
-[ActiveSupport TRCE]
-; Setup Analysis
-Fmax_0 = 42.550 MHz (2.900 MHz);
-Fmax_1 = 400.000 MHz (2.900 MHz);
-Fmax_2 = 400.000 MHz (2.900 MHz);
-Fmax_3 = 115.420 MHz (62.500 MHz);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
-; Hold Analysis
-Fmax_0 = - (-);
-Fmax_1 = - (-);
-Fmax_2 = - (-);
-Fmax_3 = - (-);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
+[ActiveSupport TRCE]
+; Setup Analysis
+Fmax_0 = 42.550 MHz (2.900 MHz);
+Fmax_1 = 400.000 MHz (2.900 MHz);
+Fmax_2 = 400.000 MHz (2.900 MHz);
+Fmax_3 = 115.420 MHz (62.500 MHz);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Fmax_0 = - (-);
+Fmax_1 = - (-);
+Fmax_2 = - (-);
+Fmax_3 = - (-);
+Failed = 0 (Total 4);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO640C/impl1/run_options.txt b/CPLD/LCMXO640C/impl1/run_options.txt
index 1256a49..55b837f 100644
--- a/CPLD/LCMXO640C/impl1/run_options.txt
+++ b/CPLD/LCMXO640C/impl1/run_options.txt
@@ -1,81 +1,81 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\run_options.txt
-#--  Written on Wed Aug 16 04:50:37 2023
-
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-
-
-#implementation: "impl1"
-impl -add impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -num_critical_paths 3
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C}
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO640C
-set_option -package T100C
-set_option -speed_grade -3
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 70
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./RAM2GS_LCMXO640C_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\run_options.txt
+#--  Written on Sat Aug 19 20:57:05 2023
+
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v"
+
+
+#implementation: "impl1"
+impl -add impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO640C}
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO640C
+set_option -package T100C
+set_option -speed_grade -3
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 70
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./RAM2GS_LCMXO640C_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO640C/impl1/scratchproject.prs b/CPLD/LCMXO640C/impl1/scratchproject.prs
index 09b97d6..870188c 100644
--- a/CPLD/LCMXO640C/impl1/scratchproject.prs
+++ b/CPLD/LCMXO640C/impl1/scratchproject.prs
@@ -1,80 +1,80 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\scratchproject.prs
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-
-
-#implementation: "impl1"
-impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -num_critical_paths 3
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/}
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C}
-
-#device options
-set_option -technology MACHXO
-set_option -part LCMXO640C
-set_option -package T100C
-set_option -speed_grade -3
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "RAM2GS"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency 70
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi"
-
-#set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srf" 
-impl -active "impl1"
+#--  Synopsys, Inc.
+#--  Version R-2021.03L-SP1
+#--  Project file Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\scratchproject.prs
+
+#project files
+add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
+add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v"
+
+
+#implementation: "impl1"
+impl -add Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1 -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -num_critical_paths 3
+set_option -project_relative_includes 1
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/}
+set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO640C}
+
+#device options
+set_option -technology MACHXO
+set_option -part LCMXO640C
+set_option -package T100C
+set_option -speed_grade -3
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "RAM2GS"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+set_option -hdl_strict_syntax 0
+
+# mapper_without_write_options
+set_option -frequency 70
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_structural_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr auto
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+set_option -seqshift_no_replicate 0
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi"
+
+#set log file 
+set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srf" 
+impl -active "impl1"
diff --git a/CPLD/LCMXO640C/impl1/stdout.log b/CPLD/LCMXO640C/impl1/stdout.log
index bca3727..330d9d5 100644
--- a/CPLD/LCMXO640C/impl1/stdout.log
+++ b/CPLD/LCMXO640C/impl1/stdout.log
@@ -1,89 +1,89 @@
-Running in Lattice mode
-
-                               Synplify Pro (R) 
-
-                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
-
-                    Copyright (c) 1988 - 2021 Synopsys, Inc.
-   This software and the associated documentation are proprietary to Synopsys,
- Inc. This software may only be used in accordance with the terms and conditions
- of a written license agreement with Synopsys, Inc. All other use, reproduction,
-            or distribution of this software is strictly prohibited.
-
-Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
-Install:     C:\lscc\diamond\3.12\synpbase
-Hostname:    ZANEPC
-Date:        Wed Aug 16 04:50:37 2023
-Version:     R-2021.03L-SP1
-
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
-ProductType: synplify_pro
-
-
-
-
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr"
-Running: impl1 in foreground
-
-Running proj_1|impl1
-
-Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 04:50:37 2023
-
-Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 04:50:37 2023
-
-Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 04:50:37 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
-
-compiler completed
-# Wed Aug 16 04:50:39 2023
-
-Return Code: 0
-Run Time:00h:00m:02s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 04:50:39 2023
-
-multi_srs_gen completed
-# Wed Aug 16 04:50:39 2023
-
-Return Code: 0
-Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
-Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 04:50:39 2023
-
-premap completed with warnings
-# Wed Aug 16 04:50:41 2023
-
-Return Code: 1
-Run Time:00h:00m:02s
-Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 04:50:41 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 04:50:41 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
-
-fpga_mapper completed with warnings
-# Wed Aug 16 04:50:45 2023
-
-Return Code: 1
-Run Time:00h:00m:04s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
-Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO640C_impl1_synplify.tcl"
-exit status=0
-exit status=0
-Save changes for project:
-D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\proj_1.prj
-batch mode default:no
+Running in Lattice mode
+
+                               Synplify Pro (R) 
+
+                Version R-2021.03L-SP1 for win64 - Aug 10, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+            or distribution of this software is strictly prohibited.
+
+Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
+Install:     C:\lscc\diamond\3.12\synpbase
+Hostname:    ZANEMACWIN11
+Date:        Sat Aug 19 20:57:04 2023
+Version:     R-2021.03L-SP1
+
+Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
+ProductType: synplify_pro
+
+
+
+
+log file: "Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr"
+Running: impl1 in foreground
+
+Running proj_1|impl1
+
+Running Flow: compile (Compile) on proj_1|impl1
+# Sat Aug 19 20:57:05 2023
+
+Running Flow: compile_flow (Compile Process) on proj_1|impl1
+# Sat Aug 19 20:57:05 2023
+
+Running: compiler (Compile Input) on proj_1|impl1
+# Sat Aug 19 20:57:05 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
+
+compiler completed
+# Sat Aug 19 20:57:06 2023
+
+Return Code: 0
+Run Time:00h:00m:01s
+
+Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
+# Sat Aug 19 20:57:06 2023
+
+multi_srs_gen completed
+# Sat Aug 19 20:57:06 2023
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
+Complete: Compile Process on proj_1|impl1
+
+Running: premap (Premap) on proj_1|impl1
+# Sat Aug 19 20:57:06 2023
+
+premap completed with warnings
+# Sat Aug 19 20:57:08 2023
+
+Return Code: 1
+Run Time:00h:00m:02s
+Complete: Compile on proj_1|impl1
+
+Running Flow: map (Map) on proj_1|impl1
+# Sat Aug 19 20:57:08 2023
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on proj_1|impl1
+# Sat Aug 19 20:57:08 2023
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
+
+fpga_mapper completed with warnings
+# Sat Aug 19 20:57:12 2023
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on proj_1|impl1
+Copied Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
+Complete: Logic Synthesis on proj_1|impl1
+TCL script complete: "RAM2GS_LCMXO640C_impl1_synplify.tcl"
+exit status=0
+exit status=0
+Save changes for project:
+Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\proj_1.prj
+batch mode default:no
diff --git a/CPLD/LCMXO640C/impl1/stdout.log.bak.2 b/CPLD/LCMXO640C/impl1/stdout.log.bak.2
index bef7f20..a0395cf 100644
--- a/CPLD/LCMXO640C/impl1/stdout.log.bak.2
+++ b/CPLD/LCMXO640C/impl1/stdout.log.bak.2
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:29:26 2023
+Date:        Wed Aug 16 03:31:17 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
@@ -28,26 +28,26 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:29:27 2023
+# Wed Aug 16 03:31:17 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:29:27 2023
+# Wed Aug 16 03:31:17 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:29:27 2023
+# Wed Aug 16 03:31:17 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:29:28 2023
+# Wed Aug 16 03:31:19 2023
 
 Return Code: 0
-Run Time:00h:00m:01s
+Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:29:28 2023
+# Wed Aug 16 03:31:19 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:29:29 2023
+# Wed Aug 16 03:31:20 2023
 
 Return Code: 0
 Run Time:00h:00m:01s
@@ -56,28 +56,28 @@ Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:29:29 2023
+# Wed Aug 16 03:31:20 2023
 
 premap completed with warnings
-# Wed Aug 16 02:29:30 2023
+# Wed Aug 16 03:31:22 2023
 
 Return Code: 1
-Run Time:00h:00m:01s
+Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:29:30 2023
+# Wed Aug 16 03:31:22 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:29:30 2023
+# Wed Aug 16 03:31:22 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:29:34 2023
+# Wed Aug 16 03:31:27 2023
 
 Return Code: 1
-Run Time:00h:00m:04s
+Run Time:00h:00m:05s
 Complete: Map on proj_1|impl1
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
diff --git a/CPLD/LCMXO640C/impl1/stdout.log.bak.3 b/CPLD/LCMXO640C/impl1/stdout.log.bak.3
index 4ea5288..bef7f20 100644
--- a/CPLD/LCMXO640C/impl1/stdout.log.bak.3
+++ b/CPLD/LCMXO640C/impl1/stdout.log.bak.3
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:04:50 2023
+Date:        Wed Aug 16 02:29:26 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
@@ -28,56 +28,56 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:04:50 2023
+# Wed Aug 16 02:29:27 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:04:50 2023
+# Wed Aug 16 02:29:27 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:04:50 2023
+# Wed Aug 16 02:29:27 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:04:52 2023
+# Wed Aug 16 02:29:28 2023
 
 Return Code: 0
-Run Time:00h:00m:02s
+Run Time:00h:00m:01s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:04:52 2023
+# Wed Aug 16 02:29:28 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:04:52 2023
+# Wed Aug 16 02:29:29 2023
 
 Return Code: 0
-Run Time:00h:00m:00s
+Run Time:00h:00m:01s
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:04:52 2023
+# Wed Aug 16 02:29:29 2023
 
 premap completed with warnings
-# Wed Aug 16 02:04:54 2023
+# Wed Aug 16 02:29:30 2023
 
 Return Code: 1
-Run Time:00h:00m:02s
+Run Time:00h:00m:01s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:04:54 2023
+# Wed Aug 16 02:29:30 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:04:54 2023
+# Wed Aug 16 02:29:30 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:04:57 2023
+# Wed Aug 16 02:29:34 2023
 
 Return Code: 1
-Run Time:00h:00m:03s
+Run Time:00h:00m:04s
 Complete: Map on proj_1|impl1
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
diff --git a/CPLD/LCMXO640C/impl1/stdout.log.bak.4 b/CPLD/LCMXO640C/impl1/stdout.log.bak.4
index 51fe536..4ea5288 100644
--- a/CPLD/LCMXO640C/impl1/stdout.log.bak.4
+++ b/CPLD/LCMXO640C/impl1/stdout.log.bak.4
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:04:18 2023
+Date:        Wed Aug 16 02:04:50 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
@@ -28,26 +28,26 @@ Running: impl1 in foreground
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:04:18 2023
+# Wed Aug 16 02:04:50 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:04:18 2023
+# Wed Aug 16 02:04:50 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:04:18 2023
+# Wed Aug 16 02:04:50 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:04:20 2023
+# Wed Aug 16 02:04:52 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:04:20 2023
+# Wed Aug 16 02:04:52 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:04:20 2023
+# Wed Aug 16 02:04:52 2023
 
 Return Code: 0
 Run Time:00h:00m:00s
@@ -56,25 +56,25 @@ Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:04:20 2023
+# Wed Aug 16 02:04:52 2023
 
 premap completed with warnings
-# Wed Aug 16 02:04:22 2023
+# Wed Aug 16 02:04:54 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:04:22 2023
+# Wed Aug 16 02:04:54 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:04:22 2023
+# Wed Aug 16 02:04:54 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:04:25 2023
+# Wed Aug 16 02:04:57 2023
 
 Return Code: 1
 Run Time:00h:00m:03s
diff --git a/CPLD/LCMXO640C/impl1/stdout.log.bak.5 b/CPLD/LCMXO640C/impl1/stdout.log.bak.5
index 2caa0f6..51fe536 100644
--- a/CPLD/LCMXO640C/impl1/stdout.log.bak.5
+++ b/CPLD/LCMXO640C/impl1/stdout.log.bak.5
@@ -13,7 +13,7 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Wed Aug 16 02:03:29 2023
+Date:        Wed Aug 16 02:04:18 2023
 Version:     R-2021.03L-SP1
 
 Arguments:   -product synplify_pro -batch RAM2GS_LCMXO640C_impl1_synplify.tcl
@@ -22,33 +22,32 @@ ProductType: synplify_pro
 
 
 
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\backup\RAM2GS_LCMXO640C_impl1.srr
 log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Wed Aug 16 02:03:29 2023
+# Wed Aug 16 02:04:18 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Wed Aug 16 02:03:29 2023
+# Wed Aug 16 02:04:18 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Wed Aug 16 02:03:29 2023
+# Wed Aug 16 02:04:18 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srs
 
 compiler completed
-# Wed Aug 16 02:03:31 2023
+# Wed Aug 16 02:04:20 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Wed Aug 16 02:03:31 2023
+# Wed Aug 16 02:04:20 2023
 
 multi_srs_gen completed
-# Wed Aug 16 02:03:31 2023
+# Wed Aug 16 02:04:20 2023
 
 Return Code: 0
 Run Time:00h:00m:00s
@@ -57,25 +56,25 @@ Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Wed Aug 16 02:03:31 2023
+# Wed Aug 16 02:04:20 2023
 
 premap completed with warnings
-# Wed Aug 16 02:03:33 2023
+# Wed Aug 16 02:04:22 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Wed Aug 16 02:03:33 2023
+# Wed Aug 16 02:04:22 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Wed Aug 16 02:03:33 2023
+# Wed Aug 16 02:04:22 2023
 Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm
 
 fpga_mapper completed with warnings
-# Wed Aug 16 02:03:36 2023
+# Wed Aug 16 02:04:25 2023
 
 Return Code: 1
 Run Time:00h:00m:03s
diff --git a/CPLD/LCMXO640C/impl1/synlog.tcl b/CPLD/LCMXO640C/impl1/synlog.tcl
index 2e1f256..fdf905e 100644
--- a/CPLD/LCMXO640C/impl1/synlog.tcl
+++ b/CPLD/LCMXO640C/impl1/synlog.tcl
@@ -1 +1 @@
-run_tcl -fg RAM2GS_LCMXO640C_impl1_synplify.tcl
+run_tcl -fg RAM2GS_LCMXO640C_impl1_synplify.tcl
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_comp.rt.csv.rptmap b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_comp.rt.csv.rptmap
index 819ecad..75705fd 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_comp.rt.csv.rptmap
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_comp.rt.csv.rptmap
@@ -1 +1 @@
-./synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv,RAM2GS_LCMXO640C_impl1_comp.rt.csv,Module Runtime Summary
+./synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv,RAM2GS_LCMXO640C_impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr
index ae24fe1..7d03858 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr
@@ -1,108 +1,106 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.db b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.db
index aaabde395cc6edfd7b806127bbb837a60f4ebaa0..b1736ee606b98f88ccc4c0fa7125fa108e192fd0 100644
GIT binary patch
delta 50
zcmZp0XmHrTCcrY4fq&{|L4kb!i48JhnT%}W>B*u@&hEx$CQ6Z3F+r&X`Nfl0%Lg+l
G-v9t$wGM9p

delta 68
zcmZp0XmHrTCcx6bz~8W0P@s%oyN;1vypcayl*!rM*vv%9#VW=>FV&?evn(~nB|o_|
XH#M)MIL1A*#G^E6@@n~DCT<-7k9`zc

diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.rptmap b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.rptmap
index 62b936c..e105a5a 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.rptmap
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_compiler.srr.rptmap
@@ -1 +1 @@
-./synlog/RAM2GS_LCMXO640C_impl1_compiler.srr,RAM2GS_LCMXO640C_impl1_compiler.srr,Compile Log
+./synlog/RAM2GS_LCMXO640C_impl1_compiler.srr,RAM2GS_LCMXO640C_impl1_compiler.srr,Compile Log
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr
index 1678e8f..00bdc38 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr
@@ -1,659 +1,659 @@
-# Wed Aug 16 04:50:41 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:02s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:02s		    -2.99ns		 127 /        92
-   9		0h:00m:02s		    -3.09ns		 127 /        92
-  10		0h:00m:02s		    -3.19ns		 127 /        92
-  11		0h:00m:02s		    -3.19ns		 127 /        92
-  12		0h:00m:02s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:45 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo640c-3
-
-Register bits: 92 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Wed Aug 16 04:50:45 2023
-
-###########################################################]
+# Sat Aug 19 20:57:08 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N: FX271 :"y:\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:57:11 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo640c-3
+
+Register bits: 92 of 640 (14%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:57:12 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr.db b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.srr.db
index cb4c157f860a13dfa9ce989f76c00da7e35eab68..89dd9085930916826180c0a4c42c7ea5bb64c417 100644
GIT binary patch
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diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.szr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_fpga_mapper.szr
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GIT binary patch
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diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr
index d691d60..aef77d1 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr
@@ -1,28 +1,28 @@
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:39 2023
-
-###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:06 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr
index f81b743..1c9fa5c 100644
--- a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr
+++ b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr
@@ -1,162 +1,162 @@
-# Wed Aug 16 04:50:39 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:41 2023
-
-###########################################################]
+# Sat Aug 19 20:57:07 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt 
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:57:08 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr.db b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.srr.db
index d9916f4b03648202292a912b1dd9e9e5e5ec6b27..128214c91be4e56786eca81db5f462f3704ba0cc 100644
GIT binary patch
delta 354
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diff --git a/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.szr b/CPLD/LCMXO640C/impl1/synlog/RAM2GS_LCMXO640C_impl1_premap.szr
index 85706cb6c3d51a69a5139c9c07b124c0a11105ff..06c3b0ee87b17d77b5905cb0defec1b32a842de4 100644
GIT binary patch
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    -
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Wed Aug 16 04:50:37 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-Linked File:  layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-Linked File:  RAM2GS_LCMXO640C_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:38 2023
-
-###########################################################]
-
-
    
-
    -
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Aug 16 04:50:39 2023
-
-###########################################################]
-
-
    
-
    -
-# Wed Aug 16 04:50:39 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  RAM2GS_LCMXO640C_impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS  
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 16 04:50:41 2023
-
-###########################################################]
-
-
    
-
    -
-# Wed Aug 16 04:50:41 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -3.26ns		 127 /        89
-   2		0h:00m:01s		    -3.23ns		 123 /        89
-   3		0h:00m:01s		    -3.23ns		 123 /        89
-   4		0h:00m:01s		    -3.23ns		 123 /        89
-   5		0h:00m:01s		    -3.23ns		 124 /        89
-   6		0h:00m:01s		    -3.23ns		 124 /        89
-@N:FX271 : ram2gs-spi.v(105) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
-@N:FX271 : ram2gs-spi.v(105) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
-Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
-
-   7		0h:00m:02s		    -2.99ns		 128 /        92
-
-
-   8		0h:00m:02s		    -2.99ns		 127 /        92
-   9		0h:00m:02s		    -3.09ns		 127 /        92
-  10		0h:00m:02s		    -3.19ns		 127 /        92
-  11		0h:00m:02s		    -3.19ns		 127 /        92
-  12		0h:00m:02s		    -3.19ns		 127 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
-
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Wed Aug 16 04:50:45 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -3.705
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
-RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
-PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
-PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
-nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
-===============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                           Arrival            
-Instance         Reference     Type        Pin     Net              Time        Slack  
-                 Clock                                                                 
----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
-CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
-CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
-CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
-CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
-Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
-Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
-Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
-Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
-Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
-=======================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                               Required            
-Instance         Reference     Type        Pin     Net                  Time         Slack  
-                 Clock                                                                      
---------------------------------------------------------------------------------------------
-UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
-UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
-nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
-LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
-n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
-LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
-n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
-CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
-ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
-C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
-============================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMCLK_RNO          Net          -        -       -         -           1         
-UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted         Net          -        -       -         -           3         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.702
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -3.705
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
-CmdSubmitted        Net          -        -       -         -           3         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
-N_139_i             Net          -        -       -         -           3         
-UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
-UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                      Arrival           
-Instance     Reference     Type        Pin     Net         Time        Slack 
-             Clock                                                           
------------------------------------------------------------------------------
-LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
-n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
-FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
-FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
-FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
-FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
-S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
-S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
-FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
-FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                               Required           
-Instance       Reference     Type        Pin     Net                  Time         Slack 
-               Clock                                                                     
------------------------------------------------------------------------------------------
-CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
-XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
-Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
-RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
-UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
-UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
-LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
-n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
-nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
-nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
-=========================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            CmdLEDEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN              Net          -        -       -         -           3         
-CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
-CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
-N_21_i             Net          -        -       -         -           1         
-CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.309
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.312
-
-    Number of logic level(s):                1
-    Starting point:                          LEDEN / Q
-    Ending point:                            XOR8MEG / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                      Pin      Pin               Arrival     No. of    
-Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
-LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
-LEDEN                  Net          -        -       -         -           3         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
-XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
-XOR8MEG_3              Net          -        -       -         -           1         
-XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
-=====================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      2.213
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -2.216
-
-    Number of logic level(s):                1
-    Starting point:                          n8MEGEN / Q
-    Ending point:                            Cmdn8MEGEN / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
-n8MEGEN            Net          -        -       -         -           2         
-Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
-Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
-N_19_i             Net          -        -       -         -           1         
-Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                        Arrival           
-Instance      Reference     Type        Pin     Net           Time        Slack 
-              Clock                                                             
---------------------------------------------------------------------------------
-CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
-CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
-FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
-FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
-================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                             Required           
-Instance       Reference     Type        Pin     Net                Time         Slack 
-               Clock                                                                   
----------------------------------------------------------------------------------------
-nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
-nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
-nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
-RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
-nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
-=======================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                Net          -        -       -         -           5         
-nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
-nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
-G_17_1             Net          -        -       -         -           1         
-nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
-nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
-N_39_i             Net          -        -       -         -           1         
-nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.606
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.609
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRowColSel / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
-CBR                     Net          -        -       -         -           5         
-nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
-nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
-N_179                   Net          -        -       -         -           1         
-nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
-nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
-nRowColSel_0_0          Net          -        -       -         -           1         
-nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
-======================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            1.003
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         -0.003
-
-    - Propagation time:                      3.510
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -3.513
-
-    Number of logic level(s):                2
-    Starting point:                          CBR_fast / Q
-    Ending point:                            nRCAS / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
-CBR_fast                  Net          -        -       -         -           2         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
-nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
-N_37_i                    Net          -        -       -         -           1         
-nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
-========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo640c-3
-
-Register bits: 92 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2:           9
-FD1P3AX:        11
-FD1S3AX:        59
-FD1S3AY:        5
-FD1S3IX:        14
-FD1S3JX:        3
-GSR:            1
-IB:             26
-INV:            8
-OB:             33
-ORCALUT4:       119
-PFUMX:          2
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
-
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Wed Aug 16 04:50:45 2023
-
-###########################################################]
-
-
    
+
    +
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sat Aug 19 20:57:05 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+Linked File:  layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+Linked File:  RAM2GS_LCMXO640C_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:05 2023
+
+###########################################################]
+
+
    
+
    +
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sat Aug 19 20:57:06 2023
+
+###########################################################]
+
+
    
+
    +
+Premap Report
+
+
+
    
+
    +
+# Sat Aug 19 20:57:07 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
+
+Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+Linked File:  RAM2GS_LCMXO640C_impl1_scck.rpt
+See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)
+
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
+@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
+@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS  
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+ClockId_0_0       RCLK                port                   48         nRWE           
+ClockId_0_1       PHI2                port                   19         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 184MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sat Aug 19 20:57:08 2023
+
+###########################################################]
+
+
    
+
    +
+Map & Optimize Report
+
+
+
    
+
    +
+# Sat Aug 19 20:57:08 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
+
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -3.26ns		 127 /        89
+   2		0h:00m:01s		    -3.23ns		 123 /        89
+   3		0h:00m:01s		    -3.23ns		 123 /        89
+   4		0h:00m:01s		    -3.23ns		 123 /        89
+   5		0h:00m:01s		    -3.23ns		 124 /        89
+   6		0h:00m:01s		    -3.23ns		 124 /        89
+@N:FX271 : ram2gs-spi.v(105) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
+@N:FX271 : ram2gs-spi.v(105) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
+@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
+Timing driven replication report
+Added 3 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   7		0h:00m:01s		    -2.99ns		 128 /        92
+
+
+   8		0h:00m:01s		    -2.99ns		 127 /        92
+   9		0h:00m:01s		    -3.09ns		 127 /        92
+  10		0h:00m:01s		    -3.19ns		 127 /        92
+  11		0h:00m:01s		    -3.19ns		 127 /        92
+  12		0h:00m:01s		    -3.19ns		 127 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB)
+
+Writing Analyst data base Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
+
+Writing EDIF Netlist and constraint files
+@N:FX1056 :  | Writing EDF file: Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB)
+
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Sat Aug 19 20:57:11 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -3.705
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
+RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      7.560   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705 
+PHI2      PHI2    |  No paths    -       |  350.000     343.998  |  175.000     166.500  |  175.000     171.784
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                           Arrival            
+Instance         Reference     Type        Pin     Net              Time        Slack  
+                 Clock                                                                 
+---------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705 
+CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297 
+CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297 
+CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297 
+CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216 
+Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216 
+Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       166.500
+Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       166.500
+Bank[4]          PHI2          FD1S3AX     Q       Bank[4]          1.348       166.500
+Bank[5]          PHI2          FD1S3AX     Q       Bank[5]          1.348       166.500
+=======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                               Required            
+Instance         Reference     Type        Pin     Net                  Time         Slack  
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705 
+UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705 
+nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705 
+LEDEN            PHI2          FD1P3AX     SP      N_33                 0.806        -2.800 
+n8MEGEN          PHI2          FD1P3AX     SP      N_31                 0.806        -2.800 
+LEDEN            PHI2          FD1P3AX     D       N_70                 -0.003       -2.216 
+n8MEGEN          PHI2          FD1P3AX     D       N_69                 -0.003       -2.216 
+CmdSubmitted     PHI2          FD1S3AX     D       N_460_0              173.997      166.500
+ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      167.797
+C1Submitted      PHI2          FD1S3AX     D       C1Submitted_RNO      173.997      167.797
+============================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMCLK_RNO          Net          -        -       -         -           1         
+UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted         Net          -        -       -         -           3         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.702
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -3.705
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -         
+CmdSubmitted        Net          -        -       -         -           3         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -         
+N_139_i             Net          -        -       -         -           3         
+UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -         
+UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                      Arrival           
+Instance     Reference     Type        Pin     Net         Time        Slack 
+             Clock                                                           
+-----------------------------------------------------------------------------
+LEDEN        RCLK          FD1P3AX     Q       LEDEN       1.552       -2.312
+n8MEGEN      RCLK          FD1P3AX     Q       n8MEGEN     1.456       -2.216
+FS[13]       RCLK          FD1S3AX     Q       FS[13]      1.552       7.560 
+FS[14]       RCLK          FD1S3AX     Q       FS[14]      1.552       7.560 
+FS[15]       RCLK          FD1S3AX     Q       FS[15]      1.552       7.560 
+FS[17]       RCLK          FD1S3AX     Q       FS[17]      1.552       7.560 
+S[1]         RCLK          FD1S3IX     Q       S[1]        1.768       8.533 
+S[0]         RCLK          FD1S3IX     Q       CO0         1.756       8.545 
+FS[16]       RCLK          FD1S3AX     Q       FS[16]      1.612       8.689 
+FS[12]       RCLK          FD1S3AX     Q       FS[12]      1.552       8.749 
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                               Required           
+Instance       Reference     Type        Pin     Net                  Time         Slack 
+               Clock                                                                     
+-----------------------------------------------------------------------------------------
+CmdLEDEN       RCLK          FD1P3AX     D       N_21_i               -0.003       -2.312
+XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
+Cmdn8MEGEN     RCLK          FD1P3AX     D       N_19_i               -0.003       -2.216
+RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
+UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.560 
+UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668 
+LEDEN          RCLK          FD1P3AX     SP      N_33                 15.806       8.261 
+n8MEGEN        RCLK          FD1P3AX     SP      N_31                 15.806       8.261 
+nRCS           RCLK          FD1S3AY     D       N_28_i               14.997       8.533 
+nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653 
+=========================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            CmdLEDEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN              Net          -        -       -         -           3         
+CmdLEDEN_RNO       ORCALUT4     A        In      0.000     1.552 r     -         
+CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -         
+N_21_i             Net          -        -       -         -           1         
+CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.309
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.312
+
+    Number of logic level(s):                1
+    Starting point:                          LEDEN / Q
+    Ending point:                            XOR8MEG / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                      Pin      Pin               Arrival     No. of    
+Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+LEDEN                  FD1P3AX      Q        Out     1.552     1.552 r     -         
+LEDEN                  Net          -        -       -         -           3         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     B        In      0.000     1.552 r     -         
+XOR8MEG_3_u_0_a3_3     ORCALUT4     Z        Out     0.757     2.309 f     -         
+XOR8MEG_3              Net          -        -       -         -           1         
+XOR8MEG                FD1P3AX      D        In      0.000     2.309 f     -         
+=====================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      2.213
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -2.216
+
+    Number of logic level(s):                1
+    Starting point:                          n8MEGEN / Q
+    Ending point:                            Cmdn8MEGEN / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -         
+n8MEGEN            Net          -        -       -         -           2         
+Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -         
+Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -         
+N_19_i             Net          -        -       -         -           1         
+Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR           nCRAS         FD1S3AX     Q       CBR           1.660       -3.609
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.456       -3.513
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.456       -3.405
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+nRWE           nCRAS         FD1S3AY     D       N_39_i             -0.003       -3.609
+nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.609
+nRCAS          nCRAS         FD1S3AY     D       N_37_i             -0.003       -3.513
+RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.405
+nRCS           nCRAS         FD1S3AY     D       N_28_i             -0.003       -3.405
+=======================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+CBR                FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                Net          -        -       -         -           5         
+nRWE_RNO_0         ORCALUT4     A        In      0.000     1.660 r     -         
+nRWE_RNO_0         ORCALUT4     Z        Out     1.189     2.849 f     -         
+G_17_1             Net          -        -       -         -           1         
+nRWE_RNO           ORCALUT4     B        In      0.000     2.849 f     -         
+nRWE_RNO           ORCALUT4     Z        Out     0.757     3.606 r     -         
+N_39_i             Net          -        -       -         -           1         
+nRWE               FD1S3AY      D        In      0.000     3.606 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.606
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.609
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.660     1.660 r     -         
+CBR                     Net          -        -       -         -           5         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.660 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.189     2.849 f     -         
+N_179                   Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.849 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.757     3.606 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     3.606 f     -         
+======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            1.003
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         -0.003
+
+    - Propagation time:                      3.510
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -3.513
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.456     1.456 r     -         
+CBR_fast                  Net          -        -       -         -           2         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.456 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.753 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_RNO                 ORCALUT4     B        In      0.000     2.753 r     -         
+nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.510 f     -         
+N_37_i                    Net          -        -       -         -           1         
+nRCAS                     FD1S3AY      D        In      0.000     3.510 f     -         
+========================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo640c-3
+
+Register bits: 92 of 640 (14%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2:           9
+FD1P3AX:        11
+FD1S3AX:        59
+FD1S3AY:        5
+FD1S3IX:        14
+FD1S3JX:        3
+GSR:            1
+IB:             26
+INV:            8
+OB:             33
+ORCALUT4:       119
+PFUMX:          2
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 196MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Sat Aug 19 20:57:12 2023
+
+###########################################################]
+
+
    
diff --git a/CPLD/LCMXO640C/impl1/syntmp/RAM2GS_LCMXO640C_impl1_toc.htm b/CPLD/LCMXO640C/impl1/syntmp/RAM2GS_LCMXO640C_impl1_toc.htm
index ee1c362..4d931c0 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/RAM2GS_LCMXO640C_impl1_toc.htm
+++ b/CPLD/LCMXO640C/impl1/syntmp/RAM2GS_LCMXO640C_impl1_toc.htm
@@ -1,58 +1,58 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
  
\ No newline at end of file
diff --git a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_compiler.log b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_compiler.log
index 47810e2..4e68afb 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_compiler.log
+++ b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_compiler.log
@@ -1,10 +1,10 @@
-C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO640C -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
-rc:0 success:1 runtime:2
-file:..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs|io:o|time:1692175838|size:10551|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr|io:o|time:1692175838|size:4581|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\..\RAM2GS-SPI.v|io:i|time:1692174460|size:11765|exec:0|csum:DDFDD384E6E6239925365D2C41FC9773
-file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
+C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs  -top  RAM2GS  -hdllog  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I Y:\Repos\RAM2GS\CPLD\LCMXO640C  -I Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO640C -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
+rc:0 success:1 runtime:1
+file:..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs|io:o|time:1692493025|size:10491|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO640C_impl1_compiler.srr|io:o|time:1692493025|size:4494|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\..\RAM2GS-SPI.v|io:i|time:1692234355|size:14885|exec:0|csum:22AA32E3708F79533C7AD37D1C9B8166
+file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
diff --git a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_fpga_mapper.log b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_fpga_mapper.log
index 0662fec..edd1a4a 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_fpga_mapper.log
+++ b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1   -part LCMXO640C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\report\RAM2GS_LCMXO640C_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\syntmp\RAM2GS_LCMXO640C_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO640C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO640C_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO640C_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO640C_impl1.plg -osyn ..\RAM2GS_LCMXO640C_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
-rc:1 success:1 runtime:4
-file:..\RAM2GS_LCMXO640C_impl1.edi|io:o|time:1692175845|size:125385|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:i|time:1692175841|size:15190|exec:0|csum:9F911839406505D524BE4CEAD0B58F03
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO640C_impl1.plg|io:o|time:1692175845|size:854|exec:0|csum:
-file:..\RAM2GS_LCMXO640C_impl1.srm|io:o|time:1692175844|size:29135|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr|io:o|time:1692175845|size:35917|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1   -part LCMXO640C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\report\RAM2GS_LCMXO640C_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi   -freq 70.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\syntmp\RAM2GS_LCMXO640C_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.srm  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO640C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO640C_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO640C_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO640C_impl1.plg -osyn ..\RAM2GS_LCMXO640C_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
+rc:1 success:1 runtime:4
+file:..\RAM2GS_LCMXO640C_impl1.edi|io:o|time:1692493031|size:125386|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:i|time:1692493028|size:16785|exec:0|csum:178209CFAD9CF12DF8E8DF39B113B165
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:RAM2GS_LCMXO640C_impl1.plg|io:o|time:1692493032|size:854|exec:0|csum:
+file:..\RAM2GS_LCMXO640C_impl1.srm|io:o|time:1692493030|size:29193|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO640C_impl1_fpga_mapper.srr|io:o|time:1692493032|size:35763|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_multi_srs_gen.log b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_multi_srs_gen.log
index 5140b26..db06364 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_multi_srs_gen.log
+++ b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -1,7 +1,7 @@
-C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr
-rc:0 success:1 runtime:0
-file:..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs|io:i|time:1692175838|size:10551|exec:0|csum:3D60DEE8C5D91625A20313AD35E47D0F
-file:..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs|io:o|time:1692175839|size:10295|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr|io:o|time:1692175839|size:1157|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
+C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs  -log  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr
+rc:0 success:1 runtime:0
+file:..\synwork\RAM2GS_LCMXO640C_impl1_comp.srs|io:i|time:1692493025|size:10491|exec:0|csum:12A53627E8CBEEEF92B6756D748ED400
+file:..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs|io:o|time:1692493026|size:10367|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO640C_impl1_multi_srs_gen.srr|io:o|time:1692493026|size:1163|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
diff --git a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_premap.log b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_premap.log
index c4400aa..aae7980 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/cmdrec_premap.log
+++ b/CPLD/LCMXO640C/impl1/syntmp/cmdrec_premap.log
@@ -1,14 +1,14 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1   -part LCMXO640C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\report\RAM2GS_LCMXO640C_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_cck.rpt   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\syntmp\RAM2GS_LCMXO640C_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO640C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO640C_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO640C_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO640C_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO640C_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO640C_impl1_premap.srr -sn 2021.03 -jobname "premap"
-rc:1 success:1 runtime:2
-file:..\RAM2GS_LCMXO640C_impl1.edi|io:o|time:1692174593|size:125385|exec:0|csum:
-file:..\RAM2GS_LCMXO640C_impl1_cck.rpt|io:o|time:1692175841|size:4751|exec:0|csum:
-file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs|io:i|time:1692175839|size:10295|exec:0|csum:26C922427A03758F05FE1D9390156563
-file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:o|time:1692175841|size:15190|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
-file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO640C_impl1.plg|io:o|time:1692175840|size:0|exec:0|csum:
-file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:o|time:1692175841|size:15190|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO640C_impl1_premap.srr|io:o|time:1692175841|size:8417|exec:0|csum:
-file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1   -part LCMXO640C  -package T100C  -grade -3    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\report\RAM2GS_LCMXO640C_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi  -conchk_prepass  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_cck.rpt   -freq 70.000   -tcl  Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\syntmp\RAM2GS_LCMXO640C_impl1.plg  -osyn  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_prem.srd  -prjdir  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\  -prjname  proj_1  -log  Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synlog\RAM2GS_LCMXO640C_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO640C -package T100C -grade -3 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO640C_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO640C_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO640C_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO640C_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO640C_impl1_premap.srr -sn 2021.03 -jobname "premap"
+rc:1 success:1 runtime:2
+file:..\RAM2GS_LCMXO640C_impl1.edi|io:o|time:1692234355|size:122599|exec:0|csum:
+file:..\RAM2GS_LCMXO640C_impl1_cck.rpt|io:o|time:1692493028|size:4637|exec:0|csum:
+file:..\..\..\RAM2GS.sdc|io:i|time:1692234355|size:177|exec:0|csum:D3C84F35CD07AA1A8E8B9E68D571CD53
+file:..\synwork\RAM2GS_LCMXO640C_impl1_mult.srs|io:i|time:1692493026|size:10367|exec:0|csum:C7D441417E65C26355C99F5CF1E4BB69
+file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:o|time:1692493028|size:16785|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v|io:i|time:1628601068|size:42996|exec:0|csum:DB253AD0113DC963D616C8E55D1D1D5D
+file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
+file:RAM2GS_LCMXO640C_impl1.plg|io:o|time:1692493027|size:0|exec:0|csum:
+file:..\synwork\RAM2GS_LCMXO640C_impl1_prem.srd|io:o|time:1692493028|size:16785|exec:0|csum:
+file:..\synlog\RAM2GS_LCMXO640C_impl1_premap.srr|io:o|time:1692493028|size:8364|exec:0|csum:
+file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO640C/impl1/syntmp/statusReport.html b/CPLD/LCMXO640C/impl1/syntmp/statusReport.html
index a96d302..e629912 100644
--- a/CPLD/LCMXO640C/impl1/syntmp/statusReport.html
+++ b/CPLD/LCMXO640C/impl1/syntmp/statusReport.html
@@ -1,115 +1,115 @@
- 
- 			 			
-			Project Status Summary Page
-			
-			
-			
-
- 			
- 			
-
     
- 
- 
-
- 		  
-		 
-
-
-
- 
- 
-  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO : LCMXO640C 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  0  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
- 				   
-         
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- 			
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- 			
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-
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-
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-  
-  
-     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete400-00m:01s-8/16/2023
    4:50:38 AM
     (premap)Complete27100m:01s0m:01s173MB8/16/2023
    4:50:41 AM
     (fpga_mapper)Complete20600m:04s0m:04s185MB8/16/2023
    4:50:45 AM
    Multi-srs GeneratorComplete8/16/2023
    4:50:39 AM    		 		
    
- 
     
- 
- 				   
- 
-  
-  
-
-
-
- 
-
-
-
- 
-
- 
-
-    
    Area Summary
     
     
     
    Register bits 92I/O cells 67
    Block RAMs
-(v_ram) 0DSPs
-(dsp_used) 0
    ORCA LUTs
-(total_luts) 119

    
- 
- 				   
- 
-  
- 
-    
- 
- 
- 
- 
- 
- 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz0.6 MHz-3.705
     RCLK62.5 MHz13.3 MHz-2.312
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz0.6 MHz-3.609
    
-
    
- 
- 				   
-  
-
- 
-
-    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
-
     
-
     
+ 
+ 			 			
+			Project Status Summary Page
+			
+			
+			
+
+ 			
+ 			
+
     
+ 
+ 
+
+ 		  
+		 
+
+
+
+ 
+ 
+  
     	     
    Project Settings
      Project Name  proj_1  Device Name  impl1: Lattice MachXO : LCMXO640C 
      Implementation Name  impl1  Top Module  RAM2GS 
     
      Pipelining  0  Retiming  0 
      Resource Sharing  1  Fanout Guide  1000 
      Disable I/O Insertion  0  Disable Sequential Optimizations  0 
      Clock Conversion  1  FSM Compiler  1 

    	 
+ 				   
+         
+ 		
+ 			
+			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+         
+  
+  
+ 
+
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+  
+     
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
     (compiler)Complete400-00m:00s-8/19/2023
    8:57:05 PM
     (premap)Complete27100m:01s0m:01s184MB8/19/2023
    8:57:08 PM
     (fpga_mapper)Complete20600m:03s0m:03s196MB8/19/2023
    8:57:12 PM
    Multi-srs GeneratorComplete8/19/2023
    8:57:06 PM    		 		
    
+ 
     
+ 
+ 				   
+ 
+  
+  
+
+
+
+ 
+
+
+
+ 
+
+ 
+
+    
    Area Summary
     
     
     
    Register bits 92I/O cells 67
    Block RAMs
+(v_ram) 0DSPs
+(dsp_used) 0
    ORCA LUTs
+(total_luts) 119

    
+ 
+ 				   
+ 
+  
+ 
+    
+ 
+ 
+ 
+ 
+ 
+ 
    Timing Summary
     
     
    Clock NameReq FreqEst FreqSlack
     PHI22.9 MHz0.6 MHz-3.705
     RCLK62.5 MHz13.3 MHz-2.312
     nCCAS2.9 MHzNANA
     nCRAS2.9 MHz0.6 MHz-3.609
    
+
    
+ 
+ 				   
+  
+
+ 
+
+    
    Optimizations Summary
     
    Combined Clock Conversion 4 / 0

    
+
     
+
     
  
\ No newline at end of file
diff --git a/CPLD/LCMXO640C/impl1/synwork/.cckTransfer b/CPLD/LCMXO640C/impl1/synwork/.cckTransfer
index fda5e8f94eba7dafb5be05db18f257d8d9ea42b0..c06976e4092fb00d140843dab49a563eb9521dbd 100644
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diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.fdep b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.fdep
index db31bc0..cbbfcb4 100644
--- a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.fdep
+++ b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.fdep
@@ -1,16 +1,16 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO640C\\impl1\\synwork\\RAM2GS_LCMXO640C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO640C|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO640C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692174460
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work RAM2GS 0
+#OPTIONS:"|-layerid|0|-orig_srs|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO640C\\impl1\\synwork\\RAM2GS_LCMXO640C_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO640C|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO640C\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo.v":1628601068
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+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
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+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692234355
+0			"Y:\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work RAM2GS 0
diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv
index 915b7cd..0b328e3 100644
--- a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv
+++ b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_comp.rt.csv
@@ -1 +1 @@
-Library, Design Unit, compile Time, Peak Mem Usage
+Library, Design Unit, compile Time, Peak Mem Usage
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diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_m_srm/1.srm b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_m_srm/1.srm
index 2ca303fafe8e5a93378fa347a5ea58a44491a48f..b92137a8857f35811f316d01aef8f49699fd5729 100644
GIT binary patch
delta 1153
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diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_m_srm/fileinfo.srm b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_m_srm/fileinfo.srm
index adf68aabb3bc69f378c5744876d9590550701e2b..44488e09d7bcb1376e45cb6675f4bf52dcfb5e9d 100644
GIT binary patch
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diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_prem_srm/fileinfo.srm b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_prem_srm/fileinfo.srm
index 51942619a1907f37869b33bd4eb72d7a8f34600d..f7e65ac6c7cfca567b9fdf2c6ed2782f44abbf0d 100644
GIT binary patch
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diff --git a/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_prem_srm/skeleton.srm b/CPLD/LCMXO640C/impl1/synwork/RAM2GS_LCMXO640C_impl1_prem_srm/skeleton.srm
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delta 68
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XH#M)MIL1A*#G^E6@@n~DCT<-7k9`zc

diff --git a/CPLD/LCMXO640C/impl1/synwork/modulechange.db b/CPLD/LCMXO640C/impl1/synwork/modulechange.db
index 42e2c42ba15c6fbf8dffd73f1dc7b727af7a18b2..ad06d65e74818c5f5f0484ca25ef7adbf4764a3d 100644
GIT binary patch
delta 199
zcmZoTz}Rqrae}mk%zoMAy(e=4E&S$R`RRzh4P-?tSAu4
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m@BAM(^C&#!=VxJOW?=l!&c@8Zl5(e`W|P5xc}Dg{0RjMPfidX-

delta 157
zcmZoTz}Rqrae}lUKLY~;8xX^Q{zM&Paef9pk%zoMAy(e=4E&S$R`P}Np66HHtSAu4
z%iPE;Ir$QA3!}v5aK5#SLhO7&4E#s=JNbS2dHK%rP2>yOtf*ka$7ajM!cfjKIa>&E|=6#f%&b0t^iN-}%36=23Xc&(Fa4pM{Z`osF3RsHEz{CWHU-jBJYn1OQuc
BC87WT

diff --git a/CPLD/LCMXO640C/impl1/version.log b/CPLD/LCMXO640C/impl1/version.log
index 9d5f37d..a8d67f6 100644
--- a/CPLD/LCMXO640C/impl1/version.log
+++ b/CPLD/LCMXO640C/impl1/version.log
@@ -1,2 +1,2 @@
-R-2021.03L-SP1
-Synplify Pro (R)
+R-2021.03L-SP1
+Synplify Pro (R)
diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws
deleted file mode 100644
index 63563b76eda4b19c3f4f321afd3f1b7df67b8d5e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 48
ocmZ?JV1NM`h8%`OhGK>ihIoc@hJ1!1hHN0O04SEskP1@-0GYrBX8-^I

diff --git a/CPLD/MAXII/db/RAM2GS-MAXII.quiproj.11208.rdr.flock b/CPLD/MAXII/db/RAM2GS-MAXII.quiproj.11208.rdr.flock
new file mode 100644
index 0000000..e69de29
diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb
index cb9fb76a5cee67b4d2c7d25fbf69877374c0bea9..ed0caddb38db5c7b1edae706ccf17722f0ed44c8 100644
GIT binary patch
delta 2770
zcmV;@3N7{48T}cMM}L_#00000004Ij00000003J80000000000008|A00000004La
z?3zo6q*oQkdt%}<5m7-=QILQL#;&S&scPq1T
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z=iYnnx%YlE56;;0LwUXZ{C7SEZ}1#=MB;n+Rs5vM%*lnBnfJ*1{C7SE=Q(hm1LryL
z=E#BfOHKcv{G`0=-tdLB&Ckg1%Ln75WBAA)z0W_qU0^eMHHM|>%!LP~@%F{_&Zp$f
zL-aE+H@gSp7Jr01k=bjub_?cPMB1+?_76{vUGV`-JS4wyuh-ov92vKn;^Kb1wmT?P
z@w74MJ5PMO^Q&N+L&;tnU*Zam{$jSFwX$^OB(;D5eVxkpbwbzHDf-mjY2ubSAO
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z=V&pag^1=Onv19tQ9Gj69(O}Zix`Y>F~Nld=M$Vuu#;drL9@F$96uB6Dm1$a&8|YT
ztI+H!G`kATu0pd*&Aeh<<7#|M{zPi{33I_XmLm><*cshWz9<9@LDqXw=!V`awB9SU-Yc};E41D#wB9SU-Yc};E41D#Z0%Vx
zi+`^GmK`iPSah)9VBW!;gN}o?gJ4-o_=Z}hmebqarXR8$WZ4d~YzJAkgDl%YmhB)L
zDUf>*bLK&;1rQ>|R^Wt4u@pEVQtU8aauVqy>9WBw|J`Qi>4T?^;q~De=&z4;VVRJE
zDh&seeI{1$wpH~Y**dyr*(8!xsq3_DK7YRrWH92(Zi$V3{GnGDCn_UUwY<
zrX#>~1hn=jCv^B+NFp(DWc9|Sss#lim$VruRnS(tF4b_KYuSpvNnlU
z7c9c8PHF9mMxGM8u*I%g9QsSgCfU`jcu>
zs#B?UrFxcX+)}87X)jAC?SFJ>_e(os+9lJ@Y1TMoGEZS!k1*Tpvm-!uFvyMz*&!l3
zT4V=~>=Qrk}_1`;Z-k(#T)D^8J9Qa5VPW)xvkrB|L@B*YCDYSDObP0>aCwKu9-VSo
z?#sI368&5eh|pIT{eLYpXgzmHZVp#eFqh>9^?2k0|8@b5CpoLQXxbk0uq;9gHKIPq
zy9N#;>TE{P*)nI&W(NY}Wz4NF33`f6AS)&cWU<5+z0g9nSXV9~k2Z4RqPHg(6TYOj
ze66+jkT}&!l&-!g(|e`cpag>HuPk67M*%q`#LuztEFT=LX@8(P1>RPM9OzT#m}CYM
zl-QKB0F>@WcJXmigxrH584bNZKwywdg<~!nU<}%Y$(v|Zcaaj>F%*@Wa}zS?6K@1o
zHJn03Ew&cd0;`sGPc|V0bV7HxB^~HUE|%m%NzRw#TuF9H(k4_#%RT|PU)|T2qq34I
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zF_6ryEPt&Z%(`7rke(d!;1R
zqh+Mc4;S%m2EnpSj6r4fwe{C|l
zuC7BPzqzB6U&NuyyS8h{=c|~H`6by~q|aM$^k$pBf5Do*FlP<30S=~P_F*WyF-P0!
z)(k7ZIYSq>XLppo8@mdpkvKARTQ9~_9NFX|2Y
z{5~!}In?PtAqlj#`(8!aAC3&9NAbY?W8M@g%$I9SKN_Q?51RaIaq++`!a)l2)N^ml
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zk$+z?`Y;QI(CVnle4*w&KjYI{oBye%IjiFA58nS()2w>`MAlN_y#@b=nxp4y%xOPo
zPh2s;G$W)_&za1-Z$6nedZx{3#d{3tH8y8EDxNoJoJEWfXU6$lEknLF-Tutx(~4(1
zdX1W#7>b9GI5ri}>mO$k4#b-?Bu*j4Lw`4K*K+Bbg_;oeVL*;*jy_y-bjlfwYF&D0
znu}&rv-yLX_a|zaKlyidFhSu=@A*eHwS;C{QT7Ms_iNr?%9IqM`Lh~xvDW+-HO=E%
z@GsOfpRX~0S8M*~nx_93ohT#tZY|EAN0k83+^A{(xTd*X)BJsnSxwsS)HHuvV}E|P
z=DoUiRGHtd+5CEq`9Ljcs|T}>)tdjR#(bn^^8>XWeXrL1b2a9NYBry%Wyn^|(fex5
z6=4=;Nrs<_cb?b)=1VyP3CyCYGam)y51NHNgfRIqSv+TI{^PE_S3|0V?3O^}mcJ_Ir8~uPE+w4C1>970;vrG$$0jxbyod5s;

delta 2724
zcmV;V3S0I48P*w)M}L4c00000002-600000003J80000000000007nu00000004La
z?3zo6q*oQkdt%}8?(yyOr6v
z(1k&F?p%mV5f_3WxY0!*f(uuQpy1BnMg(1`_!`geoO|x0`hONAamK{ZA5?$;^SI}n
zd+)jD-uulwIA_my<@L^s-^Ccb$#dWliSOap@slQVXP4&Y9+mgS?_vxta^NBdE^^?l
zkpmx)n*JgANqN`3;j`;opOoL{55^~_@R2`ukAHZ(#Aft*3`^6wOAkup>sK~9pO7~X
z(a*u$>K=?+5P$MSX0O@aEtqc;X}_Y_KR!Ek#Ro9)ko?BIUU#Q(WZY(oi~I5V?x0Y`
z)8?S>JT(fhS?d;#5HuB5-?eC@JsdZ^7>%04Z`0en>ONw(o8HwJOw=4VDMDpxXPT@t
z88_>A@^X~9N$ST!-Mnix*1
zCPtI}lTl$9f5#`cM&td0{SIM2KRLcV**_}yjPT8~lRM7TUSmVTkc=tV%#)Zdc-Wns
zK7Y=H&ga~_M9M=G8Kb}5y?Zw!ag&jOa%Cs;_uoqc?+&tH{-32ZZ}gaYYk0hkq)jw3&6OPha1a#
zj+P=?jA$XE`G`6ZwIgcnaW|y2h`|V#5?oAhA;I|sI|;TEG`nm2=xvRcLmpnKz89(72S>8>FowWCtYeD^Fx^%Tr{gCY-%XW}uJIJyfWZ4d~YzNs$
zf!u?bGY?`dfDkFR0w+X@rN9Z1Vu$&XlSm&)mko~j?>0Nn9z1gjuMf{ae`Bl*%Y+nE
zX*i(lGqHlNTU8H|?UP%UO(I#7x=!2XGk@2C3`W1{Z=aolL@v4y8`>Bjoc52$qd+#J
z7t{k}uf212^XTC8bTowQ_9IF4?HvsVmL?OWm9nzcNgwjG3uy!$G>7_b5
z8s@!|CfdQE%sz<4rx|O{GCi&SH=(Jw2LrVM;D5(Py*Y0j}%cjh&E0dO{|1
z!t{|ZgBQ;B4_gtnL#lY@M1gK!s((Dsbm*RhsZf9MFWXX7Um(2haHy7Tkp)gW>MX*c
z>jF&I1
zn5t2wlcMURs5&W{&U~02U7M+0il~z!>MWJzA*rYMIxG45qxZ7f`e^p^Qhy|ClW29p
zBFyTP)~;woYF1eGVbxA8=~rJPa1*veY-B}8O{S6*MntP#QICjN7fS$f`NRb^U)vee
ze%o!g7!mFim>4&b$p&QOHHq!SaoOezIWFzE*yHk#1tFG*STtf8S&bDd)vi>3QcX&A
zD%Gx3&r*$B4wW$NWeKI7E`RNQX-7=EWZF5+8i!2gDQxQzW}AI>1jr5s*>NE|L}W*c
z?7)#7Lu^c>ph+QMQG?9a^eHbp`(-D>?3|dL9fOve_dmImN4LpO|p%xBY)grZ07&Vt(Qg)l8AX5Giqn4Ih7OipL9Ib0mI)4SOCqoYODRWFRg9$)}
zUd{qgx*yra$4L=#4}zrUdVhe>`H@S7V=fwC4BCasn`l*ckrLVo6qTBH6EeUPZv<8~
zoI*q`wied{tCn_8HX#IbLU*@i9n?rJmE>YcE|lbaNp?!oCQnDpJ^{F2-Pc#5vXUtb
zB~utmrZALDVUxKB3jsuv#RohA)sq4UNq>t4*(u5PLMc^}IAytRXdNYhaEn2exs~Ow
z^@CZr3n~&?vG#OPM$t-XU&$z3E`>^BM(?1=qUKVmsU({EwW5%=o!qI*5@KdzJM{-;m+m5LtwYJ7=0qZ+Sqmo?EpGANiSXe7G6YlF?0=|{
z7>v$eq@opd(3v82qEa;Fyp^$a)G1qxd~zU`a0&O17O;wM3eF(;zcd-$R@b4C-`vs3
zFXGVUUE4L}^Ht2p{F3Y~(&sHWdb3U6zhF&Yn6rl200+}C`!JN-Jy_(JG*4q4+HO==|
z%cZXtYC_zD0XeBT`bf>uIe%v`s%7n=X)c;g&E|J%-k+*z{@~x)83cuy-t&)YY6;D@
zqU;aMZ`ZuPk|`-f^G7x2Qmy$IUJa?bI;tW4uIA{YMUX-e=g(@IUlBnO0h;HY*T$@_j;hUH&?R}I
e@KHgRFF(nSmJP5wkefshj{sXgf3yJ~sXGNv}

diff --git a/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb
index 1aff5d6ed8affa49cd554b49347974408cad1e75..151fd5fbb1246b7bbe20b34c2f41599212bf0b45 100644
GIT binary patch
delta 672
zcmV;R0$=^?3hWAyj(_7YO;RmwGGUTf-1vjsx^v;eg}8Fz5AX;014JlTzwf^0P9B}i
ztu3_VgfsVX?sx7v=e|y6gb-)IXTcXd7!XT;3qlm|n-#}oADZGanB`U3BgAoCosZsR5?$E=aZmB6%_=v9{d
zkiM$A`l?5S_4Iya&*7JS{Klv792l`G$uqrJtQLdP@{`vA9w1Sd-GuKKRTzZYor&+a
zoVcj?Br?`a%(7%$RG#raJKK{L0zFRySf@!q|B}}tw}?uRn5T1*vzQymW#YJ*viLXV
zb8&!(+x&p;gKJCWAl&Tr*IGe4YBz&^`|bRQzMvkpI*_+@y2a`5crYNAnE!1>@dlHj
z0wNO&P)~Lw4zEmzIXKkquLfJ|
zar3Tmjt=ok_^yMYTpi9XUGO~@%s(^+tonBc^Nx|kneu`kXsk>RCjp!BEVcJ6I#h9--A5+Z1#Es`TPpmmM@0w0AYAyF8Zh>=-9-{7?t|xk_m~S(Y
zO?w+lPBv}+qasT(c*rHmP8v?4mJjGQhjd&i2jjz82FDl~XXFDqiM~M{le9U{KLE48
G1FZo8XHfzG

delta 672
zcmV;R0$=^?3hWAyj(?%UG)Zk~lL?c=;>I83)}0F%F2t1!e}F&0y&`l`zwf^0P9B}i
ztu3_lgfsVX?sx7v=e|y+gb-)IXTcXd7!XUp3qlm|n-<4pADZGanB`U3BgAoCozXoTfJ%)0Kl(6)IV#H-F;YnBLf(>CHIoHm$XJ
z;}&)6&35Pop9ZQEM{nY=H3B~+`*w=l35;0oci-88d2L77qrTso(>k~=r{*Wm)bu;<
zb*$-DiLPvexTknjW_2I+-*{}IF+UfSi!XwuTD4NE29>4f)u8&a@|5QlqQP#hVnktP
zVVTgNFNuV;BTLNw#=wm}cgFBub4MuK(miZtujyW3!biOLFM;)rEiI-t?0F>_=v9{d
zkiM$A`l?5S_4Iya&%u{{{Klv792l`G$um7)tQLdP;*-|_9w1?t-GuKKRTzZYor&+a
zoVcj?Br?`a%(7%$RG#s_+gpC
z0wNQ0P)~Lw4z5gy893DKF9(}z
zar3Tmjt=ok_^yMYTpi9XUGO~@%s(^+tonBb^Nx|kneu`kXsk>RCjp!BEVP
zS)MHU=3X!u>cJ6I#h9--A4iz|i5t&xo>+5i-ZeeKsI}aSxV>`D(L>ao)Ad9z74tJK
zvT1K&$;qb8e^g{i1`oL;*-67m)bat{=8%pnkW0E%K`3JMV
G1FZr1mtF+`

diff --git a/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb
index 67484baf30c64f553732f4ca6e1eeb8d04c639f0..1fdc0000f5a2cfa2d06da4ea7705d1b9fcaf3dd0 100644
GIT binary patch
delta 523
zcmV+m0`&ck2aN}iPk%K600000000F70000000000004~x00000004LaZd0!HEyx#*uTBCMi_3N#!I(d?Me%FMwdij$J#kip2APrEPX+U-o$G
zZlKm7KD}?0x@>R^W$zc|0KJYN9moK3b9Eg?v$C4Z!z|Czuz$*ymmVyP^Z5e)tYq>&
z;@SNf6fT}4P-rsE9CRC=NECOI(t#PAcuOS0S0eG3NJUhnPGR=T
zi#W|92i^g^5c#c$<__KkKCX&K4Q{{=SOeS0E3;<_ZvsYXCzN$XxoDMWQN-jnMG|dO
zWP%-vEYzaNlz(t3GQkc-CfKD&!XAnw-lWLXa4C{7e=Le5=AlU90So`>Qp979l>$<^
zS2e9_25O(2N%|DW^hsI?DJFZ+>iOD*T2$lkVJgzTZ47KaqTCYkkBHA)fuOf5ez*voL4^qbAUA0)ImS)@EteN1(bo7cG5Som1bJ
z4pbLO%iOPascY9RISnfVGos_v=xA5OmuzL!aTjRt1bM^4M=f^bk`Jj;gMg3DGsCbn
zCPDcc83YP}S38PMg5Jm%U!>DSr~dP$0K@VRi{HgnH?%$;*@
z(srcQAs(G?6rDCY#%AvqFRlVuJSt{$*z=0P
z`;gO52#;-jDR>K~CSo*wILC&I_lOjlPI3?3h9wc@{kZaAI;X)DsR*S=!znV6l$n>9
z=N08B%M%aY0X!GQok(UL-UdFb%O?YFK#!OMWfZloS;Cuuk=k=*UQx{(DH;?pxJi*j
zn-p1Rk0J+kD1Wjke2T2IN0D{*DUxu2B8jh3WOMiwNtizlMG^~8B=Lxe|8yzhF~@2H
zQdz5-Ry70KCTEg1#W8J?Rzix&4t9FJcCjt%Vf;7|S=Uv1uF`jv!3kp4zVJU&DyNjA
ztFFd@XHRe=UPq6$TW7Be+yw@!Kz9}B6X-(%*IWOMV`iXJ2UT4ix66{LnTwbh-3sHV
zdPL2(&X`n3jY&3osi6JFPfdj}CHzP&747$77a4I0d4{}U;h`4GlHV8u@JZm+^)g`4
o)BK;%NiKT5@DwZ!shl1_3qAh{cxIW<8#0g4yjZ*gvoQi(0hMFh!T{v@r6Hyet
zEe`?TuZRx}iMnxNf*TWcGo`f>fi^Rdj3Iw$JJTjE3>yYy{2&iHl5?Z*0-w?-ml|hKVe63@}2
z?groiVpSfnRfd$To3|=IwaBp&&rg!Ok?j!&doCP}Rk_BtUw1>h!bhjcF6#vsLu^z0
zD~GF(SWd2i{pCNm7+L+7y*Du_grM(ob$Na7*DFoz$CD-eveoI`hc7H#7r}qXAyqin3A?nNKLPo{rnom*F%CtMn4l<4Oksa_Mx=A+p-InE!8EKwKY7Uro`(@nO4h7hSTvHfggrTQ
zdC)|(l+9AnG!~Mygy-lSbc~A;@ykC6XyGUNhv0bs2HyRKoOpE*60gQ`FY}$+)A!LQ
z(Z^=>ZKGlHSX|v|t!>W87yMxmVcN&Tz8f4v(Iuru(ltc-uxLGKHr9Vd{p*x?Jt-%6
z`V+9zYTQYC95dj)$4Artag6*VW|aY!olfNT{zQyGCiJ~uANE!*q4vnHm+$dU2OZWuAW}qqBK+Tg8A*wzKlPf&X^VwoxNf*}UD==ITap&Fo@#R934?
zVY|6v*-o8r05yekNg<{cMBR~`swI^+r&>QcaT9zuB=`Yv2OOj>XBEt4BR5~LjeOoL
zSe9)TifIg1snMsWXhXXvk4Kh!epZpy^B)9BR?n=}WJwCoOpqg_P<@b4%Qp!5OeU&R
e3$Y|x`2kkjgRLTBdA(7(`e~`-F95Sh1n~i@rtH4}

delta 1007
zcmV{v@r6Hyet
zEe`?lt&yl05_RLk1UDw?W=d-%0&O~xj3IxRcBV~S7&zqg-Z^u>^SX~Smti5qB={Wo
z>HrLgrpc@j8T^e2bU+#Kl-J&(05s$_Viax7UfT}(U5-7XMn2NomU%s
zG4Nq2>t%cdBi8mi@AN?5_Mt;zFEHb->$o}GM-!U{9UphHvg^d#
zd%K|}Lmd;~{f(BTw}AuV`rw{<3?|Xgy(j#oG@r8;jh9wwxmsSXTIEuuYE@Uu1#Vot
zii#l(kZ&%qev~=3KKaop*;#a4U-f_dLy{J)w6G0Z5`sYo^Qp!vcm2)cftd%T#C7zz
zyFPe;Sd|BCl_4eT=B>(4J#?%@^ONLmXnRD#t_#OwRj#q^*WJLb@X%?p%X-1Z5ZM&}
z%Hi50mXqsXZ~4zJg;xI+_f13!A?UkYU2fm~bxRZb(PRm)Y{k9%@P&oz5*U9z%*&0J
zH>!p;ztqLLoF`gPg^yYnWh8LCB0{YdZdz|qO6pJ<`as{=g+FW+~L{@YB_XR6GJiO6Jw$ho==J#hXo=O
z6O^QgDe6sDj6+cC3DUyEE!2!f}R{X
zJZM5%%9T>FVk{UgkTsr|+Xr
zqK~cG+h)_^vADL~Uf-IPFZjbCf^>j~1IIsx!b?hxq-%)uVbOfhYHojs#@A`_dP+|4
z%qL)H)VS03Bxb;QkB_E<`4565t7q0~vLuCPCP*Sus6I%j2CKDCc
dLM(|^et^~XV5^8&UT>7Hep>4I3$sZC@c}C!^!5M%

diff --git a/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb
index 02308bd9d391bb5f40622aa3125e74ff4737ca09..056819bd04d7c6d91d16e38b504c43dd9e8aa65a 100644
GIT binary patch
delta 567
zcmV-70?7UG2k{4xZhuwFN<%RaZMACg0Sc}Z#ic7z5ClKKU6-yew@-_GaohU%aTnt2
zoS7syY138|Yali`b22kIGr5)uIu7wuUg9)i3yizH#JP)D`KCsNZ@P^9!^;c7DYL!_}w5F}FsR4jVR}WV{NrKdf2IIRMt^r4|bfos7hrE{JG={(evPEggzm(GLzN;w~abb|7aC!KQ;
zN+)ncI>8IP$bY|%V?=*!XN_d?c_l`7egI|=(7Q)7t=gD;!tv8kX%j}g>_nO*-=J1o
z&ca$)lN2}Kcsy-)Ym!n~7g`N|!Whc*?;f_37uFWUi`E6avugTo`F7af+BSwG50V_c
zs;-zXS&{>*i}MR2IfLz)K
zq+$dn^e1E^slxuLlwZ0KfaC-`(YQ7Ga+%kGJ6kV%#%OMdS`6-7sjMl#rPkVH;tFqh
zdDb+!jCEtOjddB%Ut(4;KQZv5gC_%kFh9roq2SI8f>9>_p#_7?cRvWN1V3V6G|*d&
zNwI@LpDQmhCb0a9JTf!+*BCRJ{P#h&OE6|ej|vh^{x6u(KvzNL*sw!xZz^XGU$d10
FTmi?<4~PH&

delta 567
zcmV-70?7UG2k{4xZhutCP6IIvEl?J*NFZ?nfjDsBgh1lN2XNyE*U@wVD(IqV%kriC
z4BLBloJl%i5lAIc+T{6-?L0fF*K};-Z)u9tg{?8}>J;ZXVr^p1U~XY{^T$pn8((!#
z{VHqR^_#cHWUXQD{bJJp%%47y`ga4{$pdQ(;zsKN-dQ!hx4b*-Z*3dLkqb$V
z9#vP&mn_MF)kS<-G>s*!Tnb#eTVr{P!z199yB;e<)PD_;i4zerKN33xM7Yq6o+_kB
z4PpQa5J+i7{M*hU>C5_)@O68U@m-6N6Nt&J)1Aw*KHOOy?HgAMBbMs=5}K(jh4z3G
z$2WxWN@Z!v`DW9k8#E3#CzzL*?-=;gL594(2JoMNJ`@2;P#)v}6Xt8^k47?IQecw#
zmSQFY?JI|oEzoo7^JMZr5A^folP5}o?3HLxCFEX~f>wgbJg3I21Y(C=oSh%uf3uYW
FTme`-77+jd

diff --git a/CPLD/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAXII/db/RAM2GS.asm.qmsg
index 6f3b874..473664c 100644
--- a/CPLD/MAXII/db/RAM2GS.asm.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692170598614 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692170598620 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 16 03:23:18 2023 " "Processing started: Wed Aug 16 03:23:18 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692170598620 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1692170598620 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1692170598620 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1692170598890 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1692170598896 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170599005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:23:19 2023 " "Processing ended: Wed Aug 16 03:23:19 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170599005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170599005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170599005 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1692170599005 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692496813370 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692496813386 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 22:00:13 2023 " "Processing started: Sat Aug 19 22:00:13 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692496813386 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1692496813386 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1692496813386 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1692496814729 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1692496815011 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4665 " "Peak virtual memory: 4665 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496817339 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:17 2023 " "Processing ended: Sat Aug 19 22:00:17 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496817339 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496817339 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496817339 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1692496817339 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAXII/db/RAM2GS.asm.rdb
index ae989adc9848498c8b393b87e031f486d4a1682a..646bf051fd4e51601dd2d6b802258480e0539b97 100644
GIT binary patch
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diff --git a/CPLD/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAXII/db/RAM2GS.cmp.cdb
index 28e8d43aa0ce0a14840dfd0529d4e62ee6cf45aa..aa53ff4f5bbaf1a6bbdafa46dee9dd544dfaa006 100644
GIT binary patch
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diff --git a/CPLD/MAXII/db/RAM2GS.cmp.logdb b/CPLD/MAXII/db/RAM2GS.cmp.logdb
index 626799f..d45424f 100644
--- a/CPLD/MAXII/db/RAM2GS.cmp.logdb
+++ b/CPLD/MAXII/db/RAM2GS.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/CPLD/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAXII/db/RAM2GS.cmp.rdb
index 1d1811382b73bfc6af6dd5fef35b9a9327089bd6..e41904959210725e69ced4ba9156ea33af75948d 100644
GIT binary patch
delta 13590
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diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info
index a50bbdd..8af81af 100644
--- a/CPLD/MAXII/db/RAM2GS.db_info
+++ b/CPLD/MAXII/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Version_Index = 503488000
-Creation_Time = Wed Aug 16 05:07:32 2023
+Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Version_Index = 503488000
+Creation_Time = Sat Aug 19 21:57:06 2023
diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg
index de65bdd..5aebef0 100644
--- a/CPLD/MAXII/db/RAM2GS.fit.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg
@@ -1,43 +1,43 @@
-{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1692170596213 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1692170596216 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692170596253 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692170596253 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1692170596305 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1692170596315 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170596447 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170596447 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170596447 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170596447 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170596447 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1692170596447 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS.sdc " "Reading SDC File: '../RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692170596516 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS-MAX.sdc " "Reading SDC File: '../RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692170596518 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1692170596522 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        ARCLK " " 200.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        DRCLK " " 200.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCCAS " " 350.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCRAS " " 350.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000         PHI2 " " 350.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  16.000         RCLK " "  16.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170596522 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1692170596522 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692170596527 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692170596527 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692170596530 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RD~16 " "Destination \"RD~16\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170596537 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692170596537 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1692170596540 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1692170596557 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1692170596585 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1692170596586 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1692170596586 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1692170596586 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170596634 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1692170596637 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1692170596740 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170596867 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1692170596869 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1692170597241 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170597241 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1692170597262 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1692170597408 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1692170597408 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1692170597493 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1692170597493 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170597494 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1692170597504 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170597512 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1692170597570 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170597599 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:23:17 2023 " "Processing ended: Wed Aug 16 03:23:17 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170597599 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170597599 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170597599 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1692170597599 ""}
+{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1692496796355 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1692496796386 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692496796417 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692496796417 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1692496796855 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1692496796870 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1692496797323 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692496797448 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692496797589 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1692496797714 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        ARCLK " " 200.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        DRCLK " " 200.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCCAS " " 350.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCRAS " " 350.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000         PHI2 " " 350.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  16.000         RCLK " "  16.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1692496797714 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 41 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797745 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 8 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 22 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797792 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797792 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797792 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 342 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797808 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 18 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797808 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RD~16 " "Destination \"RD~16\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797808 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 16 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797808 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797808 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 341 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797808 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692496797823 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1692496797823 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1692496797870 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496798011 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1692496798370 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1692496798667 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496798854 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1692496798870 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1692496799276 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496799276 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1692496799323 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1692496799495 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1692496799495 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1692496800073 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1692496800073 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496800073 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1692496800105 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496800120 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1692496800917 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496803339 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:03 2023 " "Processing ended: Sat Aug 19 22:00:03 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496803339 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496803339 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496803339 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1692496803339 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info
index dfffd8a..1d5ce26 100644
--- a/CPLD/MAXII/db/RAM2GS.hier_info
+++ b/CPLD/MAXII/db/RAM2GS.hier_info
@@ -1,285 +1,285 @@
-|RAM2GS
-PHI2 => Bank[0].CLK
-PHI2 => Bank[1].CLK
-PHI2 => Bank[2].CLK
-PHI2 => Bank[3].CLK
-PHI2 => Bank[4].CLK
-PHI2 => Bank[5].CLK
-PHI2 => Bank[6].CLK
-PHI2 => Bank[7].CLK
-PHI2 => RA11.CLK
-PHI2 => PHI2r.DATAIN
-PHI2 => CmdDRDIn.CLK
-PHI2 => CmdDRCLK.CLK
-PHI2 => CmdUFMPrgm.CLK
-PHI2 => CmdUFMErase.CLK
-PHI2 => CmdSubmitted.CLK
-PHI2 => Cmdn8MEGEN.CLK
-PHI2 => CmdLEDEN.CLK
-PHI2 => XOR8MEG.CLK
-PHI2 => ADSubmitted.CLK
-PHI2 => C1Submitted.CLK
-PHI2 => UFMOscEN.CLK
-PHI2 => CmdEnable.CLK
-MAin[0] => RA.DATAA
-MAin[0] => RowA.DATAB
-MAin[0] => Equal0.IN7
-MAin[0] => Equal1.IN7
-MAin[0] => Equal3.IN6
-MAin[1] => RA.DATAA
-MAin[1] => RowA.DATAB
-MAin[1] => Equal0.IN6
-MAin[1] => Equal1.IN6
-MAin[1] => Equal3.IN7
-MAin[2] => RA.DATAA
-MAin[2] => RowA.DATAB
-MAin[2] => Equal0.IN5
-MAin[2] => Equal1.IN5
-MAin[2] => Equal3.IN5
-MAin[3] => RA.DATAA
-MAin[3] => RowA.DATAB
-MAin[3] => Equal0.IN4
-MAin[3] => Equal1.IN4
-MAin[3] => Equal3.IN4
-MAin[4] => RA.DATAA
-MAin[4] => RowA.DATAB
-MAin[4] => Equal0.IN3
-MAin[4] => Equal1.IN3
-MAin[4] => Equal3.IN3
-MAin[5] => RA.DATAA
-MAin[5] => RowA.DATAB
-MAin[5] => Equal0.IN2
-MAin[5] => Equal1.IN2
-MAin[5] => Equal3.IN2
-MAin[6] => RA.DATAA
-MAin[6] => RowA.DATAB
-MAin[6] => Equal0.IN1
-MAin[6] => Equal1.IN1
-MAin[6] => Equal3.IN1
-MAin[7] => RA.DATAA
-MAin[7] => RowA.DATAB
-MAin[7] => Equal0.IN0
-MAin[7] => Equal1.IN0
-MAin[7] => Equal3.IN0
-MAin[8] => RA.DATAA
-MAin[8] => RowA.DATAB
-MAin[9] => RA.DATAA
-MAin[9] => RDQMH.DATAA
-MAin[9] => RowA.DATAB
-MAin[9] => RDQML.DATAA
-CROW[0] => RBA.DATAB
-CROW[1] => RBA.DATAB
-Din[0] => XOR8MEG.IN1
-Din[0] => CmdDRDIn.DATAB
-Din[0] => WRD[0].DATAIN
-Din[0] => Bank[0].DATAIN
-Din[0] => Equal14.IN2
-Din[0] => Equal15.IN4
-Din[0] => Cmdn8MEGEN.DATAB
-Din[1] => XOR8MEG.IN1
-Din[1] => CmdDRCLK.DATAB
-Din[1] => CmdLEDEN.DATAB
-Din[1] => WRD[1].DATAIN
-Din[1] => Bank[1].DATAIN
-Din[1] => Equal14.IN7
-Din[1] => Equal15.IN7
-Din[2] => CmdUFMPrgm.DATAB
-Din[2] => WRD[2].DATAIN
-Din[2] => Bank[2].DATAIN
-Din[2] => Equal14.IN6
-Din[2] => Equal15.IN3
-Din[2] => Equal16.IN1
-Din[3] => CmdUFMErase.DATAB
-Din[3] => WRD[3].DATAIN
-Din[3] => Bank[3].DATAIN
-Din[3] => Equal14.IN5
-Din[3] => Equal15.IN2
-Din[3] => Equal16.IN0
-Din[4] => WRD[4].DATAIN
-Din[4] => Bank[4].DATAIN
-Din[4] => Equal14.IN4
-Din[4] => Equal15.IN6
-Din[4] => Equal17.IN3
-Din[4] => Equal18.IN0
-Din[4] => Equal19.IN3
-Din[5] => WRD[5].DATAIN
-Din[5] => Bank[5].DATAIN
-Din[5] => Equal14.IN3
-Din[5] => Equal15.IN1
-Din[5] => Equal17.IN2
-Din[5] => Equal18.IN3
-Din[5] => Equal19.IN0
-Din[6] => RA11.IN1
-Din[6] => WRD[6].DATAIN
-Din[6] => Bank[6].DATAIN
-Din[6] => Equal14.IN1
-Din[6] => Equal15.IN5
-Din[6] => Equal17.IN1
-Din[6] => Equal18.IN2
-Din[6] => Equal19.IN2
-Din[7] => WRD[7].DATAIN
-Din[7] => Bank[7].DATAIN
-Din[7] => Equal14.IN0
-Din[7] => Equal15.IN0
-Din[7] => Equal17.IN0
-Din[7] => Equal18.IN1
-Din[7] => Equal19.IN1
-Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
-Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
-Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
-Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
-Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
-Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
-Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
-Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
-nCCAS => WRD[0].CLK
-nCCAS => WRD[1].CLK
-nCCAS => WRD[2].CLK
-nCCAS => WRD[3].CLK
-nCCAS => WRD[4].CLK
-nCCAS => WRD[5].CLK
-nCCAS => WRD[6].CLK
-nCCAS => WRD[7].CLK
-nCCAS => RD.IN0
-nCCAS => CBR.DATAIN
-nCCAS => CASr.DATAIN
-nCRAS => CBR.CLK
-nCRAS => FWEr.CLK
-nCRAS => RowA[0].CLK
-nCRAS => RowA[1].CLK
-nCRAS => RowA[2].CLK
-nCRAS => RowA[3].CLK
-nCRAS => RowA[4].CLK
-nCRAS => RowA[5].CLK
-nCRAS => RowA[6].CLK
-nCRAS => RowA[7].CLK
-nCRAS => RowA[8].CLK
-nCRAS => RowA[9].CLK
-nCRAS => RBA[0]~reg0.CLK
-nCRAS => RBA[1]~reg0.CLK
-nCRAS => LED.IN1
-nCRAS => RASr.DATAIN
-nFWE => RD.IN1
-nFWE => CMDWR.IN1
-nFWE => ADWR.IN1
-nFWE => C1WR.IN1
-nFWE => FWEr.DATAIN
-LED <= LED.DB_MAX_OUTPUT_PORT_TYPE
-RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
-RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
-RD[0] <> RD[0]
-RD[1] <> RD[1]
-RD[2] <> RD[2]
-RD[3] <> RD[3]
-RD[4] <> RD[4]
-RD[5] <> RD[5]
-RD[6] <> RD[6]
-RD[7] <> RD[7]
-nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RCLK => UFMProgram.CLK
-RCLK => UFMErase.CLK
-RCLK => UFMReqErase.CLK
-RCLK => LEDEN.CLK
-RCLK => UFMInitDone.CLK
-RCLK => n8MEGEN.CLK
-RCLK => UFMD.CLK
-RCLK => DRShift.CLK
-RCLK => DRDIn.CLK
-RCLK => DRCLK.CLK
-RCLK => ARShift.CLK
-RCLK => ARCLK.CLK
-RCLK => Ready.CLK
-RCLK => IS[0].CLK
-RCLK => IS[1].CLK
-RCLK => IS[2].CLK
-RCLK => IS[3].CLK
-RCLK => nRowColSel.CLK
-RCLK => RCKEEN.CLK
-RCLK => RA10.CLK
-RCLK => nRWE~reg0.CLK
-RCLK => nRCAS~reg0.CLK
-RCLK => nRRAS~reg0.CLK
-RCLK => nRCS~reg0.CLK
-RCLK => RCKE~reg0.CLK
-RCLK => InitReady.CLK
-RCLK => FS[0].CLK
-RCLK => FS[1].CLK
-RCLK => FS[2].CLK
-RCLK => FS[3].CLK
-RCLK => FS[4].CLK
-RCLK => FS[5].CLK
-RCLK => FS[6].CLK
-RCLK => FS[7].CLK
-RCLK => FS[8].CLK
-RCLK => FS[9].CLK
-RCLK => FS[10].CLK
-RCLK => FS[11].CLK
-RCLK => FS[12].CLK
-RCLK => FS[13].CLK
-RCLK => FS[14].CLK
-RCLK => FS[15].CLK
-RCLK => FS[16].CLK
-RCLK => FS[17].CLK
-RCLK => S[0].CLK
-RCLK => S[1].CLK
-RCLK => CASr3.CLK
-RCLK => CASr2.CLK
-RCLK => CASr.CLK
-RCLK => RASr3.CLK
-RCLK => RASr2.CLK
-RCLK => RASr.CLK
-RCLK => PHI2r3.CLK
-RCLK => PHI2r2.CLK
-RCLK => PHI2r.CLK
-RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE
-RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|RAM2GS|UFM:UFM_inst
-arclk => arclk.IN1
-ardin => ardin.IN1
-arshft => arshft.IN1
-drclk => drclk.IN1
-drdin => drdin.IN1
-drshft => drshft.IN1
-erase => erase.IN1
-oscena => oscena.IN1
-program => program.IN1
-busy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.busy
-drdout <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.drdout
-osc <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.osc
-rtpbusy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.rtpbusy
-
-
-|RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component
-arclk => maxii_ufm_block1.ARCLK
-ardin => maxii_ufm_block1.ARDIN
-arshft => maxii_ufm_block1.ARSHFT
-busy <= maxii_ufm_block1.BUSY
-drclk => maxii_ufm_block1.DRCLK
-drdin => maxii_ufm_block1.DRDIN
-drdout <= maxii_ufm_block1.DRDOUT
-drshft => maxii_ufm_block1.DRSHFT
-erase => maxii_ufm_block1.ERASE
-osc <= maxii_ufm_block1.OSC
-oscena => maxii_ufm_block1.OSCENA
-program => maxii_ufm_block1.PROGRAM
-rtpbusy <= maxii_ufm_block1.BGPBUSY
-
-
+|RAM2GS
+PHI2 => Bank[0].CLK
+PHI2 => Bank[1].CLK
+PHI2 => Bank[2].CLK
+PHI2 => Bank[3].CLK
+PHI2 => Bank[4].CLK
+PHI2 => Bank[5].CLK
+PHI2 => Bank[6].CLK
+PHI2 => Bank[7].CLK
+PHI2 => RA11.CLK
+PHI2 => PHI2r.DATAIN
+PHI2 => CmdDRDIn.CLK
+PHI2 => CmdDRCLK.CLK
+PHI2 => CmdUFMPrgm.CLK
+PHI2 => CmdUFMErase.CLK
+PHI2 => CmdSubmitted.CLK
+PHI2 => Cmdn8MEGEN.CLK
+PHI2 => CmdLEDEN.CLK
+PHI2 => XOR8MEG.CLK
+PHI2 => ADSubmitted.CLK
+PHI2 => C1Submitted.CLK
+PHI2 => UFMOscEN.CLK
+PHI2 => CmdEnable.CLK
+MAin[0] => RA.DATAA
+MAin[0] => RowA.DATAB
+MAin[0] => Equal0.IN7
+MAin[0] => Equal1.IN7
+MAin[0] => Equal3.IN6
+MAin[1] => RA.DATAA
+MAin[1] => RowA.DATAB
+MAin[1] => Equal0.IN6
+MAin[1] => Equal1.IN6
+MAin[1] => Equal3.IN7
+MAin[2] => RA.DATAA
+MAin[2] => RowA.DATAB
+MAin[2] => Equal0.IN5
+MAin[2] => Equal1.IN5
+MAin[2] => Equal3.IN5
+MAin[3] => RA.DATAA
+MAin[3] => RowA.DATAB
+MAin[3] => Equal0.IN4
+MAin[3] => Equal1.IN4
+MAin[3] => Equal3.IN4
+MAin[4] => RA.DATAA
+MAin[4] => RowA.DATAB
+MAin[4] => Equal0.IN3
+MAin[4] => Equal1.IN3
+MAin[4] => Equal3.IN3
+MAin[5] => RA.DATAA
+MAin[5] => RowA.DATAB
+MAin[5] => Equal0.IN2
+MAin[5] => Equal1.IN2
+MAin[5] => Equal3.IN2
+MAin[6] => RA.DATAA
+MAin[6] => RowA.DATAB
+MAin[6] => Equal0.IN1
+MAin[6] => Equal1.IN1
+MAin[6] => Equal3.IN1
+MAin[7] => RA.DATAA
+MAin[7] => RowA.DATAB
+MAin[7] => Equal0.IN0
+MAin[7] => Equal1.IN0
+MAin[7] => Equal3.IN0
+MAin[8] => RA.DATAA
+MAin[8] => RowA.DATAB
+MAin[9] => RA.DATAA
+MAin[9] => RDQMH.DATAA
+MAin[9] => RowA.DATAB
+MAin[9] => RDQML.DATAA
+CROW[0] => RBA.DATAB
+CROW[1] => RBA.DATAB
+Din[0] => XOR8MEG.IN1
+Din[0] => CmdDRDIn.DATAB
+Din[0] => WRD[0].DATAIN
+Din[0] => Bank[0].DATAIN
+Din[0] => Equal14.IN2
+Din[0] => Equal15.IN4
+Din[0] => Cmdn8MEGEN.DATAB
+Din[1] => XOR8MEG.IN1
+Din[1] => CmdDRCLK.DATAB
+Din[1] => CmdLEDEN.DATAB
+Din[1] => WRD[1].DATAIN
+Din[1] => Bank[1].DATAIN
+Din[1] => Equal14.IN7
+Din[1] => Equal15.IN7
+Din[2] => CmdUFMPrgm.DATAB
+Din[2] => WRD[2].DATAIN
+Din[2] => Bank[2].DATAIN
+Din[2] => Equal14.IN6
+Din[2] => Equal15.IN3
+Din[2] => Equal16.IN1
+Din[3] => CmdUFMErase.DATAB
+Din[3] => WRD[3].DATAIN
+Din[3] => Bank[3].DATAIN
+Din[3] => Equal14.IN5
+Din[3] => Equal15.IN2
+Din[3] => Equal16.IN0
+Din[4] => WRD[4].DATAIN
+Din[4] => Bank[4].DATAIN
+Din[4] => Equal14.IN4
+Din[4] => Equal15.IN6
+Din[4] => Equal17.IN3
+Din[4] => Equal18.IN0
+Din[4] => Equal19.IN3
+Din[5] => WRD[5].DATAIN
+Din[5] => Bank[5].DATAIN
+Din[5] => Equal14.IN3
+Din[5] => Equal15.IN1
+Din[5] => Equal17.IN2
+Din[5] => Equal18.IN3
+Din[5] => Equal19.IN0
+Din[6] => RA11.IN1
+Din[6] => WRD[6].DATAIN
+Din[6] => Bank[6].DATAIN
+Din[6] => Equal14.IN1
+Din[6] => Equal15.IN5
+Din[6] => Equal17.IN1
+Din[6] => Equal18.IN2
+Din[6] => Equal19.IN2
+Din[7] => WRD[7].DATAIN
+Din[7] => Bank[7].DATAIN
+Din[7] => Equal14.IN0
+Din[7] => Equal15.IN0
+Din[7] => Equal17.IN0
+Din[7] => Equal18.IN1
+Din[7] => Equal19.IN1
+Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
+Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
+Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
+Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
+Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
+Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
+Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
+Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
+nCCAS => WRD[0].CLK
+nCCAS => WRD[1].CLK
+nCCAS => WRD[2].CLK
+nCCAS => WRD[3].CLK
+nCCAS => WRD[4].CLK
+nCCAS => WRD[5].CLK
+nCCAS => WRD[6].CLK
+nCCAS => WRD[7].CLK
+nCCAS => RD.IN0
+nCCAS => CBR.DATAIN
+nCCAS => CASr.DATAIN
+nCRAS => CBR.CLK
+nCRAS => FWEr.CLK
+nCRAS => RowA[0].CLK
+nCRAS => RowA[1].CLK
+nCRAS => RowA[2].CLK
+nCRAS => RowA[3].CLK
+nCRAS => RowA[4].CLK
+nCRAS => RowA[5].CLK
+nCRAS => RowA[6].CLK
+nCRAS => RowA[7].CLK
+nCRAS => RowA[8].CLK
+nCRAS => RowA[9].CLK
+nCRAS => RBA[0]~reg0.CLK
+nCRAS => RBA[1]~reg0.CLK
+nCRAS => LED.IN1
+nCRAS => RASr.DATAIN
+nFWE => RD.IN1
+nFWE => CMDWR.IN1
+nFWE => ADWR.IN1
+nFWE => C1WR.IN1
+nFWE => FWEr.DATAIN
+LED <= LED.DB_MAX_OUTPUT_PORT_TYPE
+RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
+RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
+RD[0] <> RD[0]
+RD[1] <> RD[1]
+RD[2] <> RD[2]
+RD[3] <> RD[3]
+RD[4] <> RD[4]
+RD[5] <> RD[5]
+RD[6] <> RD[6]
+RD[7] <> RD[7]
+nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RCLK => UFMProgram.CLK
+RCLK => UFMErase.CLK
+RCLK => UFMReqErase.CLK
+RCLK => LEDEN.CLK
+RCLK => UFMInitDone.CLK
+RCLK => n8MEGEN.CLK
+RCLK => UFMD.CLK
+RCLK => DRShift.CLK
+RCLK => DRDIn.CLK
+RCLK => DRCLK.CLK
+RCLK => ARShift.CLK
+RCLK => ARCLK.CLK
+RCLK => Ready.CLK
+RCLK => IS[0].CLK
+RCLK => IS[1].CLK
+RCLK => IS[2].CLK
+RCLK => IS[3].CLK
+RCLK => nRowColSel.CLK
+RCLK => RCKEEN.CLK
+RCLK => RA10.CLK
+RCLK => nRWE~reg0.CLK
+RCLK => nRCAS~reg0.CLK
+RCLK => nRRAS~reg0.CLK
+RCLK => nRCS~reg0.CLK
+RCLK => RCKE~reg0.CLK
+RCLK => InitReady.CLK
+RCLK => FS[0].CLK
+RCLK => FS[1].CLK
+RCLK => FS[2].CLK
+RCLK => FS[3].CLK
+RCLK => FS[4].CLK
+RCLK => FS[5].CLK
+RCLK => FS[6].CLK
+RCLK => FS[7].CLK
+RCLK => FS[8].CLK
+RCLK => FS[9].CLK
+RCLK => FS[10].CLK
+RCLK => FS[11].CLK
+RCLK => FS[12].CLK
+RCLK => FS[13].CLK
+RCLK => FS[14].CLK
+RCLK => FS[15].CLK
+RCLK => FS[16].CLK
+RCLK => FS[17].CLK
+RCLK => S[0].CLK
+RCLK => S[1].CLK
+RCLK => CASr3.CLK
+RCLK => CASr2.CLK
+RCLK => CASr.CLK
+RCLK => RASr3.CLK
+RCLK => RASr2.CLK
+RCLK => RASr.CLK
+RCLK => PHI2r3.CLK
+RCLK => PHI2r2.CLK
+RCLK => PHI2r.CLK
+RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE
+RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|RAM2GS|UFM:UFM_inst
+arclk => arclk.IN1
+ardin => ardin.IN1
+arshft => arshft.IN1
+drclk => drclk.IN1
+drdin => drdin.IN1
+drshft => drshft.IN1
+erase => erase.IN1
+oscena => oscena.IN1
+program => program.IN1
+busy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.busy
+drdout <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.drdout
+osc <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.osc
+rtpbusy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.rtpbusy
+
+
+|RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component
+arclk => maxii_ufm_block1.ARCLK
+ardin => maxii_ufm_block1.ARDIN
+arshft => maxii_ufm_block1.ARSHFT
+busy <= maxii_ufm_block1.BUSY
+drclk => maxii_ufm_block1.DRCLK
+drdin => maxii_ufm_block1.DRDIN
+drdout <= maxii_ufm_block1.DRDOUT
+drshft => maxii_ufm_block1.DRSHFT
+erase => maxii_ufm_block1.ERASE
+osc <= maxii_ufm_block1.OSC
+oscena => maxii_ufm_block1.OSCENA
+program => maxii_ufm_block1.PROGRAM
+rtpbusy <= maxii_ufm_block1.BGPBUSY
+
+
diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif
index 39ffab31379f4b17e038fd094e44e3b588dc2461..9f5433ac90e74fc2ec5848af8c549a8dd77d316c 100644
GIT binary patch
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diff --git a/CPLD/MAXII/db/RAM2GS.lpc.html b/CPLD/MAXII/db/RAM2GS.lpc.html
index f7c4e12..68ca49f 100644
--- a/CPLD/MAXII/db/RAM2GS.lpc.html
+++ b/CPLD/MAXII/db/RAM2GS.lpc.html
@@ -1,50 +1,50 @@
-
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_unv_component9000400000000
    UFM_inst9404444400000
    
+
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_unv_component9000400000000
    UFM_inst9404444400000
    
diff --git a/CPLD/MAXII/db/RAM2GS.lpc.txt b/CPLD/MAXII/db/RAM2GS.lpc.txt
index e3e31f1..bafdf6b 100644
--- a/CPLD/MAXII/db/RAM2GS.lpc.txt
+++ b/CPLD/MAXII/db/RAM2GS.lpc.txt
@@ -1,8 +1,8 @@
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                                                  ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_unv_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; UFM_inst                               ; 9     ; 4              ; 0            ; 4              ; 4      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                  ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; UFM_inst|UFM_altufm_none_unv_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; UFM_inst                               ; 9     ; 4              ; 0            ; 4              ; 4      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD/MAXII/db/RAM2GS.map.cdb b/CPLD/MAXII/db/RAM2GS.map.cdb
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diff --git a/CPLD/MAXII/db/RAM2GS.map.hdb b/CPLD/MAXII/db/RAM2GS.map.hdb
index 9e555d5849cfb497dba7cc329add034bffdf6fdf..b128f96be8448858f679ca6db09e4f03f711ae5f 100644
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diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb
index 43e076bf186e0906e12233f4ede2a159277fb2c7..75db29cf6b601f8941c74da8b156b57015909c15 100644
GIT binary patch
delta 470
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z1ci*UJzi+jsed$Y8Je3=0!_7Hkx6J~K$wnuQ}^phsHUL0>bm#zp@d2~62`SU8qY9b5u4)g05U;Th%UhL_29D_l~-+87Lc%`y`-H@pFD$G&#V)Nr~cvqk~|0ZX&)b^rhX

delta 470
zcmV;{0V)2+2FC`Fe}5A}(3PTsi`pVB=;{$WXt7O7(hB~pA0ZBiLp>+S&G6btk>a9w
z;q<+C?wtFQW(~s_1J;0P;34C$S?oo2VDQ-Oc9%db2#FPxCvY(c5&irLD?)h2CVcOR
z7yoxC2-ZbR2KWL;NF1?$14oR5AlL_?=LO}-D{Kj=L;8}qAAishauz@REb(VyK%K;U
zfiFe3m%ip;8}I8Gwm?$nyfvaPD>Sa)708mG#3vjx4?
z_6r$id%V!5Q-5yUGBgjN_?k-HB9qWefiNBSrsma?P)$H})p76XLkX4KR8sR)oU}a9
z*qxy7SU8qY>0bgfRUOl1)tek-e-pg({LLsqk?(_9p0get;?%+b@OT|K|s7ea?^P(zV7LNIig-WNvrik|K
z3apqVUH;0a-xEmw1@_kXSG5h2$K0jWG7wDb^ei!~MPH+_eoy?P@^|tZWsG*Csq3A4
M)N!;Mvqk~|0l9DN(*OVf

diff --git a/CPLD/MAXII/db/RAM2GS.smart_action.txt b/CPLD/MAXII/db/RAM2GS.smart_action.txt
index c8e8a13..437a63e 100644
--- a/CPLD/MAXII/db/RAM2GS.smart_action.txt
+++ b/CPLD/MAXII/db/RAM2GS.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/CPLD/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAXII/db/RAM2GS.sta.qmsg
index 22ea0d6..3641928 100644
--- a/CPLD/MAXII/db/RAM2GS.sta.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.sta.qmsg
@@ -1,23 +1,23 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692170600297 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692170600303 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 16 03:23:20 2023 " "Processing started: Wed Aug 16 03:23:20 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692170600303 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1692170600303 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1692170600303 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1692170600413 ""}
-{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1692170600544 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170600588 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170600588 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1692170600638 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1692170600782 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS.sdc " "Reading SDC File: '../RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692170600821 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS-MAX.sdc " "Reading SDC File: '../RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692170600823 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1692170600837 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1692170600856 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1692170600858 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.744 " "Worst-case setup slack is -15.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -15.744             -15.744 DRCLK  " "  -15.744             -15.744 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -15.723             -15.723 ARCLK  " "  -15.723             -15.723 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.153             -69.927 RCLK  " "   -7.153             -69.927 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358               0.000 nCRAS  " "    0.358               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.545               0.000 PHI2  " "    0.545               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600859 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170600859 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.277 " "Worst-case hold slack is -16.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.277             -16.277 ARCLK  " "  -16.277             -16.277 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.276             -16.276 DRCLK  " "  -16.276             -16.276 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.517              -1.433 PHI2  " "   -0.517              -1.433 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 nCRAS  " "    0.177               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.111               0.000 RCLK  " "    1.111               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600870 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170600870 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692170600875 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692170600885 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 7.734 " "Worst-case minimum pulse width slack is 7.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.734               0.000 RCLK  " "    7.734               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 ARCLK  " "   70.000               0.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 DRCLK  " "   70.000               0.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 PHI2  " "  174.734               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 nCCAS  " "  174.734               0.000 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 nCRAS  " "  174.734               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170600888 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170600888 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1692170600956 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692170600976 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692170600977 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170601040 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:23:21 2023 " "Processing ended: Wed Aug 16 03:23:21 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170601040 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170601040 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170601040 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1692170601040 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692496820839 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692496820855 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 22:00:20 2023 " "Processing started: Sat Aug 19 22:00:20 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692496820855 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1692496820855 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1692496820855 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1692496821026 ""}
+{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1692496821917 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496821948 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496821948 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1692496822027 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1692496822151 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692496823855 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692496824151 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1692496824589 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1692496825730 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1692496825730 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.744 " "Worst-case setup slack is -15.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -15.744             -15.744 DRCLK  " "  -15.744             -15.744 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -15.723             -15.723 ARCLK  " "  -15.723             -15.723 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.153             -69.927 RCLK  " "   -7.153             -69.927 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358               0.000 nCRAS  " "    0.358               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.545               0.000 PHI2  " "    0.545               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496825980 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496825980 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.277 " "Worst-case hold slack is -16.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.277             -16.277 ARCLK  " "  -16.277             -16.277 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.276             -16.276 DRCLK  " "  -16.276             -16.276 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.517              -1.433 PHI2  " "   -0.517              -1.433 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 nCRAS  " "    0.177               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.111               0.000 RCLK  " "    1.111               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496826401 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496826401 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692496826667 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692496826995 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 7.734 " "Worst-case minimum pulse width slack is 7.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.734               0.000 RCLK  " "    7.734               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 ARCLK  " "   70.000               0.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 DRCLK  " "   70.000               0.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 PHI2  " "  174.734               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 nCCAS  " "  174.734               0.000 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.734               0.000 nCRAS  " "  174.734               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496827261 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496827261 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1692496830355 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692496831214 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692496831230 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4678 " "Peak virtual memory: 4678 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496833730 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:33 2023 " "Processing ended: Sat Aug 19 22:00:33 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496833730 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496833730 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496833730 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1692496833730 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAXII/db/RAM2GS.sta.rdb
index 483082dc75111dffbb3ef4c3db47a650507c538b..de798c530c7849c77661611b5707fb8d03f44e10 100644
GIT binary patch
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diff --git a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb
index a486dfafe5807d1ede06352a0525c695d8b32a75..fede3efc9d60518dd886381d444a60bc7a8fb7be 100644
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diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt
index 8461117..4020328 100644
--- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt
@@ -1,91 +1,91 @@
-Assembler report for RAM2GS
-Wed Aug 16 03:23:18 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Aug 16 03:23:18 2023 ;
-; Revision Name         ; RAM2GS                                ;
-; Top-level Entity Name ; RAM2GS                                ;
-; Family                ; MAX II                                ;
-; Device                ; EPM240T100C5                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+------------------------------------------------------------------------+
-; Assembler Generated Files                                              ;
-+------------------------------------------------------------------------+
-; File Name                                                              ;
-+------------------------------------------------------------------------+
-; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
-+------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
-+----------------+---------------------------------------------------------------------------------+
-; Option         ; Setting                                                                         ;
-+----------------+---------------------------------------------------------------------------------+
-; JTAG usercode  ; 0x00172E3B                                                                      ;
-; Checksum       ; 0x0017312B                                                                      ;
-+----------------+---------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:23:18 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 4663 megabytes
-    Info: Processing ended: Wed Aug 16 03:23:19 2023
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:00
-
-
+Assembler report for RAM2GS
+Sat Aug 19 22:00:16 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sat Aug 19 22:00:16 2023 ;
+; Revision Name         ; RAM2GS                                ;
+; Top-level Entity Name ; RAM2GS                                ;
+; Family                ; MAX II                                ;
+; Device                ; EPM240T100C5                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------------------------+
+; Assembler Generated Files                                 ;
++-----------------------------------------------------------+
+; File Name                                                 ;
++-----------------------------------------------------------+
+; //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
++-----------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------+
+; Assembler Device Options: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
++----------------+--------------------------------------------------------------------+
+; Option         ; Setting                                                            ;
++----------------+--------------------------------------------------------------------+
+; JTAG usercode  ; 0x00172E3B                                                         ;
+; Checksum       ; 0x0017312B                                                         ;
++----------------+--------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 22:00:13 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4665 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:17 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done
index c11d9e5..8bb0f2f 100644
--- a/CPLD/MAXII/output_files/RAM2GS.done
+++ b/CPLD/MAXII/output_files/RAM2GS.done
@@ -1 +1 @@
-Wed Aug 16 03:23:21 2023
+Sat Aug 19 22:00:45 2023
diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt
index 44a1bda..181adba 100644
--- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt
@@ -1,760 +1,760 @@
-Fitter report for RAM2GS
-Wed Aug 16 03:23:17 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Pin-Out File
-  6. Fitter Resource Usage Summary
-  7. Input Pins
-  8. Output Pins
-  9. Bidir Pins
- 10. I/O Bank Usage
- 11. All Package Pins
- 12. Output Pin Default Load For Reported TCO
- 13. Fitter Resource Utilization by Entity
- 14. Delay Chain Summary
- 15. Control Signals
- 16. Global & Other Fast Signals
- 17. Routing Usage Summary
- 18. LAB Logic Elements
- 19. LAB-wide Signals
- 20. LAB Signals Sourced
- 21. LAB Signals Sourced Out
- 22. LAB Distinct Inputs
- 23. Fitter Device Options
- 24. Estimated Delay Added for Hold Timing Summary
- 25. Estimated Delay Added for Hold Timing Details
- 26. Fitter Messages
- 27. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------+
-; Fitter Summary                                                      ;
-+-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Wed Aug 16 03:23:17 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2GS                                      ;
-; Top-level Entity Name ; RAM2GS                                      ;
-; Family                ; MAX II                                      ;
-; Device                ; EPM240T100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 175 / 240 ( 73 % )                          ;
-; Total pins            ; 63 / 80 ( 79 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                      ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option                                                             ; Setting                        ; Default Value                  ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                             ; EPM240T100C5                   ;                                ;
-; Maximum processors allowed for parallel compilation                ; 4                              ;                                ;
-; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
-; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
-; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
-; Use smart compilation                                              ; Off                            ; Off                            ;
-; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
-; Enable compact report table                                        ; Off                            ; Off                            ;
-; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
-; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
-; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
-; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
-; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
-; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
-; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
-; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
-; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
-; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
-; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
-; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
-; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
-; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
-; Slow Slew Rate                                                     ; Off                            ; Off                            ;
-; PCI I/O                                                            ; Off                            ; Off                            ;
-; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
-; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
-; Auto Delay Chains                                                  ; On                             ; On                             ;
-; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
-; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
-; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
-; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
-; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
-; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
-; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
-; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
-; Auto Global Clock                                                  ; On                             ; On                             ;
-; Auto Global Register Control Signals                               ; On                             ; On                             ;
-; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.04        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.6%      ;
-;     Processors 3-4         ;   1.3%      ;
-+----------------------------+-------------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                       ;
-+---------------------------------------------+-----------------------+
-; Resource                                    ; Usage                 ;
-+---------------------------------------------+-----------------------+
-; Total logic elements                        ; 175 / 240 ( 73 % )    ;
-;     -- Combinational with no register       ; 77                    ;
-;     -- Register only                        ; 21                    ;
-;     -- Combinational with a register        ; 77                    ;
-;                                             ;                       ;
-; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 57                    ;
-;     -- 3 input functions                    ; 46                    ;
-;     -- 2 input functions                    ; 42                    ;
-;     -- 1 input functions                    ; 8                     ;
-;     -- 0 input functions                    ; 1                     ;
-;                                             ;                       ;
-; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 159                   ;
-;     -- arithmetic mode                      ; 16                    ;
-;     -- qfbk mode                            ; 8                     ;
-;     -- register cascade mode                ; 0                     ;
-;     -- synchronous clear/load mode          ; 27                    ;
-;     -- asynchronous clear/load mode         ; 0                     ;
-;                                             ;                       ;
-; Total registers                             ; 98 / 240 ( 41 % )     ;
-; Total LABs                                  ; 21 / 24 ( 88 % )      ;
-; Logic elements in carry chains              ; 17                    ;
-; Virtual pins                                ; 0                     ;
-; I/O pins                                    ; 63 / 80 ( 79 % )      ;
-;     -- Clock pins                           ; 2 / 4 ( 50 % )        ;
-;                                             ;                       ;
-; UFM blocks                                  ; 1 / 1 ( 100 % )       ;
-;                                             ;                       ;
-;     -- Total Fixed Point DSP Blocks         ; 0                     ;
-;     -- Total Floating Point DSP Blocks      ; 0                     ;
-;                                             ;                       ;
-; Global signals                              ; 4                     ;
-;     -- Global clocks                        ; 4 / 4 ( 100 % )       ;
-; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 19.4% / 20.4% / 18.3% ;
-; Peak interconnect usage (total/H/V)         ; 19.4% / 20.4% / 18.3% ;
-; Maximum fan-out                             ; 55                    ;
-; Highest non-global fan-out                  ; 41                    ;
-; Total fan-out                               ; 661                   ;
-; Average fan-out                             ; 2.77                  ;
-+---------------------------------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                      ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 22                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage                                              ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 25 / 42 ( 60 % )  ; 3.3V          ; --           ;
-+----------+-------------------+---------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                               ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; 1        ; 83         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 10       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 11       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 13       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 25       ; 19         ; 1        ; #TDO           ; output ;              ;           ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 32       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 46       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 58       ; 48         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 60       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 61       ; 49         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 62       ; 50         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 63       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 64       ; 51         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 65       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 75       ; 61         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 76       ; 62         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 77       ; 63         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 78       ; 64         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 79       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 81       ; 65         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 82       ; 66         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 83       ; 67         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 84       ; 68         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 85       ; 69         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 86       ; 70         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 87       ; 71         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 88       ; 72         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 93       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO                    ;
-+----------------------------+-------+------------------------+
-; I/O Standard               ; Load  ; Termination Resistance ;
-+----------------------------+-------+------------------------+
-; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
-; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
-; 2.5 V                      ; 10 pF ; Not Available          ;
-; 1.8 V                      ; 10 pF ; Not Available          ;
-; 1.5 V                      ; 10 pF ; Not Available          ;
-; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-+----------------------------+-------+------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                        ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS                                                   ; 175 (175)   ; 98           ; 1          ; 63   ; 0            ; 77 (77)      ; 21 (21)           ; 77 (77)          ; 17 (17)         ; 8 (8)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; LED     ; Output   ; --            ;
-; RBA[0]  ; Output   ; --            ;
-; RBA[1]  ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; nRCS    ; Output   ; --            ;
-; RCKE    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; nRRAS   ; Output   ; --            ;
-; nRCAS   ; Output   ; --            ;
-; RDQMH   ; Output   ; --            ;
-; RDQML   ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-; nCRAS   ; Input    ; (0)           ;
-; MAin[0] ; Input    ; (0)           ;
-; MAin[1] ; Input    ; (0)           ;
-; MAin[2] ; Input    ; (0)           ;
-; MAin[3] ; Input    ; (0)           ;
-; MAin[4] ; Input    ; (0)           ;
-; MAin[5] ; Input    ; (0)           ;
-; MAin[6] ; Input    ; (0)           ;
-; MAin[7] ; Input    ; (0)           ;
-; MAin[8] ; Input    ; (0)           ;
-; MAin[9] ; Input    ; (0)           ;
-; RCLK    ; Input    ; (0)           ;
-; nCCAS   ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; CROW[1] ; Input    ; (1)           ;
-; PHI2    ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (1)           ;
-; nFWE    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (1)           ;
-; Din[7]  ; Input    ; (1)           ;
-; Din[1]  ; Input    ; (1)           ;
-; Din[4]  ; Input    ; (1)           ;
-; Din[2]  ; Input    ; (1)           ;
-; Din[3]  ; Input    ; (1)           ;
-; Din[5]  ; Input    ; (1)           ;
-+---------+----------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                 ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name       ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1 ; LC_X4_Y1_N0 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdLEDEN~1 ; LC_X4_Y1_N8 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1    ; LC_X3_Y1_N4 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; PHI2       ; PIN_52      ; 22      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-; RCLK       ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; RD~16      ; LC_X3_Y4_N0 ; 8       ; Output enable           ; no     ; --                   ; --               ;
-; Ready      ; LC_X3_Y2_N8 ; 40      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~6  ; LC_X4_Y2_N7 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; nCCAS      ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
-; nCRAS      ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-
-
-+----------------------------------------------------------------------+
-; Global & Other Fast Signals                                          ;
-+-------+----------+---------+----------------------+------------------+
-; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
-+-------+----------+---------+----------------------+------------------+
-; PHI2  ; PIN_52   ; 22      ; Global Clock         ; GCLK3            ;
-; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
-; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK1            ;
-; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK2            ;
-+-------+----------+---------+----------------------+------------------+
-
-
-+--------------------------------------------+
-; Routing Usage Summary                      ;
-+-----------------------+--------------------+
-; Routing Resource Type ; Usage              ;
-+-----------------------+--------------------+
-; C4s                   ; 120 / 784 ( 15 % ) ;
-; Direct links          ; 34 / 888 ( 4 % )   ;
-; Global clocks         ; 4 / 4 ( 100 % )    ;
-; LAB clocks            ; 12 / 32 ( 38 % )   ;
-; LUT chains            ; 11 / 216 ( 5 % )   ;
-; Local interconnects   ; 232 / 888 ( 26 % ) ;
-; R4s                   ; 117 / 704 ( 17 % ) ;
-+-----------------------+--------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 8.33) ; Number of LABs  (Total = 21) ;
-+--------------------------------------------+------------------------------+
-; 1                                          ; 0                            ;
-; 2                                          ; 3                            ;
-; 3                                          ; 0                            ;
-; 4                                          ; 0                            ;
-; 5                                          ; 1                            ;
-; 6                                          ; 0                            ;
-; 7                                          ; 2                            ;
-; 8                                          ; 0                            ;
-; 9                                          ; 0                            ;
-; 10                                         ; 15                           ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals                                                  ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.24) ; Number of LABs  (Total = 21) ;
-+------------------------------------+------------------------------+
-; 1 Clock                            ; 12                           ;
-; 1 Clock enable                     ; 3                            ;
-; 1 Sync. clear                      ; 3                            ;
-; 2 Clocks                           ; 8                            ;
-+------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 8.57) ; Number of LABs  (Total = 21) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 0                            ;
-; 2                                           ; 3                            ;
-; 3                                           ; 0                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 1                            ;
-; 6                                           ; 0                            ;
-; 7                                           ; 2                            ;
-; 8                                           ; 0                            ;
-; 9                                           ; 0                            ;
-; 10                                          ; 12                           ;
-; 11                                          ; 1                            ;
-; 12                                          ; 2                            ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.62) ; Number of LABs  (Total = 21) ;
-+-------------------------------------------------+------------------------------+
-; 0                                               ; 0                            ;
-; 1                                               ; 1                            ;
-; 2                                               ; 2                            ;
-; 3                                               ; 1                            ;
-; 4                                               ; 2                            ;
-; 5                                               ; 2                            ;
-; 6                                               ; 5                            ;
-; 7                                               ; 5                            ;
-; 8                                               ; 2                            ;
-; 9                                               ; 0                            ;
-; 10                                              ; 0                            ;
-; 11                                              ; 1                            ;
-+-------------------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 9.43) ; Number of LABs  (Total = 21) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 0                            ;
-; 2                                           ; 2                            ;
-; 3                                           ; 1                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 1                            ;
-; 6                                           ; 2                            ;
-; 7                                           ; 0                            ;
-; 8                                           ; 2                            ;
-; 9                                           ; 2                            ;
-; 10                                          ; 2                            ;
-; 11                                          ; 2                            ;
-; 12                                          ; 3                            ;
-; 13                                          ; 2                            ;
-; 14                                          ; 0                            ;
-; 15                                          ; 0                            ;
-; 16                                          ; 0                            ;
-; 17                                          ; 1                            ;
-; 18                                          ; 0                            ;
-; 19                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Fitter Device Options                                                   ;
-+----------------------------------------------+--------------------------+
-; Option                                       ; Setting                  ;
-+----------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
-; Enable device-wide output enable (DEV_OE)    ; Off                      ;
-; Enable INIT_DONE output                      ; Off                      ;
-; Configuration scheme                         ; Passive Serial           ;
-; Reserve all unused pins                      ; As output driving ground ;
-+----------------------------------------------+--------------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary              ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; I/O             ; RCLK                 ; 4.0               ;
-; I/O             ; nCRAS                ; 3.0               ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details              ;
-+-----------------+----------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; nCCAS           ; CBR                  ; 3.041             ;
-; PHI2            ; PHI2r                ; 1.523             ;
-; nCRAS           ; RASr                 ; 1.214             ;
-+-----------------+----------------------+-------------------+
-Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (119006): Selected device EPM240T100C5 for design "RAM2GS"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EPM240T100I5 is compatible
-    Info (176445): Device EPM240T100A5 is compatible
-    Info (176445): Device EPM570T100C5 is compatible
-    Info (176445): Device EPM570T100I5 is compatible
-    Info (176445): Device EPM570T100A5 is compatible
-Info (332104): Reading SDC File: '../RAM2GS.sdc'
-Info (332104): Reading SDC File: '../RAM2GS-MAX.sdc'
-Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
-Info (332111): Found 6 clocks
-    Info (332111):   Period   Clock Name
-    Info (332111): ======== ============
-    Info (332111):  200.000        ARCLK
-    Info (332111):  200.000        DRCLK
-    Info (332111):  350.000        nCCAS
-    Info (332111):  350.000        nCRAS
-    Info (332111):  350.000         PHI2
-    Info (332111):   16.000         RCLK
-Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 40
-Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
-    Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 13
-Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
-Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-    Info (186217): Destination "LED~0" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-    Info (186217): Destination "RASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
-Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-    Info (186217): Destination "CBR" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 17
-    Info (186217): Destination "RD~16" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 59
-    Info (186217): Destination "CASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
-Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-Info (186079): Completed Auto Global Promotion Operation
-Info (176234): Starting register packing
-Info (186468): Started processing fast register assignments
-Info (186469): Finished processing fast register assignments
-Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 17% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 5345 megabytes
-    Info: Processing ended: Wed Aug 16 03:23:17 2023
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg.
-
-
+Fitter report for RAM2GS
+Sat Aug 19 22:00:01 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Pin-Out File
+  6. Fitter Resource Usage Summary
+  7. Input Pins
+  8. Output Pins
+  9. Bidir Pins
+ 10. I/O Bank Usage
+ 11. All Package Pins
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Delay Chain Summary
+ 15. Control Signals
+ 16. Global & Other Fast Signals
+ 17. Routing Usage Summary
+ 18. LAB Logic Elements
+ 19. LAB-wide Signals
+ 20. LAB Signals Sourced
+ 21. LAB Signals Sourced Out
+ 22. LAB Distinct Inputs
+ 23. Fitter Device Options
+ 24. Estimated Delay Added for Hold Timing Summary
+ 25. Estimated Delay Added for Hold Timing Details
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Fitter Summary                                                      ;
++-----------------------+---------------------------------------------+
+; Fitter Status         ; Successful - Sat Aug 19 22:00:00 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; RAM2GS                                      ;
+; Top-level Entity Name ; RAM2GS                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 175 / 240 ( 73 % )                          ;
+; Total pins            ; 63 / 80 ( 79 % )                            ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                             ;
++-----------------------+---------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                      ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option                                                             ; Setting                        ; Default Value                  ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device                                                             ; EPM240T100C5                   ;                                ;
+; Maximum processors allowed for parallel compilation                ; 4                              ;                                ;
+; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
+; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
+; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
+; Use smart compilation                                              ; Off                            ; Off                            ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
+; Enable compact report table                                        ; Off                            ; Off                            ;
+; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
+; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
+; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
+; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
+; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
+; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
+; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
+; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
+; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
+; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
+; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
+; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
+; Slow Slew Rate                                                     ; Off                            ; Off                            ;
+; PCI I/O                                                            ; Off                            ; Off                            ;
+; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
+; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
+; Auto Delay Chains                                                  ; On                             ; On                             ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
+; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
+; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
+; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
+; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
+; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
+; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
+; Auto Global Clock                                                  ; On                             ; On                             ;
+; Auto Global Register Control Signals                               ; On                             ; On                             ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.6%      ;
+;     Processors 3-4         ;   0.4%      ;
++----------------------------+-------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 175 / 240 ( 73 % )    ;
+;     -- Combinational with no register       ; 77                    ;
+;     -- Register only                        ; 21                    ;
+;     -- Combinational with a register        ; 77                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 57                    ;
+;     -- 3 input functions                    ; 46                    ;
+;     -- 2 input functions                    ; 42                    ;
+;     -- 1 input functions                    ; 8                     ;
+;     -- 0 input functions                    ; 1                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 159                   ;
+;     -- arithmetic mode                      ; 16                    ;
+;     -- qfbk mode                            ; 8                     ;
+;     -- register cascade mode                ; 0                     ;
+;     -- synchronous clear/load mode          ; 27                    ;
+;     -- asynchronous clear/load mode         ; 0                     ;
+;                                             ;                       ;
+; Total registers                             ; 98 / 240 ( 41 % )     ;
+; Total LABs                                  ; 21 / 24 ( 88 % )      ;
+; Logic elements in carry chains              ; 17                    ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 63 / 80 ( 79 % )      ;
+;     -- Clock pins                           ; 2 / 4 ( 50 % )        ;
+;                                             ;                       ;
+; UFM blocks                                  ; 1 / 1 ( 100 % )       ;
+;                                             ;                       ;
+;     -- Total Fixed Point DSP Blocks         ; 0                     ;
+;     -- Total Floating Point DSP Blocks      ; 0                     ;
+;                                             ;                       ;
+; Global signals                              ; 4                     ;
+;     -- Global clocks                        ; 4 / 4 ( 100 % )       ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 19.4% / 20.4% / 18.3% ;
+; Peak interconnect usage (total/H/V)         ; 19.4% / 20.4% / 18.3% ;
+; Maximum fan-out                             ; 55                    ;
+; Highest non-global fan-out                  ; 41                    ;
+; Total fan-out                               ; 661                   ;
+; Average fan-out                             ; 2.77                  ;
++---------------------------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                      ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 22                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                               ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage                                              ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
+; 2        ; 25 / 42 ( 60 % )  ; 3.3V          ; --           ;
++----------+-------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                               ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+; 1        ; 83         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 10       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 11       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 13       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
+; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
+; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
+; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
+; 25       ; 19         ; 1        ; #TDO           ; output ;              ;           ; --         ;                 ; --       ; --           ;
+; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 32       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 46       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 58       ; 48         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 60       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 61       ; 49         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 62       ; 50         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 63       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
+; 64       ; 51         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 65       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 66       ; 52         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 75       ; 61         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 76       ; 62         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 77       ; 63         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 78       ; 64         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 79       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 81       ; 65         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 82       ; 66         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 83       ; 67         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 84       ; 68         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 85       ; 69         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 86       ; 70         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 87       ; 71         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
+; 88       ; 72         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 93       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
+; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO                    ;
++----------------------------+-------+------------------------+
+; I/O Standard               ; Load  ; Termination Resistance ;
++----------------------------+-------+------------------------+
+; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
+; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
+; 2.5 V                      ; 10 pF ; Not Available          ;
+; 1.8 V                      ; 10 pF ; Not Available          ;
+; 1.5 V                      ; 10 pF ; Not Available          ;
+; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
++----------------------------+-------+------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                        ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2GS                                                   ; 175 (175)   ; 98           ; 1          ; 63   ; 0            ; 77 (77)      ; 21 (21)           ; 77 (77)          ; 17 (17)         ; 8 (8)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;       |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work         ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------+
+; Delay Chain Summary                ;
++---------+----------+---------------+
+; Name    ; Pin Type ; Pad to Core 0 ;
++---------+----------+---------------+
+; Dout[0] ; Output   ; --            ;
+; Dout[1] ; Output   ; --            ;
+; Dout[2] ; Output   ; --            ;
+; Dout[3] ; Output   ; --            ;
+; Dout[4] ; Output   ; --            ;
+; Dout[5] ; Output   ; --            ;
+; Dout[6] ; Output   ; --            ;
+; Dout[7] ; Output   ; --            ;
+; LED     ; Output   ; --            ;
+; RBA[0]  ; Output   ; --            ;
+; RBA[1]  ; Output   ; --            ;
+; RA[0]   ; Output   ; --            ;
+; RA[1]   ; Output   ; --            ;
+; RA[2]   ; Output   ; --            ;
+; RA[3]   ; Output   ; --            ;
+; RA[4]   ; Output   ; --            ;
+; RA[5]   ; Output   ; --            ;
+; RA[6]   ; Output   ; --            ;
+; RA[7]   ; Output   ; --            ;
+; RA[8]   ; Output   ; --            ;
+; RA[9]   ; Output   ; --            ;
+; RA[10]  ; Output   ; --            ;
+; RA[11]  ; Output   ; --            ;
+; nRCS    ; Output   ; --            ;
+; RCKE    ; Output   ; --            ;
+; nRWE    ; Output   ; --            ;
+; nRRAS   ; Output   ; --            ;
+; nRCAS   ; Output   ; --            ;
+; RDQMH   ; Output   ; --            ;
+; RDQML   ; Output   ; --            ;
+; RD[0]   ; Bidir    ; (0)           ;
+; RD[1]   ; Bidir    ; (0)           ;
+; RD[2]   ; Bidir    ; (0)           ;
+; RD[3]   ; Bidir    ; (0)           ;
+; RD[4]   ; Bidir    ; (0)           ;
+; RD[5]   ; Bidir    ; (0)           ;
+; RD[6]   ; Bidir    ; (0)           ;
+; RD[7]   ; Bidir    ; (0)           ;
+; nCRAS   ; Input    ; (0)           ;
+; MAin[0] ; Input    ; (0)           ;
+; MAin[1] ; Input    ; (0)           ;
+; MAin[2] ; Input    ; (0)           ;
+; MAin[3] ; Input    ; (0)           ;
+; MAin[4] ; Input    ; (0)           ;
+; MAin[5] ; Input    ; (0)           ;
+; MAin[6] ; Input    ; (0)           ;
+; MAin[7] ; Input    ; (0)           ;
+; MAin[8] ; Input    ; (0)           ;
+; MAin[9] ; Input    ; (0)           ;
+; RCLK    ; Input    ; (0)           ;
+; nCCAS   ; Input    ; (0)           ;
+; CROW[0] ; Input    ; (1)           ;
+; CROW[1] ; Input    ; (1)           ;
+; PHI2    ; Input    ; (0)           ;
+; Din[6]  ; Input    ; (1)           ;
+; nFWE    ; Input    ; (1)           ;
+; Din[0]  ; Input    ; (1)           ;
+; Din[7]  ; Input    ; (1)           ;
+; Din[1]  ; Input    ; (1)           ;
+; Din[4]  ; Input    ; (1)           ;
+; Din[2]  ; Input    ; (1)           ;
+; Din[3]  ; Input    ; (1)           ;
+; Din[5]  ; Input    ; (1)           ;
++---------+----------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                 ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; Name       ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; CmdDRDIn~1 ; LC_X4_Y1_N0 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
+; CmdLEDEN~1 ; LC_X4_Y1_N8 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; DRDIn~1    ; LC_X3_Y1_N4 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; PHI2       ; PIN_52      ; 22      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
+; RCLK       ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
+; RD~16      ; LC_X3_Y4_N0 ; 8       ; Output enable           ; no     ; --                   ; --               ;
+; Ready      ; LC_X3_Y2_N8 ; 40      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; always8~6  ; LC_X4_Y2_N7 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; nCCAS      ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
+; nCRAS      ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+
+
++----------------------------------------------------------------------+
+; Global & Other Fast Signals                                          ;
++-------+----------+---------+----------------------+------------------+
+; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++-------+----------+---------+----------------------+------------------+
+; PHI2  ; PIN_52   ; 22      ; Global Clock         ; GCLK3            ;
+; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
+; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK1            ;
+; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK2            ;
++-------+----------+---------+----------------------+------------------+
+
+
++--------------------------------------------+
+; Routing Usage Summary                      ;
++-----------------------+--------------------+
+; Routing Resource Type ; Usage              ;
++-----------------------+--------------------+
+; C4s                   ; 120 / 784 ( 15 % ) ;
+; Direct links          ; 34 / 888 ( 4 % )   ;
+; Global clocks         ; 4 / 4 ( 100 % )    ;
+; LAB clocks            ; 12 / 32 ( 38 % )   ;
+; LUT chains            ; 11 / 216 ( 5 % )   ;
+; Local interconnects   ; 232 / 888 ( 26 % ) ;
+; R4s                   ; 117 / 704 ( 17 % ) ;
++-----------------------+--------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 8.33) ; Number of LABs  (Total = 21) ;
++--------------------------------------------+------------------------------+
+; 1                                          ; 0                            ;
+; 2                                          ; 3                            ;
+; 3                                          ; 0                            ;
+; 4                                          ; 0                            ;
+; 5                                          ; 1                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 2                            ;
+; 8                                          ; 0                            ;
+; 9                                          ; 0                            ;
+; 10                                         ; 15                           ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.24) ; Number of LABs  (Total = 21) ;
++------------------------------------+------------------------------+
+; 1 Clock                            ; 12                           ;
+; 1 Clock enable                     ; 3                            ;
+; 1 Sync. clear                      ; 3                            ;
+; 2 Clocks                           ; 8                            ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 8.57) ; Number of LABs  (Total = 21) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 3                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 1                            ;
+; 6                                           ; 0                            ;
+; 7                                           ; 2                            ;
+; 8                                           ; 0                            ;
+; 9                                           ; 0                            ;
+; 10                                          ; 12                           ;
+; 11                                          ; 1                            ;
+; 12                                          ; 2                            ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 5.62) ; Number of LABs  (Total = 21) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 1                            ;
+; 2                                               ; 2                            ;
+; 3                                               ; 1                            ;
+; 4                                               ; 2                            ;
+; 5                                               ; 2                            ;
+; 6                                               ; 5                            ;
+; 7                                               ; 5                            ;
+; 8                                               ; 2                            ;
+; 9                                               ; 0                            ;
+; 10                                              ; 0                            ;
+; 11                                              ; 1                            ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 9.43) ; Number of LABs  (Total = 21) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 2                            ;
+; 3                                           ; 1                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 1                            ;
+; 6                                           ; 2                            ;
+; 7                                           ; 0                            ;
+; 8                                           ; 2                            ;
+; 9                                           ; 2                            ;
+; 10                                          ; 2                            ;
+; 11                                          ; 2                            ;
+; 12                                          ; 3                            ;
+; 13                                          ; 2                            ;
+; 14                                          ; 0                            ;
+; 15                                          ; 0                            ;
+; 16                                          ; 0                            ;
+; 17                                          ; 1                            ;
+; 18                                          ; 0                            ;
+; 19                                          ; 1                            ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options                                                   ;
++----------------------------------------------+--------------------------+
+; Option                                       ; Setting                  ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
+; Enable device-wide output enable (DEV_OE)    ; Off                      ;
+; Enable INIT_DONE output                      ; Off                      ;
+; Configuration scheme                         ; Passive Serial           ;
+; Reserve all unused pins                      ; As output driving ground ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; I/O             ; RCLK                 ; 4.0               ;
+; I/O             ; nCRAS                ; 3.0               ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details              ;
++-----------------+----------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; nCCAS           ; CBR                  ; 3.041             ;
+; PHI2            ; PHI2r                ; 1.523             ;
+; nCRAS           ; RASr                 ; 1.214             ;
++-----------------+----------------------+-------------------+
+Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (119006): Selected device EPM240T100C5 for design "RAM2GS"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EPM240T100I5 is compatible
+    Info (176445): Device EPM240T100A5 is compatible
+    Info (176445): Device EPM570T100C5 is compatible
+    Info (176445): Device EPM570T100I5 is compatible
+    Info (176445): Device EPM570T100A5 is compatible
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 6 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):  200.000        ARCLK
+    Info (332111):  200.000        DRCLK
+    Info (332111):  350.000        nCCAS
+    Info (332111):  350.000        nCRAS
+    Info (332111):  350.000         PHI2
+    Info (332111):   16.000         RCLK
+Info (186079): Completed User Assigned Global Signals Promotion Operation
+Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
+Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
+    Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
+Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
+Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+    Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
+    Info (186217): Destination "RASr" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
+Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+    Info (186217): Destination "CBR" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
+    Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
+    Info (186217): Destination "CASr" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
+Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+Info (186079): Completed Auto Global Promotion Operation
+Info (176234): Starting register packing
+Info (186468): Started processing fast register assignments
+Info (186469): Finished processing fast register assignments
+Info (176235): Finished register packing
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 17% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds.
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Info (144001): Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 5345 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:03 2023
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:03
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg.
+
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.smsg b/CPLD/MAXII/output_files/RAM2GS.fit.smsg
index 6df10d8..a3cd98a 100644
--- a/CPLD/MAXII/output_files/RAM2GS.fit.smsg
+++ b/CPLD/MAXII/output_files/RAM2GS.fit.smsg
@@ -1,4 +1,4 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176244): Moving registers into LUTs to improve timing and density
-Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176244): Moving registers into LUTs to improve timing and density
+Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary
index 62e1f92..f45499e 100644
--- a/CPLD/MAXII/output_files/RAM2GS.fit.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Wed Aug 16 03:23:17 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX II
-Device : EPM240T100C5
-Timing Models : Final
-Total logic elements : 175 / 240 ( 73 % )
-Total pins : 63 / 80 ( 79 % )
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
+Fitter Status : Successful - Sat Aug 19 22:00:00 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX II
+Device : EPM240T100C5
+Timing Models : Final
+Total logic elements : 175 / 240 ( 73 % )
+Total pins : 63 / 80 ( 79 % )
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt
index 0c6ef6e..2a07f3f 100644
--- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt
@@ -1,118 +1,118 @@
-Flow report for RAM2GS
-Wed Aug 16 03:23:21 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------+
-; Flow Summary                                                        ;
-+-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Wed Aug 16 03:23:18 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2GS                                      ;
-; Top-level Entity Name ; RAM2GS                                      ;
-; Family                ; MAX II                                      ;
-; Device                ; EPM240T100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 175 / 240 ( 73 % )                          ;
-; Total pins            ; 63 / 80 ( 79 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 08/16/2023 03:23:05 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; RAM2GS              ;
-+-------------------+---------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                   ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-; Assignment Name                       ; Value                           ; Default Value ; Entity Name ; Section Id ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID                 ; 207120313862967.169217058515824 ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                ; 85                              ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                ; 0                               ; --            ; --          ; --         ;
-; NUM_PARALLEL_PROCESSORS               ; 4                               ; --            ; --          ; --         ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                            ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air     ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY              ; output_files                    ; --            ; --          ; --         ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                        ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:10     ; 1.0                     ; 4701 MB             ; 00:00:24                           ;
-; Fitter               ; 00:00:02     ; 1.0                     ; 5345 MB             ; 00:00:03                           ;
-; Assembler            ; 00:00:00     ; 1.0                     ; 4662 MB             ; 00:00:00                           ;
-; Timing Analyzer      ; 00:00:01     ; 1.0                     ; 4676 MB             ; 00:00:01                           ;
-; Total                ; 00:00:13     ; --                      ; --                  ; 00:00:28                           ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                    ;
-+----------------------+------------------+------------+------------+----------------+
-; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+----------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Fitter               ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Assembler            ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Timing Analyzer      ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-+----------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_sta RAM2GS-MAXII -c RAM2GS
-
-
-
+Flow report for RAM2GS
+Sat Aug 19 22:00:32 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Flow Summary                                                        ;
++-----------------------+---------------------------------------------+
+; Flow Status           ; Successful - Sat Aug 19 22:00:16 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; RAM2GS                                      ;
+; Top-level Entity Name ; RAM2GS                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 175 / 240 ( 73 % )                          ;
+; Total pins            ; 63 / 80 ( 79 % )                            ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                             ;
++-----------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 08/19/2023 21:59:22 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; RAM2GS              ;
++-------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                   ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name                       ; Value                           ; Default Value ; Entity Name ; Section Id ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID                 ; 207120313862967.169249676205304 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                ; 85                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                ; 0                               ; --            ; --          ; --         ;
+; NUM_PARALLEL_PROCESSORS               ; 4                               ; --            ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                            ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air     ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY              ; output_files                    ; --            ; --          ; --         ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:19     ; 1.0                     ; 4703 MB             ; 00:00:25                           ;
+; Fitter               ; 00:00:06     ; 1.0                     ; 5345 MB             ; 00:00:03                           ;
+; Assembler            ; 00:00:03     ; 1.0                     ; 4664 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:12     ; 1.0                     ; 4678 MB             ; 00:00:01                           ;
+; Total                ; 00:00:40     ; --                      ; --                  ; 00:00:30                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Fitter               ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Assembler            ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Timing Analyzer      ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_sta RAM2GS-MAXII -c RAM2GS
+
+
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.jdi b/CPLD/MAXII/output_files/RAM2GS.jdi
index 4294046..1411d48 100644
--- a/CPLD/MAXII/output_files/RAM2GS.jdi
+++ b/CPLD/MAXII/output_files/RAM2GS.jdi
@@ -1,8 +1,8 @@
-
-  
-    
-  
-  
-    
-  
-
+
+  
+    
+  
+  
+    
+  
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt
index d9b84b4..bc0d881 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt
@@ -1,312 +1,312 @@
-Analysis & Synthesis report for RAM2GS
-Wed Aug 16 03:23:14 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis IP Cores Summary
-  9. General Register Statistics
- 10. Inverted Register Statistics
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
- 13. Analysis & Synthesis Messages
- 14. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                              ;
-+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Aug 16 03:23:14 2023       ;
-; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name               ; RAM2GS                                      ;
-; Top-level Entity Name       ; RAM2GS                                      ;
-; Family                      ; MAX II                                      ;
-; Total logic elements        ; 184                                         ;
-; Total pins                  ; 63                                          ;
-; Total virtual pins          ; 0                                           ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
-+-----------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                              ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                           ; Setting            ; Default Value      ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                           ; EPM240T100C5       ;                    ;
-; Top-level entity name                                            ; RAM2GS             ; RAM2GS             ;
-; Family name                                                      ; MAX II             ; Cyclone V          ;
-; Maximum processors allowed for parallel compilation              ; 4                  ;                    ;
-; Use smart compilation                                            ; Off                ; Off                ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                      ; Off                ; Off                ;
-; Restructure Multiplexers                                         ; Auto               ; Auto               ;
-; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
-; Preserve fewer node names                                        ; On                 ; On                 ;
-; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
-; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                         ; Auto               ; Auto               ;
-; Safe State Machine                                               ; Off                ; Off                ;
-; Extract Verilog State Machines                                   ; On                 ; On                 ;
-; Extract VHDL State Machines                                      ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
-; Parallel Synthesis                                               ; On                 ; On                 ;
-; NOT Gate Push-Back                                               ; On                 ; On                 ;
-; Power-Up Don't Care                                              ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
-; Remove Duplicate Registers                                       ; On                 ; On                 ;
-; Ignore CARRY Buffers                                             ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
-; Ignore LCELL Buffers                                             ; Off                ; Off                ;
-; Ignore SOFT Buffers                                              ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
-; Optimization Technique                                           ; Balanced           ; Balanced           ;
-; Carry Chain Length                                               ; 70                 ; 70                 ;
-; Auto Carry Chains                                                ; On                 ; On                 ;
-; Auto Open-Drain Pins                                             ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
-; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
-; Allow Synchronous Control Signals                                ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
-; Auto Resource Sharing                                            ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
-; Report Parameter Settings                                        ; On                 ; On                 ;
-; Report Source Assignments                                        ; On                 ; On                 ;
-; Report Connectivity Checks                                       ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
-; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
-; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
-; HDL message level                                                ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
-; Clock MUX Protection                                             ; On                 ; On                 ;
-; Block Design Naming                                              ; Auto               ; Auto               ;
-; Synthesis Effort                                                 ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
-; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                      ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                              ; Library ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File            ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v     ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v      ;         ;
-; ../RAM2GS.mif                    ; yes             ; User Memory Initialization File  ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif ;         ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary         ;
-+---------------------------------------------+-------+
-; Resource                                    ; Usage ;
-+---------------------------------------------+-------+
-; Total logic elements                        ; 184   ;
-;     -- Combinational with no register       ; 86    ;
-;     -- Register only                        ; 30    ;
-;     -- Combinational with a register        ; 68    ;
-;                                             ;       ;
-; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 57    ;
-;     -- 3 input functions                    ; 46    ;
-;     -- 2 input functions                    ; 42    ;
-;     -- 1 input functions                    ; 8     ;
-;     -- 0 input functions                    ; 1     ;
-;                                             ;       ;
-; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 168   ;
-;     -- arithmetic mode                      ; 16    ;
-;     -- qfbk mode                            ; 0     ;
-;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 10    ;
-;     -- asynchronous clear/load mode         ; 0     ;
-;                                             ;       ;
-; Total registers                             ; 98    ;
-; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 63    ;
-; UFM blocks                                  ; 1     ;
-; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 55    ;
-; Total fan-out                               ; 662   ;
-; Average fan-out                             ; 2.67  ;
-+---------------------------------------------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                          ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS                                                   ; 184 (184)   ; 98           ; 1          ; 63   ; 0            ; 86 (86)      ; 30 (30)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                               ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; UFM.v           ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 98    ;
-; Number of registers using Synchronous Clear  ; 6     ;
-; Number of registers using Synchronous Load   ; 4     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 11    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics                     ;
-+----------------------------------------+---------+
-; Inverted Register                      ; Fan out ;
-+----------------------------------------+---------+
-; nRCS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
-; nRRAS~reg0                             ; 1       ;
-; nRCAS~reg0                             ; 1       ;
-; Total number of inverted registers = 4 ;         ;
-+----------------------------------------+---------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[1]               ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |RAM2GS|CmdLEDEN           ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|C1Submitted        ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                             ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
-; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:23:04 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
-    Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
-Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_unv File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47
-    Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 150
-Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 91
-Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 201
-Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 30 output pins
-    Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 184 logic cells
-    Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
-    Info: Peak virtual memory: 4701 megabytes
-    Info: Processing ended: Wed Aug 16 03:23:14 2023
-    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:24
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg.
-
-
+Analysis & Synthesis report for RAM2GS
+Sat Aug 19 21:59:40 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis IP Cores Summary
+  9. General Register Statistics
+ 10. Inverted Register Statistics
+ 11. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 12. Port Connectivity Checks: "UFM:UFM_inst"
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                              ;
++-----------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sat Aug 19 21:59:40 2023       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name               ; RAM2GS                                      ;
+; Top-level Entity Name       ; RAM2GS                                      ;
+; Family                      ; MAX II                                      ;
+; Total logic elements        ; 184                                         ;
+; Total pins                  ; 63                                          ;
+; Total virtual pins          ; 0                                           ;
+; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
++-----------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; EPM240T100C5       ;                    ;
+; Top-level entity name                                            ; RAM2GS             ; RAM2GS             ;
+; Family name                                                      ; MAX II             ; Cyclone V          ;
+; Maximum processors allowed for parallel compilation              ; 4                  ;                    ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Restructure Multiplexers                                         ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                         ; Auto               ; Auto               ;
+; Safe State Machine                                               ; Off                ; Off                ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Optimization Technique                                           ; Balanced           ; Balanced           ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Auto Resource Sharing                                            ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                       ;
++------------------------------------------+-----------------+----------------------------------------+----------------------------------------------+---------+
+; File Name with User-Entered Path         ; Used in Netlist ; File Type                              ; File Name with Absolute Path                 ; Library ;
++------------------------------------------+-----------------+----------------------------------------+----------------------------------------------+---------+
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; yes             ; User Verilog HDL File                  ; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v     ;         ;
+; //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v  ; yes             ; User Wizard-Generated File             ; //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v      ;         ;
+; RAM2GS.mif                               ; yes             ; Auto-Found Memory Initialization File  ; //ZaneMac/Repos/RAM2GS/CPLD/MAXII/RAM2GS.mif ;         ;
++------------------------------------------+-----------------+----------------------------------------+----------------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary         ;
++---------------------------------------------+-------+
+; Resource                                    ; Usage ;
++---------------------------------------------+-------+
+; Total logic elements                        ; 184   ;
+;     -- Combinational with no register       ; 86    ;
+;     -- Register only                        ; 30    ;
+;     -- Combinational with a register        ; 68    ;
+;                                             ;       ;
+; Logic element usage by number of LUT inputs ;       ;
+;     -- 4 input functions                    ; 57    ;
+;     -- 3 input functions                    ; 46    ;
+;     -- 2 input functions                    ; 42    ;
+;     -- 1 input functions                    ; 8     ;
+;     -- 0 input functions                    ; 1     ;
+;                                             ;       ;
+; Logic elements by mode                      ;       ;
+;     -- normal mode                          ; 168   ;
+;     -- arithmetic mode                      ; 16    ;
+;     -- qfbk mode                            ; 0     ;
+;     -- register cascade mode                ; 0     ;
+;     -- synchronous clear/load mode          ; 10    ;
+;     -- asynchronous clear/load mode         ; 0     ;
+;                                             ;       ;
+; Total registers                             ; 98    ;
+; Total logic cells in carry chains           ; 17    ;
+; I/O pins                                    ; 63    ;
+; UFM blocks                                  ; 1     ;
+; Maximum fan-out node                        ; RCLK  ;
+; Maximum fan-out                             ; 55    ;
+; Total fan-out                               ; 662   ;
+; Average fan-out                             ; 2.67  ;
++---------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                          ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2GS                                                   ; 184 (184)   ; 98           ; 1          ; 63   ; 0            ; 86 (86)      ; 30 (30)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;       |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work         ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                               ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; UFM.v           ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 98    ;
+; Number of registers using Synchronous Clear  ; 6     ;
+; Number of registers using Synchronous Load   ; 4     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 11    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; nRCS~reg0                              ; 1       ;
+; nRWE~reg0                              ; 1       ;
+; nRRAS~reg0                             ; 1       ;
+; nRCAS~reg0                             ; 1       ;
+; Total number of inverted registers = 4 ;         ;
++----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[1]               ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |RAM2GS|CmdLEDEN           ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|C1Submitted        ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                             ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 21:59:20 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (12021): Found 1 design units, including 1 entities, in source file //zanemac/repos/ram2gs/cpld/ram2gs-max.v
+    Info (12023): Found entity 1: RAM2GS File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
+Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
+    Info (12023): Found entity 1: UFM_altufm_none_unv File: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 47
+    Info (12023): Found entity 2: UFM File: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 150
+Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
+Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
+Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 201
+Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 25 input pins
+    Info (21059): Implemented 30 output pins
+    Info (21060): Implemented 8 bidirectional pins
+    Info (21061): Implemented 184 logic cells
+    Info (21070): Implemented 1 User Flash Memory blocks
+Info (144001): Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
+    Info: Peak virtual memory: 4703 megabytes
+    Info: Processing ended: Sat Aug 19 21:59:42 2023
+    Info: Elapsed time: 00:00:22
+    Info: Total CPU time (on all processors): 00:00:25
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg.
+
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.smsg b/CPLD/MAXII/output_files/RAM2GS.map.smsg
index e9c00ac..947eac9 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.smsg
+++ b/CPLD/MAXII/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(60): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
-Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 173
+Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
+Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 73
+Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //ZaneMac/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 173
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary
index c93b1c5..fb98ed9 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Wed Aug 16 03:23:14 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX II
-Total logic elements : 184
-Total pins : 63
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
+Analysis & Synthesis Status : Successful - Sat Aug 19 21:59:40 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX II
+Total logic elements : 184
+Total pins : 63
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2GS.pin b/CPLD/MAXII/output_files/RAM2GS.pin
index f7e2045..1fad15b 100644
--- a/CPLD/MAXII/output_files/RAM2GS.pin
+++ b/CPLD/MAXII/output_files/RAM2GS.pin
@@ -1,165 +1,165 @@
- -- Copyright (C) 2019  Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions 
- -- and other software and tools, and any partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Intel Program License 
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors.  Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 1:       3.3V
- --                  Bank 2:       3.3V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-CHIP  "RAM2GS"  ASSIGNED TO AN: EPM240T100C5
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND*                         : 1         :        :                   :         : 2         :                
-RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 10        : gnd    :                   :         :           :                
-GNDINT                       : 11        : gnd    :                   :         :           :                
-RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
-RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
-TMS                          : 22        : input  :                   :         : 1         :                
-TDI                          : 23        : input  :                   :         : 1         :                
-TCK                          : 24        : input  :                   :         : 1         :                
-TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 32        : gnd    :                   :         :           :                
-Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 46        : gnd    :                   :         :           :                
-Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
-nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 58        :        :                   :         : 2         :                
-VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
-GNDIO                        : 60        : gnd    :                   :         :           :                
-GND*                         : 61        :        :                   :         : 2         :                
-GND*                         : 62        :        :                   :         : 2         :                
-VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
-GND*                         : 64        :        :                   :         : 2         :                
-GNDINT                       : 65        : gnd    :                   :         :           :                
-GND*                         : 66        :        :                   :         : 2         :                
-nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 75        :        :                   :         : 2         :                
-GND*                         : 76        :        :                   :         : 2         :                
-GND*                         : 77        :        :                   :         : 2         :                
-GND*                         : 78        :        :                   :         : 2         :                
-GNDIO                        : 79        : gnd    :                   :         :           :                
-VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
-GND*                         : 81        :        :                   :         : 2         :                
-GND*                         : 82        :        :                   :         : 2         :                
-GND*                         : 83        :        :                   :         : 2         :                
-GND*                         : 84        :        :                   :         : 2         :                
-GND*                         : 85        :        :                   :         : 2         :                
-GND*                         : 86        :        :                   :         : 2         :                
-GND*                         : 87        :        :                   :         : 2         :                
-LED                          : 88        : output : 3.3-V LVTTL       :         : 2         : Y              
-RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-GNDIO                        : 93        : gnd    :                   :         :           :                
-VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
-RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
-RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+CHIP  "RAM2GS"  ASSIGNED TO AN: EPM240T100C5
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND*                         : 1         :        :                   :         : 2         :                
+RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 10        : gnd    :                   :         :           :                
+GNDINT                       : 11        : gnd    :                   :         :           :                
+RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
+RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
+TMS                          : 22        : input  :                   :         : 1         :                
+TDI                          : 23        : input  :                   :         : 1         :                
+TCK                          : 24        : input  :                   :         : 1         :                
+TDO                          : 25        : output :                   :         : 1         :                
+RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 32        : gnd    :                   :         :           :                
+Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 46        : gnd    :                   :         :           :                
+Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
+nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
+Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
+GND*                         : 58        :        :                   :         : 2         :                
+VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
+GNDIO                        : 60        : gnd    :                   :         :           :                
+GND*                         : 61        :        :                   :         : 2         :                
+GND*                         : 62        :        :                   :         : 2         :                
+VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
+GND*                         : 64        :        :                   :         : 2         :                
+GNDINT                       : 65        : gnd    :                   :         :           :                
+GND*                         : 66        :        :                   :         : 2         :                
+nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+GND*                         : 75        :        :                   :         : 2         :                
+GND*                         : 76        :        :                   :         : 2         :                
+GND*                         : 77        :        :                   :         : 2         :                
+GND*                         : 78        :        :                   :         : 2         :                
+GNDIO                        : 79        : gnd    :                   :         :           :                
+VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
+GND*                         : 81        :        :                   :         : 2         :                
+GND*                         : 82        :        :                   :         : 2         :                
+GND*                         : 83        :        :                   :         : 2         :                
+GND*                         : 84        :        :                   :         : 2         :                
+GND*                         : 85        :        :                   :         : 2         :                
+GND*                         : 86        :        :                   :         : 2         :                
+GND*                         : 87        :        :                   :         : 2         :                
+LED                          : 88        : output : 3.3-V LVTTL       :         : 2         : Y              
+RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+GNDIO                        : 93        : gnd    :                   :         :           :                
+VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
+RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
+RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD/MAXII/output_files/RAM2GS.sld b/CPLD/MAXII/output_files/RAM2GS.sld
index f7d3ed7..41a6030 100644
--- a/CPLD/MAXII/output_files/RAM2GS.sld
+++ b/CPLD/MAXII/output_files/RAM2GS.sld
@@ -1 +1 @@
-
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt
index 7961400..e537b41 100644
--- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt
@@ -1,1011 +1,1011 @@
-Timing Analyzer report for RAM2GS
-Wed Aug 16 03:23:21 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Timing Analyzer Summary
-  3. Parallel Compilation
-  4. SDC File List
-  5. Clocks
-  6. Fmax Summary
-  7. Setup Summary
-  8. Hold Summary
-  9. Recovery Summary
- 10. Removal Summary
- 11. Minimum Pulse Width Summary
- 12. Setup: 'DRCLK'
- 13. Setup: 'ARCLK'
- 14. Setup: 'RCLK'
- 15. Setup: 'nCRAS'
- 16. Setup: 'PHI2'
- 17. Hold: 'ARCLK'
- 18. Hold: 'DRCLK'
- 19. Hold: 'PHI2'
- 20. Hold: 'nCRAS'
- 21. Hold: 'RCLK'
- 22. Setup Transfers
- 23. Hold Transfers
- 24. Report TCCS
- 25. Report RSKM
- 26. Unconstrained Paths Summary
- 27. Clock Status Summary
- 28. Unconstrained Input Ports
- 29. Unconstrained Output Ports
- 30. Unconstrained Input Ports
- 31. Unconstrained Output Ports
- 32. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                     ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Timing Analyzer       ; Legacy Timing Analyzer                              ;
-; Revision Name         ; RAM2GS                                              ;
-; Device Family         ; MAX II                                              ;
-; Device Name           ; EPM240T100C5                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Slow Model                                          ;
-; Rise/Fall Delays      ; Unavailable                                         ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 2           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------+
-; SDC File List                                         ;
-+-------------------+--------+--------------------------+
-; SDC File Path     ; Status ; Read at                  ;
-+-------------------+--------+--------------------------+
-; ../RAM2GS.sdc     ; OK     ; Wed Aug 16 03:23:20 2023 ;
-; ../RAM2GS-MAX.sdc ; OK     ; Wed Aug 16 03:23:20 2023 ;
-+-------------------+--------+--------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                              ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-; nCCAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
-; nCRAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
-; PHI2       ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
-; RCLK       ; Base ; 16.000  ; 62.5 MHz  ; 0.000 ; 8.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-
-
-+-------------------------------------------------+
-; Fmax Summary                                    ;
-+-----------+-----------------+------------+------+
-; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
-; 35.93 MHz ; 35.93 MHz       ; PHI2       ;      ;
-; 87.43 MHz ; 87.43 MHz       ; RCLK       ;      ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; DRCLK ; -15.744 ; -15.744       ;
-; ARCLK ; -15.723 ; -15.723       ;
-; RCLK  ; -7.153  ; -69.927       ;
-; nCRAS ; 0.358   ; 0.000         ;
-; PHI2  ; 0.545   ; 0.000         ;
-+-------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -16.277 ; -16.277       ;
-; DRCLK ; -16.276 ; -16.276       ;
-; PHI2  ; -0.517  ; -1.433        ;
-; nCRAS ; 0.177   ; 0.000         ;
-; RCLK  ; 1.111   ; 0.000         ;
-+-------+---------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+---------------------------------+
-; Minimum Pulse Width Summary     ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; RCLK  ; 7.734   ; 0.000         ;
-; ARCLK ; 70.000  ; 0.000         ;
-; DRCLK ; 70.000  ; 0.000         ;
-; PHI2  ; 174.734 ; 0.000         ;
-; nCCAS ; 174.734 ; 0.000         ;
-; nCRAS ; 174.734 ; 0.000         ;
-+-------+---------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -15.744 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -2.195     ; 1.549      ;
-; -15.724 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -2.195     ; 1.529      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -15.723 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 8.000        ; -1.619     ; 2.104      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK'                                                                                                                                                                            ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -7.153 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.213      ;
-; -7.077 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.137      ;
-; -6.989 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.049      ;
-; -6.783 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.843      ;
-; -6.655 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.715      ;
-; -6.568 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.628      ;
-; -6.492 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.552      ;
-; -6.404 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.464      ;
-; -6.343 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.852      ;
-; -6.343 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.852      ;
-; -6.334 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.394      ;
-; -6.220 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.280      ;
-; -5.605 ; CmdSubmitted                                                                                ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.114      ;
-; -5.599 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.108      ;
-; -5.577 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.086      ;
-; -5.296 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.805      ;
-; -5.243 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.752      ;
-; -5.224 ; CmdLEDEN                                                                                    ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.733      ;
-; -4.658 ; CmdUFMPrgm                                                                                  ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.167      ;
-; -4.655 ; CmdUFMPrgm                                                                                  ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.164      ;
-; -4.396 ; CmdUFMErase                                                                                 ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 1.905      ;
-; -4.393 ; CmdUFMErase                                                                                 ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 1.902      ;
-; -0.901 ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 1.000        ; 3.348      ; 4.916      ;
-; -0.822 ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 1.000        ; 3.348      ; 4.837      ;
-; -0.665 ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 1.000        ; 3.348      ; 4.680      ;
-; 0.099  ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 2.000        ; 3.348      ; 4.916      ;
-; 0.178  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 2.000        ; 3.348      ; 4.837      ;
-; 0.335  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 2.000        ; 3.348      ; 4.680      ;
-; 1.951  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFMD        ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.911      ;
-; 1.973  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.889      ;
-; 1.975  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.887      ;
-; 4.562  ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 11.105     ;
-; 4.647  ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 11.020     ;
-; 4.845  ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.822     ;
-; 4.945  ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.722     ;
-; 5.143  ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.524     ;
-; 5.168  ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.499     ;
-; 5.459  ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.208     ;
-; 5.603  ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.064     ;
-; 5.801  ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.866      ;
-; 6.158  ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.509      ;
-; 6.164  ; InitReady                                                                                   ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.503      ;
-; 6.298  ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.369      ;
-; 6.441  ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.226      ;
-; 6.462  ; S[0]                                                                                        ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.205      ;
-; 6.496  ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.171      ;
-; 6.589  ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.078      ;
-; 6.614  ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.053      ;
-; 6.620  ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.047      ;
-; 6.752  ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.915      ;
-; 6.762  ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.905      ;
-; 6.794  ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.873      ;
-; 6.910  ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.757      ;
-; 6.912  ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.755      ;
-; 7.065  ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.602      ;
-; 7.081  ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.586      ;
-; 7.090  ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.577      ;
-; 7.120  ; S[1]                                                                                        ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.547      ;
-; 7.121  ; UFMInitDone                                                                                 ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.546      ;
-; 7.140  ; InitReady                                                                                   ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.527      ;
-; 7.151  ; FS[5]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.516      ;
-; 7.180  ; Ready                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.487      ;
-; 7.229  ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.438      ;
-; 7.264  ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.403      ;
-; 7.377  ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.290      ;
-; 7.380  ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.287      ;
-; 7.382  ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.285      ;
-; 7.385  ; RASr2                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.282      ;
-; 7.409  ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.258      ;
-; 7.412  ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.255      ;
-; 7.438  ; S[0]                                                                                        ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.229      ;
-; 7.447  ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.220      ;
-; 7.479  ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.188      ;
-; 7.506  ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.161      ;
-; 7.558  ; FS[6]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.109      ;
-; 7.570  ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.097      ;
-; 7.583  ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.084      ;
-; 7.606  ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.061      ;
-; 7.626  ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.041      ;
-; 7.641  ; InitReady                                                                                   ; IS[3]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.026      ;
-; 7.645  ; InitReady                                                                                   ; IS[1]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.022      ;
-; 7.711  ; S[0]                                                                                        ; Ready       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.956      ;
-; 7.762  ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.905      ;
-; 7.766  ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.901      ;
-; 7.786  ; FS[17]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.881      ;
-; 7.871  ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.796      ;
-; 7.882  ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.785      ;
-; 7.939  ; S[0]                                                                                        ; IS[3]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.728      ;
-; 7.943  ; S[0]                                                                                        ; IS[1]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.724      ;
-; 7.961  ; InitReady                                                                                   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.706      ;
-; 8.058  ; FS[15]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.609      ;
-; 8.072  ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.595      ;
-; 8.096  ; S[1]                                                                                        ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.571      ;
-; 8.130  ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.537      ;
-; 8.195  ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.472      ;
-; 8.203  ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.464      ;
-; 8.221  ; FS[14]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.446      ;
-; 8.259  ; S[0]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.408      ;
-; 8.301  ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.366      ;
-; 8.309  ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.358      ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Setup: 'nCRAS'                                                                                          ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; 0.358   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.916      ;
-; 0.779   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.495      ;
-; 0.780   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.494      ;
-; 0.789   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.485      ;
-; 0.789   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.485      ;
-; 0.790   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.484      ;
-; 0.791   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.483      ;
-; 1.260   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.014      ;
-; 1.260   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.014      ;
-; 1.261   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.013      ;
-; 1.264   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.010      ;
-; 1.269   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.005      ;
-; 173.113 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 175.000      ; 5.955      ; 7.509      ;
-; 348.113 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 350.000      ; 5.955      ; 7.509      ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2'                                                                                            ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-; 0.545   ; LEDEN     ; XOR8MEG      ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 3.280      ;
-; 1.198   ; Ready     ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 3.158      ; 3.627      ;
-; 1.883   ; n8MEGEN   ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 3.158      ; 2.942      ;
-; 1.925   ; LEDEN     ; CmdLEDEN     ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 1.900      ;
-; 1.963   ; n8MEGEN   ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 1.862      ;
-; 161.083 ; Bank[6]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
-; 161.083 ; Bank[6]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
-; 161.083 ; Bank[6]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
-; 161.249 ; Bank[7]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
-; 161.249 ; Bank[7]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
-; 161.249 ; Bank[7]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
-; 161.787 ; Bank[5]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
-; 161.787 ; Bank[5]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
-; 161.787 ; Bank[5]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
-; 161.798 ; Bank[6]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
-; 161.798 ; Bank[6]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
-; 161.798 ; Bank[6]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
-; 161.964 ; Bank[7]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
-; 161.964 ; Bank[7]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
-; 161.964 ; Bank[7]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
-; 162.217 ; Bank[6]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.450     ;
-; 162.289 ; Bank[4]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
-; 162.289 ; Bank[4]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
-; 162.289 ; Bank[4]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
-; 162.359 ; Bank[2]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
-; 162.359 ; Bank[2]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
-; 162.359 ; Bank[2]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
-; 162.383 ; Bank[7]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.284     ;
-; 162.502 ; Bank[5]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
-; 162.502 ; Bank[5]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
-; 162.502 ; Bank[5]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
-; 162.522 ; Bank[3]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
-; 162.522 ; Bank[3]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
-; 162.522 ; Bank[3]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
-; 162.921 ; Bank[5]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.746     ;
-; 163.004 ; Bank[4]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
-; 163.004 ; Bank[4]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
-; 163.004 ; Bank[4]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
-; 163.056 ; Bank[1]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
-; 163.056 ; Bank[1]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
-; 163.056 ; Bank[1]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
-; 163.074 ; Bank[2]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
-; 163.074 ; Bank[2]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
-; 163.074 ; Bank[2]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
-; 163.237 ; Bank[3]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
-; 163.237 ; Bank[3]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
-; 163.237 ; Bank[3]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
-; 163.423 ; Bank[4]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.244     ;
-; 163.493 ; Bank[2]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.174     ;
-; 163.570 ; Bank[0]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
-; 163.570 ; Bank[0]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
-; 163.570 ; Bank[0]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
-; 163.656 ; Bank[3]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.011     ;
-; 163.771 ; Bank[1]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
-; 163.771 ; Bank[1]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
-; 163.771 ; Bank[1]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
-; 163.824 ; Bank[6]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.843     ;
-; 163.990 ; Bank[7]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.677     ;
-; 164.000 ; Bank[6]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.667     ;
-; 164.000 ; Bank[6]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.667     ;
-; 164.166 ; Bank[7]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.501     ;
-; 164.166 ; Bank[7]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.501     ;
-; 164.190 ; Bank[1]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.477     ;
-; 164.285 ; Bank[0]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
-; 164.285 ; Bank[0]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
-; 164.285 ; Bank[0]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
-; 164.528 ; Bank[5]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.139     ;
-; 164.704 ; Bank[0]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
-; 164.704 ; Bank[5]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
-; 164.704 ; Bank[5]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
-; 165.030 ; Bank[4]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.637      ;
-; 165.100 ; Bank[2]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.567      ;
-; 165.206 ; Bank[4]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.461      ;
-; 165.206 ; Bank[4]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.461      ;
-; 165.263 ; Bank[3]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.404      ;
-; 165.276 ; Bank[2]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.391      ;
-; 165.276 ; Bank[2]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.391      ;
-; 165.439 ; Bank[3]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.228      ;
-; 165.439 ; Bank[3]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.228      ;
-; 165.797 ; Bank[1]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.870      ;
-; 165.951 ; Bank[6]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.716      ;
-; 165.951 ; Bank[6]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.716      ;
-; 165.973 ; Bank[1]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.694      ;
-; 165.973 ; Bank[1]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.694      ;
-; 166.117 ; Bank[7]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.550      ;
-; 166.117 ; Bank[7]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.550      ;
-; 166.311 ; Bank[0]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.356      ;
-; 166.487 ; Bank[0]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.180      ;
-; 166.487 ; Bank[0]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.180      ;
-; 166.655 ; Bank[5]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.012      ;
-; 166.655 ; Bank[5]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.012      ;
-; 167.157 ; Bank[4]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.510      ;
-; 167.157 ; Bank[4]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.510      ;
-; 167.227 ; Bank[2]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.440      ;
-; 167.227 ; Bank[2]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.440      ;
-; 167.390 ; Bank[3]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.277      ;
-; 167.390 ; Bank[3]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.277      ;
-; 167.924 ; Bank[1]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.743      ;
-; 167.924 ; Bank[1]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.743      ;
-; 168.438 ; Bank[0]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.229      ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.277 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -1.619     ; 2.104      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.276 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.195     ; 1.529      ;
-; -16.256 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.195     ; 1.549      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Hold: 'PHI2'                                                                                               ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -0.517  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 1.862      ;
-; -0.479  ; LEDEN       ; CmdLEDEN     ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 1.900      ;
-; -0.437  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.158      ; 2.942      ;
-; 0.248   ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.158      ; 3.627      ;
-; 0.901   ; LEDEN       ; XOR8MEG      ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 3.280      ;
-; 1.668   ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 1.889      ;
-; 1.909   ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.130      ;
-; 2.134   ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.355      ;
-; 2.332   ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.553      ;
-; 2.332   ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.553      ;
-; 4.449   ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.670      ;
-; 5.001   ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.222      ;
-; 5.001   ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.222      ;
-; 6.056   ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.277      ;
-; 6.475   ; CmdEnable   ; CmdLEDEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
-; 6.475   ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
-; 6.475   ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
-; 7.190   ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
-; 7.190   ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
-; 7.190   ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
-; 178.853 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 4.074      ;
-; 179.466 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 4.687      ;
-; 179.980 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.201      ;
-; 180.514 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.735      ;
-; 180.677 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.898      ;
-; 180.747 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.968      ;
-; 180.813 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.034      ;
-; 180.913 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.134      ;
-; 181.249 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.470      ;
-; 181.327 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.548      ;
-; 181.427 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.648      ;
-; 181.605 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.826      ;
-; 181.787 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.008      ;
-; 181.861 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.082      ;
-; 181.953 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.174      ;
-; 181.961 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.182      ;
-; 182.024 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.245      ;
-; 182.094 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.315      ;
-; 182.119 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.340      ;
-; 182.124 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.345      ;
-; 182.194 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.415      ;
-; 182.596 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.817      ;
-; 182.653 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.874      ;
-; 182.696 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.917      ;
-; 182.816 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.037      ;
-; 182.886 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.107      ;
-; 183.134 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.355      ;
-; 183.135 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.356      ;
-; 183.234 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.455      ;
-; 183.300 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.521      ;
-; 183.388 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.609      ;
-; 183.400 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.621      ;
-; 183.649 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.870      ;
-; 183.926 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.147      ;
-; 184.092 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.313      ;
-; 184.183 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.404      ;
-; 184.346 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.567      ;
-; 184.416 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.637      ;
-; 184.742 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.963      ;
-; 184.918 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.139     ;
-; 185.161 ; Bank[0]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
-; 185.161 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
-; 185.161 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
-; 185.256 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.477     ;
-; 185.456 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.677     ;
-; 185.622 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.843     ;
-; 185.675 ; Bank[1]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
-; 185.675 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
-; 185.675 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
-; 185.790 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.011     ;
-; 185.876 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
-; 185.876 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
-; 185.876 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
-; 185.953 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.174     ;
-; 186.023 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.244     ;
-; 186.209 ; Bank[3]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
-; 186.209 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
-; 186.209 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
-; 186.372 ; Bank[2]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
-; 186.372 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
-; 186.372 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
-; 186.390 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
-; 186.390 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
-; 186.390 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
-; 186.442 ; Bank[4]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
-; 186.442 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
-; 186.442 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
-; 186.525 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.746     ;
-; 186.924 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
-; 186.924 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
-; 186.924 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
-; 186.944 ; Bank[5]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
-; 186.944 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
-; 186.944 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
-; 187.063 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.284     ;
-; 187.087 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
-; 187.087 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
-; 187.087 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
-; 187.157 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.378     ;
-; 187.157 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.378     ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS'                                                                                           ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; 0.177   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.005      ;
-; 0.182   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.010      ;
-; 0.185   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.013      ;
-; 0.186   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.014      ;
-; 0.186   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.014      ;
-; 0.655   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.483      ;
-; 0.656   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.484      ;
-; 0.657   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.485      ;
-; 0.657   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.485      ;
-; 0.666   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.494      ;
-; 0.667   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.495      ;
-; 1.088   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.916      ;
-; 1.333   ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 5.955      ; 7.509      ;
-; 176.333 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -175.000     ; 5.955      ; 7.509      ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK'                                                                                            ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; 1.111 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 3.348      ; 4.680      ;
-; 1.268 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 3.348      ; 4.837      ;
-; 1.347 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 3.348      ; 4.916      ;
-; 1.395 ; CASr2       ; CASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.616      ;
-; 1.640 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.861      ;
-; 1.659 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.880      ;
-; 1.729 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.950      ;
-; 1.899 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.120      ;
-; 1.964 ; S[0]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.185      ;
-; 1.984 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.205      ;
-; 2.108 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.329      ;
-; 2.111 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -1.000       ; 3.348      ; 4.680      ;
-; 2.116 ; UFMD        ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
-; 2.116 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
-; 2.117 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.144 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
-; 2.144 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
-; 2.145 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.366      ;
-; 2.186 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.407      ;
-; 2.201 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.422      ;
-; 2.203 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.424      ;
-; 2.226 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.447      ;
-; 2.230 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.230 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.231 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.239 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.239 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.240 ; UFMD        ; UFMD        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.461      ;
-; 2.241 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.462      ;
-; 2.242 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
-; 2.242 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
-; 2.250 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
-; 2.250 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
-; 2.268 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -1.000       ; 3.348      ; 4.837      ;
-; 2.273 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.494      ;
-; 2.278 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.499      ;
-; 2.280 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.501      ;
-; 2.347 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -1.000       ; 3.348      ; 4.916      ;
-; 2.349 ; PHI2r2      ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.570      ;
-; 2.355 ; PHI2r2      ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.576      ;
-; 2.360 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.581      ;
-; 2.370 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.591      ;
-; 2.411 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.632      ;
-; 2.497 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.718      ;
-; 2.547 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.768      ;
-; 2.605 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.826      ;
-; 2.619 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.840      ;
-; 2.721 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.942      ;
-; 2.893 ; FS[16]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.114      ;
-; 2.936 ; IS[1]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.157      ;
-; 2.940 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
-; 2.940 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
-; 2.948 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.169      ;
-; 2.949 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.957 ; RASr2       ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.178      ;
-; 2.963 ; RASr2       ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.184      ;
-; 2.976 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
-; 2.976 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
-; 2.991 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.212      ;
-; 3.006 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.227      ;
-; 3.051 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.272      ;
-; 3.059 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.280      ;
-; 3.087 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
-; 3.087 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
-; 3.091 ; PHI2r3      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.312      ;
-; 3.091 ; PHI2r3      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.312      ;
-; 3.118 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.339      ;
-; 3.167 ; UFMD        ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.388      ;
-; 3.170 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.170 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.170 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.171 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.392      ;
-; 3.179 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.179 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.181 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.402      ;
-; 3.182 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.403      ;
-; 3.183 ; RASr        ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.404      ;
-; 3.198 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.419      ;
-; 3.212 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.433      ;
-; 3.238 ; UFMReqErase ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.459      ;
-; 3.281 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
-; 3.281 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
-; 3.282 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.503      ;
-; 3.290 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
-; 3.290 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
-; 3.328 ; S[1]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.549      ;
-; 3.329 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.550      ;
-; 3.335 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.556      ;
-; 3.354 ; UFMReqErase ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.575      ;
-; 3.355 ; UFMInitDone ; ARShift     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.576      ;
-; 3.376 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.597      ;
-; 3.392 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.613      ;
-; 3.393 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.614      ;
-; 3.401 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.622      ;
-; 3.418 ; RCKE~reg0   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.639      ;
-; 3.462 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.683      ;
-; 3.492 ; FS[3]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.713      ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 31    ; 31   ;
-; Unconstrained Input Port Paths  ; 249   ; 249  ;
-; Unconstrained Output Ports      ; 38    ; 38   ;
-; Unconstrained Output Port Paths ; 78    ; 78   ;
-+---------------------------------+-------+------+
-
-
-+-------------------------------------+
-; Clock Status Summary                ;
-+--------+-------+------+-------------+
-; Target ; Clock ; Type ; Status      ;
-+--------+-------+------+-------------+
-; ARCLK  ; ARCLK ; Base ; Constrained ;
-; DRCLK  ; DRCLK ; Base ; Constrained ;
-; PHI2   ; PHI2  ; Base ; Constrained ;
-; RCLK   ; RCLK  ; Base ; Constrained ;
-; nCCAS  ; nCCAS ; Base ; Constrained ;
-; nCRAS  ; nCRAS ; Base ; Constrained ;
-+--------+-------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:23:20 2023
-Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS
-Info: qsta_default_script.tcl version: #1
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332104): Reading SDC File: '../RAM2GS.sdc'
-Info (332104): Reading SDC File: '../RAM2GS-MAX.sdc'
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
-Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -15.744
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):   -15.744             -15.744 DRCLK 
-    Info (332119):   -15.723             -15.723 ARCLK 
-    Info (332119):    -7.153             -69.927 RCLK 
-    Info (332119):     0.358               0.000 nCRAS 
-    Info (332119):     0.545               0.000 PHI2 
-Info (332146): Worst-case hold slack is -16.277
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):   -16.277             -16.277 ARCLK 
-    Info (332119):   -16.276             -16.276 DRCLK 
-    Info (332119):    -0.517              -1.433 PHI2 
-    Info (332119):     0.177               0.000 nCRAS 
-    Info (332119):     1.111               0.000 RCLK 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 7.734
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     7.734               0.000 RCLK 
-    Info (332119):    70.000               0.000 ARCLK 
-    Info (332119):    70.000               0.000 DRCLK 
-    Info (332119):   174.734               0.000 PHI2 
-    Info (332119):   174.734               0.000 nCCAS 
-    Info (332119):   174.734               0.000 nCRAS 
-Info (332001): The selected device family is not supported by the report_metastability command.
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 4676 megabytes
-    Info: Processing ended: Wed Aug 16 03:23:21 2023
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
+Timing Analyzer report for RAM2GS
+Sat Aug 19 22:00:33 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Fmax Summary
+  7. Setup Summary
+  8. Hold Summary
+  9. Recovery Summary
+ 10. Removal Summary
+ 11. Minimum Pulse Width Summary
+ 12. Setup: 'DRCLK'
+ 13. Setup: 'ARCLK'
+ 14. Setup: 'RCLK'
+ 15. Setup: 'nCRAS'
+ 16. Setup: 'PHI2'
+ 17. Hold: 'ARCLK'
+ 18. Hold: 'DRCLK'
+ 19. Hold: 'PHI2'
+ 20. Hold: 'nCRAS'
+ 21. Hold: 'RCLK'
+ 22. Setup Transfers
+ 23. Hold Transfers
+ 24. Report TCCS
+ 25. Report RSKM
+ 26. Unconstrained Paths Summary
+ 27. Clock Status Summary
+ 28. Unconstrained Input Ports
+ 29. Unconstrained Output Ports
+ 30. Unconstrained Input Ports
+ 31. Unconstrained Output Ports
+ 32. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; RAM2GS                                              ;
+; Device Family         ; MAX II                                              ;
+; Device Name           ; EPM240T100C5                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Slow Model                                          ;
+; Rise/Fall Delays      ; Unavailable                                         ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------+
+; SDC File List                                                                  ;
++--------------------------------------------+--------+--------------------------+
+; SDC File Path                              ; Status ; Read at                  ;
++--------------------------------------------+--------+--------------------------+
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc     ; OK     ; Sat Aug 19 22:00:23 2023 ;
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc ; OK     ; Sat Aug 19 22:00:24 2023 ;
++--------------------------------------------+--------+--------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                              ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
+; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
+; nCCAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
+; nCRAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
+; PHI2       ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
+; RCLK       ; Base ; 16.000  ; 62.5 MHz  ; 0.000 ; 8.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+
+
++-------------------------------------------------+
+; Fmax Summary                                    ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
+; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
+; 35.93 MHz ; 35.93 MHz       ; PHI2       ;      ;
+; 87.43 MHz ; 87.43 MHz       ; RCLK       ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++---------------------------------+
+; Setup Summary                   ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; DRCLK ; -15.744 ; -15.744       ;
+; ARCLK ; -15.723 ; -15.723       ;
+; RCLK  ; -7.153  ; -69.927       ;
+; nCRAS ; 0.358   ; 0.000         ;
+; PHI2  ; 0.545   ; 0.000         ;
++-------+---------+---------------+
+
+
++---------------------------------+
+; Hold Summary                    ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -16.277 ; -16.277       ;
+; DRCLK ; -16.276 ; -16.276       ;
+; PHI2  ; -0.517  ; -1.433        ;
+; nCRAS ; 0.177   ; 0.000         ;
+; RCLK  ; 1.111   ; 0.000         ;
++-------+---------+---------------+
+
+
+--------------------
+; Recovery Summary ;
+--------------------
+No paths to report.
+
+
+-------------------
+; Removal Summary ;
+-------------------
+No paths to report.
+
+
++---------------------------------+
+; Minimum Pulse Width Summary     ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; RCLK  ; 7.734   ; 0.000         ;
+; ARCLK ; 70.000  ; 0.000         ;
+; DRCLK ; 70.000  ; 0.000         ;
+; PHI2  ; 174.734 ; 0.000         ;
+; nCCAS ; 174.734 ; 0.000         ;
+; nCRAS ; 174.734 ; 0.000         ;
++-------+---------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -15.744 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -2.195     ; 1.549      ;
+; -15.724 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -2.195     ; 1.529      ;
+; 100.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -15.723 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 8.000        ; -1.619     ; 2.104      ;
+; 100.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'RCLK'                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; -7.153 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.213      ;
+; -7.077 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.137      ;
+; -6.989 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 5.049      ;
+; -6.783 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.843      ;
+; -6.655 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.715      ;
+; -6.568 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.628      ;
+; -6.492 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.552      ;
+; -6.404 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.464      ;
+; -6.343 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.852      ;
+; -6.343 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.852      ;
+; -6.334 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.394      ;
+; -6.220 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -2.607     ; 4.280      ;
+; -5.605 ; CmdSubmitted                                                                                ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.114      ;
+; -5.599 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.108      ;
+; -5.577 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 3.086      ;
+; -5.296 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.805      ;
+; -5.243 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.752      ;
+; -5.224 ; CmdLEDEN                                                                                    ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.733      ;
+; -4.658 ; CmdUFMPrgm                                                                                  ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.167      ;
+; -4.655 ; CmdUFMPrgm                                                                                  ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 2.164      ;
+; -4.396 ; CmdUFMErase                                                                                 ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 1.905      ;
+; -4.393 ; CmdUFMErase                                                                                 ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -3.158     ; 1.902      ;
+; -0.901 ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 1.000        ; 3.348      ; 4.916      ;
+; -0.822 ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 1.000        ; 3.348      ; 4.837      ;
+; -0.665 ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 1.000        ; 3.348      ; 4.680      ;
+; 0.099  ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 2.000        ; 3.348      ; 4.916      ;
+; 0.178  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 2.000        ; 3.348      ; 4.837      ;
+; 0.335  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 2.000        ; 3.348      ; 4.680      ;
+; 1.951  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFMD        ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.911      ;
+; 1.973  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.889      ;
+; 1.975  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 8.000        ; 2.195      ; 7.887      ;
+; 4.562  ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 11.105     ;
+; 4.647  ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 11.020     ;
+; 4.845  ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.822     ;
+; 4.945  ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.722     ;
+; 5.143  ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.524     ;
+; 5.168  ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.499     ;
+; 5.459  ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.208     ;
+; 5.603  ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 10.064     ;
+; 5.801  ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.866      ;
+; 6.158  ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.509      ;
+; 6.164  ; InitReady                                                                                   ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.503      ;
+; 6.298  ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.369      ;
+; 6.441  ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.226      ;
+; 6.462  ; S[0]                                                                                        ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.205      ;
+; 6.496  ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.171      ;
+; 6.589  ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.078      ;
+; 6.614  ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.053      ;
+; 6.620  ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 9.047      ;
+; 6.752  ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.915      ;
+; 6.762  ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.905      ;
+; 6.794  ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.873      ;
+; 6.910  ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.757      ;
+; 6.912  ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.755      ;
+; 7.065  ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.602      ;
+; 7.081  ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.586      ;
+; 7.090  ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.577      ;
+; 7.120  ; S[1]                                                                                        ; RA10        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.547      ;
+; 7.121  ; UFMInitDone                                                                                 ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.546      ;
+; 7.140  ; InitReady                                                                                   ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.527      ;
+; 7.151  ; FS[5]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.516      ;
+; 7.180  ; Ready                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.487      ;
+; 7.229  ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.438      ;
+; 7.264  ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.403      ;
+; 7.377  ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.290      ;
+; 7.380  ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.287      ;
+; 7.382  ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.285      ;
+; 7.385  ; RASr2                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.282      ;
+; 7.409  ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.258      ;
+; 7.412  ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.255      ;
+; 7.438  ; S[0]                                                                                        ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.229      ;
+; 7.447  ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.220      ;
+; 7.479  ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.188      ;
+; 7.506  ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.161      ;
+; 7.558  ; FS[6]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.109      ;
+; 7.570  ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.097      ;
+; 7.583  ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.084      ;
+; 7.606  ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.061      ;
+; 7.626  ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.041      ;
+; 7.641  ; InitReady                                                                                   ; IS[3]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.026      ;
+; 7.645  ; InitReady                                                                                   ; IS[1]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 8.022      ;
+; 7.711  ; S[0]                                                                                        ; Ready       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.956      ;
+; 7.762  ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.905      ;
+; 7.766  ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.901      ;
+; 7.786  ; FS[17]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.881      ;
+; 7.871  ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.796      ;
+; 7.882  ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.785      ;
+; 7.939  ; S[0]                                                                                        ; IS[3]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.728      ;
+; 7.943  ; S[0]                                                                                        ; IS[1]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.724      ;
+; 7.961  ; InitReady                                                                                   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.706      ;
+; 8.058  ; FS[15]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.609      ;
+; 8.072  ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.595      ;
+; 8.096  ; S[1]                                                                                        ; IS[2]       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.571      ;
+; 8.130  ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.537      ;
+; 8.195  ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.472      ;
+; 8.203  ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.464      ;
+; 8.221  ; FS[14]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.446      ;
+; 8.259  ; S[0]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.408      ;
+; 8.301  ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.366      ;
+; 8.309  ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 7.358      ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Setup: 'nCRAS'                                                                                          ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.358   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.916      ;
+; 0.779   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.495      ;
+; 0.780   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.494      ;
+; 0.789   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.485      ;
+; 0.789   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.485      ;
+; 0.790   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.484      ;
+; 0.791   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.483      ;
+; 1.260   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.014      ;
+; 1.260   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.014      ;
+; 1.261   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.013      ;
+; 1.264   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.010      ;
+; 1.269   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 1.000        ; 2.607      ; 2.005      ;
+; 173.113 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 175.000      ; 5.955      ; 7.509      ;
+; 348.113 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 350.000      ; 5.955      ; 7.509      ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2'                                                                                            ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; 0.545   ; LEDEN     ; XOR8MEG      ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 3.280      ;
+; 1.198   ; Ready     ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 3.158      ; 3.627      ;
+; 1.883   ; n8MEGEN   ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 3.158      ; 2.942      ;
+; 1.925   ; LEDEN     ; CmdLEDEN     ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 1.900      ;
+; 1.963   ; n8MEGEN   ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; 1.000        ; 3.158      ; 1.862      ;
+; 161.083 ; Bank[6]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
+; 161.083 ; Bank[6]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
+; 161.083 ; Bank[6]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.584     ;
+; 161.249 ; Bank[7]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
+; 161.249 ; Bank[7]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
+; 161.249 ; Bank[7]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 13.418     ;
+; 161.787 ; Bank[5]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
+; 161.787 ; Bank[5]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
+; 161.787 ; Bank[5]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.880     ;
+; 161.798 ; Bank[6]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
+; 161.798 ; Bank[6]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
+; 161.798 ; Bank[6]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.869     ;
+; 161.964 ; Bank[7]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
+; 161.964 ; Bank[7]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
+; 161.964 ; Bank[7]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.703     ;
+; 162.217 ; Bank[6]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.450     ;
+; 162.289 ; Bank[4]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
+; 162.289 ; Bank[4]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
+; 162.289 ; Bank[4]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.378     ;
+; 162.359 ; Bank[2]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
+; 162.359 ; Bank[2]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
+; 162.359 ; Bank[2]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.308     ;
+; 162.383 ; Bank[7]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.284     ;
+; 162.502 ; Bank[5]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
+; 162.502 ; Bank[5]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
+; 162.502 ; Bank[5]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.165     ;
+; 162.522 ; Bank[3]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
+; 162.522 ; Bank[3]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
+; 162.522 ; Bank[3]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 12.145     ;
+; 162.921 ; Bank[5]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.746     ;
+; 163.004 ; Bank[4]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
+; 163.004 ; Bank[4]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
+; 163.004 ; Bank[4]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.663     ;
+; 163.056 ; Bank[1]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
+; 163.056 ; Bank[1]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
+; 163.056 ; Bank[1]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.611     ;
+; 163.074 ; Bank[2]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
+; 163.074 ; Bank[2]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
+; 163.074 ; Bank[2]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.593     ;
+; 163.237 ; Bank[3]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
+; 163.237 ; Bank[3]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
+; 163.237 ; Bank[3]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.430     ;
+; 163.423 ; Bank[4]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.244     ;
+; 163.493 ; Bank[2]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.174     ;
+; 163.570 ; Bank[0]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
+; 163.570 ; Bank[0]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
+; 163.570 ; Bank[0]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.097     ;
+; 163.656 ; Bank[3]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 11.011     ;
+; 163.771 ; Bank[1]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
+; 163.771 ; Bank[1]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
+; 163.771 ; Bank[1]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.896     ;
+; 163.824 ; Bank[6]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.843     ;
+; 163.990 ; Bank[7]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.677     ;
+; 164.000 ; Bank[6]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.667     ;
+; 164.000 ; Bank[6]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.667     ;
+; 164.166 ; Bank[7]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.501     ;
+; 164.166 ; Bank[7]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.501     ;
+; 164.190 ; Bank[1]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.477     ;
+; 164.285 ; Bank[0]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
+; 164.285 ; Bank[0]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
+; 164.285 ; Bank[0]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.382     ;
+; 164.528 ; Bank[5]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 10.139     ;
+; 164.704 ; Bank[0]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
+; 164.704 ; Bank[5]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
+; 164.704 ; Bank[5]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.963      ;
+; 165.030 ; Bank[4]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.637      ;
+; 165.100 ; Bank[2]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.567      ;
+; 165.206 ; Bank[4]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.461      ;
+; 165.206 ; Bank[4]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.461      ;
+; 165.263 ; Bank[3]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.404      ;
+; 165.276 ; Bank[2]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.391      ;
+; 165.276 ; Bank[2]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.391      ;
+; 165.439 ; Bank[3]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.228      ;
+; 165.439 ; Bank[3]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 9.228      ;
+; 165.797 ; Bank[1]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.870      ;
+; 165.951 ; Bank[6]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.716      ;
+; 165.951 ; Bank[6]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.716      ;
+; 165.973 ; Bank[1]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.694      ;
+; 165.973 ; Bank[1]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.694      ;
+; 166.117 ; Bank[7]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.550      ;
+; 166.117 ; Bank[7]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.550      ;
+; 166.311 ; Bank[0]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.356      ;
+; 166.487 ; Bank[0]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.180      ;
+; 166.487 ; Bank[0]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.180      ;
+; 166.655 ; Bank[5]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.012      ;
+; 166.655 ; Bank[5]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 8.012      ;
+; 167.157 ; Bank[4]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.510      ;
+; 167.157 ; Bank[4]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.510      ;
+; 167.227 ; Bank[2]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.440      ;
+; 167.227 ; Bank[2]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.440      ;
+; 167.390 ; Bank[3]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.277      ;
+; 167.390 ; Bank[3]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 7.277      ;
+; 167.924 ; Bank[1]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.743      ;
+; 167.924 ; Bank[1]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.743      ;
+; 168.438 ; Bank[0]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 6.229      ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.277 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -1.619     ; 2.104      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.276 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.195     ; 1.529      ;
+; -16.256 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.195     ; 1.549      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Hold: 'PHI2'                                                                                               ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -0.517  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 1.862      ;
+; -0.479  ; LEDEN       ; CmdLEDEN     ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 1.900      ;
+; -0.437  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.158      ; 2.942      ;
+; 0.248   ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.158      ; 3.627      ;
+; 0.901   ; LEDEN       ; XOR8MEG      ; RCLK         ; PHI2        ; -1.000       ; 3.158      ; 3.280      ;
+; 1.668   ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 1.889      ;
+; 1.909   ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.130      ;
+; 2.134   ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.355      ;
+; 2.332   ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.553      ;
+; 2.332   ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.553      ;
+; 4.449   ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.670      ;
+; 5.001   ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.222      ;
+; 5.001   ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.222      ;
+; 6.056   ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.277      ;
+; 6.475   ; CmdEnable   ; CmdLEDEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
+; 6.475   ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
+; 6.475   ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.696      ;
+; 7.190   ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
+; 7.190   ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
+; 7.190   ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.411      ;
+; 178.853 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 4.074      ;
+; 179.466 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 4.687      ;
+; 179.980 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.201      ;
+; 180.514 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.735      ;
+; 180.677 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.898      ;
+; 180.747 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 5.968      ;
+; 180.813 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.034      ;
+; 180.913 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.134      ;
+; 181.249 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.470      ;
+; 181.327 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.548      ;
+; 181.427 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.648      ;
+; 181.605 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 6.826      ;
+; 181.787 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.008      ;
+; 181.861 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.082      ;
+; 181.953 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.174      ;
+; 181.961 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.182      ;
+; 182.024 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.245      ;
+; 182.094 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.315      ;
+; 182.119 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.340      ;
+; 182.124 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.345      ;
+; 182.194 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.415      ;
+; 182.596 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.817      ;
+; 182.653 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.874      ;
+; 182.696 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.917      ;
+; 182.816 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.037      ;
+; 182.886 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.107      ;
+; 183.134 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.355      ;
+; 183.135 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.356      ;
+; 183.234 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.455      ;
+; 183.300 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.521      ;
+; 183.388 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.609      ;
+; 183.400 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.621      ;
+; 183.649 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.870      ;
+; 183.926 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.147      ;
+; 184.092 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.313      ;
+; 184.183 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.404      ;
+; 184.346 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.567      ;
+; 184.416 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.637      ;
+; 184.742 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.963      ;
+; 184.918 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.139     ;
+; 185.161 ; Bank[0]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
+; 185.161 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
+; 185.161 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.382     ;
+; 185.256 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.477     ;
+; 185.456 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.677     ;
+; 185.622 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.843     ;
+; 185.675 ; Bank[1]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
+; 185.675 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
+; 185.675 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.896     ;
+; 185.790 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.011     ;
+; 185.876 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
+; 185.876 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
+; 185.876 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.097     ;
+; 185.953 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.174     ;
+; 186.023 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.244     ;
+; 186.209 ; Bank[3]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
+; 186.209 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
+; 186.209 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.430     ;
+; 186.372 ; Bank[2]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
+; 186.372 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
+; 186.372 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.593     ;
+; 186.390 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
+; 186.390 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
+; 186.390 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.611     ;
+; 186.442 ; Bank[4]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
+; 186.442 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
+; 186.442 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.663     ;
+; 186.525 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.746     ;
+; 186.924 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
+; 186.924 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
+; 186.924 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.145     ;
+; 186.944 ; Bank[5]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
+; 186.944 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
+; 186.944 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.165     ;
+; 187.063 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.284     ;
+; 187.087 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
+; 187.087 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
+; 187.087 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.308     ;
+; 187.157 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.378     ;
+; 187.157 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.378     ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS'                                                                                           ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.177   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.005      ;
+; 0.182   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.010      ;
+; 0.185   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.013      ;
+; 0.186   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.014      ;
+; 0.186   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.014      ;
+; 0.655   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.483      ;
+; 0.656   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.484      ;
+; 0.657   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.485      ;
+; 0.657   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.485      ;
+; 0.666   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.494      ;
+; 0.667   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.495      ;
+; 1.088   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 2.607      ; 2.916      ;
+; 1.333   ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 5.955      ; 7.509      ;
+; 176.333 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -175.000     ; 5.955      ; 7.509      ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK'                                                                                            ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 1.111 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 3.348      ; 4.680      ;
+; 1.268 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 3.348      ; 4.837      ;
+; 1.347 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 3.348      ; 4.916      ;
+; 1.395 ; CASr2       ; CASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.616      ;
+; 1.640 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.861      ;
+; 1.659 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.880      ;
+; 1.729 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.950      ;
+; 1.899 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.120      ;
+; 1.964 ; S[0]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.185      ;
+; 1.984 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.205      ;
+; 2.108 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.329      ;
+; 2.111 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -1.000       ; 3.348      ; 4.680      ;
+; 2.116 ; UFMD        ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.116 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.117 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.144 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.144 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.145 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.366      ;
+; 2.186 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.407      ;
+; 2.201 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.422      ;
+; 2.203 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.424      ;
+; 2.226 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.447      ;
+; 2.230 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.230 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.231 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
+; 2.231 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
+; 2.239 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.239 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.240 ; UFMD        ; UFMD        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.461      ;
+; 2.241 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.242 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
+; 2.242 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
+; 2.250 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
+; 2.250 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
+; 2.268 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -1.000       ; 3.348      ; 4.837      ;
+; 2.273 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.494      ;
+; 2.278 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.499      ;
+; 2.280 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.501      ;
+; 2.347 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -1.000       ; 3.348      ; 4.916      ;
+; 2.349 ; PHI2r2      ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.570      ;
+; 2.355 ; PHI2r2      ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.576      ;
+; 2.360 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.581      ;
+; 2.370 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.591      ;
+; 2.411 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.632      ;
+; 2.497 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.718      ;
+; 2.547 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.768      ;
+; 2.605 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.826      ;
+; 2.619 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.840      ;
+; 2.721 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.942      ;
+; 2.893 ; FS[16]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.114      ;
+; 2.936 ; IS[1]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.157      ;
+; 2.940 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
+; 2.940 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
+; 2.948 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.169      ;
+; 2.949 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.957 ; RASr2       ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.178      ;
+; 2.963 ; RASr2       ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.184      ;
+; 2.976 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
+; 2.976 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
+; 2.991 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.212      ;
+; 3.006 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.227      ;
+; 3.051 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.272      ;
+; 3.059 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.280      ;
+; 3.087 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
+; 3.087 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
+; 3.091 ; PHI2r3      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.312      ;
+; 3.091 ; PHI2r3      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.312      ;
+; 3.118 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.339      ;
+; 3.167 ; UFMD        ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.388      ;
+; 3.170 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
+; 3.170 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
+; 3.170 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
+; 3.171 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.392      ;
+; 3.179 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.179 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.181 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.402      ;
+; 3.182 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.403      ;
+; 3.183 ; RASr        ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.404      ;
+; 3.198 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.419      ;
+; 3.212 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.433      ;
+; 3.238 ; UFMReqErase ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.459      ;
+; 3.281 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
+; 3.281 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
+; 3.282 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.503      ;
+; 3.290 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
+; 3.290 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
+; 3.328 ; S[1]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.549      ;
+; 3.329 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.550      ;
+; 3.335 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.556      ;
+; 3.354 ; UFMReqErase ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.575      ;
+; 3.355 ; UFMInitDone ; ARShift     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.576      ;
+; 3.376 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.597      ;
+; 3.392 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.613      ;
+; 3.393 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.614      ;
+; 3.401 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.622      ;
+; 3.418 ; RCKE~reg0   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.639      ;
+; 3.462 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.683      ;
+; 3.492 ; FS[3]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.713      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 31    ; 31   ;
+; Unconstrained Input Port Paths  ; 249   ; 249  ;
+; Unconstrained Output Ports      ; 38    ; 38   ;
+; Unconstrained Output Port Paths ; 78    ; 78   ;
++---------------------------------+-------+------+
+
+
++-------------------------------------+
+; Clock Status Summary                ;
++--------+-------+------+-------------+
+; Target ; Clock ; Type ; Status      ;
++--------+-------+------+-------------+
+; ARCLK  ; ARCLK ; Base ; Constrained ;
+; DRCLK  ; DRCLK ; Base ; Constrained ;
+; PHI2   ; PHI2  ; Base ; Constrained ;
+; RCLK   ; RCLK  ; Base ; Constrained ;
+; nCCAS  ; nCCAS ; Base ; Constrained ;
+; nCRAS  ; nCRAS ; Base ; Constrained ;
++--------+-------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 22:00:20 2023
+Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS
+Info: qsta_default_script.tcl version: #1
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
+Critical Warning (332148): Timing requirements not met
+Info (332146): Worst-case setup slack is -15.744
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -15.744             -15.744 DRCLK 
+    Info (332119):   -15.723             -15.723 ARCLK 
+    Info (332119):    -7.153             -69.927 RCLK 
+    Info (332119):     0.358               0.000 nCRAS 
+    Info (332119):     0.545               0.000 PHI2 
+Info (332146): Worst-case hold slack is -16.277
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -16.277             -16.277 ARCLK 
+    Info (332119):   -16.276             -16.276 DRCLK 
+    Info (332119):    -0.517              -1.433 PHI2 
+    Info (332119):     0.177               0.000 nCRAS 
+    Info (332119):     1.111               0.000 RCLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 7.734
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     7.734               0.000 RCLK 
+    Info (332119):    70.000               0.000 ARCLK 
+    Info (332119):    70.000               0.000 DRCLK 
+    Info (332119):   174.734               0.000 PHI2 
+    Info (332119):   174.734               0.000 nCCAS 
+    Info (332119):   174.734               0.000 nCRAS 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4678 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:33 2023
+    Info: Elapsed time: 00:00:13
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.summary b/CPLD/MAXII/output_files/RAM2GS.sta.summary
index 71518be..2444f00 100644
--- a/CPLD/MAXII/output_files/RAM2GS.sta.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.sta.summary
@@ -1,69 +1,69 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Setup 'DRCLK'
-Slack : -15.744
-TNS   : -15.744
-
-Type  : Setup 'ARCLK'
-Slack : -15.723
-TNS   : -15.723
-
-Type  : Setup 'RCLK'
-Slack : -7.153
-TNS   : -69.927
-
-Type  : Setup 'nCRAS'
-Slack : 0.358
-TNS   : 0.000
-
-Type  : Setup 'PHI2'
-Slack : 0.545
-TNS   : 0.000
-
-Type  : Hold 'ARCLK'
-Slack : -16.277
-TNS   : -16.277
-
-Type  : Hold 'DRCLK'
-Slack : -16.276
-TNS   : -16.276
-
-Type  : Hold 'PHI2'
-Slack : -0.517
-TNS   : -1.433
-
-Type  : Hold 'nCRAS'
-Slack : 0.177
-TNS   : 0.000
-
-Type  : Hold 'RCLK'
-Slack : 1.111
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'RCLK'
-Slack : 7.734
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'ARCLK'
-Slack : 70.000
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'DRCLK'
-Slack : 70.000
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'PHI2'
-Slack : 174.734
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'nCCAS'
-Slack : 174.734
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'nCRAS'
-Slack : 174.734
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Setup 'DRCLK'
+Slack : -15.744
+TNS   : -15.744
+
+Type  : Setup 'ARCLK'
+Slack : -15.723
+TNS   : -15.723
+
+Type  : Setup 'RCLK'
+Slack : -7.153
+TNS   : -69.927
+
+Type  : Setup 'nCRAS'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Setup 'PHI2'
+Slack : 0.545
+TNS   : 0.000
+
+Type  : Hold 'ARCLK'
+Slack : -16.277
+TNS   : -16.277
+
+Type  : Hold 'DRCLK'
+Slack : -16.276
+TNS   : -16.276
+
+Type  : Hold 'PHI2'
+Slack : -0.517
+TNS   : -1.433
+
+Type  : Hold 'nCRAS'
+Slack : 0.177
+TNS   : 0.000
+
+Type  : Hold 'RCLK'
+Slack : 1.111
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'RCLK'
+Slack : 7.734
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'ARCLK'
+Slack : 70.000
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'DRCLK'
+Slack : 70.000
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'PHI2'
+Slack : 174.734
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'nCCAS'
+Slack : 174.734
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'nCRAS'
+Slack : 174.734
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws
deleted file mode 100644
index 63563b76eda4b19c3f4f321afd3f1b7df67b8d5e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 48
ocmZ?JV1NM`h8%`OhGK>ihIoc@hJ1!1hHN0O04SEskP1@-0GYrBX8-^I

diff --git a/CPLD/MAXV/db/RAM2GS-MAXV.quiproj.13204.rdr.flock b/CPLD/MAXV/db/RAM2GS-MAXV.quiproj.13204.rdr.flock
new file mode 100644
index 0000000..e69de29
diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb
index cb9fb76a5cee67b4d2c7d25fbf69877374c0bea9..afccacf4f345420a21668e56a4072e1469851c8d 100644
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zY^_7dq2@#)qge|l7Av$eq@opd(3v82qEa;Fyp^$a)G1qx
zd~zU`a0&O17O;wM3eF(;zcd-$R@b4C-`vs3FXGVUUE4L}^Ht2p{F3Y~(&sHWdb3U6
zzhF&Yf0(m|*#HOAG5au--I$~8bZdr{-<+X~+p{}L-;G^`lSdpGx~&)EDUNJ%k%L_h
zxsgG5oZnk}=UDB;3gPLOD13iPemCS-JS?T3$}x{83OF*nFH!-(Bxi~T=I`^SNMZi9
z#`NHSZ&zO#gihvuIvI6};{
z`MsLW>DJo(mo?4zPOIYRW{p`L`6~0}nxp)TujX;|hnnUSHShnbX;!^|yw<#`S!MpV
z=IEswbK1}BIjW}j{b)X!HaatHrWI!ge?K(Yj*90^8fOtB#LPHftYyg8rrXbKKCL+0
zf6;%b$%&zO2#H!>Ja2rQMK};|&5$^S6c63JQ_H2V7HUG=g8@0IIr>P=(K%-@s%7n=
zX)c;g&E|J%-k+*z{@~x)83cuy-t&)YY6;D@qU;aMZ`ZuPk|`-f^G7x2Qmy$IUJa?bI;tW4HLm99
zqeYNH5a-WonqLt?5doU#p4Y~#u8ykBU(h9aqVQ2cmoGojbhkQB?mWKLefshj{sXgY
G3yJ|~W?P#8

diff --git a/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb
index e16c6099826a7bc0405f36634a4e575d29443f05..0cfcff9dadade6cd610439d7c036ebee18b38721 100644
GIT binary patch
delta 860
zcmV-i1Ec)y3hWAyPZh%h00000006cE0000000000003-}WGa7+!!${4X_E<)gyO~@
zhd(oFs^TI=r(a_%0@TV+ZK`seFms7?yjx&yx=sw
z;h3%*w5m|aGQEEh@5S`S-b`=CVYg|m%^SCx#eW5?cWh}XwP7zR$w05NsJe`Z2#oRzH6UWVz
z#lJD1ivvX54G1)
zVE&;oVAa1nn0JgM&XgBCtFbaYoCIvfv*dn%gHpN3XL+*Zn|r}vs0T+-6=S~Ud>msA
zCT={(d1B46dDrw9qt3TP&mx}oo*|fK@A`~$PV1FZqp=cOb7

delta 861
zcmV-j1ET!w3hfGzPZh)i00000006cE0000000000003=~WGa7!4$~yn(k2ro3B`>+
z$gMjUE?kHpxbO$~1N;FZbWy+WzUEFIoy@H*wDg2C_i^rb?m6eaPNswqXTWE{7d#jc
zOWzAZ6!4oC$7COx;xd@!RoNrNab2E78OHUEb=@W|P1)$iTH8YMpico6#@)B8Juf&-
zZ#bqa2dyepvP^$(#Je%Qu{+b7aoBBIYxBk}>eid>&b>@um6HKN^RKlN;1%^Ecq#YRdw}Mj|l7O{mPz$FZ=k7PvJQ*VpWo7
zdZAb?2BoDjQIbo_Nbo7;U7^T4s47bTLspinsI*^4k&b>6`NJ-|3EwZOFbK6f6W?z+
zaZ&L}WUPOgm}SYhs669;x3}vW6L-|=8TEHVGv
zjN)}}Cz@#gKJYM-3%m=JMCaGW6Ddij{V9=~T7E?Y$X1)p_2;3U>`2DVlcbtopo(lw
zNYeL3=ptKvHZ@Nf=j5KBp@?jiCF%GxC?ZP{L*%5|DRq=N>F6h@BTJn7u>L|PqnZ#e
z7)5_Zp=rCg!y;pxNBPGn(8q+5xEx%W5HoP7+g}Mb*W%_~;~X90mGDCcL%BMfUAo|V
zE|`C43|RH=4CWmpi8JK|&uXkp4<`Ye@hrLDU!znm@>!lN`Q~0Q80x_hRK=LDIUh%u
z{fQgTah_OnY~D3J!l<>}i@3dV&d~$Zozpn=L@yQdEwX8EVads+&3{y6Nd^zOB-u&B
nN!0QI-R6*vE9GE(ILqJ|Bjb#GKqt{RsAG~g=lKV-zXPoS9ucR-

diff --git a/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb
index 67a1ae03711516962db41441d062b77d305c086f..c1b3fc8eda9e24990e31fe102e2cc55b38387406 100644
GIT binary patch
delta 491
zcmV`+uCyA&zdLy^Lp6je1`iWJNriz0=2C{lR9!hb57c+9aj
zKq}9wr&Z5D8B;UKnC6%TbXLyJ;OF#IZIVz`=
zqpMrv!1GSf5!)%pdf-3W^7pBSMep{+B%6hP6BssuUSAU!5U>tQw`_rC-4{L6tyxpv
zmr2wYNw2zJ6VlgiLTVan2Qy;w^yrw7;7e9JW!@<^c!WB_9VxF6ZQ+-X&XWx=LQuU%
hbc_&q`Ecg5FB4e3GwZVEKLE)*zPyvWH?u|pT>(zA)n5Pr

delta 523
zcmV+m0`&ce2crj&Pk&1S00000000F70000000000005%{00000004La#8k^p!!Qs`
zp+JQ|LV_C-;>Zd0!2$6B+&FTM(j8Uxc9n#Sk|F-tG}?`)M_
z%GOm!W5cs1I1!Iiw)N1xwdLFd$HsgGOB?ZK--{$AHg^
zHe_9E1J%}seBNl(C8lMRnWpAXJE|K&tK?C~lw8t0gFZnm;SnhB5H-S=kIu6RaE73K
zjc8~gAm3mO@K5l~75?G^fz>PP@K+b;^i(&Raiwr|r>8R~S+?ZU6FHB$0!Zd@^G@$S
N00030|FbXxSOH4+?q2`^

diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb
index 47b390b0b78676e24540a6e45bcc53246103e4a3..cb0d93beee40c74f639a32a0439b100270dbcd12 100644
GIT binary patch
delta 1037
zcmV+o1oHd647v=EPk&7W00000001Ea00000000000024$00000004La>{v@r6Hyet
zEe`?TuZRx}iMnxNf*TWcGo`f>fi^RR$ZAq(!3w2h3Q1x+VkS3;lOyZ>mFREZ4lq_snB3
ziH7by;V-56oV{SYv`b5s@>0bvm&}S?St%E|aq%iHhBQQhxzPGi=GX=lM5kn@(eZrM
z^AAZ{w9>*hYDowN9nPm3tK1DXiw|ZVloHR;qwWUa0e@mu9D`AfEL<1C@L^7Fyu48{?777**5y3Wf+~E}x*#JFJb(tU
z?j1V+tAEbr3{T1nV4Xq3v}fmEbV(p{B<_O4)8x7=zW#CNO#_tlo(bxaO2Ue=QWBX@
zD6*bEtMqb*YbUJbz-3L0#FS5riAs1rDRNyFh)7IOk|L(KH(4LO*%Q2%d)#PfFITU05`dw1ho5bboo!M6{I6QqeRPlC*^9=p1y6ixKh5
zKM82zC;Errc>f08{f3-)br2G-#&R$7o!Zm)(I?TzX7z2OVe?pA-D<6E&d3-1VGv>3
z$HTrG97EA1rAE>pRxY9T$gh|1@uf80MCVPzsoU|R(AHNUj3DwO&RC^^-p+jH
zDNBYMCHZxgTe4PCU2CR*>TET1)x{XvqXlIbUEDob=dOaaT~&Hbz8-N
zPPVi1yMh09(Y8?|Q`x-T)#mC(aLw#ucYjn?t4m?KxnkK)oo@g&g>y+ErWHipk({a}
zl{TkZKRR&}d^aTc0dNN#q%LO_%w;1tU$BjQ-Yi&_Z5E1Y3|6Vpr>AH`yC;uFmV16y
zk=64b1W8uUtkq;m3eQZCq)>g3P|G(6`AjCNQwy;qTKNH1+k>qlVtKt$y83CU;{h+T
HO9b)(GAjN#

delta 1040
zcmV+r1n>L04807HPk&GZ00000001Ea0000000000002D(00000004La>{v^0(?Ag3
zqz~Hieu)Ywssvm(Ae9ReaB&(FD%vKp(~4fO(k3mTO;b6ofD`>s+~J0}z=5BD_ywF0
zR5kOhJ?pjW#7-m*h)y-x^?1K|?PI(h7DAjNK23aS049i{?|(TVa`ZPQ@=`{RVv-o`
zbtw^IC}>Bit+{Jko53@1QA$VGo7)P~5Bdb5YHsJn`fdVzSju`CAE6Ped!09GU}*cm
zgRmDEao1Jc7#^a5&4NyjJKb@_U3cs4JwI+34vnX~?!#5u2JyY&);bLYDJe9b?mI@b
zJ8KFTVzW6;*nh@$O~U(ie2h>#ZhOP6wIm)tq4{*zfp>RzB1;B3CW!aeTaMZW9ud|D
z_RIrf5DeXZh+jyH1!uu{=9HJJm8GgvDO**ix>7N*ap_fDOj3iE8@`6o$MG;2W{wIl?B*7M0@+1+rn1YqQWmH3Vxb$>Sm4-hMRfR+uhtedx-pL*n2
ziRUNH-N^QcgMAl{#>%dt?blsxR|M!R*+sp;Vu)>uzvXc4KFY}z;$ZpDEk;)VMgL7q
zNKg0hwL?%gL8uJgp?!<^iBMWbpsbBkT9%XxwYE_~3sAR`et
zfCjMcAAdUks?OycPRet{DuagQ%+5dUl0f80+#=Se$@5TrgX7Mh22#>{CZI0*$bRy;+RGiR9bL#r1}D^#s#G
K#~-su1o8nD3H?_9

diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb
index fa45d57cfbd6109f1460f6d1c9ffcbdd703c51cd..8f4f1219d64acebcc8c0fbc7bd11b2b22ef0020d 100644
GIT binary patch
delta 596
zcmV-a0;~Oj2<``vPk)yJ00000000F70000000000008a-00000004La#8t~q!!Qs`
zp+Ln$0*MPC5Emp)2qaE?05^`DqqJ#D)JLkME%2fI3O61*yS8IDPFsN}mQ3y0$?ke~
zZR&xH6Z&baaH_BY;_j|+?o+Honl+k7GzZbkG@Nt>ceF?ntbf90KW+7HK-!~u{(}kk
zwO@U_K~bZu)$d)>0t5L5g2u_vK{v?~W%*NQ?7($`o0I%igKOGD?DZRGKEH&f6XTa%
zAY5Dyhuqp(l(%&}&Ul^BG;e9lI3TP&j5N&DEuxOHw3|hP5}u7m-lI4YAy!!;M#~a0
zjF8Q)3@u8M>-3&q+?VxvZb?NyHdu7BORmoV@YQmxY9A~k&f{I2l>}=M$w;>
ztR2o?uTbfZ`(Htz-aW0fN@E^Z+DWBtGU7gSlN1}O)sC^C7TUzcEjAWU+FhHtRN949
z11}gtss25n?d*Z21?fi1g1n<@a&K{W(BINFio+KY9Dg~gtdK8QoCB&$@nMlP8njX=
zV5x4+e2K4#xUfnf&D9!&Ma2TgmCZ&(V<1{*7Qh8a8XI600Lri9v5oL+iBWoQ~g^NQ2JWKJR*b&6ZEJkb22
zK|eCUa7X~ac#h?vz)lT-UMBvbIRnfOI|!@*KYgIrXX$~eOzC}TpWZ+h$ju%I^yc&F
iJ<;+Ydc_$Ci!U{RXq90$TyYK@+Y3

delta 615
zcmV-t0+{{o2Z0EXPk*Wc00000000F700000000000003500000004La#8k^l13?gs
z@8AOzyr?K1^&$$M`~Yu)7tdjnY~m7QWMiU!ravS2LaVyBcW1JbC<;0-$xL-`S5I}%
z%vN-4;jj9KGo!7Lcli(JD!A4$r!Y4#yV3oyHfVKEut*ZFYJc^sUZZnFrxncIA54ay
z`qjsCV2#qoRc8+i4(3}?w3%Fc=sYY@+P`ewdhjgZ`k?<{;Iu_(2IDr;fC!K>j(g~^>xzahXTd6#TC!L`Daiq%w_|gd+kWTOl5Av^L2kduA
z8rMdzS1r?>_kWB7dUt!QRU312tQ{&X!pQq9O;T)7tEJq+T9`?STWlOZZFe(CsVsz6
zgD)7Vvi@DecJ#p7g1FJTKy+43?=9~R`&-*4^N|ZlAAdcnu9z>qBnMU({IqBqRjjfU
zxXf;iG
zvJvSNsvGfKac+u2m?`4ZX&dPx+vJivl__HIec;Zil^KglXisDWMXBj%ZNqie3tS#!
zo@0Js;9E}z!^ksh0RQTLEP^
BA0+?)

diff --git a/CPLD/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAXV/db/RAM2GS.asm.qmsg
index 9235447..87e311e 100644
--- a/CPLD/MAXV/db/RAM2GS.asm.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692170504585 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692170504591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 16 03:21:44 2023 " "Processing started: Wed Aug 16 03:21:44 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692170504591 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1692170504591 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1692170504591 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1692170504855 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1692170504861 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170504974 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:21:44 2023 " "Processing ended: Wed Aug 16 03:21:44 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170504974 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170504974 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170504974 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1692170504974 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692496840526 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692496840558 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 22:00:40 2023 " "Processing started: Sat Aug 19 22:00:40 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692496840558 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1692496840558 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1692496840558 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1692496842042 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1692496842245 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496844120 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:44 2023 " "Processing ended: Sat Aug 19 22:00:44 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496844120 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496844120 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496844120 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1692496844120 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAXV/db/RAM2GS.asm.rdb
index 6dc5abcefd4228e2cda90af28a8e80c943ecb207..3a8a3e3e7bc186176eaea2062d06035034c7826c 100644
GIT binary patch
delta 528
zcmV+r0`L8(2Au|wM}M9K00000002w^000000027y00000000000012W00000004La
zoK)XW6G0H}DJrOl5<O&QiFLm6P!L~QJ?GZ|B&2q*(B!-7t}f}CTfMe-@`a^8FPj%Kxj|t
z0W(UkbK(=yO=ehDyMGy8V+LOeo$8w<;Wqt9=4s{z
z-F{S5d>ApB-R8dWdY#OE6tu+k}_o>;Ayxr!u(<
Sv%ex276rBr;V%G_Qv%h_Yx*w$

delta 539
zcmV+$0_6Rj2B-#*M}N2k0000000374000000027y0000000000001Zh00000004La
ztW@1^(?ASwU@*SFgb?uLC*Ib4tlOl%g@zU(!eFTi;$^yJZi&bxC3jb`zaD(?ZELGh
zA%rEzx!>78`_4|bI-Slv(wn4KJg;+`Oso{jlMBc*802)j~RGS5bW(|=jCc^&^Rl8aiN5V%weYF$(_wMFQsI7?l`ilGA#+jV-t
zlG5vnxTC%x@RELn6*fZSDGZAemF4(T5*N=&+LW-u&kN^uY>Cd>0tqgP9N}=Ti@H*M
zNc#R^g-KH^(0@8+|;r1-jktyq<2V
z)$aXeQ`XPm4zSvV6qOP)+}wqSM8(B-g_7MLQqAnxv8+v)7TPG@c||5Oc}^*&ri2~%
zOx=jh48nZ~cKcD-@AV)GqFr`>K<0?BT+f^(`_P&o2YE_5`QG
zlo}?YG_LlS1l#dz>w`7n$f1q=A5+70_B%E?zYZO
z&qSmIMFfSPz4f$puy`gRDf~=WN=Q^xNK{xv>e)3Pa|ESph
z`G3eY;_d%S|F_Z?{oi|^>-&Fb8+1%`Fi7wxNVlGt*!vI5Gv?X%lBlAioNO#Ud2r^*
zGVmbT-t#+Yr8HT1aIUj3d-iX~#m7ISZZ3Q)#Ih9jPcnikAtLe7qXYfaBAcS0M_16T
z$L1A{)64dl0H4)vYe}^Gxv71$)D{lZlesr)if+%+KsyB-ju%e)CIaE(X!kR`Y(VRO
zh%3mIg=5A+dGq1J?eZ}1?2{D@H1m9b6@vE2Xo&(L?}2e9JJ_NxyJuOG7r0kCkKTqo
z&VWa@=8SiRuWw28!ilpIws&Ofh&D7qG%P6>m4KEE?AmLWll8CSwzW?wpkv=1V*tW+
zj=1reY0%x}>6Fvx02jEAzH1XU$eV7Qvx|@yz*4-`xXF{Ug7Q2{}bXUad9kDl@|06#S2<)uGQ?lXf!V>^!
zAIWCKq&e(y7Ar3bBPoa(y|`MvG3a_i+@^lKfKvpI-SctC1I17{1}nP{rt*~fF2V(0
ztNXYcuV8~Of}>v!=2Yg5ZA(HQI6O)Zq+gK7Zd13+#zcVb3E3#rC;R0zPR#~0X{f?yaAUF=$qbmX1hoLxqQi3#|Cc_9c5LRQzm!9P$A;*)8k4I
zmBvcXxm8cstn1t|<&zEBQ{vn_mK2pGP%&yjXeMbf3AVmb`r1=VYl7UaQ?Y^Xv5aro
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diff --git a/CPLD/MAXV/db/RAM2GS.cmp.logdb b/CPLD/MAXV/db/RAM2GS.cmp.logdb
index 626799f..d45424f 100644
--- a/CPLD/MAXV/db/RAM2GS.cmp.logdb
+++ b/CPLD/MAXV/db/RAM2GS.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/CPLD/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAXV/db/RAM2GS.cmp.rdb
index 5e3797d32f70d3dfa4c95fb3c40d5102ff3273b2..9ef768cf71b044e8b098f15aedab72c55cc65953 100644
GIT binary patch
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diff --git a/CPLD/MAXV/db/RAM2GS.db_info b/CPLD/MAXV/db/RAM2GS.db_info
index 3c4a432..4565d8f 100644
--- a/CPLD/MAXV/db/RAM2GS.db_info
+++ b/CPLD/MAXV/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Version_Index = 503488000
-Creation_Time = Wed Aug 16 05:07:54 2023
+Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Version_Index = 503488000
+Creation_Time = Sat Aug 19 21:57:52 2023
diff --git a/CPLD/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAXV/db/RAM2GS.fit.qmsg
index 2f81f44..3ed53e4 100644
--- a/CPLD/MAXV/db/RAM2GS.fit.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.fit.qmsg
@@ -1,43 +1,43 @@
-{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1692170502239 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1692170502241 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692170502302 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692170502302 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1692170502332 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1692170502336 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692170502453 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1692170502453 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS.sdc " "Reading SDC File: '../RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692170502502 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS-MAX.sdc " "Reading SDC File: '../RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692170502505 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1692170502512 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        ARCLK " " 200.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        DRCLK " " 200.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCCAS " " 350.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCRAS " " 350.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000         PHI2 " " 350.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  16.000         RCLK " "  16.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692170502513 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1692170502513 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692170502518 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692170502518 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692170502520 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RD~16 " "Destination \"RD~16\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692170502527 ""}  } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692170502527 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692170502528 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692170502528 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1692170502530 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1692170502546 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1692170502572 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1692170502573 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1692170502573 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1692170502573 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170502600 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1692170502603 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1692170502689 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170502805 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1692170502807 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1692170503163 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170503163 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1692170503186 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "16 " "Router estimated average interconnect usage is 16% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "16 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1692170503323 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1692170503323 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1692170503416 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1692170503416 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170503417 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1692170503427 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692170503435 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1692170503494 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170503538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:21:43 2023 " "Processing ended: Wed Aug 16 03:21:43 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170503538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170503538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170503538 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1692170503538 ""}
+{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1692496796308 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1692496796339 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692496796417 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1692496796417 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1692496796855 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1692496796870 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1692496797323 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1692496797323 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692496797448 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1692496797573 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1692496797714 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        ARCLK " " 200.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 200.000        DRCLK " " 200.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCCAS " " 350.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000        nCRAS " " 350.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 350.000         PHI2 " " 350.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  16.000         RCLK " "  16.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1692496797714 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1692496797714 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692496797729 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 41 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797745 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 8 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797745 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 22 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797776 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797776 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797776 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 342 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797776 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 18 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797776 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RD~16 " "Destination \"RD~16\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797776 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 16 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1692496797776 ""}  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1692496797776 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 341 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1692496797776 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1692496797792 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1692496797808 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1692496797870 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1692496797948 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496798011 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1692496798370 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1692496798667 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496798854 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1692496798870 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1692496799292 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496799292 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1692496799323 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "16 " "Router estimated average interconnect usage is 16% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "16 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1692496799495 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1692496799495 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1692496800089 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1692496800089 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496800089 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1692496800105 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1692496800120 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1692496800901 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5347 " "Peak virtual memory: 5347 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496803464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:03 2023 " "Processing ended: Sat Aug 19 22:00:03 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496803464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496803464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496803464 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1692496803464 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.hier_info b/CPLD/MAXV/db/RAM2GS.hier_info
index c797648..3bfd44b 100644
--- a/CPLD/MAXV/db/RAM2GS.hier_info
+++ b/CPLD/MAXV/db/RAM2GS.hier_info
@@ -1,285 +1,285 @@
-|RAM2GS
-PHI2 => Bank[0].CLK
-PHI2 => Bank[1].CLK
-PHI2 => Bank[2].CLK
-PHI2 => Bank[3].CLK
-PHI2 => Bank[4].CLK
-PHI2 => Bank[5].CLK
-PHI2 => Bank[6].CLK
-PHI2 => Bank[7].CLK
-PHI2 => RA11.CLK
-PHI2 => PHI2r.DATAIN
-PHI2 => CmdDRDIn.CLK
-PHI2 => CmdDRCLK.CLK
-PHI2 => CmdUFMPrgm.CLK
-PHI2 => CmdUFMErase.CLK
-PHI2 => CmdSubmitted.CLK
-PHI2 => Cmdn8MEGEN.CLK
-PHI2 => CmdLEDEN.CLK
-PHI2 => XOR8MEG.CLK
-PHI2 => ADSubmitted.CLK
-PHI2 => C1Submitted.CLK
-PHI2 => UFMOscEN.CLK
-PHI2 => CmdEnable.CLK
-MAin[0] => RA.DATAA
-MAin[0] => RowA.DATAB
-MAin[0] => Equal0.IN7
-MAin[0] => Equal1.IN7
-MAin[0] => Equal3.IN6
-MAin[1] => RA.DATAA
-MAin[1] => RowA.DATAB
-MAin[1] => Equal0.IN6
-MAin[1] => Equal1.IN6
-MAin[1] => Equal3.IN7
-MAin[2] => RA.DATAA
-MAin[2] => RowA.DATAB
-MAin[2] => Equal0.IN5
-MAin[2] => Equal1.IN5
-MAin[2] => Equal3.IN5
-MAin[3] => RA.DATAA
-MAin[3] => RowA.DATAB
-MAin[3] => Equal0.IN4
-MAin[3] => Equal1.IN4
-MAin[3] => Equal3.IN4
-MAin[4] => RA.DATAA
-MAin[4] => RowA.DATAB
-MAin[4] => Equal0.IN3
-MAin[4] => Equal1.IN3
-MAin[4] => Equal3.IN3
-MAin[5] => RA.DATAA
-MAin[5] => RowA.DATAB
-MAin[5] => Equal0.IN2
-MAin[5] => Equal1.IN2
-MAin[5] => Equal3.IN2
-MAin[6] => RA.DATAA
-MAin[6] => RowA.DATAB
-MAin[6] => Equal0.IN1
-MAin[6] => Equal1.IN1
-MAin[6] => Equal3.IN1
-MAin[7] => RA.DATAA
-MAin[7] => RowA.DATAB
-MAin[7] => Equal0.IN0
-MAin[7] => Equal1.IN0
-MAin[7] => Equal3.IN0
-MAin[8] => RA.DATAA
-MAin[8] => RowA.DATAB
-MAin[9] => RA.DATAA
-MAin[9] => RDQMH.DATAA
-MAin[9] => RowA.DATAB
-MAin[9] => RDQML.DATAA
-CROW[0] => RBA.DATAB
-CROW[1] => RBA.DATAB
-Din[0] => XOR8MEG.IN1
-Din[0] => CmdDRDIn.DATAB
-Din[0] => WRD[0].DATAIN
-Din[0] => Bank[0].DATAIN
-Din[0] => Equal14.IN2
-Din[0] => Equal15.IN4
-Din[0] => Cmdn8MEGEN.DATAB
-Din[1] => XOR8MEG.IN1
-Din[1] => CmdDRCLK.DATAB
-Din[1] => CmdLEDEN.DATAB
-Din[1] => WRD[1].DATAIN
-Din[1] => Bank[1].DATAIN
-Din[1] => Equal14.IN7
-Din[1] => Equal15.IN7
-Din[2] => CmdUFMPrgm.DATAB
-Din[2] => WRD[2].DATAIN
-Din[2] => Bank[2].DATAIN
-Din[2] => Equal14.IN6
-Din[2] => Equal15.IN3
-Din[2] => Equal16.IN1
-Din[3] => CmdUFMErase.DATAB
-Din[3] => WRD[3].DATAIN
-Din[3] => Bank[3].DATAIN
-Din[3] => Equal14.IN5
-Din[3] => Equal15.IN2
-Din[3] => Equal16.IN0
-Din[4] => WRD[4].DATAIN
-Din[4] => Bank[4].DATAIN
-Din[4] => Equal14.IN4
-Din[4] => Equal15.IN6
-Din[4] => Equal17.IN3
-Din[4] => Equal18.IN0
-Din[4] => Equal19.IN3
-Din[5] => WRD[5].DATAIN
-Din[5] => Bank[5].DATAIN
-Din[5] => Equal14.IN3
-Din[5] => Equal15.IN1
-Din[5] => Equal17.IN2
-Din[5] => Equal18.IN3
-Din[5] => Equal19.IN0
-Din[6] => RA11.IN1
-Din[6] => WRD[6].DATAIN
-Din[6] => Bank[6].DATAIN
-Din[6] => Equal14.IN1
-Din[6] => Equal15.IN5
-Din[6] => Equal17.IN1
-Din[6] => Equal18.IN2
-Din[6] => Equal19.IN2
-Din[7] => WRD[7].DATAIN
-Din[7] => Bank[7].DATAIN
-Din[7] => Equal14.IN0
-Din[7] => Equal15.IN0
-Din[7] => Equal17.IN0
-Din[7] => Equal18.IN1
-Din[7] => Equal19.IN1
-Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE
-Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE
-Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE
-Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE
-Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE
-Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE
-Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE
-Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE
-nCCAS => WRD[0].CLK
-nCCAS => WRD[1].CLK
-nCCAS => WRD[2].CLK
-nCCAS => WRD[3].CLK
-nCCAS => WRD[4].CLK
-nCCAS => WRD[5].CLK
-nCCAS => WRD[6].CLK
-nCCAS => WRD[7].CLK
-nCCAS => RD.IN0
-nCCAS => CBR.DATAIN
-nCCAS => CASr.DATAIN
-nCRAS => CBR.CLK
-nCRAS => FWEr.CLK
-nCRAS => RowA[0].CLK
-nCRAS => RowA[1].CLK
-nCRAS => RowA[2].CLK
-nCRAS => RowA[3].CLK
-nCRAS => RowA[4].CLK
-nCRAS => RowA[5].CLK
-nCRAS => RowA[6].CLK
-nCRAS => RowA[7].CLK
-nCRAS => RowA[8].CLK
-nCRAS => RowA[9].CLK
-nCRAS => RBA[0]~reg0.CLK
-nCRAS => RBA[1]~reg0.CLK
-nCRAS => LED.IN1
-nCRAS => RASr.DATAIN
-nFWE => RD.IN1
-nFWE => CMDWR.IN1
-nFWE => ADWR.IN1
-nFWE => C1WR.IN1
-nFWE => FWEr.DATAIN
-LED << LED.DB_MAX_OUTPUT_PORT_TYPE
-RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE
-RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE
-RD[0] <> RD[0]
-RD[1] <> RD[1]
-RD[2] <> RD[2]
-RD[3] <> RD[3]
-RD[4] <> RD[4]
-RD[5] <> RD[5]
-RD[6] <> RD[6]
-RD[7] <> RD[7]
-nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RCLK => UFMProgram.CLK
-RCLK => UFMErase.CLK
-RCLK => UFMReqErase.CLK
-RCLK => LEDEN.CLK
-RCLK => UFMInitDone.CLK
-RCLK => n8MEGEN.CLK
-RCLK => UFMD.CLK
-RCLK => DRShift.CLK
-RCLK => DRDIn.CLK
-RCLK => DRCLK.CLK
-RCLK => ARShift.CLK
-RCLK => ARCLK.CLK
-RCLK => Ready.CLK
-RCLK => IS[0].CLK
-RCLK => IS[1].CLK
-RCLK => IS[2].CLK
-RCLK => IS[3].CLK
-RCLK => nRowColSel.CLK
-RCLK => RCKEEN.CLK
-RCLK => RA10.CLK
-RCLK => nRWE~reg0.CLK
-RCLK => nRCAS~reg0.CLK
-RCLK => nRRAS~reg0.CLK
-RCLK => nRCS~reg0.CLK
-RCLK => RCKE~reg0.CLK
-RCLK => InitReady.CLK
-RCLK => FS[0].CLK
-RCLK => FS[1].CLK
-RCLK => FS[2].CLK
-RCLK => FS[3].CLK
-RCLK => FS[4].CLK
-RCLK => FS[5].CLK
-RCLK => FS[6].CLK
-RCLK => FS[7].CLK
-RCLK => FS[8].CLK
-RCLK => FS[9].CLK
-RCLK => FS[10].CLK
-RCLK => FS[11].CLK
-RCLK => FS[12].CLK
-RCLK => FS[13].CLK
-RCLK => FS[14].CLK
-RCLK => FS[15].CLK
-RCLK => FS[16].CLK
-RCLK => FS[17].CLK
-RCLK => S[0].CLK
-RCLK => S[1].CLK
-RCLK => CASr3.CLK
-RCLK => CASr2.CLK
-RCLK => CASr.CLK
-RCLK => RASr3.CLK
-RCLK => RASr2.CLK
-RCLK => RASr.CLK
-RCLK => PHI2r3.CLK
-RCLK => PHI2r2.CLK
-RCLK => PHI2r.CLK
-RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE
-RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|RAM2GS|UFM:UFM_inst
-arclk => arclk.IN1
-ardin => ardin.IN1
-arshft => arshft.IN1
-drclk => drclk.IN1
-drdin => drdin.IN1
-drshft => drshft.IN1
-erase => erase.IN1
-oscena => oscena.IN1
-program => program.IN1
-busy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.busy
-drdout <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.drdout
-osc <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.osc
-rtpbusy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.rtpbusy
-
-
-|RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component
-arclk => maxii_ufm_block1.ARCLK
-ardin => maxii_ufm_block1.ARDIN
-arshft => maxii_ufm_block1.ARSHFT
-busy <= maxii_ufm_block1.BUSY
-drclk => maxii_ufm_block1.DRCLK
-drdin => maxii_ufm_block1.DRDIN
-drdout <= maxii_ufm_block1.DRDOUT
-drshft => maxii_ufm_block1.DRSHFT
-erase => maxii_ufm_block1.ERASE
-osc <= maxii_ufm_block1.OSC
-oscena => maxii_ufm_block1.OSCENA
-program => maxii_ufm_block1.PROGRAM
-rtpbusy <= maxii_ufm_block1.BGPBUSY
-
-
+|RAM2GS
+PHI2 => Bank[0].CLK
+PHI2 => Bank[1].CLK
+PHI2 => Bank[2].CLK
+PHI2 => Bank[3].CLK
+PHI2 => Bank[4].CLK
+PHI2 => Bank[5].CLK
+PHI2 => Bank[6].CLK
+PHI2 => Bank[7].CLK
+PHI2 => RA11.CLK
+PHI2 => PHI2r.DATAIN
+PHI2 => CmdDRDIn.CLK
+PHI2 => CmdDRCLK.CLK
+PHI2 => CmdUFMPrgm.CLK
+PHI2 => CmdUFMErase.CLK
+PHI2 => CmdSubmitted.CLK
+PHI2 => Cmdn8MEGEN.CLK
+PHI2 => CmdLEDEN.CLK
+PHI2 => XOR8MEG.CLK
+PHI2 => ADSubmitted.CLK
+PHI2 => C1Submitted.CLK
+PHI2 => UFMOscEN.CLK
+PHI2 => CmdEnable.CLK
+MAin[0] => RA.DATAA
+MAin[0] => RowA.DATAB
+MAin[0] => Equal0.IN7
+MAin[0] => Equal1.IN7
+MAin[0] => Equal3.IN6
+MAin[1] => RA.DATAA
+MAin[1] => RowA.DATAB
+MAin[1] => Equal0.IN6
+MAin[1] => Equal1.IN6
+MAin[1] => Equal3.IN7
+MAin[2] => RA.DATAA
+MAin[2] => RowA.DATAB
+MAin[2] => Equal0.IN5
+MAin[2] => Equal1.IN5
+MAin[2] => Equal3.IN5
+MAin[3] => RA.DATAA
+MAin[3] => RowA.DATAB
+MAin[3] => Equal0.IN4
+MAin[3] => Equal1.IN4
+MAin[3] => Equal3.IN4
+MAin[4] => RA.DATAA
+MAin[4] => RowA.DATAB
+MAin[4] => Equal0.IN3
+MAin[4] => Equal1.IN3
+MAin[4] => Equal3.IN3
+MAin[5] => RA.DATAA
+MAin[5] => RowA.DATAB
+MAin[5] => Equal0.IN2
+MAin[5] => Equal1.IN2
+MAin[5] => Equal3.IN2
+MAin[6] => RA.DATAA
+MAin[6] => RowA.DATAB
+MAin[6] => Equal0.IN1
+MAin[6] => Equal1.IN1
+MAin[6] => Equal3.IN1
+MAin[7] => RA.DATAA
+MAin[7] => RowA.DATAB
+MAin[7] => Equal0.IN0
+MAin[7] => Equal1.IN0
+MAin[7] => Equal3.IN0
+MAin[8] => RA.DATAA
+MAin[8] => RowA.DATAB
+MAin[9] => RA.DATAA
+MAin[9] => RDQMH.DATAA
+MAin[9] => RowA.DATAB
+MAin[9] => RDQML.DATAA
+CROW[0] => RBA.DATAB
+CROW[1] => RBA.DATAB
+Din[0] => XOR8MEG.IN1
+Din[0] => CmdDRDIn.DATAB
+Din[0] => WRD[0].DATAIN
+Din[0] => Bank[0].DATAIN
+Din[0] => Equal14.IN2
+Din[0] => Equal15.IN4
+Din[0] => Cmdn8MEGEN.DATAB
+Din[1] => XOR8MEG.IN1
+Din[1] => CmdDRCLK.DATAB
+Din[1] => CmdLEDEN.DATAB
+Din[1] => WRD[1].DATAIN
+Din[1] => Bank[1].DATAIN
+Din[1] => Equal14.IN7
+Din[1] => Equal15.IN7
+Din[2] => CmdUFMPrgm.DATAB
+Din[2] => WRD[2].DATAIN
+Din[2] => Bank[2].DATAIN
+Din[2] => Equal14.IN6
+Din[2] => Equal15.IN3
+Din[2] => Equal16.IN1
+Din[3] => CmdUFMErase.DATAB
+Din[3] => WRD[3].DATAIN
+Din[3] => Bank[3].DATAIN
+Din[3] => Equal14.IN5
+Din[3] => Equal15.IN2
+Din[3] => Equal16.IN0
+Din[4] => WRD[4].DATAIN
+Din[4] => Bank[4].DATAIN
+Din[4] => Equal14.IN4
+Din[4] => Equal15.IN6
+Din[4] => Equal17.IN3
+Din[4] => Equal18.IN0
+Din[4] => Equal19.IN3
+Din[5] => WRD[5].DATAIN
+Din[5] => Bank[5].DATAIN
+Din[5] => Equal14.IN3
+Din[5] => Equal15.IN1
+Din[5] => Equal17.IN2
+Din[5] => Equal18.IN3
+Din[5] => Equal19.IN0
+Din[6] => RA11.IN1
+Din[6] => WRD[6].DATAIN
+Din[6] => Bank[6].DATAIN
+Din[6] => Equal14.IN1
+Din[6] => Equal15.IN5
+Din[6] => Equal17.IN1
+Din[6] => Equal18.IN2
+Din[6] => Equal19.IN2
+Din[7] => WRD[7].DATAIN
+Din[7] => Bank[7].DATAIN
+Din[7] => Equal14.IN0
+Din[7] => Equal15.IN0
+Din[7] => Equal17.IN0
+Din[7] => Equal18.IN1
+Din[7] => Equal19.IN1
+Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
+Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
+Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
+Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
+Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
+Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
+Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
+Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
+nCCAS => WRD[0].CLK
+nCCAS => WRD[1].CLK
+nCCAS => WRD[2].CLK
+nCCAS => WRD[3].CLK
+nCCAS => WRD[4].CLK
+nCCAS => WRD[5].CLK
+nCCAS => WRD[6].CLK
+nCCAS => WRD[7].CLK
+nCCAS => RD.IN0
+nCCAS => CBR.DATAIN
+nCCAS => CASr.DATAIN
+nCRAS => CBR.CLK
+nCRAS => FWEr.CLK
+nCRAS => RowA[0].CLK
+nCRAS => RowA[1].CLK
+nCRAS => RowA[2].CLK
+nCRAS => RowA[3].CLK
+nCRAS => RowA[4].CLK
+nCRAS => RowA[5].CLK
+nCRAS => RowA[6].CLK
+nCRAS => RowA[7].CLK
+nCRAS => RowA[8].CLK
+nCRAS => RowA[9].CLK
+nCRAS => RBA[0]~reg0.CLK
+nCRAS => RBA[1]~reg0.CLK
+nCRAS => LED.IN1
+nCRAS => RASr.DATAIN
+nFWE => RD.IN1
+nFWE => CMDWR.IN1
+nFWE => ADWR.IN1
+nFWE => C1WR.IN1
+nFWE => FWEr.DATAIN
+LED <= LED.DB_MAX_OUTPUT_PORT_TYPE
+RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
+RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
+RD[0] <> RD[0]
+RD[1] <> RD[1]
+RD[2] <> RD[2]
+RD[3] <> RD[3]
+RD[4] <> RD[4]
+RD[5] <> RD[5]
+RD[6] <> RD[6]
+RD[7] <> RD[7]
+nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RCLK => UFMProgram.CLK
+RCLK => UFMErase.CLK
+RCLK => UFMReqErase.CLK
+RCLK => LEDEN.CLK
+RCLK => UFMInitDone.CLK
+RCLK => n8MEGEN.CLK
+RCLK => UFMD.CLK
+RCLK => DRShift.CLK
+RCLK => DRDIn.CLK
+RCLK => DRCLK.CLK
+RCLK => ARShift.CLK
+RCLK => ARCLK.CLK
+RCLK => Ready.CLK
+RCLK => IS[0].CLK
+RCLK => IS[1].CLK
+RCLK => IS[2].CLK
+RCLK => IS[3].CLK
+RCLK => nRowColSel.CLK
+RCLK => RCKEEN.CLK
+RCLK => RA10.CLK
+RCLK => nRWE~reg0.CLK
+RCLK => nRCAS~reg0.CLK
+RCLK => nRRAS~reg0.CLK
+RCLK => nRCS~reg0.CLK
+RCLK => RCKE~reg0.CLK
+RCLK => InitReady.CLK
+RCLK => FS[0].CLK
+RCLK => FS[1].CLK
+RCLK => FS[2].CLK
+RCLK => FS[3].CLK
+RCLK => FS[4].CLK
+RCLK => FS[5].CLK
+RCLK => FS[6].CLK
+RCLK => FS[7].CLK
+RCLK => FS[8].CLK
+RCLK => FS[9].CLK
+RCLK => FS[10].CLK
+RCLK => FS[11].CLK
+RCLK => FS[12].CLK
+RCLK => FS[13].CLK
+RCLK => FS[14].CLK
+RCLK => FS[15].CLK
+RCLK => FS[16].CLK
+RCLK => FS[17].CLK
+RCLK => S[0].CLK
+RCLK => S[1].CLK
+RCLK => CASr3.CLK
+RCLK => CASr2.CLK
+RCLK => CASr.CLK
+RCLK => RASr3.CLK
+RCLK => RASr2.CLK
+RCLK => RASr.CLK
+RCLK => PHI2r3.CLK
+RCLK => PHI2r2.CLK
+RCLK => PHI2r.CLK
+RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE
+RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|RAM2GS|UFM:UFM_inst
+arclk => arclk.IN1
+ardin => ardin.IN1
+arshft => arshft.IN1
+drclk => drclk.IN1
+drdin => drdin.IN1
+drshft => drshft.IN1
+erase => erase.IN1
+oscena => oscena.IN1
+program => program.IN1
+busy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.busy
+drdout <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.drdout
+osc <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.osc
+rtpbusy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.rtpbusy
+
+
+|RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component
+arclk => maxii_ufm_block1.ARCLK
+ardin => maxii_ufm_block1.ARDIN
+arshft => maxii_ufm_block1.ARSHFT
+busy <= maxii_ufm_block1.BUSY
+drclk => maxii_ufm_block1.DRCLK
+drdin => maxii_ufm_block1.DRDIN
+drdout <= maxii_ufm_block1.DRDOUT
+drshft => maxii_ufm_block1.DRSHFT
+erase => maxii_ufm_block1.ERASE
+osc <= maxii_ufm_block1.OSC
+oscena => maxii_ufm_block1.OSCENA
+program => maxii_ufm_block1.PROGRAM
+rtpbusy <= maxii_ufm_block1.BGPBUSY
+
+
diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif
index 5aec3a74367adf592e3e4204d2ddfaeaaa663f4a..fc9f26a2ca9a4b6963903007996407ce6bfbc9be 100644
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diff --git a/CPLD/MAXV/db/RAM2GS.lpc.html b/CPLD/MAXV/db/RAM2GS.lpc.html
index 774a839..dc4c1e4 100644
--- a/CPLD/MAXV/db/RAM2GS.lpc.html
+++ b/CPLD/MAXV/db/RAM2GS.lpc.html
@@ -1,50 +1,50 @@
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_38r_component9000400000000
    UFM_inst9404444400000
    
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_38r_component9000400000000
    UFM_inst9404444400000
    
diff --git a/CPLD/MAXV/db/RAM2GS.lpc.txt b/CPLD/MAXV/db/RAM2GS.lpc.txt
index 008c8b2..dcf99c4 100644
--- a/CPLD/MAXV/db/RAM2GS.lpc.txt
+++ b/CPLD/MAXV/db/RAM2GS.lpc.txt
@@ -1,8 +1,8 @@
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                                                  ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_38r_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; UFM_inst                               ; 9     ; 4              ; 0            ; 4              ; 4      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                  ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; UFM_inst|UFM_altufm_none_38r_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; UFM_inst                               ; 9     ; 4              ; 0            ; 4              ; 4      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD/MAXV/db/RAM2GS.map.cdb b/CPLD/MAXV/db/RAM2GS.map.cdb
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diff --git a/CPLD/MAXV/db/RAM2GS.smart_action.txt b/CPLD/MAXV/db/RAM2GS.smart_action.txt
index c8e8a13..437a63e 100644
--- a/CPLD/MAXV/db/RAM2GS.smart_action.txt
+++ b/CPLD/MAXV/db/RAM2GS.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/CPLD/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAXV/db/RAM2GS.sta.qmsg
index dcb1aa5..0f80f4f 100644
--- a/CPLD/MAXV/db/RAM2GS.sta.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.sta.qmsg
@@ -1,23 +1,23 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692170506145 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692170506151 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 16 03:21:45 2023 " "Processing started: Wed Aug 16 03:21:45 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692170506151 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1692170506151 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1692170506151 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1692170506270 ""}
-{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1692170506479 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170506527 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170506527 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1692170506588 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1692170506795 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS.sdc " "Reading SDC File: '../RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692170506829 ""}
-{ "Info" "ISTA_SDC_FOUND" "../RAM2GS-MAX.sdc " "Reading SDC File: '../RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692170506832 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1692170506843 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1692170506864 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1692170506867 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -19.199 " "Worst-case setup slack is -19.199" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -19.199            -193.279 RCLK  " "  -19.199            -193.279 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -17.454             -17.454 DRCLK  " "  -17.454             -17.454 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -17.440             -17.440 ARCLK  " "  -17.440             -17.440 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.922              -0.922 nCRAS  " "   -0.922              -0.922 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.616               0.000 PHI2  " "    0.616               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506868 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170506868 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -14.753 " "Worst-case hold slack is -14.753" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.753             -14.753 DRCLK  " "  -14.753             -14.753 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.560             -14.560 ARCLK  " "  -14.560             -14.560 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.450              -5.440 PHI2  " "   -2.450              -5.440 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.233              -0.929 nCRAS  " "   -0.233              -0.929 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.155               0.000 RCLK  " "    2.155               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506879 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170506879 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692170506881 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692170506892 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 7.661 " "Worst-case minimum pulse width slack is 7.661" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.661               0.000 RCLK  " "    7.661               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 ARCLK  " "   70.000               0.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 DRCLK  " "   70.000               0.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 PHI2  " "  174.661               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 nCCAS  " "  174.661               0.000 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 nCRAS  " "  174.661               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692170506894 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692170506894 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1692170506962 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692170506984 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692170506985 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692170507036 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 03:21:47 2023 " "Processing ended: Wed Aug 16 03:21:47 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692170507036 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692170507036 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692170507036 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1692170507036 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692496847745 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692496847745 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 22:00:47 2023 " "Processing started: Sat Aug 19 22:00:47 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692496847745 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1692496847745 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1692496847745 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1692496847886 ""}
+{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1692496848667 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496848714 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496848714 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1692496848776 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1692496848974 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692496850737 ""}
+{ "Info" "ISTA_SDC_FOUND" "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc " "Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1692496851056 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1692496851335 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1692496852136 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1692496852136 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -19.199 " "Worst-case setup slack is -19.199" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -19.199            -193.279 RCLK  " "  -19.199            -193.279 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -17.454             -17.454 DRCLK  " "  -17.454             -17.454 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -17.440             -17.440 ARCLK  " "  -17.440             -17.440 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.922              -0.922 nCRAS  " "   -0.922              -0.922 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.616               0.000 PHI2  " "    0.616               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852355 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496852355 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -14.753 " "Worst-case hold slack is -14.753" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.753             -14.753 DRCLK  " "  -14.753             -14.753 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.560             -14.560 ARCLK  " "  -14.560             -14.560 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.450              -5.440 PHI2  " "   -2.450              -5.440 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.233              -0.929 nCRAS  " "   -0.233              -0.929 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.155               0.000 RCLK  " "    2.155               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496852636 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496852636 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692496852870 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1692496853089 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 7.661 " "Worst-case minimum pulse width slack is 7.661" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.661               0.000 RCLK  " "    7.661               0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 ARCLK  " "   70.000               0.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   70.000               0.000 DRCLK  " "   70.000               0.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 PHI2  " "  174.661               0.000 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 nCCAS  " "  174.661               0.000 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  174.661               0.000 nCRAS  " "  174.661               0.000 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1692496853323 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1692496853323 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1692496855761 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692496856433 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1692496856448 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496858746 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 22:00:58 2023 " "Processing ended: Sat Aug 19 22:00:58 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496858746 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496858746 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496858746 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1692496858746 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAXV/db/RAM2GS.sta.rdb
index 4ef61f67e59c8a046650dc8b3a593787620ffa1d..7b87dcc167e764b61e81c5b5ff58f0664ba11e88 100644
GIT binary patch
delta 13668
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diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt
index 9ed277f..6445193 100644
--- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt
@@ -1,91 +1,91 @@
-Assembler report for RAM2GS
-Wed Aug 16 03:21:44 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Aug 16 03:21:44 2023 ;
-; Revision Name         ; RAM2GS                                ;
-; Top-level Entity Name ; RAM2GS                                ;
-; Family                ; MAX V                                 ;
-; Device                ; 5M240ZT100C5                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+-----------------------------------------------------------------------+
-; Assembler Generated Files                                             ;
-+-----------------------------------------------------------------------+
-; File Name                                                             ;
-+-----------------------------------------------------------------------+
-; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
-+-----------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
-+----------------+--------------------------------------------------------------------------------+
-; Option         ; Setting                                                                        ;
-+----------------+--------------------------------------------------------------------------------+
-; JTAG usercode  ; 0x00174623                                                                     ;
-; Checksum       ; 0x00174A1B                                                                     ;
-+----------------+--------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:21:44 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 4662 megabytes
-    Info: Processing ended: Wed Aug 16 03:21:44 2023
-    Info: Elapsed time: 00:00:00
-    Info: Total CPU time (on all processors): 00:00:00
-
-
+Assembler report for RAM2GS
+Sat Aug 19 22:00:42 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sat Aug 19 22:00:42 2023 ;
+; Revision Name         ; RAM2GS                                ;
+; Top-level Entity Name ; RAM2GS                                ;
+; Family                ; MAX V                                 ;
+; Device                ; 5M240ZT100C5                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------+
+; Assembler Generated Files                                ;
++----------------------------------------------------------+
+; File Name                                                ;
++----------------------------------------------------------+
+; //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
++----------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Assembler Device Options: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
++----------------+-------------------------------------------------------------------+
+; Option         ; Setting                                                           ;
++----------------+-------------------------------------------------------------------+
+; JTAG usercode  ; 0x00174623                                                        ;
+; Checksum       ; 0x00174A1B                                                        ;
++----------------+-------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 22:00:40 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4663 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:44 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done
index 9d6b616..f52ad68 100644
--- a/CPLD/MAXV/output_files/RAM2GS.done
+++ b/CPLD/MAXV/output_files/RAM2GS.done
@@ -1 +1 @@
-Wed Aug 16 03:21:47 2023
+Sat Aug 19 22:01:08 2023
diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt
index c3de7e4..089c851 100644
--- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt
@@ -1,762 +1,762 @@
-Fitter report for RAM2GS
-Wed Aug 16 03:21:43 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Pin-Out File
-  6. Fitter Resource Usage Summary
-  7. Input Pins
-  8. Output Pins
-  9. Bidir Pins
- 10. I/O Bank Usage
- 11. All Package Pins
- 12. Output Pin Default Load For Reported TCO
- 13. Fitter Resource Utilization by Entity
- 14. Delay Chain Summary
- 15. Control Signals
- 16. Global & Other Fast Signals
- 17. Routing Usage Summary
- 18. LAB Logic Elements
- 19. LAB-wide Signals
- 20. LAB Signals Sourced
- 21. LAB Signals Sourced Out
- 22. LAB Distinct Inputs
- 23. Fitter Device Options
- 24. Estimated Delay Added for Hold Timing Summary
- 25. Estimated Delay Added for Hold Timing Details
- 26. Fitter Messages
- 27. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------+
-; Fitter Summary                                                      ;
-+-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Wed Aug 16 03:21:43 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2GS                                      ;
-; Top-level Entity Name ; RAM2GS                                      ;
-; Family                ; MAX V                                       ;
-; Device                ; 5M240ZT100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 175 / 240 ( 73 % )                          ;
-; Total pins            ; 63 / 79 ( 80 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                      ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option                                                             ; Setting                        ; Default Value                  ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                             ; 5M240ZT100C5                   ;                                ;
-; Maximum processors allowed for parallel compilation                ; 4                              ;                                ;
-; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
-; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
-; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
-; Use smart compilation                                              ; Off                            ; Off                            ;
-; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
-; Enable compact report table                                        ; Off                            ; Off                            ;
-; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
-; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
-; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
-; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
-; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
-; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
-; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
-; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
-; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
-; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
-; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
-; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
-; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
-; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
-; Slow Slew Rate                                                     ; Off                            ; Off                            ;
-; PCI I/O                                                            ; Off                            ; Off                            ;
-; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
-; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
-; Auto Delay Chains                                                  ; On                             ; On                             ;
-; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
-; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
-; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
-; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
-; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
-; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
-; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
-; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
-; Auto Global Clock                                                  ; On                             ; On                             ;
-; Auto Global Register Control Signals                               ; On                             ; On                             ;
-; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
-+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.04        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.5%      ;
-;     Processors 3-4         ;   1.3%      ;
-+----------------------------+-------------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                       ;
-+---------------------------------------------+-----------------------+
-; Resource                                    ; Usage                 ;
-+---------------------------------------------+-----------------------+
-; Total logic elements                        ; 175 / 240 ( 73 % )    ;
-;     -- Combinational with no register       ; 77                    ;
-;     -- Register only                        ; 21                    ;
-;     -- Combinational with a register        ; 77                    ;
-;                                             ;                       ;
-; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 57                    ;
-;     -- 3 input functions                    ; 46                    ;
-;     -- 2 input functions                    ; 42                    ;
-;     -- 1 input functions                    ; 8                     ;
-;     -- 0 input functions                    ; 1                     ;
-;                                             ;                       ;
-; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 159                   ;
-;     -- arithmetic mode                      ; 16                    ;
-;     -- qfbk mode                            ; 8                     ;
-;     -- register cascade mode                ; 0                     ;
-;     -- synchronous clear/load mode          ; 29                    ;
-;     -- asynchronous clear/load mode         ; 0                     ;
-;                                             ;                       ;
-; Total registers                             ; 98 / 240 ( 41 % )     ;
-; Total LABs                                  ; 22 / 24 ( 92 % )      ;
-; Logic elements in carry chains              ; 17                    ;
-; Virtual pins                                ; 0                     ;
-; I/O pins                                    ; 63 / 79 ( 80 % )      ;
-;     -- Clock pins                           ; 2 / 4 ( 50 % )        ;
-;                                             ;                       ;
-; UFM blocks                                  ; 1 / 1 ( 100 % )       ;
-;                                             ;                       ;
-;     -- Total Fixed Point DSP Blocks         ; 0                     ;
-;     -- Total Floating Point DSP Blocks      ; 0                     ;
-;                                             ;                       ;
-; Global signals                              ; 4                     ;
-;     -- Global clocks                        ; 4 / 4 ( 100 % )       ;
-; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 20.2% / 22.0% / 18.3% ;
-; Peak interconnect usage (total/H/V)         ; 20.2% / 22.0% / 18.3% ;
-; Maximum fan-out                             ; 55                    ;
-; Highest non-global fan-out                  ; 41                    ;
-; Total fan-out                               ; 661                   ;
-; Average fan-out                             ; 2.77                  ;
-+---------------------------------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                      ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 22                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage                                              ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 25 / 41 ( 61 % )  ; 3.3V          ; --           ;
-+----------+-------------------+---------------+--------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                             ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; 1        ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 10       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 11       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 13       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
-; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 25       ; 19         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 32       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 46       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 58       ; 48         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 60       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 61       ; 49         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 62       ; 50         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 63       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
-; 64       ; 51         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 65       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 75       ; 61         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 76       ; 62         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 77       ; 63         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 78       ; 64         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 79       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 81       ; 65         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 82       ; 66         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 83       ; 67         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 84       ; 68         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 85       ; 69         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 86       ; 70         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 87       ; 71         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 88       ; 72         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 93       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO                    ;
-+----------------------------+-------+------------------------+
-; I/O Standard               ; Load  ; Termination Resistance ;
-+----------------------------+-------+------------------------+
-; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
-; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
-; 2.5 V                      ; 10 pF ; Not Available          ;
-; 1.8 V                      ; 10 pF ; Not Available          ;
-; 1.5 V                      ; 10 pF ; Not Available          ;
-; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 1.2 V                      ; 10 pF ; Not Available          ;
-; LVDS_E_3R                  ; 10 pF ; Not Available          ;
-; RSDS_E_3R                  ; 10 pF ; Not Available          ;
-+----------------------------+-------+------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                        ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS                                                   ; 175 (175)   ; 98           ; 1          ; 63   ; 0            ; 77 (77)      ; 21 (21)           ; 77 (77)          ; 17 (17)         ; 8 (8)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; LED     ; Output   ; --            ;
-; RBA[0]  ; Output   ; --            ;
-; RBA[1]  ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; nRCS    ; Output   ; --            ;
-; RCKE    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; nRRAS   ; Output   ; --            ;
-; nRCAS   ; Output   ; --            ;
-; RDQMH   ; Output   ; --            ;
-; RDQML   ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-; nCRAS   ; Input    ; (0)           ;
-; MAin[0] ; Input    ; (0)           ;
-; MAin[1] ; Input    ; (0)           ;
-; MAin[2] ; Input    ; (0)           ;
-; MAin[3] ; Input    ; (0)           ;
-; MAin[4] ; Input    ; (0)           ;
-; MAin[5] ; Input    ; (0)           ;
-; MAin[6] ; Input    ; (0)           ;
-; MAin[7] ; Input    ; (0)           ;
-; MAin[8] ; Input    ; (0)           ;
-; MAin[9] ; Input    ; (0)           ;
-; RCLK    ; Input    ; (0)           ;
-; nCCAS   ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; CROW[1] ; Input    ; (1)           ;
-; PHI2    ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (1)           ;
-; nFWE    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (1)           ;
-; Din[7]  ; Input    ; (1)           ;
-; Din[1]  ; Input    ; (1)           ;
-; Din[4]  ; Input    ; (1)           ;
-; Din[2]  ; Input    ; (1)           ;
-; Din[3]  ; Input    ; (1)           ;
-; Din[5]  ; Input    ; (1)           ;
-+---------+----------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                 ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name       ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1 ; LC_X5_Y1_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdLEDEN~1 ; LC_X5_Y1_N3 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1    ; LC_X7_Y1_N7 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; PHI2       ; PIN_52      ; 22      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-; RCLK       ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; RD~16      ; LC_X3_Y4_N5 ; 8       ; Output enable           ; no     ; --                   ; --               ;
-; Ready      ; LC_X3_Y2_N8 ; 40      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~6  ; LC_X4_Y2_N2 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; nCCAS      ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-; nCRAS      ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
-+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-
-
-+----------------------------------------------------------------------+
-; Global & Other Fast Signals                                          ;
-+-------+----------+---------+----------------------+------------------+
-; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
-+-------+----------+---------+----------------------+------------------+
-; PHI2  ; PIN_52   ; 22      ; Global Clock         ; GCLK3            ;
-; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
-; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
-; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK1            ;
-+-------+----------+---------+----------------------+------------------+
-
-
-+--------------------------------------------+
-; Routing Usage Summary                      ;
-+-----------------------+--------------------+
-; Routing Resource Type ; Usage              ;
-+-----------------------+--------------------+
-; C4s                   ; 128 / 784 ( 16 % ) ;
-; Direct links          ; 37 / 888 ( 4 % )   ;
-; Global clocks         ; 4 / 4 ( 100 % )    ;
-; LAB clocks            ; 15 / 32 ( 47 % )   ;
-; LUT chains            ; 15 / 216 ( 7 % )   ;
-; Local interconnects   ; 239 / 888 ( 27 % ) ;
-; R4s                   ; 117 / 704 ( 17 % ) ;
-+-----------------------+--------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 7.95) ; Number of LABs  (Total = 22) ;
-+--------------------------------------------+------------------------------+
-; 1                                          ; 1                            ;
-; 2                                          ; 1                            ;
-; 3                                          ; 1                            ;
-; 4                                          ; 0                            ;
-; 5                                          ; 0                            ;
-; 6                                          ; 2                            ;
-; 7                                          ; 1                            ;
-; 8                                          ; 4                            ;
-; 9                                          ; 2                            ;
-; 10                                         ; 10                           ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals                                                  ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.50) ; Number of LABs  (Total = 22) ;
-+------------------------------------+------------------------------+
-; 1 Clock                            ; 13                           ;
-; 1 Clock enable                     ; 6                            ;
-; 1 Sync. clear                      ; 3                            ;
-; 1 Sync. load                       ; 2                            ;
-; 2 Clocks                           ; 9                            ;
-+------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 8.18) ; Number of LABs  (Total = 22) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 1                            ;
-; 2                                           ; 1                            ;
-; 3                                           ; 1                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 0                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 2                            ;
-; 8                                           ; 3                            ;
-; 9                                           ; 3                            ;
-; 10                                          ; 7                            ;
-; 11                                          ; 3                            ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.45) ; Number of LABs  (Total = 22) ;
-+-------------------------------------------------+------------------------------+
-; 0                                               ; 0                            ;
-; 1                                               ; 1                            ;
-; 2                                               ; 1                            ;
-; 3                                               ; 2                            ;
-; 4                                               ; 2                            ;
-; 5                                               ; 4                            ;
-; 6                                               ; 4                            ;
-; 7                                               ; 5                            ;
-; 8                                               ; 3                            ;
-+-------------------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 9.32) ; Number of LABs  (Total = 22) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 0                            ;
-; 2                                           ; 3                            ;
-; 3                                           ; 0                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 1                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 1                            ;
-; 8                                           ; 4                            ;
-; 9                                           ; 3                            ;
-; 10                                          ; 0                            ;
-; 11                                          ; 2                            ;
-; 12                                          ; 1                            ;
-; 13                                          ; 3                            ;
-; 14                                          ; 1                            ;
-; 15                                          ; 0                            ;
-; 16                                          ; 1                            ;
-; 17                                          ; 0                            ;
-; 18                                          ; 0                            ;
-; 19                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Fitter Device Options                                                   ;
-+----------------------------------------------+--------------------------+
-; Option                                       ; Setting                  ;
-+----------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
-; Enable device-wide output enable (DEV_OE)    ; Off                      ;
-; Enable INIT_DONE output                      ; Off                      ;
-; Configuration scheme                         ; Passive Serial           ;
-; Reserve all unused pins                      ; As output driving ground ;
-+----------------------------------------------+--------------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary              ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; I/O             ; nCRAS                ; 2.4               ;
-; I/O             ; RCLK                 ; 1.8               ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details              ;
-+-----------------+----------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; nCCAS           ; CBR                  ; 2.449             ;
-; PHI2            ; PHI2r                ; 0.948             ;
-; nCRAS           ; RASr                 ; 0.420             ;
-+-----------------+----------------------+-------------------+
-Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device 5M80ZT100C5 is compatible
-    Info (176445): Device 5M80ZT100I5 is compatible
-    Info (176445): Device 5M160ZT100C5 is compatible
-    Info (176445): Device 5M160ZT100I5 is compatible
-    Info (176445): Device 5M240ZT100I5 is compatible
-    Info (176445): Device 5M570ZT100C5 is compatible
-    Info (176445): Device 5M570ZT100I5 is compatible
-Info (332104): Reading SDC File: '../RAM2GS.sdc'
-Info (332104): Reading SDC File: '../RAM2GS-MAX.sdc'
-Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
-Info (332111): Found 6 clocks
-    Info (332111):   Period   Clock Name
-    Info (332111): ======== ============
-    Info (332111):  200.000        ARCLK
-    Info (332111):  200.000        DRCLK
-    Info (332111):  350.000        nCCAS
-    Info (332111):  350.000        nCRAS
-    Info (332111):  350.000         PHI2
-    Info (332111):   16.000         RCLK
-Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 40
-Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
-    Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 13
-Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
-Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-    Info (186217): Destination "LED~0" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-    Info (186217): Destination "RASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
-Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-    Info (186217): Destination "CBR" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 17
-    Info (186217): Destination "RD~16" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 59
-    Info (186217): Destination "CASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
-Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
-Info (186079): Completed Auto Global Promotion Operation
-Info (176234): Starting register packing
-Info (186468): Started processing fast register assignments
-Info (186469): Finished processing fast register assignments
-Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 16% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.25 seconds.
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 5344 megabytes
-    Info: Processing ended: Wed Aug 16 03:21:43 2023
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg.
-
-
+Fitter report for RAM2GS
+Sat Aug 19 22:00:00 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Pin-Out File
+  6. Fitter Resource Usage Summary
+  7. Input Pins
+  8. Output Pins
+  9. Bidir Pins
+ 10. I/O Bank Usage
+ 11. All Package Pins
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Delay Chain Summary
+ 15. Control Signals
+ 16. Global & Other Fast Signals
+ 17. Routing Usage Summary
+ 18. LAB Logic Elements
+ 19. LAB-wide Signals
+ 20. LAB Signals Sourced
+ 21. LAB Signals Sourced Out
+ 22. LAB Distinct Inputs
+ 23. Fitter Device Options
+ 24. Estimated Delay Added for Hold Timing Summary
+ 25. Estimated Delay Added for Hold Timing Details
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Fitter Summary                                                      ;
++-----------------------+---------------------------------------------+
+; Fitter Status         ; Successful - Sat Aug 19 22:00:00 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; RAM2GS                                      ;
+; Top-level Entity Name ; RAM2GS                                      ;
+; Family                ; MAX V                                       ;
+; Device                ; 5M240ZT100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 175 / 240 ( 73 % )                          ;
+; Total pins            ; 63 / 79 ( 80 % )                            ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                             ;
++-----------------------+---------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                      ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option                                                             ; Setting                        ; Default Value                  ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device                                                             ; 5M240ZT100C5                   ;                                ;
+; Maximum processors allowed for parallel compilation                ; 4                              ;                                ;
+; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
+; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
+; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
+; Use smart compilation                                              ; Off                            ; Off                            ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
+; Enable compact report table                                        ; Off                            ; Off                            ;
+; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
+; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
+; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
+; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
+; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
+; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
+; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
+; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
+; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
+; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
+; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
+; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
+; Slow Slew Rate                                                     ; Off                            ; Off                            ;
+; PCI I/O                                                            ; Off                            ; Off                            ;
+; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
+; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
+; Auto Delay Chains                                                  ; On                             ; On                             ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
+; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
+; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
+; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
+; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
+; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
+; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
+; Auto Global Clock                                                  ; On                             ; On                             ;
+; Auto Global Register Control Signals                               ; On                             ; On                             ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.6%      ;
+;     Processors 3-4         ;   0.4%      ;
++----------------------------+-------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 175 / 240 ( 73 % )    ;
+;     -- Combinational with no register       ; 77                    ;
+;     -- Register only                        ; 21                    ;
+;     -- Combinational with a register        ; 77                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 57                    ;
+;     -- 3 input functions                    ; 46                    ;
+;     -- 2 input functions                    ; 42                    ;
+;     -- 1 input functions                    ; 8                     ;
+;     -- 0 input functions                    ; 1                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 159                   ;
+;     -- arithmetic mode                      ; 16                    ;
+;     -- qfbk mode                            ; 8                     ;
+;     -- register cascade mode                ; 0                     ;
+;     -- synchronous clear/load mode          ; 29                    ;
+;     -- asynchronous clear/load mode         ; 0                     ;
+;                                             ;                       ;
+; Total registers                             ; 98 / 240 ( 41 % )     ;
+; Total LABs                                  ; 22 / 24 ( 92 % )      ;
+; Logic elements in carry chains              ; 17                    ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 63 / 79 ( 80 % )      ;
+;     -- Clock pins                           ; 2 / 4 ( 50 % )        ;
+;                                             ;                       ;
+; UFM blocks                                  ; 1 / 1 ( 100 % )       ;
+;                                             ;                       ;
+;     -- Total Fixed Point DSP Blocks         ; 0                     ;
+;     -- Total Floating Point DSP Blocks      ; 0                     ;
+;                                             ;                       ;
+; Global signals                              ; 4                     ;
+;     -- Global clocks                        ; 4 / 4 ( 100 % )       ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 20.2% / 22.0% / 18.3% ;
+; Peak interconnect usage (total/H/V)         ; 20.2% / 22.0% / 18.3% ;
+; Maximum fan-out                             ; 55                    ;
+; Highest non-global fan-out                  ; 41                    ;
+; Total fan-out                               ; 661                   ;
+; Average fan-out                             ; 2.77                  ;
++---------------------------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                      ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 22                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                               ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
+; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RD~16                ; -                   ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage                                              ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
+; 2        ; 25 / 41 ( 61 % )  ; 3.3V          ; --           ;
++----------+-------------------+---------------+--------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                             ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1        ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 10       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 11       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 13       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
+; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 25       ; 19         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 32       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 46       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 58       ; 48         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 60       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 61       ; 49         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 62       ; 50         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 63       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
+; 64       ; 51         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 65       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 66       ; 52         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 75       ; 61         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 76       ; 62         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 77       ; 63         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 78       ; 64         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 79       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 81       ; 65         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 82       ; 66         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 83       ; 67         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 84       ; 68         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 85       ; 69         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 86       ; 70         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 87       ; 71         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 88       ; 72         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 93       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO                    ;
++----------------------------+-------+------------------------+
+; I/O Standard               ; Load  ; Termination Resistance ;
++----------------------------+-------+------------------------+
+; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
+; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
+; 2.5 V                      ; 10 pF ; Not Available          ;
+; 1.8 V                      ; 10 pF ; Not Available          ;
+; 1.5 V                      ; 10 pF ; Not Available          ;
+; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+; 1.2 V                      ; 10 pF ; Not Available          ;
+; LVDS_E_3R                  ; 10 pF ; Not Available          ;
+; RSDS_E_3R                  ; 10 pF ; Not Available          ;
++----------------------------+-------+------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                        ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2GS                                                   ; 175 (175)   ; 98           ; 1          ; 63   ; 0            ; 77 (77)      ; 21 (21)           ; 77 (77)          ; 17 (17)         ; 8 (8)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;       |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work         ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------+
+; Delay Chain Summary                ;
++---------+----------+---------------+
+; Name    ; Pin Type ; Pad to Core 0 ;
++---------+----------+---------------+
+; Dout[0] ; Output   ; --            ;
+; Dout[1] ; Output   ; --            ;
+; Dout[2] ; Output   ; --            ;
+; Dout[3] ; Output   ; --            ;
+; Dout[4] ; Output   ; --            ;
+; Dout[5] ; Output   ; --            ;
+; Dout[6] ; Output   ; --            ;
+; Dout[7] ; Output   ; --            ;
+; LED     ; Output   ; --            ;
+; RBA[0]  ; Output   ; --            ;
+; RBA[1]  ; Output   ; --            ;
+; RA[0]   ; Output   ; --            ;
+; RA[1]   ; Output   ; --            ;
+; RA[2]   ; Output   ; --            ;
+; RA[3]   ; Output   ; --            ;
+; RA[4]   ; Output   ; --            ;
+; RA[5]   ; Output   ; --            ;
+; RA[6]   ; Output   ; --            ;
+; RA[7]   ; Output   ; --            ;
+; RA[8]   ; Output   ; --            ;
+; RA[9]   ; Output   ; --            ;
+; RA[10]  ; Output   ; --            ;
+; RA[11]  ; Output   ; --            ;
+; nRCS    ; Output   ; --            ;
+; RCKE    ; Output   ; --            ;
+; nRWE    ; Output   ; --            ;
+; nRRAS   ; Output   ; --            ;
+; nRCAS   ; Output   ; --            ;
+; RDQMH   ; Output   ; --            ;
+; RDQML   ; Output   ; --            ;
+; RD[0]   ; Bidir    ; (0)           ;
+; RD[1]   ; Bidir    ; (0)           ;
+; RD[2]   ; Bidir    ; (0)           ;
+; RD[3]   ; Bidir    ; (0)           ;
+; RD[4]   ; Bidir    ; (0)           ;
+; RD[5]   ; Bidir    ; (0)           ;
+; RD[6]   ; Bidir    ; (0)           ;
+; RD[7]   ; Bidir    ; (0)           ;
+; nCRAS   ; Input    ; (0)           ;
+; MAin[0] ; Input    ; (0)           ;
+; MAin[1] ; Input    ; (0)           ;
+; MAin[2] ; Input    ; (0)           ;
+; MAin[3] ; Input    ; (0)           ;
+; MAin[4] ; Input    ; (0)           ;
+; MAin[5] ; Input    ; (0)           ;
+; MAin[6] ; Input    ; (0)           ;
+; MAin[7] ; Input    ; (0)           ;
+; MAin[8] ; Input    ; (0)           ;
+; MAin[9] ; Input    ; (0)           ;
+; RCLK    ; Input    ; (0)           ;
+; nCCAS   ; Input    ; (0)           ;
+; CROW[0] ; Input    ; (1)           ;
+; CROW[1] ; Input    ; (1)           ;
+; PHI2    ; Input    ; (0)           ;
+; Din[6]  ; Input    ; (1)           ;
+; nFWE    ; Input    ; (1)           ;
+; Din[0]  ; Input    ; (1)           ;
+; Din[7]  ; Input    ; (1)           ;
+; Din[1]  ; Input    ; (1)           ;
+; Din[4]  ; Input    ; (1)           ;
+; Din[2]  ; Input    ; (1)           ;
+; Din[3]  ; Input    ; (1)           ;
+; Din[5]  ; Input    ; (1)           ;
++---------+----------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                 ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; Name       ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; CmdDRDIn~1 ; LC_X5_Y1_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
+; CmdLEDEN~1 ; LC_X5_Y1_N3 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; DRDIn~1    ; LC_X7_Y1_N7 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; PHI2       ; PIN_52      ; 22      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
+; RCLK       ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
+; RD~16      ; LC_X3_Y4_N5 ; 8       ; Output enable           ; no     ; --                   ; --               ;
+; Ready      ; LC_X3_Y2_N8 ; 40      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; always8~6  ; LC_X4_Y2_N2 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; nCCAS      ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
+; nCRAS      ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+
+
++----------------------------------------------------------------------+
+; Global & Other Fast Signals                                          ;
++-------+----------+---------+----------------------+------------------+
+; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++-------+----------+---------+----------------------+------------------+
+; PHI2  ; PIN_52   ; 22      ; Global Clock         ; GCLK3            ;
+; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
+; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
+; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK1            ;
++-------+----------+---------+----------------------+------------------+
+
+
++--------------------------------------------+
+; Routing Usage Summary                      ;
++-----------------------+--------------------+
+; Routing Resource Type ; Usage              ;
++-----------------------+--------------------+
+; C4s                   ; 128 / 784 ( 16 % ) ;
+; Direct links          ; 37 / 888 ( 4 % )   ;
+; Global clocks         ; 4 / 4 ( 100 % )    ;
+; LAB clocks            ; 15 / 32 ( 47 % )   ;
+; LUT chains            ; 15 / 216 ( 7 % )   ;
+; Local interconnects   ; 239 / 888 ( 27 % ) ;
+; R4s                   ; 117 / 704 ( 17 % ) ;
++-----------------------+--------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 7.95) ; Number of LABs  (Total = 22) ;
++--------------------------------------------+------------------------------+
+; 1                                          ; 1                            ;
+; 2                                          ; 1                            ;
+; 3                                          ; 1                            ;
+; 4                                          ; 0                            ;
+; 5                                          ; 0                            ;
+; 6                                          ; 2                            ;
+; 7                                          ; 1                            ;
+; 8                                          ; 4                            ;
+; 9                                          ; 2                            ;
+; 10                                         ; 10                           ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.50) ; Number of LABs  (Total = 22) ;
++------------------------------------+------------------------------+
+; 1 Clock                            ; 13                           ;
+; 1 Clock enable                     ; 6                            ;
+; 1 Sync. clear                      ; 3                            ;
+; 1 Sync. load                       ; 2                            ;
+; 2 Clocks                           ; 9                            ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 8.18) ; Number of LABs  (Total = 22) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 1                            ;
+; 2                                           ; 1                            ;
+; 3                                           ; 1                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 0                            ;
+; 6                                           ; 1                            ;
+; 7                                           ; 2                            ;
+; 8                                           ; 3                            ;
+; 9                                           ; 3                            ;
+; 10                                          ; 7                            ;
+; 11                                          ; 3                            ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 5.45) ; Number of LABs  (Total = 22) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 1                            ;
+; 2                                               ; 1                            ;
+; 3                                               ; 2                            ;
+; 4                                               ; 2                            ;
+; 5                                               ; 4                            ;
+; 6                                               ; 4                            ;
+; 7                                               ; 5                            ;
+; 8                                               ; 3                            ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 9.32) ; Number of LABs  (Total = 22) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 3                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 1                            ;
+; 6                                           ; 1                            ;
+; 7                                           ; 1                            ;
+; 8                                           ; 4                            ;
+; 9                                           ; 3                            ;
+; 10                                          ; 0                            ;
+; 11                                          ; 2                            ;
+; 12                                          ; 1                            ;
+; 13                                          ; 3                            ;
+; 14                                          ; 1                            ;
+; 15                                          ; 0                            ;
+; 16                                          ; 1                            ;
+; 17                                          ; 0                            ;
+; 18                                          ; 0                            ;
+; 19                                          ; 1                            ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options                                                   ;
++----------------------------------------------+--------------------------+
+; Option                                       ; Setting                  ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
+; Enable device-wide output enable (DEV_OE)    ; Off                      ;
+; Enable INIT_DONE output                      ; Off                      ;
+; Configuration scheme                         ; Passive Serial           ;
+; Reserve all unused pins                      ; As output driving ground ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; I/O             ; nCRAS                ; 2.4               ;
+; I/O             ; RCLK                 ; 1.8               ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details              ;
++-----------------+----------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; nCCAS           ; CBR                  ; 2.449             ;
+; PHI2            ; PHI2r                ; 0.948             ;
+; nCRAS           ; RASr                 ; 0.420             ;
++-----------------+----------------------+-------------------+
+Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device 5M80ZT100C5 is compatible
+    Info (176445): Device 5M80ZT100I5 is compatible
+    Info (176445): Device 5M160ZT100C5 is compatible
+    Info (176445): Device 5M160ZT100I5 is compatible
+    Info (176445): Device 5M240ZT100I5 is compatible
+    Info (176445): Device 5M570ZT100C5 is compatible
+    Info (176445): Device 5M570ZT100I5 is compatible
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 6 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):  200.000        ARCLK
+    Info (332111):  200.000        DRCLK
+    Info (332111):  350.000        nCCAS
+    Info (332111):  350.000        nCRAS
+    Info (332111):  350.000         PHI2
+    Info (332111):   16.000         RCLK
+Info (186079): Completed User Assigned Global Signals Promotion Operation
+Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
+Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
+    Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
+Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
+Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+    Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
+    Info (186217): Destination "RASr" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
+Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+    Info (186217): Destination "CBR" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
+    Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
+    Info (186217): Destination "CASr" may be non-global or may not use global clock File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
+Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
+Info (186079): Completed Auto Global Promotion Operation
+Info (176234): Starting register packing
+Info (186468): Started processing fast register assignments
+Info (186469): Finished processing fast register assignments
+Info (176235): Finished register packing
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 16% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.25 seconds.
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Info (144001): Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 5347 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:03 2023
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:03
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg.
+
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.smsg b/CPLD/MAXV/output_files/RAM2GS.fit.smsg
index 6df10d8..a3cd98a 100644
--- a/CPLD/MAXV/output_files/RAM2GS.fit.smsg
+++ b/CPLD/MAXV/output_files/RAM2GS.fit.smsg
@@ -1,4 +1,4 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176244): Moving registers into LUTs to improve timing and density
-Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176244): Moving registers into LUTs to improve timing and density
+Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary
index d0026e6..06af7ed 100644
--- a/CPLD/MAXV/output_files/RAM2GS.fit.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Wed Aug 16 03:21:43 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX V
-Device : 5M240ZT100C5
-Timing Models : Final
-Total logic elements : 175 / 240 ( 73 % )
-Total pins : 63 / 79 ( 80 % )
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
+Fitter Status : Successful - Sat Aug 19 22:00:00 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX V
+Device : 5M240ZT100C5
+Timing Models : Final
+Total logic elements : 175 / 240 ( 73 % )
+Total pins : 63 / 79 ( 80 % )
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt
index 7fd9392..93149bd 100644
--- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt
@@ -1,118 +1,118 @@
-Flow report for RAM2GS
-Wed Aug 16 03:21:47 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------+
-; Flow Summary                                                        ;
-+-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Wed Aug 16 03:21:44 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2GS                                      ;
-; Top-level Entity Name ; RAM2GS                                      ;
-; Family                ; MAX V                                       ;
-; Device                ; 5M240ZT100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 175 / 240 ( 73 % )                          ;
-; Total pins            ; 63 / 79 ( 80 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 08/16/2023 03:21:31 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; RAM2GS              ;
-+-------------------+---------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                   ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-; Assignment Name                       ; Value                           ; Default Value ; Entity Name ; Section Id ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID                 ; 207120313862967.169217049105972 ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                ; 85                              ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                ; 0                               ; --            ; --          ; --         ;
-; NUM_PARALLEL_PROCESSORS               ; 4                               ; --            ; --          ; --         ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V                            ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air     ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY              ; output_files                    ; --            ; --          ; --         ;
-+---------------------------------------+---------------------------------+---------------+-------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                        ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:09     ; 1.0                     ; 4702 MB             ; 00:00:24                           ;
-; Fitter               ; 00:00:02     ; 1.0                     ; 5344 MB             ; 00:00:03                           ;
-; Assembler            ; 00:00:00     ; 1.0                     ; 4662 MB             ; 00:00:00                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 4676 MB             ; 00:00:01                           ;
-; Total                ; 00:00:13     ; --                      ; --                  ; 00:00:28                           ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                    ;
-+----------------------+------------------+------------+------------+----------------+
-; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+----------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Fitter               ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Assembler            ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-; Timing Analyzer      ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
-+----------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_sta RAM2GS-MAXV -c RAM2GS
-
-
-
+Flow report for RAM2GS
+Sat Aug 19 22:00:57 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Flow Summary                                                        ;
++-----------------------+---------------------------------------------+
+; Flow Status           ; Successful - Sat Aug 19 22:00:42 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; RAM2GS                                      ;
+; Top-level Entity Name ; RAM2GS                                      ;
+; Family                ; MAX V                                       ;
+; Device                ; 5M240ZT100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 175 / 240 ( 73 % )                          ;
+; Total pins            ; 63 / 79 ( 80 % )                            ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                             ;
++-----------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 08/19/2023 21:59:22 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; RAM2GS              ;
++-------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                   ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name                       ; Value                           ; Default Value ; Entity Name ; Section Id ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID                 ; 207120313862967.169249676112252 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                ; 85                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                ; 0                               ; --            ; --          ; --         ;
+; NUM_PARALLEL_PROCESSORS               ; 4                               ; --            ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V                            ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air     ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY              ; output_files                    ; --            ; --          ; --         ;
++---------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:18     ; 1.0                     ; 4704 MB             ; 00:00:25                           ;
+; Fitter               ; 00:00:07     ; 1.0                     ; 5347 MB             ; 00:00:03                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 4663 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:10     ; 1.0                     ; 4677 MB             ; 00:00:01                           ;
+; Total                ; 00:00:37     ; --                      ; --                  ; 00:00:30                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Fitter               ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Assembler            ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
+; Timing Analyzer      ; ZanePC           ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_sta RAM2GS-MAXV -c RAM2GS
+
+
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.jdi b/CPLD/MAXV/output_files/RAM2GS.jdi
index fff5f81..7568d8e 100644
--- a/CPLD/MAXV/output_files/RAM2GS.jdi
+++ b/CPLD/MAXV/output_files/RAM2GS.jdi
@@ -1,8 +1,8 @@
-
-  
-    
-  
-  
-    
-  
-
+
+  
+    
+  
+  
+    
+  
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt
index 8f7b255..58fb77b 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt
@@ -1,312 +1,312 @@
-Analysis & Synthesis report for RAM2GS
-Wed Aug 16 03:21:40 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis IP Cores Summary
-  9. General Register Statistics
- 10. Inverted Register Statistics
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
- 13. Analysis & Synthesis Messages
- 14. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                              ;
-+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Aug 16 03:21:40 2023       ;
-; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name               ; RAM2GS                                      ;
-; Top-level Entity Name       ; RAM2GS                                      ;
-; Family                      ; MAX V                                       ;
-; Total logic elements        ; 184                                         ;
-; Total pins                  ; 63                                          ;
-; Total virtual pins          ; 0                                           ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
-+-----------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                              ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                           ; Setting            ; Default Value      ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                           ; 5M240ZT100C5       ;                    ;
-; Top-level entity name                                            ; RAM2GS             ; RAM2GS             ;
-; Family name                                                      ; MAX V              ; Cyclone V          ;
-; Maximum processors allowed for parallel compilation              ; 4                  ;                    ;
-; Use smart compilation                                            ; Off                ; Off                ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                      ; Off                ; Off                ;
-; Restructure Multiplexers                                         ; Auto               ; Auto               ;
-; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
-; Preserve fewer node names                                        ; On                 ; On                 ;
-; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
-; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                         ; Auto               ; Auto               ;
-; Safe State Machine                                               ; Off                ; Off                ;
-; Extract Verilog State Machines                                   ; On                 ; On                 ;
-; Extract VHDL State Machines                                      ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
-; Parallel Synthesis                                               ; On                 ; On                 ;
-; NOT Gate Push-Back                                               ; On                 ; On                 ;
-; Power-Up Don't Care                                              ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
-; Remove Duplicate Registers                                       ; On                 ; On                 ;
-; Ignore CARRY Buffers                                             ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
-; Ignore LCELL Buffers                                             ; Off                ; Off                ;
-; Ignore SOFT Buffers                                              ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
-; Optimization Technique                                           ; Balanced           ; Balanced           ;
-; Carry Chain Length                                               ; 70                 ; 70                 ;
-; Auto Carry Chains                                                ; On                 ; On                 ;
-; Auto Open-Drain Pins                                             ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
-; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
-; Allow Synchronous Control Signals                                ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
-; Auto Resource Sharing                                            ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
-; Report Parameter Settings                                        ; On                 ; On                 ;
-; Report Source Assignments                                        ; On                 ; On                 ;
-; Report Connectivity Checks                                       ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
-; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
-; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
-; HDL message level                                                ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
-; Clock MUX Protection                                             ; On                 ; On                 ;
-; Block Design Naming                                              ; Auto               ; Auto               ;
-; Synthesis Effort                                                 ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
-; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                     ;
-+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                             ; Library ;
-+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+---------+
-; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File            ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v    ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v      ;         ;
-; ../RAM2GS.mif                    ; yes             ; User Memory Initialization File  ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/RAM2GS.mif ;         ;
-+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary         ;
-+---------------------------------------------+-------+
-; Resource                                    ; Usage ;
-+---------------------------------------------+-------+
-; Total logic elements                        ; 184   ;
-;     -- Combinational with no register       ; 86    ;
-;     -- Register only                        ; 30    ;
-;     -- Combinational with a register        ; 68    ;
-;                                             ;       ;
-; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 57    ;
-;     -- 3 input functions                    ; 46    ;
-;     -- 2 input functions                    ; 42    ;
-;     -- 1 input functions                    ; 8     ;
-;     -- 0 input functions                    ; 1     ;
-;                                             ;       ;
-; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 168   ;
-;     -- arithmetic mode                      ; 16    ;
-;     -- qfbk mode                            ; 0     ;
-;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 10    ;
-;     -- asynchronous clear/load mode         ; 0     ;
-;                                             ;       ;
-; Total registers                             ; 98    ;
-; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 63    ;
-; UFM blocks                                  ; 1     ;
-; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 55    ;
-; Total fan-out                               ; 662   ;
-; Average fan-out                             ; 2.67  ;
-+---------------------------------------------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                          ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS                                                   ; 184 (184)   ; 98           ; 1          ; 63   ; 0            ; 86 (86)      ; 30 (30)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                               ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; UFM.v           ;
-+--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 98    ;
-; Number of registers using Synchronous Clear  ; 6     ;
-; Number of registers using Synchronous Load   ; 4     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 11    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics                     ;
-+----------------------------------------+---------+
-; Inverted Register                      ; Fan out ;
-+----------------------------------------+---------+
-; nRCS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
-; nRRAS~reg0                             ; 1       ;
-; nRCAS~reg0                             ; 1       ;
-; Total number of inverted registers = 4 ;         ;
-+----------------------------------------+---------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[1]               ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |RAM2GS|CmdLEDEN           ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|C1Submitted        ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                             ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
-; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:21:31 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
-    Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
-Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_38r File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 47
-    Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 150
-Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 91
-Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 201
-Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 30 output pins
-    Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 184 logic cells
-    Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
-    Info: Peak virtual memory: 4702 megabytes
-    Info: Processing ended: Wed Aug 16 03:21:40 2023
-    Info: Elapsed time: 00:00:09
-    Info: Total CPU time (on all processors): 00:00:24
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg.
-
-
+Analysis & Synthesis report for RAM2GS
+Sat Aug 19 21:59:39 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis IP Cores Summary
+  9. General Register Statistics
+ 10. Inverted Register Statistics
+ 11. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 12. Port Connectivity Checks: "UFM:UFM_inst"
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                              ;
++-----------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sat Aug 19 21:59:39 2023       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name               ; RAM2GS                                      ;
+; Top-level Entity Name       ; RAM2GS                                      ;
+; Family                      ; MAX V                                       ;
+; Total logic elements        ; 184                                         ;
+; Total pins                  ; 63                                          ;
+; Total virtual pins          ; 0                                           ;
+; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
++-----------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; 5M240ZT100C5       ;                    ;
+; Top-level entity name                                            ; RAM2GS             ; RAM2GS             ;
+; Family name                                                      ; MAX V              ; Cyclone V          ;
+; Maximum processors allowed for parallel compilation              ; 4                  ;                    ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Restructure Multiplexers                                         ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                         ; Auto               ; Auto               ;
+; Safe State Machine                                               ; Off                ; Off                ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Optimization Technique                                           ; Balanced           ; Balanced           ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Auto Resource Sharing                                            ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                      ;
++------------------------------------------+-----------------+----------------------------------------+---------------------------------------------+---------+
+; File Name with User-Entered Path         ; Used in Netlist ; File Type                              ; File Name with Absolute Path                ; Library ;
++------------------------------------------+-----------------+----------------------------------------+---------------------------------------------+---------+
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; yes             ; User Verilog HDL File                  ; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v    ;         ;
+; //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v   ; yes             ; User Wizard-Generated File             ; //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v      ;         ;
+; RAM2GS.mif                               ; yes             ; Auto-Found Memory Initialization File  ; //ZaneMac/Repos/RAM2GS/CPLD/MAXV/RAM2GS.mif ;         ;
++------------------------------------------+-----------------+----------------------------------------+---------------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary         ;
++---------------------------------------------+-------+
+; Resource                                    ; Usage ;
++---------------------------------------------+-------+
+; Total logic elements                        ; 184   ;
+;     -- Combinational with no register       ; 86    ;
+;     -- Register only                        ; 30    ;
+;     -- Combinational with a register        ; 68    ;
+;                                             ;       ;
+; Logic element usage by number of LUT inputs ;       ;
+;     -- 4 input functions                    ; 57    ;
+;     -- 3 input functions                    ; 46    ;
+;     -- 2 input functions                    ; 42    ;
+;     -- 1 input functions                    ; 8     ;
+;     -- 0 input functions                    ; 1     ;
+;                                             ;       ;
+; Logic elements by mode                      ;       ;
+;     -- normal mode                          ; 168   ;
+;     -- arithmetic mode                      ; 16    ;
+;     -- qfbk mode                            ; 0     ;
+;     -- register cascade mode                ; 0     ;
+;     -- synchronous clear/load mode          ; 10    ;
+;     -- asynchronous clear/load mode         ; 0     ;
+;                                             ;       ;
+; Total registers                             ; 98    ;
+; Total logic cells in carry chains           ; 17    ;
+; I/O pins                                    ; 63    ;
+; UFM blocks                                  ; 1     ;
+; Maximum fan-out node                        ; RCLK  ;
+; Maximum fan-out                             ; 55    ;
+; Total fan-out                               ; 662   ;
+; Average fan-out                             ; 2.67  ;
++---------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                          ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Entity Name         ; Library Name ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2GS                                                   ; 184 (184)   ; 98           ; 1          ; 63   ; 0            ; 86 (86)      ; 30 (30)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; RAM2GS              ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;       |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work         ;
++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                               ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; UFM.v           ;
++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 98    ;
+; Number of registers using Synchronous Clear  ; 6     ;
+; Number of registers using Synchronous Load   ; 4     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 11    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; nRCS~reg0                              ; 1       ;
+; nRWE~reg0                              ; 1       ;
+; nRRAS~reg0                             ; 1       ;
+; nRCAS~reg0                             ; 1       ;
+; Total number of inverted registers = 4 ;         ;
++----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[1]               ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |RAM2GS|CmdLEDEN           ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|C1Submitted        ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                             ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 21:59:20 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (12021): Found 1 design units, including 1 entities, in source file //zanemac/repos/ram2gs/cpld/ram2gs-max.v
+    Info (12023): Found entity 1: RAM2GS File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
+Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
+    Info (12023): Found entity 1: UFM_altufm_none_38r File: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47
+    Info (12023): Found entity 2: UFM File: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150
+Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
+Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
+Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201
+Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
+Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 25 input pins
+    Info (21059): Implemented 30 output pins
+    Info (21060): Implemented 8 bidirectional pins
+    Info (21061): Implemented 184 logic cells
+    Info (21070): Implemented 1 User Flash Memory blocks
+Info (144001): Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
+    Info: Peak virtual memory: 4704 megabytes
+    Info: Processing ended: Sat Aug 19 21:59:41 2023
+    Info: Elapsed time: 00:00:21
+    Info: Total CPU time (on all processors): 00:00:25
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg.
+
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.smsg b/CPLD/MAXV/output_files/RAM2GS.map.smsg
index 73b2291..64963c6 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.smsg
+++ b/CPLD/MAXV/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(60): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
-Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 173
+Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
+Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 73
+Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 173
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary
index 7ae7434..46cea88 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Wed Aug 16 03:21:40 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX V
-Total logic elements : 184
-Total pins : 63
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
+Analysis & Synthesis Status : Successful - Sat Aug 19 21:59:39 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX V
+Total logic elements : 184
+Total pins : 63
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2GS.pin b/CPLD/MAXV/output_files/RAM2GS.pin
index 88c2384..e0ccecf 100644
--- a/CPLD/MAXV/output_files/RAM2GS.pin
+++ b/CPLD/MAXV/output_files/RAM2GS.pin
@@ -1,165 +1,165 @@
- -- Copyright (C) 2019  Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions 
- -- and other software and tools, and any partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Intel Program License 
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors.  Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.8V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 1:       3.3V
- --                  Bank 2:       3.3V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-CHIP  "RAM2GS"  ASSIGNED TO AN: 5M240ZT100C5
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : 1         : gnd    :                   :         :           :                
-RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
-GND                          : 10        : gnd    :                   :         :           :                
-GND                          : 11        : gnd    :                   :         :           :                
-RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-VCCINT                       : 13        : power  :                   : 1.8V    :           :                
-RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
-TMS                          : 22        : input  :                   :         : 1         :                
-TDI                          : 23        : input  :                   :         : 1         :                
-TCK                          : 24        : input  :                   :         : 1         :                
-TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
-GND                          : 32        : gnd    :                   :         :           :                
-Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
-GND                          : 46        : gnd    :                   :         :           :                
-Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
-nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 58        :        :                   :         : 2         :                
-VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
-GND                          : 60        : gnd    :                   :         :           :                
-GND*                         : 61        :        :                   :         : 2         :                
-GND*                         : 62        :        :                   :         : 2         :                
-VCCINT                       : 63        : power  :                   : 1.8V    :           :                
-GND*                         : 64        :        :                   :         : 2         :                
-GND                          : 65        : gnd    :                   :         :           :                
-GND*                         : 66        :        :                   :         : 2         :                
-nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 75        :        :                   :         : 2         :                
-GND*                         : 76        :        :                   :         : 2         :                
-GND*                         : 77        :        :                   :         : 2         :                
-GND*                         : 78        :        :                   :         : 2         :                
-GND                          : 79        : gnd    :                   :         :           :                
-VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
-GND*                         : 81        :        :                   :         : 2         :                
-GND*                         : 82        :        :                   :         : 2         :                
-GND*                         : 83        :        :                   :         : 2         :                
-GND*                         : 84        :        :                   :         : 2         :                
-GND*                         : 85        :        :                   :         : 2         :                
-GND*                         : 86        :        :                   :         : 2         :                
-GND*                         : 87        :        :                   :         : 2         :                
-LED                          : 88        : output : 3.3-V LVTTL       :         : 2         : Y              
-RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-GND                          : 93        : gnd    :                   :         :           :                
-VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
-RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
-RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.8V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+CHIP  "RAM2GS"  ASSIGNED TO AN: 5M240ZT100C5
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : 1         : gnd    :                   :         :           :                
+RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
+GND                          : 10        : gnd    :                   :         :           :                
+GND                          : 11        : gnd    :                   :         :           :                
+RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+VCCINT                       : 13        : power  :                   : 1.8V    :           :                
+RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
+TMS                          : 22        : input  :                   :         : 1         :                
+TDI                          : 23        : input  :                   :         : 1         :                
+TCK                          : 24        : input  :                   :         : 1         :                
+TDO                          : 25        : output :                   :         : 1         :                
+RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
+GND                          : 32        : gnd    :                   :         :           :                
+Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
+Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
+VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
+GND                          : 46        : gnd    :                   :         :           :                
+Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
+nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
+PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
+Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
+GND*                         : 58        :        :                   :         : 2         :                
+VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
+GND                          : 60        : gnd    :                   :         :           :                
+GND*                         : 61        :        :                   :         : 2         :                
+GND*                         : 62        :        :                   :         : 2         :                
+VCCINT                       : 63        : power  :                   : 1.8V    :           :                
+GND*                         : 64        :        :                   :         : 2         :                
+GND                          : 65        : gnd    :                   :         :           :                
+GND*                         : 66        :        :                   :         : 2         :                
+nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
+GND*                         : 75        :        :                   :         : 2         :                
+GND*                         : 76        :        :                   :         : 2         :                
+GND*                         : 77        :        :                   :         : 2         :                
+GND*                         : 78        :        :                   :         : 2         :                
+GND                          : 79        : gnd    :                   :         :           :                
+VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
+GND*                         : 81        :        :                   :         : 2         :                
+GND*                         : 82        :        :                   :         : 2         :                
+GND*                         : 83        :        :                   :         : 2         :                
+GND*                         : 84        :        :                   :         : 2         :                
+GND*                         : 85        :        :                   :         : 2         :                
+GND*                         : 86        :        :                   :         : 2         :                
+GND*                         : 87        :        :                   :         : 2         :                
+LED                          : 88        : output : 3.3-V LVTTL       :         : 2         : Y              
+RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+GND                          : 93        : gnd    :                   :         :           :                
+VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
+RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
+RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
+nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD/MAXV/output_files/RAM2GS.sld b/CPLD/MAXV/output_files/RAM2GS.sld
index f7d3ed7..41a6030 100644
--- a/CPLD/MAXV/output_files/RAM2GS.sld
+++ b/CPLD/MAXV/output_files/RAM2GS.sld
@@ -1 +1 @@
-
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt
index cebfa15..ce3d966 100644
--- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt
@@ -1,1010 +1,1011 @@
-Timing Analyzer report for RAM2GS
-Wed Aug 16 03:21:47 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Timing Analyzer Summary
-  3. Parallel Compilation
-  4. SDC File List
-  5. Clocks
-  6. Fmax Summary
-  7. Setup Summary
-  8. Hold Summary
-  9. Recovery Summary
- 10. Removal Summary
- 11. Minimum Pulse Width Summary
- 12. Setup: 'RCLK'
- 13. Setup: 'DRCLK'
- 14. Setup: 'ARCLK'
- 15. Setup: 'nCRAS'
- 16. Setup: 'PHI2'
- 17. Hold: 'DRCLK'
- 18. Hold: 'ARCLK'
- 19. Hold: 'PHI2'
- 20. Hold: 'nCRAS'
- 21. Hold: 'RCLK'
- 22. Setup Transfers
- 23. Hold Transfers
- 24. Report TCCS
- 25. Report RSKM
- 26. Unconstrained Paths Summary
- 27. Clock Status Summary
- 28. Unconstrained Input Ports
- 29. Unconstrained Output Ports
- 30. Unconstrained Input Ports
- 31. Unconstrained Output Ports
- 32. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                     ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Timing Analyzer       ; Legacy Timing Analyzer                              ;
-; Revision Name         ; RAM2GS                                              ;
-; Device Family         ; MAX V                                               ;
-; Device Name           ; 5M240ZT100C5                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Slow Model                                          ;
-; Rise/Fall Delays      ; Unavailable                                         ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------+
-; SDC File List                                         ;
-+-------------------+--------+--------------------------+
-; SDC File Path     ; Status ; Read at                  ;
-+-------------------+--------+--------------------------+
-; ../RAM2GS.sdc     ; OK     ; Wed Aug 16 03:21:46 2023 ;
-; ../RAM2GS-MAX.sdc ; OK     ; Wed Aug 16 03:21:46 2023 ;
-+-------------------+--------+--------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                              ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-; nCCAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
-; nCRAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
-; PHI2       ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
-; RCLK       ; Base ; 16.000  ; 62.5 MHz  ; 0.000 ; 8.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-
-
-+-------------------------------------------------+
-; Fmax Summary                                    ;
-+-----------+-----------------+------------+------+
-; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
-; 12.41 MHz ; 12.41 MHz       ; PHI2       ;      ;
-; 40.56 MHz ; 40.56 MHz       ; RCLK       ;      ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; RCLK  ; -19.199 ; -193.279      ;
-; DRCLK ; -17.454 ; -17.454       ;
-; ARCLK ; -17.440 ; -17.440       ;
-; nCRAS ; -0.922  ; -0.922        ;
-; PHI2  ; 0.616   ; 0.000         ;
-+-------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; DRCLK ; -14.753 ; -14.753       ;
-; ARCLK ; -14.560 ; -14.560       ;
-; PHI2  ; -2.450  ; -5.440        ;
-; nCRAS ; -0.233  ; -0.929        ;
-; RCLK  ; 2.155   ; 0.000         ;
-+-------+---------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+---------------------------------+
-; Minimum Pulse Width Summary     ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; RCLK  ; 7.661   ; 0.000         ;
-; ARCLK ; 70.000  ; 0.000         ;
-; DRCLK ; 70.000  ; 0.000         ;
-; PHI2  ; 174.661 ; 0.000         ;
-; nCCAS ; 174.661 ; 0.000         ;
-; nCRAS ; 174.661 ; 0.000         ;
-+-------+---------+---------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK'                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -19.199 ; CmdSubmitted                                                                                ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 13.028     ;
-; -19.197 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 13.026     ;
-; -16.599 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 12.542     ;
-; -16.300 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 12.243     ;
-; -15.432 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.375     ;
-; -15.385 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.328     ;
-; -15.098 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.041     ;
-; -14.428 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 8.257      ;
-; -14.428 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 8.257      ;
-; -14.252 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 10.195     ;
-; -13.058 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 9.001      ;
-; -12.462 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.291      ;
-; -12.389 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.218      ;
-; -12.232 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 8.175      ;
-; -12.187 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.016      ;
-; -11.557 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 7.500      ;
-; -11.066 ; CmdLEDEN                                                                                    ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 4.895      ;
-; -10.731 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 6.674      ;
-; -10.002 ; CmdUFMPrgm                                                                                  ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.831      ;
-; -10.001 ; CmdUFMPrgm                                                                                  ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.830      ;
-; -9.594  ; CmdUFMErase                                                                                 ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.423      ;
-; -9.594  ; CmdUFMErase                                                                                 ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.423      ;
-; -8.652  ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 24.331     ;
-; -7.992  ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.671     ;
-; -7.982  ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.661     ;
-; -7.382  ; FS[5]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.061     ;
-; -7.322  ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.001     ;
-; -6.635  ; FS[16]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 22.314     ;
-; -6.318  ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.997     ;
-; -5.975  ; FS[17]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.654     ;
-; -5.761  ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.440     ;
-; -5.365  ; FS[5]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.044     ;
-; -5.275  ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.954     ;
-; -4.998  ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.677     ;
-; -4.838  ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.517     ;
-; -4.581  ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.260     ;
-; -4.532  ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.211     ;
-; -4.521  ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.200     ;
-; -4.400  ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.079     ;
-; -4.338  ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.017     ;
-; -4.336  ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.015     ;
-; -4.307  ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.986     ;
-; -4.301  ; Ready                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.980     ;
-; -4.237  ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.916     ;
-; -4.178  ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.857     ;
-; -4.127  ; UFMInitDone                                                                                 ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.806     ;
-; -3.797  ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.476     ;
-; -3.647  ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.326     ;
-; -3.606  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 8.000        ; 0.867      ; 12.152     ;
-; -3.556  ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.235     ;
-; -3.457  ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.136     ;
-; -3.408  ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.087     ;
-; -3.358  ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.037     ;
-; -3.358  ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.037     ;
-; -3.348  ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.027     ;
-; -3.319  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 8.000        ; 0.867      ; 11.865     ;
-; -3.258  ; FS[7]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.937     ;
-; -3.209  ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.888     ;
-; -3.157  ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.836     ;
-; -3.147  ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.826     ;
-; -3.137  ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.816     ;
-; -3.037  ; FS[5]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.716     ;
-; -2.822  ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.501     ;
-; -2.748  ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.427     ;
-; -2.621  ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.300     ;
-; -2.600  ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.279     ;
-; -2.533  ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.212     ;
-; -2.531  ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.210     ;
-; -2.351  ; FS[12]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.030     ;
-; -2.316  ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.995     ;
-; -2.306  ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.985     ;
-; -2.295  ; Ready                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.974     ;
-; -2.283  ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.962     ;
-; -2.150  ; FS[11]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.829     ;
-; -2.110  ; UFMInitDone                                                                                 ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.789     ;
-; -2.052  ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.731     ;
-; -2.005  ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.684     ;
-; -1.830  ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.509     ;
-; -1.804  ; FS[4]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.483     ;
-; -1.711  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 1.000        ; 4.946      ; 7.336      ;
-; -1.669  ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.348     ;
-; -1.659  ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.338     ;
-; -1.584  ; RASr2                                                                                       ; Ready       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.263     ;
-; -1.566  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 1.000        ; 4.946      ; 7.191      ;
-; -1.548  ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.227     ;
-; -1.539  ; FS[2]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.218     ;
-; -1.515  ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 1.000        ; 4.946      ; 7.140      ;
-; -1.416  ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.095     ;
-; -1.398  ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.077     ;
-; -1.387  ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.066     ;
-; -1.309  ; FS[13]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.988     ;
-; -1.255  ; FS[4]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.934     ;
-; -0.930  ; FS[7]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.609     ;
-; -0.855  ; Ready                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.534     ;
-; -0.855  ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.534     ;
-; -0.711  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 2.000        ; 4.946      ; 7.336      ;
-; -0.668  ; FS[6]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.347     ;
-; -0.662  ; FS[10]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.341     ;
-; -0.640  ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.319     ;
-; -0.566  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 2.000        ; 4.946      ; 7.191      ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -17.454 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -0.867     ; 4.587      ;
-; -17.247 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -0.867     ; 4.380      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -17.440 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 8.000        ; -2.477     ; 2.963      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Setup: 'nCRAS'                                                                                          ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.922  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 6.337      ;
-; 0.483   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.932      ;
-; 0.484   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.931      ;
-; 0.612   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.803      ;
-; 0.614   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.801      ;
-; 0.617   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.798      ;
-; 0.617   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.798      ;
-; 0.620   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.795      ;
-; 1.871   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.544      ;
-; 1.872   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.543      ;
-; 1.873   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.542      ;
-; 1.873   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.542      ;
-; 169.485 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 175.000      ; 9.682      ; 14.876     ;
-; 344.485 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 350.000      ; 9.682      ; 14.876     ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2'                                                                                            ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-; 0.616   ; LEDEN     ; XOR8MEG      ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 6.913      ;
-; 2.044   ; n8MEGEN   ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 6.850      ; 6.485      ;
-; 2.563   ; Ready     ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 6.850      ; 5.966      ;
-; 3.707   ; n8MEGEN   ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 3.822      ;
-; 4.090   ; LEDEN     ; CmdLEDEN     ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 3.439      ;
-; 134.696 ; Bank[5]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.983     ;
-; 134.696 ; Bank[5]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.983     ;
-; 134.893 ; Bank[6]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.786     ;
-; 134.893 ; Bank[6]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.786     ;
-; 135.326 ; Bank[5]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.353     ;
-; 135.523 ; Bank[6]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.156     ;
-; 136.383 ; Bank[7]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.296     ;
-; 136.383 ; Bank[7]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.296     ;
-; 136.569 ; Bank[5]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.110     ;
-; 136.569 ; Bank[5]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.110     ;
-; 136.596 ; Bank[5]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.083     ;
-; 136.596 ; Bank[5]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.083     ;
-; 136.766 ; Bank[6]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.913     ;
-; 136.766 ; Bank[6]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.913     ;
-; 136.793 ; Bank[6]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.886     ;
-; 136.793 ; Bank[6]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.886     ;
-; 137.013 ; Bank[7]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.666     ;
-; 137.370 ; Bank[3]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.309     ;
-; 137.370 ; Bank[3]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.309     ;
-; 137.570 ; Bank[2]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.109     ;
-; 137.570 ; Bank[2]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.109     ;
-; 138.000 ; Bank[3]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.679     ;
-; 138.134 ; Bank[4]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.545     ;
-; 138.134 ; Bank[4]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.545     ;
-; 138.200 ; Bank[2]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.479     ;
-; 138.256 ; Bank[7]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.423     ;
-; 138.256 ; Bank[7]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.423     ;
-; 138.283 ; Bank[7]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.396     ;
-; 138.283 ; Bank[7]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.396     ;
-; 138.764 ; Bank[4]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.915     ;
-; 139.060 ; Bank[1]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.619     ;
-; 139.060 ; Bank[1]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.619     ;
-; 139.243 ; Bank[3]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.436     ;
-; 139.243 ; Bank[3]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.436     ;
-; 139.270 ; Bank[3]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.409     ;
-; 139.270 ; Bank[3]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.409     ;
-; 139.443 ; Bank[2]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.236     ;
-; 139.443 ; Bank[2]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.236     ;
-; 139.470 ; Bank[2]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.209     ;
-; 139.470 ; Bank[2]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.209     ;
-; 139.690 ; Bank[1]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.989     ;
-; 140.007 ; Bank[4]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.672     ;
-; 140.007 ; Bank[4]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.672     ;
-; 140.034 ; Bank[4]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.645     ;
-; 140.034 ; Bank[4]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.645     ;
-; 140.811 ; Bank[0]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.868     ;
-; 140.811 ; Bank[0]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.868     ;
-; 140.933 ; Bank[1]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.746     ;
-; 140.933 ; Bank[1]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.746     ;
-; 140.960 ; Bank[1]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.719     ;
-; 140.960 ; Bank[1]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.719     ;
-; 141.441 ; Bank[0]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.238     ;
-; 141.566 ; Bank[5]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.113     ;
-; 141.763 ; Bank[6]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 32.916     ;
-; 142.684 ; Bank[0]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.995     ;
-; 142.684 ; Bank[0]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.995     ;
-; 142.711 ; Bank[0]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.968     ;
-; 142.711 ; Bank[0]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.968     ;
-; 143.253 ; Bank[7]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.426     ;
-; 144.240 ; Bank[3]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 30.439     ;
-; 144.440 ; Bank[2]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 30.239     ;
-; 145.004 ; Bank[4]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 29.675     ;
-; 145.930 ; Bank[1]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 28.749     ;
-; 146.502 ; Bank[5]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 28.177     ;
-; 146.699 ; Bank[6]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 27.980     ;
-; 147.681 ; Bank[0]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 26.998     ;
-; 148.189 ; Bank[7]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 26.490     ;
-; 149.176 ; Bank[3]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.503     ;
-; 149.376 ; Bank[2]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.303     ;
-; 149.579 ; Bank[5]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.100     ;
-; 149.579 ; Bank[5]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.100     ;
-; 149.776 ; Bank[6]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.903     ;
-; 149.776 ; Bank[6]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.903     ;
-; 149.940 ; Bank[4]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.739     ;
-; 150.866 ; Bank[1]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.813     ;
-; 151.266 ; Bank[7]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.413     ;
-; 151.266 ; Bank[7]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.413     ;
-; 152.253 ; Bank[3]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.426     ;
-; 152.253 ; Bank[3]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.426     ;
-; 152.453 ; Bank[2]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.226     ;
-; 152.453 ; Bank[2]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.226     ;
-; 152.617 ; Bank[0]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.062     ;
-; 153.017 ; Bank[4]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.662     ;
-; 153.017 ; Bank[4]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.662     ;
-; 153.633 ; Bank[5]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.046     ;
-; 153.830 ; Bank[6]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.849     ;
-; 153.943 ; Bank[1]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.736     ;
-; 153.943 ; Bank[1]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.736     ;
-; 155.320 ; Bank[7]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 19.359     ;
-; 155.694 ; Bank[0]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.985     ;
-; 155.694 ; Bank[0]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.985     ;
-; 156.307 ; Bank[3]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.372     ;
-; 156.507 ; Bank[2]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.172     ;
-; 157.071 ; Bank[4]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 17.608     ;
-; 157.997 ; Bank[1]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 16.682     ;
-+---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -14.753 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.867     ; 4.380      ;
-; -14.546 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.867     ; 4.587      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -14.560 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -2.477     ; 2.963      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Hold: 'PHI2'                                                                                               ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -2.450  ; LEDEN       ; CmdLEDEN     ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 3.439      ;
-; -2.067  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 3.822      ;
-; -0.923  ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.850      ; 5.966      ;
-; -0.404  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.850      ; 6.485      ;
-; 1.024   ; LEDEN       ; XOR8MEG      ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 6.913      ;
-; 3.430   ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.469      ;
-; 4.434   ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.473      ;
-; 4.435   ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.474      ;
-; 5.287   ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.326      ;
-; 5.416   ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.455      ;
-; 10.780  ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 10.819     ;
-; 11.355  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 11.394     ;
-; 11.356  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 11.395     ;
-; 15.750  ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.789     ;
-; 15.750  ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.789     ;
-; 15.777  ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.816     ;
-; 15.777  ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.816     ;
-; 17.020  ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.059     ;
-; 17.650  ; CmdEnable   ; CmdLEDEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.689     ;
-; 17.650  ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.689     ;
-; 182.870 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.909      ;
-; 183.351 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.390      ;
-; 184.621 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.660      ;
-; 185.340 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.379     ;
-; 185.547 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.586     ;
-; 186.111 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.150     ;
-; 186.311 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.350     ;
-; 186.369 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.408     ;
-; 187.091 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.130     ;
-; 187.298 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.337     ;
-; 188.017 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.056     ;
-; 188.120 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.159     ;
-; 188.310 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.349     ;
-; 188.581 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.620     ;
-; 188.781 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.820     ;
-; 188.788 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.827     ;
-; 188.985 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.024     ;
-; 189.046 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.085     ;
-; 189.610 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.649     ;
-; 189.768 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.807     ;
-; 189.810 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.849     ;
-; 190.061 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 15.100     ;
-; 190.797 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 15.836     ;
-; 190.987 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.026     ;
-; 191.258 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.297     ;
-; 191.455 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.494     ;
-; 191.551 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.590     ;
-; 191.751 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.790     ;
-; 192.287 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.326     ;
-; 192.484 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.523     ;
-; 192.738 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.777     ;
-; 194.228 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 19.267     ;
-; 194.425 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 19.464     ;
-; 201.959 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 26.998     ;
-; 203.710 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 28.749     ;
-; 204.636 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 29.675     ;
-; 205.200 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 30.239     ;
-; 205.400 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 30.439     ;
-; 206.387 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.426     ;
-; 206.929 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.968     ;
-; 206.929 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.968     ;
-; 206.956 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.995     ;
-; 206.956 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.995     ;
-; 207.877 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 32.916     ;
-; 208.074 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.113     ;
-; 208.199 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.238     ;
-; 208.680 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.719     ;
-; 208.680 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.719     ;
-; 208.707 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.746     ;
-; 208.707 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.746     ;
-; 208.829 ; Bank[0]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.868     ;
-; 208.829 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.868     ;
-; 209.606 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.645     ;
-; 209.606 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.645     ;
-; 209.633 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.672     ;
-; 209.633 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.672     ;
-; 209.950 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.989     ;
-; 210.170 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.209     ;
-; 210.170 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.209     ;
-; 210.197 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.236     ;
-; 210.197 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.236     ;
-; 210.370 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.409     ;
-; 210.370 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.409     ;
-; 210.397 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.436     ;
-; 210.397 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.436     ;
-; 210.580 ; Bank[1]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.619     ;
-; 210.580 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.619     ;
-; 210.876 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.915     ;
-; 211.357 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.396     ;
-; 211.357 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.396     ;
-; 211.384 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.423     ;
-; 211.384 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.423     ;
-; 211.440 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.479     ;
-; 211.506 ; Bank[4]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.545     ;
-; 211.506 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.545     ;
-; 211.640 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.679     ;
-; 212.070 ; Bank[2]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.109     ;
-; 212.070 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.109     ;
-; 212.270 ; Bank[3]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.309     ;
-; 212.270 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.309     ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS'                                                                                           ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.233  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.542      ;
-; -0.233  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.542      ;
-; -0.232  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.543      ;
-; -0.231  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.544      ;
-; 1.020   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.795      ;
-; 1.023   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.798      ;
-; 1.023   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.798      ;
-; 1.026   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.801      ;
-; 1.028   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.803      ;
-; 1.156   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.931      ;
-; 1.157   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.932      ;
-; 2.562   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 6.337      ;
-; 5.155   ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 9.682      ; 14.876     ;
-; 180.155 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -175.000     ; 9.682      ; 14.876     ;
-+---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK'                                                                                            ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; 2.155 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 4.946      ; 7.140      ;
-; 2.206 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 4.946      ; 7.191      ;
-; 2.351 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 4.946      ; 7.336      ;
-; 3.155 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -1.000       ; 4.946      ; 7.140      ;
-; 3.206 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -1.000       ; 4.946      ; 7.191      ;
-; 3.266 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.305      ;
-; 3.351 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -1.000       ; 4.946      ; 7.336      ;
-; 3.374 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.413      ;
-; 3.459 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.498      ;
-; 3.468 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.507      ;
-; 3.781 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.820      ;
-; 3.803 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.842      ;
-; 3.813 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.852      ;
-; 3.828 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.867      ;
-; 3.850 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.889      ;
-; 4.032 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.071      ;
-; 4.092 ; CASr3       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.131      ;
-; 4.618 ; RASr2       ; RASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.657      ;
-; 4.858 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.897      ;
-; 4.858 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.897      ;
-; 5.228 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
-; 5.229 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
-; 5.230 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.269      ;
-; 5.247 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.286      ;
-; 5.252 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.291      ;
-; 5.254 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.293      ;
-; 5.267 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.306      ;
-; 5.270 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.309      ;
-; 5.280 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.319      ;
-; 5.291 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.330      ;
-; 5.309 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.348      ;
-; 5.316 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.355      ;
-; 5.316 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.355      ;
-; 5.321 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.360      ;
-; 5.322 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.361      ;
-; 5.335 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.374      ;
-; 5.429 ; UFMD        ; UFMD        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.468      ;
-; 5.440 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
-; 5.440 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
-; 5.441 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.441 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.441 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.452 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
-; 5.452 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
-; 5.453 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.492      ;
-; 5.453 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.492      ;
-; 5.454 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.493      ;
-; 5.456 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.495      ;
-; 5.466 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.505      ;
-; 5.467 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.506      ;
-; 5.530 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.569      ;
-; 5.533 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.572      ;
-; 5.553 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.592      ;
-; 5.560 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.599      ;
-; 5.676 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.715      ;
-; 5.684 ; CASr3       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.723      ;
-; 5.963 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
-; 5.964 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
-; 5.987 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.026      ;
-; 6.002 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.041      ;
-; 6.005 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.044      ;
-; 6.015 ; FS[0]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.054      ;
-; 6.016 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.055      ;
-; 6.107 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
-; 6.131 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.170      ;
-; 6.146 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.185      ;
-; 6.149 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.188      ;
-; 6.159 ; FS[0]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.198      ;
-; 6.251 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
-; 6.293 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.332      ;
-; 6.395 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.434      ;
-; 6.416 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.455      ;
-; 6.442 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
-; 6.442 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
-; 6.443 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.482      ;
-; 6.454 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
-; 6.455 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.494      ;
-; 6.456 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.495      ;
-; 6.458 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.497      ;
-; 6.460 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.499      ;
-; 6.477 ; PHI2r3      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.516      ;
-; 6.477 ; PHI2r3      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.516      ;
-; 6.482 ; RASr2       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.521      ;
-; 6.534 ; IS[0]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.573      ;
-; 6.578 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.617      ;
-; 6.586 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.625      ;
-; 6.587 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.626      ;
-; 6.598 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
-; 6.599 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.638      ;
-; 6.730 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.769      ;
-; 6.731 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.770      ;
-; 6.742 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
-; 6.782 ; FS[11]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
-; 6.782 ; FS[11]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
-; 6.782 ; FS[11]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
-; 6.782 ; FS[11]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
-; 6.795 ; FS[0]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
-; 6.795 ; FS[0]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
-; 6.795 ; FS[0]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
-; 6.795 ; FS[0]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 31    ; 31   ;
-; Unconstrained Input Port Paths  ; 249   ; 249  ;
-; Unconstrained Output Ports      ; 38    ; 38   ;
-; Unconstrained Output Port Paths ; 78    ; 78   ;
-+---------------------------------+-------+------+
-
-
-+-------------------------------------+
-; Clock Status Summary                ;
-+--------+-------+------+-------------+
-; Target ; Clock ; Type ; Status      ;
-+--------+-------+------+-------------+
-; ARCLK  ; ARCLK ; Base ; Constrained ;
-; DRCLK  ; DRCLK ; Base ; Constrained ;
-; PHI2   ; PHI2  ; Base ; Constrained ;
-; RCLK   ; RCLK  ; Base ; Constrained ;
-; nCCAS  ; nCCAS ; Base ; Constrained ;
-; nCRAS  ; nCRAS ; Base ; Constrained ;
-+--------+-------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Wed Aug 16 03:21:45 2023
-Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
-Info: qsta_default_script.tcl version: #1
-Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332104): Reading SDC File: '../RAM2GS.sdc'
-Info (332104): Reading SDC File: '../RAM2GS-MAX.sdc'
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
-Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -19.199
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):   -19.199            -193.279 RCLK 
-    Info (332119):   -17.454             -17.454 DRCLK 
-    Info (332119):   -17.440             -17.440 ARCLK 
-    Info (332119):    -0.922              -0.922 nCRAS 
-    Info (332119):     0.616               0.000 PHI2 
-Info (332146): Worst-case hold slack is -14.753
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):   -14.753             -14.753 DRCLK 
-    Info (332119):   -14.560             -14.560 ARCLK 
-    Info (332119):    -2.450              -5.440 PHI2 
-    Info (332119):    -0.233              -0.929 nCRAS 
-    Info (332119):     2.155               0.000 RCLK 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 7.661
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     7.661               0.000 RCLK 
-    Info (332119):    70.000               0.000 ARCLK 
-    Info (332119):    70.000               0.000 DRCLK 
-    Info (332119):   174.661               0.000 PHI2 
-    Info (332119):   174.661               0.000 nCCAS 
-    Info (332119):   174.661               0.000 nCRAS 
-Info (332001): The selected device family is not supported by the report_metastability command.
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 4676 megabytes
-    Info: Processing ended: Wed Aug 16 03:21:47 2023
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:01
-
-
+Timing Analyzer report for RAM2GS
+Sat Aug 19 22:00:58 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Fmax Summary
+  7. Setup Summary
+  8. Hold Summary
+  9. Recovery Summary
+ 10. Removal Summary
+ 11. Minimum Pulse Width Summary
+ 12. Setup: 'RCLK'
+ 13. Setup: 'DRCLK'
+ 14. Setup: 'ARCLK'
+ 15. Setup: 'nCRAS'
+ 16. Setup: 'PHI2'
+ 17. Hold: 'DRCLK'
+ 18. Hold: 'ARCLK'
+ 19. Hold: 'PHI2'
+ 20. Hold: 'nCRAS'
+ 21. Hold: 'RCLK'
+ 22. Setup Transfers
+ 23. Hold Transfers
+ 24. Report TCCS
+ 25. Report RSKM
+ 26. Unconstrained Paths Summary
+ 27. Clock Status Summary
+ 28. Unconstrained Input Ports
+ 29. Unconstrained Output Ports
+ 30. Unconstrained Input Ports
+ 31. Unconstrained Output Ports
+ 32. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; RAM2GS                                              ;
+; Device Family         ; MAX V                                               ;
+; Device Name           ; 5M240ZT100C5                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Slow Model                                          ;
+; Rise/Fall Delays      ; Unavailable                                         ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------+
+; SDC File List                                                                  ;
++--------------------------------------------+--------+--------------------------+
+; SDC File Path                              ; Status ; Read at                  ;
++--------------------------------------------+--------+--------------------------+
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc     ; OK     ; Sat Aug 19 22:00:50 2023 ;
+; //ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc ; OK     ; Sat Aug 19 22:00:51 2023 ;
++--------------------------------------------+--------+--------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                              ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
+; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
+; nCCAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
+; nCRAS      ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
+; PHI2       ; Base ; 350.000 ; 2.86 MHz  ; 0.000 ; 175.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
+; RCLK       ; Base ; 16.000  ; 62.5 MHz  ; 0.000 ; 8.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+
+
++-------------------------------------------------+
+; Fmax Summary                                    ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
+; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
+; 12.41 MHz ; 12.41 MHz       ; PHI2       ;      ;
+; 40.56 MHz ; 40.56 MHz       ; RCLK       ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++---------------------------------+
+; Setup Summary                   ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; RCLK  ; -19.199 ; -193.279      ;
+; DRCLK ; -17.454 ; -17.454       ;
+; ARCLK ; -17.440 ; -17.440       ;
+; nCRAS ; -0.922  ; -0.922        ;
+; PHI2  ; 0.616   ; 0.000         ;
++-------+---------+---------------+
+
+
++---------------------------------+
+; Hold Summary                    ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; DRCLK ; -14.753 ; -14.753       ;
+; ARCLK ; -14.560 ; -14.560       ;
+; PHI2  ; -2.450  ; -5.440        ;
+; nCRAS ; -0.233  ; -0.929        ;
+; RCLK  ; 2.155   ; 0.000         ;
++-------+---------+---------------+
+
+
+--------------------
+; Recovery Summary ;
+--------------------
+No paths to report.
+
+
+-------------------
+; Removal Summary ;
+-------------------
+No paths to report.
+
+
++---------------------------------+
+; Minimum Pulse Width Summary     ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; RCLK  ; 7.661   ; 0.000         ;
+; ARCLK ; 70.000  ; 0.000         ;
+; DRCLK ; 70.000  ; 0.000         ;
+; PHI2  ; 174.661 ; 0.000         ;
+; nCCAS ; 174.661 ; 0.000         ;
+; nCRAS ; 174.661 ; 0.000         ;
++-------+---------+---------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'RCLK'                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; -19.199 ; CmdSubmitted                                                                                ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 13.028     ;
+; -19.197 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 13.026     ;
+; -16.599 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 12.542     ;
+; -16.300 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 12.243     ;
+; -15.432 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.375     ;
+; -15.385 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.328     ;
+; -15.098 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 11.041     ;
+; -14.428 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 8.257      ;
+; -14.428 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 8.257      ;
+; -14.252 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 10.195     ;
+; -13.058 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 9.001      ;
+; -12.462 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.291      ;
+; -12.389 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.218      ;
+; -12.232 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 8.175      ;
+; -12.187 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 6.016      ;
+; -11.557 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 7.500      ;
+; -11.066 ; CmdLEDEN                                                                                    ; LEDEN       ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 4.895      ;
+; -10.731 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 1.000        ; -4.736     ; 6.674      ;
+; -10.002 ; CmdUFMPrgm                                                                                  ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.831      ;
+; -10.001 ; CmdUFMPrgm                                                                                  ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.830      ;
+; -9.594  ; CmdUFMErase                                                                                 ; UFMProgram  ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.423      ;
+; -9.594  ; CmdUFMErase                                                                                 ; UFMErase    ; PHI2         ; RCLK        ; 1.000        ; -6.850     ; 3.423      ;
+; -8.652  ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 24.331     ;
+; -7.992  ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.671     ;
+; -7.982  ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.661     ;
+; -7.382  ; FS[5]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.061     ;
+; -7.322  ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 23.001     ;
+; -6.635  ; FS[16]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 22.314     ;
+; -6.318  ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.997     ;
+; -5.975  ; FS[17]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.654     ;
+; -5.761  ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.440     ;
+; -5.365  ; FS[5]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 21.044     ;
+; -5.275  ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.954     ;
+; -4.998  ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.677     ;
+; -4.838  ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.517     ;
+; -4.581  ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.260     ;
+; -4.532  ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.211     ;
+; -4.521  ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.200     ;
+; -4.400  ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.079     ;
+; -4.338  ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.017     ;
+; -4.336  ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 20.015     ;
+; -4.307  ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.986     ;
+; -4.301  ; Ready                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.980     ;
+; -4.237  ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.916     ;
+; -4.178  ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.857     ;
+; -4.127  ; UFMInitDone                                                                                 ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.806     ;
+; -3.797  ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.476     ;
+; -3.647  ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.326     ;
+; -3.606  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 8.000        ; 0.867      ; 12.152     ;
+; -3.556  ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.235     ;
+; -3.457  ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.136     ;
+; -3.408  ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.087     ;
+; -3.358  ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.037     ;
+; -3.358  ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.037     ;
+; -3.348  ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 19.027     ;
+; -3.319  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 8.000        ; 0.867      ; 11.865     ;
+; -3.258  ; FS[7]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.937     ;
+; -3.209  ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.888     ;
+; -3.157  ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.836     ;
+; -3.147  ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.826     ;
+; -3.137  ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.816     ;
+; -3.037  ; FS[5]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.716     ;
+; -2.822  ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.501     ;
+; -2.748  ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.427     ;
+; -2.621  ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.300     ;
+; -2.600  ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.279     ;
+; -2.533  ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.212     ;
+; -2.531  ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.210     ;
+; -2.351  ; FS[12]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 18.030     ;
+; -2.316  ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.995     ;
+; -2.306  ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.985     ;
+; -2.295  ; Ready                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.974     ;
+; -2.283  ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.962     ;
+; -2.150  ; FS[11]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.829     ;
+; -2.110  ; UFMInitDone                                                                                 ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.789     ;
+; -2.052  ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.731     ;
+; -2.005  ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.684     ;
+; -1.830  ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.509     ;
+; -1.804  ; FS[4]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.483     ;
+; -1.711  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 1.000        ; 4.946      ; 7.336      ;
+; -1.669  ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.348     ;
+; -1.659  ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.338     ;
+; -1.584  ; RASr2                                                                                       ; Ready       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.263     ;
+; -1.566  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 1.000        ; 4.946      ; 7.191      ;
+; -1.548  ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.227     ;
+; -1.539  ; FS[2]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.218     ;
+; -1.515  ; PHI2                                                                                        ; PHI2r       ; PHI2         ; RCLK        ; 1.000        ; 4.946      ; 7.140      ;
+; -1.416  ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.095     ;
+; -1.398  ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.077     ;
+; -1.387  ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 17.066     ;
+; -1.309  ; FS[13]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.988     ;
+; -1.255  ; FS[4]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.934     ;
+; -0.930  ; FS[7]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.609     ;
+; -0.855  ; Ready                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.534     ;
+; -0.855  ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.534     ;
+; -0.711  ; nCCAS                                                                                       ; CASr        ; nCCAS        ; RCLK        ; 2.000        ; 4.946      ; 7.336      ;
+; -0.668  ; FS[6]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.347     ;
+; -0.662  ; FS[10]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.341     ;
+; -0.640  ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 16.000       ; 0.000      ; 16.319     ;
+; -0.566  ; nCRAS                                                                                       ; RASr        ; nCRAS        ; RCLK        ; 2.000        ; 4.946      ; 7.191      ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -17.454 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -0.867     ; 4.587      ;
+; -17.247 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 8.000        ; -0.867     ; 4.380      ;
+; 100.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -17.440 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 8.000        ; -2.477     ; 2.963      ;
+; 100.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Setup: 'nCRAS'                                                                                          ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -0.922  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 6.337      ;
+; 0.483   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.932      ;
+; 0.484   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.931      ;
+; 0.612   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.803      ;
+; 0.614   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.801      ;
+; 0.617   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.798      ;
+; 0.617   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.798      ;
+; 0.620   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 4.795      ;
+; 1.871   ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.544      ;
+; 1.872   ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.543      ;
+; 1.873   ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.542      ;
+; 1.873   ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 1.000        ; 4.736      ; 3.542      ;
+; 169.485 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 175.000      ; 9.682      ; 14.876     ;
+; 344.485 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 350.000      ; 9.682      ; 14.876     ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2'                                                                                            ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; 0.616   ; LEDEN     ; XOR8MEG      ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 6.913      ;
+; 2.044   ; n8MEGEN   ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 6.850      ; 6.485      ;
+; 2.563   ; Ready     ; RA11         ; RCLK         ; PHI2        ; 2.000        ; 6.850      ; 5.966      ;
+; 3.707   ; n8MEGEN   ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 3.822      ;
+; 4.090   ; LEDEN     ; CmdLEDEN     ; RCLK         ; PHI2        ; 1.000        ; 6.850      ; 3.439      ;
+; 134.696 ; Bank[5]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.983     ;
+; 134.696 ; Bank[5]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.983     ;
+; 134.893 ; Bank[6]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.786     ;
+; 134.893 ; Bank[6]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.786     ;
+; 135.326 ; Bank[5]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.353     ;
+; 135.523 ; Bank[6]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 39.156     ;
+; 136.383 ; Bank[7]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.296     ;
+; 136.383 ; Bank[7]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.296     ;
+; 136.569 ; Bank[5]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.110     ;
+; 136.569 ; Bank[5]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.110     ;
+; 136.596 ; Bank[5]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.083     ;
+; 136.596 ; Bank[5]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 38.083     ;
+; 136.766 ; Bank[6]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.913     ;
+; 136.766 ; Bank[6]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.913     ;
+; 136.793 ; Bank[6]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.886     ;
+; 136.793 ; Bank[6]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.886     ;
+; 137.013 ; Bank[7]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.666     ;
+; 137.370 ; Bank[3]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.309     ;
+; 137.370 ; Bank[3]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.309     ;
+; 137.570 ; Bank[2]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.109     ;
+; 137.570 ; Bank[2]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 37.109     ;
+; 138.000 ; Bank[3]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.679     ;
+; 138.134 ; Bank[4]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.545     ;
+; 138.134 ; Bank[4]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.545     ;
+; 138.200 ; Bank[2]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.479     ;
+; 138.256 ; Bank[7]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.423     ;
+; 138.256 ; Bank[7]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.423     ;
+; 138.283 ; Bank[7]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.396     ;
+; 138.283 ; Bank[7]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 36.396     ;
+; 138.764 ; Bank[4]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.915     ;
+; 139.060 ; Bank[1]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.619     ;
+; 139.060 ; Bank[1]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.619     ;
+; 139.243 ; Bank[3]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.436     ;
+; 139.243 ; Bank[3]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.436     ;
+; 139.270 ; Bank[3]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.409     ;
+; 139.270 ; Bank[3]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.409     ;
+; 139.443 ; Bank[2]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.236     ;
+; 139.443 ; Bank[2]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.236     ;
+; 139.470 ; Bank[2]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.209     ;
+; 139.470 ; Bank[2]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 35.209     ;
+; 139.690 ; Bank[1]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.989     ;
+; 140.007 ; Bank[4]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.672     ;
+; 140.007 ; Bank[4]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.672     ;
+; 140.034 ; Bank[4]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.645     ;
+; 140.034 ; Bank[4]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 34.645     ;
+; 140.811 ; Bank[0]   ; CmdLEDEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.868     ;
+; 140.811 ; Bank[0]   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.868     ;
+; 140.933 ; Bank[1]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.746     ;
+; 140.933 ; Bank[1]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.746     ;
+; 140.960 ; Bank[1]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.719     ;
+; 140.960 ; Bank[1]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.719     ;
+; 141.441 ; Bank[0]   ; CmdSubmitted ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.238     ;
+; 141.566 ; Bank[5]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 33.113     ;
+; 141.763 ; Bank[6]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 32.916     ;
+; 142.684 ; Bank[0]   ; CmdDRDIn     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.995     ;
+; 142.684 ; Bank[0]   ; CmdDRCLK     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.995     ;
+; 142.711 ; Bank[0]   ; CmdUFMErase  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.968     ;
+; 142.711 ; Bank[0]   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.968     ;
+; 143.253 ; Bank[7]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 31.426     ;
+; 144.240 ; Bank[3]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 30.439     ;
+; 144.440 ; Bank[2]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 30.239     ;
+; 145.004 ; Bank[4]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 29.675     ;
+; 145.930 ; Bank[1]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 28.749     ;
+; 146.502 ; Bank[5]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 28.177     ;
+; 146.699 ; Bank[6]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 27.980     ;
+; 147.681 ; Bank[0]   ; XOR8MEG      ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 26.998     ;
+; 148.189 ; Bank[7]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 26.490     ;
+; 149.176 ; Bank[3]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.503     ;
+; 149.376 ; Bank[2]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.303     ;
+; 149.579 ; Bank[5]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.100     ;
+; 149.579 ; Bank[5]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 25.100     ;
+; 149.776 ; Bank[6]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.903     ;
+; 149.776 ; Bank[6]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.903     ;
+; 149.940 ; Bank[4]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 24.739     ;
+; 150.866 ; Bank[1]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.813     ;
+; 151.266 ; Bank[7]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.413     ;
+; 151.266 ; Bank[7]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 23.413     ;
+; 152.253 ; Bank[3]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.426     ;
+; 152.253 ; Bank[3]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.426     ;
+; 152.453 ; Bank[2]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.226     ;
+; 152.453 ; Bank[2]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.226     ;
+; 152.617 ; Bank[0]   ; CmdEnable    ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 22.062     ;
+; 153.017 ; Bank[4]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.662     ;
+; 153.017 ; Bank[4]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.662     ;
+; 153.633 ; Bank[5]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 21.046     ;
+; 153.830 ; Bank[6]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.849     ;
+; 153.943 ; Bank[1]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.736     ;
+; 153.943 ; Bank[1]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 20.736     ;
+; 155.320 ; Bank[7]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 19.359     ;
+; 155.694 ; Bank[0]   ; ADSubmitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.985     ;
+; 155.694 ; Bank[0]   ; C1Submitted  ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.985     ;
+; 156.307 ; Bank[3]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.372     ;
+; 156.507 ; Bank[2]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 18.172     ;
+; 157.071 ; Bank[4]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 17.608     ;
+; 157.997 ; Bank[1]   ; UFMOscEN     ; PHI2         ; PHI2        ; 175.000      ; 0.000      ; 16.682     ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -14.753 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.867     ; 4.380      ;
+; -14.546 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.867     ; 4.587      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -14.560 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -2.477     ; 2.963      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Hold: 'PHI2'                                                                                               ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -2.450  ; LEDEN       ; CmdLEDEN     ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 3.439      ;
+; -2.067  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 3.822      ;
+; -0.923  ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.850      ; 5.966      ;
+; -0.404  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.850      ; 6.485      ;
+; 1.024   ; LEDEN       ; XOR8MEG      ; RCLK         ; PHI2        ; -1.000       ; 6.850      ; 6.913      ;
+; 3.430   ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.469      ;
+; 4.434   ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.473      ;
+; 4.435   ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.474      ;
+; 5.287   ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.326      ;
+; 5.416   ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.455      ;
+; 10.780  ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 10.819     ;
+; 11.355  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 11.394     ;
+; 11.356  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 11.395     ;
+; 15.750  ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.789     ;
+; 15.750  ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.789     ;
+; 15.777  ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.816     ;
+; 15.777  ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 15.816     ;
+; 17.020  ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.059     ;
+; 17.650  ; CmdEnable   ; CmdLEDEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.689     ;
+; 17.650  ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 17.689     ;
+; 182.870 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 7.909      ;
+; 183.351 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 8.390      ;
+; 184.621 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 9.660      ;
+; 185.340 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.379     ;
+; 185.547 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 10.586     ;
+; 186.111 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.150     ;
+; 186.311 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.350     ;
+; 186.369 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 11.408     ;
+; 187.091 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.130     ;
+; 187.298 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 12.337     ;
+; 188.017 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.056     ;
+; 188.120 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.159     ;
+; 188.310 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.349     ;
+; 188.581 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.620     ;
+; 188.781 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.820     ;
+; 188.788 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 13.827     ;
+; 188.985 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.024     ;
+; 189.046 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.085     ;
+; 189.610 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.649     ;
+; 189.768 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.807     ;
+; 189.810 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 14.849     ;
+; 190.061 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 15.100     ;
+; 190.797 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 15.836     ;
+; 190.987 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.026     ;
+; 191.258 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.297     ;
+; 191.455 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.494     ;
+; 191.551 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.590     ;
+; 191.751 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 16.790     ;
+; 192.287 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.326     ;
+; 192.484 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.523     ;
+; 192.738 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 17.777     ;
+; 194.228 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 19.267     ;
+; 194.425 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 19.464     ;
+; 201.959 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 26.998     ;
+; 203.710 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 28.749     ;
+; 204.636 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 29.675     ;
+; 205.200 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 30.239     ;
+; 205.400 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 30.439     ;
+; 206.387 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.426     ;
+; 206.929 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.968     ;
+; 206.929 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.968     ;
+; 206.956 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.995     ;
+; 206.956 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 31.995     ;
+; 207.877 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 32.916     ;
+; 208.074 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.113     ;
+; 208.199 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.238     ;
+; 208.680 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.719     ;
+; 208.680 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.719     ;
+; 208.707 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.746     ;
+; 208.707 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.746     ;
+; 208.829 ; Bank[0]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.868     ;
+; 208.829 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 33.868     ;
+; 209.606 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.645     ;
+; 209.606 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.645     ;
+; 209.633 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.672     ;
+; 209.633 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.672     ;
+; 209.950 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 34.989     ;
+; 210.170 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.209     ;
+; 210.170 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.209     ;
+; 210.197 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.236     ;
+; 210.197 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.236     ;
+; 210.370 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.409     ;
+; 210.370 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.409     ;
+; 210.397 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.436     ;
+; 210.397 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.436     ;
+; 210.580 ; Bank[1]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.619     ;
+; 210.580 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.619     ;
+; 210.876 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 35.915     ;
+; 211.357 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.396     ;
+; 211.357 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.396     ;
+; 211.384 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.423     ;
+; 211.384 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.423     ;
+; 211.440 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.479     ;
+; 211.506 ; Bank[4]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.545     ;
+; 211.506 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.545     ;
+; 211.640 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 36.679     ;
+; 212.070 ; Bank[2]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.109     ;
+; 212.070 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.109     ;
+; 212.270 ; Bank[3]     ; CmdLEDEN     ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.309     ;
+; 212.270 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -175.000     ; 0.000      ; 37.309     ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS'                                                                                           ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -0.233  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.542      ;
+; -0.233  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.542      ;
+; -0.232  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.543      ;
+; -0.231  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 3.544      ;
+; 1.020   ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.795      ;
+; 1.023   ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.798      ;
+; 1.023   ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.798      ;
+; 1.026   ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.801      ;
+; 1.028   ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.803      ;
+; 1.156   ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.931      ;
+; 1.157   ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 4.932      ;
+; 2.562   ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -1.000       ; 4.736      ; 6.337      ;
+; 5.155   ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 9.682      ; 14.876     ;
+; 180.155 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -175.000     ; 9.682      ; 14.876     ;
++---------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK'                                                                                            ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 2.155 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 4.946      ; 7.140      ;
+; 2.206 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 4.946      ; 7.191      ;
+; 2.351 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 4.946      ; 7.336      ;
+; 3.155 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -1.000       ; 4.946      ; 7.140      ;
+; 3.206 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -1.000       ; 4.946      ; 7.191      ;
+; 3.266 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.305      ;
+; 3.351 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -1.000       ; 4.946      ; 7.336      ;
+; 3.374 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.413      ;
+; 3.459 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.498      ;
+; 3.468 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.507      ;
+; 3.781 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.820      ;
+; 3.803 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.842      ;
+; 3.813 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.852      ;
+; 3.828 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.867      ;
+; 3.850 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.889      ;
+; 4.032 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.071      ;
+; 4.092 ; CASr3       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.131      ;
+; 4.618 ; RASr2       ; RASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.657      ;
+; 4.858 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.897      ;
+; 4.858 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.897      ;
+; 5.228 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
+; 5.229 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
+; 5.230 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.269      ;
+; 5.247 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.286      ;
+; 5.252 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.291      ;
+; 5.254 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.293      ;
+; 5.267 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.306      ;
+; 5.270 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.309      ;
+; 5.280 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.319      ;
+; 5.291 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.330      ;
+; 5.309 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.348      ;
+; 5.316 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.355      ;
+; 5.316 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.355      ;
+; 5.321 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.360      ;
+; 5.322 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.361      ;
+; 5.335 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.374      ;
+; 5.429 ; UFMD        ; UFMD        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.468      ;
+; 5.440 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
+; 5.440 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
+; 5.441 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
+; 5.441 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
+; 5.441 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
+; 5.452 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.452 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.453 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.492      ;
+; 5.453 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.492      ;
+; 5.454 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.493      ;
+; 5.456 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.495      ;
+; 5.466 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.505      ;
+; 5.467 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.506      ;
+; 5.530 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.569      ;
+; 5.533 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.572      ;
+; 5.553 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.592      ;
+; 5.560 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.599      ;
+; 5.676 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.715      ;
+; 5.684 ; CASr3       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.723      ;
+; 5.963 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
+; 5.964 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
+; 5.987 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.026      ;
+; 6.002 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.041      ;
+; 6.005 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.044      ;
+; 6.015 ; FS[0]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.054      ;
+; 6.016 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.055      ;
+; 6.107 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
+; 6.131 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.170      ;
+; 6.146 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.185      ;
+; 6.149 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.188      ;
+; 6.159 ; FS[0]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.198      ;
+; 6.251 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
+; 6.293 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.332      ;
+; 6.395 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.434      ;
+; 6.416 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.455      ;
+; 6.442 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
+; 6.442 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
+; 6.443 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.482      ;
+; 6.454 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
+; 6.455 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.494      ;
+; 6.456 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.495      ;
+; 6.458 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.497      ;
+; 6.460 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.499      ;
+; 6.477 ; PHI2r3      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.516      ;
+; 6.477 ; PHI2r3      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.516      ;
+; 6.482 ; RASr2       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.521      ;
+; 6.534 ; IS[0]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.573      ;
+; 6.578 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.617      ;
+; 6.586 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.625      ;
+; 6.587 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.626      ;
+; 6.598 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
+; 6.599 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.638      ;
+; 6.730 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.769      ;
+; 6.731 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.770      ;
+; 6.742 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
+; 6.782 ; FS[11]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
+; 6.782 ; FS[11]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
+; 6.782 ; FS[11]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
+; 6.782 ; FS[11]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.821      ;
+; 6.795 ; FS[0]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
+; 6.795 ; FS[0]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
+; 6.795 ; FS[0]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
+; 6.795 ; FS[0]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.834      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 15       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 3        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 13       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 618      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 31    ; 31   ;
+; Unconstrained Input Port Paths  ; 249   ; 249  ;
+; Unconstrained Output Ports      ; 38    ; 38   ;
+; Unconstrained Output Port Paths ; 78    ; 78   ;
++---------------------------------+-------+------+
+
+
++-------------------------------------+
+; Clock Status Summary                ;
++--------+-------+------+-------------+
+; Target ; Clock ; Type ; Status      ;
++--------+-------+------+-------------+
+; ARCLK  ; ARCLK ; Base ; Constrained ;
+; DRCLK  ; DRCLK ; Base ; Constrained ;
+; PHI2   ; PHI2  ; Base ; Constrained ;
+; RCLK   ; RCLK  ; Base ; Constrained ;
+; nCCAS  ; nCCAS ; Base ; Constrained ;
+; nCRAS  ; nCRAS ; Base ; Constrained ;
++--------+-------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; CROW[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CROW[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Din[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[0]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[1]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[2]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[3]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[4]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[5]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[6]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[7]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[8]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MAin[9]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCCAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFWE       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQMH       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDQML       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRRAS       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Sat Aug 19 22:00:47 2023
+Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
+Info: qsta_default_script.tcl version: #1
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS.sdc'
+Info (332104): Reading SDC File: '//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.sdc'
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
+Critical Warning (332148): Timing requirements not met
+Info (332146): Worst-case setup slack is -19.199
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -19.199            -193.279 RCLK 
+    Info (332119):   -17.454             -17.454 DRCLK 
+    Info (332119):   -17.440             -17.440 ARCLK 
+    Info (332119):    -0.922              -0.922 nCRAS 
+    Info (332119):     0.616               0.000 PHI2 
+Info (332146): Worst-case hold slack is -14.753
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -14.753             -14.753 DRCLK 
+    Info (332119):   -14.560             -14.560 ARCLK 
+    Info (332119):    -2.450              -5.440 PHI2 
+    Info (332119):    -0.233              -0.929 nCRAS 
+    Info (332119):     2.155               0.000 RCLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 7.661
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     7.661               0.000 RCLK 
+    Info (332119):    70.000               0.000 ARCLK 
+    Info (332119):    70.000               0.000 DRCLK 
+    Info (332119):   174.661               0.000 PHI2 
+    Info (332119):   174.661               0.000 nCCAS 
+    Info (332119):   174.661               0.000 nCRAS 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4677 megabytes
+    Info: Processing ended: Sat Aug 19 22:00:58 2023
+    Info: Elapsed time: 00:00:11
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.summary b/CPLD/MAXV/output_files/RAM2GS.sta.summary
index 39a07ab..dec1ebb 100644
--- a/CPLD/MAXV/output_files/RAM2GS.sta.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.sta.summary
@@ -1,69 +1,69 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Setup 'RCLK'
-Slack : -19.199
-TNS   : -193.279
-
-Type  : Setup 'DRCLK'
-Slack : -17.454
-TNS   : -17.454
-
-Type  : Setup 'ARCLK'
-Slack : -17.440
-TNS   : -17.440
-
-Type  : Setup 'nCRAS'
-Slack : -0.922
-TNS   : -0.922
-
-Type  : Setup 'PHI2'
-Slack : 0.616
-TNS   : 0.000
-
-Type  : Hold 'DRCLK'
-Slack : -14.753
-TNS   : -14.753
-
-Type  : Hold 'ARCLK'
-Slack : -14.560
-TNS   : -14.560
-
-Type  : Hold 'PHI2'
-Slack : -2.450
-TNS   : -5.440
-
-Type  : Hold 'nCRAS'
-Slack : -0.233
-TNS   : -0.929
-
-Type  : Hold 'RCLK'
-Slack : 2.155
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'RCLK'
-Slack : 7.661
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'ARCLK'
-Slack : 70.000
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'DRCLK'
-Slack : 70.000
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'PHI2'
-Slack : 174.661
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'nCCAS'
-Slack : 174.661
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'nCRAS'
-Slack : 174.661
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Setup 'RCLK'
+Slack : -19.199
+TNS   : -193.279
+
+Type  : Setup 'DRCLK'
+Slack : -17.454
+TNS   : -17.454
+
+Type  : Setup 'ARCLK'
+Slack : -17.440
+TNS   : -17.440
+
+Type  : Setup 'nCRAS'
+Slack : -0.922
+TNS   : -0.922
+
+Type  : Setup 'PHI2'
+Slack : 0.616
+TNS   : 0.000
+
+Type  : Hold 'DRCLK'
+Slack : -14.753
+TNS   : -14.753
+
+Type  : Hold 'ARCLK'
+Slack : -14.560
+TNS   : -14.560
+
+Type  : Hold 'PHI2'
+Slack : -2.450
+TNS   : -5.440
+
+Type  : Hold 'nCRAS'
+Slack : -0.233
+TNS   : -0.929
+
+Type  : Hold 'RCLK'
+Slack : 2.155
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'RCLK'
+Slack : 7.661
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'ARCLK'
+Slack : 70.000
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'DRCLK'
+Slack : 70.000
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'PHI2'
+Slack : 174.661
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'nCCAS'
+Slack : 174.661
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'nCRAS'
+Slack : 174.661
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/CPLD/RAM2GS-AGM.v b/CPLD/RAM2GS-AGM.v
index 0dc7503..08b6196 100644
--- a/CPLD/RAM2GS-AGM.v
+++ b/CPLD/RAM2GS-AGM.v
@@ -1,8 +1,7 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
               nCCAS, nCRAS, nFWE, LED,
               RBA, RA, RD, nRCS, RCLK, RCKE,
-              nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-              nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML);
 
     /* 65816 Phase 2 Clock */
     input PHI2;
@@ -346,12 +345,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
         end
     end
 
-    /* UFM Control */
-    output nUFMCSout = nUFMCS;
-    output UFMCLKout = UFMCLK;
-    output UFMSDIout = UFMSDI;
-    output UFMSDOout = UFMSDO;
-    input [3:0] In;
+    /* UFM Control */ 
     always @(posedge RCLK) begin
         if (~InitReady && FS[17:10]==8'h00) begin
             nUFMCS <= 1'b1;
diff --git a/CPLD/RAM2GS-LCMXO2.mem b/CPLD/RAM2GS-LCMXO2.mem
new file mode 100644
index 0000000..eccce6a
--- /dev/null
+++ b/CPLD/RAM2GS-LCMXO2.mem
@@ -0,0 +1,7 @@
+// Auto-generated by memint 08/19/2023 20:50:21
+#Format=Hex
+#Depth=16
+#Width=8
+#AddrRadix=3
+#DataRadix=3
+#Data
diff --git a/CPLD/RAM2GS-LCMXO2.v b/CPLD/RAM2GS-LCMXO2.v
index c228114..0a03d80 100644
--- a/CPLD/RAM2GS-LCMXO2.v
+++ b/CPLD/RAM2GS-LCMXO2.v
@@ -62,7 +62,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
     /* UFM Interface */
     reg wb_rst;
-    reg wb_cyc_stb;
+    reg wb_cyc_stb;
+	reg wb_req;
     reg wb_we;
     reg [7:0] wb_adr;
     reg [7:0] wb_dati;
@@ -87,8 +88,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
     reg CmdValid = 0;
     reg Cmdn8MEGEN = 0;
     reg CmdLEDEN = 0;
+    reg CmdUFMWrite = 0;
+    reg CmdUFMShift = 0;
     reg CmdUFMData = 0;
-    reg CMDUFMWrite = 0;
     wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
     wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
     wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
@@ -360,365 +362,244 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
     /* UFM Control */
     always @(posedge RCLK) begin
-        if (~InitReady && FS[17:10]==8'h00) begin
-            wb_rst <= ~FS[9];
-            wb_cyc_stb <= 1'b0;
+        if (~InitReady && FS[17:15]==3'h0) begin
+            wb_rst <= ~FS[14];
             wb_we <= 1'b0;
+			wb_cyc_stb <= 1'b0;
+			wb_req <= 1'b0;
             wb_adr[7:0] <= 8'h00;
             wb_dati[7:0] <= 8'h00;
-        end else if (~InitReady && FS[17:10]==8'h01) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+        end else if (~InitReady && FS[17:15]==3'h1) begin
+            wb_rst <= 1'b0;
+			
+			if (FS[8:0]==0) wb_cyc_stb <= 0;
+			else if (FS[8:0]==1 && wb_req) wb_cyc_stb <= 1;
+			else if (wb_ack) wb_cyc_stb <= 0;
+            case (FS[14:9])
+                0: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
-                    wb_dati[7:0] <= 8'h80;
-                    wb_cyc_stb <= FS[4:0]==5'h10;
-                end 5'h01: begin // Enable configuration interface - command
+                    wb_dati[7:0] <= 8'h80;
+					wb_req <= 1;
+                end 1: begin // Enable configuration interface - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h74;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h02: begin // Enable configuration interface - operand 1/3
+					wb_req <= 1;
+                end 2: begin // Enable configuration interface - operand 1/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h08;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h03: begin // Enable configuration interface - operand 2/3
+					wb_req <= 1;
+                end 3: begin // Enable configuration interface - operand 2/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h04: begin // Enable configuration interface - operand 3/3
+					wb_req <= 1;
+                end 4: begin // Enable configuration interface - operand 3/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h1F: begin // Close frame
+					wb_req <= 1;
+                end 5: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end default: begin
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
-                end
-            endcase
-        end else if (~InitReady && FS[17:10]==8'h02) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+					wb_req <= 1;
+
+                end 6: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h80;
-
-                end 5'h01: begin // Poll status register - command
+					wb_req <= 1;
+                end 7: begin // Poll status register - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h3C;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h02: begin // Poll status register - operand 1/3
+					wb_req <= 1;
+                end 8: begin // Poll status register - operand 1/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-
-                end 5'h03: begin // Poll status register - operand 2/3
+					wb_req <= 1;
+                end 9: begin // Poll status register - operand 2/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h04: begin // Poll status register - operand 3/3
+					wb_req <= 1;
+                end 10: begin // Poll status register - operand 3/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-
-                end 5'h05: begin // Read status register 1/4
+					wb_req <= 1;
+                end 11, 12, 13, 14: begin // Read status register 1-4
                     wb_we <= 1'b0;
                     wb_adr[7:0] <= 8'h73;
                     wb_dati[7:0] <= 8'h3C;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h06: begin // Read status register 2/4
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h73;
-                    wb_dati[7:0] <= 8'h00;
-
-                end 5'h07: begin // Read status register 3/4
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h73;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h08: begin // Read status register 4/4
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h73;
-                    wb_dati[7:0] <= 8'h00;
-
-                end 5'h1F: begin // Close frame
+					wb_req <= 1;
+                end 15: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end default: begin
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
-                end
-            endcase
-        end else if (~InitReady && FS[17:10]==8'h03) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+					wb_req <= 1;
+
+                end 16: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h80;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h01: begin // Set UFM address - command
+					wb_req <= 1;
+                end 17: begin // Set UFM address - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'hB4;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h02: begin // Set UFM address - operand 1/3
+					wb_req <= 1;
+                end 18: begin // Set UFM address - operand 1/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h03: begin // Set UFM address - operand 2/3
+					wb_req <= 1;
+                end 19: begin // Set UFM address - operand 2/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h04: begin // Set UFM address - operand 3/3
+					wb_req <= 1;
+                end 20: begin // Set UFM address - operand 3/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h05: begin // Set UFM address - data 1/4
+					wb_req <= 1;
+                end 21: begin // Set UFM address - data 1/4
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h40;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h06: begin // Set UFM address - data 2/4
+					wb_req <= 1;
+                end 22: begin // Set UFM address - data 2/4
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h07: begin // Set UFM address - data 3/4
+					wb_req <= 1;
+                end 23: begin // Set UFM address - data 3/4
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h08: begin // Set UFM address - data 4/4
+					wb_req <= 1;
+                end 24: begin // Set UFM address - data 4/4
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h01;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h1F: begin // Close frame
+                    wb_dati[7:0] <= 190;
+					wb_req <= 1;
+                end 25: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end default: begin
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
-                end
-            endcase
-        end else if (~InitReady && FS[17:10]==8'h04) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+					wb_req <= 1;
+
+                end 26: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h80;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h01: begin // Read UFM page - command
+					wb_req <= 1;
+                end 27: begin // Read UFM page - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'hCA;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h02: begin // Read UFM page - operand 1/3
+					wb_req <= 1;
+                end 28: begin // Read UFM page - operand 1/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h10;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h03: begin // Read UFM page - operand 2/3
+					wb_req <= 1;
+                end 29: begin // Read UFM page - operand 2/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h04: begin // Read UFM page - operand 3/3
+					wb_req <= 1;
+                end 30: begin // Read UFM page - operand 3/3
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h01;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h05: begin // Read UFM page - data 1/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
+					wb_req <= 1;
+                end 31: begin // Read UFM page - data 1/16
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                    
-                    if (FS[4:0]==5'h1F) begin
+					wb_req <= 1;
+                    if (wb_ack) begin
                         LEDEN <= wb_dato[1];
                         n8MEGEN <= wb_dato[0];
                     end
-                end 5'h06: begin // Read UFM page - data 2/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
+                end     32, 33, 34,
+                    35, 36, 37, 38,
+                    39, 40, 41, 42,
+                    43, 44, 45, 46: begin // Read UFM page - data 2/16
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h07: begin // Read UFM page - data 3/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h08: begin // Read UFM page - data 4/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h09: begin // Read UFM page - data 5/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0A: begin // Read UFM page - data 6/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0B: begin // Read UFM page - data 7/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0C: begin // Read UFM page - data 8/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0D: begin // Read UFM page - data 9/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0E: begin // Read UFM page - data 10/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h0F: begin // Read UFM page - data 11/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h10: begin // Read UFM page - data 12/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h11: begin // Read UFM page - data 13/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h12: begin // Read UFM page - data 14/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h13: begin // Read UFM page - data 15/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h14: begin // Read UFM page - data 16/16
-                    wb_we <= 1'b1;
-                    wb_adr[7:0] <= 8'h71;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h1F: begin // Close frame
+					wb_req <= 1;
+                end 47: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end default: begin
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
-                end
-            endcase
-        end else if (~InitReady && FS[17:10]==8'h05) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+					wb_req <= 1;
+
+                end 48: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h80;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h01: begin // Disable configuration interface - command
+					wb_req <= 1;
+                end 49: begin // Disable configuration interface - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h26;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h02: begin // Disable configuration interface - operand 1/2
+					wb_req <= 1;
+                end 50: begin // Disable configuration interface - operand 1/2
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h03: begin // Disable configuration interface - operand 2/2
+					wb_req <= 1;
+                end 51: begin // Disable configuration interface - operand 2/2
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h1F: begin // Close frame
+					wb_req <= 1;
+                end 52: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end default: begin
-                    wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
-                    wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
-                end
-            endcase
-        end else if (~InitReady && FS[17:10]==8'h06) begin
-            wb_rst <= 1'b0;
-            case (FS[9:5])
-                5'h00: begin // Open frame
+					wb_req <= 1;
+
+                end 53: begin // Open frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h80;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h01: begin // Disable configuration interface - command
+					wb_req <= 1;
+                end 54: begin // Disable configuration interface - command
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h71;
                     wb_dati[7:0] <= 8'hFF;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
-                end 5'h1F: begin // Close frame
+					wb_req <= 1;
+                end 55: begin // Close frame
                     wb_we <= 1'b1;
                     wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= FS[4:0]==5'h00;
+					wb_req <= 1;
                 end default: begin
                     wb_we <= 1'b0;
-                    wb_adr[7:0] <= 8'h00;
+                    wb_adr[7:0] <= 8'h70;
                     wb_dati[7:0] <= 8'h00;
-                    wb_cyc_stb <= 1'b0;
+					wb_req <= 0;
                 end
             endcase
         end else if (~InitReady) begin
             wb_rst <= 1'b0;
-            wb_cyc_stb <= 1'b0;
+            wb_cyc_stb <= 1'b0;
+			wb_req <= 1'b0;
             wb_we <= 1'b0;
             wb_adr[7:0] <= 8'h00;
             wb_dati[7:0] <= 8'h00;
         end else if (~PHI2r2 & PHI2r3 & CmdValid) begin
             wb_rst <= 1'b0;
+			wb_req <= 1'b0;
             // Set user command signals after PHI2 falls
             LEDEN <= CmdLEDEN;
             n8MEGEN <= Cmdn8MEGEN;
@@ -726,8 +607,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
                 wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
                 wb_dati[7:0] <= { wb_dati[6:0], wb_we };
                 wb_we <= CmdUFMData;
-            end
-            if (CmdUFMWrite) wb_cyc_stb <= 1;
+				wb_cyc_stb <= 1'b0;
+            end else if (CmdUFMWrite) wb_cyc_stb <= 1;
         end else wb_cyc_stb <= 0;
     end
 endmodule

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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm
index c919829852109566bc782c25d86e375b9f2ed891..87522d1effe59b78191566e1e378e93fc05c2aa7 100644
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/_mh_info b/CPLD/LCMXO2-640HC/impl1/synwork/_mh_info
index 37bc105..4e98067 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/_mh_info
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/_mh_info
@@ -1 +1 @@
-|1|
+|1|
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
index 1a088e6..8e3a670 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
@@ -1,40 +1,40 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL compiler and linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-Modified Files: 0
-FID:  path (prevtimestamp, timestamp)
-
-*******************************************************************
-Modules that may have changed as a result of file changes: 0
-MID:  lib.cell.view
-
-*******************************************************************
-Unmodified files: 8
-FID:  path (timestamp)
-0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v (2021-08-10 09:11:08)
-1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
-2        C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v (2021-08-10 09:07:02)
-3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
-4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
-5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
-7        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v (2023-08-16 20:52:02)
-6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v (2023-08-16 20:58:34)
-
-*******************************************************************
-Unchanged modules: 2
-MID:  lib.cell.view
-0        work.RAM2GS.verilog
-1        work.REFB.verilog
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL compiler and linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+Modified Files: 0
+FID:  path (prevtimestamp, timestamp)
+
+*******************************************************************
+Modules that may have changed as a result of file changes: 0
+MID:  lib.cell.view
+
+*******************************************************************
+Unmodified files: 8
+FID:  path (timestamp)
+0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v (2021-08-10 09:11:08)
+1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
+2        C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v (2021-08-10 09:07:02)
+3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
+4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
+5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
+10       Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v (2023-08-19 07:27:00)
+11       Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v (2023-08-19 07:32:34)
+
+*******************************************************************
+Unchanged modules: 2
+MID:  lib.cell.view
+0        work.RAM2GS.verilog
+1        work.REFB.verilog
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
index b5d3d64..84eb0b2 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
@@ -1,23 +1,23 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
-#numinternalfiles:6
-#defaultlanguage:verilog
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
-1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
-#Dependency Lists(Uses List)
-0 1
-1 -1
-#Dependency Lists(Users Of)
-0 -1
-1 0
-#Design Unit to File Association
-module work RAM2GS 0
-module work REFB 1
+#OPTIONS:"|-layerid|0|-orig_srs|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692444754
+#CUR:"Y:\\Repos\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692444420
+#numinternalfiles:6
+#defaultlanguage:verilog
+0			"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work RAM2GS 0
+module work REFB 1
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdepxmr b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdepxmr
index 37d628b..8bc2ba2 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdepxmr
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdepxmr
@@ -1 +1 @@
-#XMR Information
+#XMR Information
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.rt.csv
index 915b7cd..0b328e3 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.rt.csv
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.rt.csv
@@ -1 +1 @@
-Library, Design Unit, compile Time, Peak Mem Usage
+Library, Design Unit, compile Time, Peak Mem Usage
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
index 1f02696..516f23a 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
@@ -1,31 +1,31 @@
-Selecting top level module RAM2GS
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
-Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
-Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"Y:\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db
index 4c6c160b1f0aff146ca6d6b6a454c671081b4fee..b09d515c93a7beacefad81d214c37a74c712778c 100644
GIT binary patch
delta 110
zcmZp0XmHrTCcv|lfxnTTiLaSYn0M*M!pXd1Ijn5rxyhnT&hEx$CQ6Z3F+r&X`Nfl$
v%7#g3spPS+iI>J>NNUPOFlnhwZkDTM(Nd{pn%pYqG}%qw5+v3rUkjuFSdSf4

delta 154
zcmZp0XmHrTCcsn4z~9Kv#MjLGm$!0bVLGo)BO@!jc%x{tD3i0hv6+dIi&cz&UaCt`
zW?5>COMY@`Zfaghag2LriAQPDDt0CdXtt=j4~Bz%|Oq{0Ay9=U`zd#HK(?
zPJ!dU6FVzIBP-)%J~qH%6M)8dag}jVPlP~eMFe*+C=R41+JXxLpt_TMo
zI|Kg_{tkX0ejdIvd=vQm_}DiqD!k`qcV%Z~Xk=xXEGTEgm2x-V$bpT8p%%o|oZKMC
z&ysStVAtjea@CBiU-;kgzt}9GaEV`zg@u`c@jnYQm}CNzjLht8%nTsq4Vw%;%k#3a
TFfns7va>KUb1
             
         
-        
+        
             
         
         
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf
deleted file mode 100644
index 4244ff9..0000000
--- a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf
+++ /dev/null
@@ -1,137 +0,0 @@
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ;
-IOBUF PORT "CROW[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=FAST ;
-IOBUF PORT "CROW[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "PHI2" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
-IOBUF PORT "RCLK" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
-IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Din[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[8]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "MAin[9]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "nFWE" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
-IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
-IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=14 OPENDRAIN=OFF ;
-IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[7]" SITE "71" ;
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html
index a187e77..9ccc776 100644
--- a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html
+++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html
@@ -72,6 +72,24 @@ prj_run Export -impl impl1
 
 
 
+pn230819063022
+#Start recording tcl command: 8/19/2023 06:30:15
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+#Stop recording: 8/19/2023 06:30:22
+
+
+
+pn230819205700
+#Start recording tcl command: 8/19/2023 20:52:34
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_project close
+#Stop recording: 8/19/2023 20:57:00
+
+
+
 
    
 
    
 
    
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819063022.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819063022.tcr
new file mode 100644
index 0000000..80c3ed1
--- /dev/null
+++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819063022.tcr
@@ -0,0 +1,4 @@
+#Start recording tcl command: 8/19/2023 06:30:15
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+#Stop recording: 8/19/2023 06:30:22
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819205700.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819205700.tcr
new file mode 100644
index 0000000..b379f81
--- /dev/null
+++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230819205700.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/19/2023 20:52:34
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_project close
+#Stop recording: 8/19/2023 20:57:00
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230820055550.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230820055550.tcr
new file mode 100644
index 0000000..5ea0e9f
--- /dev/null
+++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230820055550.tcr
@@ -0,0 +1,7 @@
+#Start recording tcl command: 8/20/2023 05:55:38
+#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task IBIS
+prj_project close
+#Stop recording: 8/20/2023 05:55:50
diff --git a/CPLD/LCMXO256C/impl1/.build_status b/CPLD/LCMXO256C/impl1/.build_status
index a122c3d..5615e13 100644
--- a/CPLD/LCMXO256C/impl1/.build_status
+++ b/CPLD/LCMXO256C/impl1/.build_status
@@ -2,56 +2,56 @@
 
     
         
-            
-            
-            
-            
+            
+            
+            
+            
         
-        
-            
-            
-            
-            
-            
+        
+            
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
+        
+            
         
         
-            
-            
+            
+            
             
             
             
         
-        
-            
+        
+            
         
         
         
-        
-        
-        
-        
+        
+        
+        
+        
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
     
 
diff --git a/CPLD/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs b/CPLD/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs
index 3418f0a..992c181 100644
--- a/CPLD/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs
+++ b/CPLD/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs
@@ -1,3373 +1,3373 @@
-|************************************************************************
-| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
-| Generate date: Wed Aug 16 04:50:48 2023
-|************************************************************************
-| IBIS File machxo.ibs
-| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
-| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
-| North Carolina State University, ERL, 2006
-|************************************************************************
-[IBIS ver]       3.2
-[File Name]     RAM2GS_LCMXO256C_im~.ibs
-[File Rev]       2.2
-[Date]           Mon Sep 28 10:44:10 EDT 2009
-[Source]         Lattice Semiconductor EE12 Process
-[Notes]          "Preliminary Version"
-                 Lattice Semiconductor has worked hard to ensure the
-                 models below are accurate and complete.  However, the
-                 data below was generated using simulation of the
-                 input/output model files for the silicon.  Therefore,
-                 the data below is for reference and initial design
-                 purposes only.
-|
-                 The data below is correlated to Spice models.  
-                 For questions regarding this data please contact
-                 us at www.latticesemi.com.
-|
-                 Lattice Semiconductor grants permission to use this
-                 data for use in printed circuit design using this
-                 Lattice programmable logic device.  Other use of this
-                 code, including the selling or duplication of any
-                 portion is strictly prohibited.
-|
-|                NAMING CONVENTION
-|
-        The IBIS [Model] header is limited by the specification to a
-        total of characters.  With such a set of characters available
-        for naming models it becomes important to attempt to
-        meaningfully encode the IO standards so they fit within the
-        twenty character limit.  It would seem that twenty characters
-        would provide room enough for describing IO's.  However, the
-        PLD IO structure continues to grow more and more complex.  The
-        complexity is making the twenty characters insuffiently
-        descriptive.  In order to overcome this issue the naming
-        convention described below is implemented to resolve the issue.
-|
-The twenty character space is managed as follows:
-                 bbbvvvsdddprugtcoixx
-|
-                 b = standard
-                 v = voltage (x.xx V)
-                 s = slew code
-                 d = drive (xx.x ma)
-                 p = pullup code
-                 r = series resistance code
-                 u = terminate to vcc code
-                 g = terminate to gnd code
-                 t = terminate to vtt code
-                 c = common mode termination mode
-                 o = diff resistor code
-                 i = diff resistor current code
-                 x = reserved
-|
-|
-                 standard
-|
-                 LVCMOS                   lvc
-                 lvcmosd                  lvd
-                 LVDSE                    lve
-                 LVTTL                    lvt
-                 lvttld                   ltd
-                 PCI                      pci
-                 pcix                     pcx
-                 AGP1x                    ag1
-                 agp2x                    ag2
-                 sstl_I                   ss1
-                 sstl_II                  ss2
-                 sstld_I                  s1d
-                 sstld_II                 s2d
-                 CTT                      ctt
-                 hstl_i                   hs1
-                 hstl_ii                  hs2
-                 hstl_iii                 hs3
-                 hstl_iv                  hs4
-                 hstld_i                  h1d
-                 hstld_ii                 h2d
-                 gtl                      gtl
-                 gtlplus                  gtp
-                 lvds                     lvs
-                 blvds                    blv
-                 mlvds                    mlv
-                 lvpecl                   lvp
-                 cml                      cml
-                 hypt                     hyp
-                 rsds                     rsd
-                 vref1                    vr1
-                 vref2                    vr2
-                 ref_res                  rer
-|
-|
-                 slew
-                 na                       a
-                 fast                     f
-                 slow                     s
-|
-                 pullmode
-                 off                      a
-                 pullup                   b
-                 pulldown                 c
-                 bushold                  d
-                 pciclamp                 e
-                 up_pciclamp              f
-                 down_pciclamp            g
-                 keeper_pciclamp          h
-                 schmitt                  i
-                 up_schmitt               j
-                 down_schmitt             k
-                 keeper_schmitt           l
-                 up_pciclamp_schmitt      m
-                 down_pciclamp_schmitt    n
-                 keeper_pciclamp_schmitt  o
-                 pciclamp_schmitt         p
-|
-                 impedence
-                 off                      a
-                 25                       b
-                 33                       c
-                 50                       d
-                 100                      e
-|
-                 termVCC
-                 off                      a
-                 50                       b
-                 100                      c
-                 120                      d
-|
-                 termGND
-                 off                      a
-                 50                       b
-                 100                      c
-                 120                      d
-|
-                 termVTT
-                 off                      a
-                 60                       b
-                 75                       c
-                 120                      d
-                 150                      e
-                 210                      f
-|
-                 VCMT
-                 off                      a
-                 VCMT                     b
-                 VTT                      c
-                 DDR-2                    d
-|
-                 differential resistor
-                 off                      a
-                 120                      b
-                 150                      c
-                 220                      d
-                 420                      e
-|
-                 differential current
-                 NA                       a
-                 2                        b
-                 3.5                      c
-                 4                        d
-                 6                        e
-|
-                 Reserved                 IO type
-                 in                       input only
-                 ou                       output
-                 io                       I/O
-                 od                       Open drain
-                 on                       Inverting differential I/O
-                                          (signal name only)
-                 op                       Non-Inverting differential I/O
-                                          (signal name only)
-|
-   All the IO models are generated with pull mode set to UP.
-|
-                 Lattice Semiconductor Corporation
-                 5555 NE Moore Court
-                 Hillsboro, OR 97214
-                 U.S.A
-|
-                 TEL: 1-800-Lattice (USA and Canada)
-                      408-826-6000 (other locations)
-|
-                 web: http://www.latticesemi.com/
-                 email: techsupport@latticesemi.com
-|
-|
-|
-[Disclaimer]     This IBIS source code is intended as a design reference
-   which illustrates how the Lattice Semiconductor device operates.
-   It is the user's responsibility to verify their design for
-   consistency and functionality through the use of formal
-   verification methods.  Lattice Semiconductor provides no warranty
-   regarding the use or functionality of this data.
-|
-[Copyright]      Copyright 2009 by Lattice Semiconductor Corporation
-|
-|  
-|************************************************************************
-|                       Component XO
-|************************************************************************
-|  
-[Component]     MXO256_MXO640_MXO1K_MXO2K
-[Manufacturer]    Lattice Semiconductor Corp.
-[Package]
-|TQFP100
-| variable            typ              min              max
-R_pkg                 70.5m            54.0m            87.0m
-L_pkg                 4.57nH           4.27nH           4.87nH
-C_pkg                 .52pF            .47pF            .57pF
-|
-[Pin] signal_name           model_name           R_pin     L_pin     C_pin
-32            CROW[0]              lvc330fxxxaaaaaaaain
-34            CROW[1]              lvc330fxxxaaaaaaaain
-21            Din[0]               lvc330fxxxaaaaaaaain
-15            Din[1]               lvc330fxxxaaaaaaaain
-14            Din[2]               lvc330fxxxaaaaaaaain
-16            Din[3]               lvc330fxxxaaaaaaaain
-18            Din[4]               lvc330fxxxaaaaaaaain
-17            Din[5]               lvc330fxxxaaaaaaaain
-20            Din[6]               lvc330fxxxaaaaaaaain
-19            Din[7]               lvc330fxxxaaaaaaaain
-1             Dout[0]              lvc330f040aaaaaaaaio
-7             Dout[1]              lvc330f040aaaaaaaaio
-8             Dout[2]              lvc330f040aaaaaaaaio
-6             Dout[3]              lvc330f040aaaaaaaaio
-4             Dout[4]              lvc330f040aaaaaaaaio
-5             Dout[5]              lvc330f040aaaaaaaaio
-2             Dout[6]              lvc330f040aaaaaaaaio
-3             Dout[7]              lvc330f040aaaaaaaaio
-57            LED                  lvc330s140aaaaaaaaio
-23            MAin[0]              lvc330fxxxaaaaaaaain
-38            MAin[1]              lvc330fxxxaaaaaaaain
-37            MAin[2]              lvc330fxxxaaaaaaaain
-47            MAin[3]              lvc330fxxxaaaaaaaain
-46            MAin[4]              lvc330fxxxaaaaaaaain
-45            MAin[5]              lvc330fxxxaaaaaaaain
-49            MAin[6]              lvc330fxxxaaaaaaaain
-44            MAin[7]              lvc330fxxxaaaaaaaain
-50            MAin[8]              lvc330fxxxaaaaaaaain
-51            MAin[9]              lvc330fxxxaaaaaaaain
-39            PHI2                 lvc330fxxxcaaaaaaain
-98            RA[0]                lvc330s040aaaaaaaaio
-87            RA[10]               lvc330s040aaaaaaaaio
-79            RA[11]               lvc330s040aaaaaaaaio
-89            RA[1]                lvc330s040aaaaaaaaio
-94            RA[2]                lvc330s040aaaaaaaaio
-97            RA[3]                lvc330s040aaaaaaaaio
-99            RA[4]                lvc330s040aaaaaaaaio
-95            RA[5]                lvc330s040aaaaaaaaio
-91            RA[6]                lvc330s040aaaaaaaaio
-100           RA[7]                lvc330s040aaaaaaaaio
-96            RA[8]                lvc330s040aaaaaaaaio
-85            RA[9]                lvc330s040aaaaaaaaio
-63            RBA[0]               lvc330s040aaaaaaaaio
-83            RBA[1]               lvc330s040aaaaaaaaio
-82            RCKE                 lvc330s040aaaaaaaaio
-86            RCLK                 lvc330fxxxaaaaaaaain
-76            RDQMH                lvc330s040aaaaaaaaio
-61            RDQML                lvc330s040aaaaaaaaio
-64            RD[0]                lvc330s040aaaaaaaaio
-65            RD[1]                lvc330s040aaaaaaaaio
-66            RD[2]                lvc330s040aaaaaaaaio
-67            RD[3]                lvc330s040aaaaaaaaio
-68            RD[4]                lvc330s040aaaaaaaaio
-69            RD[5]                lvc330s040aaaaaaaaio
-70            RD[6]                lvc330s040aaaaaaaaio
-71            RD[7]                lvc330s040aaaaaaaaio
-58            UFMCLK               lvc330s040aaaaaaaaio
-56            UFMSDI               lvc330s040aaaaaaaaio
-55            UFMSDO               lvc330fxxxaaaaaaaain
-27            nCCAS                lvc330fxxxbaaaaaaain
-43            nCRAS                lvc330fxxxbaaaaaaain
-22            nFWE                 lvc330fxxxaaaaaaaain
-78            nRCAS                lvc330s040aaaaaaaaio
-77            nRCS                 lvc330s040aaaaaaaaio
-73            nRRAS                lvc330s040aaaaaaaaio
-72            nRWE                 lvc330s040aaaaaaaaio
-53            nUFMCS               lvc330s040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330f040aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
-  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
-  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
-  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
-  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
-  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
-  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
-  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
-  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
-  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
-  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
-  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
-  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
-  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
-  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
-  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
-  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
-  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
-  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
-  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
-  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
-  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
-  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
-  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
-  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
-  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
-  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
-  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
-  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
-  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
-  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
-  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
-  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
-  0.00    9.270000nA        8.640000nA           10.950000nA
-  0.10    2.215985mA        1.960397mA           2.507890mA
-  0.20    4.086375mA        3.683686mA           4.498680mA
-  0.30    5.594166mA        5.150675mA           5.952471mA
-  0.40    6.738256mA        6.352364mA           6.929962mA
-  0.50    7.557146mA        7.289853mA           7.572152mA
-  0.60    8.124436mA        7.983242mA           8.013343mA
-  0.70    8.511126mA        8.476831mA           8.337834mA
-  0.80    8.778316mA        8.826620mA           8.591424mA
-  0.90    8.972606mA        9.080609mA           8.798515mA
-  1.00    9.121395mA        9.272098mA           8.969206mA
-  1.10    9.240584mA        9.422087mA           9.101296mA
-  1.20    9.339574mA        9.543476mA           9.202186mA
-  1.30    9.424063mA        9.644765mA           9.285275mA
-  1.40    9.498053mA        9.731354mA           9.357665mA
-  1.50    9.564242mA        9.806743mA           9.423455mA
-  1.60    9.625232mA        9.873832mA           9.485944mA
-  1.70    9.684621mA        9.934821mA           9.548134mA
-  1.80    9.747011mA        9.992810mA           9.610224mA
-  1.90    9.814800mA        10.052999mA          9.670813mA
-  2.00    9.885689mA        10.122988mA          9.728603mA
-  2.10    9.955379mA        10.203977mA          9.783293mA
-  2.20    10.021968mA       10.292966mA          9.835282mA
-  2.30    10.083958mA       10.380954mA          9.884972mA
-  2.40    10.141947mA       10.464943mA          9.932861mA
-  2.50    10.196936mA       10.542932mA          9.979551mA
-  2.60    10.249926mA       10.614921mA          10.025941mA
-  2.70    10.300915mA       10.681910mA          10.071930mA
-  2.80    10.350904mA       10.744899mA          10.118920mA
-  2.90    10.400894mA       10.805888mA          10.167909mA
-  3.00    10.451883mA       10.863877mA          10.218899mA
-  3.10    10.504872mA       10.921864mA          10.273889mA
-  3.20    10.559862mA       10.978747mA          10.332878mA
-  3.30    10.618848mA       11.037379mA          10.397868mA
-  3.40    10.682725mA       11.085335mA          10.469857mA
-  3.50    10.751986mA       11.124616mA          10.550843mA
-  3.60    10.804292mA       11.163898mA          10.640599mA
-  3.70    10.840604mA       11.203179mA          10.738212mA
-  3.80    10.876916mA       11.242461mA          10.773505mA
-  3.90    10.913228mA       11.281743mA          10.808797mA
-  4.00    10.949540mA       11.321024mA          10.844090mA
-  4.10    10.985852mA       11.360306mA          10.879382mA
-  4.20    11.022164mA       11.399587mA          10.914675mA
-  4.30    11.058476mA       11.438869mA          10.949967mA
-  4.40    11.094788mA       11.478151mA          10.985259mA
-  4.50    11.131100mA       11.517432mA          11.020552mA
-  4.60    11.167412mA       11.556714mA          11.055844mA
-  4.70    11.203724mA       11.595995mA          11.091137mA
-  4.80    11.240036mA       11.635277mA          11.126429mA
-  4.90    11.276348mA       11.674559mA          11.161721mA
-  5.00    11.312660mA       11.713840mA          11.197014mA
-  5.10    11.348972mA       11.753122mA          11.232306mA
-  5.20    11.385284mA       11.792403mA          11.267599mA
-  5.30    11.421596mA       11.831685mA          11.302891mA
-  5.40    11.457908mA       11.870967mA          11.338183mA
-  5.50    11.494220mA       11.910248mA          11.373476mA
-  5.60    11.530532mA       11.949530mA          11.408768mA
-  5.70    11.566844mA       11.988811mA          11.444061mA
-  5.80    11.603156mA       12.028093mA          11.479353mA
-  5.90    11.639468mA       12.067375mA          11.514645mA
-  6.00    11.675780mA       12.106656mA          11.549938mA
-  6.10    11.712092mA       12.145938mA          11.585230mA
-  6.20    11.748404mA       12.185219mA          11.620523mA
-  6.30    11.784716mA       12.224501mA          11.655815mA
-  6.40    11.821028mA       12.263783mA          11.691107mA
-  6.50    11.857340mA       12.303064mA          11.726400mA
-  6.60    11.893652mA       12.342346mA          11.761692mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    6.260163mA        5.384933mA           7.315403mA
-  -3.20    6.239699mA        5.366401mA           7.291487mA
-  -3.10    6.219236mA        5.347870mA           7.267570mA
-  -3.00    6.198773mA        5.329339mA           7.243653mA
-  -2.90    6.178310mA        5.310808mA           7.219736mA
-  -2.80    6.157847mA        5.292277mA           7.195819mA
-  -2.70    6.137383mA        5.273745mA           7.171903mA
-  -2.60    6.116920mA        5.255214mA           7.147986mA
-  -2.50    6.096457mA        5.236683mA           7.124069mA
-  -2.40    6.075994mA        5.218152mA           7.100152mA
-  -2.30    6.055531mA        5.199621mA           7.076235mA
-  -2.20    6.035067mA        5.181089mA           7.052319mA
-  -2.10    6.014604mA        5.162558mA           7.028402mA
-  -2.00    5.994141mA        5.144027mA           7.004485mA
-  -1.90    5.973678mA        5.125496mA           6.980568mA
-  -1.80    5.953215mA        5.106965mA           6.956651mA
-  -1.70    5.932751mA        5.088433mA           6.932735mA
-  -1.60    5.912288mA        5.069902mA           6.908818mA
-  -1.50    5.891825mA        5.051371mA           6.884901mA
-  -1.40    5.871362mA        5.032840mA           6.860984mA
-  -1.30    5.850899mA        5.014309mA           6.837067mA
-  -1.20    5.830435mA        4.995777mA           6.813151mA
-  -1.10    5.809972mA        4.977246mA           6.789234mA
-  -1.00    5.789509mA        4.958715mA           6.765317mA
-  -0.90    5.769046mA        4.940184mA           6.741400mA
-  -0.80    5.748583mA        4.921653mA           6.717483mA
-  -0.70    5.728119mA        4.903121mA           6.693567mA
-  -0.60    5.707656mA        4.884590mA           6.669650mA
-  -0.50    5.687193mA        4.866059mA           6.645733mA
-  -0.40    5.666730mA        4.847528mA           6.621816mA
-  -0.30    5.646267mA        4.828997mA           6.597899mA
-  -0.20    4.435786mA        3.802115mA           5.174820mA
-  -0.10    2.131925mA        1.838548mA           2.475669mA
-  0.00    -6.170000nA       -5.460000nA          -7.060000nA
-  0.10    -1.893038mA       -1.673728mA          -2.145840mA
-  0.20    -3.512428mA       -3.164516mA          -3.900829mA
-  0.30    -4.854717mA       -4.471005mA          -5.257719mA
-  0.40    -5.916606mA       -5.591894mA          -6.209108mA
-  0.50    -6.694696mA       -6.525883mA          -6.765898mA
-  0.60    -7.186085mA       -7.271372mA          -7.127487mA
-  0.70    -7.501974mA       -7.827161mA          -7.398777mA
-  0.80    -7.747264mA       -8.192150mA          -7.614967mA
-  0.90    -7.946053mA       -8.442739mA          -7.794856mA
-  1.00    -8.112642mA       -8.647928mA          -7.949846mA
-  1.10    -8.255932mA       -8.820317mA          -8.086935mA
-  1.20    -8.381921mA       -8.968206mA          -8.210725mA
-  1.30    -8.494611mA       -9.097295mA          -8.324315mA
-  1.40    -8.596900mA       -9.211784mA          -8.430004mA
-  1.50    -8.691089mA       -9.314673mA          -8.529494mA
-  1.60    -8.778479mA       -9.407962mA          -8.623884mA
-  1.70    -8.860368mA       -9.493551mA          -8.714073mA
-  1.80    -8.937858mA       -9.572640mA          -8.800963mA
-  1.90    -9.011447mA       -9.646329mA          -8.884952mA
-  2.00    -9.081837mA       -9.715418mA          -8.966642mA
-  2.10    -9.149526mA       -9.780507mA          -9.046332mA
-  2.20    -9.214816mA       -9.842296mA          -9.124421mA
-  2.30    -9.278305mA       -9.901185mA          -9.201211mA
-  2.40    -9.340094mA       -9.957574mA          -9.277001mA
-  2.50    -9.400784mA       -10.011863mA         -9.352391mA
-  2.60    -9.460574mA       -10.063852mA         -9.427582mA
-  2.70    -9.519964mA       -10.115841mA         -9.503173mA
-  2.80    -9.579454mA       -10.165830mA         -9.579563mA
-  2.90    -9.639644mA       -10.215819mA         -9.657654mA
-  3.00    -9.701034mA       -10.264808mA         -9.737845mA
-  3.10    -9.764525mA       -10.315796mA         -9.821135mA
-  3.20    -9.830715mA       -10.367780mA         -9.908326mA
-  3.30    -9.900606mA       -10.421706mA         -10.000817mA
-  3.40    -9.975092mA       -10.478956mA         -10.098808mA
-  3.50    -10.055705mA      -10.535873mA         -10.202798mA
-  3.60    -10.141346mA      -10.578599mA         -10.316786mA
-  3.70    -10.228551mA      -10.620789mA         -10.438679mA
-  3.80    -10.281620mA      -10.662980mA         -10.570555mA
-  3.90    -10.322662mA      -10.705170mA         -10.682977mA
-  4.00    -10.363704mA      -10.747360mA         -10.725640mA
-  4.10    -10.404746mA      -10.789550mA         -10.768303mA
-  4.20    -10.445787mA      -10.831741mA         -10.810966mA
-  4.30    -10.486829mA      -10.873931mA         -10.853629mA
-  4.40    -10.527871mA      -10.916121mA         -10.896292mA
-  4.50    -10.568913mA      -10.958311mA         -10.938955mA
-  4.60    -10.609955mA      -11.000502mA         -10.981618mA
-  4.70    -10.650997mA      -11.042692mA         -11.024281mA
-  4.80    -10.692039mA      -11.084882mA         -11.066944mA
-  4.90    -10.733081mA      -11.127072mA         -11.109607mA
-  5.00    -10.774122mA      -11.169262mA         -11.152270mA
-  5.10    -10.815164mA      -11.211453mA         -11.194933mA
-  5.20    -10.856206mA      -11.253643mA         -11.237597mA
-  5.30    -10.897248mA      -11.295833mA         -11.280260mA
-  5.40    -10.938290mA      -11.338023mA         -11.322923mA
-  5.50    -10.979332mA      -11.380214mA         -11.365586mA
-  5.60    -11.020374mA      -11.422404mA         -11.408249mA
-  5.70    -11.061416mA      -11.464594mA         -11.450912mA
-  5.80    -11.102458mA      -11.506784mA         -11.493575mA
-  5.90    -11.143499mA      -11.548975mA         -11.536238mA
-  6.00    -11.184541mA      -11.591165mA         -11.578901mA
-  6.10    -11.225583mA      -11.633355mA         -11.621564mA
-  6.20    -11.266625mA      -11.675545mA         -11.664227mA
-  6.30    -11.307667mA      -11.717736mA         -11.706890mA
-  6.40    -11.348709mA      -11.759926mA         -11.749553mA
-  6.50    -11.389751mA      -11.802116mA         -11.792216mA
-  6.55    -11.410272mA      -11.823211mA         -11.813548mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.204000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270300uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  0.287529/0.242724n  0.301503/0.328867n  0.291718/0.195168n
-dV/dt_f  0.313320/0.253363n  0.309840/0.389332n  0.311820/0.168025n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.782900V         2.609000V            2.960100V
-0.2020ns          2.783000V         2.608900V            2.962600V
-0.4040ns          2.787900V         2.610900V            3.090500V
-0.6061ns          3.029800V         2.611800V            3.431300V
-0.8081ns          3.255100V         2.678900V            3.466400V
-1.0101ns          3.294700V         2.982700V            3.469200V
-1.2121ns          3.298300V         3.109600V            3.469600V
-1.4141ns          3.299300V         3.123400V            3.469800V
-1.6162ns          3.299600V         3.137700V            3.469900V
-1.8182ns          3.299700V         3.138900V            3.469900V
-2.0202ns          3.299800V         3.139300V            3.469900V
-2.2222ns          3.299900V         3.139600V            3.469900V
-2.4242ns          3.299900V         3.139700V            3.469200V
-2.6263ns          3.299900V         3.139700V            3.471700V
-2.8283ns          3.299900V         3.139800V            3.470600V
-3.0303ns          3.299900V         3.139800V            3.470200V
-3.2323ns          3.299900V         3.139900V            3.470100V
-3.4343ns          3.302400V         3.139900V            3.470000V
-3.6364ns          3.301400V         3.139900V            3.470000V
-3.8384ns          3.300600V         3.139900V            3.470000V
-4.0404ns          3.300200V         3.139900V            3.470000V
-4.2424ns          3.300000V         3.139900V            3.470000V
-4.4444ns          3.300000V         3.139900V            3.470000V
-4.6465ns          3.300000V         3.139900V            3.469900V
-4.8485ns          3.300000V         3.140000V            3.469900V
-5.0505ns          3.300000V         3.141300V            3.469900V
-5.2525ns          3.300000V         3.142100V            3.469900V
-5.4545ns          3.299900V         3.140900V            3.469900V
-5.6566ns          3.299900V         3.140500V            3.469900V
-5.8586ns          3.299900V         3.140200V            3.469900V
-6.0606ns          3.299900V         3.140100V            3.469900V
-6.2626ns          3.299900V         3.140000V            3.469900V
-6.4646ns          3.299900V         3.140000V            3.469900V
-6.6667ns          3.299900V         3.140000V            3.470000V
-6.8687ns          3.299900V         3.140000V            3.470000V
-7.0707ns          3.299900V         3.140000V            3.470000V
-7.2727ns          3.299900V         3.139900V            3.470000V
-7.4747ns          3.299900V         3.139900V            3.470000V
-7.6768ns          3.299900V         3.139900V            3.470000V
-7.8788ns          3.299900V         3.139900V            3.470000V
-8.0808ns          3.299900V         3.139900V            3.470000V
-8.2828ns          3.299900V         3.139900V            3.470000V
-8.4848ns          3.299900V         3.139800V            3.470000V
-8.6869ns          3.299900V         3.139800V            3.470000V
-8.8889ns          3.299900V         3.139900V            3.470000V
-9.0909ns          3.299900V         3.139900V            3.470000V
-9.2929ns          3.299900V         3.139900V            3.470000V
-9.4949ns          3.300000V         3.139900V            3.470000V
-9.6970ns          3.300000V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.139900V            3.470000V
-11.7172ns         3.300000V         3.139900V            3.470000V
-11.9192ns         3.300000V         3.139900V            3.470000V
-12.1212ns         3.300000V         3.139900V            3.470000V
-12.3232ns         3.300000V         3.139900V            3.470000V
-12.5253ns         3.300000V         3.139900V            3.470000V
-12.7273ns         3.300000V         3.139900V            3.470000V
-12.9293ns         3.300000V         3.139900V            3.470000V
-13.1313ns         3.300000V         3.140000V            3.470000V
-13.3333ns         3.300000V         3.140000V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              4.225900uV        4.920300uV           3.956100uV
-0.2020ns          -0.116150mV       2.502300uV           -0.231550mV
-0.4040ns          -1.969300mV       5.640900uV           0.966840mV
-0.6061ns          23.188000mV       -0.508470mV          0.314560V
-0.8081ns          0.256150V         -5.285700mV          0.577600V
-1.0101ns          0.498250V         54.786000mV          0.667290V
-1.2121ns          0.599860V         0.232770V            0.689990V
-1.4141ns          0.636760V         0.420560V            0.696020V
-1.6162ns          0.647730V         0.550470V            0.696970V
-1.8182ns          0.651730V         0.605400V            0.696980V
-2.0202ns          0.652900V         0.628190V            0.696540V
-2.2222ns          0.653040V         0.636320V            0.696120V
-2.4242ns          0.653000V         0.639440V            0.698020V
-2.6263ns          0.652920V         0.640980V            0.608850V
-2.8283ns          0.652830V         0.641740V            0.523850V
-3.0303ns          0.652750V         0.642070V            0.484440V
-3.2323ns          0.652670V         0.642220V            0.464640V
-3.4343ns          0.646540V         0.642370V            0.456500V
-3.6364ns          0.546150V         0.642430V            0.451090V
-3.8384ns          0.483220V         0.642470V            0.449010V
-4.0404ns          0.451320V         0.642490V            0.447190V
-4.2424ns          0.434720V         0.642510V            0.447190V
-4.4444ns          0.427460V         0.642520V            0.447460V
-4.6465ns          0.422730V         0.642530V            0.449720V
-4.8485ns          0.420080V         0.642410V            0.452230V
-5.0505ns          0.418790V         0.647910V            0.454820V
-5.2525ns          0.418520V         0.569370V            0.457130V
-5.4545ns          0.419000V         0.507240V            0.459260V
-5.6566ns          0.420340V         0.472210V            0.461230V
-5.8586ns          0.422900V         0.450470V            0.463090V
-6.0606ns          0.425610V         0.440570V            0.464890V
-6.2626ns          0.428790V         0.434240V            0.466650V
-6.4646ns          0.432030V         0.430580V            0.468260V
-6.6667ns          0.435070V         0.428580V            0.469780V
-6.8687ns          0.437890V         0.427410V            0.471150V
-7.0707ns          0.440590V         0.426660V            0.472420V
-7.2727ns          0.443180V         0.426510V            0.473570V
-7.4747ns          0.445620V         0.426790V            0.474650V
-7.6768ns          0.447910V         0.427810V            0.475620V
-7.8788ns          0.450050V         0.429350V            0.476520V
-8.0808ns          0.452040V         0.431730V            0.477340V
-8.2828ns          0.453900V         0.435000V            0.478100V
-8.4848ns          0.455630V         0.438710V            0.478780V
-8.6869ns          0.457250V         0.442390V            0.479420V
-8.8889ns          0.458760V         0.446040V            0.479990V
-9.0909ns          0.460180V         0.449510V            0.480530V
-9.2929ns          0.461490V         0.452860V            0.481010V
-9.4949ns          0.462720V         0.455990V            0.481460V
-9.6970ns          0.463870V         0.458960V            0.481860V
-9.8990ns          0.464940V         0.461730V            0.482240V
-10.1010ns         0.466405V         0.465580V            0.482735V
-10.3030ns         0.467740V         0.469110V            0.483180V
-10.5051ns         0.468550V         0.471260V            0.483440V
-10.7071ns         0.469310V         0.473300V            0.483680V
-10.9091ns         0.470010V         0.475190V            0.483900V
-11.1111ns         0.470670V         0.476990V            0.484100V
-11.3131ns         0.471280V         0.478660V            0.484280V
-11.5152ns         0.471860V         0.480240V            0.484450V
-11.7172ns         0.472390V         0.481710V            0.484610V
-11.9192ns         0.472890V         0.483100V            0.484740V
-12.1212ns         0.473350V         0.484400V            0.484870V
-12.3232ns         0.473780V         0.485630V            0.484990V
-12.5253ns         0.474180V         0.486770V            0.485100V
-12.7273ns         0.474560V         0.487850V            0.485200V
-12.9293ns         0.474910V         0.488850V            0.485290V
-13.1313ns         0.475230V         0.489800V            0.485370V
-13.3333ns         0.475530V         0.490690V            0.485440V
-13.5354ns         0.475810V         0.491530V            0.485510V
-13.7374ns         0.476080V         0.492300V            0.485570V
-13.9394ns         0.476320V         0.493040V            0.485630V
-14.1414ns         0.476550V         0.493730V            0.485680V
-14.3434ns         0.476760V         0.494380V            0.485730V
-14.5455ns         0.476960V         0.494980V            0.485780V
-14.7475ns         0.477140V         0.495550V            0.485810V
-14.9495ns         0.477310V         0.496080V            0.485850V
-15.1515ns         0.477470V         0.496580V            0.485880V
-15.3535ns         0.477620V         0.497050V            0.485920V
-15.5556ns         0.477760V         0.497490V            0.485940V
-15.7576ns         0.477880V         0.497900V            0.485970V
-15.9596ns         0.478000V         0.498290V            0.485990V
-16.1616ns         0.478110V         0.498650V            0.486010V
-16.3636ns         0.478220V         0.499000V            0.486030V
-16.5657ns         0.478310V         0.499300V            0.486050V
-16.7677ns         0.478400V         0.499590V            0.486070V
-16.9697ns         0.478480V         0.499870V            0.486080V
-17.1717ns         0.478560V         0.500150V            0.486100V
-17.3737ns         0.478630V         0.500410V            0.486110V
-17.5758ns         0.478700V         0.500640V            0.486120V
-17.7778ns         0.478760V         0.500850V            0.486130V
-17.9798ns         0.478820V         0.501040V            0.486140V
-18.1818ns         0.478870V         0.501230V            0.486150V
-18.3838ns         0.478920V         0.501420V            0.486160V
-18.5859ns         0.478970V         0.501600V            0.486160V
-18.7879ns         0.479010V         0.501750V            0.486170V
-18.9899ns         0.479050V         0.501890V            0.486170V
-19.1919ns         0.479090V         0.502030V            0.486180V
-19.3939ns         0.479130V         0.502160V            0.486190V
-19.5960ns         0.479160V         0.502290V            0.486190V
-19.7980ns         0.479190V         0.502400V            0.486190V
-20.0000ns         0.479220V         0.502510V            0.486200V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              0.479590V         0.504150V            0.486240V
-0.2020ns          0.479620V         0.504110V            0.490470V
-0.4040ns          0.474700V         0.515850V            0.339650V
-0.6061ns          0.247410V         0.518820V            26.921000mV
-0.8081ns          33.630000mV       0.443630V            3.148700mV
-1.0101ns          5.280400mV        0.238780V            1.060300mV
-1.2121ns          1.954600mV        78.283000mV          0.294910mV
-1.4141ns          1.002900mV        15.120000mV          0.121950mV
-1.6162ns          0.281790mV        5.205600mV           54.285000uV
-1.8182ns          0.158200mV        2.668100mV           18.736000uV
-2.0202ns          86.848000uV       1.413600mV           -3.438700uV
-2.2222ns          51.525000uV       0.962940mV           -2.338900uV
-2.4242ns          18.844000uV       0.395150mV           -0.402350mV
-2.6263ns          5.905300uV        0.211990mV           -8.792700uV
-2.8283ns          1.900600uV        0.117500mV           -65.770000uV
-3.0303ns          -0.928100uV       94.558000uV          -55.523000uV
-3.2323ns          1.519900uV        57.044000uV          -52.135000uV
-3.4343ns          91.150000uV       30.103000uV          -44.758000uV
-3.6364ns          -33.181000uV      19.965000uV          -45.346000uV
-3.8384ns          -61.875000uV      10.378000uV          -43.013000uV
-4.0404ns          -55.678000uV      5.470400uV           -40.659000uV
-4.2424ns          -56.185000uV      2.225700uV           -38.424000uV
-4.4444ns          -54.079000uV      0.339030uV           -36.424000uV
-4.6465ns          -49.722000uV      42.294000nV          -34.475000uV
-4.8485ns          -47.356000uV      -67.623000uV         -32.629000uV
-5.0505ns          -45.017000uV      0.334260mV           -30.892000uV
-5.2525ns          -42.772000uV      24.321000uV          -29.369000uV
-5.4545ns          -40.550000uV      -57.294000uV         -27.879000uV
-5.6566ns          -38.605000uV      -81.026000uV         -26.455000uV
-5.8586ns          -36.728000uV      -83.374000uV         -25.106000uV
-6.0606ns          -34.884000uV      -73.915000uV         -23.906000uV
-6.2626ns          -33.048000uV      -70.059000uV         -22.718000uV
-6.4646ns          -31.513000uV      -66.837000uV         -21.555000uV
-6.6667ns          -30.051000uV      -63.741000uV         -20.455000uV
-6.8687ns          -28.580000uV      -60.682000uV         -19.480000uV
-7.0707ns          -27.108000uV      -57.943000uV         -18.510000uV
-7.2727ns          -25.888000uV      -55.297000uV         -17.548000uV
-7.4747ns          -24.730000uV      -52.722000uV         -16.641000uV
-7.6768ns          -23.520000uV      -50.167000uV         -15.845000uV
-7.8788ns          -22.298000uV      -47.891000uV         -15.046000uV
-8.0808ns          -21.294000uV      -45.695000uV         -14.242000uV
-8.2828ns          -20.344000uV      -43.550000uV         -13.487000uV
-8.4848ns          -19.327000uV      -41.420000uV         -12.832000uV
-8.6869ns          -18.294000uV      -39.563000uV         -12.169000uV
-8.8889ns          -17.459000uV      -37.784000uV         -11.491000uV
-9.0909ns          -16.672000uV      -36.017000uV         -10.860000uV
-9.2929ns          -15.813000uV      -34.253000uV         -10.318000uV
-9.4949ns          -14.935000uV      -32.736000uV         -9.766400uV
-9.6970ns          -14.237000uV      -31.289000uV         -9.192700uV
-9.8990ns          -13.584000uV      -29.817000uV         -8.661200uV
-10.1010ns         -12.478000uV      -27.709000uV         -7.982350uV
-10.3030ns         -11.518000uV      -25.885000uV         -7.262900uV
-10.5051ns         -10.975000uV      -24.642000uV         -6.813500uV
-10.7071ns         -10.351000uV      -23.387000uV         -6.441800uV
-10.9091ns         -9.707800uV       -22.333000uV         -6.054500uV
-11.1111ns         -9.217800uV       -21.337000uV         -5.636200uV
-11.3131ns         -8.765200uV       -20.281000uV         -5.254700uV
-11.5152ns         -8.231600uV       -19.208000uV         -4.946000uV
-11.7172ns         -7.678200uV       -18.321000uV         -4.620100uV
-11.9192ns         -7.266900uV       -17.488000uV         -4.260300uV
-12.1212ns         -6.890500uV       -16.587000uV         -3.935200uV
-12.3232ns         -6.432500uV       -15.666000uV         -3.678600uV
-12.5253ns         -5.954600uV       -14.919000uV         -3.403800uV
-12.7273ns         -5.609300uV       -14.221000uV         -3.092900uV
-12.9293ns         -5.296400uV       -13.450000uV         -2.814900uV
-13.1313ns         -4.902200uV       -12.657000uV         -2.601600uV
-13.3333ns         -4.488100uV       -12.026000uV         -2.369400uV
-13.5354ns         -4.198200uV       -11.442000uV         -2.099800uV
-13.7374ns         -3.938700uV       -10.780000uV         -1.861200uV
-13.9394ns         -3.598400uV       -10.096000uV         -1.684200uV
-14.1414ns         -3.238300uV       -9.563600uV          -1.487800uV
-14.3434ns         -2.995000uV       -9.074900uV          -1.252900uV
-14.5455ns         -2.780300uV       -8.505800uV          -1.047700uV
-14.7475ns         -2.485800uV       -7.913400uV          -0.901200uV
-14.9495ns         -2.171700uV       -7.464100uV          -0.734910uV
-15.1515ns         -1.967700uV       -7.055800uV          -0.529500uV
-15.3535ns         -1.790700uV       -6.565500uV          -0.352370uV
-15.5556ns         -1.535100uV       -6.051500uV          -0.231220uV
-15.7576ns         -1.260300uV       -5.672300uV          -90.901000nV
-15.9596ns         -1.089700uV       -5.331900uV          87.337000nV
-16.1616ns         -0.944660uV       -4.908600uV          0.238960uV
-16.3636ns         -0.722200uV       -4.461500uV          0.337930uV
-16.5657ns         -0.480790uV       -4.141700uV          0.456510uV
-16.7677ns         -0.338220uV       -3.858700uV          0.613870uV
-16.9697ns         -0.219860uV       -3.492600uV          0.746520uV
-17.1717ns         -26.846000nV      -3.102500uV          0.830300uV
-17.3737ns         0.184450uV        -2.833200uV          0.932440uV
-17.5758ns         0.301760uV        -2.598700uV          1.070900uV
-17.7778ns         0.396050uV        -2.281300uV          1.185800uV
-17.9798ns         0.563350uV        -1.940200uV          1.253900uV
-18.1818ns         0.748530uV        -1.713800uV          1.340400uV
-18.3838ns         0.849240uV        -1.520500uV          1.463300uV
-18.5859ns         0.929260uV        -1.244900uV          1.563400uV
-18.7879ns         1.076500uV        -0.945630uV          1.618300uV
-18.9899ns         1.240200uV        -0.755480uV          1.685500uV
-19.1919ns         1.323300uV        -0.596720uV          1.777100uV
-19.3939ns         1.386600uV        -0.356900uV          1.868700uV
-19.5960ns         1.516000uV        -93.762000nV         1.960300uV
-19.7980ns         1.661600uV        58.234000nV          2.029300uV
-20.0000ns         1.679900uV        0.178250uV           2.053600uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468600V
-0.4040ns          3.300900V         3.139100V            3.481500V
-0.6061ns          3.273500V         3.140100V            3.087100V
-0.8081ns          2.996200V         3.146300V            2.839700V
-1.0101ns          2.788200V         3.080900V            2.749500V
-1.2121ns          2.688900V         2.938500V            2.718000V
-1.4141ns          2.644300V         2.755500V            2.708000V
-1.6162ns          2.624600V         2.644100V            2.704400V
-1.8182ns          2.616600V         2.580800V            2.704300V
-2.0202ns          2.613600V         2.541800V            2.704600V
-2.2222ns          2.612200V         2.522600V            2.705800V
-2.4242ns          2.612400V         2.511700V            2.715900V
-2.6263ns          2.613100V         2.506400V            2.750300V
-2.8283ns          2.613800V         2.503800V            2.759900V
-3.0303ns          2.614700V         2.502700V            2.769100V
-3.2323ns          2.615500V         2.502100V            2.777600V
-3.4343ns          2.621600V         2.502400V            2.785300V
-3.6364ns          2.628100V         2.502800V            2.792600V
-3.8384ns          2.632500V         2.503300V            2.799400V
-4.0404ns          2.639100V         2.503900V            2.806100V
-4.2424ns          2.645800V         2.504500V            2.812200V
-4.4444ns          2.652000V         2.505100V            2.818200V
-4.6465ns          2.658100V         2.505700V            2.823700V
-4.8485ns          2.663800V         2.508100V            2.829100V
-5.0505ns          2.669000V         2.489000V            2.834000V
-5.2525ns          2.674300V         2.476800V            2.838800V
-5.4545ns          2.679100V         2.477300V            2.843300V
-5.6566ns          2.683900V         2.482300V            2.847700V
-5.8586ns          2.688200V         2.488300V            2.851700V
-6.0606ns          2.692500V         2.494500V            2.855700V
-6.2626ns          2.696400V         2.500200V            2.859400V
-6.4646ns          2.700300V         2.505800V            2.863000V
-6.6667ns          2.703900V         2.511100V            2.866300V
-6.8687ns          2.707400V         2.516200V            2.869600V
-7.0707ns          2.710700V         2.521000V            2.872700V
-7.2727ns          2.713900V         2.525700V            2.875700V
-7.4747ns          2.716900V         2.530100V            2.878500V
-7.6768ns          2.719800V         2.534400V            2.881200V
-7.8788ns          2.722500V         2.538400V            2.883800V
-8.0808ns          2.725200V         2.542300V            2.886300V
-8.2828ns          2.727700V         2.545900V            2.888700V
-8.4848ns          2.730200V         2.549500V            2.891000V
-8.6869ns          2.732400V         2.552800V            2.893100V
-8.8889ns          2.734700V         2.556100V            2.895300V
-9.0909ns          2.736800V         2.559100V            2.897300V
-9.2929ns          2.738800V         2.562100V            2.899200V
-9.4949ns          2.740700V         2.564900V            2.901100V
-9.6970ns          2.742600V         2.567700V            2.903000V
-9.8990ns          2.744300V         2.570200V            2.904700V
-10.1010ns         2.746850V         2.573900V            2.907350V
-10.3030ns         2.749200V         2.577400V            2.909900V
-10.5051ns         2.750700V         2.579600V            2.911600V
-10.7071ns         2.752100V         2.581700V            2.913200V
-10.9091ns         2.753400V         2.583700V            2.914800V
-11.1111ns         2.754700V         2.585700V            2.916300V
-11.3131ns         2.756000V         2.587500V            2.917800V
-11.5152ns         2.757200V         2.589300V            2.919300V
-11.7172ns         2.758300V         2.591000V            2.920700V
-11.9192ns         2.759400V         2.592600V            2.922000V
-12.1212ns         2.760400V         2.594200V            2.923300V
-12.3232ns         2.761400V         2.595700V            2.924600V
-12.5253ns         2.762300V         2.597100V            2.925800V
-12.7273ns         2.763200V         2.598500V            2.927000V
-12.9293ns         2.764000V         2.599800V            2.928100V
-13.1313ns         2.764900V         2.601100V            2.929200V
-13.3333ns         2.765600V         2.602300V            2.930200V
-13.5354ns         2.766400V         2.603500V            2.931300V
-13.7374ns         2.767100V         2.604600V            2.932200V
-13.9394ns         2.767800V         2.605700V            2.933200V
-14.1414ns         2.768400V         2.606800V            2.934100V
-14.3434ns         2.769000V         2.607800V            2.935000V
-14.5455ns         2.769600V         2.608700V            2.935800V
-14.7475ns         2.770200V         2.609600V            2.936600V
-14.9495ns         2.770700V         2.610500V            2.937400V
-15.1515ns         2.771200V         2.611300V            2.938200V
-15.3535ns         2.771700V         2.612100V            2.938900V
-15.5556ns         2.772200V         2.612900V            2.939600V
-15.7576ns         2.772600V         2.613600V            2.940300V
-15.9596ns         2.773000V         2.614400V            2.941000V
-16.1616ns         2.773400V         2.615000V            2.941600V
-16.3636ns         2.773800V         2.615700V            2.942200V
-16.5657ns         2.774100V         2.616300V            2.942800V
-16.7677ns         2.774400V         2.616900V            2.943400V
-16.9697ns         2.774700V         2.617500V            2.943900V
-17.1717ns         2.775000V         2.618000V            2.944500V
-17.3737ns         2.775300V         2.618600V            2.945000V
-17.5758ns         2.775600V         2.619100V            2.945500V
-17.7778ns         2.775800V         2.619500V            2.945900V
-17.9798ns         2.776100V         2.620000V            2.946400V
-18.1818ns         2.776300V         2.620400V            2.946900V
-18.3838ns         2.776500V         2.620900V            2.947300V
-18.5859ns         2.776700V         2.621300V            2.947700V
-18.7879ns         2.776900V         2.621700V            2.948100V
-18.9899ns         2.777100V         2.622000V            2.948500V
-19.1919ns         2.777200V         2.622400V            2.948900V
-19.3939ns         2.777400V         2.622700V            2.949300V
-19.5960ns         2.777500V         2.623000V            2.949600V
-19.7980ns         2.777700V         2.623300V            2.950000V
-20.0000ns         2.777800V         2.623600V            2.950300V
-|  
-| End [Model] lvc330f040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330fxxxaaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.201000pA       1.415500nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-| End [Model] lvc330fxxxaaaaaaaain
-|************************************************************************
-[Model]           lvc330fxxxbaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201050A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133030A
-  -1.38    -0.116640A        -0.121710A           -0.116640A
-  -1.30    -0.101410A        -0.107420A           -0.100700A
-  -1.22    -86.417000mA      -93.409000mA         -84.978000mA
-  -1.14    -71.666000mA      -79.637000mA         -69.556000mA
-  -1.06    -57.221000mA      -66.146000mA         -54.661000mA
-  -0.98    -43.217000mA      -53.024000mA         -40.890000mA
-  -0.90    -29.927000mA      -40.408000mA         -29.654000mA
-  -0.82    -17.982000mA      -28.511000mA         -21.115000mA
-  -0.74    -8.854400mA       -17.682000mA         -13.653000mA
-  -0.66    -3.663100mA       -8.577600mA          -7.237700mA
-  -0.58    -1.172200mA       -2.564300mA          -2.648300mA
-  -0.50    -0.318120mA       -0.464400mA          -0.594790mA
-  -0.42    -0.137880mA       -0.131860mA          -0.170510mA
-  -0.34    -0.109480mA       -92.671000uA         -0.122000mA
-  -0.26    -0.105780mA       -87.760000uA         -0.117970mA
-  -0.18    -0.105360mA       -87.079000uA         -0.117690mA
-  -0.10    -0.105300mA       -86.972000uA         -0.117660mA
-  -0.02    -0.105290mA       -86.946000uA         -0.117640mA
-  0.06    -0.105270mA       -86.931000uA         -0.117630mA
-  0.14    -0.105260mA       -86.918000uA         -0.117610mA
-  0.22    -0.105240mA       -86.905000uA         -0.117600mA
-  0.30    -0.105230mA       -86.892000uA         -0.117580mA
-  0.38    -0.105220mA       -86.878000uA         -0.117560mA
-  0.46    -0.105200mA       -86.864000uA         -0.117540mA
-  0.54    -0.105180mA       -86.849000uA         -0.117530mA
-  0.62    -0.105170mA       -86.834000uA         -0.117500mA
-  0.70    -0.105150mA       -86.818000uA         -0.117480mA
-  0.78    -0.105130mA       -86.801000uA         -0.117460mA
-  0.86    -0.105110mA       -86.783000uA         -0.117420mA
-  0.94    -0.105060mA       -86.761000uA         -0.117350mA
-  1.02    -0.105000mA       -86.718000uA         -0.117250mA
-  1.10    -0.104900mA       -86.652000uA         -0.117140mA
-  1.18    -0.104790mA       -86.563000uA         -0.117010mA
-  1.26    -0.104660mA       -86.454000uA         -0.116870mA
-  1.34    -0.104520mA       -86.328000uA         -0.116710mA
-  1.42    -0.104360mA       -86.186000uA         -0.116550mA
-  1.50    -0.104190mA       -86.027000uA         -0.116380mA
-  1.58    -0.104010mA       -85.852000uA         -0.116200mA
-  1.66    -0.103810mA       -85.660000uA         -0.116010mA
-  1.74    -0.103600mA       -85.448000uA         -0.115810mA
-  1.82    -0.103380mA       -85.214000uA         -0.115600mA
-  1.90    -0.103130mA       -84.953000uA         -0.115380mA
-  1.98    -0.102860mA       -84.659000uA         -0.115140mA
-  2.06    -0.102560mA       -84.336000uA         -0.114880mA
-  2.14    -0.102230mA       -83.988000uA         -0.114600mA
-  2.22    -0.101860mA       -83.605000uA         -0.114300mA
-  2.30    -0.101430mA       -83.172000uA         -0.113960mA
-  2.38    -0.100960mA       -82.673000uA         -0.113590mA
-  2.46    -0.100430mA       -82.088000uA         -0.113170mA
-  2.54    -99.809000uA      -81.393000uA         -0.112690mA
-  2.62    -99.072000uA      -80.257000uA         -0.112130mA
-  2.70    -98.172000uA      -76.079000uA         -0.111480mA
-  2.78    -97.041000uA      -68.566000uA         -0.110710mA
-  2.86    -94.411000uA      -58.013000uA         -0.109770mA
-  2.94    -86.817000uA      -44.639000uA         -0.108560mA
-  3.02    -74.531000uA      -28.610000uA         -0.106940mA
-  3.10    -57.975000uA      -10.054000uA         -0.102590mA
-  3.18    -37.471000uA      11.025000uA          -91.172000uA
-  3.26    -13.273000uA      34.949000uA          -73.303000uA
-  3.30    0.149480uA        48.450000uA          -62.148000uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.925400uA        1.695300uA           2.182200uA
-  -3.26    1.907100uA        1.679500uA           2.161600uA
-  -3.22    1.889100uA        1.664000uA           2.141300uA
-  -3.18    1.871200uA        1.648600uA           2.121100uA
-  -3.14    1.853600uA        1.633400uA           2.101200uA
-  -3.10    1.836100uA        1.618400uA           2.081400uA
-  -3.06    1.818900uA        1.603500uA           2.061900uA
-  -3.02    1.801800uA        1.588800uA           2.042600uA
-  -2.98    1.785000uA        1.574200uA           2.023500uA
-  -2.94    1.768300uA        1.559800uA           2.004600uA
-  -2.90    1.751800uA        1.545600uA           1.985900uA
-  -2.86    1.735600uA        1.531500uA           1.967400uA
-  -2.82    1.719500uA        1.517600uA           1.949100uA
-  -2.78    1.703600uA        1.503800uA           1.931100uA
-  -2.74    1.687800uA        1.490200uA           1.913200uA
-  -2.70    1.672300uA        1.476700uA           1.895500uA
-  -2.66    1.657000uA        1.463400uA           1.878100uA
-  -2.62    1.641800uA        1.450200uA           1.860800uA
-  -2.58    1.626800uA        1.437200uA           1.843800uA
-  -2.54    1.612000uA        1.424300uA           1.827000uA
-  -2.50    1.597400uA        1.411500uA           1.810300uA
-  -2.46    1.582900uA        1.398900uA           1.793900uA
-  -2.42    1.568600uA        1.386500uA           1.777600uA
-  -2.38    1.554500uA        1.374100uA           1.761600uA
-  -2.34    1.540600uA        1.361900uA           1.745700uA
-  -2.30    1.526800uA        1.349900uA           1.730100uA
-  -2.26    1.513300uA        1.337900uA           1.714600uA
-  -2.22    1.499800uA        1.326100uA           1.699300uA
-  -2.18    1.486600uA        1.314500uA           1.684300uA
-  -2.14    1.473500uA        1.302900uA           1.669400uA
-  -2.10    1.460500uA        1.291500uA           1.654700uA
-  -2.06    1.447700uA        1.280200uA           1.640100uA
-  -2.02    1.435100uA        1.269000uA           1.625800uA
-  -1.98    1.422600uA        1.257900uA           1.611700uA
-  -1.94    1.410300uA        1.247000uA           1.597700uA
-  -1.90    1.398200uA        1.236200uA           1.583900uA
-  -1.86    1.386100uA        1.225500uA           1.570300uA
-  -1.82    1.374300uA        1.214800uA           1.556900uA
-  -1.78    1.362500uA        1.204400uA           1.543600uA
-  -1.74    1.351000uA        1.194000uA           1.530500uA
-  -1.70    1.339500uA        1.183700uA           1.517600uA
-  -1.66    1.328200uA        1.173500uA           1.504900uA
-  -1.62    1.317000uA        1.163400uA           1.492300uA
-  -1.58    1.306000uA        1.153500uA           1.479900uA
-  -1.54    1.295100uA        1.143600uA           1.467600uA
-  -1.50    1.284300uA        1.133800uA           1.455500uA
-  -1.46    1.273700uA        1.124100uA           1.443600uA
-  -1.42    1.263200uA        1.114500uA           1.431800uA
-  -1.38    1.252800uA        1.105000uA           1.420200uA
-  -1.34    1.242500uA        1.095600uA           1.408700uA
-  -1.30    1.232300uA        1.086200uA           1.397400uA
-  -1.26    1.222300uA        1.077000uA           1.386200uA
-  -1.22    1.212300uA        1.067800uA           1.375200uA
-  -1.18    1.202500uA        1.058700uA           1.364300uA
-  -1.14    1.192800uA        1.049700uA           1.353500uA
-  -1.10    1.183200uA        1.040800uA           1.342900uA
-  -1.06    1.173700uA        1.031900uA           1.332400uA
-  -1.02    1.164300uA        1.023100uA           1.322100uA
-  -0.98    1.154900uA        1.014400uA           1.311900uA
-  -0.94    1.145700uA        1.005700uA           1.301800uA
-  -0.90    1.136600uA        0.997110uA           1.291800uA
-  -0.86    1.127600uA        0.988570uA           1.281900uA
-  -0.82    1.118600uA        0.980090uA           1.272200uA
-  -0.78    1.109700uA        0.971680uA           1.262500uA
-  -0.74    1.100900uA        0.963320uA           1.253000uA
-  -0.70    1.092200uA        0.955010uA           1.243600uA
-  -0.66    1.083600uA        0.946770uA           1.234300uA
-  -0.62    1.075000uA        0.938590uA           1.225100uA
-  -0.58    1.066500uA        0.930470uA           1.215900uA
-  -0.54    1.058100uA        0.922430uA           1.206900uA
-  -0.50    1.049700uA        0.914500uA           1.198000uA
-  -0.46    1.041400uA        0.906750uA           1.189000uA
-  -0.42    1.033100uA        0.899340uA           1.180100uA
-  -0.38    1.024800uA        0.892740uA           1.171100uA
-  -0.34    1.020592uA        0.890363uA           1.166191uA
-  -0.30    1.020569uA        0.890343uA           1.166164uA
-  -0.26    1.020475uA        0.890261uA           1.166058uA
-  -0.22    1.020102uA        0.889935uA           1.165631uA
-  -0.18    1.018607uA        0.888631uA           1.163922uA
-  -0.14    1.012627uA        0.883414uA           1.157089uA
-  -0.10    0.988706uA        0.862546uA           1.129756uA
-  -0.06    0.893025uA        0.779074uA           1.020425uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-| End [Model] lvc330fxxxbaaaaaaain
-|************************************************************************
-[Model]           lvc330fxxxcaaaaaaain
-Model_type        Input
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447790A           -0.471180A
-  -2.18    -0.421140A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201050A           -0.209560A
-  -1.62    -0.174190A        -0.174390A           -0.177660A
-  -1.54    -0.150480A        -0.153310A           -0.151880A
-  -1.46    -0.132440A        -0.136600A           -0.133040A
-  -1.38    -0.116650A        -0.121720A           -0.116660A
-  -1.30    -0.101420A        -0.107430A           -0.100730A
-  -1.22    -86.431000mA      -93.414000mA         -85.016000mA
-  -1.14    -71.684000mA      -79.643000mA         -69.612000mA
-  -1.06    -57.245000mA      -66.154000mA         -54.753000mA
-  -0.98    -43.252000mA      -53.034000mA         -41.074000mA
-  -0.90    -29.984000mA      -40.420000mA         -30.037000mA
-  -0.82    -18.095000mA      -28.529000mA         -21.592000mA
-  -0.74    -9.103200mA       -17.711000mA         -14.139000mA
-  -0.66    -4.031300mA       -8.632500mA          -7.727000mA
-  -0.58    -1.542300mA       -2.680900mA          -3.137100mA
-  -0.50    -0.637910mA       -0.641580mA          -1.050200mA
-  -0.42    -0.382200mA       -0.283040mA          -0.537030mA
-  -0.34    -0.274320mA       -0.191220mA          -0.380580mA
-  -0.26    -0.195030mA       -0.134430mA          -0.271430mA
-  -0.18    -0.125260mA       -86.198000uA         -0.174070mA
-  -0.10    -63.603000uA      -43.916000uA         -87.706000uA
-  -0.02    -11.477000uA      -8.053000uA          -15.489000uA
-  0.06    29.171000uA       20.579000uA          38.171000uA
-  0.14    58.135000uA       42.109000uA          72.311000uA
-  0.22    76.454000uA       57.027000uA          90.391000uA
-  0.30    86.646000uA       66.282000uA          99.147000uA
-  0.38    91.915000uA       71.334000uA          0.103720mA
-  0.46    94.550000uA       73.863000uA          0.106370mA
-  0.54    95.817000uA       75.185000uA          0.107930mA
-  0.62    96.442000uA       75.976000uA          0.108770mA
-  0.70    96.793000uA       76.516000uA          0.109190mA
-  0.78    97.021000uA       76.923000uA          0.109410mA
-  0.86    97.187000uA       77.250000uA          0.109550mA
-  0.94    97.320000uA       77.526000uA          0.109650mA
-  1.02    97.431000uA       77.766000uA          0.109720mA
-  1.10    97.528000uA       77.982000uA          0.109790mA
-  1.18    97.616000uA       78.178000uA          0.109850mA
-  1.26    97.697000uA       78.360000uA          0.109900mA
-  1.34    97.773000uA       78.530000uA          0.109950mA
-  1.42    97.844000uA       78.691000uA          0.110000mA
-  1.50    97.912000uA       78.844000uA          0.110050mA
-  1.58    97.978000uA       78.991000uA          0.110090mA
-  1.66    98.042000uA       79.132000uA          0.110130mA
-  1.74    98.104000uA       79.268000uA          0.110170mA
-  1.82    98.164000uA       79.399000uA          0.110220mA
-  1.90    98.223000uA       79.526000uA          0.110260mA
-  1.98    98.280000uA       79.648000uA          0.110300mA
-  2.06    98.337000uA       79.768000uA          0.110330mA
-  2.14    98.393000uA       79.890000uA          0.110370mA
-  2.22    98.448000uA       80.015000uA          0.110410mA
-  2.30    98.503000uA       80.140000uA          0.110450mA
-  2.38    98.559000uA       80.265000uA          0.110490mA
-  2.46    98.617000uA       80.391000uA          0.110530mA
-  2.54    98.679000uA       80.518000uA          0.110570mA
-  2.62    98.744000uA       80.648000uA          0.110620mA
-  2.70    98.813000uA       80.782000uA          0.110670mA
-  2.78    98.889000uA       80.922000uA          0.110720mA
-  2.86    98.972000uA       81.070000uA          0.110780mA
-  2.94    99.065000uA       81.227000uA          0.110850mA
-  3.02    99.170000uA       81.396000uA          0.110930mA
-  3.10    99.290000uA       81.580000uA          0.111020mA
-  3.18    99.427000uA       81.843000uA          0.111120mA
-  3.26    99.584000uA       82.507000uA          0.111250mA
-  3.30    99.674000uA       83.566000uA          0.111320mA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    0.153710mA        0.132100mA           0.170160mA
-  -3.26    0.152730mA        0.131080mA           0.169210mA
-  -3.22    0.151750mA        0.130060mA           0.168250mA
-  -3.18    0.150760mA        0.129030mA           0.167280mA
-  -3.14    0.149760mA        0.128000mA           0.166290mA
-  -3.10    0.148750mA        0.126970mA           0.165290mA
-  -3.06    0.147740mA        0.125930mA           0.164280mA
-  -3.02    0.146720mA        0.124900mA           0.163270mA
-  -2.98    0.145700mA        0.123870mA           0.162240mA
-  -2.94    0.144670mA        0.122850mA           0.161210mA
-  -2.90    0.143640mA        0.121820mA           0.160170mA
-  -2.86    0.142610mA        0.120800mA           0.159120mA
-  -2.82    0.141580mA        0.119780mA           0.158070mA
-  -2.78    0.140550mA        0.118770mA           0.157010mA
-  -2.74    0.139520mA        0.117770mA           0.155950mA
-  -2.70    0.138490mA        0.116770mA           0.154890mA
-  -2.66    0.137460mA        0.115780mA           0.153830mA
-  -2.62    0.136440mA        0.114800mA           0.152760mA
-  -2.58    0.135420mA        0.113820mA           0.151700mA
-  -2.54    0.134410mA        0.112860mA           0.150630mA
-  -2.50    0.133400mA        0.111900mA           0.149570mA
-  -2.46    0.132400mA        0.110960mA           0.148510mA
-  -2.42    0.131410mA        0.110030mA           0.147460mA
-  -2.38    0.130420mA        0.109110mA           0.146410mA
-  -2.34    0.129450mA        0.108200mA           0.145370mA
-  -2.30    0.128490mA        0.107310mA           0.144330mA
-  -2.26    0.127530mA        0.106430mA           0.143310mA
-  -2.22    0.126590mA        0.105570mA           0.142290mA
-  -2.18    0.125660mA        0.104720mA           0.141280mA
-  -2.14    0.124750mA        0.103880mA           0.140280mA
-  -2.10    0.123850mA        0.103060mA           0.139300mA
-  -2.06    0.122960mA        0.102260mA           0.138330mA
-  -2.02    0.122090mA        0.101480mA           0.137370mA
-  -1.98    0.121230mA        0.100710mA           0.136420mA
-  -1.94    0.120390mA        99.955000uA          0.135490mA
-  -1.90    0.119560mA        99.221000uA          0.134580mA
-  -1.86    0.118760mA        98.504000uA          0.133680mA
-  -1.82    0.117970mA        97.804000uA          0.132800mA
-  -1.78    0.117200mA        97.123000uA          0.131940mA
-  -1.74    0.116440mA        96.459000uA          0.131090mA
-  -1.70    0.115710mA        95.814000uA          0.130260mA
-  -1.66    0.114990mA        95.186000uA          0.129460mA
-  -1.62    0.114300mA        94.577000uA          0.128670mA
-  -1.58    0.113620mA        93.985000uA          0.127900mA
-  -1.54    0.112960mA        93.412000uA          0.127150mA
-  -1.50    0.112320mA        92.857000uA          0.126420mA
-  -1.46    0.111700mA        92.319000uA          0.125710mA
-  -1.42    0.111100mA        91.799000uA          0.125030mA
-  -1.38    0.110520mA        91.297000uA          0.124360mA
-  -1.34    0.109960mA        90.812000uA          0.123710mA
-  -1.30    0.109420mA        90.344000uA          0.123090mA
-  -1.26    0.108900mA        89.893000uA          0.122490mA
-  -1.22    0.108400mA        89.459000uA          0.121900mA
-  -1.18    0.107910mA        89.041000uA          0.121340mA
-  -1.14    0.107450mA        88.639000uA          0.120800mA
-  -1.10    0.107000mA        88.253000uA          0.120280mA
-  -1.06    0.106570mA        87.883000uA          0.119780mA
-  -1.02    0.106160mA        87.527000uA          0.119300mA
-  -0.98    0.105760mA        87.187000uA          0.118840mA
-  -0.94    0.105390mA        86.861000uA          0.118400mA
-  -0.90    0.105030mA        86.548000uA          0.117980mA
-  -0.86    0.104690mA        86.250000uA          0.117580mA
-  -0.82    0.104360mA        85.965000uA          0.117190mA
-  -0.78    0.104050mA        85.693000uA          0.116830mA
-  -0.74    0.103750mA        85.433000uA          0.116480mA
-  -0.70    0.103470mA        85.185000uA          0.116150mA
-  -0.66    0.103200mA        84.949000uA          0.115830mA
-  -0.62    0.102950mA        84.724000uA          0.115540mA
-  -0.58    0.102710mA        84.509000uA          0.115260mA
-  -0.54    0.102490mA        84.306000uA          0.114990mA
-  -0.50    0.102270mA        84.112000uA          0.114740mA
-  -0.46    0.102070mA        83.927000uA          0.114500mA
-  -0.42    0.101880mA        83.752000uA          0.114280mA
-  -0.38    0.101700mA        83.587000uA          0.114070mA
-  -0.34    0.101620mA        83.508000uA          0.113960mA
-  -0.30    0.101620mA        83.508000uA          0.113960mA
-  -0.26    0.101620mA        83.508000uA          0.113960mA
-  -0.22    0.101620mA        83.508000uA          0.113960mA
-  -0.18    0.101620mA        83.508000uA          0.113750mA
-  -0.14    0.100460mA        82.918000uA          0.112450mA
-  -0.10    0.100030mA        82.241000uA          0.112040mA
-  -0.06    99.844000uA       81.938000uA          0.111870mA
-  -0.02    99.724000uA       81.761000uA          0.111750mA
-  0.00    99.674000uA       81.693000uA          0.111690mA
-|  
-| End [Model] lvc330fxxxcaaaaaaain
-|************************************************************************
-[Model]           lvc330s040aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
-  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
-  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
-  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
-  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
-  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
-  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
-  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
-  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
-  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
-  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
-  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
-  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
-  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
-  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
-  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
-  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
-  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
-  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
-  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
-  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
-  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
-  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
-  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
-  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
-  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
-  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
-  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
-  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
-  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
-  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
-  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
-  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
-  0.00    9.270000nA        8.640000nA           10.950000nA
-  0.10    2.215985mA        1.960397mA           2.507890mA
-  0.20    4.086375mA        3.683686mA           4.498680mA
-  0.30    5.594166mA        5.150675mA           5.952471mA
-  0.40    6.738256mA        6.352364mA           6.929962mA
-  0.50    7.557146mA        7.289853mA           7.572152mA
-  0.60    8.124436mA        7.983242mA           8.013343mA
-  0.70    8.511126mA        8.476831mA           8.337834mA
-  0.80    8.778316mA        8.826620mA           8.591424mA
-  0.90    8.972606mA        9.080609mA           8.798515mA
-  1.00    9.121395mA        9.272098mA           8.969206mA
-  1.10    9.240584mA        9.422087mA           9.101296mA
-  1.20    9.339574mA        9.543476mA           9.202186mA
-  1.30    9.424063mA        9.644765mA           9.285275mA
-  1.40    9.498053mA        9.731354mA           9.357665mA
-  1.50    9.564242mA        9.806743mA           9.423455mA
-  1.60    9.625232mA        9.873832mA           9.485944mA
-  1.70    9.684621mA        9.934821mA           9.548134mA
-  1.80    9.747011mA        9.992810mA           9.610224mA
-  1.90    9.814800mA        10.052999mA          9.670813mA
-  2.00    9.885689mA        10.122988mA          9.728603mA
-  2.10    9.955379mA        10.203977mA          9.783293mA
-  2.20    10.021968mA       10.292966mA          9.835282mA
-  2.30    10.083958mA       10.380954mA          9.884972mA
-  2.40    10.141947mA       10.464943mA          9.932861mA
-  2.50    10.196936mA       10.542932mA          9.979551mA
-  2.60    10.249926mA       10.614921mA          10.025941mA
-  2.70    10.300915mA       10.681910mA          10.071930mA
-  2.80    10.350904mA       10.744899mA          10.118920mA
-  2.90    10.400894mA       10.805888mA          10.167909mA
-  3.00    10.451883mA       10.863877mA          10.218899mA
-  3.10    10.504872mA       10.921864mA          10.273889mA
-  3.20    10.559862mA       10.978747mA          10.332878mA
-  3.30    10.618848mA       11.037379mA          10.397868mA
-  3.40    10.682725mA       11.085335mA          10.469857mA
-  3.50    10.751986mA       11.124616mA          10.550843mA
-  3.60    10.804292mA       11.163898mA          10.640599mA
-  3.70    10.840604mA       11.203179mA          10.738212mA
-  3.80    10.876916mA       11.242461mA          10.773505mA
-  3.90    10.913228mA       11.281743mA          10.808797mA
-  4.00    10.949540mA       11.321024mA          10.844090mA
-  4.10    10.985852mA       11.360306mA          10.879382mA
-  4.20    11.022164mA       11.399587mA          10.914675mA
-  4.30    11.058476mA       11.438869mA          10.949967mA
-  4.40    11.094788mA       11.478151mA          10.985259mA
-  4.50    11.131100mA       11.517432mA          11.020552mA
-  4.60    11.167412mA       11.556714mA          11.055844mA
-  4.70    11.203724mA       11.595995mA          11.091137mA
-  4.80    11.240036mA       11.635277mA          11.126429mA
-  4.90    11.276348mA       11.674559mA          11.161721mA
-  5.00    11.312660mA       11.713840mA          11.197014mA
-  5.10    11.348972mA       11.753122mA          11.232306mA
-  5.20    11.385284mA       11.792403mA          11.267599mA
-  5.30    11.421596mA       11.831685mA          11.302891mA
-  5.40    11.457908mA       11.870967mA          11.338183mA
-  5.50    11.494220mA       11.910248mA          11.373476mA
-  5.60    11.530532mA       11.949530mA          11.408768mA
-  5.70    11.566844mA       11.988811mA          11.444061mA
-  5.80    11.603156mA       12.028093mA          11.479353mA
-  5.90    11.639468mA       12.067375mA          11.514645mA
-  6.00    11.675780mA       12.106656mA          11.549938mA
-  6.10    11.712092mA       12.145938mA          11.585230mA
-  6.20    11.748404mA       12.185219mA          11.620523mA
-  6.30    11.784716mA       12.224501mA          11.655815mA
-  6.40    11.821028mA       12.263783mA          11.691107mA
-  6.50    11.857340mA       12.303064mA          11.726400mA
-  6.60    11.893652mA       12.342346mA          11.761692mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    6.260163mA        5.384933mA           7.315403mA
-  -3.20    6.239699mA        5.366401mA           7.291487mA
-  -3.10    6.219236mA        5.347870mA           7.267570mA
-  -3.00    6.198773mA        5.329339mA           7.243653mA
-  -2.90    6.178310mA        5.310808mA           7.219736mA
-  -2.80    6.157847mA        5.292277mA           7.195819mA
-  -2.70    6.137383mA        5.273745mA           7.171903mA
-  -2.60    6.116920mA        5.255214mA           7.147986mA
-  -2.50    6.096457mA        5.236683mA           7.124069mA
-  -2.40    6.075994mA        5.218152mA           7.100152mA
-  -2.30    6.055531mA        5.199621mA           7.076235mA
-  -2.20    6.035067mA        5.181089mA           7.052319mA
-  -2.10    6.014604mA        5.162558mA           7.028402mA
-  -2.00    5.994141mA        5.144027mA           7.004485mA
-  -1.90    5.973678mA        5.125496mA           6.980568mA
-  -1.80    5.953215mA        5.106965mA           6.956651mA
-  -1.70    5.932751mA        5.088433mA           6.932735mA
-  -1.60    5.912288mA        5.069902mA           6.908818mA
-  -1.50    5.891825mA        5.051371mA           6.884901mA
-  -1.40    5.871362mA        5.032840mA           6.860984mA
-  -1.30    5.850899mA        5.014309mA           6.837067mA
-  -1.20    5.830435mA        4.995777mA           6.813151mA
-  -1.10    5.809972mA        4.977246mA           6.789234mA
-  -1.00    5.789509mA        4.958715mA           6.765317mA
-  -0.90    5.769046mA        4.940184mA           6.741400mA
-  -0.80    5.748583mA        4.921653mA           6.717483mA
-  -0.70    5.728119mA        4.903121mA           6.693567mA
-  -0.60    5.707656mA        4.884590mA           6.669650mA
-  -0.50    5.687193mA        4.866059mA           6.645733mA
-  -0.40    5.666730mA        4.847528mA           6.621816mA
-  -0.30    5.646267mA        4.828997mA           6.597899mA
-  -0.20    4.435786mA        3.802115mA           5.174820mA
-  -0.10    2.131925mA        1.838548mA           2.475669mA
-  0.00    -6.170000nA       -5.460000nA          -7.060000nA
-  0.10    -1.893038mA       -1.673728mA          -2.145840mA
-  0.20    -3.512428mA       -3.164516mA          -3.900829mA
-  0.30    -4.854717mA       -4.471005mA          -5.257719mA
-  0.40    -5.916606mA       -5.591894mA          -6.209108mA
-  0.50    -6.694696mA       -6.525883mA          -6.765898mA
-  0.60    -7.186085mA       -7.271372mA          -7.127487mA
-  0.70    -7.501974mA       -7.827161mA          -7.398777mA
-  0.80    -7.747264mA       -8.192150mA          -7.614967mA
-  0.90    -7.946053mA       -8.442739mA          -7.794856mA
-  1.00    -8.112642mA       -8.647928mA          -7.949846mA
-  1.10    -8.255932mA       -8.820317mA          -8.086935mA
-  1.20    -8.381921mA       -8.968206mA          -8.210725mA
-  1.30    -8.494611mA       -9.097295mA          -8.324315mA
-  1.40    -8.596900mA       -9.211784mA          -8.430004mA
-  1.50    -8.691089mA       -9.314673mA          -8.529494mA
-  1.60    -8.778479mA       -9.407962mA          -8.623884mA
-  1.70    -8.860368mA       -9.493551mA          -8.714073mA
-  1.80    -8.937858mA       -9.572640mA          -8.800963mA
-  1.90    -9.011447mA       -9.646329mA          -8.884952mA
-  2.00    -9.081837mA       -9.715418mA          -8.966642mA
-  2.10    -9.149526mA       -9.780507mA          -9.046332mA
-  2.20    -9.214816mA       -9.842296mA          -9.124421mA
-  2.30    -9.278305mA       -9.901185mA          -9.201211mA
-  2.40    -9.340094mA       -9.957574mA          -9.277001mA
-  2.50    -9.400784mA       -10.011863mA         -9.352391mA
-  2.60    -9.460574mA       -10.063852mA         -9.427582mA
-  2.70    -9.519964mA       -10.115841mA         -9.503173mA
-  2.80    -9.579454mA       -10.165830mA         -9.579563mA
-  2.90    -9.639644mA       -10.215819mA         -9.657654mA
-  3.00    -9.701034mA       -10.264808mA         -9.737845mA
-  3.10    -9.764525mA       -10.315796mA         -9.821135mA
-  3.20    -9.830715mA       -10.367780mA         -9.908326mA
-  3.30    -9.900606mA       -10.421706mA         -10.000817mA
-  3.40    -9.975092mA       -10.478956mA         -10.098808mA
-  3.50    -10.055705mA      -10.535873mA         -10.202798mA
-  3.60    -10.141346mA      -10.578599mA         -10.316786mA
-  3.70    -10.228551mA      -10.620789mA         -10.438679mA
-  3.80    -10.281620mA      -10.662980mA         -10.570555mA
-  3.90    -10.322662mA      -10.705170mA         -10.682977mA
-  4.00    -10.363704mA      -10.747360mA         -10.725640mA
-  4.10    -10.404746mA      -10.789550mA         -10.768303mA
-  4.20    -10.445787mA      -10.831741mA         -10.810966mA
-  4.30    -10.486829mA      -10.873931mA         -10.853629mA
-  4.40    -10.527871mA      -10.916121mA         -10.896292mA
-  4.50    -10.568913mA      -10.958311mA         -10.938955mA
-  4.60    -10.609955mA      -11.000502mA         -10.981618mA
-  4.70    -10.650997mA      -11.042692mA         -11.024281mA
-  4.80    -10.692039mA      -11.084882mA         -11.066944mA
-  4.90    -10.733081mA      -11.127072mA         -11.109607mA
-  5.00    -10.774122mA      -11.169262mA         -11.152270mA
-  5.10    -10.815164mA      -11.211453mA         -11.194933mA
-  5.20    -10.856206mA      -11.253643mA         -11.237597mA
-  5.30    -10.897248mA      -11.295833mA         -11.280260mA
-  5.40    -10.938290mA      -11.338023mA         -11.322923mA
-  5.50    -10.979332mA      -11.380214mA         -11.365586mA
-  5.60    -11.020374mA      -11.422404mA         -11.408249mA
-  5.70    -11.061416mA      -11.464594mA         -11.450912mA
-  5.80    -11.102458mA      -11.506784mA         -11.493575mA
-  5.90    -11.143499mA      -11.548975mA         -11.536238mA
-  6.00    -11.184541mA      -11.591165mA         -11.578901mA
-  6.10    -11.225583mA      -11.633355mA         -11.621564mA
-  6.20    -11.266625mA      -11.675545mA         -11.664227mA
-  6.30    -11.307667mA      -11.717736mA         -11.706890mA
-  6.40    -11.348709mA      -11.759926mA         -11.749553mA
-  6.50    -11.389751mA      -11.802116mA         -11.792216mA
-  6.55    -11.410272mA      -11.823211mA         -11.813548mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.201000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.065000nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  0.287457/0.467122n  0.301305/0.700268n  0.291706/0.349090n
-dV/dt_f  0.309900/0.449885n  0.304680/0.837003n  0.308100/0.266290n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.782900V         2.609000V            2.960100V
-0.2020ns          2.783000V         2.608900V            2.962600V
-0.4040ns          2.788300V         2.610900V            3.086900V
-0.6061ns          3.016200V         2.611900V            3.417200V
-0.8081ns          3.244000V         2.678900V            3.463300V
-1.0101ns          3.291900V         2.961800V            3.467200V
-1.2121ns          3.295700V         3.102900V            3.468900V
-1.4141ns          3.297500V         3.120100V            3.469600V
-1.6162ns          3.298700V         3.136000V            3.469800V
-1.8182ns          3.299500V         3.136600V            3.469900V
-2.0202ns          3.299700V         3.137000V            3.469900V
-2.2222ns          3.299800V         3.138000V            3.469900V
-2.4242ns          3.299900V         3.138900V            3.469200V
-2.6263ns          3.299900V         3.139400V            3.471100V
-2.8283ns          3.299900V         3.139700V            3.470500V
-3.0303ns          3.299900V         3.139800V            3.470100V
-3.2323ns          3.299900V         3.139800V            3.470000V
-3.4343ns          3.300600V         3.139900V            3.470000V
-3.6364ns          3.301100V         3.139900V            3.470000V
-3.8384ns          3.300500V         3.139900V            3.470000V
-4.0404ns          3.300200V         3.139900V            3.470000V
-4.2424ns          3.300000V         3.139900V            3.470000V
-4.4444ns          3.300000V         3.139900V            3.470000V
-4.6465ns          3.300000V         3.139900V            3.470000V
-4.8485ns          3.300000V         3.140000V            3.469900V
-5.0505ns          3.300000V         3.140800V            3.469900V
-5.2525ns          3.300000V         3.141300V            3.469900V
-5.4545ns          3.299900V         3.140700V            3.469900V
-5.6566ns          3.299900V         3.140400V            3.469900V
-5.8586ns          3.299900V         3.140200V            3.469900V
-6.0606ns          3.299900V         3.140000V            3.469900V
-6.2626ns          3.299900V         3.140000V            3.469900V
-6.4646ns          3.299900V         3.140000V            3.469900V
-6.6667ns          3.299900V         3.140000V            3.469900V
-6.8687ns          3.299900V         3.140000V            3.469900V
-7.0707ns          3.299900V         3.139900V            3.469900V
-7.2727ns          3.299900V         3.139900V            3.470000V
-7.4747ns          3.299900V         3.139900V            3.470000V
-7.6768ns          3.299900V         3.139900V            3.470000V
-7.8788ns          3.299900V         3.139900V            3.470000V
-8.0808ns          3.299900V         3.139900V            3.470000V
-8.2828ns          3.299900V         3.139900V            3.470000V
-8.4848ns          3.299900V         3.139900V            3.470000V
-8.6869ns          3.299900V         3.139900V            3.470000V
-8.8889ns          3.299900V         3.139800V            3.470000V
-9.0909ns          3.299900V         3.139800V            3.470000V
-9.2929ns          3.299900V         3.139900V            3.470000V
-9.4949ns          3.299900V         3.139900V            3.470000V
-9.6970ns          3.299900V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.139900V            3.470000V
-11.7172ns         3.300000V         3.139900V            3.470000V
-11.9192ns         3.300000V         3.139900V            3.470000V
-12.1212ns         3.300000V         3.139900V            3.470000V
-12.3232ns         3.300000V         3.139900V            3.470000V
-12.5253ns         3.300000V         3.139900V            3.470000V
-12.7273ns         3.300000V         3.139900V            3.470000V
-12.9293ns         3.300000V         3.139900V            3.470000V
-13.1313ns         3.300000V         3.139900V            3.470000V
-13.3333ns         3.300000V         3.139900V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              4.225900uV        4.920300uV           3.956100uV
-0.2020ns          -0.116230mV       2.501000uV           -0.231630mV
-0.4040ns          -1.733400mV       5.664000uV           -6.571900mV
-0.6061ns          1.816900mV        -0.405040mV          0.151930V
-0.8081ns          0.105890V         -6.434700mV          0.334290V
-1.0101ns          0.246820V         13.033000mV          0.470790V
-1.2121ns          0.360950V         89.173000mV          0.542490V
-1.4141ns          0.454430V         0.176030V            0.572640V
-1.6162ns          0.508590V         0.271450V            0.582550V
-1.8182ns          0.534420V         0.353570V            0.588040V
-2.0202ns          0.543170V         0.429910V            0.588930V
-2.2222ns          0.549780V         0.484400V            0.588840V
-2.4242ns          0.550820V         0.517300V            0.590870V
-2.6263ns          0.551300V         0.536250V            0.553540V
-2.8283ns          0.551520V         0.543010V            0.497470V
-3.0303ns          0.551620V         0.548720V            0.468060V
-3.2323ns          0.551660V         0.549820V            0.453000V
-3.4343ns          0.558640V         0.550520V            0.446500V
-3.6364ns          0.508640V         0.550950V            0.442330V
-3.8384ns          0.463860V         0.551240V            0.440380V
-4.0404ns          0.438900V         0.551370V            0.438930V
-4.2424ns          0.425590V         0.551450V            0.438730V
-4.4444ns          0.417880V         0.551520V            0.438850V
-4.6465ns          0.413990V         0.551560V            0.439830V
-4.8485ns          0.411950V         0.551690V            0.441070V
-5.0505ns          0.411060V         0.558950V            0.443300V
-5.2525ns          0.410360V         0.519020V            0.446000V
-5.4545ns          0.410640V         0.480460V            0.448850V
-5.6566ns          0.411100V         0.455460V            0.451660V
-5.8586ns          0.412570V         0.440580V            0.454380V
-6.0606ns          0.414210V         0.430510V            0.456880V
-6.2626ns          0.416980V         0.426080V            0.459280V
-6.4646ns          0.420210V         0.423650V            0.461440V
-6.6667ns          0.423660V         0.422350V            0.463510V
-6.8687ns          0.426990V         0.421790V            0.465350V
-7.0707ns          0.430100V         0.421350V            0.467110V
-7.2727ns          0.433090V         0.421520V            0.468670V
-7.4747ns          0.435900V         0.421800V            0.470160V
-7.6768ns          0.438640V         0.422560V            0.471470V
-7.8788ns          0.441270V         0.423400V            0.472730V
-8.0808ns          0.443800V         0.425080V            0.473840V
-8.2828ns          0.446130V         0.426920V            0.474900V
-8.4848ns          0.448370V         0.429830V            0.475830V
-8.6869ns          0.450420V         0.433230V            0.476730V
-8.8889ns          0.452380V         0.436930V            0.477510V
-9.0909ns          0.454180V         0.440610V            0.478270V
-9.2929ns          0.455900V         0.444280V            0.478930V
-9.4949ns          0.457470V         0.447610V            0.479560V
-9.6970ns          0.458970V         0.450880V            0.480120V
-9.8990ns          0.460340V         0.453950V            0.480650V
-10.1010ns         0.462260V         0.458380V            0.481335V
-10.3030ns         0.464000V         0.462500V            0.481950V
-10.5051ns         0.465050V         0.464970V            0.482320V
-10.7071ns         0.466050V         0.467390V            0.482650V
-10.9091ns         0.466960V         0.469580V            0.482960V
-11.1111ns         0.467830V         0.471720V            0.483240V
-11.3131ns         0.468630V         0.473660V            0.483500V
-11.5152ns         0.469380V         0.475550V            0.483730V
-11.7172ns         0.470080V         0.477260V            0.483950V
-11.9192ns         0.470740V         0.478940V            0.484140V
-12.1212ns         0.471340V         0.480450V            0.484330V
-12.3232ns         0.471910V         0.481930V            0.484490V
-12.5253ns         0.472440V         0.483270V            0.484640V
-12.7273ns         0.472930V         0.484580V            0.484780V
-12.9293ns         0.473390V         0.485750V            0.484900V
-13.1313ns         0.473820V         0.486910V            0.485020V
-13.3333ns         0.474220V         0.487950V            0.485120V
-13.5354ns         0.474590V         0.488970V            0.485220V
-13.7374ns         0.474940V         0.489880V            0.485310V
-13.9394ns         0.475260V         0.490780V            0.485390V
-14.1414ns         0.475560V         0.491590V            0.485460V
-14.3434ns         0.475840V         0.492380V            0.485530V
-14.5455ns         0.476100V         0.493090V            0.485590V
-14.7475ns         0.476340V         0.493790V            0.485640V
-14.9495ns         0.476570V         0.494420V            0.485700V
-15.1515ns         0.476780V         0.495030V            0.485740V
-15.3535ns         0.476970V         0.495580V            0.485790V
-15.5556ns         0.477160V         0.496120V            0.485820V
-15.7576ns         0.477330V         0.496610V            0.485860V
-15.9596ns         0.477490V         0.497090V            0.485890V
-16.1616ns         0.477630V         0.497510V            0.485920V
-16.3636ns         0.477770V         0.497930V            0.485950V
-16.5657ns         0.477890V         0.498290V            0.485980V
-16.7677ns         0.478010V         0.498640V            0.486000V
-16.9697ns         0.478120V         0.498990V            0.486020V
-17.1717ns         0.478230V         0.499340V            0.486040V
-17.3737ns         0.478320V         0.499630V            0.486060V
-17.5758ns         0.478410V         0.499920V            0.486070V
-17.7778ns         0.478490V         0.500160V            0.486090V
-17.9798ns         0.478570V         0.500400V            0.486100V
-18.1818ns         0.478640V         0.500630V            0.486110V
-18.3838ns         0.478710V         0.500870V            0.486120V
-18.5859ns         0.478770V         0.501070V            0.486130V
-18.7879ns         0.478830V         0.501260V            0.486140V
-18.9899ns         0.478880V         0.501430V            0.486150V
-19.1919ns         0.478930V         0.501590V            0.486160V
-19.3939ns         0.478980V         0.501750V            0.486170V
-19.5960ns         0.479020V         0.501910V            0.486170V
-19.7980ns         0.479060V         0.502040V            0.486180V
-20.0000ns         0.479100V         0.502180V            0.486180V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              0.479590V         0.504150V            0.486240V
-0.2020ns          0.479620V         0.504110V            0.490470V
-0.4040ns          0.474660V         0.515850V            0.338690V
-0.6061ns          0.260970V         0.518810V            49.227000mV
-0.8081ns          57.693000mV       0.442430V            5.358900mV
-1.0101ns          10.006000mV       0.270560V            1.610600mV
-1.2121ns          3.219300mV        0.116620V            0.420340mV
-1.4141ns          1.539600mV        28.455000mV          0.168590mV
-1.6162ns          0.544500mV        9.235500mV           63.243000uV
-1.8182ns          0.242750mV        4.555900mV           28.107000uV
-2.0202ns          0.152510mV        2.530000mV           3.232400uV
-2.2222ns          71.354000uV       1.674500mV           0.754660uV
-2.4242ns          30.528000uV       0.925740mV           -0.544570mV
-2.6263ns          17.219000uV       0.496800mV           -0.223670mV
-2.8283ns          7.642900uV        0.286310mV           -18.013000uV
-3.0303ns          2.754100uV        0.206810mV           -16.664000uV
-3.2323ns          3.719000uV        0.129010mV           -14.948000uV
-3.4343ns          -0.126320mV       73.076000uV          -9.356000uV
-3.6364ns          -0.242850mV       44.601000uV          -11.098000uV
-3.8384ns          -32.574000uV      27.309000uV          -9.946200uV
-4.0404ns          3.566200uV        14.959000uV          -9.483100uV
-4.2424ns          -5.306100uV       8.251900uV           -8.932600uV
-4.4444ns          -13.750000uV      4.915800uV           -8.381600uV
-4.6465ns          10.940000uV       2.652800uV           -7.820100uV
-4.8485ns          18.035000uV       -0.108180mV          -7.265300uV
-5.0505ns          2.807200uV        0.153640mV           -6.819000uV
-5.2525ns          2.502100uV        -0.230170mV          -6.373400uV
-5.4545ns          3.131600uV        -97.756000uV         -5.936700uV
-5.6566ns          2.983900uV        -12.193000uV         -5.505100uV
-5.8586ns          2.947300uV        25.147000uV          -5.155800uV
-6.0606ns          3.185500uV        13.918000uV          -4.806500uV
-6.2626ns          3.361600uV        13.732000uV          -4.457800uV
-6.4646ns          3.383800uV        15.275000uV          -4.112200uV
-6.6667ns          3.430500uV        14.174000uV          -3.816000uV
-6.8687ns          3.538200uV        13.495000uV          -3.520100uV
-7.0707ns          3.619900uV        13.582000uV          -3.230000uV
-7.2727ns          3.637500uV        13.501000uV          -2.942000uV
-7.4747ns          3.665100uV        13.116000uV          -2.688300uV
-7.6768ns          3.717300uV        12.820000uV          -2.435300uV
-7.8788ns          3.759700uV        12.684000uV          -2.191800uV
-8.0808ns          3.777800uV        12.528000uV          -1.949700uV
-8.2828ns          3.800700uV        12.338000uV          -1.731900uV
-8.4848ns          3.835100uV        12.144000uV          -1.514700uV
-8.6869ns          3.864700uV        11.942000uV          -1.308300uV
-8.8889ns          3.882800uV        11.757000uV          -1.103000uV
-9.0909ns          3.903100uV        11.601000uV          -0.916190uV
-9.2929ns          3.928900uV        11.419000uV          -0.730020uV
-9.4949ns          3.951900uV        11.189000uV          -0.554530uV
-9.6970ns          3.968200uV        10.989000uV          -0.379920uV
-9.8990ns          3.985700uV        10.842000uV          -0.219880uV
-10.1010ns         4.015950uV        10.553500uV          12.615000nV
-10.3030ns         4.039500uV        10.248000uV          0.231740uV
-10.5051ns         4.054400uV        10.116000uV          0.368100uV
-10.7071ns         4.071500uV        9.956800uV           0.504010uV
-10.9091ns         4.087100uV        9.748000uV           0.632480uV
-11.1111ns         4.098800uV        9.573200uV           0.760290uV
-11.3131ns         4.111100uV        9.460300uV           0.877400uV
-11.5152ns         4.125100uV        9.320800uV           0.994070uV
-11.7172ns         4.137800uV        9.133200uV           1.103600uV
-11.9192ns         4.147200uV        8.978700uV           1.212600uV
-12.1212ns         4.157100uV        8.884300uV           1.313000uV
-12.3232ns         4.168500uV        8.764100uV           1.413100uV
-12.5253ns         4.178700uV        8.597200uV           1.506700uV
-12.7273ns         4.186000uV        8.456400uV           1.599900uV
-12.9293ns         4.193900uV        8.362900uV           1.686000uV
-13.1313ns         4.203100uV        8.269500uV           1.771700uV
-13.3333ns         4.211200uV        8.176000uV           1.851800uV
-13.5354ns         4.216800uV        8.065600uV           1.931600uV
-13.7374ns         4.222900uV        7.924500uV           2.005300uV
-13.9394ns         4.230300uV        7.808100uV           2.078800uV
-14.1414ns         4.236700uV        7.736300uV           2.147500uV
-14.3434ns         4.240800uV        7.664500uV           2.215800uV
-14.5455ns         4.245400uV        7.592700uV           2.279000uV
-14.7475ns         4.251200uV        7.503700uV           2.342000uV
-14.9495ns         4.256200uV        7.383500uV           2.400800uV
-15.1515ns         4.259000uV        7.286500uV           2.459400uV
-15.3535ns         4.262400uV        7.231700uV           2.513600uV
-15.5556ns         4.267000uV        7.176900uV           2.567700uV
-15.7576ns         4.270800uV        7.122100uV           2.618100uV
-15.9596ns         4.272600uV        7.049900uV           2.668300uV
-16.1616ns         4.274900uV        6.946400uV           2.714800uV
-16.3636ns         4.278400uV        6.865000uV           2.761200uV
-16.5657ns         4.281200uV        6.823600uV           2.804400uV
-16.7677ns         4.282300uV        6.782200uV           2.847500uV
-16.9697ns         4.283800uV        6.740700uV           2.887400uV
-17.1717ns         4.286400uV        6.682100uV           2.927100uV
-17.3737ns         4.288400uV        6.592100uV           2.964200uV
-17.5758ns         4.288700uV        6.523200uV           3.001200uV
-17.7778ns         4.289500uV        6.492500uV           3.035400uV
-17.9798ns         4.291500uV        6.461700uV           3.069500uV
-18.1818ns         4.292800uV        6.430900uV           3.101400uV
-18.3838ns         4.292600uV        6.383000uV           3.133100uV
-18.5859ns         4.292900uV        6.304200uV           3.162500uV
-18.7879ns         4.294300uV        6.245400uV           3.191700uV
-18.9899ns         4.295100uV        6.223200uV           3.219100uV
-19.1919ns         4.294400uV        6.200900uV           3.246200uV
-19.3939ns         4.294300uV        6.178600uV           3.270600uV
-19.5960ns         4.295200uV        6.139500uV           3.294900uV
-19.7980ns         4.295400uV        6.069700uV           3.319200uV
-20.0000ns         4.294000uV        6.076600uV           3.343600uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468600V
-0.4040ns          3.300900V         3.139100V            3.483300V
-0.6061ns          3.304400V         3.140100V            3.272000V
-0.8081ns          3.179500V         3.145900V            3.030300V
-1.0101ns          3.015400V         3.136300V            2.907000V
-1.2121ns          2.895000V         3.095000V            2.856700V
-1.4141ns          2.821600V         2.995500V            2.837500V
-1.6162ns          2.781500V         2.910100V            2.829200V
-1.8182ns          2.760300V         2.834600V            2.826700V
-2.0202ns          2.751400V         2.769700V            2.825700V
-2.2222ns          2.745500V         2.722000V            2.826100V
-2.4242ns          2.743500V         2.688600V            2.830900V
-2.6263ns          2.743000V         2.667400V            2.878100V
-2.8283ns          2.742800V         2.654200V            2.895900V
-3.0303ns          2.742900V         2.645000V            2.900000V
-3.2323ns          2.743200V         2.639400V            2.902500V
-3.4343ns          2.756300V         2.636600V            2.904500V
-3.6364ns          2.776700V         2.635200V            2.906500V
-3.8384ns          2.790100V         2.634000V            2.908200V
-4.0404ns          2.792600V         2.633800V            2.909800V
-4.2424ns          2.793100V         2.633700V            2.911300V
-4.4444ns          2.793600V         2.633900V            2.912900V
-4.6465ns          2.793500V         2.634100V            2.914200V
-4.8485ns          2.793500V         2.636300V            2.915600V
-5.0505ns          2.793500V         2.635700V            2.916900V
-5.2525ns          2.793500V         2.642300V            2.918100V
-5.4545ns          2.793500V         2.652700V            2.919300V
-5.6566ns          2.793400V         2.656300V            2.920400V
-5.8586ns          2.793400V         2.655900V            2.921400V
-6.0606ns          2.793300V         2.655100V            2.922500V
-6.2626ns          2.793200V         2.654600V            2.923500V
-6.4646ns          2.793100V         2.654000V            2.924400V
-6.6667ns          2.793000V         2.653400V            2.925300V
-6.8687ns          2.792900V         2.652800V            2.926200V
-7.0707ns          2.792800V         2.652200V            2.927100V
-7.2727ns          2.792700V         2.651700V            2.928000V
-7.4747ns          2.792600V         2.651100V            2.928900V
-7.6768ns          2.792500V         2.650500V            2.929700V
-7.8788ns          2.792300V         2.650000V            2.930600V
-8.0808ns          2.792200V         2.649500V            2.931500V
-8.2828ns          2.792100V         2.648900V            2.932300V
-8.4848ns          2.791900V         2.648400V            2.933200V
-8.6869ns          2.791800V         2.647900V            2.934100V
-8.8889ns          2.791600V         2.647400V            2.935000V
-9.0909ns          2.791500V         2.647000V            2.935800V
-9.2929ns          2.791300V         2.646500V            2.936600V
-9.4949ns          2.791200V         2.646000V            2.937400V
-9.6970ns          2.791000V         2.645600V            2.938200V
-9.8990ns          2.790900V         2.645100V            2.939000V
-10.1010ns         2.790650V         2.644500V            2.940050V
-10.3030ns         2.790400V         2.643900V            2.941100V
-10.5051ns         2.790200V         2.643500V            2.941700V
-10.7071ns         2.790100V         2.643100V            2.942400V
-10.9091ns         2.789900V         2.642700V            2.943000V
-11.1111ns         2.789700V         2.642400V            2.943600V
-11.3131ns         2.789600V         2.642000V            2.944100V
-11.5152ns         2.789400V         2.641600V            2.944700V
-11.7172ns         2.789200V         2.641300V            2.945200V
-11.9192ns         2.789100V         2.641000V            2.945700V
-12.1212ns         2.788900V         2.640600V            2.946200V
-12.3232ns         2.788700V         2.640300V            2.946700V
-12.5253ns         2.788600V         2.640000V            2.947100V
-12.7273ns         2.788400V         2.639700V            2.947600V
-12.9293ns         2.788200V         2.639400V            2.948000V
-13.1313ns         2.788000V         2.639100V            2.948400V
-13.3333ns         2.787900V         2.638900V            2.948800V
-13.5354ns         2.787700V         2.638600V            2.949200V
-13.7374ns         2.787500V         2.638300V            2.949600V
-13.9394ns         2.787400V         2.638000V            2.949900V
-14.1414ns         2.787200V         2.637800V            2.950300V
-14.3434ns         2.787000V         2.637500V            2.950600V
-14.5455ns         2.786900V         2.637300V            2.950900V
-14.7475ns         2.786700V         2.637100V            2.951200V
-14.9495ns         2.786500V         2.636800V            2.951500V
-15.1515ns         2.786400V         2.636600V            2.951800V
-15.3535ns         2.786200V         2.636400V            2.952100V
-15.5556ns         2.786100V         2.636100V            2.952400V
-15.7576ns         2.785900V         2.635900V            2.952600V
-15.9596ns         2.785800V         2.635700V            2.952900V
-16.1616ns         2.785600V         2.635500V            2.953100V
-16.3636ns         2.785500V         2.635300V            2.953400V
-16.5657ns         2.785300V         2.635100V            2.953600V
-16.7677ns         2.785200V         2.634900V            2.953800V
-16.9697ns         2.785000V         2.634700V            2.954000V
-17.1717ns         2.784900V         2.634500V            2.954200V
-17.3737ns         2.784800V         2.634300V            2.954400V
-17.5758ns         2.784600V         2.634200V            2.954600V
-17.7778ns         2.784500V         2.634000V            2.954800V
-17.9798ns         2.784400V         2.633800V            2.955000V
-18.1818ns         2.784300V         2.633600V            2.955100V
-18.3838ns         2.784200V         2.633500V            2.955300V
-18.5859ns         2.784100V         2.633300V            2.955500V
-18.7879ns         2.784000V         2.633100V            2.955600V
-18.9899ns         2.783900V         2.633000V            2.955800V
-19.1919ns         2.783800V         2.632800V            2.955900V
-19.3939ns         2.783700V         2.632700V            2.956100V
-19.5960ns         2.783600V         2.632500V            2.956200V
-19.7980ns         2.783600V         2.632400V            2.956300V
-20.0000ns         2.783500V         2.632200V            2.956500V
-|  
-| End [Model] lvc330s040aaaaaaaaio
-|************************************************************************
-[Model]           lvc330s140aaaaaaaaio
-Model_type        I/O
-Polarity          Non-Inverting
-Enable            Active-Low
-Vinl =            0.800000V
-Vinh =            2.000000V
-Vmeas =           1.650000V
-Cref =            0.0F
-Rref =            1.000000M
-Vref =            0.0V
-C_comp            2.68pF          2.54pF             2.92pF
-|  
-|  
-[Temperature Range]     25.000000         0.105000k            -40.000000
-[Voltage Range]         3.300000V         3.140000V            3.470000V
-[Pulldown] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -50.584550mA      -43.999960mA         -54.623576mA
-  -3.20    -50.404450mA      -43.837800mA         -54.427552mA
-  -3.10    -50.224350mA      -43.675640mA         -54.231528mA
-  -3.00    -50.044250mA      -43.513480mA         -54.035504mA
-  -2.90    -49.864150mA      -43.351320mA         -53.839480mA
-  -2.80    -49.684050mA      -43.189160mA         -53.643456mA
-  -2.70    -49.503950mA      -43.027000mA         -53.447432mA
-  -2.60    -49.323850mA      -42.864840mA         -53.251408mA
-  -2.50    -49.143750mA      -42.702680mA         -53.055384mA
-  -2.40    -48.963650mA      -42.540520mA         -52.859360mA
-  -2.30    -48.783550mA      -42.378360mA         -52.663336mA
-  -2.20    -48.603450mA      -42.216200mA         -52.467312mA
-  -2.10    -48.423350mA      -42.054040mA         -52.271288mA
-  -2.00    -48.243250mA      -41.891880mA         -52.075264mA
-  -1.90    -48.063150mA      -41.729720mA         -51.879240mA
-  -1.80    -47.883050mA      -41.567560mA         -51.683216mA
-  -1.70    -47.702950mA      -41.405400mA         -51.487192mA
-  -1.60    -47.522850mA      -41.243240mA         -51.291168mA
-  -1.50    -47.342750mA      -41.081080mA         -51.095144mA
-  -1.40    -47.162650mA      -40.960000mA         -50.899120mA
-  -1.30    -46.982550mA      -40.310000mA         -50.703096mA
-  -1.20    -46.802450mA      -39.409000mA         -50.507072mA
-  -1.10    -46.622350mA      -38.410000mA         -50.311048mA
-  -1.00    -46.442250mA      -37.323000mA         -50.115024mA
-  -0.90    -46.262150mA      -36.180000mA         -49.919000mA
-  -0.80    -46.082050mA      -35.076000mA         -49.327000mA
-  -0.70    -45.748900mA      -34.427000mA         -47.994000mA
-  -0.60    -42.249200mA      -34.203200mA         -45.776900mA
-  -0.50    -36.169470mA      -30.752860mA         -40.603750mA
-  -0.40    -29.014551mA      -24.879886mA         -32.919898mA
-  -0.30    -21.670346mA      -18.677585mA         -24.687602mA
-  -0.20    -14.338705mA      -12.435585mA         -16.367748mA
-  -0.10    -7.093292mA       -6.195266mA          -8.095791mA
-  0.00    27.190000nA       25.680000nA          31.680000nA
-  0.10    6.587285mA        5.878497mA           7.387890mA
-  0.20    12.314175mA       11.156186mA          13.529180mA
-  0.30    17.106166mA       15.766175mA          18.285171mA
-  0.40    20.907156mA       19.661164mA          21.673162mA
-  0.50    23.747146mA       22.813153mA          23.968152mA
-  0.60    25.783136mA       25.234142mA          25.549143mA
-  0.70    27.212126mA       27.008131mA          26.699134mA
-  0.80    28.206116mA       28.280120mA          27.588124mA
-  0.90    28.917106mA       29.203109mA          28.308115mA
-  1.00    29.453095mA       29.892098mA          28.908106mA
-  1.10    29.875084mA       30.426087mA          29.398096mA
-  1.20    30.221074mA       30.854076mA          29.770086mA
-  1.30    30.513063mA       31.208065mA          30.064075mA
-  1.40    30.767053mA       31.507054mA          30.315065mA
-  1.50    30.993042mA       31.766043mA          30.542055mA
-  1.60    31.203032mA       31.995032mA          30.762044mA
-  1.70    31.414021mA       32.204021mA          30.983034mA
-  1.80    31.648011mA       32.407010mA          31.201024mA
-  1.90    31.903000mA       32.633999mA          31.408013mA
-  2.00    32.157989mA       32.912988mA          31.601003mA
-  2.10    32.398979mA       33.235977mA          31.780993mA
-  2.20    32.620968mA       33.562966mA          31.951982mA
-  2.30    32.826958mA       33.870954mA          32.113972mA
-  2.40    33.017947mA       34.153943mA          32.268961mA
-  2.50    33.197936mA       34.411932mA          32.419951mA
-  2.60    33.368926mA       34.647921mA          32.567941mA
-  2.70    33.532915mA       34.866910mA          32.714930mA
-  2.80    33.693904mA       35.070899mA          32.864920mA
-  2.90    33.851894mA       35.264888mA          33.017909mA
-  3.00    34.012883mA       35.450877mA          33.177899mA
-  3.10    34.176872mA       35.632864mA          33.347889mA
-  3.20    34.349862mA       35.813747mA          33.531878mA
-  3.30    34.531848mA       35.996379mA          33.730868mA
-  3.40    34.729725mA       36.157497mA          33.951857mA
-  3.50    34.942986mA       36.297102mA          34.196843mA
-  3.60    35.117958mA       36.436708mA          34.470599mA
-  3.70    35.251602mA       36.576313mA          34.772212mA
-  3.80    35.385246mA       36.715919mA          34.904053mA
-  3.90    35.518890mA       36.855525mA          35.035893mA
-  4.00    35.652534mA       36.995130mA          35.167734mA
-  4.10    35.786178mA       37.134736mA          35.299574mA
-  4.20    35.919822mA       37.274341mA          35.431414mA
-  4.30    36.053466mA       37.413947mA          35.563255mA
-  4.40    36.187110mA       37.553553mA          35.695095mA
-  4.50    36.320754mA       37.693158mA          35.826936mA
-  4.60    36.454398mA       37.832764mA          35.958776mA
-  4.70    36.588042mA       37.972369mA          36.090616mA
-  4.80    36.721686mA       38.111975mA          36.222457mA
-  4.90    36.855330mA       38.251581mA          36.354297mA
-  5.00    36.988974mA       38.391186mA          36.486138mA
-  5.10    37.122618mA       38.530792mA          36.617978mA
-  5.20    37.256262mA       38.670397mA          36.749818mA
-  5.30    37.389906mA       38.810003mA          36.881659mA
-  5.40    37.523550mA       38.949609mA          37.013499mA
-  5.50    37.657194mA       39.089214mA          37.145340mA
-  5.60    37.790838mA       39.228820mA          37.277180mA
-  5.70    37.924482mA       39.368425mA          37.409020mA
-  5.80    38.058126mA       39.508031mA          37.540861mA
-  5.90    38.191770mA       39.647637mA          37.672701mA
-  6.00    38.325414mA       39.787242mA          37.804542mA
-  6.10    38.459058mA       39.926848mA          37.936382mA
-  6.20    38.592702mA       40.066453mA          38.068222mA
-  6.30    38.726346mA       40.206059mA          38.200063mA
-  6.40    38.859990mA       40.345665mA          38.331903mA
-  6.50    38.993634mA       40.485270mA          38.463744mA
-  6.60    39.127278mA       40.624876mA          38.595584mA
-|  
-[Pullup] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    66.669757mA       87.094613mA          92.797733mA
-  -3.20    66.440741mA       86.767866mA          92.515330mA
-  -3.10    66.211726mA       86.441119mA          92.232928mA
-  -3.00    65.982711mA       86.114372mA          91.950525mA
-  -2.90    65.753695mA       85.787625mA          91.668122mA
-  -2.80    65.524680mA       85.460878mA          91.385720mA
-  -2.70    65.295664mA       85.134131mA          91.103317mA
-  -2.60    65.066649mA       84.807384mA          90.820915mA
-  -2.50    64.837633mA       84.480636mA          90.538512mA
-  -2.40    64.608618mA       84.153889mA          90.256109mA
-  -2.30    64.379602mA       83.827142mA          89.973707mA
-  -2.20    64.150587mA       83.500395mA          89.691304mA
-  -2.10    63.921571mA       83.173648mA          89.408901mA
-  -2.00    63.692556mA       82.846901mA          89.126499mA
-  -1.90    63.463540mA       82.520154mA          88.844096mA
-  -1.80    63.234525mA       82.323794mA          88.561693mA
-  -1.70    63.005509mA       81.008819mA          88.279291mA
-  -1.60    62.776494mA       78.640845mA          87.996888mA
-  -1.50    62.547479mA       75.568869mA          87.714485mA
-  -1.40    62.318463mA       71.978893mA          87.432083mA
-  -1.30    62.089448mA       67.983917mA          87.149680mA
-  -1.20    61.860432mA       63.658940mA          86.867278mA
-  -1.10    61.631417mA       59.058962mA          86.584875mA
-  -1.00    61.402401mA       54.225984mA          80.067686mA
-  -0.90    61.173386mA       49.192006mA          71.275712mA
-  -0.80    54.621889mA       45.212027mA          61.996736mA
-  -0.70    47.050911mA       41.794048mA          52.900760mA
-  -0.60    39.442932mA       35.550069mA          44.185783mA
-  -0.50    32.215954mA       29.164089mA          36.006805mA
-  -0.40    25.419974mA       23.007107mA          28.393828mA
-  -0.30    17.101700mA       15.824500mA          19.002300mA
-  -0.20    12.464986mA       11.277815mA          13.918820mA
-  -0.10    6.164125mA        5.580948mA           6.877969mA
-  0.00    -18.490000nA      -17.070000nA         -20.440000nA
-  0.10    -5.904938mA       -5.394928mA          -6.530140mA
-  0.20    -11.454128mA      -10.553116mA         -12.558129mA
-  0.30    -16.640117mA      -15.473105mA         -18.069119mA
-  0.40    -21.457106mA      -20.150094mA         -23.046108mA
-  0.50    -25.896096mA      -24.583083mA         -27.475098mA
-  0.60    -29.949085mA      -28.768072mA         -31.336087mA
-  0.70    -33.609074mA      -32.702061mA         -34.612077mA
-  0.80    -36.868064mA      -36.383050mA         -37.284067mA
-  0.90    -39.717053mA      -39.806039mA         -39.346056mA
-  1.00    -42.147042mA      -42.970028mA         -40.889046mA
-  1.10    -44.149032mA      -45.870017mA         -42.089035mA
-  1.20    -45.748021mA      -48.504006mA         -43.060025mA
-  1.30    -47.028011mA      -50.866995mA         -43.869015mA
-  1.40    -48.080000mA      -52.957984mA         -44.561004mA
-  1.50    -48.964989mA      -54.770973mA         -45.164994mA
-  1.60    -49.722979mA      -56.304962mA         -45.700984mA
-  1.70    -50.383968mA      -57.595951mA         -46.184973mA
-  1.80    -50.967958mA      -58.692940mA         -46.625963mA
-  1.90    -51.489947mA      -59.638929mA         -47.033952mA
-  2.00    -51.962937mA      -60.463918mA         -47.412942mA
-  2.10    -52.394926mA      -61.192907mA         -47.768932mA
-  2.20    -52.791916mA      -61.842896mA         -48.104921mA
-  2.30    -53.159905mA      -62.426885mA         -48.424911mA
-  2.40    -53.504894mA      -62.956874mA         -48.730901mA
-  2.50    -53.827884mA      -63.439863mA         -49.025891mA
-  2.60    -54.132874mA      -63.884852mA         -49.310882mA
-  2.70    -54.422864mA      -64.295841mA         -49.587873mA
-  2.80    -54.700854mA      -64.676830mA         -49.859863mA
-  2.90    -54.966844mA      -65.033819mA         -50.128854mA
-  3.00    -55.224834mA      -65.367808mA         -50.397845mA
-  3.10    -55.477825mA      -65.682796mA         -50.669835mA
-  3.20    -55.727815mA      -65.980780mA         -50.947826mA
-  3.30    -55.978806mA      -66.265706mA         -51.235817mA
-  3.40    -56.233792mA      -66.536956mA         -51.539808mA
-  3.50    -56.497705mA      -66.792873mA         -51.862798mA
-  3.60    -56.774346mA      -66.928560mA         -52.210786mA
-  3.70    -57.054551mA      -67.195337mA         -52.589679mA
-  3.80    -57.194470mA      -67.462113mA         -53.001555mA
-  3.90    -57.422477mA      -67.728890mA         -53.392977mA
-  4.00    -57.650484mA      -67.995667mA         -53.537857mA
-  4.10    -57.878491mA      -68.262444mA         -53.750052mA
-  4.20    -58.106498mA      -68.529220mA         -53.962246mA
-  4.30    -58.334506mA      -68.795997mA         -54.174441mA
-  4.40    -58.562513mA      -69.062774mA         -54.386636mA
-  4.50    -58.790520mA      -69.329550mA         -54.598830mA
-  4.60    -59.018527mA      -69.596327mA         -54.811025mA
-  4.70    -59.246534mA      -69.863104mA         -55.023219mA
-  4.80    -59.474541mA      -70.129881mA         -55.235414mA
-  4.90    -59.702548mA      -70.396657mA         -55.447608mA
-  5.00    -59.930555mA      -70.663434mA         -55.659803mA
-  5.10    -60.158563mA      -70.930211mA         -55.871997mA
-  5.20    -60.386570mA      -71.196988mA         -56.084192mA
-  5.30    -60.614577mA      -71.463764mA         -56.296387mA
-  5.40    -60.842584mA      -71.730541mA         -56.508581mA
-  5.50    -61.070591mA      -71.997318mA         -56.720776mA
-  5.60    -61.298598mA      -72.264094mA         -56.932970mA
-  5.70    -61.526605mA      -72.530871mA         -57.145165mA
-  5.80    -61.754612mA      -72.797648mA         -57.357359mA
-  5.90    -61.982620mA      -73.064425mA         -57.569554mA
-  6.00    -62.210627mA      -73.331201mA         -57.781748mA
-  6.10    -62.438634mA      -73.597978mA         -57.993943mA
-  6.20    -62.666641mA      -73.864755mA         -58.206138mA
-  6.30    -62.894648mA      -74.131531mA         -58.418332mA
-  6.40    -63.122655mA      -74.398308mA         -58.630527mA
-  6.50    -63.350662mA      -74.665085mA         -58.842721mA
-  6.55    -63.464666mA      -74.798473mA         -58.948819mA
-|  
-[GND_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    -0.966230A        -0.950520A           -0.981210A
-  -3.22    -0.926890A        -0.911380A           -0.941720A
-  -3.14    -0.887580A        -0.872280A           -0.902250A
-  -3.06    -0.848310A        -0.833240A           -0.862810A
-  -2.98    -0.809090A        -0.794250A           -0.823400A
-  -2.90    -0.769910A        -0.755320A           -0.784030A
-  -2.82    -0.730780A        -0.716470A           -0.744690A
-  -2.74    -0.691720A        -0.677700A           -0.705410A
-  -2.66    -0.652720A        -0.639020A           -0.666170A
-  -2.58    -0.613810A        -0.600460A           -0.627000A
-  -2.50    -0.574990A        -0.562020A           -0.587900A
-  -2.42    -0.536290A        -0.523740A           -0.548880A
-  -2.34    -0.497720A        -0.485650A           -0.509970A
-  -2.26    -0.459320A        -0.447780A           -0.471180A
-  -2.18    -0.421130A        -0.410210A           -0.432540A
-  -2.10    -0.383220A        -0.373010A           -0.394110A
-  -2.02    -0.345660A        -0.336310A           -0.355940A
-  -1.94    -0.308600A        -0.300310A           -0.318140A
-  -1.86    -0.272270A        -0.265320A           -0.280870A
-  -1.78    -0.237080A        -0.231900A           -0.244460A
-  -1.70    -0.203840A        -0.201040A           -0.209550A
-  -1.62    -0.174180A        -0.174390A           -0.177650A
-  -1.54    -0.150480A        -0.153310A           -0.151870A
-  -1.46    -0.132430A        -0.136590A           -0.133020A
-  -1.38    -0.116630A        -0.121710A           -0.116640A
-  -1.30    -0.101400A        -0.107420A           -0.100700A
-  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
-  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
-  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
-  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
-  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
-  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
-  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
-  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
-  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
-  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
-  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
-  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
-  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
-  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
-  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
-  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
-  0.06    -0.188630uA       -0.201350uA          -0.193360uA
-  0.14    -0.180980uA       -0.192340uA          -0.185900uA
-  0.22    -0.173340uA       -0.183540uA          -0.178450uA
-  0.30    -0.165690uA       -0.174750uA          -0.171010uA
-  0.38    -0.158000uA       -0.165960uA          -0.163570uA
-  0.46    -0.150270uA       -0.157150uA          -0.156120uA
-  0.54    -0.142440uA       -0.148340uA          -0.148680uA
-  0.62    -0.134460uA       -0.139540uA          -0.141240uA
-  0.70    -0.126310uA       -0.130730uA          -0.133790uA
-  0.78    -0.118040uA       -0.121920uA          -0.126340uA
-  0.86    -0.109700uA       -0.113110uA          -0.118880uA
-  0.94    -0.101320uA       -0.104310uA          -0.111370uA
-  1.02    -92.914000nA      -95.498000nA         -0.103710uA
-  1.10    -84.495000nA      -86.692000nA         -95.808000nA
-  1.18    -76.063000nA      -77.885000nA         -87.731000nA
-  1.26    -67.624000nA      -69.077000nA         -79.564000nA
-  1.34    -59.178000nA      -60.269000nA         -71.346000nA
-  1.42    -50.727000nA      -51.460000nA         -63.100000nA
-  1.50    -42.271000nA      -42.651000nA         -54.834000nA
-  1.58    -33.812000nA      -33.840000nA         -46.556000nA
-  1.66    -25.349000nA      -25.028000nA         -38.268000nA
-  1.74    -16.884000nA      -16.215000nA         -29.974000nA
-  1.82    -8.415500nA       -7.400800nA          -21.675000nA
-  1.90    55.195000pA       1.415400nA           -13.371000nA
-  1.98    8.528300nA        10.233000nA          -5.064900nA
-  2.06    17.004000nA       19.054000nA          3.244100nA
-  2.14    25.482000nA       27.876000nA          11.555000nA
-  2.22    33.962000nA       36.702000nA          19.868000nA
-  2.30    42.445000nA       45.532000nA          28.183000nA
-  2.38    50.931000nA       54.365000nA          36.499000nA
-  2.46    59.420000nA       63.204000nA          44.816000nA
-  2.54    67.912000nA       72.050000nA          53.135000nA
-  2.62    76.408000nA       80.904000nA          61.455000nA
-  2.70    84.908000nA       89.768000nA          69.776000nA
-  2.78    93.413000nA       98.647000nA          78.099000nA
-  2.86    0.101920uA        0.107550uA           86.423000nA
-  2.94    0.110440uA        0.116470uA           94.749000nA
-  3.02    0.118970uA        0.125470uA           0.103080uA
-  3.10    0.127510uA        0.135560uA           0.111410uA
-  3.18    0.136060uA        0.207650uA           0.119740uA
-  3.26    0.144710uA        0.665780uA           0.128080uA
-  3.30    0.152020uA        1.620700uA           0.132250uA
-|  
-[POWER_clamp] 
-|Voltage   I(typ)              I(min)              I(max)
-|  
-  -3.30    1.922000uA        1.691900uA           2.178700uA
-  -3.26    1.903700uA        1.676200uA           2.158100uA
-  -3.22    1.885700uA        1.660600uA           2.137700uA
-  -3.18    1.867800uA        1.645300uA           2.117600uA
-  -3.14    1.850200uA        1.630100uA           2.097600uA
-  -3.10    1.832700uA        1.615000uA           2.077900uA
-  -3.06    1.815500uA        1.600200uA           2.058300uA
-  -3.02    1.798400uA        1.585500uA           2.039000uA
-  -2.98    1.781600uA        1.570900uA           2.019900uA
-  -2.94    1.764900uA        1.556500uA           2.001000uA
-  -2.90    1.748500uA        1.542300uA           1.982300uA
-  -2.86    1.732200uA        1.528200uA           1.963900uA
-  -2.82    1.716100uA        1.514300uA           1.945600uA
-  -2.78    1.700200uA        1.500500uA           1.927500uA
-  -2.74    1.684500uA        1.486900uA           1.909700uA
-  -2.70    1.668900uA        1.473400uA           1.892000uA
-  -2.66    1.653600uA        1.460100uA           1.874600uA
-  -2.62    1.638400uA        1.446900uA           1.857300uA
-  -2.58    1.623400uA        1.433900uA           1.840300uA
-  -2.54    1.608600uA        1.421000uA           1.823400uA
-  -2.50    1.594000uA        1.408300uA           1.806800uA
-  -2.46    1.579600uA        1.395600uA           1.790400uA
-  -2.42    1.565300uA        1.383200uA           1.774100uA
-  -2.38    1.551200uA        1.370800uA           1.758100uA
-  -2.34    1.537200uA        1.358700uA           1.742200uA
-  -2.30    1.523500uA        1.346600uA           1.726600uA
-  -2.26    1.509900uA        1.334700uA           1.711100uA
-  -2.22    1.496500uA        1.322900uA           1.695800uA
-  -2.18    1.483200uA        1.311200uA           1.680700uA
-  -2.14    1.470100uA        1.299600uA           1.665900uA
-  -2.10    1.457200uA        1.288200uA           1.651200uA
-  -2.06    1.444400uA        1.276900uA           1.636600uA
-  -2.02    1.431800uA        1.265700uA           1.622300uA
-  -1.98    1.419300uA        1.254700uA           1.608200uA
-  -1.94    1.407000uA        1.243700uA           1.594200uA
-  -1.90    1.394800uA        1.232900uA           1.580400uA
-  -1.86    1.382800uA        1.222200uA           1.566800uA
-  -1.82    1.370900uA        1.211600uA           1.553400uA
-  -1.78    1.359200uA        1.201100uA           1.540100uA
-  -1.74    1.347600uA        1.190700uA           1.527000uA
-  -1.70    1.336200uA        1.180500uA           1.514100uA
-  -1.66    1.324900uA        1.170300uA           1.501400uA
-  -1.62    1.313700uA        1.160200uA           1.488800uA
-  -1.58    1.302700uA        1.150200uA           1.476400uA
-  -1.54    1.291800uA        1.140400uA           1.464100uA
-  -1.50    1.281000uA        1.130600uA           1.452000uA
-  -1.46    1.270400uA        1.120900uA           1.440100uA
-  -1.42    1.259800uA        1.111300uA           1.428300uA
-  -1.38    1.249400uA        1.101800uA           1.416700uA
-  -1.34    1.239200uA        1.092400uA           1.405200uA
-  -1.30    1.229000uA        1.083000uA           1.393900uA
-  -1.26    1.218900uA        1.073800uA           1.382700uA
-  -1.22    1.209000uA        1.064600uA           1.371700uA
-  -1.18    1.199200uA        1.055500uA           1.360800uA
-  -1.14    1.189500uA        1.046500uA           1.350100uA
-  -1.10    1.179800uA        1.037600uA           1.339400uA
-  -1.06    1.170300uA        1.028700uA           1.329000uA
-  -1.02    1.160900uA        1.019900uA           1.318600uA
-  -0.98    1.151600uA        1.011200uA           1.308400uA
-  -0.94    1.142400uA        1.002500uA           1.298300uA
-  -0.90    1.133300uA        0.993900uA           1.288300uA
-  -0.86    1.124200uA        0.985360uA           1.278400uA
-  -0.82    1.115300uA        0.976890uA           1.268700uA
-  -0.78    1.106400uA        0.968470uA           1.259000uA
-  -0.74    1.097600uA        0.960110uA           1.249500uA
-  -0.70    1.088900uA        0.951810uA           1.240100uA
-  -0.66    1.080300uA        0.943560uA           1.230800uA
-  -0.62    1.071700uA        0.935380uA           1.221600uA
-  -0.58    1.063200uA        0.927260uA           1.212500uA
-  -0.54    1.054800uA        0.919220uA           1.203400uA
-  -0.50    1.046400uA        0.911290uA           1.194500uA
-  -0.46    1.038100uA        0.903530uA           1.185600uA
-  -0.42    1.029800uA        0.896100uA           1.176600uA
-  -0.38    1.021500uA        0.889460uA           1.167600uA
-  -0.34    1.017292uA        0.887043uA           1.162691uA
-  -0.30    1.017269uA        0.887023uA           1.162665uA
-  -0.26    1.017176uA        0.886942uA           1.162558uA
-  -0.22    1.016803uA        0.886617uA           1.162132uA
-  -0.18    1.015313uA        0.885317uA           1.160429uA
-  -0.14    1.009352uA        0.880120uA           1.153616uA
-  -0.10    0.985509uA        0.859330uA           1.126366uA
-  -0.06    0.890137uA        0.776169uA           1.017362uA
-  -0.02    1.500000pA        1.200000pA           1.800000pA
-  0.00    0.0A              0.0A                 0.0A
-|  
-[Ramp]  
-| variable       typ                 min                 max 
-dV/dt_r  1.322279/1.397370n  1.285979/1.830494n  1.312139/1.075717n
-dV/dt_f  0.909660/0.907875n  0.826020/1.758264n  1.011840/0.527820n
-R_load = 50.000000
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              1.726300V         1.546200V            1.899700V
-0.2020ns          1.726800V         1.546200V            1.904800V
-0.4040ns          1.737400V         1.550000V            2.017500V
-0.6061ns          1.942100V         1.551600V            2.912500V
-0.8081ns          2.634400V         1.596800V            3.407200V
-1.0101ns          3.187200V         1.875300V            3.460800V
-1.2121ns          3.279100V         2.359700V            3.465800V
-1.4141ns          3.292700V         2.847800V            3.467100V
-1.6162ns          3.295600V         3.089900V            3.467600V
-1.8182ns          3.296700V         3.123600V            3.467900V
-2.0202ns          3.297300V         3.130900V            3.468200V
-2.2222ns          3.297500V         3.134300V            3.468700V
-2.4242ns          3.297700V         3.135700V            3.468900V
-2.6263ns          3.297900V         3.136600V            3.470800V
-2.8283ns          3.298100V         3.137000V            3.470300V
-3.0303ns          3.298400V         3.137300V            3.470100V
-3.2323ns          3.299000V         3.137500V            3.470000V
-3.4343ns          3.300800V         3.137600V            3.470000V
-3.6364ns          3.300800V         3.137800V            3.470000V
-3.8384ns          3.300300V         3.137900V            3.469900V
-4.0404ns          3.300200V         3.138000V            3.469900V
-4.2424ns          3.300000V         3.138200V            3.469900V
-4.4444ns          3.300000V         3.138400V            3.469900V
-4.6465ns          3.300000V         3.138600V            3.469900V
-4.8485ns          3.300000V         3.138900V            3.469900V
-5.0505ns          3.300000V         3.139200V            3.469900V
-5.2525ns          3.300000V         3.140400V            3.469900V
-5.4545ns          3.299900V         3.140300V            3.469900V
-5.6566ns          3.299900V         3.140100V            3.469900V
-5.8586ns          3.299900V         3.140100V            3.470000V
-6.0606ns          3.299900V         3.140000V            3.470000V
-6.2626ns          3.299900V         3.140000V            3.470000V
-6.4646ns          3.299900V         3.140000V            3.470000V
-6.6667ns          3.299900V         3.140000V            3.470000V
-6.8687ns          3.299900V         3.140000V            3.470000V
-7.0707ns          3.299900V         3.140000V            3.470000V
-7.2727ns          3.299900V         3.140000V            3.470000V
-7.4747ns          3.299900V         3.140000V            3.470000V
-7.6768ns          3.299900V         3.140000V            3.470000V
-7.8788ns          3.300000V         3.140000V            3.470000V
-8.0808ns          3.300000V         3.140000V            3.470000V
-8.2828ns          3.300000V         3.140000V            3.470000V
-8.4848ns          3.300000V         3.140000V            3.470000V
-8.6869ns          3.300000V         3.139900V            3.470000V
-8.8889ns          3.300000V         3.139900V            3.470000V
-9.0909ns          3.300000V         3.139900V            3.470000V
-9.2929ns          3.300000V         3.139900V            3.470000V
-9.4949ns          3.300000V         3.139900V            3.470000V
-9.6970ns          3.300000V         3.139900V            3.470000V
-9.8990ns          3.300000V         3.139900V            3.470000V
-10.1010ns         3.300000V         3.139900V            3.470000V
-10.3030ns         3.300000V         3.139900V            3.470000V
-10.5051ns         3.300000V         3.139900V            3.470000V
-10.7071ns         3.300000V         3.139900V            3.470000V
-10.9091ns         3.300000V         3.139900V            3.470000V
-11.1111ns         3.300000V         3.139900V            3.470000V
-11.3131ns         3.300000V         3.139900V            3.470000V
-11.5152ns         3.300000V         3.140000V            3.470000V
-11.7172ns         3.300000V         3.140000V            3.470000V
-11.9192ns         3.300000V         3.140000V            3.470000V
-12.1212ns         3.300000V         3.140000V            3.470000V
-12.3232ns         3.300000V         3.140000V            3.470000V
-12.5253ns         3.300000V         3.140000V            3.470000V
-12.7273ns         3.300000V         3.140000V            3.470000V
-12.9293ns         3.300000V         3.140000V            3.470000V
-13.1313ns         3.300000V         3.140000V            3.470000V
-13.3333ns         3.300000V         3.140000V            3.470000V
-13.5354ns         3.300000V         3.140000V            3.470000V
-13.7374ns         3.300000V         3.140000V            3.470000V
-13.9394ns         3.300000V         3.140000V            3.470000V
-14.1414ns         3.300000V         3.140000V            3.470000V
-14.3434ns         3.300000V         3.140000V            3.470000V
-14.5455ns         3.300000V         3.140000V            3.470000V
-14.7475ns         3.300000V         3.140000V            3.470000V
-14.9495ns         3.300000V         3.140000V            3.470000V
-15.1515ns         3.300000V         3.140000V            3.470000V
-15.3535ns         3.300000V         3.140000V            3.470000V
-15.5556ns         3.300000V         3.140000V            3.470000V
-15.7576ns         3.300000V         3.140000V            3.470000V
-15.9596ns         3.300000V         3.140000V            3.470000V
-16.1616ns         3.300000V         3.140000V            3.470000V
-16.3636ns         3.300000V         3.140000V            3.470000V
-16.5657ns         3.300000V         3.140000V            3.470000V
-16.7677ns         3.300000V         3.140000V            3.470000V
-16.9697ns         3.300000V         3.140000V            3.470000V
-17.1717ns         3.300000V         3.140000V            3.470000V
-17.3737ns         3.300000V         3.140000V            3.470000V
-17.5758ns         3.300000V         3.140000V            3.470000V
-17.7778ns         3.300000V         3.140000V            3.470000V
-17.9798ns         3.300000V         3.140000V            3.470000V
-18.1818ns         3.300000V         3.140000V            3.470000V
-18.3838ns         3.300000V         3.140000V            3.470000V
-18.5859ns         3.300000V         3.140000V            3.470000V
-18.7879ns         3.300000V         3.140000V            3.470000V
-18.9899ns         3.300000V         3.140000V            3.470000V
-19.1919ns         3.300000V         3.140000V            3.470000V
-19.3939ns         3.300000V         3.140000V            3.470000V
-19.5960ns         3.300000V         3.140000V            3.470000V
-19.7980ns         3.300000V         3.140000V            3.470000V
-20.0000ns         3.300000V         3.140000V            3.470000V
-|  
-[Rising Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              1.860000uV        2.247100uV           1.679700uV
-0.2020ns          -0.129790mV       4.669400uV           -0.320790mV
-0.4040ns          -1.716600mV       0.272540uV           -4.681500mV
-0.6061ns          1.221000mV        -0.447820mV          0.186680V
-0.8081ns          0.107030V         -5.196400mV          0.507800V
-1.0101ns          0.361420V         7.872900mV           0.782610V
-1.2121ns          0.574160V         63.086000mV          1.032400V
-1.4141ns          0.778920V         0.229510V            1.269500V
-1.6162ns          0.975680V         0.410340V            1.497800V
-1.8182ns          1.166800V         0.562960V            1.717900V
-2.0202ns          1.353800V         0.714380V            1.916400V
-2.2222ns          1.533600V         0.865340V            2.085800V
-2.4242ns          1.705400V         1.012700V            2.201900V
-2.6263ns          1.865600V         1.157800V            2.206500V
-2.8283ns          2.002800V         1.297100V            2.148000V
-3.0303ns          2.119800V         1.433900V            2.116300V
-3.2323ns          2.194200V         1.564200V            2.100900V
-3.4343ns          2.242600V         1.684200V            2.095200V
-3.6364ns          2.206600V         1.795900V            2.092100V
-3.8384ns          2.175600V         1.885300V            2.093400V
-4.0404ns          2.158100V         1.961700V            2.097900V
-4.2424ns          2.149800V         2.017100V            2.104000V
-4.4444ns          2.145000V         2.058100V            2.111400V
-4.6465ns          2.142500V         2.090000V            2.119600V
-4.8485ns          2.141700V         2.113000V            2.127800V
-5.0505ns          2.141900V         2.137500V            2.135200V
-5.2525ns          2.142800V         2.134100V            2.141000V
-5.4545ns          2.144700V         2.126700V            2.146000V
-5.6566ns          2.148900V         2.121500V            2.150700V
-5.8586ns          2.153600V         2.118100V            2.154700V
-6.0606ns          2.158200V         2.116400V            2.158400V
-6.2626ns          2.162900V         2.115100V            2.161600V
-6.4646ns          2.167200V         2.114600V            2.164500V
-6.6667ns          2.171000V         2.114400V            2.167000V
-6.8687ns          2.174500V         2.114500V            2.169300V
-7.0707ns          2.177500V         2.114600V            2.171300V
-7.2727ns          2.180300V         2.114800V            2.173100V
-7.4747ns          2.182800V         2.115200V            2.174700V
-7.6768ns          2.185100V         2.115600V            2.176100V
-7.8788ns          2.187100V         2.116000V            2.177400V
-8.0808ns          2.188900V         2.116500V            2.178500V
-8.2828ns          2.190500V         2.117100V            2.179500V
-8.4848ns          2.191900V         2.117700V            2.180300V
-8.6869ns          2.193200V         2.118500V            2.181100V
-8.8889ns          2.194300V         2.119600V            2.181800V
-9.0909ns          2.195300V         2.121000V            2.182400V
-9.2929ns          2.196300V         2.122600V            2.182900V
-9.4949ns          2.197100V         2.124200V            2.183400V
-9.6970ns          2.197800V         2.125900V            2.183800V
-9.8990ns          2.198500V         2.127400V            2.184200V
-10.1010ns         2.199350V         2.129450V            2.184650V
-10.3030ns         2.200000V         2.131300V            2.185000V
-10.5051ns         2.200500V         2.132300V            2.185200V
-10.7071ns         2.200800V         2.133300V            2.185400V
-10.9091ns         2.201200V         2.134200V            2.185600V
-11.1111ns         2.201500V         2.135100V            2.185800V
-11.3131ns         2.201700V         2.135800V            2.185900V
-11.5152ns         2.202000V         2.136500V            2.186000V
-11.7172ns         2.202200V         2.137100V            2.186100V
-11.9192ns         2.202400V         2.137700V            2.186200V
-12.1212ns         2.202500V         2.138200V            2.186300V
-12.3232ns         2.202700V         2.138700V            2.186400V
-12.5253ns         2.202800V         2.139100V            2.186400V
-12.7273ns         2.202900V         2.139500V            2.186500V
-12.9293ns         2.203000V         2.139900V            2.186500V
-13.1313ns         2.203100V         2.140200V            2.186600V
-13.3333ns         2.203200V         2.140500V            2.186600V
-13.5354ns         2.203300V         2.140700V            2.186600V
-13.7374ns         2.203300V         2.141000V            2.186700V
-13.9394ns         2.203400V         2.141200V            2.186700V
-14.1414ns         2.203400V         2.141400V            2.186700V
-14.3434ns         2.203500V         2.141600V            2.186700V
-14.5455ns         2.203500V         2.141800V            2.186700V
-14.7475ns         2.203600V         2.141900V            2.186800V
-14.9495ns         2.203600V         2.142000V            2.186800V
-15.1515ns         2.203600V         2.142200V            2.186800V
-15.3535ns         2.203600V         2.142300V            2.186800V
-15.5556ns         2.203700V         2.142400V            2.186800V
-15.7576ns         2.203700V         2.142500V            2.186800V
-15.9596ns         2.203700V         2.142600V            2.186800V
-16.1616ns         2.203700V         2.142600V            2.186800V
-16.3636ns         2.203700V         2.142700V            2.186800V
-16.5657ns         2.203700V         2.142800V            2.186900V
-16.7677ns         2.203700V         2.142800V            2.186900V
-16.9697ns         2.203800V         2.142900V            2.186900V
-17.1717ns         2.203800V         2.142900V            2.186900V
-17.3737ns         2.203800V         2.143000V            2.186900V
-17.5758ns         2.203800V         2.143000V            2.186900V
-17.7778ns         2.203800V         2.143000V            2.186900V
-17.9798ns         2.203800V         2.143100V            2.186900V
-18.1818ns         2.203800V         2.143100V            2.186900V
-18.3838ns         2.203800V         2.143100V            2.186900V
-18.5859ns         2.203800V         2.143100V            2.186900V
-18.7879ns         2.203800V         2.143200V            2.186900V
-18.9899ns         2.203800V         2.143200V            2.186900V
-19.1919ns         2.203800V         2.143200V            2.186900V
-19.3939ns         2.203800V         2.143200V            2.186900V
-19.5960ns         2.203800V         2.143200V            2.186900V
-19.7980ns         2.203800V         2.143200V            2.186900V
-20.0000ns         2.203800V         2.143300V            2.186900V
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       0.0
-V_fixture_min=   0.0
-V_fixture_max=   0.0
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              2.203900V         2.143400V            2.187000V
-0.2020ns          2.204000V         2.143400V            2.193500V
-0.4040ns          2.222800V         2.147700V            2.032600V
-0.6061ns          2.041300V         2.152800V            1.329800V
-0.8081ns          1.561500V         2.146100V            0.689440V
-1.0101ns          1.011100V         2.097000V            0.210050V
-1.2121ns          0.595520V         1.931200V            16.668000mV
-1.4141ns          0.291310V         1.573700V            3.287100mV
-1.6162ns          80.606000mV       1.160800V            1.540100mV
-1.8182ns          13.976000mV       0.816650V            0.795800mV
-2.0202ns          3.438200mV        0.556260V            0.249100mV
-2.2222ns          2.674800mV        0.354310V            0.141130mV
-2.4242ns          1.686600mV        0.200190V            -0.655480mV
-2.6263ns          0.612530mV        87.872000mV          -2.068600uV
-2.8283ns          0.572400mV        33.061000mV          -22.091000uV
-3.0303ns          0.375060mV        11.834000mV          -24.867000uV
-3.2323ns          0.241800mV        4.814600mV           -26.956000uV
-3.4343ns          -0.105830mV       3.354200mV           -15.925000uV
-3.6364ns          -75.323000uV      2.452700mV           -21.116000uV
-3.8384ns          4.162200uV        1.747000mV           -21.198000uV
-4.0404ns          -9.814400uV       1.397500mV           -20.735000uV
-4.2424ns          -8.341900uV       1.108100mV           -20.330000uV
-4.4444ns          -6.866100uV       0.872660mV           -19.920000uV
-4.6465ns          -5.387100uV       0.692450mV           -19.527000uV
-4.8485ns          -8.072400uV       0.289700mV           -19.137000uV
-5.0505ns          -7.958300uV       0.244360mV           -18.776000uV
-5.2525ns          -7.769600uV       -77.493000uV         -18.423000uV
-5.4545ns          -7.625700uV       -0.105340mV          -18.079000uV
-5.6566ns          -7.474800uV       -54.805000uV         -17.737000uV
-5.8586ns          -7.290100uV       10.015000uV          -17.420000uV
-6.0606ns          -7.095100uV       31.098000uV          -17.110000uV
-6.2626ns          -6.941900uV       27.849000uV          -16.798000uV
-6.4646ns          -6.801300uV       26.843000uV          -16.485000uV
-6.6667ns          -6.644700uV       25.837000uV          -16.193000uV
-6.8687ns          -6.483200uV       24.821000uV          -15.906000uV
-7.0707ns          -6.356800uV       23.930000uV          -15.617000uV
-7.2727ns          -6.241000uV       23.931000uV          -15.328000uV
-7.4747ns          -6.109700uV       23.867000uV          -15.057000uV
-7.6768ns          -5.973800uV       23.333000uV          -14.790000uV
-7.8788ns          -5.859500uV       22.861000uV          -14.523000uV
-8.0808ns          -5.751700uV       22.831000uV          -14.256000uV
-8.2828ns          -5.632300uV       22.765000uV          -14.004000uV
-8.4848ns          -5.509400uV       22.433000uV          -13.756000uV
-8.6869ns          -5.401200uV       22.127000uV          -13.508000uV
-8.8889ns          -5.297500uV       22.000000uV          -13.261000uV
-9.0909ns          -5.186800uV       21.856000uV          -13.026000uV
-9.2929ns          -5.073900uV       21.583000uV          -12.795000uV
-9.4949ns          -4.971400uV       21.321000uV          -12.566000uV
-9.6970ns          -4.872100uV       21.138000uV          -12.337000uV
-9.8990ns          -4.768700uV       20.948000uV          -12.119000uV
-10.1010ns         -4.615700uV       20.580000uV          -11.796500uV
-10.3030ns         -4.472500uV       20.255000uV          -11.478000uV
-10.5051ns         -4.375700uV       20.048000uV          -11.275000uV
-10.7071ns         -4.278400uV       19.819000uV          -11.074000uV
-10.9091ns         -4.186900uV       19.593000uV          -10.876000uV
-11.1111ns         -4.097100uV       19.385000uV          -10.679000uV
-11.3131ns         -4.006500uV       19.177000uV          -10.490000uV
-11.5152ns         -3.915700uV       18.963000uV          -10.303000uV
-11.7172ns         -3.829500uV       18.751000uV          -10.119000uV
-11.9192ns         -3.744700uV       18.550000uV          -9.935200uV
-12.1212ns         -3.659800uV       18.348000uV          -9.758900uV
-12.3232ns         -3.575000uV       18.147000uV          -9.584400uV
-12.5253ns         -3.493900uV       17.946000uV          -9.412900uV
-12.7273ns         -3.413900uV       17.750000uV          -9.242200uV
-12.9293ns         -3.334400uV       17.555000uV          -9.077700uV
-13.1313ns         -3.255000uV       17.367000uV          -8.914800uV
-13.3333ns         -3.178700uV       17.180000uV          -8.754900uV
-13.5354ns         -3.103400uV       16.992000uV          -8.595700uV
-13.7374ns         -3.028800uV       16.805000uV          -8.442200uV
-13.9394ns         -2.954500uV       16.625000uV          -8.290100uV
-14.1414ns         -2.882800uV       16.446000uV          -8.140800uV
-14.3434ns         -2.811900uV       16.271000uV          -7.992300uV
-14.5455ns         -2.741900uV       16.096000uV          -7.848800uV
-14.7475ns         -2.672100uV       15.921000uV          -7.706700uV
-14.9495ns         -2.604700uV       15.747000uV          -7.567200uV
-15.1515ns         -2.538000uV       15.582000uV          -7.428400uV
-15.3535ns         -2.472300uV       15.417000uV          -7.294300uV
-15.5556ns         -2.406900uV       15.254000uV          -7.161400uV
-15.7576ns         -2.343500uV       15.091000uV          -7.031000uV
-15.9596ns         -2.280700uV       14.928000uV          -6.901100uV
-16.1616ns         -2.219000uV       14.767000uV          -6.775700uV
-16.3636ns         -2.157500uV       14.614000uV          -6.651300uV
-16.5657ns         -2.097900uV       14.461000uV          -6.529200uV
-16.7677ns         -2.038900uV       14.310000uV          -6.407700uV
-16.9697ns         -1.980900uV       14.158000uV          -6.290200uV
-17.1717ns         -1.923100uV       14.007000uV          -6.173700uV
-17.3737ns         -1.867100uV       13.856000uV          -6.059300uV
-17.5758ns         -1.811500uV       13.715000uV          -5.945500uV
-17.7778ns         -1.756900uV       13.574000uV          -5.835400uV
-17.9798ns         -1.702700uV       13.433000uV          -5.726200uV
-18.1818ns         -1.649900uV       13.292000uV          -5.619000uV
-18.3838ns         -1.597600uV       13.151000uV          -5.512200uV
-18.5859ns         -1.546300uV       13.011000uV          -5.409000uV
-18.7879ns         -1.495300uV       12.881000uV          -5.306700uV
-18.9899ns         -1.445600uV       12.750000uV          -5.206100uV
-19.1919ns         -1.396400uV       12.619000uV          -5.105900uV
-19.3939ns         -1.348100uV       12.488000uV          -5.009100uV
-19.5960ns         -1.300200uV       12.357000uV          -4.913100uV
-19.7980ns         -1.253400uV       12.227000uV          -4.818400uV
-20.0000ns         -1.206900uV       12.109000uV          -4.724200uV
-|  
-[Falling Waveform] 
-R_fixture=       50.000000
-V_fixture=       3.300000
-V_fixture_min=   3.140000
-V_fixture_max=   3.470000
-|time     V(typ)              V(min)              V(max)
-|  
-0.0S              3.300000V         3.140000V            3.470000V
-0.2020ns          3.299700V         3.140000V            3.468500V
-0.4040ns          3.300800V         3.139500V            3.480800V
-0.6061ns          3.307700V         3.140100V            3.421400V
-0.8081ns          3.288700V         3.143500V            3.119600V
-1.0101ns          3.205000V         3.143800V            2.661400V
-1.2121ns          3.025100V         3.145800V            2.287000V
-1.4141ns          2.763000V         3.126600V            2.008100V
-1.6162ns          2.525800V         3.091800V            1.804300V
-1.8182ns          2.335100V         3.031500V            1.669500V
-2.0202ns          2.176400V         2.950000V            1.556300V
-2.2222ns          2.038500V         2.833800V            1.492000V
-2.4242ns          1.931900V         2.695300V            1.454000V
-2.6263ns          1.842100V         2.569900V            1.511700V
-2.8283ns          1.775200V         2.465400V            1.518000V
-3.0303ns          1.725800V         2.375800V            1.523200V
-3.2323ns          1.686600V         2.288200V            1.528200V
-3.4343ns          1.685200V         2.209700V            1.533400V
-3.6364ns          1.704000V         2.138800V            1.538300V
-3.8384ns          1.711300V         2.070500V            1.543000V
-4.0404ns          1.712500V         2.009900V            1.547600V
-4.2424ns          1.714100V         1.956200V            1.552200V
-4.4444ns          1.715500V         1.910000V            1.556700V
-4.6465ns          1.717000V         1.869400V            1.561200V
-4.8485ns          1.718600V         1.839700V            1.565600V
-5.0505ns          1.719900V         1.823800V            1.569900V
-5.2525ns          1.721200V         1.826000V            1.574200V
-5.4545ns          1.722500V         1.835200V            1.578400V
-5.6566ns          1.723800V         1.841500V            1.582600V
-5.8586ns          1.725000V         1.842800V            1.586700V
-6.0606ns          1.726200V         1.841300V            1.590800V
-6.2626ns          1.727400V         1.839800V            1.594800V
-6.4646ns          1.728600V         1.838400V            1.598800V
-6.6667ns          1.729800V         1.837000V            1.602700V
-6.8687ns          1.730900V         1.835500V            1.606600V
-7.0707ns          1.732000V         1.834000V            1.610400V
-7.2727ns          1.733200V         1.832700V            1.614200V
-7.4747ns          1.734300V         1.831300V            1.618000V
-7.6768ns          1.735400V         1.829900V            1.621600V
-7.8788ns          1.736400V         1.828500V            1.625300V
-8.0808ns          1.737500V         1.827100V            1.628900V
-8.2828ns          1.738600V         1.825800V            1.632500V
-8.4848ns          1.739600V         1.824400V            1.636000V
-8.6869ns          1.740600V         1.823100V            1.639400V
-8.8889ns          1.741700V         1.821800V            1.642900V
-9.0909ns          1.742700V         1.820400V            1.646300V
-9.2929ns          1.743700V         1.819100V            1.649600V
-9.4949ns          1.744700V         1.817800V            1.652900V
-9.6970ns          1.745600V         1.816500V            1.656200V
-9.8990ns          1.746600V         1.815200V            1.659400V
-10.1010ns         1.748050V         1.813350V            1.664200V
-10.3030ns         1.749400V         1.811400V            1.668900V
-10.5051ns         1.750400V         1.810200V            1.672000V
-10.7071ns         1.751300V         1.809000V            1.675000V
-10.9091ns         1.752200V         1.807800V            1.678000V
-11.1111ns         1.753100V         1.806500V            1.681000V
-11.3131ns         1.753900V         1.805400V            1.684000V
-11.5152ns         1.754800V         1.804200V            1.686900V
-11.7172ns         1.755700V         1.803000V            1.689700V
-11.9192ns         1.756500V         1.801800V            1.692600V
-12.1212ns         1.757400V         1.800700V            1.695400V
-12.3232ns         1.758200V         1.799500V            1.698200V
-12.5253ns         1.759000V         1.798400V            1.700900V
-12.7273ns         1.759800V         1.797300V            1.703600V
-12.9293ns         1.760600V         1.796200V            1.706300V
-13.1313ns         1.761400V         1.795100V            1.709000V
-13.3333ns         1.762200V         1.794000V            1.711600V
-13.5354ns         1.763000V         1.792900V            1.714200V
-13.7374ns         1.763800V         1.791800V            1.716700V
-13.9394ns         1.764500V         1.790800V            1.719300V
-14.1414ns         1.765300V         1.789700V            1.721800V
-14.3434ns         1.766000V         1.788700V            1.724200V
-14.5455ns         1.766800V         1.787700V            1.726700V
-14.7475ns         1.767500V         1.786600V            1.729100V
-14.9495ns         1.768200V         1.785600V            1.731500V
-15.1515ns         1.768900V         1.784600V            1.733900V
-15.3535ns         1.769600V         1.783600V            1.736200V
-15.5556ns         1.770300V         1.782700V            1.738500V
-15.7576ns         1.771000V         1.781700V            1.740800V
-15.9596ns         1.771700V         1.780700V            1.743100V
-16.1616ns         1.772400V         1.779800V            1.745300V
-16.3636ns         1.773000V         1.778800V            1.747500V
-16.5657ns         1.773700V         1.777900V            1.749700V
-16.7677ns         1.774300V         1.777000V            1.751900V
-16.9697ns         1.775000V         1.776000V            1.754000V
-17.1717ns         1.775600V         1.775100V            1.756200V
-17.3737ns         1.776300V         1.774200V            1.758300V
-17.5758ns         1.776900V         1.773300V            1.760300V
-17.7778ns         1.777500V         1.772400V            1.762400V
-17.9798ns         1.778100V         1.771600V            1.764400V
-18.1818ns         1.778700V         1.770700V            1.766400V
-18.3838ns         1.779300V         1.769800V            1.768400V
-18.5859ns         1.779900V         1.769000V            1.770400V
-18.7879ns         1.780500V         1.768100V            1.772300V
-18.9899ns         1.781100V         1.767300V            1.774200V
-19.1919ns         1.781600V         1.766500V            1.776200V
-19.3939ns         1.782200V         1.765700V            1.778000V
-19.5960ns         1.782800V         1.764900V            1.779900V
-19.7980ns         1.783300V         1.764000V            1.781700V
-|20.0000ns         1.783900V         1.763300V            1.783600V
-40.0000ns         1.783900V         1.550000V            1.783600V
-|  
-| End [Model] lvc330s140aaaaaaaaio
-|************************************************************************
-| End [Component]
-[End]
+|************************************************************************
+| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.1.454
+| Generate date: Sun Aug 20 05:55:46 2023
+|************************************************************************
+| IBIS File machxo.ibs
+| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
+| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
+| North Carolina State University, ERL, 2006
+|************************************************************************
+[IBIS ver]       3.2
+[File Name]     RAM2GS_LCMXO256C_im~.ibs
+[File Rev]       2.2
+[Date]           Mon Sep 28 10:44:10 EDT 2009
+[Source]         Lattice Semiconductor EE12 Process
+[Notes]          "Preliminary Version"
+                 Lattice Semiconductor has worked hard to ensure the
+                 models below are accurate and complete.  However, the
+                 data below was generated using simulation of the
+                 input/output model files for the silicon.  Therefore,
+                 the data below is for reference and initial design
+                 purposes only.
+|
+                 The data below is correlated to Spice models.  
+                 For questions regarding this data please contact
+                 us at www.latticesemi.com.
+|
+                 Lattice Semiconductor grants permission to use this
+                 data for use in printed circuit design using this
+                 Lattice programmable logic device.  Other use of this
+                 code, including the selling or duplication of any
+                 portion is strictly prohibited.
+|
+|                NAMING CONVENTION
+|
+        The IBIS [Model] header is limited by the specification to a
+        total of characters.  With such a set of characters available
+        for naming models it becomes important to attempt to
+        meaningfully encode the IO standards so they fit within the
+        twenty character limit.  It would seem that twenty characters
+        would provide room enough for describing IO's.  However, the
+        PLD IO structure continues to grow more and more complex.  The
+        complexity is making the twenty characters insuffiently
+        descriptive.  In order to overcome this issue the naming
+        convention described below is implemented to resolve the issue.
+|
+The twenty character space is managed as follows:
+                 bbbvvvsdddprugtcoixx
+|
+                 b = standard
+                 v = voltage (x.xx V)
+                 s = slew code
+                 d = drive (xx.x ma)
+                 p = pullup code
+                 r = series resistance code
+                 u = terminate to vcc code
+                 g = terminate to gnd code
+                 t = terminate to vtt code
+                 c = common mode termination mode
+                 o = diff resistor code
+                 i = diff resistor current code
+                 x = reserved
+|
+|
+                 standard
+|
+                 LVCMOS                   lvc
+                 lvcmosd                  lvd
+                 LVDSE                    lve
+                 LVTTL                    lvt
+                 lvttld                   ltd
+                 PCI                      pci
+                 pcix                     pcx
+                 AGP1x                    ag1
+                 agp2x                    ag2
+                 sstl_I                   ss1
+                 sstl_II                  ss2
+                 sstld_I                  s1d
+                 sstld_II                 s2d
+                 CTT                      ctt
+                 hstl_i                   hs1
+                 hstl_ii                  hs2
+                 hstl_iii                 hs3
+                 hstl_iv                  hs4
+                 hstld_i                  h1d
+                 hstld_ii                 h2d
+                 gtl                      gtl
+                 gtlplus                  gtp
+                 lvds                     lvs
+                 blvds                    blv
+                 mlvds                    mlv
+                 lvpecl                   lvp
+                 cml                      cml
+                 hypt                     hyp
+                 rsds                     rsd
+                 vref1                    vr1
+                 vref2                    vr2
+                 ref_res                  rer
+|
+|
+                 slew
+                 na                       a
+                 fast                     f
+                 slow                     s
+|
+                 pullmode
+                 off                      a
+                 pullup                   b
+                 pulldown                 c
+                 bushold                  d
+                 pciclamp                 e
+                 up_pciclamp              f
+                 down_pciclamp            g
+                 keeper_pciclamp          h
+                 schmitt                  i
+                 up_schmitt               j
+                 down_schmitt             k
+                 keeper_schmitt           l
+                 up_pciclamp_schmitt      m
+                 down_pciclamp_schmitt    n
+                 keeper_pciclamp_schmitt  o
+                 pciclamp_schmitt         p
+|
+                 impedence
+                 off                      a
+                 25                       b
+                 33                       c
+                 50                       d
+                 100                      e
+|
+                 termVCC
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termGND
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termVTT
+                 off                      a
+                 60                       b
+                 75                       c
+                 120                      d
+                 150                      e
+                 210                      f
+|
+                 VCMT
+                 off                      a
+                 VCMT                     b
+                 VTT                      c
+                 DDR-2                    d
+|
+                 differential resistor
+                 off                      a
+                 120                      b
+                 150                      c
+                 220                      d
+                 420                      e
+|
+                 differential current
+                 NA                       a
+                 2                        b
+                 3.5                      c
+                 4                        d
+                 6                        e
+|
+                 Reserved                 IO type
+                 in                       input only
+                 ou                       output
+                 io                       I/O
+                 od                       Open drain
+                 on                       Inverting differential I/O
+                                          (signal name only)
+                 op                       Non-Inverting differential I/O
+                                          (signal name only)
+|
+   All the IO models are generated with pull mode set to UP.
+|
+                 Lattice Semiconductor Corporation
+                 5555 NE Moore Court
+                 Hillsboro, OR 97214
+                 U.S.A
+|
+                 TEL: 1-800-Lattice (USA and Canada)
+                      408-826-6000 (other locations)
+|
+                 web: http://www.latticesemi.com/
+                 email: techsupport@latticesemi.com
+|
+|
+|
+[Disclaimer]     This IBIS source code is intended as a design reference
+   which illustrates how the Lattice Semiconductor device operates.
+   It is the user's responsibility to verify their design for
+   consistency and functionality through the use of formal
+   verification methods.  Lattice Semiconductor provides no warranty
+   regarding the use or functionality of this data.
+|
+[Copyright]      Copyright 2009 by Lattice Semiconductor Corporation
+|
+|  
+|************************************************************************
+|                       Component XO
+|************************************************************************
+|  
+[Component]     MXO256_MXO640_MXO1K_MXO2K
+[Manufacturer]    Lattice Semiconductor Corp.
+[Package]
+|TQFP100
+| variable            typ              min              max
+R_pkg                 70.5m            54.0m            87.0m
+L_pkg                 4.57nH           4.27nH           4.87nH
+C_pkg                 .52pF            .47pF            .57pF
+|
+[Pin] signal_name           model_name           R_pin     L_pin     C_pin
+32            CROW[0]              lvc330fxxxaaaaaaaain
+34            CROW[1]              lvc330fxxxaaaaaaaain
+21            Din[0]               lvc330fxxxaaaaaaaain
+15            Din[1]               lvc330fxxxaaaaaaaain
+14            Din[2]               lvc330fxxxaaaaaaaain
+16            Din[3]               lvc330fxxxaaaaaaaain
+18            Din[4]               lvc330fxxxaaaaaaaain
+17            Din[5]               lvc330fxxxaaaaaaaain
+20            Din[6]               lvc330fxxxaaaaaaaain
+19            Din[7]               lvc330fxxxaaaaaaaain
+1             Dout[0]              lvc330f040aaaaaaaaio
+7             Dout[1]              lvc330f040aaaaaaaaio
+8             Dout[2]              lvc330f040aaaaaaaaio
+6             Dout[3]              lvc330f040aaaaaaaaio
+4             Dout[4]              lvc330f040aaaaaaaaio
+5             Dout[5]              lvc330f040aaaaaaaaio
+2             Dout[6]              lvc330f040aaaaaaaaio
+3             Dout[7]              lvc330f040aaaaaaaaio
+57            LED                  lvc330s140aaaaaaaaio
+23            MAin[0]              lvc330fxxxaaaaaaaain
+38            MAin[1]              lvc330fxxxaaaaaaaain
+37            MAin[2]              lvc330fxxxaaaaaaaain
+47            MAin[3]              lvc330fxxxaaaaaaaain
+46            MAin[4]              lvc330fxxxaaaaaaaain
+45            MAin[5]              lvc330fxxxaaaaaaaain
+49            MAin[6]              lvc330fxxxaaaaaaaain
+44            MAin[7]              lvc330fxxxaaaaaaaain
+50            MAin[8]              lvc330fxxxaaaaaaaain
+51            MAin[9]              lvc330fxxxaaaaaaaain
+39            PHI2                 lvc330fxxxcaaaaaaain
+98            RA[0]                lvc330s040aaaaaaaaio
+87            RA[10]               lvc330s040aaaaaaaaio
+79            RA[11]               lvc330s040aaaaaaaaio
+89            RA[1]                lvc330s040aaaaaaaaio
+94            RA[2]                lvc330s040aaaaaaaaio
+97            RA[3]                lvc330s040aaaaaaaaio
+99            RA[4]                lvc330s040aaaaaaaaio
+95            RA[5]                lvc330s040aaaaaaaaio
+91            RA[6]                lvc330s040aaaaaaaaio
+100           RA[7]                lvc330s040aaaaaaaaio
+96            RA[8]                lvc330s040aaaaaaaaio
+85            RA[9]                lvc330s040aaaaaaaaio
+63            RBA[0]               lvc330s040aaaaaaaaio
+83            RBA[1]               lvc330s040aaaaaaaaio
+82            RCKE                 lvc330s040aaaaaaaaio
+86            RCLK                 lvc330fxxxaaaaaaaain
+76            RDQMH                lvc330s040aaaaaaaaio
+61            RDQML                lvc330s040aaaaaaaaio
+64            RD[0]                lvc330s040aaaaaaaaio
+65            RD[1]                lvc330s040aaaaaaaaio
+66            RD[2]                lvc330s040aaaaaaaaio
+67            RD[3]                lvc330s040aaaaaaaaio
+68            RD[4]                lvc330s040aaaaaaaaio
+69            RD[5]                lvc330s040aaaaaaaaio
+70            RD[6]                lvc330s040aaaaaaaaio
+71            RD[7]                lvc330s040aaaaaaaaio
+58            UFMCLK               lvc330s040aaaaaaaaio
+56            UFMSDI               lvc330s040aaaaaaaaio
+55            UFMSDO               lvc330fxxxaaaaaaaain
+27            nCCAS                lvc330fxxxbaaaaaaain
+43            nCRAS                lvc330fxxxbaaaaaaain
+22            nFWE                 lvc330fxxxaaaaaaaain
+78            nRCAS                lvc330s040aaaaaaaaio
+77            nRCS                 lvc330s040aaaaaaaaio
+73            nRRAS                lvc330s040aaaaaaaaio
+72            nRWE                 lvc330s040aaaaaaaaio
+53            nUFMCS               lvc330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330f040aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
+  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
+  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
+  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
+  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
+  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
+  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
+  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
+  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
+  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
+  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
+  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
+  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
+  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
+  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
+  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
+  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
+  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
+  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
+  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
+  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
+  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
+  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
+  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
+  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
+  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
+  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
+  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
+  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
+  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
+  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
+  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
+  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
+  0.00    9.270000nA        8.640000nA           10.950000nA
+  0.10    2.215985mA        1.960397mA           2.507890mA
+  0.20    4.086375mA        3.683686mA           4.498680mA
+  0.30    5.594166mA        5.150675mA           5.952471mA
+  0.40    6.738256mA        6.352364mA           6.929962mA
+  0.50    7.557146mA        7.289853mA           7.572152mA
+  0.60    8.124436mA        7.983242mA           8.013343mA
+  0.70    8.511126mA        8.476831mA           8.337834mA
+  0.80    8.778316mA        8.826620mA           8.591424mA
+  0.90    8.972606mA        9.080609mA           8.798515mA
+  1.00    9.121395mA        9.272098mA           8.969206mA
+  1.10    9.240584mA        9.422087mA           9.101296mA
+  1.20    9.339574mA        9.543476mA           9.202186mA
+  1.30    9.424063mA        9.644765mA           9.285275mA
+  1.40    9.498053mA        9.731354mA           9.357665mA
+  1.50    9.564242mA        9.806743mA           9.423455mA
+  1.60    9.625232mA        9.873832mA           9.485944mA
+  1.70    9.684621mA        9.934821mA           9.548134mA
+  1.80    9.747011mA        9.992810mA           9.610224mA
+  1.90    9.814800mA        10.052999mA          9.670813mA
+  2.00    9.885689mA        10.122988mA          9.728603mA
+  2.10    9.955379mA        10.203977mA          9.783293mA
+  2.20    10.021968mA       10.292966mA          9.835282mA
+  2.30    10.083958mA       10.380954mA          9.884972mA
+  2.40    10.141947mA       10.464943mA          9.932861mA
+  2.50    10.196936mA       10.542932mA          9.979551mA
+  2.60    10.249926mA       10.614921mA          10.025941mA
+  2.70    10.300915mA       10.681910mA          10.071930mA
+  2.80    10.350904mA       10.744899mA          10.118920mA
+  2.90    10.400894mA       10.805888mA          10.167909mA
+  3.00    10.451883mA       10.863877mA          10.218899mA
+  3.10    10.504872mA       10.921864mA          10.273889mA
+  3.20    10.559862mA       10.978747mA          10.332878mA
+  3.30    10.618848mA       11.037379mA          10.397868mA
+  3.40    10.682725mA       11.085335mA          10.469857mA
+  3.50    10.751986mA       11.124616mA          10.550843mA
+  3.60    10.804292mA       11.163898mA          10.640599mA
+  3.70    10.840604mA       11.203179mA          10.738212mA
+  3.80    10.876916mA       11.242461mA          10.773505mA
+  3.90    10.913228mA       11.281743mA          10.808797mA
+  4.00    10.949540mA       11.321024mA          10.844090mA
+  4.10    10.985852mA       11.360306mA          10.879382mA
+  4.20    11.022164mA       11.399587mA          10.914675mA
+  4.30    11.058476mA       11.438869mA          10.949967mA
+  4.40    11.094788mA       11.478151mA          10.985259mA
+  4.50    11.131100mA       11.517432mA          11.020552mA
+  4.60    11.167412mA       11.556714mA          11.055844mA
+  4.70    11.203724mA       11.595995mA          11.091137mA
+  4.80    11.240036mA       11.635277mA          11.126429mA
+  4.90    11.276348mA       11.674559mA          11.161721mA
+  5.00    11.312660mA       11.713840mA          11.197014mA
+  5.10    11.348972mA       11.753122mA          11.232306mA
+  5.20    11.385284mA       11.792403mA          11.267599mA
+  5.30    11.421596mA       11.831685mA          11.302891mA
+  5.40    11.457908mA       11.870967mA          11.338183mA
+  5.50    11.494220mA       11.910248mA          11.373476mA
+  5.60    11.530532mA       11.949530mA          11.408768mA
+  5.70    11.566844mA       11.988811mA          11.444061mA
+  5.80    11.603156mA       12.028093mA          11.479353mA
+  5.90    11.639468mA       12.067375mA          11.514645mA
+  6.00    11.675780mA       12.106656mA          11.549938mA
+  6.10    11.712092mA       12.145938mA          11.585230mA
+  6.20    11.748404mA       12.185219mA          11.620523mA
+  6.30    11.784716mA       12.224501mA          11.655815mA
+  6.40    11.821028mA       12.263783mA          11.691107mA
+  6.50    11.857340mA       12.303064mA          11.726400mA
+  6.60    11.893652mA       12.342346mA          11.761692mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    6.260163mA        5.384933mA           7.315403mA
+  -3.20    6.239699mA        5.366401mA           7.291487mA
+  -3.10    6.219236mA        5.347870mA           7.267570mA
+  -3.00    6.198773mA        5.329339mA           7.243653mA
+  -2.90    6.178310mA        5.310808mA           7.219736mA
+  -2.80    6.157847mA        5.292277mA           7.195819mA
+  -2.70    6.137383mA        5.273745mA           7.171903mA
+  -2.60    6.116920mA        5.255214mA           7.147986mA
+  -2.50    6.096457mA        5.236683mA           7.124069mA
+  -2.40    6.075994mA        5.218152mA           7.100152mA
+  -2.30    6.055531mA        5.199621mA           7.076235mA
+  -2.20    6.035067mA        5.181089mA           7.052319mA
+  -2.10    6.014604mA        5.162558mA           7.028402mA
+  -2.00    5.994141mA        5.144027mA           7.004485mA
+  -1.90    5.973678mA        5.125496mA           6.980568mA
+  -1.80    5.953215mA        5.106965mA           6.956651mA
+  -1.70    5.932751mA        5.088433mA           6.932735mA
+  -1.60    5.912288mA        5.069902mA           6.908818mA
+  -1.50    5.891825mA        5.051371mA           6.884901mA
+  -1.40    5.871362mA        5.032840mA           6.860984mA
+  -1.30    5.850899mA        5.014309mA           6.837067mA
+  -1.20    5.830435mA        4.995777mA           6.813151mA
+  -1.10    5.809972mA        4.977246mA           6.789234mA
+  -1.00    5.789509mA        4.958715mA           6.765317mA
+  -0.90    5.769046mA        4.940184mA           6.741400mA
+  -0.80    5.748583mA        4.921653mA           6.717483mA
+  -0.70    5.728119mA        4.903121mA           6.693567mA
+  -0.60    5.707656mA        4.884590mA           6.669650mA
+  -0.50    5.687193mA        4.866059mA           6.645733mA
+  -0.40    5.666730mA        4.847528mA           6.621816mA
+  -0.30    5.646267mA        4.828997mA           6.597899mA
+  -0.20    4.435786mA        3.802115mA           5.174820mA
+  -0.10    2.131925mA        1.838548mA           2.475669mA
+  0.00    -6.170000nA       -5.460000nA          -7.060000nA
+  0.10    -1.893038mA       -1.673728mA          -2.145840mA
+  0.20    -3.512428mA       -3.164516mA          -3.900829mA
+  0.30    -4.854717mA       -4.471005mA          -5.257719mA
+  0.40    -5.916606mA       -5.591894mA          -6.209108mA
+  0.50    -6.694696mA       -6.525883mA          -6.765898mA
+  0.60    -7.186085mA       -7.271372mA          -7.127487mA
+  0.70    -7.501974mA       -7.827161mA          -7.398777mA
+  0.80    -7.747264mA       -8.192150mA          -7.614967mA
+  0.90    -7.946053mA       -8.442739mA          -7.794856mA
+  1.00    -8.112642mA       -8.647928mA          -7.949846mA
+  1.10    -8.255932mA       -8.820317mA          -8.086935mA
+  1.20    -8.381921mA       -8.968206mA          -8.210725mA
+  1.30    -8.494611mA       -9.097295mA          -8.324315mA
+  1.40    -8.596900mA       -9.211784mA          -8.430004mA
+  1.50    -8.691089mA       -9.314673mA          -8.529494mA
+  1.60    -8.778479mA       -9.407962mA          -8.623884mA
+  1.70    -8.860368mA       -9.493551mA          -8.714073mA
+  1.80    -8.937858mA       -9.572640mA          -8.800963mA
+  1.90    -9.011447mA       -9.646329mA          -8.884952mA
+  2.00    -9.081837mA       -9.715418mA          -8.966642mA
+  2.10    -9.149526mA       -9.780507mA          -9.046332mA
+  2.20    -9.214816mA       -9.842296mA          -9.124421mA
+  2.30    -9.278305mA       -9.901185mA          -9.201211mA
+  2.40    -9.340094mA       -9.957574mA          -9.277001mA
+  2.50    -9.400784mA       -10.011863mA         -9.352391mA
+  2.60    -9.460574mA       -10.063852mA         -9.427582mA
+  2.70    -9.519964mA       -10.115841mA         -9.503173mA
+  2.80    -9.579454mA       -10.165830mA         -9.579563mA
+  2.90    -9.639644mA       -10.215819mA         -9.657654mA
+  3.00    -9.701034mA       -10.264808mA         -9.737845mA
+  3.10    -9.764525mA       -10.315796mA         -9.821135mA
+  3.20    -9.830715mA       -10.367780mA         -9.908326mA
+  3.30    -9.900606mA       -10.421706mA         -10.000817mA
+  3.40    -9.975092mA       -10.478956mA         -10.098808mA
+  3.50    -10.055705mA      -10.535873mA         -10.202798mA
+  3.60    -10.141346mA      -10.578599mA         -10.316786mA
+  3.70    -10.228551mA      -10.620789mA         -10.438679mA
+  3.80    -10.281620mA      -10.662980mA         -10.570555mA
+  3.90    -10.322662mA      -10.705170mA         -10.682977mA
+  4.00    -10.363704mA      -10.747360mA         -10.725640mA
+  4.10    -10.404746mA      -10.789550mA         -10.768303mA
+  4.20    -10.445787mA      -10.831741mA         -10.810966mA
+  4.30    -10.486829mA      -10.873931mA         -10.853629mA
+  4.40    -10.527871mA      -10.916121mA         -10.896292mA
+  4.50    -10.568913mA      -10.958311mA         -10.938955mA
+  4.60    -10.609955mA      -11.000502mA         -10.981618mA
+  4.70    -10.650997mA      -11.042692mA         -11.024281mA
+  4.80    -10.692039mA      -11.084882mA         -11.066944mA
+  4.90    -10.733081mA      -11.127072mA         -11.109607mA
+  5.00    -10.774122mA      -11.169262mA         -11.152270mA
+  5.10    -10.815164mA      -11.211453mA         -11.194933mA
+  5.20    -10.856206mA      -11.253643mA         -11.237597mA
+  5.30    -10.897248mA      -11.295833mA         -11.280260mA
+  5.40    -10.938290mA      -11.338023mA         -11.322923mA
+  5.50    -10.979332mA      -11.380214mA         -11.365586mA
+  5.60    -11.020374mA      -11.422404mA         -11.408249mA
+  5.70    -11.061416mA      -11.464594mA         -11.450912mA
+  5.80    -11.102458mA      -11.506784mA         -11.493575mA
+  5.90    -11.143499mA      -11.548975mA         -11.536238mA
+  6.00    -11.184541mA      -11.591165mA         -11.578901mA
+  6.10    -11.225583mA      -11.633355mA         -11.621564mA
+  6.20    -11.266625mA      -11.675545mA         -11.664227mA
+  6.30    -11.307667mA      -11.717736mA         -11.706890mA
+  6.40    -11.348709mA      -11.759926mA         -11.749553mA
+  6.50    -11.389751mA      -11.802116mA         -11.792216mA
+  6.55    -11.410272mA      -11.823211mA         -11.813548mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.204000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270300uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.287529/0.242724n  0.301503/0.328867n  0.291718/0.195168n
+dV/dt_f  0.313320/0.253363n  0.309840/0.389332n  0.311820/0.168025n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.782900V         2.609000V            2.960100V
+0.2020ns          2.783000V         2.608900V            2.962600V
+0.4040ns          2.787900V         2.610900V            3.090500V
+0.6061ns          3.029800V         2.611800V            3.431300V
+0.8081ns          3.255100V         2.678900V            3.466400V
+1.0101ns          3.294700V         2.982700V            3.469200V
+1.2121ns          3.298300V         3.109600V            3.469600V
+1.4141ns          3.299300V         3.123400V            3.469800V
+1.6162ns          3.299600V         3.137700V            3.469900V
+1.8182ns          3.299700V         3.138900V            3.469900V
+2.0202ns          3.299800V         3.139300V            3.469900V
+2.2222ns          3.299900V         3.139600V            3.469900V
+2.4242ns          3.299900V         3.139700V            3.469200V
+2.6263ns          3.299900V         3.139700V            3.471700V
+2.8283ns          3.299900V         3.139800V            3.470600V
+3.0303ns          3.299900V         3.139800V            3.470200V
+3.2323ns          3.299900V         3.139900V            3.470100V
+3.4343ns          3.302400V         3.139900V            3.470000V
+3.6364ns          3.301400V         3.139900V            3.470000V
+3.8384ns          3.300600V         3.139900V            3.470000V
+4.0404ns          3.300200V         3.139900V            3.470000V
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+|  
+[Rising Waveform] 
+R_fixture=       50.000000
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+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
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+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
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+18.5859ns         0.929260uV        -1.244900uV          1.563400uV
+18.7879ns         1.076500uV        -0.945630uV          1.618300uV
+18.9899ns         1.240200uV        -0.755480uV          1.685500uV
+19.1919ns         1.323300uV        -0.596720uV          1.777100uV
+19.3939ns         1.386600uV        -0.356900uV          1.868700uV
+19.5960ns         1.516000uV        -93.762000nV         1.960300uV
+19.7980ns         1.661600uV        58.234000nV          2.029300uV
+20.0000ns         1.679900uV        0.178250uV           2.053600uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468600V
+0.4040ns          3.300900V         3.139100V            3.481500V
+0.6061ns          3.273500V         3.140100V            3.087100V
+0.8081ns          2.996200V         3.146300V            2.839700V
+1.0101ns          2.788200V         3.080900V            2.749500V
+1.2121ns          2.688900V         2.938500V            2.718000V
+1.4141ns          2.644300V         2.755500V            2.708000V
+1.6162ns          2.624600V         2.644100V            2.704400V
+1.8182ns          2.616600V         2.580800V            2.704300V
+2.0202ns          2.613600V         2.541800V            2.704600V
+2.2222ns          2.612200V         2.522600V            2.705800V
+2.4242ns          2.612400V         2.511700V            2.715900V
+2.6263ns          2.613100V         2.506400V            2.750300V
+2.8283ns          2.613800V         2.503800V            2.759900V
+3.0303ns          2.614700V         2.502700V            2.769100V
+3.2323ns          2.615500V         2.502100V            2.777600V
+3.4343ns          2.621600V         2.502400V            2.785300V
+3.6364ns          2.628100V         2.502800V            2.792600V
+3.8384ns          2.632500V         2.503300V            2.799400V
+4.0404ns          2.639100V         2.503900V            2.806100V
+4.2424ns          2.645800V         2.504500V            2.812200V
+4.4444ns          2.652000V         2.505100V            2.818200V
+4.6465ns          2.658100V         2.505700V            2.823700V
+4.8485ns          2.663800V         2.508100V            2.829100V
+5.0505ns          2.669000V         2.489000V            2.834000V
+5.2525ns          2.674300V         2.476800V            2.838800V
+5.4545ns          2.679100V         2.477300V            2.843300V
+5.6566ns          2.683900V         2.482300V            2.847700V
+5.8586ns          2.688200V         2.488300V            2.851700V
+6.0606ns          2.692500V         2.494500V            2.855700V
+6.2626ns          2.696400V         2.500200V            2.859400V
+6.4646ns          2.700300V         2.505800V            2.863000V
+6.6667ns          2.703900V         2.511100V            2.866300V
+6.8687ns          2.707400V         2.516200V            2.869600V
+7.0707ns          2.710700V         2.521000V            2.872700V
+7.2727ns          2.713900V         2.525700V            2.875700V
+7.4747ns          2.716900V         2.530100V            2.878500V
+7.6768ns          2.719800V         2.534400V            2.881200V
+7.8788ns          2.722500V         2.538400V            2.883800V
+8.0808ns          2.725200V         2.542300V            2.886300V
+8.2828ns          2.727700V         2.545900V            2.888700V
+8.4848ns          2.730200V         2.549500V            2.891000V
+8.6869ns          2.732400V         2.552800V            2.893100V
+8.8889ns          2.734700V         2.556100V            2.895300V
+9.0909ns          2.736800V         2.559100V            2.897300V
+9.2929ns          2.738800V         2.562100V            2.899200V
+9.4949ns          2.740700V         2.564900V            2.901100V
+9.6970ns          2.742600V         2.567700V            2.903000V
+9.8990ns          2.744300V         2.570200V            2.904700V
+10.1010ns         2.746850V         2.573900V            2.907350V
+10.3030ns         2.749200V         2.577400V            2.909900V
+10.5051ns         2.750700V         2.579600V            2.911600V
+10.7071ns         2.752100V         2.581700V            2.913200V
+10.9091ns         2.753400V         2.583700V            2.914800V
+11.1111ns         2.754700V         2.585700V            2.916300V
+11.3131ns         2.756000V         2.587500V            2.917800V
+11.5152ns         2.757200V         2.589300V            2.919300V
+11.7172ns         2.758300V         2.591000V            2.920700V
+11.9192ns         2.759400V         2.592600V            2.922000V
+12.1212ns         2.760400V         2.594200V            2.923300V
+12.3232ns         2.761400V         2.595700V            2.924600V
+12.5253ns         2.762300V         2.597100V            2.925800V
+12.7273ns         2.763200V         2.598500V            2.927000V
+12.9293ns         2.764000V         2.599800V            2.928100V
+13.1313ns         2.764900V         2.601100V            2.929200V
+13.3333ns         2.765600V         2.602300V            2.930200V
+13.5354ns         2.766400V         2.603500V            2.931300V
+13.7374ns         2.767100V         2.604600V            2.932200V
+13.9394ns         2.767800V         2.605700V            2.933200V
+14.1414ns         2.768400V         2.606800V            2.934100V
+14.3434ns         2.769000V         2.607800V            2.935000V
+14.5455ns         2.769600V         2.608700V            2.935800V
+14.7475ns         2.770200V         2.609600V            2.936600V
+14.9495ns         2.770700V         2.610500V            2.937400V
+15.1515ns         2.771200V         2.611300V            2.938200V
+15.3535ns         2.771700V         2.612100V            2.938900V
+15.5556ns         2.772200V         2.612900V            2.939600V
+15.7576ns         2.772600V         2.613600V            2.940300V
+15.9596ns         2.773000V         2.614400V            2.941000V
+16.1616ns         2.773400V         2.615000V            2.941600V
+16.3636ns         2.773800V         2.615700V            2.942200V
+16.5657ns         2.774100V         2.616300V            2.942800V
+16.7677ns         2.774400V         2.616900V            2.943400V
+16.9697ns         2.774700V         2.617500V            2.943900V
+17.1717ns         2.775000V         2.618000V            2.944500V
+17.3737ns         2.775300V         2.618600V            2.945000V
+17.5758ns         2.775600V         2.619100V            2.945500V
+17.7778ns         2.775800V         2.619500V            2.945900V
+17.9798ns         2.776100V         2.620000V            2.946400V
+18.1818ns         2.776300V         2.620400V            2.946900V
+18.3838ns         2.776500V         2.620900V            2.947300V
+18.5859ns         2.776700V         2.621300V            2.947700V
+18.7879ns         2.776900V         2.621700V            2.948100V
+18.9899ns         2.777100V         2.622000V            2.948500V
+19.1919ns         2.777200V         2.622400V            2.948900V
+19.3939ns         2.777400V         2.622700V            2.949300V
+19.5960ns         2.777500V         2.623000V            2.949600V
+19.7980ns         2.777700V         2.623300V            2.950000V
+20.0000ns         2.777800V         2.623600V            2.950300V
+|  
+| End [Model] lvc330f040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330fxxxaaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415500nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+| End [Model] lvc330fxxxaaaaaaaain
+|************************************************************************
+[Model]           lvc330fxxxbaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201050A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133030A
+  -1.38    -0.116640A        -0.121710A           -0.116640A
+  -1.30    -0.101410A        -0.107420A           -0.100700A
+  -1.22    -86.417000mA      -93.409000mA         -84.978000mA
+  -1.14    -71.666000mA      -79.637000mA         -69.556000mA
+  -1.06    -57.221000mA      -66.146000mA         -54.661000mA
+  -0.98    -43.217000mA      -53.024000mA         -40.890000mA
+  -0.90    -29.927000mA      -40.408000mA         -29.654000mA
+  -0.82    -17.982000mA      -28.511000mA         -21.115000mA
+  -0.74    -8.854400mA       -17.682000mA         -13.653000mA
+  -0.66    -3.663100mA       -8.577600mA          -7.237700mA
+  -0.58    -1.172200mA       -2.564300mA          -2.648300mA
+  -0.50    -0.318120mA       -0.464400mA          -0.594790mA
+  -0.42    -0.137880mA       -0.131860mA          -0.170510mA
+  -0.34    -0.109480mA       -92.671000uA         -0.122000mA
+  -0.26    -0.105780mA       -87.760000uA         -0.117970mA
+  -0.18    -0.105360mA       -87.079000uA         -0.117690mA
+  -0.10    -0.105300mA       -86.972000uA         -0.117660mA
+  -0.02    -0.105290mA       -86.946000uA         -0.117640mA
+  0.06    -0.105270mA       -86.931000uA         -0.117630mA
+  0.14    -0.105260mA       -86.918000uA         -0.117610mA
+  0.22    -0.105240mA       -86.905000uA         -0.117600mA
+  0.30    -0.105230mA       -86.892000uA         -0.117580mA
+  0.38    -0.105220mA       -86.878000uA         -0.117560mA
+  0.46    -0.105200mA       -86.864000uA         -0.117540mA
+  0.54    -0.105180mA       -86.849000uA         -0.117530mA
+  0.62    -0.105170mA       -86.834000uA         -0.117500mA
+  0.70    -0.105150mA       -86.818000uA         -0.117480mA
+  0.78    -0.105130mA       -86.801000uA         -0.117460mA
+  0.86    -0.105110mA       -86.783000uA         -0.117420mA
+  0.94    -0.105060mA       -86.761000uA         -0.117350mA
+  1.02    -0.105000mA       -86.718000uA         -0.117250mA
+  1.10    -0.104900mA       -86.652000uA         -0.117140mA
+  1.18    -0.104790mA       -86.563000uA         -0.117010mA
+  1.26    -0.104660mA       -86.454000uA         -0.116870mA
+  1.34    -0.104520mA       -86.328000uA         -0.116710mA
+  1.42    -0.104360mA       -86.186000uA         -0.116550mA
+  1.50    -0.104190mA       -86.027000uA         -0.116380mA
+  1.58    -0.104010mA       -85.852000uA         -0.116200mA
+  1.66    -0.103810mA       -85.660000uA         -0.116010mA
+  1.74    -0.103600mA       -85.448000uA         -0.115810mA
+  1.82    -0.103380mA       -85.214000uA         -0.115600mA
+  1.90    -0.103130mA       -84.953000uA         -0.115380mA
+  1.98    -0.102860mA       -84.659000uA         -0.115140mA
+  2.06    -0.102560mA       -84.336000uA         -0.114880mA
+  2.14    -0.102230mA       -83.988000uA         -0.114600mA
+  2.22    -0.101860mA       -83.605000uA         -0.114300mA
+  2.30    -0.101430mA       -83.172000uA         -0.113960mA
+  2.38    -0.100960mA       -82.673000uA         -0.113590mA
+  2.46    -0.100430mA       -82.088000uA         -0.113170mA
+  2.54    -99.809000uA      -81.393000uA         -0.112690mA
+  2.62    -99.072000uA      -80.257000uA         -0.112130mA
+  2.70    -98.172000uA      -76.079000uA         -0.111480mA
+  2.78    -97.041000uA      -68.566000uA         -0.110710mA
+  2.86    -94.411000uA      -58.013000uA         -0.109770mA
+  2.94    -86.817000uA      -44.639000uA         -0.108560mA
+  3.02    -74.531000uA      -28.610000uA         -0.106940mA
+  3.10    -57.975000uA      -10.054000uA         -0.102590mA
+  3.18    -37.471000uA      11.025000uA          -91.172000uA
+  3.26    -13.273000uA      34.949000uA          -73.303000uA
+  3.30    0.149480uA        48.450000uA          -62.148000uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.925400uA        1.695300uA           2.182200uA
+  -3.26    1.907100uA        1.679500uA           2.161600uA
+  -3.22    1.889100uA        1.664000uA           2.141300uA
+  -3.18    1.871200uA        1.648600uA           2.121100uA
+  -3.14    1.853600uA        1.633400uA           2.101200uA
+  -3.10    1.836100uA        1.618400uA           2.081400uA
+  -3.06    1.818900uA        1.603500uA           2.061900uA
+  -3.02    1.801800uA        1.588800uA           2.042600uA
+  -2.98    1.785000uA        1.574200uA           2.023500uA
+  -2.94    1.768300uA        1.559800uA           2.004600uA
+  -2.90    1.751800uA        1.545600uA           1.985900uA
+  -2.86    1.735600uA        1.531500uA           1.967400uA
+  -2.82    1.719500uA        1.517600uA           1.949100uA
+  -2.78    1.703600uA        1.503800uA           1.931100uA
+  -2.74    1.687800uA        1.490200uA           1.913200uA
+  -2.70    1.672300uA        1.476700uA           1.895500uA
+  -2.66    1.657000uA        1.463400uA           1.878100uA
+  -2.62    1.641800uA        1.450200uA           1.860800uA
+  -2.58    1.626800uA        1.437200uA           1.843800uA
+  -2.54    1.612000uA        1.424300uA           1.827000uA
+  -2.50    1.597400uA        1.411500uA           1.810300uA
+  -2.46    1.582900uA        1.398900uA           1.793900uA
+  -2.42    1.568600uA        1.386500uA           1.777600uA
+  -2.38    1.554500uA        1.374100uA           1.761600uA
+  -2.34    1.540600uA        1.361900uA           1.745700uA
+  -2.30    1.526800uA        1.349900uA           1.730100uA
+  -2.26    1.513300uA        1.337900uA           1.714600uA
+  -2.22    1.499800uA        1.326100uA           1.699300uA
+  -2.18    1.486600uA        1.314500uA           1.684300uA
+  -2.14    1.473500uA        1.302900uA           1.669400uA
+  -2.10    1.460500uA        1.291500uA           1.654700uA
+  -2.06    1.447700uA        1.280200uA           1.640100uA
+  -2.02    1.435100uA        1.269000uA           1.625800uA
+  -1.98    1.422600uA        1.257900uA           1.611700uA
+  -1.94    1.410300uA        1.247000uA           1.597700uA
+  -1.90    1.398200uA        1.236200uA           1.583900uA
+  -1.86    1.386100uA        1.225500uA           1.570300uA
+  -1.82    1.374300uA        1.214800uA           1.556900uA
+  -1.78    1.362500uA        1.204400uA           1.543600uA
+  -1.74    1.351000uA        1.194000uA           1.530500uA
+  -1.70    1.339500uA        1.183700uA           1.517600uA
+  -1.66    1.328200uA        1.173500uA           1.504900uA
+  -1.62    1.317000uA        1.163400uA           1.492300uA
+  -1.58    1.306000uA        1.153500uA           1.479900uA
+  -1.54    1.295100uA        1.143600uA           1.467600uA
+  -1.50    1.284300uA        1.133800uA           1.455500uA
+  -1.46    1.273700uA        1.124100uA           1.443600uA
+  -1.42    1.263200uA        1.114500uA           1.431800uA
+  -1.38    1.252800uA        1.105000uA           1.420200uA
+  -1.34    1.242500uA        1.095600uA           1.408700uA
+  -1.30    1.232300uA        1.086200uA           1.397400uA
+  -1.26    1.222300uA        1.077000uA           1.386200uA
+  -1.22    1.212300uA        1.067800uA           1.375200uA
+  -1.18    1.202500uA        1.058700uA           1.364300uA
+  -1.14    1.192800uA        1.049700uA           1.353500uA
+  -1.10    1.183200uA        1.040800uA           1.342900uA
+  -1.06    1.173700uA        1.031900uA           1.332400uA
+  -1.02    1.164300uA        1.023100uA           1.322100uA
+  -0.98    1.154900uA        1.014400uA           1.311900uA
+  -0.94    1.145700uA        1.005700uA           1.301800uA
+  -0.90    1.136600uA        0.997110uA           1.291800uA
+  -0.86    1.127600uA        0.988570uA           1.281900uA
+  -0.82    1.118600uA        0.980090uA           1.272200uA
+  -0.78    1.109700uA        0.971680uA           1.262500uA
+  -0.74    1.100900uA        0.963320uA           1.253000uA
+  -0.70    1.092200uA        0.955010uA           1.243600uA
+  -0.66    1.083600uA        0.946770uA           1.234300uA
+  -0.62    1.075000uA        0.938590uA           1.225100uA
+  -0.58    1.066500uA        0.930470uA           1.215900uA
+  -0.54    1.058100uA        0.922430uA           1.206900uA
+  -0.50    1.049700uA        0.914500uA           1.198000uA
+  -0.46    1.041400uA        0.906750uA           1.189000uA
+  -0.42    1.033100uA        0.899340uA           1.180100uA
+  -0.38    1.024800uA        0.892740uA           1.171100uA
+  -0.34    1.020592uA        0.890363uA           1.166191uA
+  -0.30    1.020569uA        0.890343uA           1.166164uA
+  -0.26    1.020475uA        0.890261uA           1.166058uA
+  -0.22    1.020102uA        0.889935uA           1.165631uA
+  -0.18    1.018607uA        0.888631uA           1.163922uA
+  -0.14    1.012627uA        0.883414uA           1.157089uA
+  -0.10    0.988706uA        0.862546uA           1.129756uA
+  -0.06    0.893025uA        0.779074uA           1.020425uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+| End [Model] lvc330fxxxbaaaaaaain
+|************************************************************************
+[Model]           lvc330fxxxcaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447790A           -0.471180A
+  -2.18    -0.421140A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201050A           -0.209560A
+  -1.62    -0.174190A        -0.174390A           -0.177660A
+  -1.54    -0.150480A        -0.153310A           -0.151880A
+  -1.46    -0.132440A        -0.136600A           -0.133040A
+  -1.38    -0.116650A        -0.121720A           -0.116660A
+  -1.30    -0.101420A        -0.107430A           -0.100730A
+  -1.22    -86.431000mA      -93.414000mA         -85.016000mA
+  -1.14    -71.684000mA      -79.643000mA         -69.612000mA
+  -1.06    -57.245000mA      -66.154000mA         -54.753000mA
+  -0.98    -43.252000mA      -53.034000mA         -41.074000mA
+  -0.90    -29.984000mA      -40.420000mA         -30.037000mA
+  -0.82    -18.095000mA      -28.529000mA         -21.592000mA
+  -0.74    -9.103200mA       -17.711000mA         -14.139000mA
+  -0.66    -4.031300mA       -8.632500mA          -7.727000mA
+  -0.58    -1.542300mA       -2.680900mA          -3.137100mA
+  -0.50    -0.637910mA       -0.641580mA          -1.050200mA
+  -0.42    -0.382200mA       -0.283040mA          -0.537030mA
+  -0.34    -0.274320mA       -0.191220mA          -0.380580mA
+  -0.26    -0.195030mA       -0.134430mA          -0.271430mA
+  -0.18    -0.125260mA       -86.198000uA         -0.174070mA
+  -0.10    -63.603000uA      -43.916000uA         -87.706000uA
+  -0.02    -11.477000uA      -8.053000uA          -15.489000uA
+  0.06    29.171000uA       20.579000uA          38.171000uA
+  0.14    58.135000uA       42.109000uA          72.311000uA
+  0.22    76.454000uA       57.027000uA          90.391000uA
+  0.30    86.646000uA       66.282000uA          99.147000uA
+  0.38    91.915000uA       71.334000uA          0.103720mA
+  0.46    94.550000uA       73.863000uA          0.106370mA
+  0.54    95.817000uA       75.185000uA          0.107930mA
+  0.62    96.442000uA       75.976000uA          0.108770mA
+  0.70    96.793000uA       76.516000uA          0.109190mA
+  0.78    97.021000uA       76.923000uA          0.109410mA
+  0.86    97.187000uA       77.250000uA          0.109550mA
+  0.94    97.320000uA       77.526000uA          0.109650mA
+  1.02    97.431000uA       77.766000uA          0.109720mA
+  1.10    97.528000uA       77.982000uA          0.109790mA
+  1.18    97.616000uA       78.178000uA          0.109850mA
+  1.26    97.697000uA       78.360000uA          0.109900mA
+  1.34    97.773000uA       78.530000uA          0.109950mA
+  1.42    97.844000uA       78.691000uA          0.110000mA
+  1.50    97.912000uA       78.844000uA          0.110050mA
+  1.58    97.978000uA       78.991000uA          0.110090mA
+  1.66    98.042000uA       79.132000uA          0.110130mA
+  1.74    98.104000uA       79.268000uA          0.110170mA
+  1.82    98.164000uA       79.399000uA          0.110220mA
+  1.90    98.223000uA       79.526000uA          0.110260mA
+  1.98    98.280000uA       79.648000uA          0.110300mA
+  2.06    98.337000uA       79.768000uA          0.110330mA
+  2.14    98.393000uA       79.890000uA          0.110370mA
+  2.22    98.448000uA       80.015000uA          0.110410mA
+  2.30    98.503000uA       80.140000uA          0.110450mA
+  2.38    98.559000uA       80.265000uA          0.110490mA
+  2.46    98.617000uA       80.391000uA          0.110530mA
+  2.54    98.679000uA       80.518000uA          0.110570mA
+  2.62    98.744000uA       80.648000uA          0.110620mA
+  2.70    98.813000uA       80.782000uA          0.110670mA
+  2.78    98.889000uA       80.922000uA          0.110720mA
+  2.86    98.972000uA       81.070000uA          0.110780mA
+  2.94    99.065000uA       81.227000uA          0.110850mA
+  3.02    99.170000uA       81.396000uA          0.110930mA
+  3.10    99.290000uA       81.580000uA          0.111020mA
+  3.18    99.427000uA       81.843000uA          0.111120mA
+  3.26    99.584000uA       82.507000uA          0.111250mA
+  3.30    99.674000uA       83.566000uA          0.111320mA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    0.153710mA        0.132100mA           0.170160mA
+  -3.26    0.152730mA        0.131080mA           0.169210mA
+  -3.22    0.151750mA        0.130060mA           0.168250mA
+  -3.18    0.150760mA        0.129030mA           0.167280mA
+  -3.14    0.149760mA        0.128000mA           0.166290mA
+  -3.10    0.148750mA        0.126970mA           0.165290mA
+  -3.06    0.147740mA        0.125930mA           0.164280mA
+  -3.02    0.146720mA        0.124900mA           0.163270mA
+  -2.98    0.145700mA        0.123870mA           0.162240mA
+  -2.94    0.144670mA        0.122850mA           0.161210mA
+  -2.90    0.143640mA        0.121820mA           0.160170mA
+  -2.86    0.142610mA        0.120800mA           0.159120mA
+  -2.82    0.141580mA        0.119780mA           0.158070mA
+  -2.78    0.140550mA        0.118770mA           0.157010mA
+  -2.74    0.139520mA        0.117770mA           0.155950mA
+  -2.70    0.138490mA        0.116770mA           0.154890mA
+  -2.66    0.137460mA        0.115780mA           0.153830mA
+  -2.62    0.136440mA        0.114800mA           0.152760mA
+  -2.58    0.135420mA        0.113820mA           0.151700mA
+  -2.54    0.134410mA        0.112860mA           0.150630mA
+  -2.50    0.133400mA        0.111900mA           0.149570mA
+  -2.46    0.132400mA        0.110960mA           0.148510mA
+  -2.42    0.131410mA        0.110030mA           0.147460mA
+  -2.38    0.130420mA        0.109110mA           0.146410mA
+  -2.34    0.129450mA        0.108200mA           0.145370mA
+  -2.30    0.128490mA        0.107310mA           0.144330mA
+  -2.26    0.127530mA        0.106430mA           0.143310mA
+  -2.22    0.126590mA        0.105570mA           0.142290mA
+  -2.18    0.125660mA        0.104720mA           0.141280mA
+  -2.14    0.124750mA        0.103880mA           0.140280mA
+  -2.10    0.123850mA        0.103060mA           0.139300mA
+  -2.06    0.122960mA        0.102260mA           0.138330mA
+  -2.02    0.122090mA        0.101480mA           0.137370mA
+  -1.98    0.121230mA        0.100710mA           0.136420mA
+  -1.94    0.120390mA        99.955000uA          0.135490mA
+  -1.90    0.119560mA        99.221000uA          0.134580mA
+  -1.86    0.118760mA        98.504000uA          0.133680mA
+  -1.82    0.117970mA        97.804000uA          0.132800mA
+  -1.78    0.117200mA        97.123000uA          0.131940mA
+  -1.74    0.116440mA        96.459000uA          0.131090mA
+  -1.70    0.115710mA        95.814000uA          0.130260mA
+  -1.66    0.114990mA        95.186000uA          0.129460mA
+  -1.62    0.114300mA        94.577000uA          0.128670mA
+  -1.58    0.113620mA        93.985000uA          0.127900mA
+  -1.54    0.112960mA        93.412000uA          0.127150mA
+  -1.50    0.112320mA        92.857000uA          0.126420mA
+  -1.46    0.111700mA        92.319000uA          0.125710mA
+  -1.42    0.111100mA        91.799000uA          0.125030mA
+  -1.38    0.110520mA        91.297000uA          0.124360mA
+  -1.34    0.109960mA        90.812000uA          0.123710mA
+  -1.30    0.109420mA        90.344000uA          0.123090mA
+  -1.26    0.108900mA        89.893000uA          0.122490mA
+  -1.22    0.108400mA        89.459000uA          0.121900mA
+  -1.18    0.107910mA        89.041000uA          0.121340mA
+  -1.14    0.107450mA        88.639000uA          0.120800mA
+  -1.10    0.107000mA        88.253000uA          0.120280mA
+  -1.06    0.106570mA        87.883000uA          0.119780mA
+  -1.02    0.106160mA        87.527000uA          0.119300mA
+  -0.98    0.105760mA        87.187000uA          0.118840mA
+  -0.94    0.105390mA        86.861000uA          0.118400mA
+  -0.90    0.105030mA        86.548000uA          0.117980mA
+  -0.86    0.104690mA        86.250000uA          0.117580mA
+  -0.82    0.104360mA        85.965000uA          0.117190mA
+  -0.78    0.104050mA        85.693000uA          0.116830mA
+  -0.74    0.103750mA        85.433000uA          0.116480mA
+  -0.70    0.103470mA        85.185000uA          0.116150mA
+  -0.66    0.103200mA        84.949000uA          0.115830mA
+  -0.62    0.102950mA        84.724000uA          0.115540mA
+  -0.58    0.102710mA        84.509000uA          0.115260mA
+  -0.54    0.102490mA        84.306000uA          0.114990mA
+  -0.50    0.102270mA        84.112000uA          0.114740mA
+  -0.46    0.102070mA        83.927000uA          0.114500mA
+  -0.42    0.101880mA        83.752000uA          0.114280mA
+  -0.38    0.101700mA        83.587000uA          0.114070mA
+  -0.34    0.101620mA        83.508000uA          0.113960mA
+  -0.30    0.101620mA        83.508000uA          0.113960mA
+  -0.26    0.101620mA        83.508000uA          0.113960mA
+  -0.22    0.101620mA        83.508000uA          0.113960mA
+  -0.18    0.101620mA        83.508000uA          0.113750mA
+  -0.14    0.100460mA        82.918000uA          0.112450mA
+  -0.10    0.100030mA        82.241000uA          0.112040mA
+  -0.06    99.844000uA       81.938000uA          0.111870mA
+  -0.02    99.724000uA       81.761000uA          0.111750mA
+  0.00    99.674000uA       81.693000uA          0.111690mA
+|  
+| End [Model] lvc330fxxxcaaaaaaain
+|************************************************************************
+[Model]           lvc330s040aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
+  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
+  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
+  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
+  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
+  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
+  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
+  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
+  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
+  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
+  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
+  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
+  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
+  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
+  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
+  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
+  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
+  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
+  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
+  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
+  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
+  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
+  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
+  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
+  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
+  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
+  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
+  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
+  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
+  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
+  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
+  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
+  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
+  0.00    9.270000nA        8.640000nA           10.950000nA
+  0.10    2.215985mA        1.960397mA           2.507890mA
+  0.20    4.086375mA        3.683686mA           4.498680mA
+  0.30    5.594166mA        5.150675mA           5.952471mA
+  0.40    6.738256mA        6.352364mA           6.929962mA
+  0.50    7.557146mA        7.289853mA           7.572152mA
+  0.60    8.124436mA        7.983242mA           8.013343mA
+  0.70    8.511126mA        8.476831mA           8.337834mA
+  0.80    8.778316mA        8.826620mA           8.591424mA
+  0.90    8.972606mA        9.080609mA           8.798515mA
+  1.00    9.121395mA        9.272098mA           8.969206mA
+  1.10    9.240584mA        9.422087mA           9.101296mA
+  1.20    9.339574mA        9.543476mA           9.202186mA
+  1.30    9.424063mA        9.644765mA           9.285275mA
+  1.40    9.498053mA        9.731354mA           9.357665mA
+  1.50    9.564242mA        9.806743mA           9.423455mA
+  1.60    9.625232mA        9.873832mA           9.485944mA
+  1.70    9.684621mA        9.934821mA           9.548134mA
+  1.80    9.747011mA        9.992810mA           9.610224mA
+  1.90    9.814800mA        10.052999mA          9.670813mA
+  2.00    9.885689mA        10.122988mA          9.728603mA
+  2.10    9.955379mA        10.203977mA          9.783293mA
+  2.20    10.021968mA       10.292966mA          9.835282mA
+  2.30    10.083958mA       10.380954mA          9.884972mA
+  2.40    10.141947mA       10.464943mA          9.932861mA
+  2.50    10.196936mA       10.542932mA          9.979551mA
+  2.60    10.249926mA       10.614921mA          10.025941mA
+  2.70    10.300915mA       10.681910mA          10.071930mA
+  2.80    10.350904mA       10.744899mA          10.118920mA
+  2.90    10.400894mA       10.805888mA          10.167909mA
+  3.00    10.451883mA       10.863877mA          10.218899mA
+  3.10    10.504872mA       10.921864mA          10.273889mA
+  3.20    10.559862mA       10.978747mA          10.332878mA
+  3.30    10.618848mA       11.037379mA          10.397868mA
+  3.40    10.682725mA       11.085335mA          10.469857mA
+  3.50    10.751986mA       11.124616mA          10.550843mA
+  3.60    10.804292mA       11.163898mA          10.640599mA
+  3.70    10.840604mA       11.203179mA          10.738212mA
+  3.80    10.876916mA       11.242461mA          10.773505mA
+  3.90    10.913228mA       11.281743mA          10.808797mA
+  4.00    10.949540mA       11.321024mA          10.844090mA
+  4.10    10.985852mA       11.360306mA          10.879382mA
+  4.20    11.022164mA       11.399587mA          10.914675mA
+  4.30    11.058476mA       11.438869mA          10.949967mA
+  4.40    11.094788mA       11.478151mA          10.985259mA
+  4.50    11.131100mA       11.517432mA          11.020552mA
+  4.60    11.167412mA       11.556714mA          11.055844mA
+  4.70    11.203724mA       11.595995mA          11.091137mA
+  4.80    11.240036mA       11.635277mA          11.126429mA
+  4.90    11.276348mA       11.674559mA          11.161721mA
+  5.00    11.312660mA       11.713840mA          11.197014mA
+  5.10    11.348972mA       11.753122mA          11.232306mA
+  5.20    11.385284mA       11.792403mA          11.267599mA
+  5.30    11.421596mA       11.831685mA          11.302891mA
+  5.40    11.457908mA       11.870967mA          11.338183mA
+  5.50    11.494220mA       11.910248mA          11.373476mA
+  5.60    11.530532mA       11.949530mA          11.408768mA
+  5.70    11.566844mA       11.988811mA          11.444061mA
+  5.80    11.603156mA       12.028093mA          11.479353mA
+  5.90    11.639468mA       12.067375mA          11.514645mA
+  6.00    11.675780mA       12.106656mA          11.549938mA
+  6.10    11.712092mA       12.145938mA          11.585230mA
+  6.20    11.748404mA       12.185219mA          11.620523mA
+  6.30    11.784716mA       12.224501mA          11.655815mA
+  6.40    11.821028mA       12.263783mA          11.691107mA
+  6.50    11.857340mA       12.303064mA          11.726400mA
+  6.60    11.893652mA       12.342346mA          11.761692mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    6.260163mA        5.384933mA           7.315403mA
+  -3.20    6.239699mA        5.366401mA           7.291487mA
+  -3.10    6.219236mA        5.347870mA           7.267570mA
+  -3.00    6.198773mA        5.329339mA           7.243653mA
+  -2.90    6.178310mA        5.310808mA           7.219736mA
+  -2.80    6.157847mA        5.292277mA           7.195819mA
+  -2.70    6.137383mA        5.273745mA           7.171903mA
+  -2.60    6.116920mA        5.255214mA           7.147986mA
+  -2.50    6.096457mA        5.236683mA           7.124069mA
+  -2.40    6.075994mA        5.218152mA           7.100152mA
+  -2.30    6.055531mA        5.199621mA           7.076235mA
+  -2.20    6.035067mA        5.181089mA           7.052319mA
+  -2.10    6.014604mA        5.162558mA           7.028402mA
+  -2.00    5.994141mA        5.144027mA           7.004485mA
+  -1.90    5.973678mA        5.125496mA           6.980568mA
+  -1.80    5.953215mA        5.106965mA           6.956651mA
+  -1.70    5.932751mA        5.088433mA           6.932735mA
+  -1.60    5.912288mA        5.069902mA           6.908818mA
+  -1.50    5.891825mA        5.051371mA           6.884901mA
+  -1.40    5.871362mA        5.032840mA           6.860984mA
+  -1.30    5.850899mA        5.014309mA           6.837067mA
+  -1.20    5.830435mA        4.995777mA           6.813151mA
+  -1.10    5.809972mA        4.977246mA           6.789234mA
+  -1.00    5.789509mA        4.958715mA           6.765317mA
+  -0.90    5.769046mA        4.940184mA           6.741400mA
+  -0.80    5.748583mA        4.921653mA           6.717483mA
+  -0.70    5.728119mA        4.903121mA           6.693567mA
+  -0.60    5.707656mA        4.884590mA           6.669650mA
+  -0.50    5.687193mA        4.866059mA           6.645733mA
+  -0.40    5.666730mA        4.847528mA           6.621816mA
+  -0.30    5.646267mA        4.828997mA           6.597899mA
+  -0.20    4.435786mA        3.802115mA           5.174820mA
+  -0.10    2.131925mA        1.838548mA           2.475669mA
+  0.00    -6.170000nA       -5.460000nA          -7.060000nA
+  0.10    -1.893038mA       -1.673728mA          -2.145840mA
+  0.20    -3.512428mA       -3.164516mA          -3.900829mA
+  0.30    -4.854717mA       -4.471005mA          -5.257719mA
+  0.40    -5.916606mA       -5.591894mA          -6.209108mA
+  0.50    -6.694696mA       -6.525883mA          -6.765898mA
+  0.60    -7.186085mA       -7.271372mA          -7.127487mA
+  0.70    -7.501974mA       -7.827161mA          -7.398777mA
+  0.80    -7.747264mA       -8.192150mA          -7.614967mA
+  0.90    -7.946053mA       -8.442739mA          -7.794856mA
+  1.00    -8.112642mA       -8.647928mA          -7.949846mA
+  1.10    -8.255932mA       -8.820317mA          -8.086935mA
+  1.20    -8.381921mA       -8.968206mA          -8.210725mA
+  1.30    -8.494611mA       -9.097295mA          -8.324315mA
+  1.40    -8.596900mA       -9.211784mA          -8.430004mA
+  1.50    -8.691089mA       -9.314673mA          -8.529494mA
+  1.60    -8.778479mA       -9.407962mA          -8.623884mA
+  1.70    -8.860368mA       -9.493551mA          -8.714073mA
+  1.80    -8.937858mA       -9.572640mA          -8.800963mA
+  1.90    -9.011447mA       -9.646329mA          -8.884952mA
+  2.00    -9.081837mA       -9.715418mA          -8.966642mA
+  2.10    -9.149526mA       -9.780507mA          -9.046332mA
+  2.20    -9.214816mA       -9.842296mA          -9.124421mA
+  2.30    -9.278305mA       -9.901185mA          -9.201211mA
+  2.40    -9.340094mA       -9.957574mA          -9.277001mA
+  2.50    -9.400784mA       -10.011863mA         -9.352391mA
+  2.60    -9.460574mA       -10.063852mA         -9.427582mA
+  2.70    -9.519964mA       -10.115841mA         -9.503173mA
+  2.80    -9.579454mA       -10.165830mA         -9.579563mA
+  2.90    -9.639644mA       -10.215819mA         -9.657654mA
+  3.00    -9.701034mA       -10.264808mA         -9.737845mA
+  3.10    -9.764525mA       -10.315796mA         -9.821135mA
+  3.20    -9.830715mA       -10.367780mA         -9.908326mA
+  3.30    -9.900606mA       -10.421706mA         -10.000817mA
+  3.40    -9.975092mA       -10.478956mA         -10.098808mA
+  3.50    -10.055705mA      -10.535873mA         -10.202798mA
+  3.60    -10.141346mA      -10.578599mA         -10.316786mA
+  3.70    -10.228551mA      -10.620789mA         -10.438679mA
+  3.80    -10.281620mA      -10.662980mA         -10.570555mA
+  3.90    -10.322662mA      -10.705170mA         -10.682977mA
+  4.00    -10.363704mA      -10.747360mA         -10.725640mA
+  4.10    -10.404746mA      -10.789550mA         -10.768303mA
+  4.20    -10.445787mA      -10.831741mA         -10.810966mA
+  4.30    -10.486829mA      -10.873931mA         -10.853629mA
+  4.40    -10.527871mA      -10.916121mA         -10.896292mA
+  4.50    -10.568913mA      -10.958311mA         -10.938955mA
+  4.60    -10.609955mA      -11.000502mA         -10.981618mA
+  4.70    -10.650997mA      -11.042692mA         -11.024281mA
+  4.80    -10.692039mA      -11.084882mA         -11.066944mA
+  4.90    -10.733081mA      -11.127072mA         -11.109607mA
+  5.00    -10.774122mA      -11.169262mA         -11.152270mA
+  5.10    -10.815164mA      -11.211453mA         -11.194933mA
+  5.20    -10.856206mA      -11.253643mA         -11.237597mA
+  5.30    -10.897248mA      -11.295833mA         -11.280260mA
+  5.40    -10.938290mA      -11.338023mA         -11.322923mA
+  5.50    -10.979332mA      -11.380214mA         -11.365586mA
+  5.60    -11.020374mA      -11.422404mA         -11.408249mA
+  5.70    -11.061416mA      -11.464594mA         -11.450912mA
+  5.80    -11.102458mA      -11.506784mA         -11.493575mA
+  5.90    -11.143499mA      -11.548975mA         -11.536238mA
+  6.00    -11.184541mA      -11.591165mA         -11.578901mA
+  6.10    -11.225583mA      -11.633355mA         -11.621564mA
+  6.20    -11.266625mA      -11.675545mA         -11.664227mA
+  6.30    -11.307667mA      -11.717736mA         -11.706890mA
+  6.40    -11.348709mA      -11.759926mA         -11.749553mA
+  6.50    -11.389751mA      -11.802116mA         -11.792216mA
+  6.55    -11.410272mA      -11.823211mA         -11.813548mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.287457/0.467122n  0.301305/0.700268n  0.291706/0.349090n
+dV/dt_f  0.309900/0.449885n  0.304680/0.837003n  0.308100/0.266290n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.782900V         2.609000V            2.960100V
+0.2020ns          2.783000V         2.608900V            2.962600V
+0.4040ns          2.788300V         2.610900V            3.086900V
+0.6061ns          3.016200V         2.611900V            3.417200V
+0.8081ns          3.244000V         2.678900V            3.463300V
+1.0101ns          3.291900V         2.961800V            3.467200V
+1.2121ns          3.295700V         3.102900V            3.468900V
+1.4141ns          3.297500V         3.120100V            3.469600V
+1.6162ns          3.298700V         3.136000V            3.469800V
+1.8182ns          3.299500V         3.136600V            3.469900V
+2.0202ns          3.299700V         3.137000V            3.469900V
+2.2222ns          3.299800V         3.138000V            3.469900V
+2.4242ns          3.299900V         3.138900V            3.469200V
+2.6263ns          3.299900V         3.139400V            3.471100V
+2.8283ns          3.299900V         3.139700V            3.470500V
+3.0303ns          3.299900V         3.139800V            3.470100V
+3.2323ns          3.299900V         3.139800V            3.470000V
+3.4343ns          3.300600V         3.139900V            3.470000V
+3.6364ns          3.301100V         3.139900V            3.470000V
+3.8384ns          3.300500V         3.139900V            3.470000V
+4.0404ns          3.300200V         3.139900V            3.470000V
+4.2424ns          3.300000V         3.139900V            3.470000V
+4.4444ns          3.300000V         3.139900V            3.470000V
+4.6465ns          3.300000V         3.139900V            3.470000V
+4.8485ns          3.300000V         3.140000V            3.469900V
+5.0505ns          3.300000V         3.140800V            3.469900V
+5.2525ns          3.300000V         3.141300V            3.469900V
+5.4545ns          3.299900V         3.140700V            3.469900V
+5.6566ns          3.299900V         3.140400V            3.469900V
+5.8586ns          3.299900V         3.140200V            3.469900V
+6.0606ns          3.299900V         3.140000V            3.469900V
+6.2626ns          3.299900V         3.140000V            3.469900V
+6.4646ns          3.299900V         3.140000V            3.469900V
+6.6667ns          3.299900V         3.140000V            3.469900V
+6.8687ns          3.299900V         3.140000V            3.469900V
+7.0707ns          3.299900V         3.139900V            3.469900V
+7.2727ns          3.299900V         3.139900V            3.470000V
+7.4747ns          3.299900V         3.139900V            3.470000V
+7.6768ns          3.299900V         3.139900V            3.470000V
+7.8788ns          3.299900V         3.139900V            3.470000V
+8.0808ns          3.299900V         3.139900V            3.470000V
+8.2828ns          3.299900V         3.139900V            3.470000V
+8.4848ns          3.299900V         3.139900V            3.470000V
+8.6869ns          3.299900V         3.139900V            3.470000V
+8.8889ns          3.299900V         3.139800V            3.470000V
+9.0909ns          3.299900V         3.139800V            3.470000V
+9.2929ns          3.299900V         3.139900V            3.470000V
+9.4949ns          3.299900V         3.139900V            3.470000V
+9.6970ns          3.299900V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.139900V            3.470000V
+11.7172ns         3.300000V         3.139900V            3.470000V
+11.9192ns         3.300000V         3.139900V            3.470000V
+12.1212ns         3.300000V         3.139900V            3.470000V
+12.3232ns         3.300000V         3.139900V            3.470000V
+12.5253ns         3.300000V         3.139900V            3.470000V
+12.7273ns         3.300000V         3.139900V            3.470000V
+12.9293ns         3.300000V         3.139900V            3.470000V
+13.1313ns         3.300000V         3.139900V            3.470000V
+13.3333ns         3.300000V         3.139900V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
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+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              4.225900uV        4.920300uV           3.956100uV
+0.2020ns          -0.116230mV       2.501000uV           -0.231630mV
+0.4040ns          -1.733400mV       5.664000uV           -6.571900mV
+0.6061ns          1.816900mV        -0.405040mV          0.151930V
+0.8081ns          0.105890V         -6.434700mV          0.334290V
+1.0101ns          0.246820V         13.033000mV          0.470790V
+1.2121ns          0.360950V         89.173000mV          0.542490V
+1.4141ns          0.454430V         0.176030V            0.572640V
+1.6162ns          0.508590V         0.271450V            0.582550V
+1.8182ns          0.534420V         0.353570V            0.588040V
+2.0202ns          0.543170V         0.429910V            0.588930V
+2.2222ns          0.549780V         0.484400V            0.588840V
+2.4242ns          0.550820V         0.517300V            0.590870V
+2.6263ns          0.551300V         0.536250V            0.553540V
+2.8283ns          0.551520V         0.543010V            0.497470V
+3.0303ns          0.551620V         0.548720V            0.468060V
+3.2323ns          0.551660V         0.549820V            0.453000V
+3.4343ns          0.558640V         0.550520V            0.446500V
+3.6364ns          0.508640V         0.550950V            0.442330V
+3.8384ns          0.463860V         0.551240V            0.440380V
+4.0404ns          0.438900V         0.551370V            0.438930V
+4.2424ns          0.425590V         0.551450V            0.438730V
+4.4444ns          0.417880V         0.551520V            0.438850V
+4.6465ns          0.413990V         0.551560V            0.439830V
+4.8485ns          0.411950V         0.551690V            0.441070V
+5.0505ns          0.411060V         0.558950V            0.443300V
+5.2525ns          0.410360V         0.519020V            0.446000V
+5.4545ns          0.410640V         0.480460V            0.448850V
+5.6566ns          0.411100V         0.455460V            0.451660V
+5.8586ns          0.412570V         0.440580V            0.454380V
+6.0606ns          0.414210V         0.430510V            0.456880V
+6.2626ns          0.416980V         0.426080V            0.459280V
+6.4646ns          0.420210V         0.423650V            0.461440V
+6.6667ns          0.423660V         0.422350V            0.463510V
+6.8687ns          0.426990V         0.421790V            0.465350V
+7.0707ns          0.430100V         0.421350V            0.467110V
+7.2727ns          0.433090V         0.421520V            0.468670V
+7.4747ns          0.435900V         0.421800V            0.470160V
+7.6768ns          0.438640V         0.422560V            0.471470V
+7.8788ns          0.441270V         0.423400V            0.472730V
+8.0808ns          0.443800V         0.425080V            0.473840V
+8.2828ns          0.446130V         0.426920V            0.474900V
+8.4848ns          0.448370V         0.429830V            0.475830V
+8.6869ns          0.450420V         0.433230V            0.476730V
+8.8889ns          0.452380V         0.436930V            0.477510V
+9.0909ns          0.454180V         0.440610V            0.478270V
+9.2929ns          0.455900V         0.444280V            0.478930V
+9.4949ns          0.457470V         0.447610V            0.479560V
+9.6970ns          0.458970V         0.450880V            0.480120V
+9.8990ns          0.460340V         0.453950V            0.480650V
+10.1010ns         0.462260V         0.458380V            0.481335V
+10.3030ns         0.464000V         0.462500V            0.481950V
+10.5051ns         0.465050V         0.464970V            0.482320V
+10.7071ns         0.466050V         0.467390V            0.482650V
+10.9091ns         0.466960V         0.469580V            0.482960V
+11.1111ns         0.467830V         0.471720V            0.483240V
+11.3131ns         0.468630V         0.473660V            0.483500V
+11.5152ns         0.469380V         0.475550V            0.483730V
+11.7172ns         0.470080V         0.477260V            0.483950V
+11.9192ns         0.470740V         0.478940V            0.484140V
+12.1212ns         0.471340V         0.480450V            0.484330V
+12.3232ns         0.471910V         0.481930V            0.484490V
+12.5253ns         0.472440V         0.483270V            0.484640V
+12.7273ns         0.472930V         0.484580V            0.484780V
+12.9293ns         0.473390V         0.485750V            0.484900V
+13.1313ns         0.473820V         0.486910V            0.485020V
+13.3333ns         0.474220V         0.487950V            0.485120V
+13.5354ns         0.474590V         0.488970V            0.485220V
+13.7374ns         0.474940V         0.489880V            0.485310V
+13.9394ns         0.475260V         0.490780V            0.485390V
+14.1414ns         0.475560V         0.491590V            0.485460V
+14.3434ns         0.475840V         0.492380V            0.485530V
+14.5455ns         0.476100V         0.493090V            0.485590V
+14.7475ns         0.476340V         0.493790V            0.485640V
+14.9495ns         0.476570V         0.494420V            0.485700V
+15.1515ns         0.476780V         0.495030V            0.485740V
+15.3535ns         0.476970V         0.495580V            0.485790V
+15.5556ns         0.477160V         0.496120V            0.485820V
+15.7576ns         0.477330V         0.496610V            0.485860V
+15.9596ns         0.477490V         0.497090V            0.485890V
+16.1616ns         0.477630V         0.497510V            0.485920V
+16.3636ns         0.477770V         0.497930V            0.485950V
+16.5657ns         0.477890V         0.498290V            0.485980V
+16.7677ns         0.478010V         0.498640V            0.486000V
+16.9697ns         0.478120V         0.498990V            0.486020V
+17.1717ns         0.478230V         0.499340V            0.486040V
+17.3737ns         0.478320V         0.499630V            0.486060V
+17.5758ns         0.478410V         0.499920V            0.486070V
+17.7778ns         0.478490V         0.500160V            0.486090V
+17.9798ns         0.478570V         0.500400V            0.486100V
+18.1818ns         0.478640V         0.500630V            0.486110V
+18.3838ns         0.478710V         0.500870V            0.486120V
+18.5859ns         0.478770V         0.501070V            0.486130V
+18.7879ns         0.478830V         0.501260V            0.486140V
+18.9899ns         0.478880V         0.501430V            0.486150V
+19.1919ns         0.478930V         0.501590V            0.486160V
+19.3939ns         0.478980V         0.501750V            0.486170V
+19.5960ns         0.479020V         0.501910V            0.486170V
+19.7980ns         0.479060V         0.502040V            0.486180V
+20.0000ns         0.479100V         0.502180V            0.486180V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.479590V         0.504150V            0.486240V
+0.2020ns          0.479620V         0.504110V            0.490470V
+0.4040ns          0.474660V         0.515850V            0.338690V
+0.6061ns          0.260970V         0.518810V            49.227000mV
+0.8081ns          57.693000mV       0.442430V            5.358900mV
+1.0101ns          10.006000mV       0.270560V            1.610600mV
+1.2121ns          3.219300mV        0.116620V            0.420340mV
+1.4141ns          1.539600mV        28.455000mV          0.168590mV
+1.6162ns          0.544500mV        9.235500mV           63.243000uV
+1.8182ns          0.242750mV        4.555900mV           28.107000uV
+2.0202ns          0.152510mV        2.530000mV           3.232400uV
+2.2222ns          71.354000uV       1.674500mV           0.754660uV
+2.4242ns          30.528000uV       0.925740mV           -0.544570mV
+2.6263ns          17.219000uV       0.496800mV           -0.223670mV
+2.8283ns          7.642900uV        0.286310mV           -18.013000uV
+3.0303ns          2.754100uV        0.206810mV           -16.664000uV
+3.2323ns          3.719000uV        0.129010mV           -14.948000uV
+3.4343ns          -0.126320mV       73.076000uV          -9.356000uV
+3.6364ns          -0.242850mV       44.601000uV          -11.098000uV
+3.8384ns          -32.574000uV      27.309000uV          -9.946200uV
+4.0404ns          3.566200uV        14.959000uV          -9.483100uV
+4.2424ns          -5.306100uV       8.251900uV           -8.932600uV
+4.4444ns          -13.750000uV      4.915800uV           -8.381600uV
+4.6465ns          10.940000uV       2.652800uV           -7.820100uV
+4.8485ns          18.035000uV       -0.108180mV          -7.265300uV
+5.0505ns          2.807200uV        0.153640mV           -6.819000uV
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+6.0606ns          3.185500uV        13.918000uV          -4.806500uV
+6.2626ns          3.361600uV        13.732000uV          -4.457800uV
+6.4646ns          3.383800uV        15.275000uV          -4.112200uV
+6.6667ns          3.430500uV        14.174000uV          -3.816000uV
+6.8687ns          3.538200uV        13.495000uV          -3.520100uV
+7.0707ns          3.619900uV        13.582000uV          -3.230000uV
+7.2727ns          3.637500uV        13.501000uV          -2.942000uV
+7.4747ns          3.665100uV        13.116000uV          -2.688300uV
+7.6768ns          3.717300uV        12.820000uV          -2.435300uV
+7.8788ns          3.759700uV        12.684000uV          -2.191800uV
+8.0808ns          3.777800uV        12.528000uV          -1.949700uV
+8.2828ns          3.800700uV        12.338000uV          -1.731900uV
+8.4848ns          3.835100uV        12.144000uV          -1.514700uV
+8.6869ns          3.864700uV        11.942000uV          -1.308300uV
+8.8889ns          3.882800uV        11.757000uV          -1.103000uV
+9.0909ns          3.903100uV        11.601000uV          -0.916190uV
+9.2929ns          3.928900uV        11.419000uV          -0.730020uV
+9.4949ns          3.951900uV        11.189000uV          -0.554530uV
+9.6970ns          3.968200uV        10.989000uV          -0.379920uV
+9.8990ns          3.985700uV        10.842000uV          -0.219880uV
+10.1010ns         4.015950uV        10.553500uV          12.615000nV
+10.3030ns         4.039500uV        10.248000uV          0.231740uV
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+10.7071ns         4.071500uV        9.956800uV           0.504010uV
+10.9091ns         4.087100uV        9.748000uV           0.632480uV
+11.1111ns         4.098800uV        9.573200uV           0.760290uV
+11.3131ns         4.111100uV        9.460300uV           0.877400uV
+11.5152ns         4.125100uV        9.320800uV           0.994070uV
+11.7172ns         4.137800uV        9.133200uV           1.103600uV
+11.9192ns         4.147200uV        8.978700uV           1.212600uV
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+12.3232ns         4.168500uV        8.764100uV           1.413100uV
+12.5253ns         4.178700uV        8.597200uV           1.506700uV
+12.7273ns         4.186000uV        8.456400uV           1.599900uV
+12.9293ns         4.193900uV        8.362900uV           1.686000uV
+13.1313ns         4.203100uV        8.269500uV           1.771700uV
+13.3333ns         4.211200uV        8.176000uV           1.851800uV
+13.5354ns         4.216800uV        8.065600uV           1.931600uV
+13.7374ns         4.222900uV        7.924500uV           2.005300uV
+13.9394ns         4.230300uV        7.808100uV           2.078800uV
+14.1414ns         4.236700uV        7.736300uV           2.147500uV
+14.3434ns         4.240800uV        7.664500uV           2.215800uV
+14.5455ns         4.245400uV        7.592700uV           2.279000uV
+14.7475ns         4.251200uV        7.503700uV           2.342000uV
+14.9495ns         4.256200uV        7.383500uV           2.400800uV
+15.1515ns         4.259000uV        7.286500uV           2.459400uV
+15.3535ns         4.262400uV        7.231700uV           2.513600uV
+15.5556ns         4.267000uV        7.176900uV           2.567700uV
+15.7576ns         4.270800uV        7.122100uV           2.618100uV
+15.9596ns         4.272600uV        7.049900uV           2.668300uV
+16.1616ns         4.274900uV        6.946400uV           2.714800uV
+16.3636ns         4.278400uV        6.865000uV           2.761200uV
+16.5657ns         4.281200uV        6.823600uV           2.804400uV
+16.7677ns         4.282300uV        6.782200uV           2.847500uV
+16.9697ns         4.283800uV        6.740700uV           2.887400uV
+17.1717ns         4.286400uV        6.682100uV           2.927100uV
+17.3737ns         4.288400uV        6.592100uV           2.964200uV
+17.5758ns         4.288700uV        6.523200uV           3.001200uV
+17.7778ns         4.289500uV        6.492500uV           3.035400uV
+17.9798ns         4.291500uV        6.461700uV           3.069500uV
+18.1818ns         4.292800uV        6.430900uV           3.101400uV
+18.3838ns         4.292600uV        6.383000uV           3.133100uV
+18.5859ns         4.292900uV        6.304200uV           3.162500uV
+18.7879ns         4.294300uV        6.245400uV           3.191700uV
+18.9899ns         4.295100uV        6.223200uV           3.219100uV
+19.1919ns         4.294400uV        6.200900uV           3.246200uV
+19.3939ns         4.294300uV        6.178600uV           3.270600uV
+19.5960ns         4.295200uV        6.139500uV           3.294900uV
+19.7980ns         4.295400uV        6.069700uV           3.319200uV
+20.0000ns         4.294000uV        6.076600uV           3.343600uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468600V
+0.4040ns          3.300900V         3.139100V            3.483300V
+0.6061ns          3.304400V         3.140100V            3.272000V
+0.8081ns          3.179500V         3.145900V            3.030300V
+1.0101ns          3.015400V         3.136300V            2.907000V
+1.2121ns          2.895000V         3.095000V            2.856700V
+1.4141ns          2.821600V         2.995500V            2.837500V
+1.6162ns          2.781500V         2.910100V            2.829200V
+1.8182ns          2.760300V         2.834600V            2.826700V
+2.0202ns          2.751400V         2.769700V            2.825700V
+2.2222ns          2.745500V         2.722000V            2.826100V
+2.4242ns          2.743500V         2.688600V            2.830900V
+2.6263ns          2.743000V         2.667400V            2.878100V
+2.8283ns          2.742800V         2.654200V            2.895900V
+3.0303ns          2.742900V         2.645000V            2.900000V
+3.2323ns          2.743200V         2.639400V            2.902500V
+3.4343ns          2.756300V         2.636600V            2.904500V
+3.6364ns          2.776700V         2.635200V            2.906500V
+3.8384ns          2.790100V         2.634000V            2.908200V
+4.0404ns          2.792600V         2.633800V            2.909800V
+4.2424ns          2.793100V         2.633700V            2.911300V
+4.4444ns          2.793600V         2.633900V            2.912900V
+4.6465ns          2.793500V         2.634100V            2.914200V
+4.8485ns          2.793500V         2.636300V            2.915600V
+5.0505ns          2.793500V         2.635700V            2.916900V
+5.2525ns          2.793500V         2.642300V            2.918100V
+5.4545ns          2.793500V         2.652700V            2.919300V
+5.6566ns          2.793400V         2.656300V            2.920400V
+5.8586ns          2.793400V         2.655900V            2.921400V
+6.0606ns          2.793300V         2.655100V            2.922500V
+6.2626ns          2.793200V         2.654600V            2.923500V
+6.4646ns          2.793100V         2.654000V            2.924400V
+6.6667ns          2.793000V         2.653400V            2.925300V
+6.8687ns          2.792900V         2.652800V            2.926200V
+7.0707ns          2.792800V         2.652200V            2.927100V
+7.2727ns          2.792700V         2.651700V            2.928000V
+7.4747ns          2.792600V         2.651100V            2.928900V
+7.6768ns          2.792500V         2.650500V            2.929700V
+7.8788ns          2.792300V         2.650000V            2.930600V
+8.0808ns          2.792200V         2.649500V            2.931500V
+8.2828ns          2.792100V         2.648900V            2.932300V
+8.4848ns          2.791900V         2.648400V            2.933200V
+8.6869ns          2.791800V         2.647900V            2.934100V
+8.8889ns          2.791600V         2.647400V            2.935000V
+9.0909ns          2.791500V         2.647000V            2.935800V
+9.2929ns          2.791300V         2.646500V            2.936600V
+9.4949ns          2.791200V         2.646000V            2.937400V
+9.6970ns          2.791000V         2.645600V            2.938200V
+9.8990ns          2.790900V         2.645100V            2.939000V
+10.1010ns         2.790650V         2.644500V            2.940050V
+10.3030ns         2.790400V         2.643900V            2.941100V
+10.5051ns         2.790200V         2.643500V            2.941700V
+10.7071ns         2.790100V         2.643100V            2.942400V
+10.9091ns         2.789900V         2.642700V            2.943000V
+11.1111ns         2.789700V         2.642400V            2.943600V
+11.3131ns         2.789600V         2.642000V            2.944100V
+11.5152ns         2.789400V         2.641600V            2.944700V
+11.7172ns         2.789200V         2.641300V            2.945200V
+11.9192ns         2.789100V         2.641000V            2.945700V
+12.1212ns         2.788900V         2.640600V            2.946200V
+12.3232ns         2.788700V         2.640300V            2.946700V
+12.5253ns         2.788600V         2.640000V            2.947100V
+12.7273ns         2.788400V         2.639700V            2.947600V
+12.9293ns         2.788200V         2.639400V            2.948000V
+13.1313ns         2.788000V         2.639100V            2.948400V
+13.3333ns         2.787900V         2.638900V            2.948800V
+13.5354ns         2.787700V         2.638600V            2.949200V
+13.7374ns         2.787500V         2.638300V            2.949600V
+13.9394ns         2.787400V         2.638000V            2.949900V
+14.1414ns         2.787200V         2.637800V            2.950300V
+14.3434ns         2.787000V         2.637500V            2.950600V
+14.5455ns         2.786900V         2.637300V            2.950900V
+14.7475ns         2.786700V         2.637100V            2.951200V
+14.9495ns         2.786500V         2.636800V            2.951500V
+15.1515ns         2.786400V         2.636600V            2.951800V
+15.3535ns         2.786200V         2.636400V            2.952100V
+15.5556ns         2.786100V         2.636100V            2.952400V
+15.7576ns         2.785900V         2.635900V            2.952600V
+15.9596ns         2.785800V         2.635700V            2.952900V
+16.1616ns         2.785600V         2.635500V            2.953100V
+16.3636ns         2.785500V         2.635300V            2.953400V
+16.5657ns         2.785300V         2.635100V            2.953600V
+16.7677ns         2.785200V         2.634900V            2.953800V
+16.9697ns         2.785000V         2.634700V            2.954000V
+17.1717ns         2.784900V         2.634500V            2.954200V
+17.3737ns         2.784800V         2.634300V            2.954400V
+17.5758ns         2.784600V         2.634200V            2.954600V
+17.7778ns         2.784500V         2.634000V            2.954800V
+17.9798ns         2.784400V         2.633800V            2.955000V
+18.1818ns         2.784300V         2.633600V            2.955100V
+18.3838ns         2.784200V         2.633500V            2.955300V
+18.5859ns         2.784100V         2.633300V            2.955500V
+18.7879ns         2.784000V         2.633100V            2.955600V
+18.9899ns         2.783900V         2.633000V            2.955800V
+19.1919ns         2.783800V         2.632800V            2.955900V
+19.3939ns         2.783700V         2.632700V            2.956100V
+19.5960ns         2.783600V         2.632500V            2.956200V
+19.7980ns         2.783600V         2.632400V            2.956300V
+20.0000ns         2.783500V         2.632200V            2.956500V
+|  
+| End [Model] lvc330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvc330s140aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -50.584550mA      -43.999960mA         -54.623576mA
+  -3.20    -50.404450mA      -43.837800mA         -54.427552mA
+  -3.10    -50.224350mA      -43.675640mA         -54.231528mA
+  -3.00    -50.044250mA      -43.513480mA         -54.035504mA
+  -2.90    -49.864150mA      -43.351320mA         -53.839480mA
+  -2.80    -49.684050mA      -43.189160mA         -53.643456mA
+  -2.70    -49.503950mA      -43.027000mA         -53.447432mA
+  -2.60    -49.323850mA      -42.864840mA         -53.251408mA
+  -2.50    -49.143750mA      -42.702680mA         -53.055384mA
+  -2.40    -48.963650mA      -42.540520mA         -52.859360mA
+  -2.30    -48.783550mA      -42.378360mA         -52.663336mA
+  -2.20    -48.603450mA      -42.216200mA         -52.467312mA
+  -2.10    -48.423350mA      -42.054040mA         -52.271288mA
+  -2.00    -48.243250mA      -41.891880mA         -52.075264mA
+  -1.90    -48.063150mA      -41.729720mA         -51.879240mA
+  -1.80    -47.883050mA      -41.567560mA         -51.683216mA
+  -1.70    -47.702950mA      -41.405400mA         -51.487192mA
+  -1.60    -47.522850mA      -41.243240mA         -51.291168mA
+  -1.50    -47.342750mA      -41.081080mA         -51.095144mA
+  -1.40    -47.162650mA      -40.960000mA         -50.899120mA
+  -1.30    -46.982550mA      -40.310000mA         -50.703096mA
+  -1.20    -46.802450mA      -39.409000mA         -50.507072mA
+  -1.10    -46.622350mA      -38.410000mA         -50.311048mA
+  -1.00    -46.442250mA      -37.323000mA         -50.115024mA
+  -0.90    -46.262150mA      -36.180000mA         -49.919000mA
+  -0.80    -46.082050mA      -35.076000mA         -49.327000mA
+  -0.70    -45.748900mA      -34.427000mA         -47.994000mA
+  -0.60    -42.249200mA      -34.203200mA         -45.776900mA
+  -0.50    -36.169470mA      -30.752860mA         -40.603750mA
+  -0.40    -29.014551mA      -24.879886mA         -32.919898mA
+  -0.30    -21.670346mA      -18.677585mA         -24.687602mA
+  -0.20    -14.338705mA      -12.435585mA         -16.367748mA
+  -0.10    -7.093292mA       -6.195266mA          -8.095791mA
+  0.00    27.190000nA       25.680000nA          31.680000nA
+  0.10    6.587285mA        5.878497mA           7.387890mA
+  0.20    12.314175mA       11.156186mA          13.529180mA
+  0.30    17.106166mA       15.766175mA          18.285171mA
+  0.40    20.907156mA       19.661164mA          21.673162mA
+  0.50    23.747146mA       22.813153mA          23.968152mA
+  0.60    25.783136mA       25.234142mA          25.549143mA
+  0.70    27.212126mA       27.008131mA          26.699134mA
+  0.80    28.206116mA       28.280120mA          27.588124mA
+  0.90    28.917106mA       29.203109mA          28.308115mA
+  1.00    29.453095mA       29.892098mA          28.908106mA
+  1.10    29.875084mA       30.426087mA          29.398096mA
+  1.20    30.221074mA       30.854076mA          29.770086mA
+  1.30    30.513063mA       31.208065mA          30.064075mA
+  1.40    30.767053mA       31.507054mA          30.315065mA
+  1.50    30.993042mA       31.766043mA          30.542055mA
+  1.60    31.203032mA       31.995032mA          30.762044mA
+  1.70    31.414021mA       32.204021mA          30.983034mA
+  1.80    31.648011mA       32.407010mA          31.201024mA
+  1.90    31.903000mA       32.633999mA          31.408013mA
+  2.00    32.157989mA       32.912988mA          31.601003mA
+  2.10    32.398979mA       33.235977mA          31.780993mA
+  2.20    32.620968mA       33.562966mA          31.951982mA
+  2.30    32.826958mA       33.870954mA          32.113972mA
+  2.40    33.017947mA       34.153943mA          32.268961mA
+  2.50    33.197936mA       34.411932mA          32.419951mA
+  2.60    33.368926mA       34.647921mA          32.567941mA
+  2.70    33.532915mA       34.866910mA          32.714930mA
+  2.80    33.693904mA       35.070899mA          32.864920mA
+  2.90    33.851894mA       35.264888mA          33.017909mA
+  3.00    34.012883mA       35.450877mA          33.177899mA
+  3.10    34.176872mA       35.632864mA          33.347889mA
+  3.20    34.349862mA       35.813747mA          33.531878mA
+  3.30    34.531848mA       35.996379mA          33.730868mA
+  3.40    34.729725mA       36.157497mA          33.951857mA
+  3.50    34.942986mA       36.297102mA          34.196843mA
+  3.60    35.117958mA       36.436708mA          34.470599mA
+  3.70    35.251602mA       36.576313mA          34.772212mA
+  3.80    35.385246mA       36.715919mA          34.904053mA
+  3.90    35.518890mA       36.855525mA          35.035893mA
+  4.00    35.652534mA       36.995130mA          35.167734mA
+  4.10    35.786178mA       37.134736mA          35.299574mA
+  4.20    35.919822mA       37.274341mA          35.431414mA
+  4.30    36.053466mA       37.413947mA          35.563255mA
+  4.40    36.187110mA       37.553553mA          35.695095mA
+  4.50    36.320754mA       37.693158mA          35.826936mA
+  4.60    36.454398mA       37.832764mA          35.958776mA
+  4.70    36.588042mA       37.972369mA          36.090616mA
+  4.80    36.721686mA       38.111975mA          36.222457mA
+  4.90    36.855330mA       38.251581mA          36.354297mA
+  5.00    36.988974mA       38.391186mA          36.486138mA
+  5.10    37.122618mA       38.530792mA          36.617978mA
+  5.20    37.256262mA       38.670397mA          36.749818mA
+  5.30    37.389906mA       38.810003mA          36.881659mA
+  5.40    37.523550mA       38.949609mA          37.013499mA
+  5.50    37.657194mA       39.089214mA          37.145340mA
+  5.60    37.790838mA       39.228820mA          37.277180mA
+  5.70    37.924482mA       39.368425mA          37.409020mA
+  5.80    38.058126mA       39.508031mA          37.540861mA
+  5.90    38.191770mA       39.647637mA          37.672701mA
+  6.00    38.325414mA       39.787242mA          37.804542mA
+  6.10    38.459058mA       39.926848mA          37.936382mA
+  6.20    38.592702mA       40.066453mA          38.068222mA
+  6.30    38.726346mA       40.206059mA          38.200063mA
+  6.40    38.859990mA       40.345665mA          38.331903mA
+  6.50    38.993634mA       40.485270mA          38.463744mA
+  6.60    39.127278mA       40.624876mA          38.595584mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    66.669757mA       87.094613mA          92.797733mA
+  -3.20    66.440741mA       86.767866mA          92.515330mA
+  -3.10    66.211726mA       86.441119mA          92.232928mA
+  -3.00    65.982711mA       86.114372mA          91.950525mA
+  -2.90    65.753695mA       85.787625mA          91.668122mA
+  -2.80    65.524680mA       85.460878mA          91.385720mA
+  -2.70    65.295664mA       85.134131mA          91.103317mA
+  -2.60    65.066649mA       84.807384mA          90.820915mA
+  -2.50    64.837633mA       84.480636mA          90.538512mA
+  -2.40    64.608618mA       84.153889mA          90.256109mA
+  -2.30    64.379602mA       83.827142mA          89.973707mA
+  -2.20    64.150587mA       83.500395mA          89.691304mA
+  -2.10    63.921571mA       83.173648mA          89.408901mA
+  -2.00    63.692556mA       82.846901mA          89.126499mA
+  -1.90    63.463540mA       82.520154mA          88.844096mA
+  -1.80    63.234525mA       82.323794mA          88.561693mA
+  -1.70    63.005509mA       81.008819mA          88.279291mA
+  -1.60    62.776494mA       78.640845mA          87.996888mA
+  -1.50    62.547479mA       75.568869mA          87.714485mA
+  -1.40    62.318463mA       71.978893mA          87.432083mA
+  -1.30    62.089448mA       67.983917mA          87.149680mA
+  -1.20    61.860432mA       63.658940mA          86.867278mA
+  -1.10    61.631417mA       59.058962mA          86.584875mA
+  -1.00    61.402401mA       54.225984mA          80.067686mA
+  -0.90    61.173386mA       49.192006mA          71.275712mA
+  -0.80    54.621889mA       45.212027mA          61.996736mA
+  -0.70    47.050911mA       41.794048mA          52.900760mA
+  -0.60    39.442932mA       35.550069mA          44.185783mA
+  -0.50    32.215954mA       29.164089mA          36.006805mA
+  -0.40    25.419974mA       23.007107mA          28.393828mA
+  -0.30    17.101700mA       15.824500mA          19.002300mA
+  -0.20    12.464986mA       11.277815mA          13.918820mA
+  -0.10    6.164125mA        5.580948mA           6.877969mA
+  0.00    -18.490000nA      -17.070000nA         -20.440000nA
+  0.10    -5.904938mA       -5.394928mA          -6.530140mA
+  0.20    -11.454128mA      -10.553116mA         -12.558129mA
+  0.30    -16.640117mA      -15.473105mA         -18.069119mA
+  0.40    -21.457106mA      -20.150094mA         -23.046108mA
+  0.50    -25.896096mA      -24.583083mA         -27.475098mA
+  0.60    -29.949085mA      -28.768072mA         -31.336087mA
+  0.70    -33.609074mA      -32.702061mA         -34.612077mA
+  0.80    -36.868064mA      -36.383050mA         -37.284067mA
+  0.90    -39.717053mA      -39.806039mA         -39.346056mA
+  1.00    -42.147042mA      -42.970028mA         -40.889046mA
+  1.10    -44.149032mA      -45.870017mA         -42.089035mA
+  1.20    -45.748021mA      -48.504006mA         -43.060025mA
+  1.30    -47.028011mA      -50.866995mA         -43.869015mA
+  1.40    -48.080000mA      -52.957984mA         -44.561004mA
+  1.50    -48.964989mA      -54.770973mA         -45.164994mA
+  1.60    -49.722979mA      -56.304962mA         -45.700984mA
+  1.70    -50.383968mA      -57.595951mA         -46.184973mA
+  1.80    -50.967958mA      -58.692940mA         -46.625963mA
+  1.90    -51.489947mA      -59.638929mA         -47.033952mA
+  2.00    -51.962937mA      -60.463918mA         -47.412942mA
+  2.10    -52.394926mA      -61.192907mA         -47.768932mA
+  2.20    -52.791916mA      -61.842896mA         -48.104921mA
+  2.30    -53.159905mA      -62.426885mA         -48.424911mA
+  2.40    -53.504894mA      -62.956874mA         -48.730901mA
+  2.50    -53.827884mA      -63.439863mA         -49.025891mA
+  2.60    -54.132874mA      -63.884852mA         -49.310882mA
+  2.70    -54.422864mA      -64.295841mA         -49.587873mA
+  2.80    -54.700854mA      -64.676830mA         -49.859863mA
+  2.90    -54.966844mA      -65.033819mA         -50.128854mA
+  3.00    -55.224834mA      -65.367808mA         -50.397845mA
+  3.10    -55.477825mA      -65.682796mA         -50.669835mA
+  3.20    -55.727815mA      -65.980780mA         -50.947826mA
+  3.30    -55.978806mA      -66.265706mA         -51.235817mA
+  3.40    -56.233792mA      -66.536956mA         -51.539808mA
+  3.50    -56.497705mA      -66.792873mA         -51.862798mA
+  3.60    -56.774346mA      -66.928560mA         -52.210786mA
+  3.70    -57.054551mA      -67.195337mA         -52.589679mA
+  3.80    -57.194470mA      -67.462113mA         -53.001555mA
+  3.90    -57.422477mA      -67.728890mA         -53.392977mA
+  4.00    -57.650484mA      -67.995667mA         -53.537857mA
+  4.10    -57.878491mA      -68.262444mA         -53.750052mA
+  4.20    -58.106498mA      -68.529220mA         -53.962246mA
+  4.30    -58.334506mA      -68.795997mA         -54.174441mA
+  4.40    -58.562513mA      -69.062774mA         -54.386636mA
+  4.50    -58.790520mA      -69.329550mA         -54.598830mA
+  4.60    -59.018527mA      -69.596327mA         -54.811025mA
+  4.70    -59.246534mA      -69.863104mA         -55.023219mA
+  4.80    -59.474541mA      -70.129881mA         -55.235414mA
+  4.90    -59.702548mA      -70.396657mA         -55.447608mA
+  5.00    -59.930555mA      -70.663434mA         -55.659803mA
+  5.10    -60.158563mA      -70.930211mA         -55.871997mA
+  5.20    -60.386570mA      -71.196988mA         -56.084192mA
+  5.30    -60.614577mA      -71.463764mA         -56.296387mA
+  5.40    -60.842584mA      -71.730541mA         -56.508581mA
+  5.50    -61.070591mA      -71.997318mA         -56.720776mA
+  5.60    -61.298598mA      -72.264094mA         -56.932970mA
+  5.70    -61.526605mA      -72.530871mA         -57.145165mA
+  5.80    -61.754612mA      -72.797648mA         -57.357359mA
+  5.90    -61.982620mA      -73.064425mA         -57.569554mA
+  6.00    -62.210627mA      -73.331201mA         -57.781748mA
+  6.10    -62.438634mA      -73.597978mA         -57.993943mA
+  6.20    -62.666641mA      -73.864755mA         -58.206138mA
+  6.30    -62.894648mA      -74.131531mA         -58.418332mA
+  6.40    -63.122655mA      -74.398308mA         -58.630527mA
+  6.50    -63.350662mA      -74.665085mA         -58.842721mA
+  6.55    -63.464666mA      -74.798473mA         -58.948819mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.195000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.064900nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  1.322279/1.397370n  1.285979/1.830494n  1.312139/1.075717n
+dV/dt_f  0.909660/0.907875n  0.826020/1.758264n  1.011840/0.527820n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.726300V         1.546200V            1.899700V
+0.2020ns          1.726800V         1.546200V            1.904800V
+0.4040ns          1.737400V         1.550000V            2.017500V
+0.6061ns          1.942100V         1.551600V            2.912500V
+0.8081ns          2.634400V         1.596800V            3.407200V
+1.0101ns          3.187200V         1.875300V            3.460800V
+1.2121ns          3.279100V         2.359700V            3.465800V
+1.4141ns          3.292700V         2.847800V            3.467100V
+1.6162ns          3.295600V         3.089900V            3.467600V
+1.8182ns          3.296700V         3.123600V            3.467900V
+2.0202ns          3.297300V         3.130900V            3.468200V
+2.2222ns          3.297500V         3.134300V            3.468700V
+2.4242ns          3.297700V         3.135700V            3.468900V
+2.6263ns          3.297900V         3.136600V            3.470800V
+2.8283ns          3.298100V         3.137000V            3.470300V
+3.0303ns          3.298400V         3.137300V            3.470100V
+3.2323ns          3.299000V         3.137500V            3.470000V
+3.4343ns          3.300800V         3.137600V            3.470000V
+3.6364ns          3.300800V         3.137800V            3.470000V
+3.8384ns          3.300300V         3.137900V            3.469900V
+4.0404ns          3.300200V         3.138000V            3.469900V
+4.2424ns          3.300000V         3.138200V            3.469900V
+4.4444ns          3.300000V         3.138400V            3.469900V
+4.6465ns          3.300000V         3.138600V            3.469900V
+4.8485ns          3.300000V         3.138900V            3.469900V
+5.0505ns          3.300000V         3.139200V            3.469900V
+5.2525ns          3.300000V         3.140400V            3.469900V
+5.4545ns          3.299900V         3.140300V            3.469900V
+5.6566ns          3.299900V         3.140100V            3.469900V
+5.8586ns          3.299900V         3.140100V            3.470000V
+6.0606ns          3.299900V         3.140000V            3.470000V
+6.2626ns          3.299900V         3.140000V            3.470000V
+6.4646ns          3.299900V         3.140000V            3.470000V
+6.6667ns          3.299900V         3.140000V            3.470000V
+6.8687ns          3.299900V         3.140000V            3.470000V
+7.0707ns          3.299900V         3.140000V            3.470000V
+7.2727ns          3.299900V         3.140000V            3.470000V
+7.4747ns          3.299900V         3.140000V            3.470000V
+7.6768ns          3.299900V         3.140000V            3.470000V
+7.8788ns          3.300000V         3.140000V            3.470000V
+8.0808ns          3.300000V         3.140000V            3.470000V
+8.2828ns          3.300000V         3.140000V            3.470000V
+8.4848ns          3.300000V         3.140000V            3.470000V
+8.6869ns          3.300000V         3.139900V            3.470000V
+8.8889ns          3.300000V         3.139900V            3.470000V
+9.0909ns          3.300000V         3.139900V            3.470000V
+9.2929ns          3.300000V         3.139900V            3.470000V
+9.4949ns          3.300000V         3.139900V            3.470000V
+9.6970ns          3.300000V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.140000V            3.470000V
+11.7172ns         3.300000V         3.140000V            3.470000V
+11.9192ns         3.300000V         3.140000V            3.470000V
+12.1212ns         3.300000V         3.140000V            3.470000V
+12.3232ns         3.300000V         3.140000V            3.470000V
+12.5253ns         3.300000V         3.140000V            3.470000V
+12.7273ns         3.300000V         3.140000V            3.470000V
+12.9293ns         3.300000V         3.140000V            3.470000V
+13.1313ns         3.300000V         3.140000V            3.470000V
+13.3333ns         3.300000V         3.140000V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.860000uV        2.247100uV           1.679700uV
+0.2020ns          -0.129790mV       4.669400uV           -0.320790mV
+0.4040ns          -1.716600mV       0.272540uV           -4.681500mV
+0.6061ns          1.221000mV        -0.447820mV          0.186680V
+0.8081ns          0.107030V         -5.196400mV          0.507800V
+1.0101ns          0.361420V         7.872900mV           0.782610V
+1.2121ns          0.574160V         63.086000mV          1.032400V
+1.4141ns          0.778920V         0.229510V            1.269500V
+1.6162ns          0.975680V         0.410340V            1.497800V
+1.8182ns          1.166800V         0.562960V            1.717900V
+2.0202ns          1.353800V         0.714380V            1.916400V
+2.2222ns          1.533600V         0.865340V            2.085800V
+2.4242ns          1.705400V         1.012700V            2.201900V
+2.6263ns          1.865600V         1.157800V            2.206500V
+2.8283ns          2.002800V         1.297100V            2.148000V
+3.0303ns          2.119800V         1.433900V            2.116300V
+3.2323ns          2.194200V         1.564200V            2.100900V
+3.4343ns          2.242600V         1.684200V            2.095200V
+3.6364ns          2.206600V         1.795900V            2.092100V
+3.8384ns          2.175600V         1.885300V            2.093400V
+4.0404ns          2.158100V         1.961700V            2.097900V
+4.2424ns          2.149800V         2.017100V            2.104000V
+4.4444ns          2.145000V         2.058100V            2.111400V
+4.6465ns          2.142500V         2.090000V            2.119600V
+4.8485ns          2.141700V         2.113000V            2.127800V
+5.0505ns          2.141900V         2.137500V            2.135200V
+5.2525ns          2.142800V         2.134100V            2.141000V
+5.4545ns          2.144700V         2.126700V            2.146000V
+5.6566ns          2.148900V         2.121500V            2.150700V
+5.8586ns          2.153600V         2.118100V            2.154700V
+6.0606ns          2.158200V         2.116400V            2.158400V
+6.2626ns          2.162900V         2.115100V            2.161600V
+6.4646ns          2.167200V         2.114600V            2.164500V
+6.6667ns          2.171000V         2.114400V            2.167000V
+6.8687ns          2.174500V         2.114500V            2.169300V
+7.0707ns          2.177500V         2.114600V            2.171300V
+7.2727ns          2.180300V         2.114800V            2.173100V
+7.4747ns          2.182800V         2.115200V            2.174700V
+7.6768ns          2.185100V         2.115600V            2.176100V
+7.8788ns          2.187100V         2.116000V            2.177400V
+8.0808ns          2.188900V         2.116500V            2.178500V
+8.2828ns          2.190500V         2.117100V            2.179500V
+8.4848ns          2.191900V         2.117700V            2.180300V
+8.6869ns          2.193200V         2.118500V            2.181100V
+8.8889ns          2.194300V         2.119600V            2.181800V
+9.0909ns          2.195300V         2.121000V            2.182400V
+9.2929ns          2.196300V         2.122600V            2.182900V
+9.4949ns          2.197100V         2.124200V            2.183400V
+9.6970ns          2.197800V         2.125900V            2.183800V
+9.8990ns          2.198500V         2.127400V            2.184200V
+10.1010ns         2.199350V         2.129450V            2.184650V
+10.3030ns         2.200000V         2.131300V            2.185000V
+10.5051ns         2.200500V         2.132300V            2.185200V
+10.7071ns         2.200800V         2.133300V            2.185400V
+10.9091ns         2.201200V         2.134200V            2.185600V
+11.1111ns         2.201500V         2.135100V            2.185800V
+11.3131ns         2.201700V         2.135800V            2.185900V
+11.5152ns         2.202000V         2.136500V            2.186000V
+11.7172ns         2.202200V         2.137100V            2.186100V
+11.9192ns         2.202400V         2.137700V            2.186200V
+12.1212ns         2.202500V         2.138200V            2.186300V
+12.3232ns         2.202700V         2.138700V            2.186400V
+12.5253ns         2.202800V         2.139100V            2.186400V
+12.7273ns         2.202900V         2.139500V            2.186500V
+12.9293ns         2.203000V         2.139900V            2.186500V
+13.1313ns         2.203100V         2.140200V            2.186600V
+13.3333ns         2.203200V         2.140500V            2.186600V
+13.5354ns         2.203300V         2.140700V            2.186600V
+13.7374ns         2.203300V         2.141000V            2.186700V
+13.9394ns         2.203400V         2.141200V            2.186700V
+14.1414ns         2.203400V         2.141400V            2.186700V
+14.3434ns         2.203500V         2.141600V            2.186700V
+14.5455ns         2.203500V         2.141800V            2.186700V
+14.7475ns         2.203600V         2.141900V            2.186800V
+14.9495ns         2.203600V         2.142000V            2.186800V
+15.1515ns         2.203600V         2.142200V            2.186800V
+15.3535ns         2.203600V         2.142300V            2.186800V
+15.5556ns         2.203700V         2.142400V            2.186800V
+15.7576ns         2.203700V         2.142500V            2.186800V
+15.9596ns         2.203700V         2.142600V            2.186800V
+16.1616ns         2.203700V         2.142600V            2.186800V
+16.3636ns         2.203700V         2.142700V            2.186800V
+16.5657ns         2.203700V         2.142800V            2.186900V
+16.7677ns         2.203700V         2.142800V            2.186900V
+16.9697ns         2.203800V         2.142900V            2.186900V
+17.1717ns         2.203800V         2.142900V            2.186900V
+17.3737ns         2.203800V         2.143000V            2.186900V
+17.5758ns         2.203800V         2.143000V            2.186900V
+17.7778ns         2.203800V         2.143000V            2.186900V
+17.9798ns         2.203800V         2.143100V            2.186900V
+18.1818ns         2.203800V         2.143100V            2.186900V
+18.3838ns         2.203800V         2.143100V            2.186900V
+18.5859ns         2.203800V         2.143100V            2.186900V
+18.7879ns         2.203800V         2.143200V            2.186900V
+18.9899ns         2.203800V         2.143200V            2.186900V
+19.1919ns         2.203800V         2.143200V            2.186900V
+19.3939ns         2.203800V         2.143200V            2.186900V
+19.5960ns         2.203800V         2.143200V            2.186900V
+19.7980ns         2.203800V         2.143200V            2.186900V
+20.0000ns         2.203800V         2.143300V            2.186900V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.203900V         2.143400V            2.187000V
+0.2020ns          2.204000V         2.143400V            2.193500V
+0.4040ns          2.222800V         2.147700V            2.032600V
+0.6061ns          2.041300V         2.152800V            1.329800V
+0.8081ns          1.561500V         2.146100V            0.689440V
+1.0101ns          1.011100V         2.097000V            0.210050V
+1.2121ns          0.595520V         1.931200V            16.668000mV
+1.4141ns          0.291310V         1.573700V            3.287100mV
+1.6162ns          80.606000mV       1.160800V            1.540100mV
+1.8182ns          13.976000mV       0.816650V            0.795800mV
+2.0202ns          3.438200mV        0.556260V            0.249100mV
+2.2222ns          2.674800mV        0.354310V            0.141130mV
+2.4242ns          1.686600mV        0.200190V            -0.655480mV
+2.6263ns          0.612530mV        87.872000mV          -2.068600uV
+2.8283ns          0.572400mV        33.061000mV          -22.091000uV
+3.0303ns          0.375060mV        11.834000mV          -24.867000uV
+3.2323ns          0.241800mV        4.814600mV           -26.956000uV
+3.4343ns          -0.105830mV       3.354200mV           -15.925000uV
+3.6364ns          -75.323000uV      2.452700mV           -21.116000uV
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+4.0404ns          -9.814400uV       1.397500mV           -20.735000uV
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+4.4444ns          -6.866100uV       0.872660mV           -19.920000uV
+4.6465ns          -5.387100uV       0.692450mV           -19.527000uV
+4.8485ns          -8.072400uV       0.289700mV           -19.137000uV
+5.0505ns          -7.958300uV       0.244360mV           -18.776000uV
+5.2525ns          -7.769600uV       -77.493000uV         -18.423000uV
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+6.6667ns          -6.644700uV       25.837000uV          -16.193000uV
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+7.0707ns          -6.356800uV       23.930000uV          -15.617000uV
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+7.6768ns          -5.973800uV       23.333000uV          -14.790000uV
+7.8788ns          -5.859500uV       22.861000uV          -14.523000uV
+8.0808ns          -5.751700uV       22.831000uV          -14.256000uV
+8.2828ns          -5.632300uV       22.765000uV          -14.004000uV
+8.4848ns          -5.509400uV       22.433000uV          -13.756000uV
+8.6869ns          -5.401200uV       22.127000uV          -13.508000uV
+8.8889ns          -5.297500uV       22.000000uV          -13.261000uV
+9.0909ns          -5.186800uV       21.856000uV          -13.026000uV
+9.2929ns          -5.073900uV       21.583000uV          -12.795000uV
+9.4949ns          -4.971400uV       21.321000uV          -12.566000uV
+9.6970ns          -4.872100uV       21.138000uV          -12.337000uV
+9.8990ns          -4.768700uV       20.948000uV          -12.119000uV
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+11.1111ns         -4.097100uV       19.385000uV          -10.679000uV
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+12.7273ns         -3.413900uV       17.750000uV          -9.242200uV
+12.9293ns         -3.334400uV       17.555000uV          -9.077700uV
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+14.9495ns         -2.604700uV       15.747000uV          -7.567200uV
+15.1515ns         -2.538000uV       15.582000uV          -7.428400uV
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+15.5556ns         -2.406900uV       15.254000uV          -7.161400uV
+15.7576ns         -2.343500uV       15.091000uV          -7.031000uV
+15.9596ns         -2.280700uV       14.928000uV          -6.901100uV
+16.1616ns         -2.219000uV       14.767000uV          -6.775700uV
+16.3636ns         -2.157500uV       14.614000uV          -6.651300uV
+16.5657ns         -2.097900uV       14.461000uV          -6.529200uV
+16.7677ns         -2.038900uV       14.310000uV          -6.407700uV
+16.9697ns         -1.980900uV       14.158000uV          -6.290200uV
+17.1717ns         -1.923100uV       14.007000uV          -6.173700uV
+17.3737ns         -1.867100uV       13.856000uV          -6.059300uV
+17.5758ns         -1.811500uV       13.715000uV          -5.945500uV
+17.7778ns         -1.756900uV       13.574000uV          -5.835400uV
+17.9798ns         -1.702700uV       13.433000uV          -5.726200uV
+18.1818ns         -1.649900uV       13.292000uV          -5.619000uV
+18.3838ns         -1.597600uV       13.151000uV          -5.512200uV
+18.5859ns         -1.546300uV       13.011000uV          -5.409000uV
+18.7879ns         -1.495300uV       12.881000uV          -5.306700uV
+18.9899ns         -1.445600uV       12.750000uV          -5.206100uV
+19.1919ns         -1.396400uV       12.619000uV          -5.105900uV
+19.3939ns         -1.348100uV       12.488000uV          -5.009100uV
+19.5960ns         -1.300200uV       12.357000uV          -4.913100uV
+19.7980ns         -1.253400uV       12.227000uV          -4.818400uV
+20.0000ns         -1.206900uV       12.109000uV          -4.724200uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468500V
+0.4040ns          3.300800V         3.139500V            3.480800V
+0.6061ns          3.307700V         3.140100V            3.421400V
+0.8081ns          3.288700V         3.143500V            3.119600V
+1.0101ns          3.205000V         3.143800V            2.661400V
+1.2121ns          3.025100V         3.145800V            2.287000V
+1.4141ns          2.763000V         3.126600V            2.008100V
+1.6162ns          2.525800V         3.091800V            1.804300V
+1.8182ns          2.335100V         3.031500V            1.669500V
+2.0202ns          2.176400V         2.950000V            1.556300V
+2.2222ns          2.038500V         2.833800V            1.492000V
+2.4242ns          1.931900V         2.695300V            1.454000V
+2.6263ns          1.842100V         2.569900V            1.511700V
+2.8283ns          1.775200V         2.465400V            1.518000V
+3.0303ns          1.725800V         2.375800V            1.523200V
+3.2323ns          1.686600V         2.288200V            1.528200V
+3.4343ns          1.685200V         2.209700V            1.533400V
+3.6364ns          1.704000V         2.138800V            1.538300V
+3.8384ns          1.711300V         2.070500V            1.543000V
+4.0404ns          1.712500V         2.009900V            1.547600V
+4.2424ns          1.714100V         1.956200V            1.552200V
+4.4444ns          1.715500V         1.910000V            1.556700V
+4.6465ns          1.717000V         1.869400V            1.561200V
+4.8485ns          1.718600V         1.839700V            1.565600V
+5.0505ns          1.719900V         1.823800V            1.569900V
+5.2525ns          1.721200V         1.826000V            1.574200V
+5.4545ns          1.722500V         1.835200V            1.578400V
+5.6566ns          1.723800V         1.841500V            1.582600V
+5.8586ns          1.725000V         1.842800V            1.586700V
+6.0606ns          1.726200V         1.841300V            1.590800V
+6.2626ns          1.727400V         1.839800V            1.594800V
+6.4646ns          1.728600V         1.838400V            1.598800V
+6.6667ns          1.729800V         1.837000V            1.602700V
+6.8687ns          1.730900V         1.835500V            1.606600V
+7.0707ns          1.732000V         1.834000V            1.610400V
+7.2727ns          1.733200V         1.832700V            1.614200V
+7.4747ns          1.734300V         1.831300V            1.618000V
+7.6768ns          1.735400V         1.829900V            1.621600V
+7.8788ns          1.736400V         1.828500V            1.625300V
+8.0808ns          1.737500V         1.827100V            1.628900V
+8.2828ns          1.738600V         1.825800V            1.632500V
+8.4848ns          1.739600V         1.824400V            1.636000V
+8.6869ns          1.740600V         1.823100V            1.639400V
+8.8889ns          1.741700V         1.821800V            1.642900V
+9.0909ns          1.742700V         1.820400V            1.646300V
+9.2929ns          1.743700V         1.819100V            1.649600V
+9.4949ns          1.744700V         1.817800V            1.652900V
+9.6970ns          1.745600V         1.816500V            1.656200V
+9.8990ns          1.746600V         1.815200V            1.659400V
+10.1010ns         1.748050V         1.813350V            1.664200V
+10.3030ns         1.749400V         1.811400V            1.668900V
+10.5051ns         1.750400V         1.810200V            1.672000V
+10.7071ns         1.751300V         1.809000V            1.675000V
+10.9091ns         1.752200V         1.807800V            1.678000V
+11.1111ns         1.753100V         1.806500V            1.681000V
+11.3131ns         1.753900V         1.805400V            1.684000V
+11.5152ns         1.754800V         1.804200V            1.686900V
+11.7172ns         1.755700V         1.803000V            1.689700V
+11.9192ns         1.756500V         1.801800V            1.692600V
+12.1212ns         1.757400V         1.800700V            1.695400V
+12.3232ns         1.758200V         1.799500V            1.698200V
+12.5253ns         1.759000V         1.798400V            1.700900V
+12.7273ns         1.759800V         1.797300V            1.703600V
+12.9293ns         1.760600V         1.796200V            1.706300V
+13.1313ns         1.761400V         1.795100V            1.709000V
+13.3333ns         1.762200V         1.794000V            1.711600V
+13.5354ns         1.763000V         1.792900V            1.714200V
+13.7374ns         1.763800V         1.791800V            1.716700V
+13.9394ns         1.764500V         1.790800V            1.719300V
+14.1414ns         1.765300V         1.789700V            1.721800V
+14.3434ns         1.766000V         1.788700V            1.724200V
+14.5455ns         1.766800V         1.787700V            1.726700V
+14.7475ns         1.767500V         1.786600V            1.729100V
+14.9495ns         1.768200V         1.785600V            1.731500V
+15.1515ns         1.768900V         1.784600V            1.733900V
+15.3535ns         1.769600V         1.783600V            1.736200V
+15.5556ns         1.770300V         1.782700V            1.738500V
+15.7576ns         1.771000V         1.781700V            1.740800V
+15.9596ns         1.771700V         1.780700V            1.743100V
+16.1616ns         1.772400V         1.779800V            1.745300V
+16.3636ns         1.773000V         1.778800V            1.747500V
+16.5657ns         1.773700V         1.777900V            1.749700V
+16.7677ns         1.774300V         1.777000V            1.751900V
+16.9697ns         1.775000V         1.776000V            1.754000V
+17.1717ns         1.775600V         1.775100V            1.756200V
+17.3737ns         1.776300V         1.774200V            1.758300V
+17.5758ns         1.776900V         1.773300V            1.760300V
+17.7778ns         1.777500V         1.772400V            1.762400V
+17.9798ns         1.778100V         1.771600V            1.764400V
+18.1818ns         1.778700V         1.770700V            1.766400V
+18.3838ns         1.779300V         1.769800V            1.768400V
+18.5859ns         1.779900V         1.769000V            1.770400V
+18.7879ns         1.780500V         1.768100V            1.772300V
+18.9899ns         1.781100V         1.767300V            1.774200V
+19.1919ns         1.781600V         1.766500V            1.776200V
+19.3939ns         1.782200V         1.765700V            1.778000V
+19.5960ns         1.782800V         1.764900V            1.779900V
+19.7980ns         1.783300V         1.764000V            1.781700V
+|20.0000ns         1.783900V         1.763300V            1.783600V
+40.0000ns         1.783900V         1.550000V            1.783600V
+|  
+| End [Model] lvc330s140aaaaaaaaio
+|************************************************************************
+| End [Component]
+[End]
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
index 411370a..ba33f77 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
@@ -1,75 +1,75 @@
-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Wed Aug 16 04:29:49 2023 *
-NOTE DESIGN NAME: RAM2GS *
-NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
-NOTE PIN ASSIGNMENTS *
-NOTE PINS RD[0] : 64 : inout *
-NOTE PINS Dout[0] : 1 : out *
-NOTE PINS PHI2 : 39 : in *
-NOTE PINS UFMSDO : 55 : in *
-NOTE PINS UFMSDI : 56 : out *
-NOTE PINS UFMCLK : 58 : out *
-NOTE PINS nUFMCS : 53 : out *
-NOTE PINS RDQML : 61 : out *
-NOTE PINS RDQMH : 76 : out *
-NOTE PINS nRCAS : 78 : out *
-NOTE PINS nRRAS : 73 : out *
-NOTE PINS nRWE : 72 : out *
-NOTE PINS RCKE : 82 : out *
-NOTE PINS RCLK : 86 : in *
-NOTE PINS nRCS : 77 : out *
-NOTE PINS RD[7] : 71 : inout *
-NOTE PINS RD[6] : 70 : inout *
-NOTE PINS RD[5] : 69 : inout *
-NOTE PINS RD[4] : 68 : inout *
-NOTE PINS RD[3] : 67 : inout *
-NOTE PINS RD[2] : 66 : inout *
-NOTE PINS RD[1] : 65 : inout *
-NOTE PINS RA[11] : 79 : out *
-NOTE PINS RA[10] : 87 : out *
-NOTE PINS RA[9] : 85 : out *
-NOTE PINS RA[8] : 96 : out *
-NOTE PINS RA[7] : 100 : out *
-NOTE PINS RA[6] : 91 : out *
-NOTE PINS RA[5] : 95 : out *
-NOTE PINS RA[4] : 99 : out *
-NOTE PINS RA[3] : 97 : out *
-NOTE PINS RA[2] : 94 : out *
-NOTE PINS RA[1] : 89 : out *
-NOTE PINS RA[0] : 98 : out *
-NOTE PINS RBA[1] : 83 : out *
-NOTE PINS RBA[0] : 63 : out *
-NOTE PINS LED : 57 : out *
-NOTE PINS nFWE : 22 : in *
-NOTE PINS nCRAS : 43 : in *
-NOTE PINS nCCAS : 27 : in *
-NOTE PINS Dout[7] : 3 : out *
-NOTE PINS Dout[6] : 2 : out *
-NOTE PINS Dout[5] : 5 : out *
-NOTE PINS Dout[4] : 4 : out *
-NOTE PINS Dout[3] : 6 : out *
-NOTE PINS Dout[2] : 8 : out *
-NOTE PINS Dout[1] : 7 : out *
-NOTE PINS Din[7] : 19 : in *
-NOTE PINS Din[6] : 20 : in *
-NOTE PINS Din[5] : 17 : in *
-NOTE PINS Din[4] : 18 : in *
-NOTE PINS Din[3] : 16 : in *
-NOTE PINS Din[2] : 14 : in *
-NOTE PINS Din[1] : 15 : in *
-NOTE PINS Din[0] : 21 : in *
-NOTE PINS CROW[1] : 34 : in *
-NOTE PINS CROW[0] : 32 : in *
-NOTE PINS MAin[9] : 51 : in *
-NOTE PINS MAin[8] : 50 : in *
-NOTE PINS MAin[7] : 44 : in *
-NOTE PINS MAin[6] : 49 : in *
-NOTE PINS MAin[5] : 45 : in *
-NOTE PINS MAin[4] : 46 : in *
-NOTE PINS MAin[3] : 47 : in *
-NOTE PINS MAin[2] : 37 : in *
-NOTE PINS MAin[1] : 38 : in *
-NOTE PINS MAin[0] : 23 : in *
-NOTE CONFIGURATION MODE: NONE *
-NOTE COMPRESSION: off *
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Sat Aug 19 20:53:35 2023 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[0] : 64 : inout *
+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS PHI2 : 39 : in *
+NOTE PINS UFMSDO : 55 : in *
+NOTE PINS UFMSDI : 56 : out *
+NOTE PINS UFMCLK : 58 : out *
+NOTE PINS nUFMCS : 53 : out *
+NOTE PINS RDQML : 61 : out *
+NOTE PINS RDQMH : 76 : out *
+NOTE PINS nRCAS : 78 : out *
+NOTE PINS nRRAS : 73 : out *
+NOTE PINS nRWE : 72 : out *
+NOTE PINS RCKE : 82 : out *
+NOTE PINS RCLK : 86 : in *
+NOTE PINS nRCS : 77 : out *
+NOTE PINS RD[7] : 71 : inout *
+NOTE PINS RD[6] : 70 : inout *
+NOTE PINS RD[5] : 69 : inout *
+NOTE PINS RD[4] : 68 : inout *
+NOTE PINS RD[3] : 67 : inout *
+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
+NOTE PINS RA[9] : 85 : out *
+NOTE PINS RA[8] : 96 : out *
+NOTE PINS RA[7] : 100 : out *
+NOTE PINS RA[6] : 91 : out *
+NOTE PINS RA[5] : 95 : out *
+NOTE PINS RA[4] : 99 : out *
+NOTE PINS RA[3] : 97 : out *
+NOTE PINS RA[2] : 94 : out *
+NOTE PINS RA[1] : 89 : out *
+NOTE PINS RA[0] : 98 : out *
+NOTE PINS RBA[1] : 83 : out *
+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS LED : 57 : out *
+NOTE PINS nFWE : 22 : in *
+NOTE PINS nCRAS : 43 : in *
+NOTE PINS nCCAS : 27 : in *
+NOTE PINS Dout[7] : 3 : out *
+NOTE PINS Dout[6] : 2 : out *
+NOTE PINS Dout[5] : 5 : out *
+NOTE PINS Dout[4] : 4 : out *
+NOTE PINS Dout[3] : 6 : out *
+NOTE PINS Dout[2] : 8 : out *
+NOTE PINS Dout[1] : 7 : out *
+NOTE PINS Din[7] : 19 : in *
+NOTE PINS Din[6] : 20 : in *
+NOTE PINS Din[5] : 17 : in *
+NOTE PINS Din[4] : 18 : in *
+NOTE PINS Din[3] : 16 : in *
+NOTE PINS Din[2] : 14 : in *
+NOTE PINS Din[1] : 15 : in *
+NOTE PINS Din[0] : 21 : in *
+NOTE PINS CROW[1] : 34 : in *
+NOTE PINS CROW[0] : 32 : in *
+NOTE PINS MAin[9] : 51 : in *
+NOTE PINS MAin[8] : 50 : in *
+NOTE PINS MAin[7] : 44 : in *
+NOTE PINS MAin[6] : 49 : in *
+NOTE PINS MAin[5] : 45 : in *
+NOTE PINS MAin[4] : 46 : in *
+NOTE PINS MAin[3] : 47 : in *
+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr
index b029ec5..2a05ec7 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr
@@ -1,26 +1,26 @@
-----------------------------------------------------------------------
-Report for cell RAM2GS.verilog
-
-Register bits: 92 of 256 (36%)
-PIC Latch:       0
-I/O cells:       67
-                                          Cell usage:
-                               cell       count    Res Usage(%)
-                                 BB        8       100.0
-                               CCU2        9       100.0
-                            FD1P3AX       11       100.0
-                            FD1S3AX       59       100.0
-                            FD1S3AY        5       100.0
-                            FD1S3IX       14       100.0
-                            FD1S3JX        3       100.0
-                                GSR        1       100.0
-                                 IB       26       100.0
-                                INV        8       100.0
-                                 OB       33       100.0
-                           ORCALUT4      119       100.0
-                              PFUMX        2       100.0
-                                PUR        1       100.0
-                                VHI        1       100.0
-                                VLO        1       100.0
-                            
-                         TOTAL           301           
+----------------------------------------------------------------------
+Report for cell RAM2GS.verilog
+
+Register bits: 92 of 256 (36%)
+PIC Latch:       0
+I/O cells:       67
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                 BB        8       100.0
+                               CCU2        9       100.0
+                            FD1P3AX       11       100.0
+                            FD1S3AX       59       100.0
+                            FD1S3AY        5       100.0
+                            FD1S3IX       14       100.0
+                            FD1S3JX        3       100.0
+                                GSR        1       100.0
+                                 IB       26       100.0
+                                INV        8       100.0
+                                 OB       33       100.0
+                           ORCALUT4      119       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL           301           
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
index b8a5f22..ead4687 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
@@ -1,45 +1,45 @@
-BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:29:49 2023
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:53:34 2023
+
 
-
-Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
-
-Preference Summary:
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 44 MB
+Command: bitgen -w -g ES:No -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 65 MB
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit
index da1601a71ed94f6eb5aa8a6d8e483f4379bb4911..b957591132c812e8a898ba36a2e7ff1fbd3d9ead 100644
GIT binary patch
delta 31
mcmeD5==7MdT_iZMM8Q#^G+n{aQo+c;%GB7(*mUD*J7oZ+GzqW(

delta 31
mcmeD5==7MdT_ij;MZr;_G+n{aOu@j!%E;2n#B$?lJ7oZ*sR^$D

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd
index f58180a12831f24a2a0570336c37a2c7aa55e3eb..786ae1eee91ce499981789fd2474b219fb536f6b 100644
GIT binary patch
delta 40
wcmdnj#JR7DbAkx-!{q-P#UDwq)%Z;?*4LlRDCy8_FWGJ{$++EKlIg!X06oAC4*&oF

delta 40
wcmdnj#JR7DbAkx-o!B@uCG6tQPQE=Ub5X@l5xAeB-4L&09UyWQ2+n{

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
index 15579af..18517f3 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
@@ -1,271 +1,271 @@
-PAD Specification File
-***************************
-
-PART TYPE:        LCMXO256C
-Performance Grade:      3
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.19
-
-Wed Aug 16 04:50:47 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+------+----------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site | Properties                       |
-+-----------+----------+---------------+------+----------------------------------+
-| CROW[0]   | 32/1     | LVCMOS33_IN   | PB2C | SLEW:FAST PULL:KEEPER            |
-| CROW[1]   | 34/1     | LVCMOS33_IN   | PB2D | SLEW:FAST PULL:KEEPER            |
-| Din[0]    | 21/1     | LVCMOS33_IN   | PL8A | SLEW:FAST PULL:KEEPER            |
-| Din[1]    | 15/1     | LVCMOS33_IN   | PL6A | SLEW:FAST PULL:KEEPER            |
-| Din[2]    | 14/1     | LVCMOS33_IN   | PL5D | SLEW:FAST PULL:KEEPER            |
-| Din[3]    | 16/1     | LVCMOS33_IN   | PL6B | SLEW:FAST PULL:KEEPER            |
-| Din[4]    | 18/1     | LVCMOS33_IN   | PL7B | SLEW:FAST PULL:KEEPER            |
-| Din[5]    | 17/1     | LVCMOS33_IN   | PL7A | SLEW:FAST PULL:KEEPER            |
-| Din[6]    | 20/1     | LVCMOS33_IN   | PL7D | SLEW:FAST PULL:KEEPER            |
-| Din[7]    | 19/1     | LVCMOS33_IN   | PL7C | SLEW:FAST PULL:KEEPER            |
-| Dout[0]   | 1/1      | LVCMOS33_OUT  | PL2A | DRIVE:4mA SLEW:FAST              |
-| Dout[1]   | 7/1      | LVCMOS33_OUT  | PL4A | DRIVE:4mA SLEW:FAST              |
-| Dout[2]   | 8/1      | LVCMOS33_OUT  | PL4B | DRIVE:4mA SLEW:FAST              |
-| Dout[3]   | 6/1      | LVCMOS33_OUT  | PL3D | DRIVE:4mA SLEW:FAST              |
-| Dout[4]   | 4/1      | LVCMOS33_OUT  | PL3B | DRIVE:4mA SLEW:FAST              |
-| Dout[5]   | 5/1      | LVCMOS33_OUT  | PL3C | DRIVE:4mA SLEW:FAST              |
-| Dout[6]   | 2/1      | LVCMOS33_OUT  | PL2B | DRIVE:4mA SLEW:FAST              |
-| Dout[7]   | 3/1      | LVCMOS33_OUT  | PL3A | DRIVE:4mA SLEW:FAST              |
-| LED       | 57/0     | LVCMOS33_OUT  | PR7B | DRIVE:14mA SLEW:SLOW             |
-| MAin[0]   | 23/1     | LVCMOS33_IN   | PL9A | SLEW:FAST PULL:KEEPER            |
-| MAin[1]   | 38/1     | LVCMOS33_IN   | PB3C | SLEW:FAST PULL:KEEPER            |
-| MAin[2]   | 37/1     | LVCMOS33_IN   | PB3B | SLEW:FAST PULL:KEEPER            |
-| MAin[3]   | 47/1     | LVCMOS33_IN   | PB5A | SLEW:FAST PULL:KEEPER            |
-| MAin[4]   | 46/1     | LVCMOS33_IN   | PB4D | SLEW:FAST PULL:KEEPER            |
-| MAin[5]   | 45/1     | LVCMOS33_IN   | PB4C | SLEW:FAST PULL:KEEPER            |
-| MAin[6]   | 49/1     | LVCMOS33_IN   | PB5C | SLEW:FAST PULL:KEEPER            |
-| MAin[7]   | 44/1     | LVCMOS33_IN   | PB4B | SLEW:FAST PULL:KEEPER            |
-| MAin[8]   | 50/1     | LVCMOS33_IN   | PB5D | SLEW:FAST PULL:KEEPER            |
-| MAin[9]   | 51/0     | LVCMOS33_IN   | PR9B | SLEW:FAST PULL:KEEPER            |
-| PHI2      | 39/1     | LVCMOS33_IN   | PB3D | SLEW:FAST PULL:DOWN              |
-| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2C | DRIVE:4mA SLEW:SLOW              |
-| RA[10]    | 87/0     | LVCMOS33_OUT  | PT3D | DRIVE:4mA SLEW:SLOW              |
-| RA[11]    | 79/0     | LVCMOS33_OUT  | PT5A | DRIVE:4mA SLEW:SLOW              |
-| RA[1]     | 89/0     | LVCMOS33_OUT  | PT3C | DRIVE:4mA SLEW:SLOW              |
-| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3A | DRIVE:4mA SLEW:SLOW              |
-| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2D | DRIVE:4mA SLEW:SLOW              |
-| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2B | DRIVE:4mA SLEW:SLOW              |
-| RA[5]     | 95/0     | LVCMOS33_OUT  | PT2F | DRIVE:4mA SLEW:SLOW              |
-| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3B | DRIVE:4mA SLEW:SLOW              |
-| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A | DRIVE:4mA SLEW:SLOW              |
-| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2E | DRIVE:4mA SLEW:SLOW              |
-| RA[9]     | 85/0     | LVCMOS33_OUT  | PT4B | DRIVE:4mA SLEW:SLOW              |
-| RBA[0]    | 63/0     | LVCMOS33_OUT  | PR5D | DRIVE:4mA SLEW:SLOW              |
-| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT4C | DRIVE:4mA SLEW:SLOW              |
-| RCKE      | 82/0     | LVCMOS33_OUT  | PT4D | DRIVE:4mA SLEW:SLOW              |
-| RCLK      | 86/0     | LVCMOS33_IN   | PT4A | SLEW:FAST PULL:KEEPER            |
-| RDQMH     | 76/0     | LVCMOS33_OUT  | PR2A | DRIVE:4mA SLEW:SLOW              |
-| RDQML     | 61/0     | LVCMOS33_OUT  | PR6A | DRIVE:4mA SLEW:SLOW              |
-| RD[0]     | 64/0     | LVCMOS33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[1]     | 65/0     | LVCMOS33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[2]     | 66/0     | LVCMOS33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[3]     | 67/0     | LVCMOS33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[4]     | 68/0     | LVCMOS33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[5]     | 69/0     | LVCMOS33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[6]     | 70/0     | LVCMOS33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[7]     | 71/0     | LVCMOS33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| UFMCLK    | 58/0     | LVCMOS33_OUT  | PR7A | DRIVE:4mA SLEW:SLOW              |
-| UFMSDI    | 56/0     | LVCMOS33_OUT  | PR7C | DRIVE:4mA SLEW:SLOW              |
-| UFMSDO    | 55/0     | LVCMOS33_IN   | PR7D | SLEW:FAST PULL:KEEPER            |
-| nCCAS     | 27/1     | LVCMOS33_IN   | PL9B | SLEW:FAST PULL:UP                |
-| nCRAS     | 43/1     | LVCMOS33_IN   | PB4A | SLEW:FAST PULL:UP                |
-| nFWE      | 22/1     | LVCMOS33_IN   | PL8B | SLEW:FAST PULL:KEEPER            |
-| nRCAS     | 78/0     | LVCMOS33_OUT  | PT5B | DRIVE:4mA SLEW:SLOW              |
-| nRCS      | 77/0     | LVCMOS33_OUT  | PT5C | DRIVE:4mA SLEW:SLOW              |
-| nRRAS     | 73/0     | LVCMOS33_OUT  | PR2B | DRIVE:4mA SLEW:SLOW              |
-| nRWE      | 72/0     | LVCMOS33_OUT  | PR3A | DRIVE:4mA SLEW:SLOW              |
-| nUFMCS    | 53/0     | LVCMOS33_OUT  | PR8B | DRIVE:4mA SLEW:SLOW              |
-+-----------+----------+---------------+------+----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-+------+-------+
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+---------------------+------------+---------------+------+---------------+
-| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site | Dual Function |
-+----------+---------------------+------------+---------------+------+---------------+
-| 1/1      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A |               |
-| 2/1      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2B |               |
-| 3/1      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL3A |               |
-| 4/1      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL3B |               |
-| 5/1      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3C |               |
-| 6/1      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3D |               |
-| 7/1      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL4A |               |
-| 8/1      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL4B |               |
-| 9/1      |     unused, PULL:UP |            |               | PL5A |               |
-| 11/1     |     unused, PULL:UP |            |               | PL5B |               |
-| 13/1     |     unused, PULL:UP |            |               | PL5C |               |
-| 14/1     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5D | GSR_PADN      |
-| 15/1     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL6A |               |
-| 16/1     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL6B | TSALLPAD      |
-| 17/1     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL7A |               |
-| 18/1     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL7B |               |
-| 19/1     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL7C |               |
-| 20/1     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL7D |               |
-| 21/1     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL8A |               |
-| 22/1     | nFWE                | LOCATED    | LVCMOS33_IN   | PL8B |               |
-| 23/1     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL9A |               |
-| 27/1     | nCCAS               | LOCATED    | LVCMOS33_IN   | PL9B |               |
-| 29/1     |     unused, PULL:UP |            |               | PB2A |               |
-| 30/1     |     unused, PULL:UP |            |               | PB2B |               |
-| 32/1     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB2C |               |
-| 34/1     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB2D |               |
-| 36/1     |     unused, PULL:UP |            |               | PB3A | PCLKT1_1      |
-| 37/1     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB3B |               |
-| 38/1     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB3C | PCLKT1_0      |
-| 39/1     | PHI2                | LOCATED    | LVCMOS33_IN   | PB3D |               |
-| 43/1     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB4A |               |
-| 44/1     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB4B |               |
-| 45/1     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB4C |               |
-| 46/1     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB4D |               |
-| 47/1     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB5A |               |
-| 49/1     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB5C |               |
-| 50/1     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB5D |               |
-| 51/0     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR9B |               |
-| 52/0     |     unused, PULL:UP |            |               | PR9A |               |
-| 53/0     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR8B |               |
-| 54/0     |     unused, PULL:UP |            |               | PR8A |               |
-| 55/0     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR7D |               |
-| 56/0     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR7C |               |
-| 57/0     | LED                 | LOCATED    | LVCMOS33_OUT  | PR7B |               |
-| 58/0     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR7A |               |
-| 59/0     |     unused, PULL:UP |            |               | PR6B |               |
-| 61/0     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR6A |               |
-| 63/0     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR5D |               |
-| 64/0     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR5C |               |
-| 65/0     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR5B |               |
-| 66/0     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5A |               |
-| 67/0     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR4B |               |
-| 68/0     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4A |               |
-| 69/0     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR3D |               |
-| 70/0     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3C |               |
-| 71/0     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B |               |
-| 72/0     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR3A |               |
-| 73/0     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B |               |
-| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PR2A |               |
-| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT5C |               |
-| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT5B |               |
-| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT5A |               |
-| 80/0     |     unused, PULL:UP |            |               | PT4F |               |
-| 81/0     |     unused, PULL:UP |            |               | PT4E |               |
-| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT4D |               |
-| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT4C |               |
-| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT4B | PCLKT0_1      |
-| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT4A | PCLKT0_0      |
-| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT3D |               |
-| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT3C |               |
-| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3B |               |
-| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3A |               |
-| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT2F |               |
-| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2E |               |
-| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2D |               |
-| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2C |               |
-| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2B |               |
-| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A |               |
-| PB5B/0   |     unused, PULL:UP |            |               | PB5B |               |
-| PT5D/0   |     unused, PULL:UP |            |               | PT5D |               |
-| TCK/1    |                     |            |               | TCK  | TCK           |
-| TDI/1    |                     |            |               | TDI  | TDI           |
-| TDO/1    |                     |            |               | TDO  | TDO           |
-| TMS/1    |                     |            |               | TMS  | TMS           |
-+----------+---------------------+------------+---------------+------+---------------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "32";
-LOCATE  COMP  "CROW[1]"  SITE  "34";
-LOCATE  COMP  "Din[0]"  SITE  "21";
-LOCATE  COMP  "Din[1]"  SITE  "15";
-LOCATE  COMP  "Din[2]"  SITE  "14";
-LOCATE  COMP  "Din[3]"  SITE  "16";
-LOCATE  COMP  "Din[4]"  SITE  "18";
-LOCATE  COMP  "Din[5]"  SITE  "17";
-LOCATE  COMP  "Din[6]"  SITE  "20";
-LOCATE  COMP  "Din[7]"  SITE  "19";
-LOCATE  COMP  "Dout[0]"  SITE  "1";
-LOCATE  COMP  "Dout[1]"  SITE  "7";
-LOCATE  COMP  "Dout[2]"  SITE  "8";
-LOCATE  COMP  "Dout[3]"  SITE  "6";
-LOCATE  COMP  "Dout[4]"  SITE  "4";
-LOCATE  COMP  "Dout[5]"  SITE  "5";
-LOCATE  COMP  "Dout[6]"  SITE  "2";
-LOCATE  COMP  "Dout[7]"  SITE  "3";
-LOCATE  COMP  "LED"  SITE  "57";
-LOCATE  COMP  "MAin[0]"  SITE  "23";
-LOCATE  COMP  "MAin[1]"  SITE  "38";
-LOCATE  COMP  "MAin[2]"  SITE  "37";
-LOCATE  COMP  "MAin[3]"  SITE  "47";
-LOCATE  COMP  "MAin[4]"  SITE  "46";
-LOCATE  COMP  "MAin[5]"  SITE  "45";
-LOCATE  COMP  "MAin[6]"  SITE  "49";
-LOCATE  COMP  "MAin[7]"  SITE  "44";
-LOCATE  COMP  "MAin[8]"  SITE  "50";
-LOCATE  COMP  "MAin[9]"  SITE  "51";
-LOCATE  COMP  "PHI2"  SITE  "39";
-LOCATE  COMP  "RA[0]"  SITE  "98";
-LOCATE  COMP  "RA[10]"  SITE  "87";
-LOCATE  COMP  "RA[11]"  SITE  "79";
-LOCATE  COMP  "RA[1]"  SITE  "89";
-LOCATE  COMP  "RA[2]"  SITE  "94";
-LOCATE  COMP  "RA[3]"  SITE  "97";
-LOCATE  COMP  "RA[4]"  SITE  "99";
-LOCATE  COMP  "RA[5]"  SITE  "95";
-LOCATE  COMP  "RA[6]"  SITE  "91";
-LOCATE  COMP  "RA[7]"  SITE  "100";
-LOCATE  COMP  "RA[8]"  SITE  "96";
-LOCATE  COMP  "RA[9]"  SITE  "85";
-LOCATE  COMP  "RBA[0]"  SITE  "63";
-LOCATE  COMP  "RBA[1]"  SITE  "83";
-LOCATE  COMP  "RCKE"  SITE  "82";
-LOCATE  COMP  "RCLK"  SITE  "86";
-LOCATE  COMP  "RDQMH"  SITE  "76";
-LOCATE  COMP  "RDQML"  SITE  "61";
-LOCATE  COMP  "RD[0]"  SITE  "64";
-LOCATE  COMP  "RD[1]"  SITE  "65";
-LOCATE  COMP  "RD[2]"  SITE  "66";
-LOCATE  COMP  "RD[3]"  SITE  "67";
-LOCATE  COMP  "RD[4]"  SITE  "68";
-LOCATE  COMP  "RD[5]"  SITE  "69";
-LOCATE  COMP  "RD[6]"  SITE  "70";
-LOCATE  COMP  "RD[7]"  SITE  "71";
-LOCATE  COMP  "UFMCLK"  SITE  "58";
-LOCATE  COMP  "UFMSDI"  SITE  "56";
-LOCATE  COMP  "UFMSDO"  SITE  "55";
-LOCATE  COMP  "nCCAS"  SITE  "27";
-LOCATE  COMP  "nCRAS"  SITE  "43";
-LOCATE  COMP  "nFWE"  SITE  "22";
-LOCATE  COMP  "nRCAS"  SITE  "78";
-LOCATE  COMP  "nRCS"  SITE  "77";
-LOCATE  COMP  "nRRAS"  SITE  "73";
-LOCATE  COMP  "nRWE"  SITE  "72";
-LOCATE  COMP  "nUFMCS"  SITE  "53";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:47 2023
-
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO256C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.19
+
+Sat Aug 19 20:53:29 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site | Properties                       |
++-----------+----------+---------------+------+----------------------------------+
+| CROW[0]   | 32/1     | LVCMOS33_IN   | PB2C | SLEW:FAST PULL:KEEPER            |
+| CROW[1]   | 34/1     | LVCMOS33_IN   | PB2D | SLEW:FAST PULL:KEEPER            |
+| Din[0]    | 21/1     | LVCMOS33_IN   | PL8A | SLEW:FAST PULL:KEEPER            |
+| Din[1]    | 15/1     | LVCMOS33_IN   | PL6A | SLEW:FAST PULL:KEEPER            |
+| Din[2]    | 14/1     | LVCMOS33_IN   | PL5D | SLEW:FAST PULL:KEEPER            |
+| Din[3]    | 16/1     | LVCMOS33_IN   | PL6B | SLEW:FAST PULL:KEEPER            |
+| Din[4]    | 18/1     | LVCMOS33_IN   | PL7B | SLEW:FAST PULL:KEEPER            |
+| Din[5]    | 17/1     | LVCMOS33_IN   | PL7A | SLEW:FAST PULL:KEEPER            |
+| Din[6]    | 20/1     | LVCMOS33_IN   | PL7D | SLEW:FAST PULL:KEEPER            |
+| Din[7]    | 19/1     | LVCMOS33_IN   | PL7C | SLEW:FAST PULL:KEEPER            |
+| Dout[0]   | 1/1      | LVCMOS33_OUT  | PL2A | DRIVE:4mA SLEW:FAST              |
+| Dout[1]   | 7/1      | LVCMOS33_OUT  | PL4A | DRIVE:4mA SLEW:FAST              |
+| Dout[2]   | 8/1      | LVCMOS33_OUT  | PL4B | DRIVE:4mA SLEW:FAST              |
+| Dout[3]   | 6/1      | LVCMOS33_OUT  | PL3D | DRIVE:4mA SLEW:FAST              |
+| Dout[4]   | 4/1      | LVCMOS33_OUT  | PL3B | DRIVE:4mA SLEW:FAST              |
+| Dout[5]   | 5/1      | LVCMOS33_OUT  | PL3C | DRIVE:4mA SLEW:FAST              |
+| Dout[6]   | 2/1      | LVCMOS33_OUT  | PL2B | DRIVE:4mA SLEW:FAST              |
+| Dout[7]   | 3/1      | LVCMOS33_OUT  | PL3A | DRIVE:4mA SLEW:FAST              |
+| LED       | 57/0     | LVCMOS33_OUT  | PR7B | DRIVE:14mA SLEW:SLOW             |
+| MAin[0]   | 23/1     | LVCMOS33_IN   | PL9A | SLEW:FAST PULL:KEEPER            |
+| MAin[1]   | 38/1     | LVCMOS33_IN   | PB3C | SLEW:FAST PULL:KEEPER            |
+| MAin[2]   | 37/1     | LVCMOS33_IN   | PB3B | SLEW:FAST PULL:KEEPER            |
+| MAin[3]   | 47/1     | LVCMOS33_IN   | PB5A | SLEW:FAST PULL:KEEPER            |
+| MAin[4]   | 46/1     | LVCMOS33_IN   | PB4D | SLEW:FAST PULL:KEEPER            |
+| MAin[5]   | 45/1     | LVCMOS33_IN   | PB4C | SLEW:FAST PULL:KEEPER            |
+| MAin[6]   | 49/1     | LVCMOS33_IN   | PB5C | SLEW:FAST PULL:KEEPER            |
+| MAin[7]   | 44/1     | LVCMOS33_IN   | PB4B | SLEW:FAST PULL:KEEPER            |
+| MAin[8]   | 50/1     | LVCMOS33_IN   | PB5D | SLEW:FAST PULL:KEEPER            |
+| MAin[9]   | 51/0     | LVCMOS33_IN   | PR9B | SLEW:FAST PULL:KEEPER            |
+| PHI2      | 39/1     | LVCMOS33_IN   | PB3D | SLEW:FAST PULL:DOWN              |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2C | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT3D | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT5A | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT3C | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3A | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2D | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2B | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT2F | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3B | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2E | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT4B | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/0     | LVCMOS33_OUT  | PR5D | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT4C | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT4D | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT4A | SLEW:FAST PULL:KEEPER            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PR2A | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/0     | LVCMOS33_OUT  | PR6A | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/0     | LVCMOS33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/0     | LVCMOS33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/0     | LVCMOS33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/0     | LVCMOS33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/0     | LVCMOS33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/0     | LVCMOS33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/0     | LVCMOS33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/0     | LVCMOS33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/0     | LVCMOS33_OUT  | PR7A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/0     | LVCMOS33_OUT  | PR7C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/0     | LVCMOS33_IN   | PR7D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/1     | LVCMOS33_IN   | PL9B | SLEW:FAST PULL:UP                |
+| nCRAS     | 43/1     | LVCMOS33_IN   | PB4A | SLEW:FAST PULL:UP                |
+| nFWE      | 22/1     | LVCMOS33_IN   | PL8B | SLEW:FAST PULL:KEEPER            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT5B | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT5C | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/0     | LVCMOS33_OUT  | PR2B | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/0     | LVCMOS33_OUT  | PR3A | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/0     | LVCMOS33_OUT  | PR8B | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+---------------+------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site | Dual Function |
++----------+---------------------+------------+---------------+------+---------------+
+| 1/1      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A |               |
+| 2/1      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2B |               |
+| 3/1      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL3A |               |
+| 4/1      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL3B |               |
+| 5/1      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3C |               |
+| 6/1      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3D |               |
+| 7/1      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL4A |               |
+| 8/1      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL4B |               |
+| 9/1      |     unused, PULL:UP |            |               | PL5A |               |
+| 11/1     |     unused, PULL:UP |            |               | PL5B |               |
+| 13/1     |     unused, PULL:UP |            |               | PL5C |               |
+| 14/1     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5D | GSR_PADN      |
+| 15/1     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL6A |               |
+| 16/1     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL6B | TSALLPAD      |
+| 17/1     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL7A |               |
+| 18/1     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL7B |               |
+| 19/1     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL7C |               |
+| 20/1     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL7D |               |
+| 21/1     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL8A |               |
+| 22/1     | nFWE                | LOCATED    | LVCMOS33_IN   | PL8B |               |
+| 23/1     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL9A |               |
+| 27/1     | nCCAS               | LOCATED    | LVCMOS33_IN   | PL9B |               |
+| 29/1     |     unused, PULL:UP |            |               | PB2A |               |
+| 30/1     |     unused, PULL:UP |            |               | PB2B |               |
+| 32/1     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB2C |               |
+| 34/1     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB2D |               |
+| 36/1     |     unused, PULL:UP |            |               | PB3A | PCLKT1_1      |
+| 37/1     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB3B |               |
+| 38/1     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB3C | PCLKT1_0      |
+| 39/1     | PHI2                | LOCATED    | LVCMOS33_IN   | PB3D |               |
+| 43/1     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB4A |               |
+| 44/1     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB4B |               |
+| 45/1     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB4C |               |
+| 46/1     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB4D |               |
+| 47/1     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB5A |               |
+| 49/1     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB5C |               |
+| 50/1     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB5D |               |
+| 51/0     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR9B |               |
+| 52/0     |     unused, PULL:UP |            |               | PR9A |               |
+| 53/0     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR8B |               |
+| 54/0     |     unused, PULL:UP |            |               | PR8A |               |
+| 55/0     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR7D |               |
+| 56/0     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR7C |               |
+| 57/0     | LED                 | LOCATED    | LVCMOS33_OUT  | PR7B |               |
+| 58/0     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR7A |               |
+| 59/0     |     unused, PULL:UP |            |               | PR6B |               |
+| 61/0     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR6A |               |
+| 63/0     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR5D |               |
+| 64/0     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR5C |               |
+| 65/0     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR5B |               |
+| 66/0     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5A |               |
+| 67/0     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR4B |               |
+| 68/0     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4A |               |
+| 69/0     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR3D |               |
+| 70/0     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3C |               |
+| 71/0     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B |               |
+| 72/0     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR3A |               |
+| 73/0     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PR2A |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT5C |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT5B |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT5A |               |
+| 80/0     |     unused, PULL:UP |            |               | PT4F |               |
+| 81/0     |     unused, PULL:UP |            |               | PT4E |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT4D |               |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT4C |               |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT4B | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT4A | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT3D |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT3C |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3B |               |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3A |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT2F |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2E |               |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2D |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2C |               |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2B |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A |               |
+| PB5B/0   |     unused, PULL:UP |            |               | PB5B |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D |               |
+| TCK/1    |                     |            |               | TCK  | TCK           |
+| TDI/1    |                     |            |               | TDI  | TDI           |
+| TDO/1    |                     |            |               | TDO  | TDO           |
+| TMS/1    |                     |            |               | TMS  | TMS           |
++----------+---------------------+------------+---------------+------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:53:29 2023
+
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
index 9b06891..2c09156 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
@@ -1,208 +1,208 @@
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Wed Aug 16 04:50:41 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
-Preference file: RAM2GS_LCMXO256C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)      67/79           84% used
-                     67/78           85% bonded
-   SLICE             69/128          53% used
-
-
-
-Number of Signals: 251
-Number of Connections: 633
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 32)
-    PHI2_c (driver: PHI2, clk load #: 14)
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-.................
-Placer score = 582801.
-Finished Placer Phase 1.  REAL time: 6 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  582334
-Finished Placer Phase 2.  REAL time: 6 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 1 out of 80 (1%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 32
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 14
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 4 (50%)
-  SECONDARY: 1 out of 4 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 out of 79 (84.8%) PIO sites used.
-   67 out of 78 (85.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
-| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 5 secs 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-0 connections routed; 633 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 04:50:47 08/16/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 04:50:47 08/16/23
-
-Start NBR section for initial routing at 04:50:47 08/16/23
-Level 1, iteration 1
-0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.405ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 04:50:47 08/16/23
-Level 4, iteration 1
-5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 04:50:47 08/16/23
-
-Start NBR section for re-routing at 04:50:47 08/16/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 04:50:47 08/16/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 8.213ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=8 clock_loads=4
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  633 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 8.213
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.273
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Sat Aug 19 20:53:22 2023
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             69/128          53% used
+
+
+
+Number of Signals: 251
+Number of Connections: 633
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 32)
+    PHI2_c (driver: PHI2, clk load #: 14)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.................
+Placer score = 582801.
+Finished Placer Phase 1.  REAL time: 7 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  582334
+Finished Placer Phase 2.  REAL time: 7 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 80 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 32
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 14
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 7 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 633 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 20:53:30 08/19/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 20:53:30 08/19/23
+
+Start NBR section for initial routing at 20:53:30 08/19/23
+Level 1, iteration 1
+0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.344ns/0.000ns; real time: 8 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.405ns/0.000ns; real time: 8 secs 
+Level 4, iteration 1
+10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 20:53:30 08/19/23
+Level 4, iteration 1
+5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:53:30 08/19/23
+
+Start NBR section for re-routing at 20:53:30 08/19/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 8.213ns/0.000ns; real time: 8 secs 
+
+Start NBR section for post-routing at 20:53:30 08/19/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 8.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=8 clock_loads=4
+
+Total CPU time 8 secs 
+Total REAL time: 8 secs 
+Completely routed.
+End of route.  633 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 8.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.273
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 8 secs 
+Total REAL time to completion: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd
index c03664b..a84ae8f 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd
@@ -1,30 +1,30 @@
-[ActiveSupport PAR]
-; Global primary clocks
-GLOBAL_PRIMARY_USED = 2;
-; Global primary clock #0
-GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
-GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
-GLOBAL_PRIMARY_0_LOADNUM = 32;
-; Global primary clock #1
-GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
-GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_1_LOADNUM = 14;
-; # of global secondary clocks
-GLOBAL_SECONDARY_USED = 1;
-; Global secondary clock #0
-GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
-GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
-GLOBAL_SECONDARY_0_LOADNUM = 10;
-GLOBAL_SECONDARY_0_SIGTYPE = CLK;
-; I/O Bank 0 Usage
-BANK_0_USED = 36;
-BANK_0_AVAIL = 41;
-BANK_0_VCCIO = 3.3V;
-BANK_0_VREF1 = NA;
-BANK_0_VREF2 = NA;
-; I/O Bank 1 Usage
-BANK_1_USED = 31;
-BANK_1_AVAIL = 37;
-BANK_1_VCCIO = 3.3V;
-BANK_1_VREF1 = NA;
-BANK_1_VREF2 = NA;
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 2;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 32;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 14;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 1;
+; Global secondary clock #0
+GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
+GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
+GLOBAL_SECONDARY_0_LOADNUM = 10;
+GLOBAL_SECONDARY_0_SIGTYPE = CLK;
+; I/O Bank 0 Usage
+BANK_0_USED = 36;
+BANK_0_AVAIL = 41;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+BANK_0_VREF2 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 31;
+BANK_1_AVAIL = 37;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+BANK_1_VREF2 = NA;
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
index cd7783e..416ddf8 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
@@ -1,28 +1,28 @@
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Aug 16 04:50:41 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
-RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
-RAM2GS_LCMXO256C_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO256C_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            8.213        0            0.273        0            06           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sat Aug 19 20:53:22 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            8.213        0            0.273        0            08           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc
index ec074a2..8417bb5 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc
@@ -1 +1 @@
-DRC detected 0 errors and 0 warnings.
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi
index 5a41e69..a9272ba 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi
@@ -1,2786 +1,2786 @@
-(edif RAM2GS
-  (edifVersion 2 0 0)
-  (edifLevel 0)
-  (keywordMap (keywordLevel 0))
-  (status
-    (written
-      (timeStamp 2023 8 16 4 50 37)
-      (author "Synopsys, Inc.")
-      (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
-     )
-   )
-  (library LUCENT
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell CCU2 (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A0 (direction INPUT))
-           (port B0 (direction INPUT))
-           (port C0 (direction INPUT))
-           (port D0 (direction INPUT))
-           (port A1 (direction INPUT))
-           (port B1 (direction INPUT))
-           (port C1 (direction INPUT))
-           (port D1 (direction INPUT))
-           (port CIN (direction INPUT))
-           (port COUT0 (direction OUTPUT))
-           (port COUT1 (direction OUTPUT))
-           (port S0 (direction OUTPUT))
-           (port S1 (direction OUTPUT))
-         )
-        (property INJECT1_1 (string "NO"))
-        (property INJECT1_0 (string "NO"))
-        (property INIT1 (string "0000"))
-        (property INIT0 (string "0000"))
-       )
-    )
-    (cell BB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port B (direction INOUT))
-           (port I (direction INPUT))
-           (port T (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell OB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell IB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3JX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port PD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3IX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port CD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AY (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1P3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell ORCALUT4 (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port B (direction INPUT))
-           (port C (direction INPUT))
-           (port D (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell PFUMX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port ALUT (direction INPUT))
-           (port BLUT (direction INPUT))
-           (port C0 (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell GSR (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port GSR (direction INPUT))
-         )
-       )
-    )
-    (cell INV (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VHI (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VLO (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-  )
-  (library work
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell RAM2GS (cellType GENERIC)
-       (view verilog (viewType NETLIST)
-         (interface
-           (port PHI2 (direction INPUT))
-           (port (array (rename main "MAin[9:0]") 10) (direction INPUT))
-           (port (array (rename crow "CROW[1:0]") 2) (direction INPUT))
-           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
-           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
-           (port nCCAS (direction INPUT))
-           (port nCRAS (direction INPUT))
-           (port nFWE (direction INPUT))
-           (port LED (direction OUTPUT))
-           (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT))
-           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
-           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
-           (port nRCS (direction OUTPUT))
-           (port RCLK (direction INPUT))
-           (port RCKE (direction OUTPUT))
-           (port nRWE (direction OUTPUT))
-           (port nRRAS (direction OUTPUT))
-           (port nRCAS (direction OUTPUT))
-           (port RDQMH (direction OUTPUT))
-           (port RDQML (direction OUTPUT))
-           (port nUFMCS (direction OUTPUT))
-           (port UFMCLK (direction OUTPUT))
-           (port UFMSDI (direction OUTPUT))
-           (port UFMSDO (direction INPUT))
-         )
-         (contents
-          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
-          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
-          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
-          )
-          (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))"))
-          )
-          (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))"))
-          )
-          (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
-          )
-          (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
-          )
-          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
-          )
-          (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))"))
-          )
-          (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance nRWE_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_0 "WRD[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_1 "WRD[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_2 "WRD[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_3 "WRD[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_4 "WRD[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_5 "WRD[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_6 "WRD[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename WRD_7 "WRD[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMCLK (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RBA_0 "RBA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RBA_1 "RBA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RA11 (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance RA10 (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
-          )
-          (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0 "Bank[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_1 "Bank[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_2 "Bank[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_3 "Bank[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_4 "Bank[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_5 "Bank[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_6 "Bank[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_7 "Bank[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
-          )
-          (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B)+D (!C (!B A)))"))
-          )
-          (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C+(B+A)))"))
-          )
-          (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(!B+!A)))"))
-          )
-          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !A+D (!C !A+C (B !A)))"))
-          )
-          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C (!B A)+C !B))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
-          )
-          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)"))
-          )
-          (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D A)"))
-          )
-          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
-          )
-          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)+C !A))"))
-          )
-          (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+!A))"))
-          )
-          (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A))"))
-          )
-          (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B A)))"))
-          )
-          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(!B+A))"))
-          )
-          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A))"))
-          )
-          (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
-          )
-          (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+!A)"))
-          )
-          (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(!B+!A))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+!A))"))
-          )
-          (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A+B !A)+C B)"))
-          )
-          (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
-          (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A+B !A)"))
-          )
-          (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B !A)"))
-          )
-          (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
-          )
-          (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
-          )
-          (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !B+D (!C (!B A)+C !B))"))
-          )
-          (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))"))
-          )
-          (instance nRWE_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance nRWE_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance nRWE_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))"))
-          )
-          (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))"))
-          )
-          (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A)+C !B)"))
-          )
-          (instance UFMSDI_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
-          )
-          (instance UFMCLK_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C !B)+D (C (!B !A)))"))
-          )
-          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(B+A))+D (!C B+C (B+!A)))"))
-          )
-          (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A))"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)))"))
-          )
-          (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
-          )
-          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A+B A)+C A)"))
-          )
-          (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))"))
-          )
-          (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x5002"))
-          )
-          (instance (rename FS_cry_0_14 "FS_cry_0[14]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_12 "FS_cry_0[12]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_10 "FS_cry_0[10]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_8 "FS_cry_0[8]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_6 "FS_cry_0[6]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_4 "FS_cry_0[4]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_2 "FS_cry_0[2]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
-           (property INIT0 (string "0x300a"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300a"))
-          )
-          (net C1WR_0_a2 (joined
-           (portRef Z (instanceRef C1WR_0_a2))
-           (portRef B (instanceRef ADSubmitted_r))
-          ))
-          (net CBR (joined
-           (portRef Q (instanceRef CBR))
-           (portRef A (instanceRef nRWE_RNO_0))
-           (portRef A (instanceRef nRCS_RNO))
-           (portRef A (instanceRef RCKEEN_8_u))
-           (portRef B (instanceRef nRowColSel_0_0_a3_0))
-           (portRef A (instanceRef LED_pad_RNO))
-          ))
-          (net C1Submitted (joined
-           (portRef Q (instanceRef C1Submitted))
-           (portRef D (instanceRef CmdEnable_s_am))
-           (portRef B (instanceRef C1Submitted_RNO))
-          ))
-          (net (rename Bank_2 "Bank[2]") (joined
-           (portRef Q (instanceRef Bank_2))
-           (portRef A (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net Ready (joined
-           (portRef Q (instanceRef Ready))
-           (portRef B (instanceRef IS_RNO_0))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRWE_RNO_2))
-           (portRef D (instanceRef RCKEEN_8_u))
-           (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef D (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C0 (instanceRef nRWE_RNO_1))
-           (portRef A (instanceRef Ready_RNO))
-           (portRef A (instanceRef RCKEEN_8_u_RNO))
-           (portRef A (instanceRef nRowColSel_RNO))
-          ))
-          (net n8MEGEN (joined
-           (portRef Q (instanceRef n8MEGEN))
-           (portRef C (instanceRef RA11_2))
-           (portRef C (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net CO0 (joined
-           (portRef Q (instanceRef S_0))
-           (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef nRCAS_RNO_0))
-           (portRef B (instanceRef nRWE_RNO_0))
-           (portRef B (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef A (instanceRef S_RNO_0))
-           (portRef A (instanceRef nRowColSel_0_0))
-           (portRef B (instanceRef nRWE_RNO_4))
-           (portRef B (instanceRef nRWE_RNO_3))
-           (portRef C (instanceRef nRowColSel_RNO))
-           (portRef B (instanceRef nRCS_RNO_0))
-          ))
-          (net (rename S_1 "S[1]") (joined
-           (portRef Q (instanceRef S_1))
-           (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRCAS_RNO))
-           (portRef C (instanceRef nRWE_RNO_0))
-           (portRef D (instanceRef RCKEEN_8_u_1_0))
-           (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef B (instanceRef S_0_i_o2_1))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef S_RNO_0))
-           (portRef D (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef A (instanceRef nRWE_RNO_4))
-           (portRef A (instanceRef nRWE_RNO_3))
-           (portRef B (instanceRef nRowColSel_RNO))
-          ))
-          (net RASr2 (joined
-           (portRef Q (instanceRef RASr2))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef D (instanceRef nRWE_RNO_5))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef RCKE_2_0))
-           (portRef B (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef D (instanceRef RASr3))
-           (portRef D (instanceRef nRWE_RNO_3))
-           (portRef B (instanceRef RCKEEN_8_u_RNO))
-           (portRef A (instanceRef RASr2_RNIAFR1))
-          ))
-          (net InitReady (joined
-           (portRef Q (instanceRef InitReady))
-           (portRef A (instanceRef UFMCLK_RNO_0))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-           (portRef B (instanceRef LEDEN_5_i_m2))
-           (portRef B (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef B (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef PHI2r3_RNITCN41))
-           (portRef C (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef A (instanceRef UFMSDI_ens2_i_a0))
-           (portRef B (instanceRef InitReady_RNO))
-           (portRef D (instanceRef nRWE_RNO_4))
-           (portRef D (instanceRef Ready_RNO))
-           (portRef C (instanceRef RCKEEN_8_u_RNO))
-          ))
-          (net FWEr (joined
-           (portRef Q (instanceRef FWEr))
-           (portRef C (instanceRef nRCAS_RNO_0))
-           (portRef A (instanceRef nRWE_RNO))
-           (portRef C (instanceRef nRowColSel_0_0_a3_0))
-          ))
-          (net CASr3 (joined
-           (portRef Q (instanceRef CASr3))
-           (portRef B (instanceRef nRCAS_RNO_1))
-           (portRef B (instanceRef nRWE_RNO_2))
-           (portRef A (instanceRef nRowColSel_0_0_a3_0))
-           (portRef C (instanceRef nRCS_RNO_0))
-          ))
-          (net (rename IS_0 "IS[0]") (joined
-           (portRef Q (instanceRef IS_0))
-           (portRef A (instanceRef IS_RNO_0))
-           (portRef D (instanceRef nRRAS_RNO))
-           (portRef A (instanceRef nRWE_RNO_5))
-           (portRef A (instanceRef IS_n1_0_x2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef A (instanceRef IS_RNO_2))
-           (portRef A (instanceRef nRRAS_5_u_i))
-           (portRef D (instanceRef IS_RNO_3))
-           (portRef A (instanceRef IS_i_0))
-          ))
-          (net (rename IS_3 "IS[3]") (joined
-           (portRef Q (instanceRef IS_3))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef RA10_RNO))
-           (portRef A (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_1 "IS[1]") (joined
-           (portRef Q (instanceRef IS_1))
-           (portRef B (instanceRef nRWE_RNO_5))
-           (portRef B (instanceRef IS_n1_0_x2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef IS_RNO_2))
-           (portRef A (instanceRef RA10_RNO))
-           (portRef C (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_2 "IS[2]") (joined
-           (portRef Q (instanceRef IS_2))
-           (portRef C (instanceRef nRWE_RNO_5))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef C (instanceRef IS_RNO_2))
-           (portRef B (instanceRef RA10_RNO))
-           (portRef B (instanceRef IS_RNO_3))
-          ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A1 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_13_i_a2_1))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A0 (instanceRef FS_cry_0_6))
-           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef B (instanceRef un1_FS_13_i_a2_6))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A1 (instanceRef FS_cry_0_6))
-           (portRef C (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A0 (instanceRef FS_cry_0_8))
-           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A1 (instanceRef FS_cry_0_8))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_0 "FS[0]") (joined
-           (portRef Q (instanceRef FS_0))
-           (portRef A0 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_1 "FS[1]") (joined
-           (portRef Q (instanceRef FS_1))
-           (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef UFMCLK_r_i_m2))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A0 (instanceRef FS_cry_0_2))
-           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef B (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_3 "FS[3]") (joined
-           (portRef Q (instanceRef FS_3))
-           (portRef A1 (instanceRef FS_cry_0_2))
-           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_10 "FS[10]") (joined
-           (portRef Q (instanceRef FS_10))
-           (portRef A0 (instanceRef FS_cry_0_10))
-           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef nUFMCS15_0_a2))
-          ))
-          (net (rename FS_11 "FS[11]") (joined
-           (portRef Q (instanceRef FS_11))
-           (portRef A1 (instanceRef FS_cry_0_10))
-           (portRef A (instanceRef InitReady3_0_a2_3))
-           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef C (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_12 "FS[12]") (joined
-           (portRef Q (instanceRef FS_12))
-           (portRef A0 (instanceRef FS_cry_0_12))
-           (portRef A (instanceRef InitReady3_0_a2_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net (rename FS_13 "FS[13]") (joined
-           (portRef Q (instanceRef FS_13))
-           (portRef A1 (instanceRef FS_cry_0_12))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef B (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_14 "FS[14]") (joined
-           (portRef Q (instanceRef FS_14))
-           (portRef A0 (instanceRef FS_cry_0_14))
-           (portRef B (instanceRef InitReady3_0_a2_3))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
-          ))
-          (net (rename FS_15 "FS[15]") (joined
-           (portRef Q (instanceRef FS_15))
-           (portRef A1 (instanceRef FS_cry_0_14))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_16 "FS[16]") (joined
-           (portRef Q (instanceRef FS_16))
-           (portRef A0 (instanceRef FS_cry_0_16))
-           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef B (instanceRef InitReady3_0_a2))
-          ))
-          (net (rename FS_17 "FS[17]") (joined
-           (portRef Q (instanceRef FS_17))
-           (portRef A1 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef D (instanceRef InitReady3_0_a2_5))
-          ))
-          (net PHI2r2 (joined
-           (portRef Q (instanceRef PHI2r2))
-           (portRef C (instanceRef un1_FS_14_i_a2))
-           (portRef C (instanceRef PHI2r3_RNITCN41))
-           (portRef D (instanceRef PHI2r3))
-          ))
-          (net CmdUFMCS (joined
-           (portRef Q (instanceRef CmdUFMCS))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-          ))
-          (net CASr2 (joined
-           (portRef Q (instanceRef CASr2))
-           (portRef A (instanceRef nRCAS_RNO_1))
-           (portRef A (instanceRef nRWE_RNO_2))
-           (portRef A (instanceRef RCKEEN_8_u_1_0))
-           (portRef D (instanceRef CASr3))
-           (portRef D (instanceRef nRCS_RNO_0))
-          ))
-          (net CASr (joined
-           (portRef Q (instanceRef CASr))
-           (portRef D (instanceRef CASr2))
-          ))
-          (net PHI2r (joined
-           (portRef Q (instanceRef PHI2r))
-           (portRef D (instanceRef PHI2r2))
-          ))
-          (net RASr (joined
-           (portRef Q (instanceRef RASr))
-           (portRef A (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RASr2))
-          ))
-          (net (rename Bank_0 "Bank[0]") (joined
-           (portRef Q (instanceRef Bank_0))
-           (portRef A (instanceRef C1WR_0_a2_0))
-          ))
-          (net (rename Bank_1 "Bank[1]") (joined
-           (portRef Q (instanceRef Bank_1))
-           (portRef B (instanceRef C1WR_0_a2_0))
-          ))
-          (net (rename Bank_3 "Bank[3]") (joined
-           (portRef Q (instanceRef Bank_3))
-           (portRef A (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net (rename Bank_4 "Bank[4]") (joined
-           (portRef Q (instanceRef Bank_4))
-           (portRef B (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net (rename Bank_5 "Bank[5]") (joined
-           (portRef Q (instanceRef Bank_5))
-           (portRef B (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename Bank_6 "Bank[6]") (joined
-           (portRef Q (instanceRef Bank_6))
-           (portRef C (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename Bank_7 "Bank[7]") (joined
-           (portRef Q (instanceRef Bank_7))
-           (portRef D (instanceRef C1WR_0_a2_0_11))
-          ))
-          (net (rename RowA_0 "RowA[0]") (joined
-           (portRef Q (instanceRef RowA_0))
-           (portRef B (instanceRef un9_RA_0))
-          ))
-          (net (rename RowA_1 "RowA[1]") (joined
-           (portRef Q (instanceRef RowA_1))
-           (portRef B (instanceRef un9_RA_1))
-          ))
-          (net (rename RowA_2 "RowA[2]") (joined
-           (portRef Q (instanceRef RowA_2))
-           (portRef B (instanceRef un9_RA_2))
-          ))
-          (net (rename RowA_3 "RowA[3]") (joined
-           (portRef Q (instanceRef RowA_3))
-           (portRef B (instanceRef un9_RA_3))
-          ))
-          (net (rename RowA_4 "RowA[4]") (joined
-           (portRef Q (instanceRef RowA_4))
-           (portRef B (instanceRef un9_RA_4))
-          ))
-          (net (rename RowA_5 "RowA[5]") (joined
-           (portRef Q (instanceRef RowA_5))
-           (portRef B (instanceRef un9_RA_5))
-          ))
-          (net (rename RowA_6 "RowA[6]") (joined
-           (portRef Q (instanceRef RowA_6))
-           (portRef B (instanceRef un9_RA_6))
-          ))
-          (net (rename RowA_7 "RowA[7]") (joined
-           (portRef Q (instanceRef RowA_7))
-           (portRef B (instanceRef un9_RA_7))
-          ))
-          (net (rename RowA_8 "RowA[8]") (joined
-           (portRef Q (instanceRef RowA_8))
-           (portRef B (instanceRef un9_RA_8))
-          ))
-          (net (rename RowA_9 "RowA[9]") (joined
-           (portRef Q (instanceRef RowA_9))
-           (portRef B (instanceRef un9_RA_9))
-          ))
-          (net (rename WRD_0 "WRD[0]") (joined
-           (portRef Q (instanceRef WRD_0))
-           (portRef I (instanceRef RD_pad_0))
-          ))
-          (net (rename WRD_1 "WRD[1]") (joined
-           (portRef Q (instanceRef WRD_1))
-           (portRef I (instanceRef RD_pad_1))
-          ))
-          (net (rename WRD_2 "WRD[2]") (joined
-           (portRef Q (instanceRef WRD_2))
-           (portRef I (instanceRef RD_pad_2))
-          ))
-          (net (rename WRD_3 "WRD[3]") (joined
-           (portRef Q (instanceRef WRD_3))
-           (portRef I (instanceRef RD_pad_3))
-          ))
-          (net (rename WRD_4 "WRD[4]") (joined
-           (portRef Q (instanceRef WRD_4))
-           (portRef I (instanceRef RD_pad_4))
-          ))
-          (net (rename WRD_5 "WRD[5]") (joined
-           (portRef Q (instanceRef WRD_5))
-           (portRef I (instanceRef RD_pad_5))
-          ))
-          (net (rename WRD_6 "WRD[6]") (joined
-           (portRef Q (instanceRef WRD_6))
-           (portRef I (instanceRef RD_pad_6))
-          ))
-          (net (rename WRD_7 "WRD[7]") (joined
-           (portRef Q (instanceRef WRD_7))
-           (portRef I (instanceRef RD_pad_7))
-          ))
-          (net nRowColSel (joined
-           (portRef Q (instanceRef nRowColSel))
-           (portRef B (instanceRef RDQML))
-           (portRef B (instanceRef RDQMH))
-           (portRef C (instanceRef un9_RA_9))
-           (portRef C (instanceRef un9_RA_7))
-           (portRef C (instanceRef un9_RA_6))
-           (portRef C (instanceRef un9_RA_5))
-           (portRef C (instanceRef un9_RA_4))
-           (portRef C (instanceRef un9_RA_3))
-           (portRef C (instanceRef un9_RA_2))
-           (portRef C (instanceRef un9_RA_1))
-           (portRef C (instanceRef un9_RA_0))
-           (portRef C (instanceRef un9_RA_8))
-          ))
-          (net RASr3 (joined
-           (portRef Q (instanceRef RASr3))
-           (portRef C (instanceRef RCKE_2_0))
-          ))
-          (net LEDEN (joined
-           (portRef Q (instanceRef LEDEN))
-           (portRef B (instanceRef LED_pad_RNO))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef A (instanceRef CmdLEDEN_RNO))
-          ))
-          (net CmdLEDEN (joined
-           (portRef Q (instanceRef CmdLEDEN))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef A (instanceRef LEDEN_5_i_m2))
-          ))
-          (net Cmdn8MEGEN (joined
-           (portRef Q (instanceRef Cmdn8MEGEN))
-           (portRef A (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net PHI2r3 (joined
-           (portRef Q (instanceRef PHI2r3))
-           (portRef D (instanceRef un1_FS_14_i_a2))
-           (portRef D (instanceRef PHI2r3_RNITCN41))
-          ))
-          (net CmdSubmitted (joined
-           (portRef Q (instanceRef CmdSubmitted))
-           (portRef A (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef PHI2r3_RNITCN41))
-           (portRef B (instanceRef CmdSubmitted_RNO))
-          ))
-          (net (rename FS_4 "FS[4]") (joined
-           (portRef Q (instanceRef FS_4))
-           (portRef A0 (instanceRef FS_cry_0_4))
-           (portRef B (instanceRef UFMCLK_r_i_m2))
-           (portRef A (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net InitReady3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef InitReady_RNO))
-          ))
-          (net RCKEEN (joined
-           (portRef Q (instanceRef RCKEEN))
-           (portRef D (instanceRef RCKE_2_0))
-          ))
-          (net RA11_2 (joined
-           (portRef Z (instanceRef RA11_2))
-           (portRef D (instanceRef RA11))
-          ))
-          (net XOR8MEG (joined
-           (portRef Q (instanceRef XOR8MEG))
-           (portRef B (instanceRef RA11_2))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_0))
-          ))
-          (net nRRAS_0_sqmuxa (joined
-           (portRef Z (instanceRef nRowColSel_RNO))
-           (portRef CD (instanceRef nRowColSel))
-          ))
-          (net nUFMCS15 (joined
-           (portRef Z (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef B (instanceRef UFMCLK_RNO))
-           (portRef B (instanceRef UFMSDI_RNO))
-          ))
-          (net Ready_0_sqmuxa (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef A (instanceRef Ready_fast_RNO))
-          ))
-          (net RCKE_2 (joined
-           (portRef Z (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RCKE))
-          ))
-          (net nRCAS_0_sqmuxa_1 (joined
-           (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef nRCAS_RNO))
-           (portRef C (instanceRef nRWE_RNO))
-          ))
-          (net XOR8MEG18 (joined
-           (portRef Z (instanceRef XOR8MEG18_0_a2))
-           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdLEDEN))
-           (portRef SP (instanceRef Cmdn8MEGEN))
-           (portRef SP (instanceRef XOR8MEG))
-          ))
-          (net CmdEnable (joined
-           (portRef Q (instanceRef CmdEnable))
-           (portRef A (instanceRef XOR8MEG18_0_a2))
-           (portRef B (instanceRef CmdEnable_s_am))
-           (portRef A (instanceRef CmdEnable_s_bm))
-          ))
-          (net CmdEnable16 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef ADSubmitted_r))
-           (portRef C0 (instanceRef CmdEnable_s))
-           (portRef A (instanceRef C1Submitted_RNO))
-          ))
-          (net CmdEnable17 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef ADSubmitted_r))
-           (portRef A (instanceRef CmdEnable_s_am))
-          ))
-          (net CmdSubmitted_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdSubmitted_RNO))
-          ))
-          (net CmdUFMCLK_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdUFMCLK))
-           (portRef SP (instanceRef CmdUFMCS))
-           (portRef SP (instanceRef CmdUFMSDI))
-          ))
-          (net CmdUFMCLK (joined
-           (portRef Q (instanceRef CmdUFMCLK))
-           (portRef B (instanceRef UFMCLK_RNO_0))
-          ))
-          (net CmdUFMSDI (joined
-           (portRef Q (instanceRef CmdUFMSDI))
-           (portRef A (instanceRef UFMSDI_RNO_0))
-          ))
-          (net ADSubmitted (joined
-           (portRef Q (instanceRef ADSubmitted))
-           (portRef A (instanceRef ADSubmitted_r))
-           (portRef B (instanceRef CmdEnable_s_bm))
-          ))
-          (net C1Submitted_RNO (joined
-           (portRef Z (instanceRef C1Submitted_RNO))
-           (portRef D (instanceRef C1Submitted))
-          ))
-          (net ADSubmitted_r (joined
-           (portRef Z (instanceRef ADSubmitted_r))
-           (portRef D (instanceRef ADSubmitted))
-          ))
-          (net UFMSDI_RNO (joined
-           (portRef Z (instanceRef UFMSDI_RNO))
-           (portRef D (instanceRef UFMSDI))
-          ))
-          (net CmdEnable_s (joined
-           (portRef Z (instanceRef CmdEnable_s))
-           (portRef D (instanceRef CmdEnable))
-          ))
-          (net nRowColSel_0_0 (joined
-           (portRef Z (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRowColSel))
-          ))
-          (net RCKEEN_8 (joined
-           (portRef Z (instanceRef RCKEEN_8_u))
-           (portRef D (instanceRef RCKEEN))
-          ))
-          (net N_31 (joined
-           (portRef Z (instanceRef un1_FS_14_i_0))
-           (portRef SP (instanceRef n8MEGEN))
-          ))
-          (net N_33 (joined
-           (portRef Z (instanceRef un1_FS_13_i_0))
-           (portRef SP (instanceRef LEDEN))
-          ))
-          (net N_24 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i))
-           (portRef B (instanceRef nRCS_RNO))
-          ))
-          (net N_41 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef A (instanceRef nRCAS_RNO))
-          ))
-          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
-           (portRef Z (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef nRRAS_5_u_i_0))
-           (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef D (instanceRef S_1))
-           (portRef D (instanceRef RCKEEN_8_u_RNO))
-          ))
-          (net N_159 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef D (instanceRef RA10_RNO))
-          ))
-          (net N_165 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef Ready_RNO))
-          ))
-          (net N_95_5 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_5))
-           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef D (instanceRef InitReady3_0_a2))
-          ))
-          (net N_95_3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef C (instanceRef InitReady3_0_a2))
-          ))
-          (net N_51 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef D (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef B (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_126 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
-           (portRef C (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_151 (joined
-           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef C (instanceRef UFMSDI_RNO_0))
-           (portRef D (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net N_137_8 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_8))
-           (portRef C (instanceRef un1_FS_13_i_0))
-           (portRef C (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_129 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef UFMCLK_RNO_0))
-          ))
-          (net N_155 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef IS_RNO_0))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRRAS_RNO))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_56_i (joined
-           (portRef Z (instanceRef IS_n1_0_x2))
-           (portRef D (instanceRef IS_1))
-          ))
-          (net N_160 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef nRRAS_RNO))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_136 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2))
-           (portRef A (instanceRef un1_FS_13_i_0))
-           (portRef A (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_69 (joined
-           (portRef Z (instanceRef n8MEGEN_5_i_m2))
-           (portRef D (instanceRef n8MEGEN))
-          ))
-          (net N_70 (joined
-           (portRef Z (instanceRef LEDEN_5_i_m2))
-           (portRef D (instanceRef LEDEN))
-          ))
-          (net N_137_6 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef un1_FS_13_i_0))
-           (portRef B (instanceRef un1_FS_14_i_0))
-          ))
-          (net XOR8MEG_3 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef D (instanceRef XOR8MEG))
-          ))
-          (net CmdEnable16_1 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_1))
-           (portRef A (instanceRef CmdEnable16_0_a2_5))
-          ))
-          (net N_43 (joined
-           (portRef Z (instanceRef CmdEnable17_0_o2))
-           (portRef D (instanceRef CmdEnable17_0_a2_4))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_147 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0))
-           (portRef A (instanceRef un1_CMDWR))
-           (portRef C (instanceRef CmdEnable16_0_a2))
-           (portRef B (instanceRef C1WR_0_a2))
-           (portRef D (instanceRef XOR8MEG18_0_a2))
-           (portRef D (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef C1Submitted_RNO))
-          ))
-          (net CmdEnable16_4 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_4))
-           (portRef A (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net un1_Din_4 (joined
-           (portRef Z (instanceRef un1_Din_4))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_0))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a3_2))
-          ))
-          (net N_171 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a3_3))
-          ))
-          (net N_128 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_152 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef CmdLEDEN_RNO))
-           (portRef B (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net N_132 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef B (instanceRef CmdLEDEN_RNO))
-          ))
-          (net N_133 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef C (instanceRef CmdLEDEN_RNO))
-          ))
-          (net un1_CMDWR (joined
-           (portRef Z (instanceRef un1_CMDWR))
-           (portRef C (instanceRef CmdEnable_s_am))
-          ))
-          (net N_179 (joined
-           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
-           (portRef B (instanceRef nRowColSel_0_0))
-          ))
-          (net XOR8MEG_3_u_0_a3_2 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a3_3))
-          ))
-          (net UFMCLK_r_i_a2_2_2 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef C (instanceRef UFMCLK_RNO_0))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-          ))
-          (net UFMCLK_RNO (joined
-           (portRef Z (instanceRef UFMCLK_RNO))
-           (portRef D (instanceRef UFMCLK))
-          ))
-          (net UFMSDI_ens2_i_a0 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
-           (portRef B (instanceRef UFMSDI_RNO_0))
-          ))
-          (net RCKEEN_8_u_0_0 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_RNO))
-           (portRef B (instanceRef RCKEEN_8_u))
-          ))
-          (net RCKEEN_8_u_0_a2_1_out (joined
-           (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s))
-           (portRef D (instanceRef nRCS_RNO))
-          ))
-          (net nCRAS_c_i (joined
-           (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef CK (instanceRef CBR))
-           (portRef CK (instanceRef CBR_fast))
-           (portRef CK (instanceRef FWEr))
-           (portRef CK (instanceRef FWEr_fast))
-           (portRef CK (instanceRef RBA_1))
-           (portRef CK (instanceRef RBA_0))
-           (portRef CK (instanceRef RowA_9))
-           (portRef CK (instanceRef RowA_8))
-           (portRef CK (instanceRef RowA_7))
-           (portRef CK (instanceRef RowA_6))
-           (portRef CK (instanceRef RowA_5))
-           (portRef CK (instanceRef RowA_4))
-           (portRef CK (instanceRef RowA_3))
-           (portRef CK (instanceRef RowA_2))
-           (portRef CK (instanceRef RowA_1))
-           (portRef CK (instanceRef RowA_0))
-          ))
-          (net N_159_i (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef SP (instanceRef IS_3))
-           (portRef SP (instanceRef IS_2))
-           (portRef SP (instanceRef IS_1))
-          ))
-          (net RD_1_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef T (instanceRef RD_pad_0))
-           (portRef T (instanceRef RD_pad_1))
-           (portRef T (instanceRef RD_pad_2))
-           (portRef T (instanceRef RD_pad_3))
-           (portRef T (instanceRef RD_pad_4))
-           (portRef T (instanceRef RD_pad_5))
-           (portRef T (instanceRef RD_pad_6))
-           (portRef T (instanceRef RD_pad_7))
-          ))
-          (net N_28_i (joined
-           (portRef Z (instanceRef nRCS_RNO))
-           (portRef D (instanceRef nRCS))
-          ))
-          (net N_37_i (joined
-           (portRef Z (instanceRef nRCAS_RNO))
-           (portRef D (instanceRef nRCAS))
-          ))
-          (net N_24_i (joined
-           (portRef Z (instanceRef nRRAS_RNO))
-           (portRef D (instanceRef nRRAS))
-          ))
-          (net nUFMCS_s_0_N_5_i (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef D (instanceRef nUFMCS))
-          ))
-          (net N_39_i (joined
-           (portRef Z (instanceRef nRWE_RNO))
-           (portRef D (instanceRef nRWE))
-          ))
-          (net N_64_i_i (joined
-           (portRef Z (instanceRef IS_RNO_0))
-           (portRef D (instanceRef IS_0))
-          ))
-          (net N_61_i_i (joined
-           (portRef Z (instanceRef IS_RNO_3))
-           (portRef D (instanceRef IS_3))
-          ))
-          (net N_60_i_i (joined
-           (portRef Z (instanceRef IS_RNO_2))
-           (portRef D (instanceRef IS_2))
-          ))
-          (net N_177_i (joined
-           (portRef Z (instanceRef S_RNO_0))
-           (portRef D (instanceRef S_0))
-          ))
-          (net N_21_i (joined
-           (portRef Z (instanceRef CmdLEDEN_RNO))
-           (portRef D (instanceRef CmdLEDEN))
-          ))
-          (net N_19_i (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_RNO))
-           (portRef D (instanceRef Cmdn8MEGEN))
-          ))
-          (net N_139_i (joined
-           (portRef Z (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef A (instanceRef UFMCLK_RNO))
-           (portRef A (instanceRef UFMSDI_RNO))
-          ))
-          (net (rename FS_cry_0 "FS_cry[0]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_0))
-          ))
-          (net (rename FS_s_0 "FS_s[0]") (joined
-           (portRef S0 (instanceRef FS_cry_0_0))
-           (portRef D (instanceRef FS_0))
-          ))
-          (net (rename FS_cry_1 "FS_cry[1]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_0))
-           (portRef CIN (instanceRef FS_cry_0_2))
-          ))
-          (net (rename FS_s_1 "FS_s[1]") (joined
-           (portRef S1 (instanceRef FS_cry_0_0))
-           (portRef D (instanceRef FS_1))
-          ))
-          (net (rename FS_cry_2 "FS_cry[2]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_2))
-          ))
-          (net (rename FS_s_2 "FS_s[2]") (joined
-           (portRef S0 (instanceRef FS_cry_0_2))
-           (portRef D (instanceRef FS_2))
-          ))
-          (net (rename FS_cry_3 "FS_cry[3]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_2))
-           (portRef CIN (instanceRef FS_cry_0_4))
-          ))
-          (net (rename FS_s_3 "FS_s[3]") (joined
-           (portRef S1 (instanceRef FS_cry_0_2))
-           (portRef D (instanceRef FS_3))
-          ))
-          (net (rename FS_cry_4 "FS_cry[4]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_4))
-          ))
-          (net (rename FS_s_4 "FS_s[4]") (joined
-           (portRef S0 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef FS_4))
-          ))
-          (net (rename FS_cry_5 "FS_cry[5]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_4))
-           (portRef CIN (instanceRef FS_cry_0_6))
-          ))
-          (net (rename FS_s_5 "FS_s[5]") (joined
-           (portRef S1 (instanceRef FS_cry_0_4))
-           (portRef D (instanceRef FS_5))
-          ))
-          (net (rename FS_cry_6 "FS_cry[6]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_6))
-          ))
-          (net (rename FS_s_6 "FS_s[6]") (joined
-           (portRef S0 (instanceRef FS_cry_0_6))
-           (portRef D (instanceRef FS_6))
-          ))
-          (net (rename FS_cry_7 "FS_cry[7]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_6))
-           (portRef CIN (instanceRef FS_cry_0_8))
-          ))
-          (net (rename FS_s_7 "FS_s[7]") (joined
-           (portRef S1 (instanceRef FS_cry_0_6))
-           (portRef D (instanceRef FS_7))
-          ))
-          (net (rename FS_cry_8 "FS_cry[8]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_8))
-          ))
-          (net (rename FS_s_8 "FS_s[8]") (joined
-           (portRef S0 (instanceRef FS_cry_0_8))
-           (portRef D (instanceRef FS_8))
-          ))
-          (net (rename FS_cry_9 "FS_cry[9]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_8))
-           (portRef CIN (instanceRef FS_cry_0_10))
-          ))
-          (net (rename FS_s_9 "FS_s[9]") (joined
-           (portRef S1 (instanceRef FS_cry_0_8))
-           (portRef D (instanceRef FS_9))
-          ))
-          (net (rename FS_cry_10 "FS_cry[10]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_10))
-          ))
-          (net (rename FS_s_10 "FS_s[10]") (joined
-           (portRef S0 (instanceRef FS_cry_0_10))
-           (portRef D (instanceRef FS_10))
-          ))
-          (net (rename FS_cry_11 "FS_cry[11]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_10))
-           (portRef CIN (instanceRef FS_cry_0_12))
-          ))
-          (net (rename FS_s_11 "FS_s[11]") (joined
-           (portRef S1 (instanceRef FS_cry_0_10))
-           (portRef D (instanceRef FS_11))
-          ))
-          (net (rename FS_cry_12 "FS_cry[12]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_12))
-          ))
-          (net (rename FS_s_12 "FS_s[12]") (joined
-           (portRef S0 (instanceRef FS_cry_0_12))
-           (portRef D (instanceRef FS_12))
-          ))
-          (net (rename FS_cry_13 "FS_cry[13]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_12))
-           (portRef CIN (instanceRef FS_cry_0_14))
-          ))
-          (net (rename FS_s_13 "FS_s[13]") (joined
-           (portRef S1 (instanceRef FS_cry_0_12))
-           (portRef D (instanceRef FS_13))
-          ))
-          (net (rename FS_cry_14 "FS_cry[14]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_14))
-          ))
-          (net (rename FS_s_14 "FS_s[14]") (joined
-           (portRef S0 (instanceRef FS_cry_0_14))
-           (portRef D (instanceRef FS_14))
-          ))
-          (net (rename FS_cry_15 "FS_cry[15]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_14))
-           (portRef CIN (instanceRef FS_cry_0_16))
-          ))
-          (net (rename FS_s_15 "FS_s[15]") (joined
-           (portRef S1 (instanceRef FS_cry_0_14))
-           (portRef D (instanceRef FS_15))
-          ))
-          (net (rename FS_cry_16 "FS_cry[16]") (joined
-           (portRef COUT0 (instanceRef FS_cry_0_16))
-          ))
-          (net (rename FS_s_16 "FS_s[16]") (joined
-           (portRef S0 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef FS_16))
-          ))
-          (net (rename FS_s_17 "FS_s[17]") (joined
-           (portRef S1 (instanceRef FS_cry_0_16))
-           (portRef D (instanceRef FS_17))
-          ))
-          (net RA10s_i (joined
-           (portRef Z (instanceRef RA10_RNO))
-           (portRef PD (instanceRef RA10))
-          ))
-          (net Cmdn8MEGEN_4_u_i_0 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
-           (portRef A (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net UFMSDI_ens2_i_o2_0_3 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net C1WR_0_a2_0_3 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_3))
-           (portRef C (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net C1WR_0_a2_0_4 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef C1WR_0_a2_0_10))
-          ))
-          (net C1WR_0_a2_0_10 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_10))
-           (portRef C (instanceRef C1WR_0_a2_0))
-          ))
-          (net C1WR_0_a2_0_11 (joined
-           (portRef Z (instanceRef C1WR_0_a2_0_11))
-           (portRef D (instanceRef C1WR_0_a2_0))
-          ))
-          (net Ready_0_sqmuxa_0_a3_2 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef Ready_RNO))
-          ))
-          (net UFMSDI_ens2_i_a2_4_2 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net CmdEnable16_0_a2_4 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef CmdEnable16_0_a2))
-          ))
-          (net CmdEnable16_0_a2_5 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_5))
-           (portRef B (instanceRef CmdEnable16_0_a2))
-          ))
-          (net nRRAS_5_u_i_0 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0))
-           (portRef A (instanceRef nRRAS_RNO))
-           (portRef D (instanceRef nRRAS_5_u_i))
-          ))
-          (net CmdEnable17_0_a2_3 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable17_0_a2))
-          ))
-          (net CmdEnable17_0_a2_4 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_4))
-           (portRef B (instanceRef CmdEnable17_0_a2))
-          ))
-          (net un1_FS_13_i_a2_1 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_1))
-           (portRef D (instanceRef un1_FS_13_i_0))
-          ))
-          (net un1_FS_14_i_a2_0_1 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_14_i_0))
-          ))
-          (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined
-           (portRef COUT1 (instanceRef FS_cry_0_16))
-          ))
-          (net RCKEEN_8_u_1 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_1_0))
-           (portRef C (instanceRef RCKEEN_8_u))
-          ))
-          (net N_28_i_1 (joined
-           (portRef Z (instanceRef nRCS_RNO_0))
-           (portRef C (instanceRef nRCS_RNO))
-          ))
-          (net m18_0_a3_3 (joined
-           (portRef Z (instanceRef nRWE_RNO_5))
-           (portRef C (instanceRef nRWE_RNO_4))
-          ))
-          (net m18_0_a2_1 (joined
-           (portRef Z (instanceRef nRWE_RNO_1))
-           (portRef D (instanceRef nRWE_RNO))
-          ))
-          (net m6_0_a2_2 (joined
-           (portRef Z (instanceRef nRWE_RNO_2))
-           (portRef D (instanceRef nRWE_RNO_0))
-          ))
-          (net G_17_1 (joined
-           (portRef Z (instanceRef nRWE_RNO_0))
-           (portRef B (instanceRef nRWE_RNO))
-          ))
-          (net g0_1 (joined
-           (portRef Z (instanceRef nRCAS_RNO_0))
-           (portRef D (instanceRef nRCAS_RNO))
-          ))
-          (net g4_0_0_0 (joined
-           (portRef Z (instanceRef nRCAS_RNO_1))
-           (portRef D (instanceRef nRCAS_RNO_0))
-          ))
-          (net CBR_fast (joined
-           (portRef Q (instanceRef CBR_fast))
-           (portRef A (instanceRef nRCAS_RNO_0))
-           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-          ))
-          (net FWEr_fast (joined
-           (portRef Q (instanceRef FWEr_fast))
-           (portRef C (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef nRCS_RNO_0))
-          ))
-          (net Ready_fast (joined
-           (portRef Q (instanceRef Ready_fast))
-           (portRef B (instanceRef Ready_fast_RNO))
-           (portRef A (instanceRef Ready_fast_RNI29NA))
-          ))
-          (net UFMSDI_r_xx_mm_1 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_0))
-           (portRef D (instanceRef UFMSDI_RNO))
-          ))
-          (net UFMCLK_r_i_m4_xx_mm_1 (joined
-           (portRef Z (instanceRef UFMCLK_RNO_0))
-           (portRef D (instanceRef UFMCLK_RNO))
-          ))
-          (net nUFMCS_s_0_N_5_i_N_2L1 (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
-           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
-          ))
-          (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
-           (portRef Z (instanceRef XOR8MEG_CN))
-           (portRef CK (instanceRef ADSubmitted))
-           (portRef CK (instanceRef C1Submitted))
-           (portRef CK (instanceRef CmdEnable))
-           (portRef CK (instanceRef CmdLEDEN))
-           (portRef CK (instanceRef CmdSubmitted))
-           (portRef CK (instanceRef CmdUFMCLK))
-           (portRef CK (instanceRef CmdUFMCS))
-           (portRef CK (instanceRef CmdUFMSDI))
-           (portRef CK (instanceRef Cmdn8MEGEN))
-           (portRef CK (instanceRef XOR8MEG))
-          ))
-          (net VCC (joined
-           (portRef Z (instanceRef VCC))
-           (portRef CIN (instanceRef FS_cry_0_0))
-           (portRef GSR (instanceRef GSR_INST))
-          ))
-          (net GND (joined
-           (portRef Z (instanceRef GND))
-           (portRef D1 (instanceRef FS_cry_0_0))
-           (portRef C1 (instanceRef FS_cry_0_0))
-           (portRef B1 (instanceRef FS_cry_0_0))
-           (portRef D0 (instanceRef FS_cry_0_0))
-           (portRef C0 (instanceRef FS_cry_0_0))
-           (portRef B0 (instanceRef FS_cry_0_0))
-           (portRef D1 (instanceRef FS_cry_0_2))
-           (portRef C1 (instanceRef FS_cry_0_2))
-           (portRef B1 (instanceRef FS_cry_0_2))
-           (portRef D0 (instanceRef FS_cry_0_2))
-           (portRef C0 (instanceRef FS_cry_0_2))
-           (portRef B0 (instanceRef FS_cry_0_2))
-           (portRef D1 (instanceRef FS_cry_0_4))
-           (portRef C1 (instanceRef FS_cry_0_4))
-           (portRef B1 (instanceRef FS_cry_0_4))
-           (portRef D0 (instanceRef FS_cry_0_4))
-           (portRef C0 (instanceRef FS_cry_0_4))
-           (portRef B0 (instanceRef FS_cry_0_4))
-           (portRef D1 (instanceRef FS_cry_0_6))
-           (portRef C1 (instanceRef FS_cry_0_6))
-           (portRef B1 (instanceRef FS_cry_0_6))
-           (portRef D0 (instanceRef FS_cry_0_6))
-           (portRef C0 (instanceRef FS_cry_0_6))
-           (portRef B0 (instanceRef FS_cry_0_6))
-           (portRef D1 (instanceRef FS_cry_0_8))
-           (portRef C1 (instanceRef FS_cry_0_8))
-           (portRef B1 (instanceRef FS_cry_0_8))
-           (portRef D0 (instanceRef FS_cry_0_8))
-           (portRef C0 (instanceRef FS_cry_0_8))
-           (portRef B0 (instanceRef FS_cry_0_8))
-           (portRef D1 (instanceRef FS_cry_0_10))
-           (portRef C1 (instanceRef FS_cry_0_10))
-           (portRef B1 (instanceRef FS_cry_0_10))
-           (portRef D0 (instanceRef FS_cry_0_10))
-           (portRef C0 (instanceRef FS_cry_0_10))
-           (portRef B0 (instanceRef FS_cry_0_10))
-           (portRef D1 (instanceRef FS_cry_0_12))
-           (portRef C1 (instanceRef FS_cry_0_12))
-           (portRef B1 (instanceRef FS_cry_0_12))
-           (portRef D0 (instanceRef FS_cry_0_12))
-           (portRef C0 (instanceRef FS_cry_0_12))
-           (portRef B0 (instanceRef FS_cry_0_12))
-           (portRef D1 (instanceRef FS_cry_0_14))
-           (portRef C1 (instanceRef FS_cry_0_14))
-           (portRef B1 (instanceRef FS_cry_0_14))
-           (portRef D0 (instanceRef FS_cry_0_14))
-           (portRef C0 (instanceRef FS_cry_0_14))
-           (portRef B0 (instanceRef FS_cry_0_14))
-           (portRef D1 (instanceRef FS_cry_0_16))
-           (portRef C1 (instanceRef FS_cry_0_16))
-           (portRef B1 (instanceRef FS_cry_0_16))
-           (portRef D0 (instanceRef FS_cry_0_16))
-           (portRef C0 (instanceRef FS_cry_0_16))
-           (portRef B0 (instanceRef FS_cry_0_16))
-          ))
-          (net PHI2_c (joined
-           (portRef O (instanceRef PHI2_pad))
-           (portRef CK (instanceRef Bank_7))
-           (portRef CK (instanceRef Bank_6))
-           (portRef CK (instanceRef Bank_5))
-           (portRef CK (instanceRef Bank_4))
-           (portRef CK (instanceRef Bank_3))
-           (portRef CK (instanceRef Bank_2))
-           (portRef CK (instanceRef Bank_1))
-           (portRef CK (instanceRef Bank_0))
-           (portRef D (instanceRef PHI2r))
-           (portRef CK (instanceRef RA11))
-           (portRef A (instanceRef XOR8MEG_CN))
-          ))
-          (net PHI2 (joined
-           (portRef PHI2)
-           (portRef I (instanceRef PHI2_pad))
-          ))
-          (net (rename MAin_c_0 "MAin_c[0]") (joined
-           (portRef O (instanceRef MAin_pad_0))
-           (portRef B (instanceRef un1_CMDWR))
-           (portRef A (instanceRef un9_RA_0))
-           (portRef D (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef B (instanceRef XOR8MEG18_0_a2))
-           (portRef C (instanceRef CmdEnable17_0_a2))
-           (portRef D (instanceRef RowA_0))
-          ))
-          (net (rename MAin_0 "MAin[0]") (joined
-           (portRef (member main 9))
-           (portRef I (instanceRef MAin_pad_0))
-          ))
-          (net (rename MAin_c_1 "MAin_c[1]") (joined
-           (portRef O (instanceRef MAin_pad_1))
-           (portRef C (instanceRef un1_CMDWR))
-           (portRef A (instanceRef un9_RA_1))
-           (portRef C (instanceRef CmdEnable17_0_a2_4))
-           (portRef D (instanceRef CmdEnable16_0_a2_5))
-           (portRef A (instanceRef C1WR_0_a2))
-           (portRef C (instanceRef XOR8MEG18_0_a2))
-           (portRef D (instanceRef RowA_1))
-           (portRef D (instanceRef C1Submitted_RNO))
-          ))
-          (net (rename MAin_1 "MAin[1]") (joined
-           (portRef (member main 8))
-           (portRef I (instanceRef MAin_pad_1))
-          ))
-          (net (rename MAin_c_2 "MAin_c[2]") (joined
-           (portRef O (instanceRef MAin_pad_2))
-           (portRef A (instanceRef un9_RA_2))
-           (portRef A (instanceRef C1WR_0_a2_0_3))
-           (portRef D (instanceRef RowA_2))
-          ))
-          (net (rename MAin_2 "MAin[2]") (joined
-           (portRef (member main 7))
-           (portRef I (instanceRef MAin_pad_2))
-          ))
-          (net (rename MAin_c_3 "MAin_c[3]") (joined
-           (portRef O (instanceRef MAin_pad_3))
-           (portRef A (instanceRef un9_RA_3))
-           (portRef B (instanceRef C1WR_0_a2_0_3))
-           (portRef D (instanceRef RowA_3))
-          ))
-          (net (rename MAin_3 "MAin[3]") (joined
-           (portRef (member main 6))
-           (portRef I (instanceRef MAin_pad_3))
-          ))
-          (net (rename MAin_c_4 "MAin_c[4]") (joined
-           (portRef O (instanceRef MAin_pad_4))
-           (portRef A (instanceRef un9_RA_4))
-           (portRef A (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_4))
-          ))
-          (net (rename MAin_4 "MAin[4]") (joined
-           (portRef (member main 5))
-           (portRef I (instanceRef MAin_pad_4))
-          ))
-          (net (rename MAin_c_5 "MAin_c[5]") (joined
-           (portRef O (instanceRef MAin_pad_5))
-           (portRef A (instanceRef un9_RA_5))
-           (portRef B (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_5))
-          ))
-          (net (rename MAin_5 "MAin[5]") (joined
-           (portRef (member main 4))
-           (portRef I (instanceRef MAin_pad_5))
-          ))
-          (net (rename MAin_c_6 "MAin_c[6]") (joined
-           (portRef O (instanceRef MAin_pad_6))
-           (portRef A (instanceRef un9_RA_6))
-           (portRef C (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_6))
-          ))
-          (net (rename MAin_6 "MAin[6]") (joined
-           (portRef (member main 3))
-           (portRef I (instanceRef MAin_pad_6))
-          ))
-          (net (rename MAin_c_7 "MAin_c[7]") (joined
-           (portRef O (instanceRef MAin_pad_7))
-           (portRef A (instanceRef un9_RA_7))
-           (portRef D (instanceRef C1WR_0_a2_0_4))
-           (portRef D (instanceRef RowA_7))
-          ))
-          (net (rename MAin_7 "MAin[7]") (joined
-           (portRef (member main 2))
-           (portRef I (instanceRef MAin_pad_7))
-          ))
-          (net (rename MAin_c_8 "MAin_c[8]") (joined
-           (portRef O (instanceRef MAin_pad_8))
-           (portRef A (instanceRef un9_RA_8))
-           (portRef D (instanceRef RowA_8))
-          ))
-          (net (rename MAin_8 "MAin[8]") (joined
-           (portRef (member main 1))
-           (portRef I (instanceRef MAin_pad_8))
-          ))
-          (net (rename MAin_c_9 "MAin_c[9]") (joined
-           (portRef O (instanceRef MAin_pad_9))
-           (portRef A (instanceRef RDQML))
-           (portRef A (instanceRef RDQMH))
-           (portRef A (instanceRef un9_RA_9))
-           (portRef D (instanceRef RowA_9))
-          ))
-          (net (rename MAin_9 "MAin[9]") (joined
-           (portRef (member main 0))
-           (portRef I (instanceRef MAin_pad_9))
-          ))
-          (net (rename CROW_c_0 "CROW_c[0]") (joined
-           (portRef O (instanceRef CROW_pad_0))
-           (portRef D (instanceRef RBA_0))
-          ))
-          (net (rename CROW_0 "CROW[0]") (joined
-           (portRef (member crow 1))
-           (portRef I (instanceRef CROW_pad_0))
-          ))
-          (net (rename CROW_c_1 "CROW_c[1]") (joined
-           (portRef O (instanceRef CROW_pad_1))
-           (portRef D (instanceRef RBA_1))
-          ))
-          (net (rename CROW_1 "CROW[1]") (joined
-           (portRef (member crow 0))
-           (portRef I (instanceRef CROW_pad_1))
-          ))
-          (net (rename Din_c_0 "Din_c[0]") (joined
-           (portRef O (instanceRef Din_pad_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable16_0_a2_4))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_0))
-           (portRef D (instanceRef CmdUFMSDI))
-           (portRef D (instanceRef WRD_0))
-          ))
-          (net (rename Din_0 "Din[0]") (joined
-           (portRef (member din 7))
-           (portRef I (instanceRef Din_pad_0))
-          ))
-          (net (rename Din_c_1 "Din_c[1]") (joined
-           (portRef O (instanceRef Din_pad_1))
-           (portRef A (instanceRef CmdEnable17_0_a2_3))
-           (portRef B (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a3_3))
-           (portRef D (instanceRef Bank_1))
-           (portRef D (instanceRef CmdUFMCLK))
-           (portRef D (instanceRef WRD_1))
-          ))
-          (net (rename Din_1 "Din[1]") (joined
-           (portRef (member din 6))
-           (portRef I (instanceRef Din_pad_1))
-          ))
-          (net (rename Din_c_2 "Din_c[2]") (joined
-           (portRef O (instanceRef Din_pad_2))
-           (portRef A (instanceRef CmdEnable17_0_a2_4))
-           (portRef B (instanceRef CmdEnable16_0_a2_5))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_2))
-           (portRef D (instanceRef CmdUFMCS))
-           (portRef D (instanceRef WRD_2))
-          ))
-          (net (rename Din_2 "Din[2]") (joined
-           (portRef (member din 5))
-           (portRef I (instanceRef Din_pad_2))
-          ))
-          (net (rename Din_c_3 "Din_c[3]") (joined
-           (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdEnable17_0_o2))
-           (portRef C (instanceRef CmdEnable16_0_a2_4_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a3_2))
-           (portRef D (instanceRef Bank_3))
-           (portRef D (instanceRef WRD_3))
-          ))
-          (net (rename Din_3 "Din[3]") (joined
-           (portRef (member din 4))
-           (portRef I (instanceRef Din_pad_3))
-          ))
-          (net (rename Din_c_4 "Din_c[4]") (joined
-           (portRef O (instanceRef Din_pad_4))
-           (portRef D (instanceRef CmdEnable17_0_a2_3))
-           (portRef A (instanceRef CmdEnable16_0_a2_1))
-           (portRef A (instanceRef un1_Din_4))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef Bank_4))
-           (portRef D (instanceRef WRD_4))
-          ))
-          (net (rename Din_4 "Din[4]") (joined
-           (portRef (member din 3))
-           (portRef I (instanceRef Din_pad_4))
-          ))
-          (net (rename Din_c_5 "Din_c[5]") (joined
-           (portRef O (instanceRef Din_pad_5))
-           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2))
-           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdEnable17_0_o2))
-           (portRef B (instanceRef CmdEnable16_0_a2_4))
-           (portRef B (instanceRef un1_Din_4))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef Bank_5))
-           (portRef D (instanceRef WRD_5))
-          ))
-          (net (rename Din_5 "Din[5]") (joined
-           (portRef (member din 2))
-           (portRef I (instanceRef Din_pad_5))
-          ))
-          (net (rename Din_c_6 "Din_c[6]") (joined
-           (portRef O (instanceRef Din_pad_6))
-           (portRef C (instanceRef un1_Din_4))
-           (portRef A (instanceRef RA11_2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_4))
-           (portRef C (instanceRef CmdEnable16_0_a2_5))
-           (portRef D (instanceRef Bank_6))
-           (portRef D (instanceRef WRD_6))
-          ))
-          (net (rename Din_6 "Din[6]") (joined
-           (portRef (member din 1))
-           (portRef I (instanceRef Din_pad_6))
-          ))
-          (net (rename Din_c_7 "Din_c[7]") (joined
-           (portRef O (instanceRef Din_pad_7))
-           (portRef C (instanceRef CmdEnable17_0_a2_3))
-           (portRef B (instanceRef CmdEnable16_0_a2_1))
-           (portRef D (instanceRef un1_Din_4))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef Bank_7))
-           (portRef D (instanceRef WRD_7))
-          ))
-          (net (rename Din_7 "Din[7]") (joined
-           (portRef (member din 0))
-           (portRef I (instanceRef Din_pad_7))
-          ))
-          (net (rename Dout_0 "Dout[0]") (joined
-           (portRef O (instanceRef Dout_pad_0))
-           (portRef (member dout 7))
-          ))
-          (net (rename Dout_1 "Dout[1]") (joined
-           (portRef O (instanceRef Dout_pad_1))
-           (portRef (member dout 6))
-          ))
-          (net (rename Dout_2 "Dout[2]") (joined
-           (portRef O (instanceRef Dout_pad_2))
-           (portRef (member dout 5))
-          ))
-          (net (rename Dout_3 "Dout[3]") (joined
-           (portRef O (instanceRef Dout_pad_3))
-           (portRef (member dout 4))
-          ))
-          (net (rename Dout_4 "Dout[4]") (joined
-           (portRef O (instanceRef Dout_pad_4))
-           (portRef (member dout 3))
-          ))
-          (net (rename Dout_5 "Dout[5]") (joined
-           (portRef O (instanceRef Dout_pad_5))
-           (portRef (member dout 2))
-          ))
-          (net (rename Dout_6 "Dout[6]") (joined
-           (portRef O (instanceRef Dout_pad_6))
-           (portRef (member dout 1))
-          ))
-          (net (rename Dout_7 "Dout[7]") (joined
-           (portRef O (instanceRef Dout_pad_7))
-           (portRef (member dout 0))
-          ))
-          (net nCCAS_c (joined
-           (portRef O (instanceRef nCCAS_pad))
-           (portRef A (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef nCCAS_pad_RNISUR8))
-          ))
-          (net nCCAS (joined
-           (portRef nCCAS)
-           (portRef I (instanceRef nCCAS_pad))
-          ))
-          (net nCRAS_c (joined
-           (portRef O (instanceRef nCRAS_pad))
-           (portRef C (instanceRef LED_pad_RNO))
-           (portRef A (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef A (instanceRef RASr_RNO))
-          ))
-          (net nCRAS (joined
-           (portRef nCRAS)
-           (portRef I (instanceRef nCRAS_pad))
-          ))
-          (net nFWE_c (joined
-           (portRef O (instanceRef nFWE_pad))
-           (portRef C (instanceRef C1WR_0_a2_0_3))
-           (portRef B (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef nFWE_pad_RNI420B))
-          ))
-          (net nFWE (joined
-           (portRef nFWE)
-           (portRef I (instanceRef nFWE_pad))
-          ))
-          (net LED_c (joined
-           (portRef Z (instanceRef LED_pad_RNO))
-           (portRef I (instanceRef LED_pad))
-          ))
-          (net LED (joined
-           (portRef O (instanceRef LED_pad))
-           (portRef LED)
-          ))
-          (net (rename RBA_c_0 "RBA_c[0]") (joined
-           (portRef Q (instanceRef RBA_0))
-           (portRef I (instanceRef RBA_pad_0))
-          ))
-          (net (rename RBA_0 "RBA[0]") (joined
-           (portRef O (instanceRef RBA_pad_0))
-           (portRef (member rba 1))
-          ))
-          (net (rename RBA_c_1 "RBA_c[1]") (joined
-           (portRef Q (instanceRef RBA_1))
-           (portRef I (instanceRef RBA_pad_1))
-          ))
-          (net (rename RBA_1 "RBA[1]") (joined
-           (portRef O (instanceRef RBA_pad_1))
-           (portRef (member rba 0))
-          ))
-          (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Z (instanceRef un9_RA_0))
-           (portRef I (instanceRef RA_pad_0))
-          ))
-          (net (rename RA_0 "RA[0]") (joined
-           (portRef O (instanceRef RA_pad_0))
-           (portRef (member ra 11))
-          ))
-          (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Z (instanceRef un9_RA_1))
-           (portRef I (instanceRef RA_pad_1))
-          ))
-          (net (rename RA_1 "RA[1]") (joined
-           (portRef O (instanceRef RA_pad_1))
-           (portRef (member ra 10))
-          ))
-          (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Z (instanceRef un9_RA_2))
-           (portRef I (instanceRef RA_pad_2))
-          ))
-          (net (rename RA_2 "RA[2]") (joined
-           (portRef O (instanceRef RA_pad_2))
-           (portRef (member ra 9))
-          ))
-          (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Z (instanceRef un9_RA_3))
-           (portRef I (instanceRef RA_pad_3))
-          ))
-          (net (rename RA_3 "RA[3]") (joined
-           (portRef O (instanceRef RA_pad_3))
-           (portRef (member ra 8))
-          ))
-          (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Z (instanceRef un9_RA_4))
-           (portRef I (instanceRef RA_pad_4))
-          ))
-          (net (rename RA_4 "RA[4]") (joined
-           (portRef O (instanceRef RA_pad_4))
-           (portRef (member ra 7))
-          ))
-          (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Z (instanceRef un9_RA_5))
-           (portRef I (instanceRef RA_pad_5))
-          ))
-          (net (rename RA_5 "RA[5]") (joined
-           (portRef O (instanceRef RA_pad_5))
-           (portRef (member ra 6))
-          ))
-          (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Z (instanceRef un9_RA_6))
-           (portRef I (instanceRef RA_pad_6))
-          ))
-          (net (rename RA_6 "RA[6]") (joined
-           (portRef O (instanceRef RA_pad_6))
-           (portRef (member ra 5))
-          ))
-          (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Z (instanceRef un9_RA_7))
-           (portRef I (instanceRef RA_pad_7))
-          ))
-          (net (rename RA_7 "RA[7]") (joined
-           (portRef O (instanceRef RA_pad_7))
-           (portRef (member ra 4))
-          ))
-          (net (rename RA_c_8 "RA_c[8]") (joined
-           (portRef Z (instanceRef un9_RA_8))
-           (portRef I (instanceRef RA_pad_8))
-          ))
-          (net (rename RA_8 "RA[8]") (joined
-           (portRef O (instanceRef RA_pad_8))
-           (portRef (member ra 3))
-          ))
-          (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Z (instanceRef un9_RA_9))
-           (portRef I (instanceRef RA_pad_9))
-          ))
-          (net (rename RA_9 "RA[9]") (joined
-           (portRef O (instanceRef RA_pad_9))
-           (portRef (member ra 2))
-          ))
-          (net (rename RA_c_10 "RA_c[10]") (joined
-           (portRef Q (instanceRef RA10))
-           (portRef I (instanceRef RA_pad_10))
-          ))
-          (net (rename RA_10 "RA[10]") (joined
-           (portRef O (instanceRef RA_pad_10))
-           (portRef (member ra 1))
-          ))
-          (net (rename RA_c_11 "RA_c[11]") (joined
-           (portRef Q (instanceRef RA11))
-           (portRef I (instanceRef RA_pad_11))
-          ))
-          (net (rename RA_11 "RA[11]") (joined
-           (portRef O (instanceRef RA_pad_11))
-           (portRef (member ra 0))
-          ))
-          (net (rename RD_in_0 "RD_in[0]") (joined
-           (portRef O (instanceRef RD_pad_0))
-           (portRef I (instanceRef Dout_pad_0))
-          ))
-          (net (rename RD_0 "RD[0]") (joined
-           (portRef B (instanceRef RD_pad_0))
-           (portRef (member rd 7))
-          ))
-          (net (rename RD_in_1 "RD_in[1]") (joined
-           (portRef O (instanceRef RD_pad_1))
-           (portRef I (instanceRef Dout_pad_1))
-          ))
-          (net (rename RD_1 "RD[1]") (joined
-           (portRef B (instanceRef RD_pad_1))
-           (portRef (member rd 6))
-          ))
-          (net (rename RD_in_2 "RD_in[2]") (joined
-           (portRef O (instanceRef RD_pad_2))
-           (portRef I (instanceRef Dout_pad_2))
-          ))
-          (net (rename RD_2 "RD[2]") (joined
-           (portRef B (instanceRef RD_pad_2))
-           (portRef (member rd 5))
-          ))
-          (net (rename RD_in_3 "RD_in[3]") (joined
-           (portRef O (instanceRef RD_pad_3))
-           (portRef I (instanceRef Dout_pad_3))
-          ))
-          (net (rename RD_3 "RD[3]") (joined
-           (portRef B (instanceRef RD_pad_3))
-           (portRef (member rd 4))
-          ))
-          (net (rename RD_in_4 "RD_in[4]") (joined
-           (portRef O (instanceRef RD_pad_4))
-           (portRef I (instanceRef Dout_pad_4))
-          ))
-          (net (rename RD_4 "RD[4]") (joined
-           (portRef B (instanceRef RD_pad_4))
-           (portRef (member rd 3))
-          ))
-          (net (rename RD_in_5 "RD_in[5]") (joined
-           (portRef O (instanceRef RD_pad_5))
-           (portRef I (instanceRef Dout_pad_5))
-          ))
-          (net (rename RD_5 "RD[5]") (joined
-           (portRef B (instanceRef RD_pad_5))
-           (portRef (member rd 2))
-          ))
-          (net (rename RD_in_6 "RD_in[6]") (joined
-           (portRef O (instanceRef RD_pad_6))
-           (portRef I (instanceRef Dout_pad_6))
-          ))
-          (net (rename RD_6 "RD[6]") (joined
-           (portRef B (instanceRef RD_pad_6))
-           (portRef (member rd 1))
-          ))
-          (net (rename RD_in_7 "RD_in[7]") (joined
-           (portRef O (instanceRef RD_pad_7))
-           (portRef I (instanceRef Dout_pad_7))
-          ))
-          (net (rename RD_7 "RD[7]") (joined
-           (portRef B (instanceRef RD_pad_7))
-           (portRef (member rd 0))
-          ))
-          (net nRCS_c (joined
-           (portRef Q (instanceRef nRCS))
-           (portRef I (instanceRef nRCS_pad))
-          ))
-          (net nRCS (joined
-           (portRef O (instanceRef nRCS_pad))
-           (portRef nRCS)
-          ))
-          (net RCLK_c (joined
-           (portRef O (instanceRef RCLK_pad))
-           (portRef CK (instanceRef CASr))
-           (portRef CK (instanceRef CASr2))
-           (portRef CK (instanceRef CASr3))
-           (portRef CK (instanceRef FS_17))
-           (portRef CK (instanceRef FS_16))
-           (portRef CK (instanceRef FS_15))
-           (portRef CK (instanceRef FS_14))
-           (portRef CK (instanceRef FS_13))
-           (portRef CK (instanceRef FS_12))
-           (portRef CK (instanceRef FS_11))
-           (portRef CK (instanceRef FS_10))
-           (portRef CK (instanceRef FS_9))
-           (portRef CK (instanceRef FS_8))
-           (portRef CK (instanceRef FS_7))
-           (portRef CK (instanceRef FS_6))
-           (portRef CK (instanceRef FS_5))
-           (portRef CK (instanceRef FS_4))
-           (portRef CK (instanceRef FS_3))
-           (portRef CK (instanceRef FS_2))
-           (portRef CK (instanceRef FS_1))
-           (portRef CK (instanceRef FS_0))
-           (portRef CK (instanceRef IS_3))
-           (portRef CK (instanceRef IS_2))
-           (portRef CK (instanceRef IS_1))
-           (portRef CK (instanceRef IS_0))
-           (portRef CK (instanceRef InitReady))
-           (portRef CK (instanceRef LEDEN))
-           (portRef CK (instanceRef PHI2r))
-           (portRef CK (instanceRef PHI2r2))
-           (portRef CK (instanceRef PHI2r3))
-           (portRef CK (instanceRef RA10))
-           (portRef CK (instanceRef RASr))
-           (portRef CK (instanceRef RASr2))
-           (portRef CK (instanceRef RASr3))
-           (portRef CK (instanceRef RCKE))
-           (portRef CK (instanceRef RCKEEN))
-           (portRef CK (instanceRef Ready))
-           (portRef CK (instanceRef Ready_fast))
-           (portRef CK (instanceRef S_1))
-           (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef UFMCLK))
-           (portRef CK (instanceRef UFMSDI))
-           (portRef CK (instanceRef n8MEGEN))
-           (portRef CK (instanceRef nRCAS))
-           (portRef CK (instanceRef nRCS))
-           (portRef CK (instanceRef nRRAS))
-           (portRef CK (instanceRef nRWE))
-           (portRef CK (instanceRef nRowColSel))
-           (portRef CK (instanceRef nUFMCS))
-          ))
-          (net RCLK (joined
-           (portRef RCLK)
-           (portRef I (instanceRef RCLK_pad))
-          ))
-          (net RCKE_c (joined
-           (portRef Q (instanceRef RCKE))
-           (portRef C (instanceRef nRRAS_5_u_i_0))
-           (portRef I (instanceRef RCKE_pad))
-           (portRef C (instanceRef nRWE_RNO_3))
-          ))
-          (net RCKE (joined
-           (portRef O (instanceRef RCKE_pad))
-           (portRef RCKE)
-          ))
-          (net nRWE_c (joined
-           (portRef Q (instanceRef nRWE))
-           (portRef I (instanceRef nRWE_pad))
-          ))
-          (net nRWE (joined
-           (portRef O (instanceRef nRWE_pad))
-           (portRef nRWE)
-          ))
-          (net nRRAS_c (joined
-           (portRef Q (instanceRef nRRAS))
-           (portRef I (instanceRef nRRAS_pad))
-          ))
-          (net nRRAS (joined
-           (portRef O (instanceRef nRRAS_pad))
-           (portRef nRRAS)
-          ))
-          (net nRCAS_c (joined
-           (portRef Q (instanceRef nRCAS))
-           (portRef I (instanceRef nRCAS_pad))
-          ))
-          (net nRCAS (joined
-           (portRef O (instanceRef nRCAS_pad))
-           (portRef nRCAS)
-          ))
-          (net RDQMH_c (joined
-           (portRef Z (instanceRef RDQMH))
-           (portRef I (instanceRef RDQMH_pad))
-          ))
-          (net RDQMH (joined
-           (portRef O (instanceRef RDQMH_pad))
-           (portRef RDQMH)
-          ))
-          (net RDQML_c (joined
-           (portRef Z (instanceRef RDQML))
-           (portRef I (instanceRef RDQML_pad))
-          ))
-          (net RDQML (joined
-           (portRef O (instanceRef RDQML_pad))
-           (portRef RDQML)
-          ))
-          (net nUFMCS_c (joined
-           (portRef Q (instanceRef nUFMCS))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef I (instanceRef nUFMCS_pad))
-          ))
-          (net nUFMCS (joined
-           (portRef O (instanceRef nUFMCS_pad))
-           (portRef nUFMCS)
-          ))
-          (net UFMCLK_c (joined
-           (portRef Q (instanceRef UFMCLK))
-           (portRef C (instanceRef UFMCLK_RNO))
-           (portRef I (instanceRef UFMCLK_pad))
-          ))
-          (net UFMCLK (joined
-           (portRef O (instanceRef UFMCLK_pad))
-           (portRef UFMCLK)
-          ))
-          (net UFMSDI_c (joined
-           (portRef Q (instanceRef UFMSDI))
-           (portRef C (instanceRef UFMSDI_RNO))
-           (portRef I (instanceRef UFMSDI_pad))
-          ))
-          (net UFMSDI (joined
-           (portRef O (instanceRef UFMSDI_pad))
-           (portRef UFMSDI)
-          ))
-          (net UFMSDO_c (joined
-           (portRef O (instanceRef UFMSDO_pad))
-           (portRef C (instanceRef LEDEN_5_i_m2))
-           (portRef C (instanceRef n8MEGEN_5_i_m2))
-          ))
-          (net UFMSDO (joined
-           (portRef UFMSDO)
-           (portRef I (instanceRef UFMSDO_pad))
-          ))
-          (net N_460_0 (joined
-           (portRef Z (instanceRef CmdSubmitted_RNO))
-           (portRef D (instanceRef CmdSubmitted))
-          ))
-          (net N_461_0 (joined
-           (portRef Z (instanceRef InitReady_RNO))
-           (portRef D (instanceRef InitReady))
-          ))
-          (net N_462_0 (joined
-           (portRef Z (instanceRef Ready_RNO))
-           (portRef D (instanceRef Ready))
-          ))
-          (net N_463_0 (joined
-           (portRef Z (instanceRef Ready_fast_RNO))
-           (portRef D (instanceRef Ready_fast))
-          ))
-          (net nFWE_c_i (joined
-           (portRef Z (instanceRef nFWE_pad_RNI420B))
-           (portRef D (instanceRef FWEr))
-           (portRef D (instanceRef FWEr_fast))
-          ))
-          (net nCRAS_c_i_0 (joined
-           (portRef Z (instanceRef RASr_RNO))
-           (portRef D (instanceRef RASr))
-          ))
-          (net nCCAS_c_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNISUR8))
-           (portRef D (instanceRef CASr))
-           (portRef D (instanceRef CBR))
-           (portRef D (instanceRef CBR_fast))
-           (portRef CK (instanceRef WRD_7))
-           (portRef CK (instanceRef WRD_6))
-           (portRef CK (instanceRef WRD_5))
-           (portRef CK (instanceRef WRD_4))
-           (portRef CK (instanceRef WRD_3))
-           (portRef CK (instanceRef WRD_2))
-           (portRef CK (instanceRef WRD_1))
-           (portRef CK (instanceRef WRD_0))
-          ))
-          (net Ready_fast_i (joined
-           (portRef Z (instanceRef Ready_fast_RNI29NA))
-           (portRef CD (instanceRef RA11))
-           (portRef CD (instanceRef RBA_1))
-           (portRef CD (instanceRef RBA_0))
-           (portRef PD (instanceRef RowA_9))
-           (portRef CD (instanceRef RowA_8))
-           (portRef CD (instanceRef RowA_7))
-           (portRef CD (instanceRef RowA_6))
-           (portRef PD (instanceRef RowA_5))
-           (portRef CD (instanceRef RowA_4))
-           (portRef CD (instanceRef RowA_3))
-           (portRef CD (instanceRef RowA_2))
-           (portRef CD (instanceRef RowA_1))
-           (portRef CD (instanceRef RowA_0))
-          ))
-          (net (rename IS_i_0 "IS_i[0]") (joined
-           (portRef Z (instanceRef IS_i_0))
-           (portRef D (instanceRef RA10))
-          ))
-          (net RASr2_i (joined
-           (portRef Z (instanceRef RASr2_RNIAFR1))
-           (portRef CD (instanceRef S_1))
-           (portRef CD (instanceRef S_0))
-          ))
-          (net nRWE_RNO_4 (joined
-           (portRef Z (instanceRef nRWE_RNO_4))
-           (portRef BLUT (instanceRef nRWE_RNO_1))
-          ))
-          (net nRWE_RNO_3 (joined
-           (portRef Z (instanceRef nRWE_RNO_3))
-           (portRef ALUT (instanceRef nRWE_RNO_1))
-          ))
-          (net CmdEnable_s_am (joined
-           (portRef Z (instanceRef CmdEnable_s_am))
-           (portRef BLUT (instanceRef CmdEnable_s))
-          ))
-          (net CmdEnable_s_bm (joined
-           (portRef Z (instanceRef CmdEnable_s_bm))
-           (portRef ALUT (instanceRef CmdEnable_s))
-          ))
-         )
-        (property orig_inst_of (string "RAM2GS"))
-       )
-    )
-  )
-  (design RAM2GS (cellRef RAM2GS (libraryRef work))
-	(property PART (string "lcmxo256c-3") ))
-)
+(edif RAM2GS
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timeStamp 2023 8 19 20 53 17)
+      (author "Synopsys, Inc.")
+      (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
+     )
+   )
+  (library LUCENT
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell CCU2 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A0 (direction INPUT))
+           (port B0 (direction INPUT))
+           (port C0 (direction INPUT))
+           (port D0 (direction INPUT))
+           (port A1 (direction INPUT))
+           (port B1 (direction INPUT))
+           (port C1 (direction INPUT))
+           (port D1 (direction INPUT))
+           (port CIN (direction INPUT))
+           (port COUT0 (direction OUTPUT))
+           (port COUT1 (direction OUTPUT))
+           (port S0 (direction OUTPUT))
+           (port S1 (direction OUTPUT))
+         )
+        (property INJECT1_1 (string "NO"))
+        (property INJECT1_0 (string "NO"))
+        (property INIT1 (string "0000"))
+        (property INIT0 (string "0000"))
+       )
+    )
+    (cell BB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port B (direction INOUT))
+           (port I (direction INPUT))
+           (port T (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell OB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell IB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3JX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port PD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3AY (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1S3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell FD1P3AX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
+    (cell ORCALUT4 (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port B (direction INPUT))
+           (port C (direction INPUT))
+           (port D (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell PFUMX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port ALUT (direction INPUT))
+           (port BLUT (direction INPUT))
+           (port C0 (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell GSR (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port GSR (direction INPUT))
+         )
+       )
+    )
+    (cell INV (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port A (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VHI (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VLO (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+  )
+  (library work
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell RAM2GS (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port PHI2 (direction INPUT))
+           (port (array (rename main "MAin[9:0]") 10) (direction INPUT))
+           (port (array (rename crow "CROW[1:0]") 2) (direction INPUT))
+           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
+           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
+           (port nCCAS (direction INPUT))
+           (port nCRAS (direction INPUT))
+           (port nFWE (direction INPUT))
+           (port LED (direction OUTPUT))
+           (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT))
+           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
+           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
+           (port nRCS (direction OUTPUT))
+           (port RCLK (direction INPUT))
+           (port RCKE (direction OUTPUT))
+           (port nRWE (direction OUTPUT))
+           (port nRRAS (direction OUTPUT))
+           (port nRCAS (direction OUTPUT))
+           (port RDQMH (direction OUTPUT))
+           (port RDQML (direction OUTPUT))
+           (port nUFMCS (direction OUTPUT))
+           (port UFMCLK (direction OUTPUT))
+           (port UFMSDI (direction OUTPUT))
+           (port UFMSDO (direction INPUT))
+         )
+         (contents
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))"))
+          )
+          (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))"))
+          )
+          (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
+          )
+          (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
+          )
+          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
+          )
+          (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))"))
+          )
+          (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A)))"))
+          )
+          (instance nRWE_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_0 "WRD[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_1 "WRD[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_2 "WRD[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_3 "WRD[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_4 "WRD[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_5 "WRD[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_6 "WRD[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename WRD_7 "WRD[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMCLK (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RBA_0 "RBA[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename RBA_1 "RBA[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RA11 (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance RA10 (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT)))
+          )
+          (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance PHI2r (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_0 "Bank[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_1 "Bank[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_2 "Bank[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_3 "Bank[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_4 "Bank[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_5 "Bank[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_6 "Bank[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename Bank_7 "Bank[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
+          (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
+          )
+          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
+          )
+          (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C !A)"))
+          )
+          (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !B)+D (!C (!B A)))"))
+          )
+          (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(B+A)))"))
+          )
+          (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(!B+!A)))"))
+          )
+          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !A+D (!C !A+C (B !A)))"))
+          )
+          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (!B A)+C !B))"))
+          )
+          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
+          )
+          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)"))
+          )
+          (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D A)"))
+          )
+          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
+          )
+          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
+          )
+          (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C !A))"))
+          )
+          (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+!A))"))
+          )
+          (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (!B A))"))
+          )
+          (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B A)))"))
+          )
+          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+A))"))
+          )
+          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
+          )
+          (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+!A))"))
+          )
+          (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A)+C B)"))
+          )
+          (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C A)"))
+          )
+          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A+B !A)"))
+          )
+          (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
+          )
+          (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
+          )
+          (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D !B+D (!C (!B A)+C !B))"))
+          )
+          (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))"))
+          )
+          (instance nRWE_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance nRWE_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance nRWE_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))"))
+          )
+          (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))"))
+          )
+          (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A)+C !B)"))
+          )
+          (instance UFMSDI_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
+          )
+          (instance UFMCLK_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B)+D (C (!B !A)))"))
+          )
+          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+A))+D (!C B+C (B+!A)))"))
+          )
+          (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A))"))
+          )
+          (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+!A)))"))
+          )
+          (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A)))"))
+          )
+          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (!C (!B A)))"))
+          )
+          (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
+          )
+          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
+          )
+          (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A+B A)+C A)"))
+          )
+          (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C A)"))
+          )
+          (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))"))
+          )
+          (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x5002"))
+          )
+          (instance (rename FS_cry_0_14 "FS_cry_0[14]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_12 "FS_cry_0[12]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_10 "FS_cry_0[10]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_8 "FS_cry_0[8]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_6 "FS_cry_0[6]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_4 "FS_cry_0[4]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_2 "FS_cry_0[2]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT)))
+           (property INIT0 (string "0x300a"))
+           (property INJECT1_1 (string "NO"))
+           (property INJECT1_0 (string "NO"))
+           (property INIT1 (string "0x300a"))
+          )
+          (net C1WR_0_a2 (joined
+           (portRef Z (instanceRef C1WR_0_a2))
+           (portRef B (instanceRef ADSubmitted_r))
+          ))
+          (net CBR (joined
+           (portRef Q (instanceRef CBR))
+           (portRef A (instanceRef nRWE_RNO_0))
+           (portRef A (instanceRef nRCS_RNO))
+           (portRef A (instanceRef RCKEEN_8_u))
+           (portRef B (instanceRef nRowColSel_0_0_a3_0))
+           (portRef A (instanceRef LED_pad_RNO))
+          ))
+          (net C1Submitted (joined
+           (portRef Q (instanceRef C1Submitted))
+           (portRef D (instanceRef CmdEnable_s_am))
+           (portRef B (instanceRef C1Submitted_RNO))
+          ))
+          (net (rename Bank_2 "Bank[2]") (joined
+           (portRef Q (instanceRef Bank_2))
+           (portRef A (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net Ready (joined
+           (portRef Q (instanceRef Ready))
+           (portRef B (instanceRef IS_RNO_0))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef C (instanceRef nRWE_RNO_2))
+           (portRef D (instanceRef RCKEEN_8_u))
+           (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef D (instanceRef nRowColSel_0_0_a3_0))
+           (portRef D (instanceRef nRRAS_5_u_i_0))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef C (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef C0 (instanceRef nRWE_RNO_1))
+           (portRef A (instanceRef Ready_RNO))
+           (portRef A (instanceRef RCKEEN_8_u_RNO))
+           (portRef A (instanceRef nRowColSel_RNO))
+          ))
+          (net n8MEGEN (joined
+           (portRef Q (instanceRef n8MEGEN))
+           (portRef C (instanceRef RA11_2))
+           (portRef C (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net CO0 (joined
+           (portRef Q (instanceRef S_0))
+           (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef B (instanceRef nRCAS_RNO_0))
+           (portRef B (instanceRef nRWE_RNO_0))
+           (portRef B (instanceRef RCKEEN_8_u_1_0))
+           (portRef A (instanceRef S_0_i_o2_1))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef A (instanceRef S_RNO_0))
+           (portRef A (instanceRef nRowColSel_0_0))
+           (portRef B (instanceRef nRWE_RNO_4))
+           (portRef B (instanceRef nRWE_RNO_3))
+           (portRef C (instanceRef nRowColSel_RNO))
+           (portRef B (instanceRef nRCS_RNO_0))
+          ))
+          (net (rename S_1 "S[1]") (joined
+           (portRef Q (instanceRef S_1))
+           (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef C (instanceRef nRCAS_RNO))
+           (portRef C (instanceRef nRWE_RNO_0))
+           (portRef D (instanceRef RCKEEN_8_u_1_0))
+           (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef B (instanceRef S_0_i_o2_1))
+           (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef B (instanceRef S_RNO_0))
+           (portRef D (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef A (instanceRef nRWE_RNO_4))
+           (portRef A (instanceRef nRWE_RNO_3))
+           (portRef B (instanceRef nRowColSel_RNO))
+          ))
+          (net RASr2 (joined
+           (portRef Q (instanceRef RASr2))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef D (instanceRef nRWE_RNO_5))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef B (instanceRef RCKE_2_0))
+           (portRef B (instanceRef nRRAS_5_u_i_0))
+           (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef D (instanceRef RASr3))
+           (portRef D (instanceRef nRWE_RNO_3))
+           (portRef B (instanceRef RCKEEN_8_u_RNO))
+           (portRef A (instanceRef RASr2_RNIAFR1))
+          ))
+          (net InitReady (joined
+           (portRef Q (instanceRef InitReady))
+           (portRef A (instanceRef UFMCLK_RNO_0))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+           (portRef B (instanceRef LEDEN_5_i_m2))
+           (portRef B (instanceRef n8MEGEN_5_i_m2))
+           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef B (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef PHI2r3_RNITCN41))
+           (portRef C (instanceRef nUFMCS15_0_a2))
+           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef A (instanceRef UFMSDI_ens2_i_a0))
+           (portRef B (instanceRef InitReady_RNO))
+           (portRef D (instanceRef nRWE_RNO_4))
+           (portRef D (instanceRef Ready_RNO))
+           (portRef C (instanceRef RCKEEN_8_u_RNO))
+          ))
+          (net FWEr (joined
+           (portRef Q (instanceRef FWEr))
+           (portRef C (instanceRef nRCAS_RNO_0))
+           (portRef A (instanceRef nRWE_RNO))
+           (portRef C (instanceRef nRowColSel_0_0_a3_0))
+          ))
+          (net CASr3 (joined
+           (portRef Q (instanceRef CASr3))
+           (portRef B (instanceRef nRCAS_RNO_1))
+           (portRef B (instanceRef nRWE_RNO_2))
+           (portRef A (instanceRef nRowColSel_0_0_a3_0))
+           (portRef C (instanceRef nRCS_RNO_0))
+          ))
+          (net (rename IS_0 "IS[0]") (joined
+           (portRef Q (instanceRef IS_0))
+           (portRef A (instanceRef IS_RNO_0))
+           (portRef D (instanceRef nRRAS_RNO))
+           (portRef A (instanceRef nRWE_RNO_5))
+           (portRef A (instanceRef IS_n1_0_x2))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef A (instanceRef IS_RNO_2))
+           (portRef A (instanceRef nRRAS_5_u_i))
+           (portRef D (instanceRef IS_RNO_3))
+           (portRef A (instanceRef IS_i_0))
+          ))
+          (net (rename IS_3 "IS[3]") (joined
+           (portRef Q (instanceRef IS_3))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef RA10_RNO))
+           (portRef A (instanceRef IS_RNO_3))
+          ))
+          (net (rename IS_1 "IS[1]") (joined
+           (portRef Q (instanceRef IS_1))
+           (portRef B (instanceRef nRWE_RNO_5))
+           (portRef B (instanceRef IS_n1_0_x2))
+           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef B (instanceRef IS_RNO_2))
+           (portRef A (instanceRef RA10_RNO))
+           (portRef C (instanceRef IS_RNO_3))
+          ))
+          (net (rename IS_2 "IS[2]") (joined
+           (portRef Q (instanceRef IS_2))
+           (portRef C (instanceRef nRWE_RNO_5))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef C (instanceRef IS_RNO_2))
+           (portRef B (instanceRef RA10_RNO))
+           (portRef B (instanceRef IS_RNO_3))
+          ))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef Q (instanceRef FS_5))
+           (portRef A1 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef D (instanceRef un1_FS_13_i_a2_1))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2))
+          ))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef Q (instanceRef FS_6))
+           (portRef A0 (instanceRef FS_cry_0_6))
+           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef B (instanceRef un1_FS_13_i_a2_6))
+          ))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef Q (instanceRef FS_7))
+           (portRef A1 (instanceRef FS_cry_0_6))
+           (portRef C (instanceRef un1_FS_13_i_a2_6))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2))
+          ))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef Q (instanceRef FS_8))
+           (portRef A0 (instanceRef FS_cry_0_8))
+           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
+          ))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef Q (instanceRef FS_9))
+           (portRef A1 (instanceRef FS_cry_0_8))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2))
+           (portRef B (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net (rename FS_0 "FS[0]") (joined
+           (portRef Q (instanceRef FS_0))
+           (portRef A0 (instanceRef FS_cry_0_0))
+           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef A (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_1 "FS[1]") (joined
+           (portRef Q (instanceRef FS_1))
+           (portRef A1 (instanceRef FS_cry_0_0))
+           (portRef A (instanceRef un1_FS_13_i_a2_6))
+           (portRef A (instanceRef UFMCLK_r_i_m2))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef Q (instanceRef FS_2))
+           (portRef A0 (instanceRef FS_cry_0_2))
+           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef B (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_3 "FS[3]") (joined
+           (portRef Q (instanceRef FS_3))
+           (portRef A1 (instanceRef FS_cry_0_2))
+           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef C (instanceRef un1_FS_13_i_a2_1))
+          ))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef Q (instanceRef FS_10))
+           (portRef A0 (instanceRef FS_cry_0_10))
+           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef D (instanceRef un1_FS_13_i_a2_6))
+           (portRef A (instanceRef InitReady3_0_a2))
+           (portRef A (instanceRef nUFMCS15_0_a2))
+          ))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef Q (instanceRef FS_11))
+           (portRef A1 (instanceRef FS_cry_0_10))
+           (portRef A (instanceRef InitReady3_0_a2_3))
+           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef C (instanceRef UFMCLK_r_i_m2))
+           (portRef B (instanceRef nUFMCS15_0_a2))
+           (portRef C (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef Q (instanceRef FS_12))
+           (portRef A0 (instanceRef FS_cry_0_12))
+           (portRef A (instanceRef InitReady3_0_a2_5))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef Q (instanceRef FS_13))
+           (portRef A1 (instanceRef FS_cry_0_12))
+           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef B (instanceRef InitReady3_0_a2_5))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef Q (instanceRef FS_14))
+           (portRef A0 (instanceRef FS_cry_0_14))
+           (portRef B (instanceRef InitReady3_0_a2_3))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef Q (instanceRef FS_15))
+           (portRef A1 (instanceRef FS_cry_0_14))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef C (instanceRef InitReady3_0_a2_5))
+          ))
+          (net (rename FS_16 "FS[16]") (joined
+           (portRef Q (instanceRef FS_16))
+           (portRef A0 (instanceRef FS_cry_0_16))
+           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
+           (portRef B (instanceRef InitReady3_0_a2))
+          ))
+          (net (rename FS_17 "FS[17]") (joined
+           (portRef Q (instanceRef FS_17))
+           (portRef A1 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef D (instanceRef InitReady3_0_a2_5))
+          ))
+          (net PHI2r2 (joined
+           (portRef Q (instanceRef PHI2r2))
+           (portRef C (instanceRef un1_FS_14_i_a2))
+           (portRef C (instanceRef PHI2r3_RNITCN41))
+           (portRef D (instanceRef PHI2r3))
+          ))
+          (net CmdUFMCS (joined
+           (portRef Q (instanceRef CmdUFMCS))
+           (portRef A (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+          ))
+          (net CASr2 (joined
+           (portRef Q (instanceRef CASr2))
+           (portRef A (instanceRef nRCAS_RNO_1))
+           (portRef A (instanceRef nRWE_RNO_2))
+           (portRef A (instanceRef RCKEEN_8_u_1_0))
+           (portRef D (instanceRef CASr3))
+           (portRef D (instanceRef nRCS_RNO_0))
+          ))
+          (net CASr (joined
+           (portRef Q (instanceRef CASr))
+           (portRef D (instanceRef CASr2))
+          ))
+          (net PHI2r (joined
+           (portRef Q (instanceRef PHI2r))
+           (portRef D (instanceRef PHI2r2))
+          ))
+          (net RASr (joined
+           (portRef Q (instanceRef RASr))
+           (portRef A (instanceRef RCKE_2_0))
+           (portRef D (instanceRef RASr2))
+          ))
+          (net (rename Bank_0 "Bank[0]") (joined
+           (portRef Q (instanceRef Bank_0))
+           (portRef A (instanceRef C1WR_0_a2_0))
+          ))
+          (net (rename Bank_1 "Bank[1]") (joined
+           (portRef Q (instanceRef Bank_1))
+           (portRef B (instanceRef C1WR_0_a2_0))
+          ))
+          (net (rename Bank_3 "Bank[3]") (joined
+           (portRef Q (instanceRef Bank_3))
+           (portRef A (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net (rename Bank_4 "Bank[4]") (joined
+           (portRef Q (instanceRef Bank_4))
+           (portRef B (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net (rename Bank_5 "Bank[5]") (joined
+           (portRef Q (instanceRef Bank_5))
+           (portRef B (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename Bank_6 "Bank[6]") (joined
+           (portRef Q (instanceRef Bank_6))
+           (portRef C (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename Bank_7 "Bank[7]") (joined
+           (portRef Q (instanceRef Bank_7))
+           (portRef D (instanceRef C1WR_0_a2_0_11))
+          ))
+          (net (rename RowA_0 "RowA[0]") (joined
+           (portRef Q (instanceRef RowA_0))
+           (portRef B (instanceRef un9_RA_0))
+          ))
+          (net (rename RowA_1 "RowA[1]") (joined
+           (portRef Q (instanceRef RowA_1))
+           (portRef B (instanceRef un9_RA_1))
+          ))
+          (net (rename RowA_2 "RowA[2]") (joined
+           (portRef Q (instanceRef RowA_2))
+           (portRef B (instanceRef un9_RA_2))
+          ))
+          (net (rename RowA_3 "RowA[3]") (joined
+           (portRef Q (instanceRef RowA_3))
+           (portRef B (instanceRef un9_RA_3))
+          ))
+          (net (rename RowA_4 "RowA[4]") (joined
+           (portRef Q (instanceRef RowA_4))
+           (portRef B (instanceRef un9_RA_4))
+          ))
+          (net (rename RowA_5 "RowA[5]") (joined
+           (portRef Q (instanceRef RowA_5))
+           (portRef B (instanceRef un9_RA_5))
+          ))
+          (net (rename RowA_6 "RowA[6]") (joined
+           (portRef Q (instanceRef RowA_6))
+           (portRef B (instanceRef un9_RA_6))
+          ))
+          (net (rename RowA_7 "RowA[7]") (joined
+           (portRef Q (instanceRef RowA_7))
+           (portRef B (instanceRef un9_RA_7))
+          ))
+          (net (rename RowA_8 "RowA[8]") (joined
+           (portRef Q (instanceRef RowA_8))
+           (portRef B (instanceRef un9_RA_8))
+          ))
+          (net (rename RowA_9 "RowA[9]") (joined
+           (portRef Q (instanceRef RowA_9))
+           (portRef B (instanceRef un9_RA_9))
+          ))
+          (net (rename WRD_0 "WRD[0]") (joined
+           (portRef Q (instanceRef WRD_0))
+           (portRef I (instanceRef RD_pad_0))
+          ))
+          (net (rename WRD_1 "WRD[1]") (joined
+           (portRef Q (instanceRef WRD_1))
+           (portRef I (instanceRef RD_pad_1))
+          ))
+          (net (rename WRD_2 "WRD[2]") (joined
+           (portRef Q (instanceRef WRD_2))
+           (portRef I (instanceRef RD_pad_2))
+          ))
+          (net (rename WRD_3 "WRD[3]") (joined
+           (portRef Q (instanceRef WRD_3))
+           (portRef I (instanceRef RD_pad_3))
+          ))
+          (net (rename WRD_4 "WRD[4]") (joined
+           (portRef Q (instanceRef WRD_4))
+           (portRef I (instanceRef RD_pad_4))
+          ))
+          (net (rename WRD_5 "WRD[5]") (joined
+           (portRef Q (instanceRef WRD_5))
+           (portRef I (instanceRef RD_pad_5))
+          ))
+          (net (rename WRD_6 "WRD[6]") (joined
+           (portRef Q (instanceRef WRD_6))
+           (portRef I (instanceRef RD_pad_6))
+          ))
+          (net (rename WRD_7 "WRD[7]") (joined
+           (portRef Q (instanceRef WRD_7))
+           (portRef I (instanceRef RD_pad_7))
+          ))
+          (net nRowColSel (joined
+           (portRef Q (instanceRef nRowColSel))
+           (portRef B (instanceRef RDQML))
+           (portRef B (instanceRef RDQMH))
+           (portRef C (instanceRef un9_RA_9))
+           (portRef C (instanceRef un9_RA_7))
+           (portRef C (instanceRef un9_RA_6))
+           (portRef C (instanceRef un9_RA_5))
+           (portRef C (instanceRef un9_RA_4))
+           (portRef C (instanceRef un9_RA_3))
+           (portRef C (instanceRef un9_RA_2))
+           (portRef C (instanceRef un9_RA_1))
+           (portRef C (instanceRef un9_RA_0))
+           (portRef C (instanceRef un9_RA_8))
+          ))
+          (net RASr3 (joined
+           (portRef Q (instanceRef RASr3))
+           (portRef C (instanceRef RCKE_2_0))
+          ))
+          (net LEDEN (joined
+           (portRef Q (instanceRef LEDEN))
+           (portRef B (instanceRef LED_pad_RNO))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef A (instanceRef CmdLEDEN_RNO))
+          ))
+          (net CmdLEDEN (joined
+           (portRef Q (instanceRef CmdLEDEN))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef A (instanceRef LEDEN_5_i_m2))
+          ))
+          (net Cmdn8MEGEN (joined
+           (portRef Q (instanceRef Cmdn8MEGEN))
+           (portRef A (instanceRef n8MEGEN_5_i_m2))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net PHI2r3 (joined
+           (portRef Q (instanceRef PHI2r3))
+           (portRef D (instanceRef un1_FS_14_i_a2))
+           (portRef D (instanceRef PHI2r3_RNITCN41))
+          ))
+          (net CmdSubmitted (joined
+           (portRef Q (instanceRef CmdSubmitted))
+           (portRef A (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef PHI2r3_RNITCN41))
+           (portRef B (instanceRef CmdSubmitted_RNO))
+          ))
+          (net (rename FS_4 "FS[4]") (joined
+           (portRef Q (instanceRef FS_4))
+           (portRef A0 (instanceRef FS_cry_0_4))
+           (portRef B (instanceRef UFMCLK_r_i_m2))
+           (portRef A (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net InitReady3 (joined
+           (portRef Z (instanceRef InitReady3_0_a2))
+           (portRef A (instanceRef InitReady_RNO))
+          ))
+          (net RCKEEN (joined
+           (portRef Q (instanceRef RCKEEN))
+           (portRef D (instanceRef RCKE_2_0))
+          ))
+          (net RA11_2 (joined
+           (portRef Z (instanceRef RA11_2))
+           (portRef D (instanceRef RA11))
+          ))
+          (net XOR8MEG (joined
+           (portRef Q (instanceRef XOR8MEG))
+           (portRef B (instanceRef RA11_2))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_0))
+          ))
+          (net nRRAS_0_sqmuxa (joined
+           (portRef Z (instanceRef nRowColSel_RNO))
+           (portRef CD (instanceRef nRowColSel))
+          ))
+          (net nUFMCS15 (joined
+           (portRef Z (instanceRef nUFMCS15_0_a2))
+           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef B (instanceRef UFMCLK_RNO))
+           (portRef B (instanceRef UFMSDI_RNO))
+          ))
+          (net Ready_0_sqmuxa (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef A (instanceRef Ready_fast_RNO))
+          ))
+          (net RCKE_2 (joined
+           (portRef Z (instanceRef RCKE_2_0))
+           (portRef D (instanceRef RCKE))
+          ))
+          (net nRCAS_0_sqmuxa_1 (joined
+           (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef B (instanceRef nRCAS_RNO))
+           (portRef C (instanceRef nRWE_RNO))
+          ))
+          (net XOR8MEG18 (joined
+           (portRef Z (instanceRef XOR8MEG18_0_a2))
+           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef SP (instanceRef CmdLEDEN))
+           (portRef SP (instanceRef Cmdn8MEGEN))
+           (portRef SP (instanceRef XOR8MEG))
+          ))
+          (net CmdEnable (joined
+           (portRef Q (instanceRef CmdEnable))
+           (portRef A (instanceRef XOR8MEG18_0_a2))
+           (portRef B (instanceRef CmdEnable_s_am))
+           (portRef A (instanceRef CmdEnable_s_bm))
+          ))
+          (net CmdEnable16 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2))
+           (portRef D (instanceRef ADSubmitted_r))
+           (portRef C0 (instanceRef CmdEnable_s))
+           (portRef A (instanceRef C1Submitted_RNO))
+          ))
+          (net CmdEnable17 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2))
+           (portRef C (instanceRef ADSubmitted_r))
+           (portRef A (instanceRef CmdEnable_s_am))
+          ))
+          (net CmdSubmitted_1_sqmuxa (joined
+           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdSubmitted_RNO))
+          ))
+          (net CmdUFMCLK_1_sqmuxa (joined
+           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef SP (instanceRef CmdUFMCLK))
+           (portRef SP (instanceRef CmdUFMCS))
+           (portRef SP (instanceRef CmdUFMSDI))
+          ))
+          (net CmdUFMCLK (joined
+           (portRef Q (instanceRef CmdUFMCLK))
+           (portRef B (instanceRef UFMCLK_RNO_0))
+          ))
+          (net CmdUFMSDI (joined
+           (portRef Q (instanceRef CmdUFMSDI))
+           (portRef A (instanceRef UFMSDI_RNO_0))
+          ))
+          (net ADSubmitted (joined
+           (portRef Q (instanceRef ADSubmitted))
+           (portRef A (instanceRef ADSubmitted_r))
+           (portRef B (instanceRef CmdEnable_s_bm))
+          ))
+          (net C1Submitted_RNO (joined
+           (portRef Z (instanceRef C1Submitted_RNO))
+           (portRef D (instanceRef C1Submitted))
+          ))
+          (net ADSubmitted_r (joined
+           (portRef Z (instanceRef ADSubmitted_r))
+           (portRef D (instanceRef ADSubmitted))
+          ))
+          (net UFMSDI_RNO (joined
+           (portRef Z (instanceRef UFMSDI_RNO))
+           (portRef D (instanceRef UFMSDI))
+          ))
+          (net CmdEnable_s (joined
+           (portRef Z (instanceRef CmdEnable_s))
+           (portRef D (instanceRef CmdEnable))
+          ))
+          (net nRowColSel_0_0 (joined
+           (portRef Z (instanceRef nRowColSel_0_0))
+           (portRef D (instanceRef nRowColSel))
+          ))
+          (net RCKEEN_8 (joined
+           (portRef Z (instanceRef RCKEEN_8_u))
+           (portRef D (instanceRef RCKEEN))
+          ))
+          (net N_31 (joined
+           (portRef Z (instanceRef un1_FS_14_i_0))
+           (portRef SP (instanceRef n8MEGEN))
+          ))
+          (net N_33 (joined
+           (portRef Z (instanceRef un1_FS_13_i_0))
+           (portRef SP (instanceRef LEDEN))
+          ))
+          (net N_24 (joined
+           (portRef Z (instanceRef nRRAS_5_u_i))
+           (portRef B (instanceRef nRCS_RNO))
+          ))
+          (net N_41 (joined
+           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef A (instanceRef nRCAS_RNO))
+          ))
+          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
+           (portRef Z (instanceRef S_0_i_o2_1))
+           (portRef A (instanceRef nRRAS_5_u_i_0))
+           (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+           (portRef D (instanceRef S_1))
+           (portRef D (instanceRef RCKEEN_8_u_RNO))
+          ))
+          (net N_159 (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef D (instanceRef RA10_RNO))
+          ))
+          (net N_165 (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef C (instanceRef Ready_RNO))
+          ))
+          (net N_95_5 (joined
+           (portRef Z (instanceRef InitReady3_0_a2_5))
+           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef D (instanceRef InitReady3_0_a2))
+          ))
+          (net N_95_3 (joined
+           (portRef Z (instanceRef InitReady3_0_a2_3))
+           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef C (instanceRef InitReady3_0_a2))
+          ))
+          (net N_51 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
+           (portRef D (instanceRef UFMCLK_r_i_m2))
+           (portRef D (instanceRef nUFMCS15_0_a2))
+           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef B (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net N_126 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
+           (portRef C (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net N_151 (joined
+           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
+           (portRef C (instanceRef UFMSDI_RNO_0))
+           (portRef D (instanceRef un1_FS_13_i_a2_8))
+          ))
+          (net N_137_8 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_8))
+           (portRef C (instanceRef un1_FS_13_i_0))
+           (portRef C (instanceRef un1_FS_14_i_0))
+          ))
+          (net N_129 (joined
+           (portRef Z (instanceRef UFMCLK_r_i_m2))
+           (portRef D (instanceRef UFMCLK_RNO_0))
+          ))
+          (net N_155 (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef C (instanceRef IS_RNO_0))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef C (instanceRef nRRAS_RNO))
+           (portRef A (instanceRef IS_0_sqmuxa_0_o2))
+           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef B (instanceRef nRRAS_5_u_i))
+          ))
+          (net N_56_i (joined
+           (portRef Z (instanceRef IS_n1_0_x2))
+           (portRef D (instanceRef IS_1))
+          ))
+          (net N_160 (joined
+           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef B (instanceRef nRRAS_RNO))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef C (instanceRef nRRAS_5_u_i))
+          ))
+          (net N_136 (joined
+           (portRef Z (instanceRef un1_FS_14_i_a2))
+           (portRef A (instanceRef un1_FS_13_i_0))
+           (portRef A (instanceRef un1_FS_14_i_0))
+          ))
+          (net N_69 (joined
+           (portRef Z (instanceRef n8MEGEN_5_i_m2))
+           (portRef D (instanceRef n8MEGEN))
+          ))
+          (net N_70 (joined
+           (portRef Z (instanceRef LEDEN_5_i_m2))
+           (portRef D (instanceRef LEDEN))
+          ))
+          (net N_137_6 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_6))
+           (portRef B (instanceRef un1_FS_13_i_0))
+           (portRef B (instanceRef un1_FS_14_i_0))
+          ))
+          (net XOR8MEG_3 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef D (instanceRef XOR8MEG))
+          ))
+          (net CmdEnable16_1 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_1))
+           (portRef A (instanceRef CmdEnable16_0_a2_5))
+          ))
+          (net N_43 (joined
+           (portRef Z (instanceRef CmdEnable17_0_o2))
+           (portRef D (instanceRef CmdEnable17_0_a2_4))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net N_147 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0))
+           (portRef A (instanceRef un1_CMDWR))
+           (portRef C (instanceRef CmdEnable16_0_a2))
+           (portRef B (instanceRef C1WR_0_a2))
+           (portRef D (instanceRef XOR8MEG18_0_a2))
+           (portRef D (instanceRef CmdEnable17_0_a2))
+           (portRef C (instanceRef C1Submitted_RNO))
+          ))
+          (net CmdEnable16_4 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_4))
+           (portRef A (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net un1_Din_4 (joined
+           (portRef Z (instanceRef un1_Din_4))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_0))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a3_2))
+          ))
+          (net N_171 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a3_3))
+          ))
+          (net N_128 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net N_152 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef CmdLEDEN_RNO))
+           (portRef B (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net N_132 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef B (instanceRef CmdLEDEN_RNO))
+          ))
+          (net N_133 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef C (instanceRef CmdLEDEN_RNO))
+          ))
+          (net un1_CMDWR (joined
+           (portRef Z (instanceRef un1_CMDWR))
+           (portRef C (instanceRef CmdEnable_s_am))
+          ))
+          (net N_179 (joined
+           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
+           (portRef B (instanceRef nRowColSel_0_0))
+          ))
+          (net XOR8MEG_3_u_0_a3_2 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a3_3))
+          ))
+          (net UFMCLK_r_i_a2_2_2 (joined
+           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef C (instanceRef UFMCLK_RNO_0))
+           (portRef C (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+          ))
+          (net UFMCLK_RNO (joined
+           (portRef Z (instanceRef UFMCLK_RNO))
+           (portRef D (instanceRef UFMCLK))
+          ))
+          (net UFMSDI_ens2_i_a0 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
+           (portRef B (instanceRef UFMSDI_RNO_0))
+          ))
+          (net RCKEEN_8_u_0_0 (joined
+           (portRef Z (instanceRef RCKEEN_8_u_RNO))
+           (portRef B (instanceRef RCKEEN_8_u))
+          ))
+          (net RCKEEN_8_u_0_a2_1_out (joined
+           (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s))
+           (portRef D (instanceRef nRCS_RNO))
+          ))
+          (net nCRAS_c_i (joined
+           (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
+           (portRef CK (instanceRef CBR))
+           (portRef CK (instanceRef CBR_fast))
+           (portRef CK (instanceRef FWEr))
+           (portRef CK (instanceRef FWEr_fast))
+           (portRef CK (instanceRef RBA_1))
+           (portRef CK (instanceRef RBA_0))
+           (portRef CK (instanceRef RowA_9))
+           (portRef CK (instanceRef RowA_8))
+           (portRef CK (instanceRef RowA_7))
+           (portRef CK (instanceRef RowA_6))
+           (portRef CK (instanceRef RowA_5))
+           (portRef CK (instanceRef RowA_4))
+           (portRef CK (instanceRef RowA_3))
+           (portRef CK (instanceRef RowA_2))
+           (portRef CK (instanceRef RowA_1))
+           (portRef CK (instanceRef RowA_0))
+          ))
+          (net N_159_i (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef SP (instanceRef IS_3))
+           (portRef SP (instanceRef IS_2))
+           (portRef SP (instanceRef IS_1))
+          ))
+          (net RD_1_i (joined
+           (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef T (instanceRef RD_pad_0))
+           (portRef T (instanceRef RD_pad_1))
+           (portRef T (instanceRef RD_pad_2))
+           (portRef T (instanceRef RD_pad_3))
+           (portRef T (instanceRef RD_pad_4))
+           (portRef T (instanceRef RD_pad_5))
+           (portRef T (instanceRef RD_pad_6))
+           (portRef T (instanceRef RD_pad_7))
+          ))
+          (net N_28_i (joined
+           (portRef Z (instanceRef nRCS_RNO))
+           (portRef D (instanceRef nRCS))
+          ))
+          (net N_37_i (joined
+           (portRef Z (instanceRef nRCAS_RNO))
+           (portRef D (instanceRef nRCAS))
+          ))
+          (net N_24_i (joined
+           (portRef Z (instanceRef nRRAS_RNO))
+           (portRef D (instanceRef nRRAS))
+          ))
+          (net nUFMCS_s_0_N_5_i (joined
+           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef D (instanceRef nUFMCS))
+          ))
+          (net N_39_i (joined
+           (portRef Z (instanceRef nRWE_RNO))
+           (portRef D (instanceRef nRWE))
+          ))
+          (net N_64_i_i (joined
+           (portRef Z (instanceRef IS_RNO_0))
+           (portRef D (instanceRef IS_0))
+          ))
+          (net N_61_i_i (joined
+           (portRef Z (instanceRef IS_RNO_3))
+           (portRef D (instanceRef IS_3))
+          ))
+          (net N_60_i_i (joined
+           (portRef Z (instanceRef IS_RNO_2))
+           (portRef D (instanceRef IS_2))
+          ))
+          (net N_177_i (joined
+           (portRef Z (instanceRef S_RNO_0))
+           (portRef D (instanceRef S_0))
+          ))
+          (net N_21_i (joined
+           (portRef Z (instanceRef CmdLEDEN_RNO))
+           (portRef D (instanceRef CmdLEDEN))
+          ))
+          (net N_19_i (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_RNO))
+           (portRef D (instanceRef Cmdn8MEGEN))
+          ))
+          (net N_139_i (joined
+           (portRef Z (instanceRef PHI2r3_RNITCN41))
+           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef A (instanceRef UFMCLK_RNO))
+           (portRef A (instanceRef UFMSDI_RNO))
+          ))
+          (net (rename FS_cry_0 "FS_cry[0]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_0))
+          ))
+          (net (rename FS_s_0 "FS_s[0]") (joined
+           (portRef S0 (instanceRef FS_cry_0_0))
+           (portRef D (instanceRef FS_0))
+          ))
+          (net (rename FS_cry_1 "FS_cry[1]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_0))
+           (portRef CIN (instanceRef FS_cry_0_2))
+          ))
+          (net (rename FS_s_1 "FS_s[1]") (joined
+           (portRef S1 (instanceRef FS_cry_0_0))
+           (portRef D (instanceRef FS_1))
+          ))
+          (net (rename FS_cry_2 "FS_cry[2]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_2))
+          ))
+          (net (rename FS_s_2 "FS_s[2]") (joined
+           (portRef S0 (instanceRef FS_cry_0_2))
+           (portRef D (instanceRef FS_2))
+          ))
+          (net (rename FS_cry_3 "FS_cry[3]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_2))
+           (portRef CIN (instanceRef FS_cry_0_4))
+          ))
+          (net (rename FS_s_3 "FS_s[3]") (joined
+           (portRef S1 (instanceRef FS_cry_0_2))
+           (portRef D (instanceRef FS_3))
+          ))
+          (net (rename FS_cry_4 "FS_cry[4]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_4))
+          ))
+          (net (rename FS_s_4 "FS_s[4]") (joined
+           (portRef S0 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef FS_4))
+          ))
+          (net (rename FS_cry_5 "FS_cry[5]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_4))
+           (portRef CIN (instanceRef FS_cry_0_6))
+          ))
+          (net (rename FS_s_5 "FS_s[5]") (joined
+           (portRef S1 (instanceRef FS_cry_0_4))
+           (portRef D (instanceRef FS_5))
+          ))
+          (net (rename FS_cry_6 "FS_cry[6]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_6))
+          ))
+          (net (rename FS_s_6 "FS_s[6]") (joined
+           (portRef S0 (instanceRef FS_cry_0_6))
+           (portRef D (instanceRef FS_6))
+          ))
+          (net (rename FS_cry_7 "FS_cry[7]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_6))
+           (portRef CIN (instanceRef FS_cry_0_8))
+          ))
+          (net (rename FS_s_7 "FS_s[7]") (joined
+           (portRef S1 (instanceRef FS_cry_0_6))
+           (portRef D (instanceRef FS_7))
+          ))
+          (net (rename FS_cry_8 "FS_cry[8]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_8))
+          ))
+          (net (rename FS_s_8 "FS_s[8]") (joined
+           (portRef S0 (instanceRef FS_cry_0_8))
+           (portRef D (instanceRef FS_8))
+          ))
+          (net (rename FS_cry_9 "FS_cry[9]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_8))
+           (portRef CIN (instanceRef FS_cry_0_10))
+          ))
+          (net (rename FS_s_9 "FS_s[9]") (joined
+           (portRef S1 (instanceRef FS_cry_0_8))
+           (portRef D (instanceRef FS_9))
+          ))
+          (net (rename FS_cry_10 "FS_cry[10]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_10))
+          ))
+          (net (rename FS_s_10 "FS_s[10]") (joined
+           (portRef S0 (instanceRef FS_cry_0_10))
+           (portRef D (instanceRef FS_10))
+          ))
+          (net (rename FS_cry_11 "FS_cry[11]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_10))
+           (portRef CIN (instanceRef FS_cry_0_12))
+          ))
+          (net (rename FS_s_11 "FS_s[11]") (joined
+           (portRef S1 (instanceRef FS_cry_0_10))
+           (portRef D (instanceRef FS_11))
+          ))
+          (net (rename FS_cry_12 "FS_cry[12]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_12))
+          ))
+          (net (rename FS_s_12 "FS_s[12]") (joined
+           (portRef S0 (instanceRef FS_cry_0_12))
+           (portRef D (instanceRef FS_12))
+          ))
+          (net (rename FS_cry_13 "FS_cry[13]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_12))
+           (portRef CIN (instanceRef FS_cry_0_14))
+          ))
+          (net (rename FS_s_13 "FS_s[13]") (joined
+           (portRef S1 (instanceRef FS_cry_0_12))
+           (portRef D (instanceRef FS_13))
+          ))
+          (net (rename FS_cry_14 "FS_cry[14]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_14))
+          ))
+          (net (rename FS_s_14 "FS_s[14]") (joined
+           (portRef S0 (instanceRef FS_cry_0_14))
+           (portRef D (instanceRef FS_14))
+          ))
+          (net (rename FS_cry_15 "FS_cry[15]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_14))
+           (portRef CIN (instanceRef FS_cry_0_16))
+          ))
+          (net (rename FS_s_15 "FS_s[15]") (joined
+           (portRef S1 (instanceRef FS_cry_0_14))
+           (portRef D (instanceRef FS_15))
+          ))
+          (net (rename FS_cry_16 "FS_cry[16]") (joined
+           (portRef COUT0 (instanceRef FS_cry_0_16))
+          ))
+          (net (rename FS_s_16 "FS_s[16]") (joined
+           (portRef S0 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef FS_16))
+          ))
+          (net (rename FS_s_17 "FS_s[17]") (joined
+           (portRef S1 (instanceRef FS_cry_0_16))
+           (portRef D (instanceRef FS_17))
+          ))
+          (net RA10s_i (joined
+           (portRef Z (instanceRef RA10_RNO))
+           (portRef PD (instanceRef RA10))
+          ))
+          (net Cmdn8MEGEN_4_u_i_0 (joined
+           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
+           (portRef A (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net UFMSDI_ens2_i_o2_0_3 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
+          ))
+          (net C1WR_0_a2_0_3 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_3))
+           (portRef C (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net C1WR_0_a2_0_4 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef C1WR_0_a2_0_10))
+          ))
+          (net C1WR_0_a2_0_10 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_10))
+           (portRef C (instanceRef C1WR_0_a2_0))
+          ))
+          (net C1WR_0_a2_0_11 (joined
+           (portRef Z (instanceRef C1WR_0_a2_0_11))
+           (portRef D (instanceRef C1WR_0_a2_0))
+          ))
+          (net Ready_0_sqmuxa_0_a3_2 (joined
+           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
+           (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef Ready_RNO))
+          ))
+          (net UFMSDI_ens2_i_a2_4_2 (joined
+           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
+           (portRef D (instanceRef UFMSDI_ens2_i_a0))
+          ))
+          (net CmdEnable16_0_a2_4 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef CmdEnable16_0_a2))
+          ))
+          (net CmdEnable16_0_a2_5 (joined
+           (portRef Z (instanceRef CmdEnable16_0_a2_5))
+           (portRef B (instanceRef CmdEnable16_0_a2))
+          ))
+          (net nRRAS_5_u_i_0 (joined
+           (portRef Z (instanceRef nRRAS_5_u_i_0))
+           (portRef A (instanceRef nRRAS_RNO))
+           (portRef D (instanceRef nRRAS_5_u_i))
+          ))
+          (net CmdEnable17_0_a2_3 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable17_0_a2))
+          ))
+          (net CmdEnable17_0_a2_4 (joined
+           (portRef Z (instanceRef CmdEnable17_0_a2_4))
+           (portRef B (instanceRef CmdEnable17_0_a2))
+          ))
+          (net un1_FS_13_i_a2_1 (joined
+           (portRef Z (instanceRef un1_FS_13_i_a2_1))
+           (portRef D (instanceRef un1_FS_13_i_0))
+          ))
+          (net un1_FS_14_i_a2_0_1 (joined
+           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
+           (portRef D (instanceRef un1_FS_14_i_0))
+          ))
+          (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined
+           (portRef COUT1 (instanceRef FS_cry_0_16))
+          ))
+          (net RCKEEN_8_u_1 (joined
+           (portRef Z (instanceRef RCKEEN_8_u_1_0))
+           (portRef C (instanceRef RCKEEN_8_u))
+          ))
+          (net N_28_i_1 (joined
+           (portRef Z (instanceRef nRCS_RNO_0))
+           (portRef C (instanceRef nRCS_RNO))
+          ))
+          (net m18_0_a3_3 (joined
+           (portRef Z (instanceRef nRWE_RNO_5))
+           (portRef C (instanceRef nRWE_RNO_4))
+          ))
+          (net m18_0_a2_1 (joined
+           (portRef Z (instanceRef nRWE_RNO_1))
+           (portRef D (instanceRef nRWE_RNO))
+          ))
+          (net m6_0_a2_2 (joined
+           (portRef Z (instanceRef nRWE_RNO_2))
+           (portRef D (instanceRef nRWE_RNO_0))
+          ))
+          (net G_17_1 (joined
+           (portRef Z (instanceRef nRWE_RNO_0))
+           (portRef B (instanceRef nRWE_RNO))
+          ))
+          (net g0_1 (joined
+           (portRef Z (instanceRef nRCAS_RNO_0))
+           (portRef D (instanceRef nRCAS_RNO))
+          ))
+          (net g4_0_0_0 (joined
+           (portRef Z (instanceRef nRCAS_RNO_1))
+           (portRef D (instanceRef nRCAS_RNO_0))
+          ))
+          (net CBR_fast (joined
+           (portRef Q (instanceRef CBR_fast))
+           (portRef A (instanceRef nRCAS_RNO_0))
+           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+          ))
+          (net FWEr_fast (joined
+           (portRef Q (instanceRef FWEr_fast))
+           (portRef C (instanceRef RCKEEN_8_u_1_0))
+           (portRef A (instanceRef nRCS_RNO_0))
+          ))
+          (net Ready_fast (joined
+           (portRef Q (instanceRef Ready_fast))
+           (portRef B (instanceRef Ready_fast_RNO))
+           (portRef A (instanceRef Ready_fast_RNI29NA))
+          ))
+          (net UFMSDI_r_xx_mm_1 (joined
+           (portRef Z (instanceRef UFMSDI_RNO_0))
+           (portRef D (instanceRef UFMSDI_RNO))
+          ))
+          (net UFMCLK_r_i_m4_xx_mm_1 (joined
+           (portRef Z (instanceRef UFMCLK_RNO_0))
+           (portRef D (instanceRef UFMCLK_RNO))
+          ))
+          (net nUFMCS_s_0_N_5_i_N_2L1 (joined
+           (portRef Z (instanceRef nUFMCS_s_0_N_5_i_N_2L1))
+           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
+          ))
+          (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
+           (portRef Z (instanceRef XOR8MEG_CN))
+           (portRef CK (instanceRef ADSubmitted))
+           (portRef CK (instanceRef C1Submitted))
+           (portRef CK (instanceRef CmdEnable))
+           (portRef CK (instanceRef CmdLEDEN))
+           (portRef CK (instanceRef CmdSubmitted))
+           (portRef CK (instanceRef CmdUFMCLK))
+           (portRef CK (instanceRef CmdUFMCS))
+           (portRef CK (instanceRef CmdUFMSDI))
+           (portRef CK (instanceRef Cmdn8MEGEN))
+           (portRef CK (instanceRef XOR8MEG))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef CIN (instanceRef FS_cry_0_0))
+           (portRef GSR (instanceRef GSR_INST))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef D1 (instanceRef FS_cry_0_0))
+           (portRef C1 (instanceRef FS_cry_0_0))
+           (portRef B1 (instanceRef FS_cry_0_0))
+           (portRef D0 (instanceRef FS_cry_0_0))
+           (portRef C0 (instanceRef FS_cry_0_0))
+           (portRef B0 (instanceRef FS_cry_0_0))
+           (portRef D1 (instanceRef FS_cry_0_2))
+           (portRef C1 (instanceRef FS_cry_0_2))
+           (portRef B1 (instanceRef FS_cry_0_2))
+           (portRef D0 (instanceRef FS_cry_0_2))
+           (portRef C0 (instanceRef FS_cry_0_2))
+           (portRef B0 (instanceRef FS_cry_0_2))
+           (portRef D1 (instanceRef FS_cry_0_4))
+           (portRef C1 (instanceRef FS_cry_0_4))
+           (portRef B1 (instanceRef FS_cry_0_4))
+           (portRef D0 (instanceRef FS_cry_0_4))
+           (portRef C0 (instanceRef FS_cry_0_4))
+           (portRef B0 (instanceRef FS_cry_0_4))
+           (portRef D1 (instanceRef FS_cry_0_6))
+           (portRef C1 (instanceRef FS_cry_0_6))
+           (portRef B1 (instanceRef FS_cry_0_6))
+           (portRef D0 (instanceRef FS_cry_0_6))
+           (portRef C0 (instanceRef FS_cry_0_6))
+           (portRef B0 (instanceRef FS_cry_0_6))
+           (portRef D1 (instanceRef FS_cry_0_8))
+           (portRef C1 (instanceRef FS_cry_0_8))
+           (portRef B1 (instanceRef FS_cry_0_8))
+           (portRef D0 (instanceRef FS_cry_0_8))
+           (portRef C0 (instanceRef FS_cry_0_8))
+           (portRef B0 (instanceRef FS_cry_0_8))
+           (portRef D1 (instanceRef FS_cry_0_10))
+           (portRef C1 (instanceRef FS_cry_0_10))
+           (portRef B1 (instanceRef FS_cry_0_10))
+           (portRef D0 (instanceRef FS_cry_0_10))
+           (portRef C0 (instanceRef FS_cry_0_10))
+           (portRef B0 (instanceRef FS_cry_0_10))
+           (portRef D1 (instanceRef FS_cry_0_12))
+           (portRef C1 (instanceRef FS_cry_0_12))
+           (portRef B1 (instanceRef FS_cry_0_12))
+           (portRef D0 (instanceRef FS_cry_0_12))
+           (portRef C0 (instanceRef FS_cry_0_12))
+           (portRef B0 (instanceRef FS_cry_0_12))
+           (portRef D1 (instanceRef FS_cry_0_14))
+           (portRef C1 (instanceRef FS_cry_0_14))
+           (portRef B1 (instanceRef FS_cry_0_14))
+           (portRef D0 (instanceRef FS_cry_0_14))
+           (portRef C0 (instanceRef FS_cry_0_14))
+           (portRef B0 (instanceRef FS_cry_0_14))
+           (portRef D1 (instanceRef FS_cry_0_16))
+           (portRef C1 (instanceRef FS_cry_0_16))
+           (portRef B1 (instanceRef FS_cry_0_16))
+           (portRef D0 (instanceRef FS_cry_0_16))
+           (portRef C0 (instanceRef FS_cry_0_16))
+           (portRef B0 (instanceRef FS_cry_0_16))
+          ))
+          (net PHI2_c (joined
+           (portRef O (instanceRef PHI2_pad))
+           (portRef CK (instanceRef Bank_7))
+           (portRef CK (instanceRef Bank_6))
+           (portRef CK (instanceRef Bank_5))
+           (portRef CK (instanceRef Bank_4))
+           (portRef CK (instanceRef Bank_3))
+           (portRef CK (instanceRef Bank_2))
+           (portRef CK (instanceRef Bank_1))
+           (portRef CK (instanceRef Bank_0))
+           (portRef D (instanceRef PHI2r))
+           (portRef CK (instanceRef RA11))
+           (portRef A (instanceRef XOR8MEG_CN))
+          ))
+          (net PHI2 (joined
+           (portRef PHI2)
+           (portRef I (instanceRef PHI2_pad))
+          ))
+          (net (rename MAin_c_0 "MAin_c[0]") (joined
+           (portRef O (instanceRef MAin_pad_0))
+           (portRef B (instanceRef un1_CMDWR))
+           (portRef A (instanceRef un9_RA_0))
+           (portRef D (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef B (instanceRef XOR8MEG18_0_a2))
+           (portRef C (instanceRef CmdEnable17_0_a2))
+           (portRef D (instanceRef RowA_0))
+          ))
+          (net (rename MAin_0 "MAin[0]") (joined
+           (portRef (member main 9))
+           (portRef I (instanceRef MAin_pad_0))
+          ))
+          (net (rename MAin_c_1 "MAin_c[1]") (joined
+           (portRef O (instanceRef MAin_pad_1))
+           (portRef C (instanceRef un1_CMDWR))
+           (portRef A (instanceRef un9_RA_1))
+           (portRef C (instanceRef CmdEnable17_0_a2_4))
+           (portRef D (instanceRef CmdEnable16_0_a2_5))
+           (portRef A (instanceRef C1WR_0_a2))
+           (portRef C (instanceRef XOR8MEG18_0_a2))
+           (portRef D (instanceRef RowA_1))
+           (portRef D (instanceRef C1Submitted_RNO))
+          ))
+          (net (rename MAin_1 "MAin[1]") (joined
+           (portRef (member main 8))
+           (portRef I (instanceRef MAin_pad_1))
+          ))
+          (net (rename MAin_c_2 "MAin_c[2]") (joined
+           (portRef O (instanceRef MAin_pad_2))
+           (portRef A (instanceRef un9_RA_2))
+           (portRef A (instanceRef C1WR_0_a2_0_3))
+           (portRef D (instanceRef RowA_2))
+          ))
+          (net (rename MAin_2 "MAin[2]") (joined
+           (portRef (member main 7))
+           (portRef I (instanceRef MAin_pad_2))
+          ))
+          (net (rename MAin_c_3 "MAin_c[3]") (joined
+           (portRef O (instanceRef MAin_pad_3))
+           (portRef A (instanceRef un9_RA_3))
+           (portRef B (instanceRef C1WR_0_a2_0_3))
+           (portRef D (instanceRef RowA_3))
+          ))
+          (net (rename MAin_3 "MAin[3]") (joined
+           (portRef (member main 6))
+           (portRef I (instanceRef MAin_pad_3))
+          ))
+          (net (rename MAin_c_4 "MAin_c[4]") (joined
+           (portRef O (instanceRef MAin_pad_4))
+           (portRef A (instanceRef un9_RA_4))
+           (portRef A (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_4))
+          ))
+          (net (rename MAin_4 "MAin[4]") (joined
+           (portRef (member main 5))
+           (portRef I (instanceRef MAin_pad_4))
+          ))
+          (net (rename MAin_c_5 "MAin_c[5]") (joined
+           (portRef O (instanceRef MAin_pad_5))
+           (portRef A (instanceRef un9_RA_5))
+           (portRef B (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_5))
+          ))
+          (net (rename MAin_5 "MAin[5]") (joined
+           (portRef (member main 4))
+           (portRef I (instanceRef MAin_pad_5))
+          ))
+          (net (rename MAin_c_6 "MAin_c[6]") (joined
+           (portRef O (instanceRef MAin_pad_6))
+           (portRef A (instanceRef un9_RA_6))
+           (portRef C (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_6))
+          ))
+          (net (rename MAin_6 "MAin[6]") (joined
+           (portRef (member main 3))
+           (portRef I (instanceRef MAin_pad_6))
+          ))
+          (net (rename MAin_c_7 "MAin_c[7]") (joined
+           (portRef O (instanceRef MAin_pad_7))
+           (portRef A (instanceRef un9_RA_7))
+           (portRef D (instanceRef C1WR_0_a2_0_4))
+           (portRef D (instanceRef RowA_7))
+          ))
+          (net (rename MAin_7 "MAin[7]") (joined
+           (portRef (member main 2))
+           (portRef I (instanceRef MAin_pad_7))
+          ))
+          (net (rename MAin_c_8 "MAin_c[8]") (joined
+           (portRef O (instanceRef MAin_pad_8))
+           (portRef A (instanceRef un9_RA_8))
+           (portRef D (instanceRef RowA_8))
+          ))
+          (net (rename MAin_8 "MAin[8]") (joined
+           (portRef (member main 1))
+           (portRef I (instanceRef MAin_pad_8))
+          ))
+          (net (rename MAin_c_9 "MAin_c[9]") (joined
+           (portRef O (instanceRef MAin_pad_9))
+           (portRef A (instanceRef RDQML))
+           (portRef A (instanceRef RDQMH))
+           (portRef A (instanceRef un9_RA_9))
+           (portRef D (instanceRef RowA_9))
+          ))
+          (net (rename MAin_9 "MAin[9]") (joined
+           (portRef (member main 0))
+           (portRef I (instanceRef MAin_pad_9))
+          ))
+          (net (rename CROW_c_0 "CROW_c[0]") (joined
+           (portRef O (instanceRef CROW_pad_0))
+           (portRef D (instanceRef RBA_0))
+          ))
+          (net (rename CROW_0 "CROW[0]") (joined
+           (portRef (member crow 1))
+           (portRef I (instanceRef CROW_pad_0))
+          ))
+          (net (rename CROW_c_1 "CROW_c[1]") (joined
+           (portRef O (instanceRef CROW_pad_1))
+           (portRef D (instanceRef RBA_1))
+          ))
+          (net (rename CROW_1 "CROW[1]") (joined
+           (portRef (member crow 0))
+           (portRef I (instanceRef CROW_pad_1))
+          ))
+          (net (rename Din_c_0 "Din_c[0]") (joined
+           (portRef O (instanceRef Din_pad_0))
+           (portRef B (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable16_0_a2_4))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_0))
+           (portRef D (instanceRef CmdUFMSDI))
+           (portRef D (instanceRef WRD_0))
+          ))
+          (net (rename Din_0 "Din[0]") (joined
+           (portRef (member din 7))
+           (portRef I (instanceRef Din_pad_0))
+          ))
+          (net (rename Din_c_1 "Din_c[1]") (joined
+           (portRef O (instanceRef Din_pad_1))
+           (portRef A (instanceRef CmdEnable17_0_a2_3))
+           (portRef B (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a3_3))
+           (portRef D (instanceRef Bank_1))
+           (portRef D (instanceRef CmdUFMCLK))
+           (portRef D (instanceRef WRD_1))
+          ))
+          (net (rename Din_1 "Din[1]") (joined
+           (portRef (member din 6))
+           (portRef I (instanceRef Din_pad_1))
+          ))
+          (net (rename Din_c_2 "Din_c[2]") (joined
+           (portRef O (instanceRef Din_pad_2))
+           (portRef A (instanceRef CmdEnable17_0_a2_4))
+           (portRef B (instanceRef CmdEnable16_0_a2_5))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_2))
+           (portRef D (instanceRef CmdUFMCS))
+           (portRef D (instanceRef WRD_2))
+          ))
+          (net (rename Din_2 "Din[2]") (joined
+           (portRef (member din 5))
+           (portRef I (instanceRef Din_pad_2))
+          ))
+          (net (rename Din_c_3 "Din_c[3]") (joined
+           (portRef O (instanceRef Din_pad_3))
+           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef D (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdEnable17_0_o2))
+           (portRef C (instanceRef CmdEnable16_0_a2_4_0))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a3_2))
+           (portRef D (instanceRef Bank_3))
+           (portRef D (instanceRef WRD_3))
+          ))
+          (net (rename Din_3 "Din[3]") (joined
+           (portRef (member din 4))
+           (portRef I (instanceRef Din_pad_3))
+          ))
+          (net (rename Din_c_4 "Din_c[4]") (joined
+           (portRef O (instanceRef Din_pad_4))
+           (portRef D (instanceRef CmdEnable17_0_a2_3))
+           (portRef A (instanceRef CmdEnable16_0_a2_1))
+           (portRef A (instanceRef un1_Din_4))
+           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef D (instanceRef Bank_4))
+           (portRef D (instanceRef WRD_4))
+          ))
+          (net (rename Din_4 "Din[4]") (joined
+           (portRef (member din 3))
+           (portRef I (instanceRef Din_pad_4))
+          ))
+          (net (rename Din_c_5 "Din_c[5]") (joined
+           (portRef O (instanceRef Din_pad_5))
+           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_a2))
+           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef B (instanceRef CmdEnable17_0_o2))
+           (portRef B (instanceRef CmdEnable16_0_a2_4))
+           (portRef B (instanceRef un1_Din_4))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef Bank_5))
+           (portRef D (instanceRef WRD_5))
+          ))
+          (net (rename Din_5 "Din[5]") (joined
+           (portRef (member din 2))
+           (portRef I (instanceRef Din_pad_5))
+          ))
+          (net (rename Din_c_6 "Din_c[6]") (joined
+           (portRef O (instanceRef Din_pad_6))
+           (portRef C (instanceRef un1_Din_4))
+           (portRef A (instanceRef RA11_2))
+           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef B (instanceRef CmdEnable17_0_a2_4))
+           (portRef C (instanceRef CmdEnable16_0_a2_5))
+           (portRef D (instanceRef Bank_6))
+           (portRef D (instanceRef WRD_6))
+          ))
+          (net (rename Din_6 "Din[6]") (joined
+           (portRef (member din 1))
+           (portRef I (instanceRef Din_pad_6))
+          ))
+          (net (rename Din_c_7 "Din_c[7]") (joined
+           (portRef O (instanceRef Din_pad_7))
+           (portRef C (instanceRef CmdEnable17_0_a2_3))
+           (portRef B (instanceRef CmdEnable16_0_a2_1))
+           (portRef D (instanceRef un1_Din_4))
+           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
+           (portRef D (instanceRef Bank_7))
+           (portRef D (instanceRef WRD_7))
+          ))
+          (net (rename Din_7 "Din[7]") (joined
+           (portRef (member din 0))
+           (portRef I (instanceRef Din_pad_7))
+          ))
+          (net (rename Dout_0 "Dout[0]") (joined
+           (portRef O (instanceRef Dout_pad_0))
+           (portRef (member dout 7))
+          ))
+          (net (rename Dout_1 "Dout[1]") (joined
+           (portRef O (instanceRef Dout_pad_1))
+           (portRef (member dout 6))
+          ))
+          (net (rename Dout_2 "Dout[2]") (joined
+           (portRef O (instanceRef Dout_pad_2))
+           (portRef (member dout 5))
+          ))
+          (net (rename Dout_3 "Dout[3]") (joined
+           (portRef O (instanceRef Dout_pad_3))
+           (portRef (member dout 4))
+          ))
+          (net (rename Dout_4 "Dout[4]") (joined
+           (portRef O (instanceRef Dout_pad_4))
+           (portRef (member dout 3))
+          ))
+          (net (rename Dout_5 "Dout[5]") (joined
+           (portRef O (instanceRef Dout_pad_5))
+           (portRef (member dout 2))
+          ))
+          (net (rename Dout_6 "Dout[6]") (joined
+           (portRef O (instanceRef Dout_pad_6))
+           (portRef (member dout 1))
+          ))
+          (net (rename Dout_7 "Dout[7]") (joined
+           (portRef O (instanceRef Dout_pad_7))
+           (portRef (member dout 0))
+          ))
+          (net nCCAS_c (joined
+           (portRef O (instanceRef nCCAS_pad))
+           (portRef A (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef A (instanceRef nCCAS_pad_RNISUR8))
+          ))
+          (net nCCAS (joined
+           (portRef nCCAS)
+           (portRef I (instanceRef nCCAS_pad))
+          ))
+          (net nCRAS_c (joined
+           (portRef O (instanceRef nCRAS_pad))
+           (portRef C (instanceRef LED_pad_RNO))
+           (portRef A (instanceRef nCRAS_pad_RNIBPVB))
+           (portRef A (instanceRef RASr_RNO))
+          ))
+          (net nCRAS (joined
+           (portRef nCRAS)
+           (portRef I (instanceRef nCRAS_pad))
+          ))
+          (net nFWE_c (joined
+           (portRef O (instanceRef nFWE_pad))
+           (portRef C (instanceRef C1WR_0_a2_0_3))
+           (portRef B (instanceRef nCCAS_pad_RNI01SJ))
+           (portRef A (instanceRef nFWE_pad_RNI420B))
+          ))
+          (net nFWE (joined
+           (portRef nFWE)
+           (portRef I (instanceRef nFWE_pad))
+          ))
+          (net LED_c (joined
+           (portRef Z (instanceRef LED_pad_RNO))
+           (portRef I (instanceRef LED_pad))
+          ))
+          (net LED (joined
+           (portRef O (instanceRef LED_pad))
+           (portRef LED)
+          ))
+          (net (rename RBA_c_0 "RBA_c[0]") (joined
+           (portRef Q (instanceRef RBA_0))
+           (portRef I (instanceRef RBA_pad_0))
+          ))
+          (net (rename RBA_0 "RBA[0]") (joined
+           (portRef O (instanceRef RBA_pad_0))
+           (portRef (member rba 1))
+          ))
+          (net (rename RBA_c_1 "RBA_c[1]") (joined
+           (portRef Q (instanceRef RBA_1))
+           (portRef I (instanceRef RBA_pad_1))
+          ))
+          (net (rename RBA_1 "RBA[1]") (joined
+           (portRef O (instanceRef RBA_pad_1))
+           (portRef (member rba 0))
+          ))
+          (net (rename RA_c_0 "RA_c[0]") (joined
+           (portRef Z (instanceRef un9_RA_0))
+           (portRef I (instanceRef RA_pad_0))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef O (instanceRef RA_pad_0))
+           (portRef (member ra 11))
+          ))
+          (net (rename RA_c_1 "RA_c[1]") (joined
+           (portRef Z (instanceRef un9_RA_1))
+           (portRef I (instanceRef RA_pad_1))
+          ))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef O (instanceRef RA_pad_1))
+           (portRef (member ra 10))
+          ))
+          (net (rename RA_c_2 "RA_c[2]") (joined
+           (portRef Z (instanceRef un9_RA_2))
+           (portRef I (instanceRef RA_pad_2))
+          ))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef O (instanceRef RA_pad_2))
+           (portRef (member ra 9))
+          ))
+          (net (rename RA_c_3 "RA_c[3]") (joined
+           (portRef Z (instanceRef un9_RA_3))
+           (portRef I (instanceRef RA_pad_3))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef O (instanceRef RA_pad_3))
+           (portRef (member ra 8))
+          ))
+          (net (rename RA_c_4 "RA_c[4]") (joined
+           (portRef Z (instanceRef un9_RA_4))
+           (portRef I (instanceRef RA_pad_4))
+          ))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef O (instanceRef RA_pad_4))
+           (portRef (member ra 7))
+          ))
+          (net (rename RA_c_5 "RA_c[5]") (joined
+           (portRef Z (instanceRef un9_RA_5))
+           (portRef I (instanceRef RA_pad_5))
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef O (instanceRef RA_pad_5))
+           (portRef (member ra 6))
+          ))
+          (net (rename RA_c_6 "RA_c[6]") (joined
+           (portRef Z (instanceRef un9_RA_6))
+           (portRef I (instanceRef RA_pad_6))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef O (instanceRef RA_pad_6))
+           (portRef (member ra 5))
+          ))
+          (net (rename RA_c_7 "RA_c[7]") (joined
+           (portRef Z (instanceRef un9_RA_7))
+           (portRef I (instanceRef RA_pad_7))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef O (instanceRef RA_pad_7))
+           (portRef (member ra 4))
+          ))
+          (net (rename RA_c_8 "RA_c[8]") (joined
+           (portRef Z (instanceRef un9_RA_8))
+           (portRef I (instanceRef RA_pad_8))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef O (instanceRef RA_pad_8))
+           (portRef (member ra 3))
+          ))
+          (net (rename RA_c_9 "RA_c[9]") (joined
+           (portRef Z (instanceRef un9_RA_9))
+           (portRef I (instanceRef RA_pad_9))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef O (instanceRef RA_pad_9))
+           (portRef (member ra 2))
+          ))
+          (net (rename RA_c_10 "RA_c[10]") (joined
+           (portRef Q (instanceRef RA10))
+           (portRef I (instanceRef RA_pad_10))
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef O (instanceRef RA_pad_10))
+           (portRef (member ra 1))
+          ))
+          (net (rename RA_c_11 "RA_c[11]") (joined
+           (portRef Q (instanceRef RA11))
+           (portRef I (instanceRef RA_pad_11))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef O (instanceRef RA_pad_11))
+           (portRef (member ra 0))
+          ))
+          (net (rename RD_in_0 "RD_in[0]") (joined
+           (portRef O (instanceRef RD_pad_0))
+           (portRef I (instanceRef Dout_pad_0))
+          ))
+          (net (rename RD_0 "RD[0]") (joined
+           (portRef B (instanceRef RD_pad_0))
+           (portRef (member rd 7))
+          ))
+          (net (rename RD_in_1 "RD_in[1]") (joined
+           (portRef O (instanceRef RD_pad_1))
+           (portRef I (instanceRef Dout_pad_1))
+          ))
+          (net (rename RD_1 "RD[1]") (joined
+           (portRef B (instanceRef RD_pad_1))
+           (portRef (member rd 6))
+          ))
+          (net (rename RD_in_2 "RD_in[2]") (joined
+           (portRef O (instanceRef RD_pad_2))
+           (portRef I (instanceRef Dout_pad_2))
+          ))
+          (net (rename RD_2 "RD[2]") (joined
+           (portRef B (instanceRef RD_pad_2))
+           (portRef (member rd 5))
+          ))
+          (net (rename RD_in_3 "RD_in[3]") (joined
+           (portRef O (instanceRef RD_pad_3))
+           (portRef I (instanceRef Dout_pad_3))
+          ))
+          (net (rename RD_3 "RD[3]") (joined
+           (portRef B (instanceRef RD_pad_3))
+           (portRef (member rd 4))
+          ))
+          (net (rename RD_in_4 "RD_in[4]") (joined
+           (portRef O (instanceRef RD_pad_4))
+           (portRef I (instanceRef Dout_pad_4))
+          ))
+          (net (rename RD_4 "RD[4]") (joined
+           (portRef B (instanceRef RD_pad_4))
+           (portRef (member rd 3))
+          ))
+          (net (rename RD_in_5 "RD_in[5]") (joined
+           (portRef O (instanceRef RD_pad_5))
+           (portRef I (instanceRef Dout_pad_5))
+          ))
+          (net (rename RD_5 "RD[5]") (joined
+           (portRef B (instanceRef RD_pad_5))
+           (portRef (member rd 2))
+          ))
+          (net (rename RD_in_6 "RD_in[6]") (joined
+           (portRef O (instanceRef RD_pad_6))
+           (portRef I (instanceRef Dout_pad_6))
+          ))
+          (net (rename RD_6 "RD[6]") (joined
+           (portRef B (instanceRef RD_pad_6))
+           (portRef (member rd 1))
+          ))
+          (net (rename RD_in_7 "RD_in[7]") (joined
+           (portRef O (instanceRef RD_pad_7))
+           (portRef I (instanceRef Dout_pad_7))
+          ))
+          (net (rename RD_7 "RD[7]") (joined
+           (portRef B (instanceRef RD_pad_7))
+           (portRef (member rd 0))
+          ))
+          (net nRCS_c (joined
+           (portRef Q (instanceRef nRCS))
+           (portRef I (instanceRef nRCS_pad))
+          ))
+          (net nRCS (joined
+           (portRef O (instanceRef nRCS_pad))
+           (portRef nRCS)
+          ))
+          (net RCLK_c (joined
+           (portRef O (instanceRef RCLK_pad))
+           (portRef CK (instanceRef CASr))
+           (portRef CK (instanceRef CASr2))
+           (portRef CK (instanceRef CASr3))
+           (portRef CK (instanceRef FS_17))
+           (portRef CK (instanceRef FS_16))
+           (portRef CK (instanceRef FS_15))
+           (portRef CK (instanceRef FS_14))
+           (portRef CK (instanceRef FS_13))
+           (portRef CK (instanceRef FS_12))
+           (portRef CK (instanceRef FS_11))
+           (portRef CK (instanceRef FS_10))
+           (portRef CK (instanceRef FS_9))
+           (portRef CK (instanceRef FS_8))
+           (portRef CK (instanceRef FS_7))
+           (portRef CK (instanceRef FS_6))
+           (portRef CK (instanceRef FS_5))
+           (portRef CK (instanceRef FS_4))
+           (portRef CK (instanceRef FS_3))
+           (portRef CK (instanceRef FS_2))
+           (portRef CK (instanceRef FS_1))
+           (portRef CK (instanceRef FS_0))
+           (portRef CK (instanceRef IS_3))
+           (portRef CK (instanceRef IS_2))
+           (portRef CK (instanceRef IS_1))
+           (portRef CK (instanceRef IS_0))
+           (portRef CK (instanceRef InitReady))
+           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef PHI2r))
+           (portRef CK (instanceRef PHI2r2))
+           (portRef CK (instanceRef PHI2r3))
+           (portRef CK (instanceRef RA10))
+           (portRef CK (instanceRef RASr))
+           (portRef CK (instanceRef RASr2))
+           (portRef CK (instanceRef RASr3))
+           (portRef CK (instanceRef RCKE))
+           (portRef CK (instanceRef RCKEEN))
+           (portRef CK (instanceRef Ready))
+           (portRef CK (instanceRef Ready_fast))
+           (portRef CK (instanceRef S_1))
+           (portRef CK (instanceRef S_0))
+           (portRef CK (instanceRef UFMCLK))
+           (portRef CK (instanceRef UFMSDI))
+           (portRef CK (instanceRef n8MEGEN))
+           (portRef CK (instanceRef nRCAS))
+           (portRef CK (instanceRef nRCS))
+           (portRef CK (instanceRef nRRAS))
+           (portRef CK (instanceRef nRWE))
+           (portRef CK (instanceRef nRowColSel))
+           (portRef CK (instanceRef nUFMCS))
+          ))
+          (net RCLK (joined
+           (portRef RCLK)
+           (portRef I (instanceRef RCLK_pad))
+          ))
+          (net RCKE_c (joined
+           (portRef Q (instanceRef RCKE))
+           (portRef C (instanceRef nRRAS_5_u_i_0))
+           (portRef I (instanceRef RCKE_pad))
+           (portRef C (instanceRef nRWE_RNO_3))
+          ))
+          (net RCKE (joined
+           (portRef O (instanceRef RCKE_pad))
+           (portRef RCKE)
+          ))
+          (net nRWE_c (joined
+           (portRef Q (instanceRef nRWE))
+           (portRef I (instanceRef nRWE_pad))
+          ))
+          (net nRWE (joined
+           (portRef O (instanceRef nRWE_pad))
+           (portRef nRWE)
+          ))
+          (net nRRAS_c (joined
+           (portRef Q (instanceRef nRRAS))
+           (portRef I (instanceRef nRRAS_pad))
+          ))
+          (net nRRAS (joined
+           (portRef O (instanceRef nRRAS_pad))
+           (portRef nRRAS)
+          ))
+          (net nRCAS_c (joined
+           (portRef Q (instanceRef nRCAS))
+           (portRef I (instanceRef nRCAS_pad))
+          ))
+          (net nRCAS (joined
+           (portRef O (instanceRef nRCAS_pad))
+           (portRef nRCAS)
+          ))
+          (net RDQMH_c (joined
+           (portRef Z (instanceRef RDQMH))
+           (portRef I (instanceRef RDQMH_pad))
+          ))
+          (net RDQMH (joined
+           (portRef O (instanceRef RDQMH_pad))
+           (portRef RDQMH)
+          ))
+          (net RDQML_c (joined
+           (portRef Z (instanceRef RDQML))
+           (portRef I (instanceRef RDQML_pad))
+          ))
+          (net RDQML (joined
+           (portRef O (instanceRef RDQML_pad))
+           (portRef RDQML)
+          ))
+          (net nUFMCS_c (joined
+           (portRef Q (instanceRef nUFMCS))
+           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
+           (portRef I (instanceRef nUFMCS_pad))
+          ))
+          (net nUFMCS (joined
+           (portRef O (instanceRef nUFMCS_pad))
+           (portRef nUFMCS)
+          ))
+          (net UFMCLK_c (joined
+           (portRef Q (instanceRef UFMCLK))
+           (portRef C (instanceRef UFMCLK_RNO))
+           (portRef I (instanceRef UFMCLK_pad))
+          ))
+          (net UFMCLK (joined
+           (portRef O (instanceRef UFMCLK_pad))
+           (portRef UFMCLK)
+          ))
+          (net UFMSDI_c (joined
+           (portRef Q (instanceRef UFMSDI))
+           (portRef C (instanceRef UFMSDI_RNO))
+           (portRef I (instanceRef UFMSDI_pad))
+          ))
+          (net UFMSDI (joined
+           (portRef O (instanceRef UFMSDI_pad))
+           (portRef UFMSDI)
+          ))
+          (net UFMSDO_c (joined
+           (portRef O (instanceRef UFMSDO_pad))
+           (portRef C (instanceRef LEDEN_5_i_m2))
+           (portRef C (instanceRef n8MEGEN_5_i_m2))
+          ))
+          (net UFMSDO (joined
+           (portRef UFMSDO)
+           (portRef I (instanceRef UFMSDO_pad))
+          ))
+          (net N_460_0 (joined
+           (portRef Z (instanceRef CmdSubmitted_RNO))
+           (portRef D (instanceRef CmdSubmitted))
+          ))
+          (net N_461_0 (joined
+           (portRef Z (instanceRef InitReady_RNO))
+           (portRef D (instanceRef InitReady))
+          ))
+          (net N_462_0 (joined
+           (portRef Z (instanceRef Ready_RNO))
+           (portRef D (instanceRef Ready))
+          ))
+          (net N_463_0 (joined
+           (portRef Z (instanceRef Ready_fast_RNO))
+           (portRef D (instanceRef Ready_fast))
+          ))
+          (net nFWE_c_i (joined
+           (portRef Z (instanceRef nFWE_pad_RNI420B))
+           (portRef D (instanceRef FWEr))
+           (portRef D (instanceRef FWEr_fast))
+          ))
+          (net nCRAS_c_i_0 (joined
+           (portRef Z (instanceRef RASr_RNO))
+           (portRef D (instanceRef RASr))
+          ))
+          (net nCCAS_c_i (joined
+           (portRef Z (instanceRef nCCAS_pad_RNISUR8))
+           (portRef D (instanceRef CASr))
+           (portRef D (instanceRef CBR))
+           (portRef D (instanceRef CBR_fast))
+           (portRef CK (instanceRef WRD_7))
+           (portRef CK (instanceRef WRD_6))
+           (portRef CK (instanceRef WRD_5))
+           (portRef CK (instanceRef WRD_4))
+           (portRef CK (instanceRef WRD_3))
+           (portRef CK (instanceRef WRD_2))
+           (portRef CK (instanceRef WRD_1))
+           (portRef CK (instanceRef WRD_0))
+          ))
+          (net Ready_fast_i (joined
+           (portRef Z (instanceRef Ready_fast_RNI29NA))
+           (portRef CD (instanceRef RA11))
+           (portRef CD (instanceRef RBA_1))
+           (portRef CD (instanceRef RBA_0))
+           (portRef PD (instanceRef RowA_9))
+           (portRef CD (instanceRef RowA_8))
+           (portRef CD (instanceRef RowA_7))
+           (portRef CD (instanceRef RowA_6))
+           (portRef PD (instanceRef RowA_5))
+           (portRef CD (instanceRef RowA_4))
+           (portRef CD (instanceRef RowA_3))
+           (portRef CD (instanceRef RowA_2))
+           (portRef CD (instanceRef RowA_1))
+           (portRef CD (instanceRef RowA_0))
+          ))
+          (net (rename IS_i_0 "IS_i[0]") (joined
+           (portRef Z (instanceRef IS_i_0))
+           (portRef D (instanceRef RA10))
+          ))
+          (net RASr2_i (joined
+           (portRef Z (instanceRef RASr2_RNIAFR1))
+           (portRef CD (instanceRef S_1))
+           (portRef CD (instanceRef S_0))
+          ))
+          (net nRWE_RNO_4 (joined
+           (portRef Z (instanceRef nRWE_RNO_4))
+           (portRef BLUT (instanceRef nRWE_RNO_1))
+          ))
+          (net nRWE_RNO_3 (joined
+           (portRef Z (instanceRef nRWE_RNO_3))
+           (portRef ALUT (instanceRef nRWE_RNO_1))
+          ))
+          (net CmdEnable_s_am (joined
+           (portRef Z (instanceRef CmdEnable_s_am))
+           (portRef BLUT (instanceRef CmdEnable_s))
+          ))
+          (net CmdEnable_s_bm (joined
+           (portRef Z (instanceRef CmdEnable_s_bm))
+           (portRef ALUT (instanceRef CmdEnable_s))
+          ))
+         )
+        (property orig_inst_of (string "RAM2GS"))
+       )
+    )
+  )
+  (design RAM2GS (cellRef RAM2GS (libraryRef work))
+	(property PART (string "lcmxo256c-3") ))
+)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.htm b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.htm
index cd24fde..4dc3d8f 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.htm
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.htm
@@ -1,9 +1,9 @@
-
- 
- syntmp/RAM2GS_LCMXO256C_impl1_srr.htm log file
- 
- 
- 
- 				 
-
- 
+
+ 
+ syntmp/RAM2GS_LCMXO256C_impl1_srr.htm log file
+ 
+ 
+ 
+ 				 
+
+ 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
index 072d4cf..8d97239 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
@@ -1,977 +1,977 @@
-
-*
-NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
-NOTE Version:         Diamond (64-bit) 3.12.1.454*
-NOTE Readback:       Off*
-NOTE Security:      Off*
-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Wed Aug 16 04:29:49 2023 *
-NOTE DESIGN NAME: RAM2GS *
-NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
-NOTE PIN ASSIGNMENTS *
-NOTE PINS RD[0] : 64 : inout *
-NOTE PINS Dout[0] : 1 : out *
-NOTE PINS PHI2 : 39 : in *
-NOTE PINS UFMSDO : 55 : in *
-NOTE PINS UFMSDI : 56 : out *
-NOTE PINS UFMCLK : 58 : out *
-NOTE PINS nUFMCS : 53 : out *
-NOTE PINS RDQML : 61 : out *
-NOTE PINS RDQMH : 76 : out *
-NOTE PINS nRCAS : 78 : out *
-NOTE PINS nRRAS : 73 : out *
-NOTE PINS nRWE : 72 : out *
-NOTE PINS RCKE : 82 : out *
-NOTE PINS RCLK : 86 : in *
-NOTE PINS nRCS : 77 : out *
-NOTE PINS RD[7] : 71 : inout *
-NOTE PINS RD[6] : 70 : inout *
-NOTE PINS RD[5] : 69 : inout *
-NOTE PINS RD[4] : 68 : inout *
-NOTE PINS RD[3] : 67 : inout *
-NOTE PINS RD[2] : 66 : inout *
-NOTE PINS RD[1] : 65 : inout *
-NOTE PINS RA[11] : 79 : out *
-NOTE PINS RA[10] : 87 : out *
-NOTE PINS RA[9] : 85 : out *
-NOTE PINS RA[8] : 96 : out *
-NOTE PINS RA[7] : 100 : out *
-NOTE PINS RA[6] : 91 : out *
-NOTE PINS RA[5] : 95 : out *
-NOTE PINS RA[4] : 99 : out *
-NOTE PINS RA[3] : 97 : out *
-NOTE PINS RA[2] : 94 : out *
-NOTE PINS RA[1] : 89 : out *
-NOTE PINS RA[0] : 98 : out *
-NOTE PINS RBA[1] : 83 : out *
-NOTE PINS RBA[0] : 63 : out *
-NOTE PINS LED : 57 : out *
-NOTE PINS nFWE : 22 : in *
-NOTE PINS nCRAS : 43 : in *
-NOTE PINS nCCAS : 27 : in *
-NOTE PINS Dout[7] : 3 : out *
-NOTE PINS Dout[6] : 2 : out *
-NOTE PINS Dout[5] : 5 : out *
-NOTE PINS Dout[4] : 4 : out *
-NOTE PINS Dout[3] : 6 : out *
-NOTE PINS Dout[2] : 8 : out *
-NOTE PINS Dout[1] : 7 : out *
-NOTE PINS Din[7] : 19 : in *
-NOTE PINS Din[6] : 20 : in *
-NOTE PINS Din[5] : 17 : in *
-NOTE PINS Din[4] : 18 : in *
-NOTE PINS Din[3] : 16 : in *
-NOTE PINS Din[2] : 14 : in *
-NOTE PINS Din[1] : 15 : in *
-NOTE PINS Din[0] : 21 : in *
-NOTE PINS CROW[1] : 34 : in *
-NOTE PINS CROW[0] : 32 : in *
-NOTE PINS MAin[9] : 51 : in *
-NOTE PINS MAin[8] : 50 : in *
-NOTE PINS MAin[7] : 44 : in *
-NOTE PINS MAin[6] : 49 : in *
-NOTE PINS MAin[5] : 45 : in *
-NOTE PINS MAin[4] : 46 : in *
-NOTE PINS MAin[3] : 47 : in *
-NOTE PINS MAin[2] : 37 : in *
-NOTE PINS MAin[1] : 38 : in *
-NOTE PINS MAin[0] : 23 : in *
-NOTE CONFIGURATION MODE: NONE *
-NOTE COMPRESSION: off *
-
-
-QF56640*
-G0*
-F0*
-L00000
-11111111001101111111011110111100110111111101111011110011011111110111101111001101
-11111101111011111111111111111111101111001010010011010111011100101001001101011110
-11001010010011010111101111111111
-11111111001111111111011110111100110111111101111011110011011111110111101111001101
-11111101111011111111111111111111101111001010010011010111011100101001001101011101
-11001010010011010111011111111111
-11111111111111111111111111111111111111111111111111110011011111110111101111111111
-11111111111111111111111111111111101111111111111111111111111100101001001101011101
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111110011011111110111101111111111
-11111111111111110011011111110111101111111111111111111111111100101001001101011101
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111101111111111111111111011111111111111111111
-11111111111111111111111111111011111111111111111111111111111111111111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111101111111111111111111101111111111111111101
-11111111011111111111111111111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
-11111111111111111111100111111011111111111111111111111111111111011111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111101
-11111111011111111111101111111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
-11110111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111101111111111111
-11111111111111111111111011111111111111111111111111111111111111111111111111111111
-11111111111111111111111111111111
-11111111111111111111111111111111111111111111111111111111111111111111111111111111
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+NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
+NOTE Version:         Diamond (64-bit) 3.12.1.454*
+NOTE Readback:       Off*
+NOTE Security:      Off*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Sat Aug 19 20:53:35 2023 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
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+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS PHI2 : 39 : in *
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+NOTE PINS RCKE : 82 : out *
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+NOTE PINS RD[7] : 71 : inout *
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+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
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+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS LED : 57 : out *
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+NOTE PINS Dout[7] : 3 : out *
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+NOTE PINS MAin[9] : 51 : in *
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+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
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diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log
index d0353b8..9ce5b3b 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log
@@ -1,4 +1,4 @@
----- MParTrce Tool Log File ----
-
-==== Par Standard Out ====
-==== End of Par Standard Out ====
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
index 64b2698..fff24e6 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
@@ -1,336 +1,336 @@
-
-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-Design Information
-------------------
-
-Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial -ioreg
-     b RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
-     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/
-     Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplif
-     y.lpf -lpf
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c
-     0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO256CTQFP100
-Target Performance:   3
-Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/16/23  04:50:39
-
-Design Summary
---------------
-
-   Number of PFU registers:    92 out of   256 (36%)
-   Number of SLICEs:        69 out of   128 (54%)
-      SLICEs as Logic/ROM:     69 out of   128 (54%)
-      SLICEs as RAM:            0 out of    64 (0%)
-      SLICEs as Carry:          9 out of   128 (7%)
-   Number of LUT4s:        137 out of   256 (54%)
-      Number used as logic LUTs:        119
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 78 (86%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  5
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net N_31: 1 loads, 1 LSLICEs
-     Net N_33: 1 loads, 1 LSLICEs
-     Net N_159_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
-   Number of LSRs:  4
-     Net RA10s_i: 1 loads, 1 LSLICEs
-     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
-     Net RASr2: 2 loads, 2 LSLICEs
-     Net Ready_fast: 7 loads, 7 LSLICEs
-
-                                    Page 1
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:39
-
-Design Summary (cont)
----------------------
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net InitReady: 16 loads
-     Net Ready: 16 loads
-     Net S[1]: 13 loads
-     Net CO0: 12 loads
-     Net nRowColSel: 12 loads
-     Net RASr2: 11 loads
-     Net Din_c[5]: 10 loads
-     Net Din_c[3]: 9 loads
-     Net IS[0]: 9 loads
-     Net MAin_c[1]: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-Design Errors/Warnings
-----------------------
-
-   No errors or warnings present.
-
-IO (PIO) Attributes
--------------------
-
-+---------------------+-----------+-----------+------------+------------+
-| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
-|                     |           |  IO_TYPE  | Register   |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[0]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| PHI2                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDO              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQML               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 2
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:39
-
-IO (PIO) Attributes (cont)
---------------------------
-| RCKE                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCLK                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCS                | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[7]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[6]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[5]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[4]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[3]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[2]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[1]               | BIDIR     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| LED                 | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nFWE                | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCRAS               | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCCAS               | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 3
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:39
-
-IO (PIO) Attributes (cont)
---------------------------
-| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[7]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[6]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[5]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[4]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[3]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[2]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[1]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[0]              | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[1]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[0]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[9]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[8]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[7]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[6]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[5]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[4]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[3]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[2]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[1]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[0]             | INPUT     | LVCMOS33  |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-
-
-                                    Page 4
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/23  04:50:39
-
-Removed logic
--------------
-
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal nCRAS_c_i was merged into signal nCRAS_c
-Signal nFWE_c_i was merged into signal nFWE_c
-Signal nCRAS_c_i_0 was merged into signal nCRAS_c
-Signal nCCAS_c_i was merged into signal nCCAS_c
-Signal Ready_fast_i was merged into signal Ready_fast
-Signal IS_i[0] was merged into signal IS[0]
-Signal RASr2_i was merged into signal RASr2
-Signal XOR8MEG.CN was merged into signal PHI2_c
-Signal GND undriven or does not drive anything - clipped.
-Signal VCC undriven or does not drive anything - clipped.
-Signal FS_cry[2] undriven or does not drive anything - clipped.
-Signal FS_cry[4] undriven or does not drive anything - clipped.
-Signal FS_cry[6] undriven or does not drive anything - clipped.
-Signal FS_cry[8] undriven or does not drive anything - clipped.
-Signal FS_cry[10] undriven or does not drive anything - clipped.
-Signal FS_cry[12] undriven or does not drive anything - clipped.
-Signal FS_cry[14] undriven or does not drive anything - clipped.
-Signal FS_cry_0_COUT1[16] undriven or does not drive anything - clipped.
-Signal FS_cry[16] undriven or does not drive anything - clipped.
-Signal FS_cry[0] undriven or does not drive anything - clipped.
-Block nCRAS_pad_RNIBPVB was optimized away.
-Block nFWE_pad_RNI420B was optimized away.
-Block RASr_RNO was optimized away.
-Block nCCAS_pad_RNISUR8 was optimized away.
-Block Ready_fast_RNI29NA was optimized away.
-Block IS_i[0] was optimized away.
-Block RASr2_RNIAFR1 was optimized away.
-Block XOR8MEG.CN was optimized away.
-Block GND was optimized away.
-Block VCC was optimized away.
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 29 MB
-        
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-                                    Page 5
-
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial -ioreg
+     b RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf
+     Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf
+     -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO.lpf -c 0 -gui -msgset
+     Y:/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO256CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/19/23  20:53:19
+
+Design Summary
+--------------
+
+   Number of PFU registers:    92 out of   256 (36%)
+   Number of SLICEs:        69 out of   128 (54%)
+      SLICEs as Logic/ROM:     69 out of   128 (54%)
+      SLICEs as RAM:            0 out of    64 (0%)
+      SLICEs as Carry:          9 out of   128 (7%)
+   Number of LUT4s:        137 out of   256 (54%)
+      Number used as logic LUTs:        119
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 78 (86%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 )
+     Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK )
+     Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  5
+     Net XOR8MEG18: 3 loads, 3 LSLICEs
+     Net N_31: 1 loads, 1 LSLICEs
+     Net N_33: 1 loads, 1 LSLICEs
+     Net N_159_i: 2 loads, 2 LSLICEs
+     Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
+   Number of LSRs:  4
+     Net RA10s_i: 1 loads, 1 LSLICEs
+     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
+     Net RASr2: 2 loads, 2 LSLICEs
+     Net Ready_fast: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:53:19
+
+Design Summary (cont)
+---------------------
+     Net InitReady: 16 loads
+     Net Ready: 16 loads
+     Net S[1]: 13 loads
+     Net CO0: 12 loads
+     Net nRowColSel: 12 loads
+     Net RASr2: 11 loads
+     Net Din_c[5]: 10 loads
+     Net Din_c[3]: 9 loads
+     Net IS[0]: 9 loads
+     Net MAin_c[1]: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:53:19
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:53:19
+
+IO (PIO) Attributes (cont)
+--------------------------
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/19/23  20:53:19
+
+Removed logic
+-------------
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_c_i was merged into signal nCRAS_c
+Signal nFWE_c_i was merged into signal nFWE_c
+Signal nCRAS_c_i_0 was merged into signal nCRAS_c
+Signal nCCAS_c_i was merged into signal nCCAS_c
+Signal Ready_fast_i was merged into signal Ready_fast
+Signal IS_i[0] was merged into signal IS[0]
+Signal RASr2_i was merged into signal RASr2
+Signal XOR8MEG.CN was merged into signal PHI2_c
+Signal GND undriven or does not drive anything - clipped.
+Signal VCC undriven or does not drive anything - clipped.
+Signal FS_cry[2] undriven or does not drive anything - clipped.
+Signal FS_cry[4] undriven or does not drive anything - clipped.
+Signal FS_cry[6] undriven or does not drive anything - clipped.
+Signal FS_cry[8] undriven or does not drive anything - clipped.
+Signal FS_cry[10] undriven or does not drive anything - clipped.
+Signal FS_cry[12] undriven or does not drive anything - clipped.
+Signal FS_cry[14] undriven or does not drive anything - clipped.
+Signal FS_cry_0_COUT1[16] undriven or does not drive anything - clipped.
+Signal FS_cry[16] undriven or does not drive anything - clipped.
+Signal FS_cry[0] undriven or does not drive anything - clipped.
+Block nCRAS_pad_RNIBPVB was optimized away.
+Block nFWE_pad_RNI420B was optimized away.
+Block RASr_RNO was optimized away.
+Block nCCAS_pad_RNISUR8 was optimized away.
+Block Ready_fast_RNI29NA was optimized away.
+Block IS_i[0] was optimized away.
+Block RASr2_RNIAFR1 was optimized away.
+Block XOR8MEG.CN was optimized away.
+Block GND was optimized away.
+Block VCC was optimized away.
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 50 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 5
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e
index dc1115c..fb895f8 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e
@@ -1,551 +1,551 @@
-
-comp 0: SLICE_0 (FSLICE)
-
-comp 1: SLICE_1 (FSLICE)
-
-comp 2: SLICE_2 (FSLICE)
-
-comp 3: SLICE_3 (FSLICE)
-
-comp 4: SLICE_4 (FSLICE)
-
-comp 5: SLICE_5 (FSLICE)
-
-comp 6: SLICE_6 (FSLICE)
-
-comp 7: SLICE_7 (FSLICE)
-
-comp 8: SLICE_8 (FSLICE)
-
-comp 9: SLICE_9 (FSLICE)
-ADSubmitted_r = (~CmdEnable16*((~C1WR_0_a2*ADSubmitted)+CmdEnable17))
-ADSubmitted.D = ADSubmitted_r
-ADSubmitted.CLK = ~PHI2_c
-ADSubmitted.SP = VCC
-ADSubmitted.LSR = GND
-CmdEnable17 = (N_147*(MAin_c[0]*(CmdEnable17_0_a2_4*CmdEnable17_0_a2_3)))
-
-comp 10: SLICE_14 (FSLICE)
-C1Submitted_RNO = (~MAin_c[1]*(CmdEnable16+C1Submitted)+MAin_c[1]*(~N_147*(CmdEnable16+C1Submitted)+N_147*CmdEnable16))
-C1Submitted.D = C1Submitted_RNO
-C1Submitted.CLK = ~PHI2_c
-C1Submitted.SP = VCC
-C1Submitted.LSR = GND
-CmdEnable16 = (N_147*(CmdEnable16_0_a2_5*CmdEnable16_0_a2_4))
-
-comp 11: SLICE_19 (FSLICE)
-N_177_i = (~CO0+S[1])
-CO0.D = N_177_i
-CO0.CLK = RCLK_c
-CO0.SP = VCC
-CO0.LSR = ~RASr2
-Ready_0_sqmuxa_0_a3_2 = (S[1]*(~RASr2*(IS[3]*CO0)))
-
-comp 12: SLICE_20 (FSLICE)
-CmdEnable_s = ((CmdEnable+ADSubmitted)*CmdEnable16)+(((C1Submitted*un1_CMDWR*CmdEnable17)+(CmdEnable*CmdEnable17)+(~un1_CMDWR*CmdEnable))*~CmdEnable16)
-CmdEnable.D = CmdEnable_s
-CmdEnable.CLK = ~PHI2_c
-CmdEnable.SP = VCC
-CmdEnable.LSR = GND
-
-comp 13: SLICE_21 (FSLICE)
-N_21_i = (~N_152*(~N_133*~N_132)+N_152*(~N_133*(~N_132*LEDEN)))
-CmdLEDEN.D = N_21_i
-CmdLEDEN.CLK = ~PHI2_c
-CmdLEDEN.SP = XOR8MEG18
-CmdLEDEN.LSR = GND
-N_152 = (~N_128*(Din_c[5]*~Din_c[3]))
-
-comp 14: SLICE_22 (FSLICE)
-N_460_0 = (CmdSubmitted_1_sqmuxa+CmdSubmitted)
-CmdSubmitted.D = N_460_0
-CmdSubmitted.CLK = ~PHI2_c
-CmdSubmitted.SP = VCC
-CmdSubmitted.LSR = GND
-N_136 = (PHI2r3*(~PHI2r2*(InitReady*CmdSubmitted)))
-
-comp 15: SLICE_26 (FSLICE)
-N_19_i = (~n8MEGEN*(~N_152*~Cmdn8MEGEN_4_u_i_0)+n8MEGEN*~Cmdn8MEGEN_4_u_i_0)
-Cmdn8MEGEN.D = N_19_i
-Cmdn8MEGEN.CLK = ~PHI2_c
-Cmdn8MEGEN.SP = XOR8MEG18
-Cmdn8MEGEN.LSR = GND
-Cmdn8MEGEN_4_u_i_0 = (~N_128*(~N_43*(~Cmdn8MEGEN+CmdEnable16_4)+N_43*CmdEnable16_4)+N_128*~Cmdn8MEGEN)
-
-comp 16: SLICE_29 (FSLICE)
-N_64_i_i = (~N_155*(Ready@~IS[0])+N_155*IS[0])
-IS[0].D = N_64_i_i
-IS[0].CLK = RCLK_c
-IS[0].SP = VCC
-IS[0].LSR = GND
-N_24 = ((~N_160*(~N_155*IS[0])+N_160*~N_155)+nRRAS_5_u_i_0)
-
-comp 17: SLICE_30 (FSLICE)
-N_56_i = (IS[1]@IS[0])
-IS[1].D = N_56_i
-IS[1].CLK = RCLK_c
-IS[1].SP = N_159_i
-IS[1].LSR = GND
-N_60_i_i = (IS[2]@(IS[1]*IS[0]))
-IS[2].D = N_60_i_i
-IS[2].CLK = RCLK_c
-IS[2].SP = N_159_i
-IS[2].LSR = GND
-
-comp 18: SLICE_31 (FSLICE)
-N_61_i_i = (~IS[0]*IS[3]+IS[0]*(~IS[1]*IS[3]+IS[1]*(IS[2]@IS[3])))
-IS[3].D = N_61_i_i
-IS[3].CLK = RCLK_c
-IS[3].SP = N_159_i
-IS[3].LSR = GND
-RA10s_i = ((~IS[3]+(IS[1]+IS[2]))+N_159)
-
-comp 19: SLICE_32 (FSLICE)
-N_461_0 = (InitReady3+InitReady)
-InitReady.D = N_461_0
-InitReady.CLK = RCLK_c
-InitReady.SP = VCC
-InitReady.LSR = GND
-UFMSDI_ens2_i_a0 = (~UFMSDI_ens2_i_a2_4_2*~InitReady+UFMSDI_ens2_i_a2_4_2*(~N_126*~InitReady+N_126*(N_51*~InitReady)))
-
-comp 20: SLICE_33 (FSLICE)
-N_70 = (~UFMSDO_c*(~InitReady+CmdLEDEN)+UFMSDO_c*(InitReady*CmdLEDEN))
-LEDEN.D = N_70
-LEDEN.CLK = RCLK_c
-LEDEN.SP = N_33
-LEDEN.LSR = GND
-LED_c = ((~LEDEN+CBR)+nCRAS_c)
-
-comp 21: SLICE_39 (FSLICE)
-RA11_2 = (~n8MEGEN*(XOR8MEG@Din_c[6])+n8MEGEN*XOR8MEG)
-RA_c[11].D = RA11_2
-RA_c[11].CLK = PHI2_c
-RA_c[11].SP = VCC
-RA_c[11].LSR = ~Ready_fast
-N_171 = (~un1_Din_4*XOR8MEG)
-
-comp 22: SLICE_41 (FSLICE)
-RCKEEN_8 = (~Ready*RCKEEN_8_u_0_0+Ready*(~RCKEEN_8_u_1*RCKEEN_8_u_0_0+RCKEEN_8_u_1*(~CBR+RCKEEN_8_u_0_0)))
-RCKEEN.D = RCKEEN_8
-RCKEEN.CLK = RCLK_c
-RCKEEN.SP = VCC
-RCKEEN.LSR = GND
-RCKEEN_8_u_1 = (~S[1]*(~FWEr_fast+CO0)+S[1]*(FWEr_fast*(~CO0+~CASr2)))
-PHI2r2.D = PHI2r
-PHI2r2.CLK = RCLK_c
-PHI2r2.SP = VCC
-PHI2r2.LSR = GND
-
-comp 23: SLICE_42 (FSLICE)
-RCKE_2 = (~RCKEEN*(RASr3*~RASr2)+RCKEEN*((RASr+RASr2)+RASr3))
-RCKE_c.D = RCKE_2
-RCKE_c.CLK = RCLK_c
-RCKE_c.SP = VCC
-RCKE_c.LSR = GND
-m18_0_a3_3 = (RASr2*(~IS[2]*(~IS[1]*IS[0])))
-PHI2r.D = PHI2_c
-PHI2r.CLK = RCLK_c
-PHI2r.SP = VCC
-PHI2r.LSR = GND
-
-comp 24: SLICE_43 (FSLICE)
-N_462_0 = (~InitReady*Ready+InitReady*(~N_165*(Ready+Ready_0_sqmuxa_0_a3_2)+N_165*Ready))
-Ready.D = N_462_0
-Ready.CLK = RCLK_c
-Ready.SP = VCC
-Ready.LSR = GND
-RCKEEN_8_u_0_0 = (~S_0_i_o2[1]*(~InitReady*(~RASr2*Ready)+InitReady*(~RASr2+~Ready))+S_0_i_o2[1]*(InitReady*~Ready))
-PHI2r3.D = PHI2r2
-PHI2r3.CLK = RCLK_c
-PHI2r3.SP = VCC
-PHI2r3.LSR = GND
-
-comp 25: SLICE_44 (FSLICE)
-N_463_0 = (Ready_0_sqmuxa+Ready_fast)
-Ready_fast.D = N_463_0
-Ready_fast.CLK = RCLK_c
-Ready_fast.SP = VCC
-Ready_fast.LSR = GND
-Ready_0_sqmuxa = (Ready_0_sqmuxa_0_a3_2*(~Ready*(~N_165*InitReady)))
-RASr.D = ~nCRAS_c
-RASr.CLK = RCLK_c
-RASr.SP = VCC
-RASr.LSR = GND
-
-comp 26: SLICE_50 (FSLICE)
-S_0_i_o2[1] = (CO0+S[1])
-S[1].D = S_0_i_o2[1]
-S[1].CLK = RCLK_c
-S[1].SP = VCC
-S[1].LSR = ~RASr2
-nRRAS_0_sqmuxa = (~CO0*(~S[1]*Ready))
-
-comp 27: SLICE_51 (FSLICE)
-UFMCLK_RNO = (~UFMCLK_r_i_m4_xx_mm_1*(~UFMCLK_c*(~nUFMCS15*N_139_i)+UFMCLK_c*~nUFMCS15)+UFMCLK_r_i_m4_xx_mm_1*(UFMCLK_c*(~nUFMCS15*~N_139_i)))
-UFMCLK_c.D = UFMCLK_RNO
-UFMCLK_c.CLK = RCLK_c
-UFMCLK_c.SP = VCC
-UFMCLK_c.LSR = GND
-UFMCLK_r_i_m4_xx_mm_1 = (~N_129*((~CmdUFMCLK+~InitReady)+UFMCLK_r_i_a2_2_2)+N_129*((~CmdUFMCLK*InitReady)+UFMCLK_r_i_a2_2_2))
-RASr2.D = RASr
-RASr2.CLK = RCLK_c
-RASr2.SP = VCC
-RASr2.LSR = GND
-
-comp 28: SLICE_52 (FSLICE)
-UFMSDI_RNO = (~UFMSDI_r_xx_mm_1*(UFMSDI_c*(~nUFMCS15*~N_139_i))+UFMSDI_r_xx_mm_1*(~UFMSDI_c*(~nUFMCS15*N_139_i)+UFMSDI_c*~nUFMCS15))
-UFMSDI_c.D = UFMSDI_RNO
-UFMSDI_c.CLK = RCLK_c
-UFMSDI_c.SP = VCC
-UFMSDI_c.LSR = GND
-N_139_i = (~PHI2r3*~InitReady+PHI2r3*(~PHI2r2*(~InitReady+CmdSubmitted)+PHI2r2*~InitReady))
-RASr3.D = RASr2
-RASr3.CLK = RCLK_c
-RASr3.SP = VCC
-RASr3.LSR = GND
-
-comp 29: SLICE_55 (FSLICE)
-RA_c[4] = (~nRowColSel*RowA[4]+nRowColSel*MAin_c[4])
-WRD[4].D = Din_c[4]
-WRD[4].CLK = ~nCCAS_c
-WRD[4].SP = VCC
-WRD[4].LSR = GND
-WRD[5].D = Din_c[5]
-WRD[5].CLK = ~nCCAS_c
-WRD[5].SP = VCC
-WRD[5].LSR = GND
-
-comp 30: SLICE_56 (FSLICE)
-N_126 = (~FS[9]*FS[7]+FS[9]*(~FS[7]*FS[5]))
-WRD[6].D = Din_c[6]
-WRD[6].CLK = ~nCCAS_c
-WRD[6].SP = VCC
-WRD[6].LSR = GND
-C1WR_0_a2_0_11 = (Bank[7]*(Bank[6]*(Bank[5]*~Bank[2])))
-WRD[7].D = Din_c[7]
-WRD[7].CLK = ~nCCAS_c
-WRD[7].SP = VCC
-WRD[7].LSR = GND
-
-comp 31: SLICE_57 (FSLICE)
-XOR8MEG_3 = (~XOR8MEG_3_u_0_a3_2*N_171+XOR8MEG_3_u_0_a3_2*((~LEDEN+~Din_c[1])+N_171))
-XOR8MEG.D = XOR8MEG_3
-XOR8MEG.CLK = ~PHI2_c
-XOR8MEG.SP = XOR8MEG18
-XOR8MEG.LSR = GND
-XOR8MEG_3_u_0_a3_2 = (un1_Din_4*(~Din_c[3]*(Din_c[2]*Din_c[0])))
-
-comp 32: SLICE_58 (FSLICE)
-N_69 = (~UFMSDO_c*(~InitReady+Cmdn8MEGEN)+UFMSDO_c*(InitReady*Cmdn8MEGEN))
-n8MEGEN.D = N_69
-n8MEGEN.CLK = RCLK_c
-n8MEGEN.SP = N_31
-n8MEGEN.LSR = GND
-N_151 = (~N_51*(~InitReady*~FS[8]))
-
-comp 33: SLICE_59 (FSLICE)
-N_37_i = (~g0_1*(~S[1]*(~nRCAS_0_sqmuxa_1*N_41)+S[1]*~nRCAS_0_sqmuxa_1)+g0_1*(~nRCAS_0_sqmuxa_1*N_41))
-nRCAS_c.D = N_37_i
-nRCAS_c.CLK = RCLK_c
-nRCAS_c.SP = VCC
-nRCAS_c.LSR = GND
-N_41 = (~S[1]*((~N_160+N_155)+Ready)+S[1]*(~Ready*(~N_160+N_155)))
-
-comp 34: SLICE_60 (FSLICE)
-N_28_i = (~RCKEEN_8_u_0_a2_1_out*~N_24+RCKEEN_8_u_0_a2_1_out*(~N_28_i_1*(~N_24*CBR)+N_28_i_1*~N_24))
-nRCS_c.D = N_28_i
-nRCS_c.CLK = RCLK_c
-nRCS_c.SP = VCC
-nRCS_c.LSR = GND
-N_28_i_1 = (~CASr2*(FWEr_fast+CO0)+CASr2*(~CASr3*(CO0@FWEr_fast)+CASr3*(FWEr_fast+CO0)))
-
-comp 35: SLICE_61 (FSLICE)
-N_24_i = (~IS[0]*(~N_155*(~N_160*~nRRAS_5_u_i_0)+N_155*~nRRAS_5_u_i_0)+IS[0]*(N_155*~nRRAS_5_u_i_0))
-nRRAS_c.D = N_24_i
-nRRAS_c.CLK = RCLK_c
-nRRAS_c.SP = VCC
-nRRAS_c.LSR = GND
-nRRAS_5_u_i_0 = (Ready*(~RCKE_c*(RASr2*~S_0_i_o2[1])+RCKE_c*~S_0_i_o2[1]))
-
-comp 36: SLICE_62 (FSLICE)
-N_39_i = (~m18_0_a2_1*((~G_17_1+~FWEr)+nRCAS_0_sqmuxa_1)+m18_0_a2_1*((G_17_1*~FWEr)+nRCAS_0_sqmuxa_1))
-nRWE_c.D = N_39_i
-nRWE_c.CLK = RCLK_c
-nRWE_c.SP = VCC
-nRWE_c.LSR = GND
-nRCAS_0_sqmuxa_1 = (Ready*(RASr2*(~S_0_i_o2[1]*CBR_fast)))
-
-comp 37: SLICE_63 (FSLICE)
-nRowColSel_0_0 = (~S[1]*(~Ready*N_179+Ready*(CO0+N_179))+S[1]*(~Ready*N_179+Ready*(~CO0+N_179)))
-nRowColSel.D = nRowColSel_0_0
-nRowColSel.CLK = RCLK_c
-nRowColSel.SP = VCC
-nRowColSel.LSR = nRRAS_0_sqmuxa
-N_179 = (Ready*(FWEr*(~CBR*~CASr3)))
-
-comp 38: SLICE_64 (FSLICE)
-nUFMCS_s_0_N_5_i = (~nUFMCS_s_0_N_5_i_N_2L1*((N_139_i+nUFMCS15)+nUFMCS_c)+nUFMCS_s_0_N_5_i_N_2L1*(~nUFMCS_c*nUFMCS15+nUFMCS_c*(~N_139_i+nUFMCS15)))
-nUFMCS_c.D = nUFMCS_s_0_N_5_i
-nUFMCS_c.CLK = RCLK_c
-nUFMCS_c.SP = VCC
-nUFMCS_c.LSR = GND
-nUFMCS15 = (~N_51*(~InitReady*(~FS[11]*~FS[10])))
-
-comp 39: nRWE_RNO_1/SLICE_65 (FSLICE)
-m18_0_a2_1 = ((~RASr2*RCKE_c*~CO0*~S[1])*Ready)+((InitReady*m18_0_a3_3*~CO0*~S[1])*~Ready)
-
-comp 40: SLICE_66 (FSLICE)
-UFMCLK_r_i_a2_2_2 = (N_95_5*(N_95_3*(~InitReady*FS[16])))
-RowA[0].D = MAin_c[0]
-RowA[0].CLK = ~nCRAS_c
-RowA[0].SP = VCC
-RowA[0].LSR = ~Ready_fast
-nUFMCS_s_0_N_5_i_N_2L1 = (~UFMCLK_r_i_a2_2_2*(~InitReady+CmdUFMCS))
-RowA[1].D = MAin_c[1]
-RowA[1].CLK = ~nCRAS_c
-RowA[1].SP = VCC
-RowA[1].LSR = ~Ready_fast
-
-comp 41: SLICE_67 (FSLICE)
-XOR8MEG18 = (N_147*(~MAin_c[1]*(MAin_c[0]*CmdEnable)))
-RowA[4].D = MAin_c[4]
-RowA[4].CLK = ~nCRAS_c
-RowA[4].SP = VCC
-RowA[4].LSR = ~Ready_fast
-CmdUFMCLK_1_sqmuxa = (~Din_c[3]*(Din_c[5]*(~N_128*XOR8MEG18)))
-RowA[5].D = MAin_c[5]
-RowA[5].CLK = ~nCRAS_c
-RowA[5].SP = VCC
-RowA[5].LSR = ~Ready_fast
-
-comp 42: SLICE_68 (FSLICE)
-N_31 = (~un1_FS_14_i_a2_0_1*N_136+un1_FS_14_i_a2_0_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
-un1_FS_14_i_a2_0_1 = (~FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
-
-comp 43: SLICE_69 (FSLICE)
-N_33 = (~un1_FS_13_i_a2_1*N_136+un1_FS_13_i_a2_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
-un1_FS_13_i_a2_1 = (FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
-
-comp 44: SLICE_70 (FSLICE)
-C1WR_0_a2 = (N_147*MAin_c[1])
-Bank[0].D = Din_c[0]
-Bank[0].CLK = PHI2_c
-Bank[0].SP = VCC
-Bank[0].LSR = GND
-N_147 = (C1WR_0_a2_0_11*(C1WR_0_a2_0_10*(Bank[1]*Bank[0])))
-Bank[1].D = Din_c[1]
-Bank[1].CLK = PHI2_c
-Bank[1].SP = VCC
-Bank[1].LSR = GND
-
-comp 45: SLICE_71 (FSLICE)
-C1WR_0_a2_0_10 = (C1WR_0_a2_0_4*(C1WR_0_a2_0_3*(Bank[4]*Bank[3])))
-Bank[2].D = Din_c[2]
-Bank[2].CLK = PHI2_c
-Bank[2].SP = VCC
-Bank[2].LSR = GND
-C1WR_0_a2_0_4 = (MAin_c[7]*(MAin_c[6]*(MAin_c[5]*MAin_c[4])))
-Bank[3].D = Din_c[3]
-Bank[3].CLK = PHI2_c
-Bank[3].SP = VCC
-Bank[3].LSR = GND
-
-comp 46: SLICE_72 (FSLICE)
-N_129 = (~N_51*(FS[11]*FS[4])+N_51*FS[1])
-RowA[2].D = MAin_c[2]
-RowA[2].CLK = ~nCRAS_c
-RowA[2].SP = VCC
-RowA[2].LSR = ~Ready_fast
-N_51 = ((FS[12]+FS[16])+UFMSDI_ens2_i_o2_0_3)
-RowA[3].D = MAin_c[3]
-RowA[3].CLK = ~nCRAS_c
-RowA[3].SP = VCC
-RowA[3].LSR = ~Ready_fast
-
-comp 47: SLICE_73 (FSLICE)
-N_159 = (N_155+Ready)
-CmdUFMCLK.D = Din_c[1]
-CmdUFMCLK.CLK = ~PHI2_c
-CmdUFMCLK.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMCLK.LSR = GND
-N_155 = (((~InitReady+~RASr2)+S[1])+CO0)
-CmdUFMCS.D = Din_c[2]
-CmdUFMCS.CLK = ~PHI2_c
-CmdUFMCS.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMCS.LSR = GND
-
-comp 48: SLICE_74 (FSLICE)
-InitReady3 = (N_95_5*(N_95_3*(FS[16]*FS[10])))
-CmdUFMSDI.D = Din_c[0]
-CmdUFMSDI.CLK = ~PHI2_c
-CmdUFMSDI.SP = CmdUFMCLK_1_sqmuxa
-CmdUFMSDI.LSR = GND
-N_95_3 = (FS[14]*FS[11])
-
-comp 49: SLICE_75 (FSLICE)
-N_133 = (~N_128*(~Din_c[5]*~Din_c[1]))
-CASr.D = ~nCCAS_c
-CASr.CLK = RCLK_c
-CASr.SP = VCC
-CASr.LSR = GND
-N_128 = ((~Din_c[4]+Din_c[6])+Din_c[7])
-CASr2.D = CASr
-CASr2.CLK = RCLK_c
-CASr2.SP = VCC
-CASr2.LSR = GND
-
-comp 50: SLICE_76 (FSLICE)
-CmdEnable16_0_a2_4 = (~MAin_c[0]*(~Din_c[3]*(~Din_c[1]*CmdEnable16_4)))
-Bank[4].D = Din_c[4]
-Bank[4].CLK = PHI2_c
-Bank[4].SP = VCC
-Bank[4].LSR = GND
-CmdEnable16_4 = (~Din_c[5]*Din_c[0])
-Bank[5].D = Din_c[5]
-Bank[5].CLK = PHI2_c
-Bank[5].SP = VCC
-Bank[5].LSR = GND
-
-comp 51: SLICE_77 (FSLICE)
-CmdEnable16_0_a2_5 = (MAin_c[1]*(Din_c[6]*(~Din_c[2]*CmdEnable16_1)))
-Bank[6].D = Din_c[6]
-Bank[6].CLK = PHI2_c
-Bank[6].SP = VCC
-Bank[6].LSR = GND
-CmdEnable16_1 = (Din_c[7]*~Din_c[4])
-Bank[7].D = Din_c[7]
-Bank[7].CLK = PHI2_c
-Bank[7].SP = VCC
-Bank[7].LSR = GND
-
-comp 52: SLICE_78 (FSLICE)
-CmdEnable17_0_a2_4 = (~N_43*(MAin_c[1]*(~Din_c[6]*Din_c[2])))
-CBR.D = ~nCCAS_c
-CBR.CLK = ~nCRAS_c
-CBR.SP = VCC
-CBR.LSR = GND
-N_43 = (~Din_c[5]+~Din_c[3])
-CBR_fast.D = ~nCCAS_c
-CBR_fast.CLK = ~nCRAS_c
-CBR_fast.SP = VCC
-CBR_fast.LSR = GND
-
-comp 53: SLICE_79 (FSLICE)
-G_17_1 = (m6_0_a2_2*(S[1]*(CO0*~CBR)))
-WRD[0].D = Din_c[0]
-WRD[0].CLK = ~nCCAS_c
-WRD[0].SP = VCC
-WRD[0].LSR = GND
-m6_0_a2_2 = (Ready*(~CASr3*CASr2))
-WRD[1].D = Din_c[1]
-WRD[1].CLK = ~nCCAS_c
-WRD[1].SP = VCC
-WRD[1].LSR = GND
-
-comp 54: SLICE_80 (FSLICE)
-g0_1 = (~g4_0_0_0*(~FWEr*(~CO0*~CBR_fast))+g4_0_0_0*(~FWEr*(~CO0*~CBR_fast)+FWEr*(CO0*~CBR_fast)))
-RowA[8].D = MAin_c[8]
-RowA[8].CLK = ~nCRAS_c
-RowA[8].SP = VCC
-RowA[8].LSR = ~Ready_fast
-g4_0_0_0 = (~CASr3*CASr2)
-RowA[9].D = MAin_c[9]
-RowA[9].CLK = ~nCRAS_c
-RowA[9].SP = VCC
-RowA[9].LSR = ~Ready_fast
-
-comp 55: SLICE_81 (FSLICE)
-N_95_5 = (FS[17]*(FS[15]*(FS[13]*FS[12])))
-FWEr.D = ~nFWE_c
-FWEr.CLK = ~nCRAS_c
-FWEr.SP = VCC
-FWEr.LSR = GND
-UFMSDI_ens2_i_o2_0_3 = (((FS[13]+FS[14])+FS[15])+FS[17])
-FWEr_fast.D = ~nFWE_c
-FWEr_fast.CLK = ~nCRAS_c
-FWEr_fast.SP = VCC
-FWEr_fast.LSR = GND
-
-comp 56: SLICE_82 (FSLICE)
-CmdSubmitted_1_sqmuxa = (~Din_c[3]*(~N_128*XOR8MEG18)+Din_c[3]*(~Din_c[5]*(~N_128*XOR8MEG18)))
-CASr3.D = CASr2
-CASr3.CLK = RCLK_c
-CASr3.SP = VCC
-CASr3.LSR = GND
-N_132 = (~Din_c[3]*(~CmdLEDEN*N_128)+Din_c[3]*(~Din_c[5]*(~CmdLEDEN*N_128)+Din_c[5]*~CmdLEDEN))
-
-comp 57: SLICE_83 (FSLICE)
-N_165 = (~IS[2]+(~IS[1]+~IS[0]))
-RBA_c[0].D = CROW_c[0]
-RBA_c[0].CLK = ~nCRAS_c
-RBA_c[0].SP = VCC
-RBA_c[0].LSR = ~Ready_fast
-N_160 = ((IS[1]+IS[2])+IS[3])
-RBA_c[1].D = CROW_c[1]
-RBA_c[1].CLK = ~nCRAS_c
-RBA_c[1].SP = VCC
-RBA_c[1].LSR = ~Ready_fast
-
-comp 58: SLICE_84 (FSLICE)
-N_137_6 = (FS[10]*(~FS[7]*(~FS[6]*~FS[1])))
-UFMSDI_ens2_i_a2_4_2 = (FS[11]*(~FS[10]*(~FS[8]*FS[6])))
-
-comp 59: SLICE_85 (FSLICE)
-un1_Din_4 = (~Din_c[7]*(~Din_c[6]*(~Din_c[5]*~Din_c[4])))
-WRD[2].D = Din_c[2]
-WRD[2].CLK = ~nCCAS_c
-WRD[2].SP = VCC
-WRD[2].LSR = GND
-CmdEnable17_0_a2_3 = (~Din_c[4]*(Din_c[7]*(Din_c[0]*~Din_c[1])))
-WRD[3].D = Din_c[3]
-WRD[3].CLK = ~nCCAS_c
-WRD[3].SP = VCC
-WRD[3].LSR = GND
-
-comp 60: SLICE_86 (FSLICE)
-RA_c[9] = (~nRowColSel*RowA[9]+nRowColSel*MAin_c[9])
-RDQML_c = (~nRowColSel+~MAin_c[9])
-
-comp 61: SLICE_87 (FSLICE)
-N_137_8 = (N_151*(FS[11]*(~FS[9]*FS[4])))
-UFMSDI_r_xx_mm_1 = (~N_151*(~UFMSDI_ens2_i_a0*CmdUFMSDI)+N_151*~UFMSDI_ens2_i_a0)
-
-comp 62: SLICE_88 (FSLICE)
-RD_1_i = (nCCAS_c+nFWE_c)
-RowA[6].D = MAin_c[6]
-RowA[6].CLK = ~nCRAS_c
-RowA[6].SP = VCC
-RowA[6].LSR = ~Ready_fast
-C1WR_0_a2_0_3 = (~nFWE_c*(MAin_c[3]*MAin_c[2]))
-RowA[7].D = MAin_c[7]
-RowA[7].CLK = ~nCRAS_c
-RowA[7].SP = VCC
-RowA[7].LSR = ~Ready_fast
-
-comp 63: SLICE_89 (FSLICE)
-RA_c[8] = (~nRowColSel*RowA[8]+nRowColSel*MAin_c[8])
-RDQMH_c = (~nRowColSel+MAin_c[9])
-
-comp 64: SLICE_90 (FSLICE)
-RA_c[0] = (~nRowColSel*RowA[0]+nRowColSel*MAin_c[0])
-un1_CMDWR = (~MAin_c[1]*(MAin_c[0]*N_147)+MAin_c[1]*N_147)
-
-comp 65: SLICE_91 (FSLICE)
-RA_c[1] = (~nRowColSel*RowA[1]+nRowColSel*MAin_c[1])
-RA_c[7] = (~nRowColSel*RowA[7]+nRowColSel*MAin_c[7])
-
-comp 66: SLICE_92 (FSLICE)
-RA_c[2] = (~nRowColSel*RowA[2]+nRowColSel*MAin_c[2])
-RA_c[6] = (~nRowColSel*RowA[6]+nRowColSel*MAin_c[6])
-
-comp 67: SLICE_93 (FSLICE)
-RA_c[3] = (~nRowColSel*RowA[3]+nRowColSel*MAin_c[3])
-RA_c[5] = (~nRowColSel*RowA[5]+nRowColSel*MAin_c[5])
-
-comp 68: SLICE_94 (FSLICE)
-RCKEEN_8_u_0_a2_1_out = (S[1]*Ready)
-RA_c[10].D = ~IS[0]
-RA_c[10].CLK = RCLK_c
-RA_c[10].SP = VCC
-RA_c[10].LSR = RA10s_i
-N_159_i = (~N_155*~Ready)
+
+comp 0: SLICE_0 (FSLICE)
+
+comp 1: SLICE_1 (FSLICE)
+
+comp 2: SLICE_2 (FSLICE)
+
+comp 3: SLICE_3 (FSLICE)
+
+comp 4: SLICE_4 (FSLICE)
+
+comp 5: SLICE_5 (FSLICE)
+
+comp 6: SLICE_6 (FSLICE)
+
+comp 7: SLICE_7 (FSLICE)
+
+comp 8: SLICE_8 (FSLICE)
+
+comp 9: SLICE_9 (FSLICE)
+ADSubmitted_r = (~CmdEnable16*((~C1WR_0_a2*ADSubmitted)+CmdEnable17))
+ADSubmitted.D = ADSubmitted_r
+ADSubmitted.CLK = ~PHI2_c
+ADSubmitted.SP = VCC
+ADSubmitted.LSR = GND
+CmdEnable17 = (N_147*(MAin_c[0]*(CmdEnable17_0_a2_4*CmdEnable17_0_a2_3)))
+
+comp 10: SLICE_14 (FSLICE)
+C1Submitted_RNO = (~MAin_c[1]*(CmdEnable16+C1Submitted)+MAin_c[1]*(~N_147*(CmdEnable16+C1Submitted)+N_147*CmdEnable16))
+C1Submitted.D = C1Submitted_RNO
+C1Submitted.CLK = ~PHI2_c
+C1Submitted.SP = VCC
+C1Submitted.LSR = GND
+CmdEnable16 = (N_147*(CmdEnable16_0_a2_5*CmdEnable16_0_a2_4))
+
+comp 11: SLICE_19 (FSLICE)
+N_177_i = (~CO0+S[1])
+CO0.D = N_177_i
+CO0.CLK = RCLK_c
+CO0.SP = VCC
+CO0.LSR = ~RASr2
+Ready_0_sqmuxa_0_a3_2 = (S[1]*(~RASr2*(IS[3]*CO0)))
+
+comp 12: SLICE_20 (FSLICE)
+CmdEnable_s = ((CmdEnable+ADSubmitted)*CmdEnable16)+(((C1Submitted*un1_CMDWR*CmdEnable17)+(CmdEnable*CmdEnable17)+(~un1_CMDWR*CmdEnable))*~CmdEnable16)
+CmdEnable.D = CmdEnable_s
+CmdEnable.CLK = ~PHI2_c
+CmdEnable.SP = VCC
+CmdEnable.LSR = GND
+
+comp 13: SLICE_21 (FSLICE)
+N_21_i = (~N_152*(~N_133*~N_132)+N_152*(~N_133*(~N_132*LEDEN)))
+CmdLEDEN.D = N_21_i
+CmdLEDEN.CLK = ~PHI2_c
+CmdLEDEN.SP = XOR8MEG18
+CmdLEDEN.LSR = GND
+N_152 = (~N_128*(Din_c[5]*~Din_c[3]))
+
+comp 14: SLICE_22 (FSLICE)
+N_460_0 = (CmdSubmitted_1_sqmuxa+CmdSubmitted)
+CmdSubmitted.D = N_460_0
+CmdSubmitted.CLK = ~PHI2_c
+CmdSubmitted.SP = VCC
+CmdSubmitted.LSR = GND
+N_136 = (PHI2r3*(~PHI2r2*(InitReady*CmdSubmitted)))
+
+comp 15: SLICE_26 (FSLICE)
+N_19_i = (~n8MEGEN*(~N_152*~Cmdn8MEGEN_4_u_i_0)+n8MEGEN*~Cmdn8MEGEN_4_u_i_0)
+Cmdn8MEGEN.D = N_19_i
+Cmdn8MEGEN.CLK = ~PHI2_c
+Cmdn8MEGEN.SP = XOR8MEG18
+Cmdn8MEGEN.LSR = GND
+Cmdn8MEGEN_4_u_i_0 = (~N_128*(~N_43*(~Cmdn8MEGEN+CmdEnable16_4)+N_43*CmdEnable16_4)+N_128*~Cmdn8MEGEN)
+
+comp 16: SLICE_29 (FSLICE)
+N_64_i_i = (~N_155*(Ready@~IS[0])+N_155*IS[0])
+IS[0].D = N_64_i_i
+IS[0].CLK = RCLK_c
+IS[0].SP = VCC
+IS[0].LSR = GND
+N_24 = ((~N_160*(~N_155*IS[0])+N_160*~N_155)+nRRAS_5_u_i_0)
+
+comp 17: SLICE_30 (FSLICE)
+N_56_i = (IS[1]@IS[0])
+IS[1].D = N_56_i
+IS[1].CLK = RCLK_c
+IS[1].SP = N_159_i
+IS[1].LSR = GND
+N_60_i_i = (IS[2]@(IS[1]*IS[0]))
+IS[2].D = N_60_i_i
+IS[2].CLK = RCLK_c
+IS[2].SP = N_159_i
+IS[2].LSR = GND
+
+comp 18: SLICE_31 (FSLICE)
+N_61_i_i = (~IS[0]*IS[3]+IS[0]*(~IS[1]*IS[3]+IS[1]*(IS[2]@IS[3])))
+IS[3].D = N_61_i_i
+IS[3].CLK = RCLK_c
+IS[3].SP = N_159_i
+IS[3].LSR = GND
+RA10s_i = ((~IS[3]+(IS[1]+IS[2]))+N_159)
+
+comp 19: SLICE_32 (FSLICE)
+N_461_0 = (InitReady3+InitReady)
+InitReady.D = N_461_0
+InitReady.CLK = RCLK_c
+InitReady.SP = VCC
+InitReady.LSR = GND
+UFMSDI_ens2_i_a0 = (~UFMSDI_ens2_i_a2_4_2*~InitReady+UFMSDI_ens2_i_a2_4_2*(~N_126*~InitReady+N_126*(N_51*~InitReady)))
+
+comp 20: SLICE_33 (FSLICE)
+N_70 = (~UFMSDO_c*(~InitReady+CmdLEDEN)+UFMSDO_c*(InitReady*CmdLEDEN))
+LEDEN.D = N_70
+LEDEN.CLK = RCLK_c
+LEDEN.SP = N_33
+LEDEN.LSR = GND
+LED_c = ((~LEDEN+CBR)+nCRAS_c)
+
+comp 21: SLICE_39 (FSLICE)
+RA11_2 = (~n8MEGEN*(XOR8MEG@Din_c[6])+n8MEGEN*XOR8MEG)
+RA_c[11].D = RA11_2
+RA_c[11].CLK = PHI2_c
+RA_c[11].SP = VCC
+RA_c[11].LSR = ~Ready_fast
+N_171 = (~un1_Din_4*XOR8MEG)
+
+comp 22: SLICE_41 (FSLICE)
+RCKEEN_8 = (~Ready*RCKEEN_8_u_0_0+Ready*(~RCKEEN_8_u_1*RCKEEN_8_u_0_0+RCKEEN_8_u_1*(~CBR+RCKEEN_8_u_0_0)))
+RCKEEN.D = RCKEEN_8
+RCKEEN.CLK = RCLK_c
+RCKEEN.SP = VCC
+RCKEEN.LSR = GND
+RCKEEN_8_u_1 = (~S[1]*(~FWEr_fast+CO0)+S[1]*(FWEr_fast*(~CO0+~CASr2)))
+PHI2r2.D = PHI2r
+PHI2r2.CLK = RCLK_c
+PHI2r2.SP = VCC
+PHI2r2.LSR = GND
+
+comp 23: SLICE_42 (FSLICE)
+RCKE_2 = (~RCKEEN*(RASr3*~RASr2)+RCKEEN*((RASr+RASr2)+RASr3))
+RCKE_c.D = RCKE_2
+RCKE_c.CLK = RCLK_c
+RCKE_c.SP = VCC
+RCKE_c.LSR = GND
+m18_0_a3_3 = (RASr2*(~IS[2]*(~IS[1]*IS[0])))
+PHI2r.D = PHI2_c
+PHI2r.CLK = RCLK_c
+PHI2r.SP = VCC
+PHI2r.LSR = GND
+
+comp 24: SLICE_43 (FSLICE)
+N_462_0 = (~InitReady*Ready+InitReady*(~N_165*(Ready+Ready_0_sqmuxa_0_a3_2)+N_165*Ready))
+Ready.D = N_462_0
+Ready.CLK = RCLK_c
+Ready.SP = VCC
+Ready.LSR = GND
+RCKEEN_8_u_0_0 = (~S_0_i_o2[1]*(~InitReady*(~RASr2*Ready)+InitReady*(~RASr2+~Ready))+S_0_i_o2[1]*(InitReady*~Ready))
+PHI2r3.D = PHI2r2
+PHI2r3.CLK = RCLK_c
+PHI2r3.SP = VCC
+PHI2r3.LSR = GND
+
+comp 25: SLICE_44 (FSLICE)
+N_463_0 = (Ready_0_sqmuxa+Ready_fast)
+Ready_fast.D = N_463_0
+Ready_fast.CLK = RCLK_c
+Ready_fast.SP = VCC
+Ready_fast.LSR = GND
+Ready_0_sqmuxa = (Ready_0_sqmuxa_0_a3_2*(~Ready*(~N_165*InitReady)))
+RASr.D = ~nCRAS_c
+RASr.CLK = RCLK_c
+RASr.SP = VCC
+RASr.LSR = GND
+
+comp 26: SLICE_50 (FSLICE)
+S_0_i_o2[1] = (CO0+S[1])
+S[1].D = S_0_i_o2[1]
+S[1].CLK = RCLK_c
+S[1].SP = VCC
+S[1].LSR = ~RASr2
+nRRAS_0_sqmuxa = (~CO0*(~S[1]*Ready))
+
+comp 27: SLICE_51 (FSLICE)
+UFMCLK_RNO = (~UFMCLK_r_i_m4_xx_mm_1*(~UFMCLK_c*(~nUFMCS15*N_139_i)+UFMCLK_c*~nUFMCS15)+UFMCLK_r_i_m4_xx_mm_1*(UFMCLK_c*(~nUFMCS15*~N_139_i)))
+UFMCLK_c.D = UFMCLK_RNO
+UFMCLK_c.CLK = RCLK_c
+UFMCLK_c.SP = VCC
+UFMCLK_c.LSR = GND
+UFMCLK_r_i_m4_xx_mm_1 = (~N_129*((~CmdUFMCLK+~InitReady)+UFMCLK_r_i_a2_2_2)+N_129*((~CmdUFMCLK*InitReady)+UFMCLK_r_i_a2_2_2))
+RASr2.D = RASr
+RASr2.CLK = RCLK_c
+RASr2.SP = VCC
+RASr2.LSR = GND
+
+comp 28: SLICE_52 (FSLICE)
+UFMSDI_RNO = (~UFMSDI_r_xx_mm_1*(UFMSDI_c*(~nUFMCS15*~N_139_i))+UFMSDI_r_xx_mm_1*(~UFMSDI_c*(~nUFMCS15*N_139_i)+UFMSDI_c*~nUFMCS15))
+UFMSDI_c.D = UFMSDI_RNO
+UFMSDI_c.CLK = RCLK_c
+UFMSDI_c.SP = VCC
+UFMSDI_c.LSR = GND
+N_139_i = (~PHI2r3*~InitReady+PHI2r3*(~PHI2r2*(~InitReady+CmdSubmitted)+PHI2r2*~InitReady))
+RASr3.D = RASr2
+RASr3.CLK = RCLK_c
+RASr3.SP = VCC
+RASr3.LSR = GND
+
+comp 29: SLICE_55 (FSLICE)
+RA_c[4] = (~nRowColSel*RowA[4]+nRowColSel*MAin_c[4])
+WRD[4].D = Din_c[4]
+WRD[4].CLK = ~nCCAS_c
+WRD[4].SP = VCC
+WRD[4].LSR = GND
+WRD[5].D = Din_c[5]
+WRD[5].CLK = ~nCCAS_c
+WRD[5].SP = VCC
+WRD[5].LSR = GND
+
+comp 30: SLICE_56 (FSLICE)
+N_126 = (~FS[9]*FS[7]+FS[9]*(~FS[7]*FS[5]))
+WRD[6].D = Din_c[6]
+WRD[6].CLK = ~nCCAS_c
+WRD[6].SP = VCC
+WRD[6].LSR = GND
+C1WR_0_a2_0_11 = (Bank[7]*(Bank[6]*(Bank[5]*~Bank[2])))
+WRD[7].D = Din_c[7]
+WRD[7].CLK = ~nCCAS_c
+WRD[7].SP = VCC
+WRD[7].LSR = GND
+
+comp 31: SLICE_57 (FSLICE)
+XOR8MEG_3 = (~XOR8MEG_3_u_0_a3_2*N_171+XOR8MEG_3_u_0_a3_2*((~LEDEN+~Din_c[1])+N_171))
+XOR8MEG.D = XOR8MEG_3
+XOR8MEG.CLK = ~PHI2_c
+XOR8MEG.SP = XOR8MEG18
+XOR8MEG.LSR = GND
+XOR8MEG_3_u_0_a3_2 = (un1_Din_4*(~Din_c[3]*(Din_c[2]*Din_c[0])))
+
+comp 32: SLICE_58 (FSLICE)
+N_69 = (~UFMSDO_c*(~InitReady+Cmdn8MEGEN)+UFMSDO_c*(InitReady*Cmdn8MEGEN))
+n8MEGEN.D = N_69
+n8MEGEN.CLK = RCLK_c
+n8MEGEN.SP = N_31
+n8MEGEN.LSR = GND
+N_151 = (~N_51*(~InitReady*~FS[8]))
+
+comp 33: SLICE_59 (FSLICE)
+N_37_i = (~g0_1*(~S[1]*(~nRCAS_0_sqmuxa_1*N_41)+S[1]*~nRCAS_0_sqmuxa_1)+g0_1*(~nRCAS_0_sqmuxa_1*N_41))
+nRCAS_c.D = N_37_i
+nRCAS_c.CLK = RCLK_c
+nRCAS_c.SP = VCC
+nRCAS_c.LSR = GND
+N_41 = (~S[1]*((~N_160+N_155)+Ready)+S[1]*(~Ready*(~N_160+N_155)))
+
+comp 34: SLICE_60 (FSLICE)
+N_28_i = (~RCKEEN_8_u_0_a2_1_out*~N_24+RCKEEN_8_u_0_a2_1_out*(~N_28_i_1*(~N_24*CBR)+N_28_i_1*~N_24))
+nRCS_c.D = N_28_i
+nRCS_c.CLK = RCLK_c
+nRCS_c.SP = VCC
+nRCS_c.LSR = GND
+N_28_i_1 = (~CASr2*(FWEr_fast+CO0)+CASr2*(~CASr3*(CO0@FWEr_fast)+CASr3*(FWEr_fast+CO0)))
+
+comp 35: SLICE_61 (FSLICE)
+N_24_i = (~IS[0]*(~N_155*(~N_160*~nRRAS_5_u_i_0)+N_155*~nRRAS_5_u_i_0)+IS[0]*(N_155*~nRRAS_5_u_i_0))
+nRRAS_c.D = N_24_i
+nRRAS_c.CLK = RCLK_c
+nRRAS_c.SP = VCC
+nRRAS_c.LSR = GND
+nRRAS_5_u_i_0 = (Ready*(~RCKE_c*(RASr2*~S_0_i_o2[1])+RCKE_c*~S_0_i_o2[1]))
+
+comp 36: SLICE_62 (FSLICE)
+N_39_i = (~m18_0_a2_1*((~G_17_1+~FWEr)+nRCAS_0_sqmuxa_1)+m18_0_a2_1*((G_17_1*~FWEr)+nRCAS_0_sqmuxa_1))
+nRWE_c.D = N_39_i
+nRWE_c.CLK = RCLK_c
+nRWE_c.SP = VCC
+nRWE_c.LSR = GND
+nRCAS_0_sqmuxa_1 = (Ready*(RASr2*(~S_0_i_o2[1]*CBR_fast)))
+
+comp 37: SLICE_63 (FSLICE)
+nRowColSel_0_0 = (~S[1]*(~Ready*N_179+Ready*(CO0+N_179))+S[1]*(~Ready*N_179+Ready*(~CO0+N_179)))
+nRowColSel.D = nRowColSel_0_0
+nRowColSel.CLK = RCLK_c
+nRowColSel.SP = VCC
+nRowColSel.LSR = nRRAS_0_sqmuxa
+N_179 = (Ready*(FWEr*(~CBR*~CASr3)))
+
+comp 38: SLICE_64 (FSLICE)
+nUFMCS_s_0_N_5_i = (~nUFMCS_s_0_N_5_i_N_2L1*((N_139_i+nUFMCS15)+nUFMCS_c)+nUFMCS_s_0_N_5_i_N_2L1*(~nUFMCS_c*nUFMCS15+nUFMCS_c*(~N_139_i+nUFMCS15)))
+nUFMCS_c.D = nUFMCS_s_0_N_5_i
+nUFMCS_c.CLK = RCLK_c
+nUFMCS_c.SP = VCC
+nUFMCS_c.LSR = GND
+nUFMCS15 = (~N_51*(~InitReady*(~FS[11]*~FS[10])))
+
+comp 39: nRWE_RNO_1/SLICE_65 (FSLICE)
+m18_0_a2_1 = ((~RASr2*RCKE_c*~CO0*~S[1])*Ready)+((InitReady*m18_0_a3_3*~CO0*~S[1])*~Ready)
+
+comp 40: SLICE_66 (FSLICE)
+UFMCLK_r_i_a2_2_2 = (N_95_5*(N_95_3*(~InitReady*FS[16])))
+RowA[0].D = MAin_c[0]
+RowA[0].CLK = ~nCRAS_c
+RowA[0].SP = VCC
+RowA[0].LSR = ~Ready_fast
+nUFMCS_s_0_N_5_i_N_2L1 = (~UFMCLK_r_i_a2_2_2*(~InitReady+CmdUFMCS))
+RowA[1].D = MAin_c[1]
+RowA[1].CLK = ~nCRAS_c
+RowA[1].SP = VCC
+RowA[1].LSR = ~Ready_fast
+
+comp 41: SLICE_67 (FSLICE)
+XOR8MEG18 = (N_147*(~MAin_c[1]*(MAin_c[0]*CmdEnable)))
+RowA[4].D = MAin_c[4]
+RowA[4].CLK = ~nCRAS_c
+RowA[4].SP = VCC
+RowA[4].LSR = ~Ready_fast
+CmdUFMCLK_1_sqmuxa = (~Din_c[3]*(Din_c[5]*(~N_128*XOR8MEG18)))
+RowA[5].D = MAin_c[5]
+RowA[5].CLK = ~nCRAS_c
+RowA[5].SP = VCC
+RowA[5].LSR = ~Ready_fast
+
+comp 42: SLICE_68 (FSLICE)
+N_31 = (~un1_FS_14_i_a2_0_1*N_136+un1_FS_14_i_a2_0_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
+un1_FS_14_i_a2_0_1 = (~FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
+
+comp 43: SLICE_69 (FSLICE)
+N_33 = (~un1_FS_13_i_a2_1*N_136+un1_FS_13_i_a2_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
+un1_FS_13_i_a2_1 = (FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
+
+comp 44: SLICE_70 (FSLICE)
+C1WR_0_a2 = (N_147*MAin_c[1])
+Bank[0].D = Din_c[0]
+Bank[0].CLK = PHI2_c
+Bank[0].SP = VCC
+Bank[0].LSR = GND
+N_147 = (C1WR_0_a2_0_11*(C1WR_0_a2_0_10*(Bank[1]*Bank[0])))
+Bank[1].D = Din_c[1]
+Bank[1].CLK = PHI2_c
+Bank[1].SP = VCC
+Bank[1].LSR = GND
+
+comp 45: SLICE_71 (FSLICE)
+C1WR_0_a2_0_10 = (C1WR_0_a2_0_4*(C1WR_0_a2_0_3*(Bank[4]*Bank[3])))
+Bank[2].D = Din_c[2]
+Bank[2].CLK = PHI2_c
+Bank[2].SP = VCC
+Bank[2].LSR = GND
+C1WR_0_a2_0_4 = (MAin_c[7]*(MAin_c[6]*(MAin_c[5]*MAin_c[4])))
+Bank[3].D = Din_c[3]
+Bank[3].CLK = PHI2_c
+Bank[3].SP = VCC
+Bank[3].LSR = GND
+
+comp 46: SLICE_72 (FSLICE)
+N_129 = (~N_51*(FS[11]*FS[4])+N_51*FS[1])
+RowA[2].D = MAin_c[2]
+RowA[2].CLK = ~nCRAS_c
+RowA[2].SP = VCC
+RowA[2].LSR = ~Ready_fast
+N_51 = ((FS[12]+FS[16])+UFMSDI_ens2_i_o2_0_3)
+RowA[3].D = MAin_c[3]
+RowA[3].CLK = ~nCRAS_c
+RowA[3].SP = VCC
+RowA[3].LSR = ~Ready_fast
+
+comp 47: SLICE_73 (FSLICE)
+N_159 = (N_155+Ready)
+CmdUFMCLK.D = Din_c[1]
+CmdUFMCLK.CLK = ~PHI2_c
+CmdUFMCLK.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMCLK.LSR = GND
+N_155 = (((~InitReady+~RASr2)+S[1])+CO0)
+CmdUFMCS.D = Din_c[2]
+CmdUFMCS.CLK = ~PHI2_c
+CmdUFMCS.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMCS.LSR = GND
+
+comp 48: SLICE_74 (FSLICE)
+InitReady3 = (N_95_5*(N_95_3*(FS[16]*FS[10])))
+CmdUFMSDI.D = Din_c[0]
+CmdUFMSDI.CLK = ~PHI2_c
+CmdUFMSDI.SP = CmdUFMCLK_1_sqmuxa
+CmdUFMSDI.LSR = GND
+N_95_3 = (FS[14]*FS[11])
+
+comp 49: SLICE_75 (FSLICE)
+N_133 = (~N_128*(~Din_c[5]*~Din_c[1]))
+CASr.D = ~nCCAS_c
+CASr.CLK = RCLK_c
+CASr.SP = VCC
+CASr.LSR = GND
+N_128 = ((~Din_c[4]+Din_c[6])+Din_c[7])
+CASr2.D = CASr
+CASr2.CLK = RCLK_c
+CASr2.SP = VCC
+CASr2.LSR = GND
+
+comp 50: SLICE_76 (FSLICE)
+CmdEnable16_0_a2_4 = (~MAin_c[0]*(~Din_c[3]*(~Din_c[1]*CmdEnable16_4)))
+Bank[4].D = Din_c[4]
+Bank[4].CLK = PHI2_c
+Bank[4].SP = VCC
+Bank[4].LSR = GND
+CmdEnable16_4 = (~Din_c[5]*Din_c[0])
+Bank[5].D = Din_c[5]
+Bank[5].CLK = PHI2_c
+Bank[5].SP = VCC
+Bank[5].LSR = GND
+
+comp 51: SLICE_77 (FSLICE)
+CmdEnable16_0_a2_5 = (MAin_c[1]*(Din_c[6]*(~Din_c[2]*CmdEnable16_1)))
+Bank[6].D = Din_c[6]
+Bank[6].CLK = PHI2_c
+Bank[6].SP = VCC
+Bank[6].LSR = GND
+CmdEnable16_1 = (Din_c[7]*~Din_c[4])
+Bank[7].D = Din_c[7]
+Bank[7].CLK = PHI2_c
+Bank[7].SP = VCC
+Bank[7].LSR = GND
+
+comp 52: SLICE_78 (FSLICE)
+CmdEnable17_0_a2_4 = (~N_43*(MAin_c[1]*(~Din_c[6]*Din_c[2])))
+CBR.D = ~nCCAS_c
+CBR.CLK = ~nCRAS_c
+CBR.SP = VCC
+CBR.LSR = GND
+N_43 = (~Din_c[5]+~Din_c[3])
+CBR_fast.D = ~nCCAS_c
+CBR_fast.CLK = ~nCRAS_c
+CBR_fast.SP = VCC
+CBR_fast.LSR = GND
+
+comp 53: SLICE_79 (FSLICE)
+G_17_1 = (m6_0_a2_2*(S[1]*(CO0*~CBR)))
+WRD[0].D = Din_c[0]
+WRD[0].CLK = ~nCCAS_c
+WRD[0].SP = VCC
+WRD[0].LSR = GND
+m6_0_a2_2 = (Ready*(~CASr3*CASr2))
+WRD[1].D = Din_c[1]
+WRD[1].CLK = ~nCCAS_c
+WRD[1].SP = VCC
+WRD[1].LSR = GND
+
+comp 54: SLICE_80 (FSLICE)
+g0_1 = (~g4_0_0_0*(~FWEr*(~CO0*~CBR_fast))+g4_0_0_0*(~FWEr*(~CO0*~CBR_fast)+FWEr*(CO0*~CBR_fast)))
+RowA[8].D = MAin_c[8]
+RowA[8].CLK = ~nCRAS_c
+RowA[8].SP = VCC
+RowA[8].LSR = ~Ready_fast
+g4_0_0_0 = (~CASr3*CASr2)
+RowA[9].D = MAin_c[9]
+RowA[9].CLK = ~nCRAS_c
+RowA[9].SP = VCC
+RowA[9].LSR = ~Ready_fast
+
+comp 55: SLICE_81 (FSLICE)
+N_95_5 = (FS[17]*(FS[15]*(FS[13]*FS[12])))
+FWEr.D = ~nFWE_c
+FWEr.CLK = ~nCRAS_c
+FWEr.SP = VCC
+FWEr.LSR = GND
+UFMSDI_ens2_i_o2_0_3 = (((FS[13]+FS[14])+FS[15])+FS[17])
+FWEr_fast.D = ~nFWE_c
+FWEr_fast.CLK = ~nCRAS_c
+FWEr_fast.SP = VCC
+FWEr_fast.LSR = GND
+
+comp 56: SLICE_82 (FSLICE)
+CmdSubmitted_1_sqmuxa = (~Din_c[3]*(~N_128*XOR8MEG18)+Din_c[3]*(~Din_c[5]*(~N_128*XOR8MEG18)))
+CASr3.D = CASr2
+CASr3.CLK = RCLK_c
+CASr3.SP = VCC
+CASr3.LSR = GND
+N_132 = (~Din_c[3]*(~CmdLEDEN*N_128)+Din_c[3]*(~Din_c[5]*(~CmdLEDEN*N_128)+Din_c[5]*~CmdLEDEN))
+
+comp 57: SLICE_83 (FSLICE)
+N_165 = (~IS[2]+(~IS[1]+~IS[0]))
+RBA_c[0].D = CROW_c[0]
+RBA_c[0].CLK = ~nCRAS_c
+RBA_c[0].SP = VCC
+RBA_c[0].LSR = ~Ready_fast
+N_160 = ((IS[1]+IS[2])+IS[3])
+RBA_c[1].D = CROW_c[1]
+RBA_c[1].CLK = ~nCRAS_c
+RBA_c[1].SP = VCC
+RBA_c[1].LSR = ~Ready_fast
+
+comp 58: SLICE_84 (FSLICE)
+N_137_6 = (FS[10]*(~FS[7]*(~FS[6]*~FS[1])))
+UFMSDI_ens2_i_a2_4_2 = (FS[11]*(~FS[10]*(~FS[8]*FS[6])))
+
+comp 59: SLICE_85 (FSLICE)
+un1_Din_4 = (~Din_c[7]*(~Din_c[6]*(~Din_c[5]*~Din_c[4])))
+WRD[2].D = Din_c[2]
+WRD[2].CLK = ~nCCAS_c
+WRD[2].SP = VCC
+WRD[2].LSR = GND
+CmdEnable17_0_a2_3 = (~Din_c[4]*(Din_c[7]*(Din_c[0]*~Din_c[1])))
+WRD[3].D = Din_c[3]
+WRD[3].CLK = ~nCCAS_c
+WRD[3].SP = VCC
+WRD[3].LSR = GND
+
+comp 60: SLICE_86 (FSLICE)
+RA_c[9] = (~nRowColSel*RowA[9]+nRowColSel*MAin_c[9])
+RDQML_c = (~nRowColSel+~MAin_c[9])
+
+comp 61: SLICE_87 (FSLICE)
+N_137_8 = (N_151*(FS[11]*(~FS[9]*FS[4])))
+UFMSDI_r_xx_mm_1 = (~N_151*(~UFMSDI_ens2_i_a0*CmdUFMSDI)+N_151*~UFMSDI_ens2_i_a0)
+
+comp 62: SLICE_88 (FSLICE)
+RD_1_i = (nCCAS_c+nFWE_c)
+RowA[6].D = MAin_c[6]
+RowA[6].CLK = ~nCRAS_c
+RowA[6].SP = VCC
+RowA[6].LSR = ~Ready_fast
+C1WR_0_a2_0_3 = (~nFWE_c*(MAin_c[3]*MAin_c[2]))
+RowA[7].D = MAin_c[7]
+RowA[7].CLK = ~nCRAS_c
+RowA[7].SP = VCC
+RowA[7].LSR = ~Ready_fast
+
+comp 63: SLICE_89 (FSLICE)
+RA_c[8] = (~nRowColSel*RowA[8]+nRowColSel*MAin_c[8])
+RDQMH_c = (~nRowColSel+MAin_c[9])
+
+comp 64: SLICE_90 (FSLICE)
+RA_c[0] = (~nRowColSel*RowA[0]+nRowColSel*MAin_c[0])
+un1_CMDWR = (~MAin_c[1]*(MAin_c[0]*N_147)+MAin_c[1]*N_147)
+
+comp 65: SLICE_91 (FSLICE)
+RA_c[1] = (~nRowColSel*RowA[1]+nRowColSel*MAin_c[1])
+RA_c[7] = (~nRowColSel*RowA[7]+nRowColSel*MAin_c[7])
+
+comp 66: SLICE_92 (FSLICE)
+RA_c[2] = (~nRowColSel*RowA[2]+nRowColSel*MAin_c[2])
+RA_c[6] = (~nRowColSel*RowA[6]+nRowColSel*MAin_c[6])
+
+comp 67: SLICE_93 (FSLICE)
+RA_c[3] = (~nRowColSel*RowA[3]+nRowColSel*MAin_c[3])
+RA_c[5] = (~nRowColSel*RowA[5]+nRowColSel*MAin_c[5])
+
+comp 68: SLICE_94 (FSLICE)
+RCKEEN_8_u_0_a2_1_out = (S[1]*Ready)
+RA_c[10].D = ~IS[0]
+RA_c[10].CLK = RCLK_c
+RA_c[10].SP = VCC
+RA_c[10].LSR = RA10s_i
+N_159_i = (~N_155*~Ready)
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd
index f58180a12831f24a2a0570336c37a2c7aa55e3eb..786ae1eee91ce499981789fd2474b219fb536f6b 100644
GIT binary patch
delta 40
wcmdnj#JR7DbAkx-!{q-P#UDwq)%Z;?*4LlRDCy8_FWGJ{$++EKlIg!X06oAC4*&oF

delta 40
wcmdnj#JR7DbAkx-o!B@uCG6tQPQE=Ub5X@l5xAeB-4L&09UyWQ2+n{

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd
index 37f17ab29ad3c4b822fd750b2848b933cde194d3..b9c78fda601b9df2a004e2d6c8726d04b7024511 100644
GIT binary patch
literal 144453
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Aug 16 20:59:41 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | -| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | -| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | -| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3A | | | | -| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | -| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | -| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | -| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | -| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | -| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | -| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | -| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | -| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | -| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | -| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | -| 28/2 | unused, PULL:DOWN | | | PB4B | | | | -| 29/2 | unused, PULL:DOWN | | | PB4C | | | | -| 30/2 | unused, PULL:DOWN | | | PB4D | | | | -| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | -| 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | -| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | -| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | -| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | -| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | -| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | -| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | -| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | -| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | -| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | -| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | -| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | -| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | -| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | -| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | -| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | -| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | -| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | -| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | -| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | -| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | -| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | -| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | -| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | -| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | -| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | -| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "63"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "62"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "15"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:42 2023 - +PAD Specification File +*************************** + +PART TYPE: LCMXO2-640HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.39 + +Sat Aug 19 21:55:06 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | 3.3V | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | +| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | +| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3A | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | +| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | +| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | +| 28/2 | unused, PULL:DOWN | | | PB4B | | | | +| 29/2 | unused, PULL:DOWN | | | PB4C | | | | +| 30/2 | unused, PULL:DOWN | | | PB4D | | | | +| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | +| 45/2 | unused, PULL:DOWN | | | PB14A | | | | +| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | +| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | +| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | +| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | +| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | +| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | +| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | +| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | +| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | +| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | +| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | +| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | +| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "15"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sat Aug 19 21:55:09 2023 + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par index 5638eea..1691b38 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par @@ -1,237 +1,216 @@ - -Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" -Wed Aug 16 20:59:37 2023 - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf -Preference file: LCMXO2_640HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 63+4(JTAG)/80 84% used - 63+4(JTAG)/79 85% bonded - IOLOGIC 25/80 31% used - - SLICE 117/320 36% used - - EFB 1/1 100% used - - -Number of Signals: 380 -Number of Connections: 1008 - -Pin Constraint Summary: - 63 out of 63 pins locked (100% locked). - -The following 3 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 46) - PHI2_c (driver: PHI2, clk load #: 19) - nCRAS_c (driver: nCRAS, clk load #: 10) - -WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. - -The following 2 signals are selected to use the secondary clock routing resources: - nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) - un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10) - -WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -.............. -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 55012. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 54994 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 4 out of 80 (5%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 - SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 - SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 - - PRIMARY : 3 out of 8 (37%) - SECONDARY: 2 out of 8 (25%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. - 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. - Number of PIO comps: 63; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 3.3V | - | -| 1 | 20 / 20 (100%) | 3.3V | - | -| 2 | 12 / 20 ( 60%) | 3.3V | - | -| 3 | 18 / 20 ( 90%) | 3.3V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - -0 connections routed; 1008 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 - -Completed router resource preassignment. Real time: 5 secs - -Start NBR router at 20:59:43 08/16/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 20:59:43 08/16/23 - -Start NBR section for initial routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 20:59:43 08/16/23 -Level 1, iteration 1 -0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23 -Level 4, iteration 0 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs -Level 4, iteration 0 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs - -Start NBR section for re-routing at 20:59:44 08/16/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs - -Start NBR section for post-routing at 20:59:44 08/16/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 4.922ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=wb_clk loads=1 clock_loads=1 - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 1008 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 4.922 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.088 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" +Sat Aug 19 21:55:01 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf +Preference file: LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 63+4(JTAG)/80 84% used + 63+4(JTAG)/79 85% bonded + IOLOGIC 25/80 31% used + + SLICE 113/320 35% used + + EFB 1/1 100% used + + +Number of Signals: 374 +Number of Connections: 978 + +Pin Constraint Summary: + 63 out of 63 pins locked (100% locked). + +The following 3 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 47) + PHI2_c (driver: PHI2, clk load #: 21) + nCRAS_c (driver: nCRAS, clk load #: 10) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +............ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.................... +Placer score = 53481. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 53406 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 4 out of 80 (5%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 + SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 + + PRIMARY : 3 out of 8 (37%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. + 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. + Number of PIO comps: 63; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 3.3V | - | +| 1 | 20 / 20 (100%) | 3.3V | - | +| 2 | 12 / 20 ( 60%) | 3.3V | - | +| 3 | 18 / 20 ( 90%) | 3.3V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 5 secs + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 978 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 8 secs + +Start NBR router at 21:55:09 08/19/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:55:09 08/19/23 + +Start NBR section for initial routing at 21:55:10 08/19/23 +Level 1, iteration 1 +0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.085ns/0.000ns; real time: 9 secs +Level 2, iteration 1 +0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.138ns/0.000ns; real time: 9 secs +Level 3, iteration 1 +0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 7.276ns/0.000ns; real time: 9 secs +Level 4, iteration 1 +10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:55:10 08/19/23 +Level 4, iteration 1 +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23 + +Start NBR section for re-routing at 21:55:10 08/19/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs + +Start NBR section for post-routing at 21:55:10 08/19/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 6.966ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 9 secs +Total REAL time: 9 secs +Completely routed. +End of route. 978 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 6.966 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 9 secs +Total REAL time to completion: 10 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd index 1e33411..04f8cf8 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd @@ -1,47 +1,42 @@ -[ActiveSupport PAR] -; Global primary clocks -GLOBAL_PRIMARY_USED = 3; -; Global primary clock #0 -GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; -GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_0_LOADNUM = 46; -; Global primary clock #1 -GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; -GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_1_LOADNUM = 19; -; Global primary clock #2 -GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c; -GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_2_LOADNUM = 10; -; # of global secondary clocks -GLOBAL_SECONDARY_USED = 2; -; Global secondary clock #0 -GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i; -GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE; -GLOBAL_SECONDARY_0_LOADNUM = 10; -GLOBAL_SECONDARY_0_SIGTYPE = CE; -; Global secondary clock #1 -GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c; -GLOBAL_SECONDARY_1_DRIVERTYPE = PIO; -GLOBAL_SECONDARY_1_LOADNUM = 10; -GLOBAL_SECONDARY_1_SIGTYPE = CLK; -; I/O Bank 0 Usage -BANK_0_USED = 13; -BANK_0_AVAIL = 19; -BANK_0_VCCIO = 3.3V; -BANK_0_VREF1 = NA; -; I/O Bank 1 Usage -BANK_1_USED = 20; -BANK_1_AVAIL = 20; -BANK_1_VCCIO = 3.3V; -BANK_1_VREF1 = NA; -; I/O Bank 2 Usage -BANK_2_USED = 12; -BANK_2_AVAIL = 20; -BANK_2_VCCIO = 3.3V; -BANK_2_VREF1 = NA; -; I/O Bank 3 Usage -BANK_3_USED = 18; -BANK_3_AVAIL = 20; -BANK_3_VCCIO = 3.3V; -BANK_3_VREF1 = NA; +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 3; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_0_LOADNUM = 47; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 21; +; Global primary clock #2 +GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c; +GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_2_LOADNUM = 10; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCCAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 10; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 13; +BANK_0_AVAIL = 19; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 20; +BANK_1_AVAIL = 20; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 12; +BANK_2_AVAIL = 20; +BANK_2_VCCIO = 3.3V; +BANK_2_VREF1 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 18; +BANK_3_AVAIL = 20; +BANK_3_VCCIO = 3.3V; +BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par index ccd14db..99d8fe8 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par @@ -1,27 +1,27 @@ -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Wed Aug 16 20:59:37 2023 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t -LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui --msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml - - -Preference file: LCMXO2_640HC_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 4.922 0 0.088 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sat Aug 19 21:55:01 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t +LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui +-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Preference file: LCMXO2_640HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 6.966 0 0.304 0 10 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 10 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc index ec074a2..8417bb5 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc @@ -1 +1 @@ -DRC detected 0 errors and 0 warnings. +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi index f410ddc..8e09e7b 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi @@ -1,4350 +1,4316 @@ -(edif RAM2GS - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timeStamp 2023 8 16 20 59 35) - (author "Synopsys, Inc.") - (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) - ) - ) - (library LUCENT - (edifLevel 0) - (technology (numberDefinition )) - (cell CCU2D (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A0 (direction INPUT)) - (port B0 (direction INPUT)) - (port C0 (direction INPUT)) - (port D0 (direction INPUT)) - (port A1 (direction INPUT)) - (port B1 (direction INPUT)) - (port C1 (direction INPUT)) - (port D1 (direction INPUT)) - (port CIN (direction INPUT)) - (port COUT (direction OUTPUT)) - (port S0 (direction OUTPUT)) - (port S1 (direction OUTPUT)) - ) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0000")) - (property INIT0 (string "0000")) - ) - ) - (cell BB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port B (direction INOUT)) - (port I (direction INPUT)) - (port T (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell OB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell IB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell FD1S3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3JX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell IFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3BX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell ORCALUT4 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port C (direction INPUT)) - (port D (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell PFUMX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port ALUT (direction INPUT)) - (port BLUT (direction INPUT)) - (port C0 (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell GSR (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port GSR (direction INPUT)) - ) - ) - ) - (cell INV (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VHI (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VLO (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - ) - (library work - (edifLevel 0) - (technology (numberDefinition )) - (cell EFB (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port WBCLKI (direction INPUT)) - (port WBRSTI (direction INPUT)) - (port WBCYCI (direction INPUT)) - (port WBSTBI (direction INPUT)) - (port WBWEI (direction INPUT)) - (port WBADRI7 (direction INPUT)) - (port WBADRI6 (direction INPUT)) - (port WBADRI5 (direction INPUT)) - (port WBADRI4 (direction INPUT)) - (port WBADRI3 (direction INPUT)) - (port WBADRI2 (direction INPUT)) - (port WBADRI1 (direction INPUT)) - (port WBADRI0 (direction INPUT)) - (port WBDATI7 (direction INPUT)) - (port WBDATI6 (direction INPUT)) - (port WBDATI5 (direction INPUT)) - (port WBDATI4 (direction INPUT)) - (port WBDATI3 (direction INPUT)) - (port WBDATI2 (direction INPUT)) - (port WBDATI1 (direction INPUT)) - (port WBDATI0 (direction INPUT)) - (port PLL0DATI7 (direction INPUT)) - (port PLL0DATI6 (direction INPUT)) - (port PLL0DATI5 (direction INPUT)) - (port PLL0DATI4 (direction INPUT)) - (port PLL0DATI3 (direction INPUT)) - (port PLL0DATI2 (direction INPUT)) - (port PLL0DATI1 (direction INPUT)) - (port PLL0DATI0 (direction INPUT)) - (port PLL0ACKI (direction INPUT)) - (port PLL1DATI7 (direction INPUT)) - (port PLL1DATI6 (direction INPUT)) - (port PLL1DATI5 (direction INPUT)) - (port PLL1DATI4 (direction INPUT)) - (port PLL1DATI3 (direction INPUT)) - (port PLL1DATI2 (direction INPUT)) - (port PLL1DATI1 (direction INPUT)) - (port PLL1DATI0 (direction INPUT)) - (port PLL1ACKI (direction INPUT)) - (port I2C1SCLI (direction INPUT)) - (port I2C1SDAI (direction INPUT)) - (port I2C2SCLI (direction INPUT)) - (port I2C2SDAI (direction INPUT)) - (port SPISCKI (direction INPUT)) - (port SPIMISOI (direction INPUT)) - (port SPIMOSII (direction INPUT)) - (port SPISCSN (direction INPUT)) - (port TCCLKI (direction INPUT)) - (port TCRSTN (direction INPUT)) - (port TCIC (direction INPUT)) - (port UFMSN (direction INPUT)) - (port WBDATO7 (direction OUTPUT)) - (port WBDATO6 (direction OUTPUT)) - (port WBDATO5 (direction OUTPUT)) - (port WBDATO4 (direction OUTPUT)) - (port WBDATO3 (direction OUTPUT)) - (port WBDATO2 (direction OUTPUT)) - (port WBDATO1 (direction OUTPUT)) - (port WBDATO0 (direction OUTPUT)) - (port WBACKO (direction OUTPUT)) - (port PLLCLKO (direction OUTPUT)) - (port PLLRSTO (direction OUTPUT)) - (port PLL0STBO (direction OUTPUT)) - (port PLL1STBO (direction OUTPUT)) - (port PLLWEO (direction OUTPUT)) - (port PLLADRO4 (direction OUTPUT)) - (port PLLADRO3 (direction OUTPUT)) - (port PLLADRO2 (direction OUTPUT)) - (port PLLADRO1 (direction OUTPUT)) - (port PLLADRO0 (direction OUTPUT)) - (port PLLDATO7 (direction OUTPUT)) - (port PLLDATO6 (direction OUTPUT)) - (port PLLDATO5 (direction OUTPUT)) - (port PLLDATO4 (direction OUTPUT)) - (port PLLDATO3 (direction OUTPUT)) - (port PLLDATO2 (direction OUTPUT)) - (port PLLDATO1 (direction OUTPUT)) - (port PLLDATO0 (direction OUTPUT)) - (port I2C1SCLO (direction OUTPUT)) - (port I2C1SCLOEN (direction OUTPUT)) - (port I2C1SDAO (direction OUTPUT)) - (port I2C1SDAOEN (direction OUTPUT)) - (port I2C2SCLO (direction OUTPUT)) - (port I2C2SCLOEN (direction OUTPUT)) - (port I2C2SDAO (direction OUTPUT)) - (port I2C2SDAOEN (direction OUTPUT)) - (port I2C1IRQO (direction OUTPUT)) - (port I2C2IRQO (direction OUTPUT)) - (port SPISCKO (direction OUTPUT)) - (port SPISCKEN (direction OUTPUT)) - (port SPIMISOO (direction OUTPUT)) - (port SPIMISOEN (direction OUTPUT)) - (port SPIMOSIO (direction OUTPUT)) - (port SPIMOSIEN (direction OUTPUT)) - (port SPIMCSN0 (direction OUTPUT)) - (port SPIMCSN1 (direction OUTPUT)) - (port SPIMCSN2 (direction OUTPUT)) - (port SPIMCSN3 (direction OUTPUT)) - (port SPIMCSN4 (direction OUTPUT)) - (port SPIMCSN5 (direction OUTPUT)) - (port SPIMCSN6 (direction OUTPUT)) - (port SPIMCSN7 (direction OUTPUT)) - (port SPICSNEN (direction OUTPUT)) - (port SPIIRQO (direction OUTPUT)) - (port TCINT (direction OUTPUT)) - (port TCOC (direction OUTPUT)) - (port WBCUFMIRQ (direction OUTPUT)) - (port CFGWAKE (direction OUTPUT)) - (port CFGSTDBY (direction OUTPUT)) - ) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_SCLK_SEL (string "PCLOCK")) - (property TC_MODE (string "CTCM")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C2_ADDRESSING (string "7BIT")) - (property I2C1_ADDRESSING (string "7BIT")) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "NONE")) - (property UFM_INIT_ALL_ZEROS (string "ENABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 1)) - (property DEV_DENSITY (string "640L")) - (property EFB_WB_CLK_FREQ (string "62.5")) - (property EFB_UFM (string "ENABLED")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property EFB_SPI (string "DISABLED")) - (property EFB_I2C2 (string "DISABLED")) - (property EFB_I2C1 (string "DISABLED")) - (property orig_inst_of (string "EFB")) - ) - ) - (cell REFB (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT)) - (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) - (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) - (port wb_we (direction INPUT)) - (port wb_cyc_stb (direction INPUT)) - (port wb_rst (direction INPUT)) - (port wb_clk (direction INPUT)) - ) - (contents - (instance EFBInst_0 (viewRef verilog (cellRef EFB)) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "NONE")) - (property UFM_INIT_ALL_ZEROS (string "ENABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 1)) - (property DEV_DENSITY (string "640L")) - (property EFB_UFM (string "ENABLED")) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_MODE (string "CTCM")) - (property TC_SCLK_SEL (string "PCLOCK")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property EFB_SPI (string "DISABLED")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C2_ADDRESSING (string "7BIT")) - (property EFB_I2C2 (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C1_ADDRESSING (string "7BIT")) - (property EFB_I2C1 (string "DISABLED")) - (property EFB_WB_CLK_FREQ (string "62.5")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net wb_clk (joined - (portRef wb_clk) - (portRef WBCLKI (instanceRef EFBInst_0)) - )) - (net wb_rst (joined - (portRef wb_rst) - (portRef WBRSTI (instanceRef EFBInst_0)) - )) - (net wb_cyc_stb (joined - (portRef wb_cyc_stb) - (portRef WBSTBI (instanceRef EFBInst_0)) - (portRef WBCYCI (instanceRef EFBInst_0)) - )) - (net wb_we (joined - (portRef wb_we) - (portRef WBWEI (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_7 "wb_adr[7]") (joined - (portRef (member wb_adr 0)) - (portRef WBADRI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_6 "wb_adr[6]") (joined - (portRef (member wb_adr 1)) - (portRef WBADRI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_5 "wb_adr[5]") (joined - (portRef (member wb_adr 2)) - (portRef WBADRI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_4 "wb_adr[4]") (joined - (portRef (member wb_adr 3)) - (portRef WBADRI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_3 "wb_adr[3]") (joined - (portRef (member wb_adr 4)) - (portRef WBADRI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_2 "wb_adr[2]") (joined - (portRef (member wb_adr 5)) - (portRef WBADRI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_1 "wb_adr[1]") (joined - (portRef (member wb_adr 6)) - (portRef WBADRI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_0 "wb_adr[0]") (joined - (portRef (member wb_adr 7)) - (portRef WBADRI0 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_7 "wb_dati[7]") (joined - (portRef (member wb_dati 0)) - (portRef WBDATI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_6 "wb_dati[6]") (joined - (portRef (member wb_dati 1)) - (portRef WBDATI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_5 "wb_dati[5]") (joined - (portRef (member wb_dati 2)) - (portRef WBDATI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_4 "wb_dati[4]") (joined - (portRef (member wb_dati 3)) - (portRef WBDATI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_3 "wb_dati[3]") (joined - (portRef (member wb_dati 4)) - (portRef WBDATI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_2 "wb_dati[2]") (joined - (portRef (member wb_dati 5)) - (portRef WBDATI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_1 "wb_dati[1]") (joined - (portRef (member wb_dati 6)) - (portRef WBDATI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_0 "wb_dati[0]") (joined - (portRef (member wb_dati 7)) - (portRef WBDATI0 (instanceRef EFBInst_0)) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef TCIC (instanceRef EFBInst_0)) - (portRef TCRSTN (instanceRef EFBInst_0)) - (portRef TCCLKI (instanceRef EFBInst_0)) - (portRef SPISCSN (instanceRef EFBInst_0)) - (portRef SPIMOSII (instanceRef EFBInst_0)) - (portRef SPIMISOI (instanceRef EFBInst_0)) - (portRef SPISCKI (instanceRef EFBInst_0)) - (portRef I2C2SDAI (instanceRef EFBInst_0)) - (portRef I2C2SCLI (instanceRef EFBInst_0)) - (portRef I2C1SDAI (instanceRef EFBInst_0)) - (portRef I2C1SCLI (instanceRef EFBInst_0)) - (portRef PLL1ACKI (instanceRef EFBInst_0)) - (portRef PLL1DATI0 (instanceRef EFBInst_0)) - (portRef PLL1DATI1 (instanceRef EFBInst_0)) - (portRef PLL1DATI2 (instanceRef EFBInst_0)) - (portRef PLL1DATI3 (instanceRef EFBInst_0)) - (portRef PLL1DATI4 (instanceRef EFBInst_0)) - (portRef PLL1DATI5 (instanceRef EFBInst_0)) - (portRef PLL1DATI6 (instanceRef EFBInst_0)) - (portRef PLL1DATI7 (instanceRef EFBInst_0)) - (portRef PLL0ACKI (instanceRef EFBInst_0)) - (portRef PLL0DATI0 (instanceRef EFBInst_0)) - (portRef PLL0DATI1 (instanceRef EFBInst_0)) - (portRef PLL0DATI2 (instanceRef EFBInst_0)) - (portRef PLL0DATI3 (instanceRef EFBInst_0)) - (portRef PLL0DATI4 (instanceRef EFBInst_0)) - (portRef PLL0DATI5 (instanceRef EFBInst_0)) - (portRef PLL0DATI6 (instanceRef EFBInst_0)) - (portRef PLL0DATI7 (instanceRef EFBInst_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef UFMSN (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_7 "wb_dat_o_1[7]") (joined - (portRef WBDATO7 (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_6 "wb_dat_o_1[6]") (joined - (portRef WBDATO6 (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_5 "wb_dat_o_1[5]") (joined - (portRef WBDATO5 (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_4 "wb_dat_o_1[4]") (joined - (portRef WBDATO4 (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_3 "wb_dat_o_1[3]") (joined - (portRef WBDATO3 (instanceRef EFBInst_0)) - )) - (net (rename wb_dat_o_1_2 "wb_dat_o_1[2]") (joined - (portRef WBDATO2 (instanceRef EFBInst_0)) - )) - (net (rename wb_dato_1 "wb_dato[1]") (joined - (portRef WBDATO1 (instanceRef EFBInst_0)) - (portRef (member wb_dato 0)) - )) - (net (rename wb_dato_0 "wb_dato[0]") (joined - (portRef WBDATO0 (instanceRef EFBInst_0)) - (portRef (member wb_dato 1)) - )) - (net wb_ack_o (joined - (portRef WBACKO (instanceRef EFBInst_0)) - )) - (net PLLCLKO (joined - (portRef PLLCLKO (instanceRef EFBInst_0)) - )) - (net PLLRSTO (joined - (portRef PLLRSTO (instanceRef EFBInst_0)) - )) - (net PLL0STBO (joined - (portRef PLL0STBO (instanceRef EFBInst_0)) - )) - (net PLL1STBO (joined - (portRef PLL1STBO (instanceRef EFBInst_0)) - )) - (net PLLWEO (joined - (portRef PLLWEO (instanceRef EFBInst_0)) - )) - (net PLLADRO4 (joined - (portRef PLLADRO4 (instanceRef EFBInst_0)) - )) - (net PLLADRO3 (joined - (portRef PLLADRO3 (instanceRef EFBInst_0)) - )) - (net PLLADRO2 (joined - (portRef PLLADRO2 (instanceRef EFBInst_0)) - )) - (net PLLADRO1 (joined - (portRef PLLADRO1 (instanceRef EFBInst_0)) - )) - (net PLLADRO0 (joined - (portRef PLLADRO0 (instanceRef EFBInst_0)) - )) - (net PLLDATO7 (joined - (portRef PLLDATO7 (instanceRef EFBInst_0)) - )) - (net PLLDATO6 (joined - (portRef PLLDATO6 (instanceRef EFBInst_0)) - )) - (net PLLDATO5 (joined - (portRef PLLDATO5 (instanceRef EFBInst_0)) - )) - (net PLLDATO4 (joined - (portRef PLLDATO4 (instanceRef EFBInst_0)) - )) - (net PLLDATO3 (joined - (portRef PLLDATO3 (instanceRef EFBInst_0)) - )) - (net PLLDATO2 (joined - (portRef PLLDATO2 (instanceRef EFBInst_0)) - )) - (net PLLDATO1 (joined - (portRef PLLDATO1 (instanceRef EFBInst_0)) - )) - (net PLLDATO0 (joined - (portRef PLLDATO0 (instanceRef EFBInst_0)) - )) - (net I2C1SCLO (joined - (portRef I2C1SCLO (instanceRef EFBInst_0)) - )) - (net I2C1SCLOEN (joined - (portRef I2C1SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C1SDAO (joined - (portRef I2C1SDAO (instanceRef EFBInst_0)) - )) - (net I2C1SDAOEN (joined - (portRef I2C1SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C2SCLO (joined - (portRef I2C2SCLO (instanceRef EFBInst_0)) - )) - (net I2C2SCLOEN (joined - (portRef I2C2SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C2SDAO (joined - (portRef I2C2SDAO (instanceRef EFBInst_0)) - )) - (net I2C2SDAOEN (joined - (portRef I2C2SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C1IRQO (joined - (portRef I2C1IRQO (instanceRef EFBInst_0)) - )) - (net I2C2IRQO (joined - (portRef I2C2IRQO (instanceRef EFBInst_0)) - )) - (net SPISCKO (joined - (portRef SPISCKO (instanceRef EFBInst_0)) - )) - (net SPISCKEN (joined - (portRef SPISCKEN (instanceRef EFBInst_0)) - )) - (net SPIMISOO (joined - (portRef SPIMISOO (instanceRef EFBInst_0)) - )) - (net SPIMISOEN (joined - (portRef SPIMISOEN (instanceRef EFBInst_0)) - )) - (net SPIMOSIO (joined - (portRef SPIMOSIO (instanceRef EFBInst_0)) - )) - (net SPIMOSIEN (joined - (portRef SPIMOSIEN (instanceRef EFBInst_0)) - )) - (net SPIMCSN0 (joined - (portRef SPIMCSN0 (instanceRef EFBInst_0)) - )) - (net SPIMCSN1 (joined - (portRef SPIMCSN1 (instanceRef EFBInst_0)) - )) - (net SPIMCSN2 (joined - (portRef SPIMCSN2 (instanceRef EFBInst_0)) - )) - (net SPIMCSN3 (joined - (portRef SPIMCSN3 (instanceRef EFBInst_0)) - )) - (net SPIMCSN4 (joined - (portRef SPIMCSN4 (instanceRef EFBInst_0)) - )) - (net SPIMCSN5 (joined - (portRef SPIMCSN5 (instanceRef EFBInst_0)) - )) - (net SPIMCSN6 (joined - (portRef SPIMCSN6 (instanceRef EFBInst_0)) - )) - (net SPIMCSN7 (joined - (portRef SPIMCSN7 (instanceRef EFBInst_0)) - )) - (net SPICSNEN (joined - (portRef SPICSNEN (instanceRef EFBInst_0)) - )) - (net SPIIRQO (joined - (portRef SPIIRQO (instanceRef EFBInst_0)) - )) - (net TCINT (joined - (portRef TCINT (instanceRef EFBInst_0)) - )) - (net TCOC (joined - (portRef TCOC (instanceRef EFBInst_0)) - )) - (net wbc_ufm_irq (joined - (portRef WBCUFMIRQ (instanceRef EFBInst_0)) - )) - (net CFGWAKE (joined - (portRef CFGWAKE (instanceRef EFBInst_0)) - )) - (net CFGSTDBY (joined - (portRef CFGSTDBY (instanceRef EFBInst_0)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "REFB")) - ) - ) - (cell RAM2GS (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port PHI2 (direction INPUT)) - (port (array (rename main "MAin[9:0]") 10) (direction INPUT)) - (port (array (rename crow "CROW[1:0]") 2) (direction INPUT)) - (port (array (rename din "Din[7:0]") 8) (direction INPUT)) - (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) - (port nCCAS (direction INPUT)) - (port nCRAS (direction INPUT)) - (port nFWE (direction INPUT)) - (port LED (direction OUTPUT)) - (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT)) - (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) - (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) - (port nRCS (direction OUTPUT)) - (port RCLK (direction INPUT)) - (port RCKE (direction OUTPUT)) - (port nRWE (direction OUTPUT)) - (port nRRAS (direction OUTPUT)) - (port nRCAS (direction OUTPUT)) - (port RDQMH (direction OUTPUT)) - (port RDQML (direction OUTPUT)) - ) - (contents - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) - ) - (instance wb_rst_RNO_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename FS_RNI1T8E_7 "FS_RNI1T8E[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename FS_RNIPIOA_11 "FS_RNIPIOA[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C+(!B+!A))")) - ) - (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D (!C A+C (B+A)))")) - ) - (instance (rename FS_RNIPIOA_0_11 "FS_RNIPIOA_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (!B A))")) - ) - (instance wb_cyc_stb_65_0_iv_0_a2_2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C !A)")) - ) - (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename wb_adr_10_0_a2_RNIQ1AL_1 "wb_adr_10_0_a2_RNIQ1AL[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename FS_RNIU61E_5 "FS_RNIU61E[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !A+C (!B !A))+D (!B !A))")) - ) - (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) - ) - (instance wb_clk_9_iv_i_o2_2_RNIOE4Q (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename wb_adr_10_0_a2_RNIIJC01_1 "wb_adr_10_0_a2_RNIIJC01[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B+A)+C B)+D B)")) - ) - (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) - ) - (instance wb_we_0_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance wb_rst_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance (rename wb_adr_10_0_o2_0_RNI0U1R_0 "wb_adr_10_0_o2_0_RNI0U1R[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename wb_dati_10_0_iv_0_RNO_0 "wb_dati_10_0_iv_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C (B+A)+C A))")) - ) - (instance wb_clk_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance wb_clk_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) - ) - (instance wb_clk_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance CmdSubmitted_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "TRUE")) - ) - (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - ) - (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance RA11_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance wb_we (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance wb_rst (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance wb_clk (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdUFMData (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdSubmitted_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CMDUFMWrite (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance wb_cyc_stb_65_0_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) - ) - (instance (rename wb_dati_10_1_iv_0_4 "wb_dati_10_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B !A)))")) - ) - (instance (rename wb_adr_10_0_0 "wb_adr_10_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) - ) - (instance wb_we_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B !A)))")) - ) - (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C B))")) - ) - (instance un1_FS_7_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B A)))")) - ) - (instance (rename wb_adr_10_0_i_o2_6 "wb_adr_10_0_i_o2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (B+A))")) - ) - (instance (rename wb_adr_10_0_i_o2_5 "wb_adr_10_0_i_o2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (B+A))")) - ) - (instance (rename wb_adr_10_0_i_o2_4 "wb_adr_10_0_i_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (B+A))")) - ) - (instance (rename wb_dati_10_0_iv_0_0 "wb_dati_10_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_10_1_iv_0_3 "wb_dati_10_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) - ) - (instance (rename wb_dati_10_1_iv_0_7 "wb_dati_10_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B A)))")) - ) - (instance (rename wb_dati_10_1_iv_0_1_4 "wb_dati_10_1_iv_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 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(portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef B (instanceRef IS_RNO_2)) - (portRef A (instanceRef RA10_0io_RNO_0)) - (portRef C (instanceRef IS_RNO_3)) - )) - (net (rename IS_2 "IS[2]") (joined - (portRef Q (instanceRef IS_2)) - (portRef C (instanceRef nRWE_0io_RNO_1)) - (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef C (instanceRef IS_RNO_2)) - (portRef B (instanceRef RA10_0io_RNO_0)) - (portRef B (instanceRef IS_RNO_3)) - )) - (net (rename FS_0 "FS[0]") (joined - (portRef Q (instanceRef FS_0)) - (portRef A1 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef un1_FS_7_i_a4_0_0)) - )) - (net (rename FS_1 "FS[1]") (joined - (portRef Q (instanceRef FS_1)) - (portRef A0 (instanceRef FS_cry_0_1)) - (portRef A (instanceRef un1_FS_7_i_a4_0_3)) - )) - (net (rename FS_10 "FS[10]") (joined - (portRef Q (instanceRef FS_10)) - (portRef A1 (instanceRef FS_cry_0_9)) - (portRef C (instanceRef wb_adr_10_0_a2_3_0)) - (portRef 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(portRef A (instanceRef FS_RNIPIOA_0_11)) - (portRef A (instanceRef FS_RNIPIOA_11)) - (portRef D (instanceRef FS_RNI1T8E_7)) - )) - (net (rename FS_11 "FS[11]") (joined - (portRef Q (instanceRef FS_11)) - (portRef A0 (instanceRef FS_cry_0_11)) - (portRef B (instanceRef wb_adr_10_0_a2_3_0)) - (portRef C (instanceRef wb_dati_10_1_iv_0_o2_1_5)) - (portRef B (instanceRef wb_we_0_0_a2_0)) - (portRef A (instanceRef wb_we_0_0_o2)) - (portRef A (instanceRef wb_adr_10_0_o2_0_0)) - (portRef B (instanceRef wb_dati_10_1_iv_0_m2_3)) - (portRef C (instanceRef wb_dati_10_1_iv_0_a4_0_1_6)) - (portRef C (instanceRef wb_dati_10_1_iv_0_a4_0_0_4)) - (portRef B (instanceRef wb_adr_10_0_a2_1)) - (portRef C (instanceRef wb_adr_10_0_a4_0_0_0)) - (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_1)) - (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_0_7)) - (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_o2_1)) - (portRef A (instanceRef wb_adr_10_0_a2_6_0)) - (portRef D (instanceRef wb_dati_10_0_iv_0_RNO_0)) - (portRef D (instanceRef wb_rst_RNO)) - (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO)) - (portRef C (instanceRef FS_RNIPIOA_0_11)) - (portRef C (instanceRef FS_RNIPIOA_11)) - (portRef C (instanceRef FS_RNI1T8E_7)) - )) - (net (rename FS_12 "FS[12]") (joined - (portRef Q (instanceRef FS_12)) - (portRef A1 (instanceRef FS_cry_0_11)) - (portRef A (instanceRef wb_adr_10_0_a2_3_0)) - (portRef B (instanceRef wb_dati_10_1_iv_0_1_6)) - (portRef D (instanceRef wb_dati_10_1_iv_0_o2_1_5)) - (portRef B (instanceRef wb_we_0_0_o2)) - (portRef B (instanceRef wb_adr_10_0_o2_0_0)) - (portRef C (instanceRef wb_dati_10_1_iv_0_m2_3)) - (portRef D (instanceRef wb_dati_10_1_iv_0_a4_0_1_6)) - (portRef D (instanceRef wb_dati_10_1_iv_0_a4_0_0_4)) - (portRef C (instanceRef wb_adr_10_0_a2_1)) - (portRef D (instanceRef wb_adr_10_0_a4_0_0_0)) - (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_1)) - (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2_4)) - (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_o2_1)) - (portRef A (instanceRef wb_we_0_0_a4)) - (portRef B (instanceRef wb_adr_10_0_a2_6_0)) - (portRef C (instanceRef wb_adr_10_0_a4_7_0)) - (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_4)) - (portRef A (instanceRef wb_dati_10_1_iv_0_1_7)) - (portRef A (instanceRef wb_we_0_0)) - (portRef C (instanceRef wb_dati_10_0_iv_0_RNO_0)) - (portRef C (instanceRef wb_rst_RNO)) - (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO)) - (portRef B (instanceRef FS_RNIPIOA_0_11)) - (portRef B (instanceRef FS_RNIPIOA_11)) - (portRef A (instanceRef FS_RNI1T8E_7)) - )) - (net (rename FS_13 "FS[13]") (joined - (portRef Q (instanceRef FS_13)) - (portRef A0 (instanceRef FS_cry_0_13)) - (portRef D (instanceRef wb_rst_3_0_a2)) - (portRef A (instanceRef InitReady3_0_a4_2)) - (portRef A (instanceRef wb_clk_9_iv_i_o2)) - (portRef D (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q)) - )) - (net (rename FS_14 "FS[14]") (joined - (portRef Q (instanceRef FS_14)) - (portRef A1 (instanceRef FS_cry_0_13)) - (portRef B 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(instanceRef CASr)) - (portRef CK (instanceRef CASr2)) - (portRef CK (instanceRef CASr3)) - (portRef CK (instanceRef FS_17)) - (portRef CK (instanceRef FS_16)) - (portRef CK (instanceRef FS_15)) - (portRef CK (instanceRef FS_14)) - (portRef CK (instanceRef FS_13)) - (portRef CK (instanceRef FS_12)) - (portRef CK (instanceRef FS_11)) - (portRef CK (instanceRef FS_10)) - (portRef CK (instanceRef FS_9)) - (portRef CK (instanceRef FS_8)) - (portRef CK (instanceRef FS_7)) - (portRef CK (instanceRef FS_6)) - (portRef CK (instanceRef FS_5)) - (portRef CK (instanceRef FS_4)) - (portRef CK (instanceRef FS_3)) - (portRef CK (instanceRef FS_2)) - (portRef CK (instanceRef FS_1)) - (portRef CK (instanceRef FS_0)) - (portRef CK (instanceRef IS_3)) - (portRef CK (instanceRef IS_2)) - (portRef CK (instanceRef IS_1)) - (portRef CK (instanceRef IS_0)) - (portRef CK (instanceRef InitReady)) - (portRef CK (instanceRef LEDEN)) - (portRef CK (instanceRef PHI2r2)) - (portRef CK (instanceRef PHI2r3)) - (portRef CK (instanceRef RASr)) - (portRef CK (instanceRef RASr2)) - (portRef CK (instanceRef RASr3)) - (portRef CK (instanceRef RCKE)) - (portRef CK (instanceRef RCKEEN)) - (portRef CK (instanceRef Ready)) - (portRef CK (instanceRef Ready_fast)) - (portRef CK (instanceRef S_1)) - (portRef CK (instanceRef S_0)) - (portRef CK (instanceRef n8MEGEN)) - (portRef CK (instanceRef nRowColSel)) - (portRef CK (instanceRef wb_adr_7)) - (portRef CK (instanceRef wb_adr_6)) - (portRef CK (instanceRef wb_adr_5)) - (portRef CK (instanceRef wb_adr_4)) - (portRef CK (instanceRef wb_adr_3)) - (portRef CK (instanceRef wb_adr_2)) - (portRef CK (instanceRef wb_adr_1)) - (portRef CK (instanceRef wb_adr_0)) - (portRef CK (instanceRef wb_clk)) - (portRef CK (instanceRef wb_cyc_stb)) - (portRef CK (instanceRef wb_dati_7)) - (portRef CK (instanceRef wb_dati_6)) - (portRef CK (instanceRef wb_dati_5)) - (portRef CK (instanceRef wb_dati_4)) - (portRef CK (instanceRef wb_dati_3)) - (portRef CK (instanceRef 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(portRef I (instanceRef nRRAS_pad)) - )) - (net nRRAS (joined - (portRef O (instanceRef nRRAS_pad)) - (portRef nRRAS) - )) - (net nRCAS_c (joined - (portRef Q (instanceRef nRCAS_0io)) - (portRef I (instanceRef nRCAS_pad)) - )) - (net nRCAS (joined - (portRef O (instanceRef nRCAS_pad)) - (portRef nRCAS) - )) - (net RDQMH_c (joined - (portRef Z (instanceRef RDQMH_pad_RNO)) - (portRef I (instanceRef RDQMH_pad)) - )) - (net RDQMH (joined - (portRef O (instanceRef RDQMH_pad)) - (portRef RDQMH) - )) - (net RDQML_c (joined - (portRef Z (instanceRef RDQML_0)) - (portRef I (instanceRef RDQML_pad)) - )) - (net RDQML (joined - (portRef O (instanceRef RDQML_pad)) - (portRef RDQML) - )) - (net N_545_0 (joined - (portRef Z (instanceRef CmdSubmitted_RNO)) - (portRef D (instanceRef CmdSubmitted)) - )) - (net N_548_0 (joined - (portRef Z (instanceRef CmdSubmitted_fast_RNO)) - (portRef D (instanceRef CmdSubmitted_fast)) - )) - (net N_546_0 (joined - (portRef Z (instanceRef InitReady_RNO)) - (portRef D (instanceRef InitReady)) - )) - (net N_547_0 (joined - (portRef Z (instanceRef Ready_RNO)) - (portRef D (instanceRef Ready)) - )) - (net N_549_0 (joined - (portRef Z (instanceRef Ready_fast_RNO)) - (portRef D (instanceRef Ready_fast)) - )) - (net nFWE_c_i (joined - (portRef Z (instanceRef nFWE_pad_RNI420B)) - (portRef D (instanceRef FWEr)) - (portRef D (instanceRef FWEr_fast)) - )) - (net nCRAS_c_i_0 (joined - (portRef Z (instanceRef RASr_RNO)) - (portRef D (instanceRef RASr)) - )) - (net nCCAS_c_i (joined - (portRef Z (instanceRef nCCAS_pad_RNISUR8)) - (portRef D (instanceRef CASr)) - (portRef D (instanceRef CBR)) - (portRef D (instanceRef CBR_fast)) - (portRef SCLK (instanceRef WRD_0io_7)) - (portRef SCLK (instanceRef WRD_0io_6)) - (portRef SCLK (instanceRef WRD_0io_5)) - (portRef SCLK (instanceRef WRD_0io_4)) - (portRef SCLK (instanceRef WRD_0io_3)) - (portRef SCLK (instanceRef WRD_0io_2)) - (portRef SCLK (instanceRef WRD_0io_1)) - (portRef SCLK (instanceRef WRD_0io_0)) - )) - (net (rename IS_i_0 "IS_i[0]") (joined - (portRef Z (instanceRef RA10_0io_RNO)) - (portRef D (instanceRef RA10_0io)) - )) - (net RASr2_i (joined - (portRef Z (instanceRef RASr2_RNIAFR1)) - (portRef CD (instanceRef S_1)) - (portRef CD (instanceRef S_0)) - )) - (net InitReady_i (joined - (portRef Z (instanceRef wb_rst_RNO_0)) - (portRef SP (instanceRef wb_rst)) - )) - (net wb_clk_RNO_2 (joined - (portRef Z (instanceRef wb_clk_RNO_2)) - (portRef BLUT (instanceRef wb_clk_RNO)) - )) - (net wb_clk_RNO_1 (joined - (portRef Z (instanceRef wb_clk_RNO_1)) - (portRef ALUT (instanceRef wb_clk_RNO)) - )) - (net N_1 (joined - (portRef CIN (instanceRef FS_cry_0_0)) - )) - ) - (property orig_inst_of (string "RAM2GS")) - ) - ) - ) - (design RAM2GS (cellRef RAM2GS (libraryRef work)) - (property PART (string "lcmxo2_640hc-4") )) -) +(edif RAM2GS + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2023 8 19 21 54 54) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell CCU2D (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A0 (direction INPUT)) + (port B0 (direction INPUT)) + (port C0 (direction INPUT)) + (port D0 (direction INPUT)) + (port A1 (direction INPUT)) + (port B1 (direction INPUT)) + (port C1 (direction INPUT)) + (port D1 (direction INPUT)) + (port CIN (direction INPUT)) + (port COUT (direction OUTPUT)) + (port S0 (direction OUTPUT)) + (port S1 (direction OUTPUT)) + ) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0000")) + (property INIT0 (string "0000")) + ) + ) + (cell BB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port B (direction INOUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell OB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell FD1S3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3JX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3BX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell ORCALUT4 (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell PFUMX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port ALUT (direction INPUT)) + (port BLUT (direction INPUT)) + (port C0 (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell EFB (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port WBCLKI (direction INPUT)) + (port WBRSTI (direction INPUT)) + (port WBCYCI (direction INPUT)) + (port WBSTBI (direction INPUT)) + (port WBWEI (direction INPUT)) + (port WBADRI7 (direction INPUT)) + (port WBADRI6 (direction INPUT)) + (port WBADRI5 (direction INPUT)) + (port WBADRI4 (direction INPUT)) + (port WBADRI3 (direction INPUT)) + (port WBADRI2 (direction INPUT)) + (port WBADRI1 (direction INPUT)) + (port WBADRI0 (direction INPUT)) + (port WBDATI7 (direction INPUT)) + (port WBDATI6 (direction INPUT)) + (port WBDATI5 (direction INPUT)) + (port WBDATI4 (direction INPUT)) + (port WBDATI3 (direction INPUT)) + (port WBDATI2 (direction INPUT)) + (port WBDATI1 (direction INPUT)) + (port WBDATI0 (direction INPUT)) + (port PLL0DATI7 (direction INPUT)) + (port PLL0DATI6 (direction INPUT)) + (port PLL0DATI5 (direction INPUT)) + (port PLL0DATI4 (direction INPUT)) + (port PLL0DATI3 (direction INPUT)) + (port PLL0DATI2 (direction INPUT)) + (port PLL0DATI1 (direction INPUT)) + (port PLL0DATI0 (direction INPUT)) + (port PLL0ACKI (direction INPUT)) + (port PLL1DATI7 (direction INPUT)) + (port PLL1DATI6 (direction INPUT)) + (port PLL1DATI5 (direction INPUT)) + (port PLL1DATI4 (direction INPUT)) + (port PLL1DATI3 (direction INPUT)) + (port PLL1DATI2 (direction INPUT)) + (port PLL1DATI1 (direction INPUT)) + (port PLL1DATI0 (direction INPUT)) + (port PLL1ACKI (direction INPUT)) + (port I2C1SCLI (direction INPUT)) + (port I2C1SDAI (direction INPUT)) + (port I2C2SCLI (direction INPUT)) + (port I2C2SDAI (direction INPUT)) + (port SPISCKI (direction INPUT)) + (port SPIMISOI (direction INPUT)) + (port SPIMOSII (direction INPUT)) + (port SPISCSN (direction INPUT)) + (port TCCLKI (direction INPUT)) + (port TCRSTN (direction INPUT)) + (port TCIC (direction INPUT)) + (port UFMSN (direction INPUT)) + (port WBDATO7 (direction OUTPUT)) + (port WBDATO6 (direction OUTPUT)) + (port WBDATO5 (direction OUTPUT)) + (port WBDATO4 (direction OUTPUT)) + (port WBDATO3 (direction OUTPUT)) + (port WBDATO2 (direction OUTPUT)) + (port WBDATO1 (direction OUTPUT)) + (port WBDATO0 (direction OUTPUT)) + (port WBACKO (direction OUTPUT)) + (port PLLCLKO (direction OUTPUT)) + (port PLLRSTO (direction OUTPUT)) + (port PLL0STBO (direction OUTPUT)) + (port PLL1STBO (direction OUTPUT)) + (port PLLWEO (direction OUTPUT)) + (port PLLADRO4 (direction OUTPUT)) + (port PLLADRO3 (direction OUTPUT)) + (port PLLADRO2 (direction OUTPUT)) + (port PLLADRO1 (direction OUTPUT)) + (port PLLADRO0 (direction OUTPUT)) + (port PLLDATO7 (direction OUTPUT)) + (port PLLDATO6 (direction OUTPUT)) + (port PLLDATO5 (direction OUTPUT)) + (port PLLDATO4 (direction OUTPUT)) + (port PLLDATO3 (direction OUTPUT)) + (port PLLDATO2 (direction OUTPUT)) + (port PLLDATO1 (direction OUTPUT)) + (port PLLDATO0 (direction OUTPUT)) + (port I2C1SCLO (direction OUTPUT)) + (port I2C1SCLOEN (direction OUTPUT)) + (port I2C1SDAO (direction OUTPUT)) + (port I2C1SDAOEN (direction OUTPUT)) + (port I2C2SCLO (direction OUTPUT)) + (port I2C2SCLOEN (direction OUTPUT)) + (port I2C2SDAO (direction OUTPUT)) + (port I2C2SDAOEN (direction OUTPUT)) + (port I2C1IRQO (direction OUTPUT)) + (port I2C2IRQO (direction OUTPUT)) + (port SPISCKO (direction OUTPUT)) + (port SPISCKEN (direction OUTPUT)) + (port SPIMISOO (direction OUTPUT)) + (port SPIMISOEN (direction OUTPUT)) + (port SPIMOSIO (direction OUTPUT)) + (port SPIMOSIEN (direction OUTPUT)) + (port SPIMCSN0 (direction OUTPUT)) + (port SPIMCSN1 (direction OUTPUT)) + (port SPIMCSN2 (direction OUTPUT)) + (port SPIMCSN3 (direction OUTPUT)) + (port SPIMCSN4 (direction OUTPUT)) + (port SPIMCSN5 (direction OUTPUT)) + (port SPIMCSN6 (direction OUTPUT)) + (port SPIMCSN7 (direction OUTPUT)) + (port SPICSNEN (direction OUTPUT)) + (port SPIIRQO (direction OUTPUT)) + (port TCINT (direction OUTPUT)) + (port TCOC (direction OUTPUT)) + (port WBCUFMIRQ (direction OUTPUT)) + (port CFGWAKE (direction OUTPUT)) + (port CFGSTDBY (direction OUTPUT)) + ) + (property TC_ICAPTURE (string "DISABLED")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICR_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_TOP_SEL (string "OFF")) + (property TC_RESETN (string "ENABLED")) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_OCR_SET (integer 32767)) + (property TC_TOP_SET (integer 65535)) + (property GSR (string "ENABLED")) + (property TC_CCLK_SEL (integer 1)) + (property TC_SCLK_SEL (string "PCLOCK")) + (property TC_MODE (string "CTCM")) + (property SPI_WAKEUP (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_MODE (string "MASTER")) + (property I2C2_WAKEUP (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C2_ADDRESSING (string "7BIT")) + (property I2C1_ADDRESSING (string "7BIT")) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + (property UFM_INIT_FILE_NAME (string "../RAM2GS-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_PAGES (integer 1)) + (property DEV_DENSITY (string "640L")) + (property EFB_WB_CLK_FREQ (string "66.7")) + (property EFB_UFM (string "ENABLED")) + (property EFB_TC_PORTMODE (string "WB")) + (property EFB_TC (string "DISABLED")) + (property EFB_SPI (string "DISABLED")) + (property EFB_I2C2 (string "DISABLED")) + (property EFB_I2C1 (string "DISABLED")) + (property orig_inst_of (string "EFB")) + ) + ) + (cell REFB (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT)) + (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) + (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) + (port wb_we (direction INPUT)) + (port wb_cyc_stb (direction INPUT)) + (port wb_rst (direction INPUT)) + (port RCLK_c (direction INPUT)) + (port d_N_5_mux (direction OUTPUT)) + (port wb_ack (direction OUTPUT)) + (port un1_FS_29 (direction INPUT)) + (port un1_FS_11 (direction INPUT)) + (port InitReady (direction INPUT)) + ) + (contents + (instance EFBInst_0_RNI9PBJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance EFBInst_0 (viewRef verilog (cellRef EFB)) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + (property UFM_INIT_FILE_NAME (string "../RAM2GS-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_PAGES (integer 1)) + (property DEV_DENSITY (string "640L")) + (property EFB_UFM (string "ENABLED")) + (property TC_ICAPTURE (string "DISABLED")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICR_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_TOP_SEL (string "OFF")) + (property TC_RESETN (string "ENABLED")) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_OCR_SET (integer 32767)) + (property TC_TOP_SET (integer 65535)) + (property GSR (string "ENABLED")) + (property TC_CCLK_SEL (integer 1)) + (property TC_MODE (string "CTCM")) + (property TC_SCLK_SEL (string "PCLOCK")) + (property EFB_TC_PORTMODE (string "WB")) + (property EFB_TC (string "DISABLED")) + (property SPI_WAKEUP (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_MODE (string "MASTER")) + (property EFB_SPI (string "DISABLED")) + (property I2C2_WAKEUP (string "DISABLED")) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C2_ADDRESSING (string "7BIT")) + (property EFB_I2C2 (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C1_ADDRESSING (string "7BIT")) + (property EFB_I2C1 (string "DISABLED")) + (property EFB_WB_CLK_FREQ (string "66.7")) + ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (net InitReady (joined + (portRef InitReady) + (portRef A (instanceRef EFBInst_0_RNI9PBJ)) + )) + (net un1_FS_11 (joined + (portRef un1_FS_11) + (portRef B (instanceRef EFBInst_0_RNI9PBJ)) + )) + (net un1_FS_29 (joined + (portRef un1_FS_29) + (portRef C (instanceRef EFBInst_0_RNI9PBJ)) + )) + (net wb_ack (joined + (portRef WBACKO (instanceRef EFBInst_0)) + (portRef D (instanceRef EFBInst_0_RNI9PBJ)) + (portRef wb_ack) + )) + (net d_N_5_mux (joined + (portRef Z (instanceRef EFBInst_0_RNI9PBJ)) + (portRef d_N_5_mux) + )) + (net RCLK_c (joined + (portRef RCLK_c) + (portRef WBCLKI (instanceRef EFBInst_0)) + )) + (net wb_rst (joined + (portRef wb_rst) + (portRef WBRSTI (instanceRef EFBInst_0)) + )) + (net wb_cyc_stb (joined + (portRef wb_cyc_stb) + (portRef WBSTBI (instanceRef EFBInst_0)) + (portRef WBCYCI (instanceRef EFBInst_0)) + )) + (net wb_we (joined + (portRef wb_we) + (portRef WBWEI (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef (member wb_adr 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef (member wb_adr 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef (member wb_adr 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef (member wb_adr 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef (member wb_adr 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef (member wb_adr 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef (member wb_adr 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef (member wb_adr 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef (member wb_dati 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef (member wb_dati 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef (member wb_dati 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef (member wb_dati 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef (member wb_dati 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef (member wb_dati 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef (member wb_dati 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef (member wb_dati 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)) + )) + (net GND (joined + (portRef Z (instanceRef GND)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + )) + (net VCC (joined + (portRef Z (instanceRef VCC)) + (portRef UFMSN (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_7 "wb_dat_o_1[7]") (joined + (portRef WBDATO7 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_6 "wb_dat_o_1[6]") (joined + (portRef WBDATO6 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_5 "wb_dat_o_1[5]") (joined + (portRef WBDATO5 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_4 "wb_dat_o_1[4]") (joined + (portRef WBDATO4 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_3 "wb_dat_o_1[3]") (joined + (portRef WBDATO3 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_2 "wb_dat_o_1[2]") (joined + (portRef WBDATO2 (instanceRef EFBInst_0)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef WBDATO1 (instanceRef EFBInst_0)) + (portRef (member wb_dato 0)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef WBDATO0 (instanceRef EFBInst_0)) + (portRef (member wb_dato 1)) + )) + (net PLLCLKO (joined + (portRef PLLCLKO (instanceRef EFBInst_0)) + )) + (net PLLRSTO (joined + (portRef PLLRSTO (instanceRef EFBInst_0)) + )) + (net PLL0STBO (joined + (portRef PLL0STBO (instanceRef EFBInst_0)) + )) + (net PLL1STBO (joined + (portRef PLL1STBO (instanceRef EFBInst_0)) + )) + (net PLLWEO (joined + (portRef PLLWEO (instanceRef EFBInst_0)) + )) + (net PLLADRO4 (joined + (portRef PLLADRO4 (instanceRef EFBInst_0)) + )) + (net PLLADRO3 (joined + (portRef PLLADRO3 (instanceRef EFBInst_0)) + )) + (net PLLADRO2 (joined + (portRef PLLADRO2 (instanceRef EFBInst_0)) + )) + (net PLLADRO1 (joined + (portRef PLLADRO1 (instanceRef EFBInst_0)) + )) + (net PLLADRO0 (joined + (portRef PLLADRO0 (instanceRef EFBInst_0)) + )) + (net PLLDATO7 (joined + (portRef PLLDATO7 (instanceRef EFBInst_0)) + )) + (net PLLDATO6 (joined + (portRef PLLDATO6 (instanceRef EFBInst_0)) + )) + (net PLLDATO5 (joined + (portRef PLLDATO5 (instanceRef EFBInst_0)) + )) + (net PLLDATO4 (joined + (portRef PLLDATO4 (instanceRef EFBInst_0)) + )) + (net PLLDATO3 (joined + (portRef PLLDATO3 (instanceRef EFBInst_0)) + )) + (net PLLDATO2 (joined + (portRef PLLDATO2 (instanceRef EFBInst_0)) + )) + (net PLLDATO1 (joined + (portRef PLLDATO1 (instanceRef EFBInst_0)) + )) + (net PLLDATO0 (joined + (portRef PLLDATO0 (instanceRef EFBInst_0)) + )) + (net I2C1SCLO (joined + (portRef I2C1SCLO (instanceRef EFBInst_0)) + )) + (net I2C1SCLOEN (joined + (portRef I2C1SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C1SDAO (joined + (portRef I2C1SDAO (instanceRef EFBInst_0)) + )) + (net I2C1SDAOEN (joined + (portRef I2C1SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C2SCLO (joined + (portRef I2C2SCLO (instanceRef EFBInst_0)) + )) + (net I2C2SCLOEN (joined + (portRef I2C2SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C2SDAO (joined + (portRef I2C2SDAO (instanceRef EFBInst_0)) + )) + (net I2C2SDAOEN (joined + (portRef I2C2SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C1IRQO (joined + (portRef I2C1IRQO (instanceRef EFBInst_0)) + )) + (net I2C2IRQO (joined + (portRef I2C2IRQO (instanceRef EFBInst_0)) + )) + (net SPISCKO (joined + (portRef SPISCKO (instanceRef EFBInst_0)) + )) + (net SPISCKEN (joined + (portRef SPISCKEN (instanceRef EFBInst_0)) + )) + (net SPIMISOO (joined + (portRef SPIMISOO (instanceRef EFBInst_0)) + )) + (net SPIMISOEN (joined + (portRef SPIMISOEN (instanceRef EFBInst_0)) + )) + (net SPIMOSIO (joined + (portRef SPIMOSIO (instanceRef EFBInst_0)) + )) + (net SPIMOSIEN (joined + (portRef SPIMOSIEN (instanceRef EFBInst_0)) + )) + (net SPIMCSN0 (joined + (portRef SPIMCSN0 (instanceRef EFBInst_0)) + )) + (net SPIMCSN1 (joined + (portRef SPIMCSN1 (instanceRef EFBInst_0)) + )) + (net SPIMCSN2 (joined + (portRef SPIMCSN2 (instanceRef EFBInst_0)) + )) + (net SPIMCSN3 (joined + (portRef SPIMCSN3 (instanceRef EFBInst_0)) + )) + (net SPIMCSN4 (joined + (portRef SPIMCSN4 (instanceRef EFBInst_0)) + )) + (net SPIMCSN5 (joined + (portRef SPIMCSN5 (instanceRef EFBInst_0)) + )) + (net SPIMCSN6 (joined + (portRef SPIMCSN6 (instanceRef EFBInst_0)) + )) + (net SPIMCSN7 (joined + (portRef SPIMCSN7 (instanceRef EFBInst_0)) + )) + (net SPICSNEN (joined + (portRef SPICSNEN (instanceRef EFBInst_0)) + )) + (net SPIIRQO (joined + (portRef SPIIRQO (instanceRef EFBInst_0)) + )) + (net TCINT (joined + (portRef TCINT (instanceRef EFBInst_0)) + )) + (net TCOC (joined + (portRef TCOC (instanceRef EFBInst_0)) + )) + (net wbc_ufm_irq (joined + (portRef WBCUFMIRQ (instanceRef EFBInst_0)) + )) + (net CFGWAKE (joined + (portRef CFGWAKE (instanceRef EFBInst_0)) + )) + (net CFGSTDBY (joined + (portRef CFGSTDBY (instanceRef EFBInst_0)) + )) + ) + (property NGD_DRC_MASK (integer 1)) + (property orig_inst_of (string "REFB")) + ) + ) + (cell RAM2GS (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port PHI2 (direction INPUT)) + (port (array (rename main "MAin[9:0]") 10) (direction INPUT)) + (port (array (rename crow "CROW[1:0]") 2) (direction INPUT)) + (port (array (rename din "Din[7:0]") 8) (direction INPUT)) + (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) + (port nCCAS (direction INPUT)) + (port nCRAS (direction INPUT)) + (port nFWE (direction INPUT)) + (port LED (direction OUTPUT)) + (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT)) + (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) + (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) + (port nRCS (direction OUTPUT)) + (port RCLK (direction INPUT)) + (port RCKE (direction OUTPUT)) + (port nRWE (direction OUTPUT)) + (port nRRAS (direction OUTPUT)) + (port nRCAS (direction OUTPUT)) + (port RDQMH (direction OUTPUT)) + (port RDQML (direction OUTPUT)) + ) + (contents + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nRWE_0io_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_RNO_4 "wb_dati_5_1_iv_0_a3_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance (rename wb_dati_5_1_iv_0_RNO_7 "wb_dati_5_1_iv_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A+B A)))")) + ) + (instance (rename FS_RNI3V8E_9 "FS_RNI3V8E[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) + ) + (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) + ) + (instance CmdUFMData_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (B+A)+C A))")) + ) + (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))")) + ) + (instance XOR8MEG_3_u_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance XOR8MEG_3_u_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (C (B !A)))")) + ) + (instance XOR8MEG_3_u_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "A")) + ) + (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(B+!A)))")) + ) + (instance wb_cyc_stb_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+A))")) + ) + (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA11_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance wb_we (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance wb_rst (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance wb_req (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdValid_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CmdValid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CmdUFMWrite (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMShift_fast (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMShift (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMData (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename wb_adr_5_0 "wb_adr_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (B+A))")) + ) + (instance (rename wb_dati_5_1_iv_0_4 "wb_dati_5_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (B !A)+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_6 "wb_dati_5_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_5 "wb_dati_5_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_2 "wb_dati_5_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_1 "wb_dati_5_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (C+(B+A)))")) + ) + (instance (rename wb_adr_5_1 "wb_adr_5[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C (!B !A)+C (!B+A)))")) + ) + (instance wb_we_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(B A))+D (B A))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_6 "wb_dati_5_1_iv_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_3 "wb_dati_5_1_iv_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) + ) + (instance CmdValid_fast_RNITQBM1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (!C (B A)+C (!B+A)))")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance (rename wb_dati_5_0_iv_0_0 "wb_dati_5_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + ) + (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_wb_cyc_stb_1_sqmuxa_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C B+C (B+A)))")) + ) + (instance Cmdn8MEGEN_4_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A)+C (B+A))")) + ) + (instance CmdLEDEN_4_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename wb_dati_5_1_iv_0_RNO_4 "wb_dati_5_1_iv_0_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance RA10_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance CmdEnable16 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance CmdEnable17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (!B A)+C !B))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_7 "wb_dati_5_1_iv_0_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_4 "wb_dati_5_1_iv_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (B+A))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance CmdUFMWrite_3_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C B))")) + ) + (instance CmdUFMShift_3_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C !B))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) + ) + (instance un1_wb_we95_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A+B !A))+D (C (B A)))")) + ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_6 "wb_dati_5_1_iv_0_a3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_4 "wb_dati_5_1_iv_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_1_7 "wb_dati_5_1_iv_0_a3_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_2 "wb_dati_5_1_iv_0_a3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B+A)))")) + ) + (instance (rename wb_adr_cnst_sn_m4_32 "wb_adr_cnst_sn.m4_32") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance un1_FS_40_1_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B A+B !A)))")) + ) + (instance un1_wb_adr_0_sqmuxa_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_adr_5_6 "wb_adr_5[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (B+!A))")) + ) + (instance (rename wb_adr_5_5 "wb_adr_5[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (B+!A))")) + ) + (instance (rename wb_adr_5_4 "wb_adr_5[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (B+!A))")) + ) + (instance Cmdn8MEGEN_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C !B)")) + ) + (instance CmdLEDEN_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C B)")) + ) + (instance PHI2r3_RNIS5A51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_0_4 "wb_dati_5_1_iv_0_a2_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance (rename wb_dati_5_1_iv_0_o3_1 "wb_dati_5_1_iv_0_o3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))")) + ) + (instance un1_FS_40_1_a6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_4 "wb_dati_5_1_iv_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance wb_we95 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D (C (B A)))")) + ) + (instance nRCAS_r_i_a3_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (C (!B A)))")) + ) + (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_wb_cyc_stb_2_sqmuxa_i_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance C1WR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_3_7 "wb_dati_5_1_iv_0_a3_3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance ADWR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_2_0_1 "wb_dati_5_1_iv_0_a3_2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) + ) + (instance C1WR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_0_0_3 "wb_dati_5_1_iv_0_a3_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A))+D (C (B A)))")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance wb_we113_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D (!B+A))")) + ) + (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B A)))")) + ) + (instance un1_FS_40_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C (B !A))+D (C (B !A)))")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+A))")) + ) + (instance un1_Bank_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_wb_cyc_stb_2_sqmuxa_i_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance un1_FS_29 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance XOR8MEG11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance XOR8MEG14 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance un1_Din_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance un1_FS_40_1_o6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (!B !A)+C (!B+A)))")) + ) + (instance InitReady3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_wb_cyc_stb_1_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename wb_dati_5_0_iv_0_a3_1_0 "wb_dati_5_0_iv_0_a3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)+C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_0_0_0_1 "wb_dati_5_1_iv_0_a3_0_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_m3_7 "wb_dati_5_1_iv_0_m3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C (B+!A))")) + ) + (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) + ) + (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance (rename FS_RNIVOOA_14 "FS_RNIVOOA[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_7 "wb_dati_5_1_iv_0_a2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance C1Submitted_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B A))")) + ) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance C1WR_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_1_1_4 "wb_dati_5_1_iv_0_a3_1_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance un1_wb_cyc_stb_2_sqmuxa_i_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance un1_FS_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance wb_rst10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance un1_Bank_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance InitReady3_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_3_0_7 "wb_dati_5_1_iv_0_a3_3_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance ADWR_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) + ) + (instance ADWR_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_0_0_6 "wb_dati_5_1_iv_0_a3_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A)+C (B A))")) + ) + (instance CmdEnable17_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance CmdEnable17_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance CmdEnable16_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance CmdEnable16_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance LEDEN_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_3 "wb_adr_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance wb_we113_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance XOR8MEG9_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance un1_wb_cyc_stb_2_sqmuxa_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance CmdUFMWrite_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance un1_FS_21_1_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance un1_FS_22_1_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance RA10_2_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance un1_PHI2r3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance wb_we95_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance XOR8MEG14_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance un1_Bank_1_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename wb_adr_cnst_0_0 "wb_adr_cnst_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A+B A))")) + ) + (instance un1_ADWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B+A))")) + ) + (instance un1_wb_adr_0_sqmuxa_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+A))")) + ) + (instance un1_FS_40_1_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)+C (!B A))+D (!C A+C (!B A)))")) + ) + (instance un1_FS_40_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A))+D (!B !A))")) + ) + (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) + ) + (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) + ) + (instance wb_rste (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (!C (B !A)+C (!B+!A)))")) + ) + (instance wb_reqe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !A)+D (!C (!B A)+C (!B+!A)))")) + ) + (instance CmdUFMShift_fast_RNIG9JD1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(C (B A)))")) + ) + (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance CmdUFMShift_3_u_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C !B))")) + ) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(!B !A)))")) + ) + (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A)+C !A)")) + ) + (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance nRWE_0io_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+A))")) + ) + (instance nRWE_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (!C A+C !B))")) + ) + (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C !B+C (!B !A)))")) + ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C (!B !A))")) + ) + (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))")) + ) + (instance (rename wb_adr_cnst_sn_m2_0_a3 "wb_adr_cnst_sn.m2_0_a3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_dati_5_1_iv_0_o3_2 "wb_dati_5_1_iv_0_o3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C (B+A))")) + ) + (instance nRRAS_5_u_i_0_RNILD5I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a3_1 "wb_dati_5_1_iv_0_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_0_3 "wb_dati_5_1_iv_0_a2_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A))")) + ) + (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)+C B)+D B)")) + ) + (instance (rename wb_dati_5_1_iv_0_3 "wb_dati_5_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (B+A)))")) + ) + (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x5002")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_15 "FS_cry_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance ufmefb (viewRef netlist (cellRef REFB)) + ) + (net un1_wb_cyc_stb_1_sqmuxa_0 (joined + (portRef Z (instanceRef un1_wb_cyc_stb_1_sqmuxa_0)) + (portRef D (instanceRef wb_cyc_stb)) + )) + (net un1_ADWR (joined + (portRef Z (instanceRef un1_ADWR)) + (portRef B (instanceRef C1Submitted_s)) + (portRef B (instanceRef ADSubmitted_r)) + )) + (net wb_rst (joined + (portRef Q (instanceRef wb_rst)) + (portRef wb_rst (instanceRef ufmefb)) + (portRef C (instanceRef wb_rste)) + )) + (net wb_cyc_stb (joined + (portRef Q (instanceRef wb_cyc_stb)) + (portRef wb_cyc_stb (instanceRef ufmefb)) + )) + (net wb_we (joined + (portRef Q (instanceRef wb_we)) + (portRef wb_we (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_0_iv_0_0)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef Q (instanceRef wb_adr_0)) + (portRef (member wb_adr 7) (instanceRef ufmefb)) + (portRef C (instanceRef wb_adr_5_1)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef Q (instanceRef wb_adr_1)) + (portRef (member wb_adr 6) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_2)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef Q (instanceRef wb_adr_2)) + (portRef (member wb_adr 5) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_3)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef Q (instanceRef wb_adr_3)) + (portRef (member wb_adr 4) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_4)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef Q (instanceRef wb_adr_4)) + (portRef (member wb_adr 3) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_5)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef Q (instanceRef wb_adr_5)) + (portRef (member wb_adr 2) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_6)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef Q (instanceRef wb_adr_6)) + (portRef (member wb_adr 1) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_7)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef Q (instanceRef wb_adr_7)) + (portRef (member wb_adr 0) (instanceRef ufmefb)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef Q (instanceRef wb_dati_0)) + (portRef (member wb_dati 7) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_1)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef Q (instanceRef wb_dati_1)) + (portRef (member wb_dati 6) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_0_2)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef Q (instanceRef wb_dati_2)) + (portRef (member wb_dati 5) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_3)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef Q (instanceRef wb_dati_3)) + (portRef (member wb_dati 4) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_0_4)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef Q (instanceRef wb_dati_4)) + (portRef (member wb_dati 3) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_0_5)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef Q (instanceRef wb_dati_5)) + (portRef (member wb_dati 2) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_6)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef Q (instanceRef wb_dati_6)) + (portRef (member wb_dati 1) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_7)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef Q (instanceRef wb_dati_7)) + (portRef (member wb_dati 0) (instanceRef ufmefb)) + (portRef C (instanceRef wb_adr_5_0)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef (member wb_dato 1) (instanceRef ufmefb)) + (portRef C (instanceRef n8MEGEN_6)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef (member wb_dato 0) (instanceRef ufmefb)) + (portRef C (instanceRef LEDEN_6)) + )) + (net wb_ack (joined + (portRef wb_ack (instanceRef ufmefb)) + (portRef A (instanceRef wb_cyc_stb_RNO_1)) + )) + (net CBR (joined + (portRef Q (instanceRef CBR)) + (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u)) + (portRef B (instanceRef nRowColSel_0_0_a3_0)) + (portRef A (instanceRef LED_pad_RNO)) + )) + (net InitReady (joined + (portRef Q (instanceRef InitReady)) + (portRef InitReady (instanceRef ufmefb)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef A (instanceRef wb_adr_cnst_sn_m2_0_a3)) + (portRef D (instanceRef CmdUFMShift_fast_RNIG9JD1)) + (portRef A (instanceRef wb_adr_5_7)) + (portRef A (instanceRef wb_adr_5_3)) + (portRef A (instanceRef wb_adr_5_2)) + (portRef B (instanceRef n8MEGEN_6)) + (portRef B (instanceRef LEDEN_6)) + (portRef D (instanceRef wb_rst10)) + (portRef C (instanceRef un1_wb_cyc_stb_1_sqmuxa_0_a3)) + (portRef A (instanceRef un1_wb_cyc_stb_2_sqmuxa_i_a3)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef B (instanceRef PHI2r3_RNIS5A51)) + (portRef A (instanceRef wb_adr_5_4)) + (portRef A (instanceRef wb_adr_5_5)) + (portRef A (instanceRef wb_adr_5_6)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef A (instanceRef wb_dati_5_0_iv_0_0)) + (portRef B (instanceRef CmdValid_fast_RNITQBM1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_6)) + (portRef B (instanceRef wb_we_0)) + (portRef A (instanceRef wb_adr_5_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_5)) + (portRef A (instanceRef wb_dati_5_1_iv_0_4)) + (portRef A (instanceRef wb_adr_5_0)) + (portRef B (instanceRef InitReady_RNO)) + (portRef C0 (instanceRef wb_cyc_stb_RNO)) + (portRef D (instanceRef Ready_RNO)) + (portRef C (instanceRef RCKEEN_8_u_RNO)) + )) + (net C1Submitted (joined + (portRef Q (instanceRef C1Submitted)) + (portRef A (instanceRef C1Submitted_s)) + (portRef D (instanceRef CmdEnable_s_am)) + )) + (net (rename Bank_2 "Bank[2]") (joined + (portRef Q (instanceRef Bank_0io_2)) + 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(net LED (joined + (portRef O (instanceRef LED_pad)) + (portRef LED) + )) + (net (rename RBA_c_0 "RBA_c[0]") (joined + (portRef Q (instanceRef RBA_0io_0)) + (portRef I (instanceRef RBA_pad_0)) + )) + (net (rename RBA_0 "RBA[0]") (joined + (portRef O (instanceRef RBA_pad_0)) + (portRef (member rba 1)) + )) + (net (rename RBA_c_1 "RBA_c[1]") (joined + (portRef Q (instanceRef RBA_0io_1)) + (portRef I (instanceRef RBA_pad_1)) + )) + (net (rename RBA_1 "RBA[1]") (joined + (portRef O (instanceRef RBA_pad_1)) + (portRef (member rba 0)) + )) + (net (rename RA_c_0 "RA_c[0]") (joined + (portRef Z (instanceRef un9_RA_0)) + (portRef I (instanceRef RA_pad_0)) + )) + (net (rename RA_0 "RA[0]") (joined + (portRef O (instanceRef RA_pad_0)) + (portRef (member ra 11)) + )) + (net (rename RA_c_1 "RA_c[1]") (joined + (portRef Z (instanceRef un9_RA_1)) + (portRef I (instanceRef RA_pad_1)) + )) + (net (rename RA_1 "RA[1]") (joined + (portRef O (instanceRef RA_pad_1)) + (portRef (member ra 10)) + )) + (net (rename RA_c_2 "RA_c[2]") (joined + (portRef Z (instanceRef un9_RA_2)) + (portRef I (instanceRef RA_pad_2)) + )) + (net (rename RA_2 "RA[2]") (joined + (portRef O (instanceRef RA_pad_2)) + (portRef (member ra 9)) + )) + (net (rename RA_c_3 "RA_c[3]") (joined + (portRef Z (instanceRef un9_RA_3)) + (portRef I (instanceRef RA_pad_3)) + )) + (net (rename RA_3 "RA[3]") (joined + (portRef O (instanceRef RA_pad_3)) + (portRef (member ra 8)) + )) + (net (rename RA_c_4 "RA_c[4]") (joined + (portRef Z (instanceRef un9_RA_4)) + (portRef I (instanceRef RA_pad_4)) + )) + (net (rename RA_4 "RA[4]") (joined + (portRef O (instanceRef RA_pad_4)) + (portRef (member ra 7)) + )) + (net (rename RA_c_5 "RA_c[5]") (joined + (portRef Z (instanceRef un9_RA_5)) + (portRef I (instanceRef RA_pad_5)) + )) + (net (rename RA_5 "RA[5]") (joined + (portRef O (instanceRef RA_pad_5)) + (portRef (member ra 6)) + )) + (net (rename RA_c_6 "RA_c[6]") (joined + (portRef Z (instanceRef un9_RA_6)) + (portRef I (instanceRef RA_pad_6)) + )) + (net (rename RA_6 "RA[6]") (joined + (portRef O (instanceRef RA_pad_6)) + (portRef (member ra 5)) + )) + (net (rename RA_c_7 "RA_c[7]") (joined + (portRef Z (instanceRef un9_RA_7)) + (portRef I (instanceRef RA_pad_7)) + )) + (net (rename RA_7 "RA[7]") (joined + (portRef O (instanceRef RA_pad_7)) + (portRef (member ra 4)) + )) + (net (rename RA_c_8 "RA_c[8]") (joined + (portRef Z (instanceRef un9_RA_8)) + (portRef I (instanceRef RA_pad_8)) + )) + (net (rename RA_8 "RA[8]") (joined + (portRef O (instanceRef RA_pad_8)) + (portRef (member ra 3)) + )) + (net (rename RA_c_9 "RA_c[9]") (joined + (portRef Z (instanceRef un9_RA_9)) + (portRef I (instanceRef RA_pad_9)) + )) + (net (rename RA_9 "RA[9]") (joined + (portRef O (instanceRef RA_pad_9)) + (portRef (member ra 2)) + )) + (net (rename RA_c_10 "RA_c[10]") (joined + (portRef Q (instanceRef RA10_0io)) + (portRef I (instanceRef RA_pad_10)) + )) + (net (rename RA_10 "RA[10]") (joined + (portRef O (instanceRef RA_pad_10)) + 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(portRef O (instanceRef RDQML_pad)) + (portRef RDQML) + )) + (net N_487_0 (joined + (portRef Z (instanceRef InitReady_RNO)) + (portRef D (instanceRef InitReady)) + )) + (net N_486_0 (joined + (portRef Z (instanceRef Ready_RNO)) + (portRef D (instanceRef Ready)) + )) + (net N_489_0 (joined + (portRef Z (instanceRef Ready_fast_RNO)) + (portRef D (instanceRef Ready_fast)) + )) + (net nFWE_c_i (joined + (portRef Z (instanceRef nFWE_pad_RNI420B)) + (portRef D (instanceRef FWEr)) + (portRef D (instanceRef FWEr_fast)) + )) + (net nCRAS_c_i_0 (joined + (portRef Z (instanceRef RASr_RNO)) + (portRef D (instanceRef RASr)) + )) + (net nCCAS_c_i (joined + (portRef Z (instanceRef nCCAS_pad_RNISUR8)) + (portRef D (instanceRef CASr)) + (portRef D (instanceRef CBR)) + (portRef D (instanceRef CBR_fast)) + (portRef SCLK (instanceRef WRD_0io_7)) + (portRef SCLK (instanceRef WRD_0io_6)) + (portRef SCLK (instanceRef WRD_0io_5)) + (portRef SCLK (instanceRef WRD_0io_4)) + (portRef SCLK (instanceRef WRD_0io_3)) + (portRef SCLK (instanceRef WRD_0io_2)) + (portRef SCLK (instanceRef WRD_0io_1)) + (portRef SCLK (instanceRef WRD_0io_0)) + )) + (net RASr2_i (joined + (portRef Z (instanceRef RASr2_RNIAFR1)) + (portRef CD (instanceRef S_1)) + (portRef CD (instanceRef S_0)) + )) + (net wb_cyc_stb_RNO_1 (joined + (portRef Z (instanceRef wb_cyc_stb_RNO_1)) + (portRef BLUT (instanceRef wb_cyc_stb_RNO)) + )) + (net wb_cyc_stb_RNO_0 (joined + (portRef Z (instanceRef wb_cyc_stb_RNO_0)) + (portRef ALUT (instanceRef wb_cyc_stb_RNO)) + )) + (net XOR8MEG_3_u_0_am (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_am)) + (portRef BLUT (instanceRef XOR8MEG_3_u_0)) + )) + (net XOR8MEG_3_u_0_bm (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_bm)) + (portRef ALUT (instanceRef XOR8MEG_3_u_0)) + )) + (net CmdEnable_s_am (joined + (portRef Z (instanceRef CmdEnable_s_am)) + (portRef BLUT (instanceRef CmdEnable_s)) + )) + (net CmdEnable_s_bm (joined + (portRef Z (instanceRef CmdEnable_s_bm)) + (portRef ALUT (instanceRef CmdEnable_s)) + )) + (net N_1 (joined + (portRef CIN (instanceRef FS_cry_0_0)) + )) + ) + (property orig_inst_of (string "RAM2GS")) + ) + ) + ) + (design RAM2GS (cellRef RAM2GS (libraryRef work)) + (property PART (string "lcmxo2_640hc-4") )) +) diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm index c6b7d36..b1545de 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm @@ -1,9 +1,9 @@ - - - syntmp/LCMXO2_640HC_impl1_srr.htm log file - - - - - - + + + syntmp/LCMXO2_640HC_impl1_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed index 5236a9c..fb7c955 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed @@ -1,1434 +1,1434 @@ -* -NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* -NOTE Copyright (C), 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+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +CE650* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +FC87 diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log index d0353b8..9ce5b3b 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log @@ -1,4 +1,4 @@ ----- MParTrce Tool Log File ---- - -==== Par Standard Out ==== -==== End of Par Standard Out ==== +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp index f3b47ce..57720b6 100644 --- a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp +++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp @@ -1,468 +1,468 @@ - - Lattice Mapping Report File for Design Module 'RAM2GS' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr - LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document - s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf - -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui - -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -Target Vendor: LATTICE -Target Device: LCMXO2-640HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 08/16/23 20:59:36 - -Design Summary --------------- - - Number of registers: 109 out of 877 (12%) - PFU registers: 84 out of 640 (13%) - PIO registers: 25 out of 237 (11%) - Number of SLICEs: 117 out of 320 (37%) - SLICEs as Logic/ROM: 117 out of 320 (37%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 230 out of 640 (36%) - Number used as logic LUTs: 210 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 5 - Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) - Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk ) - Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 7 - Net N_245_i: 1 loads, 1 LSLICEs - Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs - - Page 1 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -Design Summary (cont) ---------------------- - Net InitReady: 1 loads, 1 LSLICEs - Net un1_wb_clk32_i: 10 loads, 10 LSLICEs - Net N_18: 2 loads, 2 LSLICEs - Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_193_i: 2 loads, 2 LSLICEs - Number of LSRs: 5 - Net RA10s_i: 1 loads, 0 LSLICEs - Net wb_clk23: 3 loads, 3 LSLICEs - Net wb_rst: 1 loads, 0 LSLICEs - Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 42 loads - Net FS[12]: 27 loads - Net FS[10]: 25 loads - Net FS[11]: 22 loads - Net FS[7]: 17 loads - Net FS[6]: 16 loads - Net Ready: 15 loads - Net Ready_fast: 14 loads - Net nRowColSel: 12 loads - Net S[1]: 12 loads - - - - - Number of warnings: 1 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - -WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will - temporarily disable certain features of the device including Power - Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. - Functionality is restored after the Flash Memory (UFM/Configuration) - Interface is disabled using Disable Configuration Interface command 0x26 - followed by Bypass command 0xFF. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ - - Page 2 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -IO (PIO) Attributes (cont) --------------------------- -| RDQMH | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[3] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RA[0] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ - - Page 3 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -IO (PIO) Attributes (cont) --------------------------- -| LED | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[3] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ - - Page 4 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -IO (PIO) Attributes (cont) --------------------------- -| MAin[2] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block GSR_INST undriven or does not drive anything - clipped. -Signal nCRAS_c_i was merged into signal nCRAS_c -Signal RASr2_i was merged into signal RASr2 -Signal InitReady_i was merged into signal InitReady -Signal XOR8MEG.CN was merged into signal PHI2_c -Signal GND undriven or does not drive anything - clipped. -Signal ufmefb/VCC undriven or does not drive anything - clipped. -Signal ufmefb/GND undriven or does not drive anything - clipped. -Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. -Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. -Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped. -Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped. -Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped. -Signal ufmefb/TCOC undriven or does not drive anything - clipped. -Signal ufmefb/TCINT undriven or does not drive anything - clipped. -Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped. -Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. -Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. -Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped. -Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped. -Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped. -Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped. -Signal ufmefb/SPISCKO undriven or does not drive anything - clipped. -Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped. -Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. -Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. -Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. -Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. -Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. -Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. -Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. -Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. -Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. - - Page 5 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -Removed logic (cont) --------------------- -Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. -Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. -Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. -Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. -Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. -Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. -Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped. -Signal ufmefb/PLLWEO undriven or does not drive anything - clipped. -Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. -Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. -Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. -Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. -Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped. -Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped. -Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. -Signal N_1 undriven or does not drive anything - clipped. -Block nCRAS_pad_RNIBPVB was optimized away. -Block RASr2_RNIAFR1 was optimized away. -Block wb_rst_RNO_0 was optimized away. -Block XOR8MEG.CN was optimized away. -Block GND was optimized away. -Block ufmefb/VCC was optimized away. -Block ufmefb/GND was optimized away. - - - -Embedded Functional Block Connection Summary --------------------------------------------- - - Desired WISHBONE clock frequency: 62.5 MHz - Clock source: wb_clk - Reset source: wb_rst - Functions mode: - I2C #1 (Primary) Function: DISABLED - I2C #2 (Secondary) Function: DISABLED - SPI Function: DISABLED - Timer/Counter Function: DISABLED - Timer/Counter Mode: WB - UFM Connection: ENABLED - PLL0 Connection: DISABLED - PLL1 Connection: DISABLED - I2C Function Summary: - -------------------- - None - SPI Function Summary: - -------------------- - None - Timer/Counter Function Summary: - ------------------------------ - None - - Page 6 - - - - -Design: RAM2GS Date: 08/16/23 20:59:36 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - UFM Function Summary: - -------------------- - UFM Utilization: General Purpose Flash Memory - Initialized UFM Pages: 1 Pages (1*128 Bits) - Available General - Purpose Flash Memory: 191 Pages (191*128 Bits) - - EBR Blocks with Unique - Initialization Data: 0 - - WID EBR Instance - --- ------------ - - -ASIC Components ---------------- - -Instance Name: ufmefb/EFBInst_0 - Type: EFB - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 37 MB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 7 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights - reserved. + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial + LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr + LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf + Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf + -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset + Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-640HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/19/23 21:54:57 + +Design Summary +-------------- + + Number of registers: 111 out of 877 (13%) + PFU registers: 86 out of 640 (13%) + PIO registers: 25 out of 237 (11%) + Number of SLICEs: 113 out of 320 (35%) + SLICEs as Logic/ROM: 113 out of 320 (35%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 222 out of 640 (35%) + Number used as logic LUTs: 202 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : Yes + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 ) + Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 6 + Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs + Net XOR8MEG18: 6 loads, 6 LSLICEs + Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +Design Summary (cont) +--------------------- + Net un1_wb_rst14_i: 9 loads, 9 LSLICEs + Net un1_FS_38_i: 2 loads, 2 LSLICEs + Net N_253_i: 2 loads, 2 LSLICEs + Number of LSRs: 5 + Net RA10s_i: 1 loads, 0 LSLICEs + Net wb_rst10: 3 loads, 3 LSLICEs + Net wb_rst: 1 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 2 loads, 2 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net InitReady: 33 loads + Net FS[13]: 22 loads + Net FS[12]: 21 loads + Net FS[14]: 20 loads + Net wb_rst11: 18 loads + Net FS[10]: 16 loads + Net Ready: 16 loads + Net FS[11]: 15 loads + Net FS[9]: 15 loads + Net Ready_fast: 14 loads + + + + + Number of warnings: 1 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + +WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will + temporarily disable certain features of the device including Power + Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. + Functionality is restored after the Flash Memory (UFM/Configuration) + Interface is disabled using Disable Configuration Interface command 0x26 + followed by Bypass command 0xFF. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + + Page 2 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +IO (PIO) Attributes (cont) +-------------------------- +| nRCAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RCLK | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[5] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +IO (PIO) Attributes (cont) +-------------------------- +| nFWE | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[6] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[3] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +IO (PIO) Attributes (cont) +-------------------------- +| MAin[1] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_c_i was merged into signal nCRAS_c +Signal RASr2_i was merged into signal RASr2 +Signal XOR8MEG.CN was merged into signal PHI2_c +Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG +Signal GND undriven or does not drive anything - clipped. +Signal ufmefb/VCC undriven or does not drive anything - clipped. +Signal ufmefb/GND undriven or does not drive anything - clipped. +Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. +Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. +Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped. +Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped. +Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped. +Signal ufmefb/TCOC undriven or does not drive anything - clipped. +Signal ufmefb/TCINT undriven or does not drive anything - clipped. +Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped. +Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. + + Page 5 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +Removed logic (cont) +-------------------- +Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped. +Signal ufmefb/PLLWEO undriven or does not drive anything - clipped. +Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. +Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. +Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. +Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped. +Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. +Signal N_1 undriven or does not drive anything - clipped. +Block nCRAS_pad_RNIBPVB was optimized away. +Block RASr2_RNIAFR1 was optimized away. +Block XOR8MEG.CN was optimized away. +Block XOR8MEG_3_u_0_am was optimized away. +Block GND was optimized away. +Block ufmefb/VCC was optimized away. +Block ufmefb/GND was optimized away. + + + +Embedded Functional Block Connection Summary +-------------------------------------------- + + Desired WISHBONE clock frequency: 66.7 MHz + Clock source: RCLK_c + Reset source: wb_rst + Functions mode: + I2C #1 (Primary) Function: DISABLED + I2C #2 (Secondary) Function: DISABLED + SPI Function: DISABLED + Timer/Counter Function: DISABLED + Timer/Counter Mode: WB + UFM Connection: ENABLED + PLL0 Connection: DISABLED + PLL1 Connection: DISABLED + I2C Function Summary: + -------------------- + None + SPI Function Summary: + -------------------- + None + Timer/Counter Function Summary: + ------------------------------ + None + UFM Function Summary: + -------------------- + UFM Utilization: General Purpose Flash Memory + + Page 6 + + + + +Design: RAM2GS Date: 08/19/23 21:54:57 + +Embedded Functional Block Connection Summary (cont) +--------------------------------------------------- + Initialized UFM Pages: 1 Pages (1*128 Bits) + Available General + Purpose Flash Memory: 191 Pages (191*128 Bits) + + EBR Blocks with Unique + Initialization Data: 0 + + WID EBR Instance + --- ------------ + + +ASIC Components +--------------- + +Instance Name: ufmefb/EFBInst_0 + Type: EFB + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 57 MB + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 7 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. 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